1 //===-- HexagonSplitTFRCondSets.cpp - split TFR condsets into xfers -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
9 //===----------------------------------------------------------------------===//
10 // This pass tries to provide opportunities for better optimization of muxes.
11 // The default code generated for something like: flag = (a == b) ? 1 : 3;
14 // {p0 = cmp.eq(r0,r1)}
15 // {r3 = mux(p0,#1,#3)}
17 // This requires two packets. If we use .new predicated immediate transfers,
18 // then we can do this in a single packet, e.g.:
20 // {p0 = cmp.eq(r0,r1)
21 // if (p0.new) r3 = #1
22 // if (!p0.new) r3 = #3}
24 // Note that the conditional assignments are not generated in .new form here.
25 // We assume opptimisically that they will be formed later.
27 //===----------------------------------------------------------------------===//
30 #include "HexagonMachineFunctionInfo.h"
31 #include "HexagonSubtarget.h"
32 #include "HexagonTargetMachine.h"
33 #include "llvm/CodeGen/LatencyPriorityQueue.h"
34 #include "llvm/CodeGen/MachineDominators.h"
35 #include "llvm/CodeGen/MachineFunctionPass.h"
36 #include "llvm/CodeGen/MachineInstrBuilder.h"
37 #include "llvm/CodeGen/MachineLoopInfo.h"
38 #include "llvm/CodeGen/MachineRegisterInfo.h"
39 #include "llvm/CodeGen/Passes.h"
40 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
41 #include "llvm/CodeGen/SchedulerRegistry.h"
42 #include "llvm/Support/Compiler.h"
43 #include "llvm/Support/Debug.h"
44 #include "llvm/Support/MathExtras.h"
45 #include "llvm/Target/TargetInstrInfo.h"
46 #include "llvm/Target/TargetMachine.h"
47 #include "llvm/Target/TargetRegisterInfo.h"
51 #define DEBUG_TYPE "xfer"
54 void initializeHexagonSplitTFRCondSetsPass(PassRegistry&);
60 class HexagonSplitTFRCondSets : public MachineFunctionPass {
61 const HexagonTargetMachine &QTM;
62 const HexagonSubtarget &QST;
66 HexagonSplitTFRCondSets(const HexagonTargetMachine& TM) :
67 MachineFunctionPass(ID), QTM(TM), QST(*TM.getSubtargetImpl()) {
68 initializeHexagonSplitTFRCondSetsPass(*PassRegistry::getPassRegistry());
71 const char *getPassName() const override {
72 return "Hexagon Split TFRCondSets";
74 bool runOnMachineFunction(MachineFunction &Fn) override;
78 char HexagonSplitTFRCondSets::ID = 0;
81 bool HexagonSplitTFRCondSets::runOnMachineFunction(MachineFunction &Fn) {
83 const TargetInstrInfo *TII = QTM.getSubtargetImpl()->getInstrInfo();
85 // Loop over all of the basic blocks.
86 for (MachineFunction::iterator MBBb = Fn.begin(), MBBe = Fn.end();
87 MBBb != MBBe; ++MBBb) {
88 MachineBasicBlock* MBB = MBBb;
89 // Traverse the basic block.
90 for (MachineBasicBlock::iterator MII = MBB->begin(); MII != MBB->end();
92 MachineInstr *MI = MII;
93 switch(MI->getOpcode()) {
94 case Hexagon::TFR_condset_ri: {
95 int DestReg = MI->getOperand(0).getReg();
96 int SrcReg1 = MI->getOperand(2).getReg();
98 // Do not emit the predicated copy if the source and the destination
99 // is the same register.
100 if (DestReg != SrcReg1) {
101 BuildMI(*MBB, MII, MI->getDebugLoc(),
102 TII->get(Hexagon::A2_tfrt), DestReg).
103 addReg(MI->getOperand(1).getReg()).addReg(SrcReg1);
105 BuildMI(*MBB, MII, MI->getDebugLoc(),
106 TII->get(Hexagon::C2_cmoveif), DestReg).
107 addReg(MI->getOperand(1).getReg()).
108 addImm(MI->getOperand(3).getImm());
110 MII = MBB->erase(MI);
114 case Hexagon::TFR_condset_ir: {
115 int DestReg = MI->getOperand(0).getReg();
116 int SrcReg2 = MI->getOperand(3).getReg();
118 BuildMI(*MBB, MII, MI->getDebugLoc(),
119 TII->get(Hexagon::C2_cmoveit), DestReg).
120 addReg(MI->getOperand(1).getReg()).
121 addImm(MI->getOperand(2).getImm());
123 // Do not emit the predicated copy if the source and
124 // the destination is the same register.
125 if (DestReg != SrcReg2) {
126 BuildMI(*MBB, MII, MI->getDebugLoc(),
127 TII->get(Hexagon::A2_tfrf), DestReg).
128 addReg(MI->getOperand(1).getReg()).addReg(SrcReg2);
130 MII = MBB->erase(MI);
134 case Hexagon::TFR_condset_ii: {
135 int DestReg = MI->getOperand(0).getReg();
136 int SrcReg1 = MI->getOperand(1).getReg();
138 int Immed1 = MI->getOperand(2).getImm();
139 int Immed2 = MI->getOperand(3).getImm();
140 BuildMI(*MBB, MII, MI->getDebugLoc(),
141 TII->get(Hexagon::C2_cmoveit),
142 DestReg).addReg(SrcReg1).addImm(Immed1);
143 BuildMI(*MBB, MII, MI->getDebugLoc(),
144 TII->get(Hexagon::C2_cmoveif),
145 DestReg).addReg(SrcReg1).addImm(Immed2);
146 MII = MBB->erase(MI);
158 //===----------------------------------------------------------------------===//
159 // Public Constructor Functions
160 //===----------------------------------------------------------------------===//
162 static void initializePassOnce(PassRegistry &Registry) {
163 const char *Name = "Hexagon Split TFRCondSets";
164 PassInfo *PI = new PassInfo(Name, "hexagon-split-tfr",
165 &HexagonSplitTFRCondSets::ID, nullptr, false,
167 Registry.registerPass(*PI, true);
170 void llvm::initializeHexagonSplitTFRCondSetsPass(PassRegistry &Registry) {
171 CALL_ONCE_INITIALIZATION(initializePassOnce)
175 llvm::createHexagonSplitTFRCondSets(const HexagonTargetMachine &TM) {
176 return new HexagonSplitTFRCondSets(TM);