1 //===-- HexagonRegisterInfo.cpp - Hexagon Register Information ------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Hexagon implementation of the TargetRegisterInfo
13 //===----------------------------------------------------------------------===//
15 #include "HexagonRegisterInfo.h"
17 #include "HexagonMachineFunctionInfo.h"
18 #include "HexagonSubtarget.h"
19 #include "HexagonTargetMachine.h"
20 #include "llvm/ADT/BitVector.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineFunctionPass.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/CodeGen/PseudoSourceValue.h"
28 #include "llvm/CodeGen/RegisterScavenging.h"
29 #include "llvm/IR/Function.h"
30 #include "llvm/IR/Type.h"
31 #include "llvm/MC/MachineLocation.h"
32 #include "llvm/Support/CommandLine.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Target/TargetInstrInfo.h"
35 #include "llvm/Target/TargetMachine.h"
36 #include "llvm/Target/TargetOptions.h"
40 HexagonRegisterInfo::HexagonRegisterInfo()
41 : HexagonGenRegisterInfo(Hexagon::R31) {}
44 HexagonRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
45 static const MCPhysReg CalleeSavedRegsV3[] = {
46 Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19,
47 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23,
48 Hexagon::R24, Hexagon::R25, Hexagon::R26, Hexagon::R27, 0
51 switch (MF->getSubtarget<HexagonSubtarget>().getHexagonArchVersion()) {
52 case HexagonSubtarget::V4:
53 case HexagonSubtarget::V5:
54 return CalleeSavedRegsV3;
56 llvm_unreachable("Callee saved registers requested for unknown architecture "
60 BitVector HexagonRegisterInfo::getReservedRegs(const MachineFunction &MF)
62 BitVector Reserved(getNumRegs());
63 Reserved.set(HEXAGON_RESERVED_REG_1);
64 Reserved.set(HEXAGON_RESERVED_REG_2);
65 Reserved.set(Hexagon::R29);
66 Reserved.set(Hexagon::R30);
67 Reserved.set(Hexagon::R31);
68 Reserved.set(Hexagon::D14);
69 Reserved.set(Hexagon::D15);
70 Reserved.set(Hexagon::LC0);
71 Reserved.set(Hexagon::LC1);
72 Reserved.set(Hexagon::SA0);
73 Reserved.set(Hexagon::SA1);
78 const TargetRegisterClass* const*
79 HexagonRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
80 static const TargetRegisterClass * const CalleeSavedRegClassesV3[] = {
81 &Hexagon::IntRegsRegClass, &Hexagon::IntRegsRegClass,
82 &Hexagon::IntRegsRegClass, &Hexagon::IntRegsRegClass,
83 &Hexagon::IntRegsRegClass, &Hexagon::IntRegsRegClass,
84 &Hexagon::IntRegsRegClass, &Hexagon::IntRegsRegClass,
85 &Hexagon::IntRegsRegClass, &Hexagon::IntRegsRegClass,
86 &Hexagon::IntRegsRegClass, &Hexagon::IntRegsRegClass,
89 switch (MF->getSubtarget<HexagonSubtarget>().getHexagonArchVersion()) {
90 case HexagonSubtarget::V4:
91 case HexagonSubtarget::V5:
92 return CalleeSavedRegClassesV3;
94 llvm_unreachable("Callee saved register classes requested for unknown "
95 "architecture version");
98 void HexagonRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
99 int SPAdj, unsigned FIOperandNum,
100 RegScavenger *RS) const {
102 // Hexagon_TODO: Do we need to enforce this for Hexagon?
103 assert(SPAdj == 0 && "Unexpected");
105 MachineInstr &MI = *II;
106 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
108 // Addressable stack objects are accessed using neg. offsets from %fp.
109 MachineFunction &MF = *MI.getParent()->getParent();
110 const HexagonInstrInfo &TII =
111 *static_cast<const HexagonInstrInfo *>(MF.getSubtarget().getInstrInfo());
112 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
113 MachineFrameInfo &MFI = *MF.getFrameInfo();
115 unsigned FrameReg = getFrameRegister(MF);
116 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
117 if (!TFI->hasFP(MF)) {
118 // We will not reserve space on the stack for the lr and fp registers.
119 Offset -= 2 * Hexagon_WordSize;
122 const unsigned FrameSize = MFI.getStackSize();
124 if (!MFI.hasVarSizedObjects() &&
125 TII.isValidOffset(MI.getOpcode(), (FrameSize+Offset)) &&
126 !TII.isSpillPredRegOp(&MI)) {
127 // Replace frame index with a stack pointer reference.
128 MI.getOperand(FIOperandNum).ChangeToRegister(getStackRegister(), false,
130 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(FrameSize+Offset);
132 // Replace frame index with a frame pointer reference.
133 if (!TII.isValidOffset(MI.getOpcode(), Offset)) {
135 // If the offset overflows, then correct it.
137 // For loads, we do not need a reserved register
138 // r0 = memw(r30 + #10000) to:
140 // r0 = add(r30, #10000)
142 if ( (MI.getOpcode() == Hexagon::L2_loadri_io) ||
143 (MI.getOpcode() == Hexagon::L2_loadrd_io) ||
144 (MI.getOpcode() == Hexagon::L2_loadrh_io) ||
145 (MI.getOpcode() == Hexagon::L2_loadruh_io) ||
146 (MI.getOpcode() == Hexagon::L2_loadrb_io) ||
147 (MI.getOpcode() == Hexagon::L2_loadrub_io)) {
148 unsigned dstReg = (MI.getOpcode() == Hexagon::L2_loadrd_io) ?
149 getSubReg(MI.getOperand(0).getReg(), Hexagon::subreg_loreg) :
150 MI.getOperand(0).getReg();
152 // Check if offset can fit in addi.
153 if (!TII.isValidOffset(Hexagon::A2_addi, Offset)) {
154 BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
155 TII.get(Hexagon::CONST32_Int_Real), dstReg).addImm(Offset);
156 BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
157 TII.get(Hexagon::A2_add),
158 dstReg).addReg(FrameReg).addReg(dstReg);
160 BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
161 TII.get(Hexagon::A2_addi),
162 dstReg).addReg(FrameReg).addImm(Offset);
165 MI.getOperand(FIOperandNum).ChangeToRegister(dstReg, false, false,true);
166 MI.getOperand(FIOperandNum+1).ChangeToImmediate(0);
167 } else if ((MI.getOpcode() == Hexagon::S2_storeri_io) ||
168 (MI.getOpcode() == Hexagon::S2_storerd_io) ||
169 (MI.getOpcode() == Hexagon::S2_storerh_io) ||
170 (MI.getOpcode() == Hexagon::S2_storerb_io)) {
171 // For stores, we need a reserved register. Change
172 // memw(r30 + #10000) = r0 to:
174 // rs = add(r30, #10000);
176 unsigned resReg = HEXAGON_RESERVED_REG_1;
178 // Check if offset can fit in addi.
179 if (!TII.isValidOffset(Hexagon::A2_addi, Offset)) {
180 BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
181 TII.get(Hexagon::CONST32_Int_Real), resReg).addImm(Offset);
182 BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
183 TII.get(Hexagon::A2_add),
184 resReg).addReg(FrameReg).addReg(resReg);
186 BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
187 TII.get(Hexagon::A2_addi),
188 resReg).addReg(FrameReg).addImm(Offset);
190 MI.getOperand(FIOperandNum).ChangeToRegister(resReg, false, false,true);
191 MI.getOperand(FIOperandNum+1).ChangeToImmediate(0);
192 } else if (TII.isMemOp(&MI)) {
193 // use the constant extender if the instruction provides it
194 if (TII.isConstExtended(&MI)) {
195 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false);
196 MI.getOperand(FIOperandNum+1).ChangeToImmediate(Offset);
197 TII.immediateExtend(&MI);
199 llvm_unreachable("Need to implement for memops");
202 unsigned dstReg = MI.getOperand(0).getReg();
203 BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
204 TII.get(Hexagon::CONST32_Int_Real), dstReg).addImm(Offset);
205 BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
206 TII.get(Hexagon::A2_add),
207 dstReg).addReg(FrameReg).addReg(dstReg);
208 // Can we delete MI??? r2 = add (r2, #0).
209 MI.getOperand(FIOperandNum).ChangeToRegister(dstReg, false, false,true);
210 MI.getOperand(FIOperandNum+1).ChangeToImmediate(0);
213 // If the offset is small enough to fit in the immediate field, directly
215 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false);
216 MI.getOperand(FIOperandNum+1).ChangeToImmediate(Offset);
222 unsigned HexagonRegisterInfo::getRARegister() const {
226 unsigned HexagonRegisterInfo::getFrameRegister(const MachineFunction
228 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
229 if (TFI->hasFP(MF)) {
236 unsigned HexagonRegisterInfo::getFrameRegister() const {
240 unsigned HexagonRegisterInfo::getStackRegister() const {
244 #define GET_REGINFO_TARGET_DESC
245 #include "HexagonGenRegisterInfo.inc"