1 //===- HexagonMachineScheduler.cpp - MI Scheduler for Hexagon -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // MachineScheduler schedules machine instructions after phi elimination. It
11 // preserves LiveIntervals so it can be invoked before register allocation.
13 //===----------------------------------------------------------------------===//
15 #include "HexagonMachineScheduler.h"
16 #include "llvm/CodeGen/MachineLoopInfo.h"
17 #include "llvm/IR/Function.h"
21 #define DEBUG_TYPE "misched"
23 /// Platform-specific modifications to DAG.
24 void VLIWMachineScheduler::postprocessDAG() {
25 SUnit* LastSequentialCall = nullptr;
26 // Currently we only catch the situation when compare gets scheduled
27 // before preceding call.
28 for (unsigned su = 0, e = SUnits.size(); su != e; ++su) {
30 if (SUnits[su].getInstr()->isCall())
31 LastSequentialCall = &(SUnits[su]);
32 // Look for a compare that defines a predicate.
33 else if (SUnits[su].getInstr()->isCompare() && LastSequentialCall)
34 SUnits[su].addPred(SDep(LastSequentialCall, SDep::Barrier));
38 /// Check if scheduling of this SU is possible
39 /// in the current packet.
40 /// It is _not_ precise (statefull), it is more like
41 /// another heuristic. Many corner cases are figured
43 bool VLIWResourceModel::isResourceAvailable(SUnit *SU) {
44 if (!SU || !SU->getInstr())
47 // First see if the pipeline could receive this instruction
48 // in the current cycle.
49 switch (SU->getInstr()->getOpcode()) {
51 if (!ResourcesModel->canReserveResources(SU->getInstr()))
53 case TargetOpcode::EXTRACT_SUBREG:
54 case TargetOpcode::INSERT_SUBREG:
55 case TargetOpcode::SUBREG_TO_REG:
56 case TargetOpcode::REG_SEQUENCE:
57 case TargetOpcode::IMPLICIT_DEF:
58 case TargetOpcode::COPY:
59 case TargetOpcode::INLINEASM:
63 // Now see if there are no other dependencies to instructions already
65 for (unsigned i = 0, e = Packet.size(); i != e; ++i) {
66 if (Packet[i]->Succs.size() == 0)
68 for (SUnit::const_succ_iterator I = Packet[i]->Succs.begin(),
69 E = Packet[i]->Succs.end(); I != E; ++I) {
70 // Since we do not add pseudos to packets, might as well
71 // ignore order dependencies.
75 if (I->getSUnit() == SU)
82 /// Keep track of available resources.
83 bool VLIWResourceModel::reserveResources(SUnit *SU) {
84 bool startNewCycle = false;
85 // Artificially reset state.
87 ResourcesModel->clearResources();
92 // If this SU does not fit in the packet
94 if (!isResourceAvailable(SU)) {
95 ResourcesModel->clearResources();
101 switch (SU->getInstr()->getOpcode()) {
103 ResourcesModel->reserveResources(SU->getInstr());
105 case TargetOpcode::EXTRACT_SUBREG:
106 case TargetOpcode::INSERT_SUBREG:
107 case TargetOpcode::SUBREG_TO_REG:
108 case TargetOpcode::REG_SEQUENCE:
109 case TargetOpcode::IMPLICIT_DEF:
110 case TargetOpcode::KILL:
111 case TargetOpcode::CFI_INSTRUCTION:
112 case TargetOpcode::EH_LABEL:
113 case TargetOpcode::COPY:
114 case TargetOpcode::INLINEASM:
117 Packet.push_back(SU);
120 DEBUG(dbgs() << "Packet[" << TotalPackets << "]:\n");
121 for (unsigned i = 0, e = Packet.size(); i != e; ++i) {
122 DEBUG(dbgs() << "\t[" << i << "] SU(");
123 DEBUG(dbgs() << Packet[i]->NodeNum << ")\t");
124 DEBUG(Packet[i]->getInstr()->dump());
128 // If packet is now full, reset the state so in the next cycle
130 if (Packet.size() >= SchedModel->getIssueWidth()) {
131 ResourcesModel->clearResources();
134 startNewCycle = true;
137 return startNewCycle;
140 /// schedule - Called back from MachineScheduler::runOnMachineFunction
141 /// after setting up the current scheduling region. [RegionBegin, RegionEnd)
142 /// only includes instructions that have DAG nodes, not scheduling boundaries.
143 void VLIWMachineScheduler::schedule() {
145 << "********** MI Converging Scheduling VLIW BB#" << BB->getNumber()
146 << " " << BB->getName()
147 << " in_func " << BB->getParent()->getFunction()->getName()
148 << " at loop depth " << MLI->getLoopDepth(BB)
151 buildDAGWithRegPressure();
153 // Postprocess the DAG to add platform-specific artificial dependencies.
156 SmallVector<SUnit*, 8> TopRoots, BotRoots;
157 findRootsAndBiasEdges(TopRoots, BotRoots);
159 // Initialize the strategy before modifying the DAG.
160 SchedImpl->initialize(this);
162 // To view Height/Depth correctly, they should be accessed at least once.
164 // FIXME: SUnit::dumpAll always recompute depth and height now. The max
165 // depth/height could be computed directly from the roots and leaves.
166 DEBUG(unsigned maxH = 0;
167 for (unsigned su = 0, e = SUnits.size(); su != e; ++su)
168 if (SUnits[su].getHeight() > maxH)
169 maxH = SUnits[su].getHeight();
170 dbgs() << "Max Height " << maxH << "\n";);
171 DEBUG(unsigned maxD = 0;
172 for (unsigned su = 0, e = SUnits.size(); su != e; ++su)
173 if (SUnits[su].getDepth() > maxD)
174 maxD = SUnits[su].getDepth();
175 dbgs() << "Max Depth " << maxD << "\n";);
176 DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su)
177 SUnits[su].dumpAll(this));
179 initQueues(TopRoots, BotRoots);
181 bool IsTopNode = false;
182 while (SUnit *SU = SchedImpl->pickNode(IsTopNode)) {
183 if (!checkSchedLimit())
186 scheduleMI(SU, IsTopNode);
188 updateQueues(SU, IsTopNode);
190 // Notify the scheduling strategy after updating the DAG.
191 SchedImpl->schedNode(SU, IsTopNode);
193 assert(CurrentTop == CurrentBottom && "Nonempty unscheduled zone.");
198 void ConvergingVLIWScheduler::initialize(ScheduleDAGMI *dag) {
199 DAG = static_cast<VLIWMachineScheduler*>(dag);
200 SchedModel = DAG->getSchedModel();
202 Top.init(DAG, SchedModel);
203 Bot.init(DAG, SchedModel);
205 // Initialize the HazardRecognizers. If itineraries don't exist, are empty, or
206 // are disabled, then these HazardRecs will be disabled.
207 const InstrItineraryData *Itin = DAG->getSchedModel()->getInstrItineraries();
208 const TargetSubtargetInfo &STI = DAG->MF.getSubtarget();
209 const TargetInstrInfo *TII = STI.getInstrInfo();
210 delete Top.HazardRec;
211 delete Bot.HazardRec;
212 Top.HazardRec = TII->CreateTargetMIHazardRecognizer(Itin, DAG);
213 Bot.HazardRec = TII->CreateTargetMIHazardRecognizer(Itin, DAG);
215 delete Top.ResourceModel;
216 delete Bot.ResourceModel;
217 Top.ResourceModel = new VLIWResourceModel(STI, DAG->getSchedModel());
218 Bot.ResourceModel = new VLIWResourceModel(STI, DAG->getSchedModel());
220 assert((!llvm::ForceTopDown || !llvm::ForceBottomUp) &&
221 "-misched-topdown incompatible with -misched-bottomup");
224 void ConvergingVLIWScheduler::releaseTopNode(SUnit *SU) {
228 for (SUnit::succ_iterator I = SU->Preds.begin(), E = SU->Preds.end();
230 unsigned PredReadyCycle = I->getSUnit()->TopReadyCycle;
231 unsigned MinLatency = I->getLatency();
233 Top.MaxMinLatency = std::max(MinLatency, Top.MaxMinLatency);
235 if (SU->TopReadyCycle < PredReadyCycle + MinLatency)
236 SU->TopReadyCycle = PredReadyCycle + MinLatency;
238 Top.releaseNode(SU, SU->TopReadyCycle);
241 void ConvergingVLIWScheduler::releaseBottomNode(SUnit *SU) {
245 assert(SU->getInstr() && "Scheduled SUnit must have instr");
247 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
249 unsigned SuccReadyCycle = I->getSUnit()->BotReadyCycle;
250 unsigned MinLatency = I->getLatency();
252 Bot.MaxMinLatency = std::max(MinLatency, Bot.MaxMinLatency);
254 if (SU->BotReadyCycle < SuccReadyCycle + MinLatency)
255 SU->BotReadyCycle = SuccReadyCycle + MinLatency;
257 Bot.releaseNode(SU, SU->BotReadyCycle);
260 /// Does this SU have a hazard within the current instruction group.
262 /// The scheduler supports two modes of hazard recognition. The first is the
263 /// ScheduleHazardRecognizer API. It is a fully general hazard recognizer that
264 /// supports highly complicated in-order reservation tables
265 /// (ScoreboardHazardRecognizer) and arbitrary target-specific logic.
267 /// The second is a streamlined mechanism that checks for hazards based on
268 /// simple counters that the scheduler itself maintains. It explicitly checks
269 /// for instruction dispatch limitations, including the number of micro-ops that
270 /// can dispatch per cycle.
272 /// TODO: Also check whether the SU must start a new group.
273 bool ConvergingVLIWScheduler::VLIWSchedBoundary::checkHazard(SUnit *SU) {
274 if (HazardRec->isEnabled())
275 return HazardRec->getHazardType(SU) != ScheduleHazardRecognizer::NoHazard;
277 unsigned uops = SchedModel->getNumMicroOps(SU->getInstr());
278 if (IssueCount + uops > SchedModel->getIssueWidth())
284 void ConvergingVLIWScheduler::VLIWSchedBoundary::releaseNode(SUnit *SU,
285 unsigned ReadyCycle) {
286 if (ReadyCycle < MinReadyCycle)
287 MinReadyCycle = ReadyCycle;
289 // Check for interlocks first. For the purpose of other heuristics, an
290 // instruction that cannot issue appears as if it's not in the ReadyQueue.
291 if (ReadyCycle > CurrCycle || checkHazard(SU))
298 /// Move the boundary of scheduled code by one cycle.
299 void ConvergingVLIWScheduler::VLIWSchedBoundary::bumpCycle() {
300 unsigned Width = SchedModel->getIssueWidth();
301 IssueCount = (IssueCount <= Width) ? 0 : IssueCount - Width;
303 assert(MinReadyCycle < UINT_MAX && "MinReadyCycle uninitialized");
304 unsigned NextCycle = std::max(CurrCycle + 1, MinReadyCycle);
306 if (!HazardRec->isEnabled()) {
307 // Bypass HazardRec virtual calls.
308 CurrCycle = NextCycle;
310 // Bypass getHazardType calls in case of long latency.
311 for (; CurrCycle != NextCycle; ++CurrCycle) {
313 HazardRec->AdvanceCycle();
315 HazardRec->RecedeCycle();
320 DEBUG(dbgs() << "*** " << Available.getName() << " cycle "
321 << CurrCycle << '\n');
324 /// Move the boundary of scheduled code by one SUnit.
325 void ConvergingVLIWScheduler::VLIWSchedBoundary::bumpNode(SUnit *SU) {
326 bool startNewCycle = false;
328 // Update the reservation table.
329 if (HazardRec->isEnabled()) {
330 if (!isTop() && SU->isCall) {
331 // Calls are scheduled with their preceding instructions. For bottom-up
332 // scheduling, clear the pipeline state before emitting.
335 HazardRec->EmitInstruction(SU);
339 startNewCycle = ResourceModel->reserveResources(SU);
341 // Check the instruction group dispatch limit.
342 // TODO: Check if this SU must end a dispatch group.
343 IssueCount += SchedModel->getNumMicroOps(SU->getInstr());
345 DEBUG(dbgs() << "*** Max instrs at cycle " << CurrCycle << '\n');
349 DEBUG(dbgs() << "*** IssueCount " << IssueCount
350 << " at cycle " << CurrCycle << '\n');
353 /// Release pending ready nodes in to the available queue. This makes them
354 /// visible to heuristics.
355 void ConvergingVLIWScheduler::VLIWSchedBoundary::releasePending() {
356 // If the available queue is empty, it is safe to reset MinReadyCycle.
357 if (Available.empty())
358 MinReadyCycle = UINT_MAX;
360 // Check to see if any of the pending instructions are ready to issue. If
361 // so, add them to the available queue.
362 for (unsigned i = 0, e = Pending.size(); i != e; ++i) {
363 SUnit *SU = *(Pending.begin()+i);
364 unsigned ReadyCycle = isTop() ? SU->TopReadyCycle : SU->BotReadyCycle;
366 if (ReadyCycle < MinReadyCycle)
367 MinReadyCycle = ReadyCycle;
369 if (ReadyCycle > CurrCycle)
376 Pending.remove(Pending.begin()+i);
379 CheckPending = false;
382 /// Remove SU from the ready set for this boundary.
383 void ConvergingVLIWScheduler::VLIWSchedBoundary::removeReady(SUnit *SU) {
384 if (Available.isInQueue(SU))
385 Available.remove(Available.find(SU));
387 assert(Pending.isInQueue(SU) && "bad ready count");
388 Pending.remove(Pending.find(SU));
392 /// If this queue only has one ready candidate, return it. As a side effect,
393 /// advance the cycle until at least one node is ready. If multiple instructions
394 /// are ready, return NULL.
395 SUnit *ConvergingVLIWScheduler::VLIWSchedBoundary::pickOnlyChoice() {
399 for (unsigned i = 0; Available.empty(); ++i) {
400 assert(i <= (HazardRec->getMaxLookAhead() + MaxMinLatency) &&
401 "permanent hazard"); (void)i;
402 ResourceModel->reserveResources(nullptr);
406 if (Available.size() == 1)
407 return *Available.begin();
412 void ConvergingVLIWScheduler::traceCandidate(const char *Label,
414 SUnit *SU, PressureChange P) {
415 dbgs() << Label << " " << Q.getName() << " ";
417 dbgs() << DAG->TRI->getRegPressureSetName(P.getPSet()) << ":"
418 << P.getUnitInc() << " ";
425 /// getSingleUnscheduledPred - If there is exactly one unscheduled predecessor
426 /// of SU, return it, otherwise return null.
427 static SUnit *getSingleUnscheduledPred(SUnit *SU) {
428 SUnit *OnlyAvailablePred = nullptr;
429 for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
431 SUnit &Pred = *I->getSUnit();
432 if (!Pred.isScheduled) {
433 // We found an available, but not scheduled, predecessor. If it's the
434 // only one we have found, keep track of it... otherwise give up.
435 if (OnlyAvailablePred && OnlyAvailablePred != &Pred)
437 OnlyAvailablePred = &Pred;
440 return OnlyAvailablePred;
443 /// getSingleUnscheduledSucc - If there is exactly one unscheduled successor
444 /// of SU, return it, otherwise return null.
445 static SUnit *getSingleUnscheduledSucc(SUnit *SU) {
446 SUnit *OnlyAvailableSucc = nullptr;
447 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
449 SUnit &Succ = *I->getSUnit();
450 if (!Succ.isScheduled) {
451 // We found an available, but not scheduled, successor. If it's the
452 // only one we have found, keep track of it... otherwise give up.
453 if (OnlyAvailableSucc && OnlyAvailableSucc != &Succ)
455 OnlyAvailableSucc = &Succ;
458 return OnlyAvailableSucc;
461 // Constants used to denote relative importance of
462 // heuristic components for cost computation.
463 static const unsigned PriorityOne = 200;
464 static const unsigned PriorityTwo = 50;
465 static const unsigned ScaleTwo = 10;
466 static const unsigned FactorOne = 2;
468 /// Single point to compute overall scheduling cost.
469 /// TODO: More heuristics will be used soon.
470 int ConvergingVLIWScheduler::SchedulingCost(ReadyQueue &Q, SUnit *SU,
471 SchedCandidate &Candidate,
472 RegPressureDelta &Delta,
474 // Initial trivial priority.
477 // Do not waste time on a node that is already scheduled.
478 if (!SU || SU->isScheduled)
481 // Forced priority is high.
482 if (SU->isScheduleHigh)
483 ResCount += PriorityOne;
485 // Critical path first.
486 if (Q.getID() == TopQID) {
487 ResCount += (SU->getHeight() * ScaleTwo);
489 // If resources are available for it, multiply the
490 // chance of scheduling.
491 if (Top.ResourceModel->isResourceAvailable(SU))
492 ResCount <<= FactorOne;
494 ResCount += (SU->getDepth() * ScaleTwo);
496 // If resources are available for it, multiply the
497 // chance of scheduling.
498 if (Bot.ResourceModel->isResourceAvailable(SU))
499 ResCount <<= FactorOne;
502 unsigned NumNodesBlocking = 0;
503 if (Q.getID() == TopQID) {
504 // How many SUs does it block from scheduling?
505 // Look at all of the successors of this node.
506 // Count the number of nodes that
507 // this node is the sole unscheduled node for.
508 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
510 if (getSingleUnscheduledPred(I->getSUnit()) == SU)
513 // How many unscheduled predecessors block this node?
514 for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
516 if (getSingleUnscheduledSucc(I->getSUnit()) == SU)
519 ResCount += (NumNodesBlocking * ScaleTwo);
521 // Factor in reg pressure as a heuristic.
522 ResCount -= (Delta.Excess.getUnitInc()*PriorityTwo);
523 ResCount -= (Delta.CriticalMax.getUnitInc()*PriorityTwo);
525 DEBUG(if (verbose) dbgs() << " Total(" << ResCount << ")");
530 /// Pick the best candidate from the top queue.
532 /// TODO: getMaxPressureDelta results can be mostly cached for each SUnit during
533 /// DAG building. To adjust for the current scheduling location we need to
534 /// maintain the number of vreg uses remaining to be top-scheduled.
535 ConvergingVLIWScheduler::CandResult ConvergingVLIWScheduler::
536 pickNodeFromQueue(ReadyQueue &Q, const RegPressureTracker &RPTracker,
537 SchedCandidate &Candidate) {
540 // getMaxPressureDelta temporarily modifies the tracker.
541 RegPressureTracker &TempTracker = const_cast<RegPressureTracker&>(RPTracker);
543 // BestSU remains NULL if no top candidates beat the best existing candidate.
544 CandResult FoundCandidate = NoCand;
545 for (ReadyQueue::iterator I = Q.begin(), E = Q.end(); I != E; ++I) {
546 RegPressureDelta RPDelta;
547 TempTracker.getMaxPressureDelta((*I)->getInstr(), RPDelta,
548 DAG->getRegionCriticalPSets(),
549 DAG->getRegPressure().MaxSetPressure);
551 int CurrentCost = SchedulingCost(Q, *I, Candidate, RPDelta, false);
553 // Initialize the candidate if needed.
556 Candidate.RPDelta = RPDelta;
557 Candidate.SCost = CurrentCost;
558 FoundCandidate = NodeOrder;
563 if (CurrentCost > Candidate.SCost) {
564 DEBUG(traceCandidate("CCAND", Q, *I));
566 Candidate.RPDelta = RPDelta;
567 Candidate.SCost = CurrentCost;
568 FoundCandidate = BestCost;
572 // Fall through to original instruction order.
573 // Only consider node order if Candidate was chosen from this Q.
574 if (FoundCandidate == NoCand)
577 return FoundCandidate;
580 /// Pick the best candidate node from either the top or bottom queue.
581 SUnit *ConvergingVLIWScheduler::pickNodeBidrectional(bool &IsTopNode) {
582 // Schedule as far as possible in the direction of no choice. This is most
583 // efficient, but also provides the best heuristics for CriticalPSets.
584 if (SUnit *SU = Bot.pickOnlyChoice()) {
588 if (SUnit *SU = Top.pickOnlyChoice()) {
592 SchedCandidate BotCand;
593 // Prefer bottom scheduling when heuristics are silent.
594 CandResult BotResult = pickNodeFromQueue(Bot.Available,
595 DAG->getBotRPTracker(), BotCand);
596 assert(BotResult != NoCand && "failed to find the first candidate");
598 // If either Q has a single candidate that provides the least increase in
599 // Excess pressure, we can immediately schedule from that Q.
601 // RegionCriticalPSets summarizes the pressure within the scheduled region and
602 // affects picking from either Q. If scheduling in one direction must
603 // increase pressure for one of the excess PSets, then schedule in that
604 // direction first to provide more freedom in the other direction.
605 if (BotResult == SingleExcess || BotResult == SingleCritical) {
609 // Check if the top Q has a better candidate.
610 SchedCandidate TopCand;
611 CandResult TopResult = pickNodeFromQueue(Top.Available,
612 DAG->getTopRPTracker(), TopCand);
613 assert(TopResult != NoCand && "failed to find the first candidate");
615 if (TopResult == SingleExcess || TopResult == SingleCritical) {
619 // If either Q has a single candidate that minimizes pressure above the
620 // original region's pressure pick it.
621 if (BotResult == SingleMax) {
625 if (TopResult == SingleMax) {
629 if (TopCand.SCost > BotCand.SCost) {
633 // Otherwise prefer the bottom candidate in node order.
638 /// Pick the best node to balance the schedule. Implements MachineSchedStrategy.
639 SUnit *ConvergingVLIWScheduler::pickNode(bool &IsTopNode) {
640 if (DAG->top() == DAG->bottom()) {
641 assert(Top.Available.empty() && Top.Pending.empty() &&
642 Bot.Available.empty() && Bot.Pending.empty() && "ReadyQ garbage");
646 if (llvm::ForceTopDown) {
647 SU = Top.pickOnlyChoice();
649 SchedCandidate TopCand;
650 CandResult TopResult =
651 pickNodeFromQueue(Top.Available, DAG->getTopRPTracker(), TopCand);
652 assert(TopResult != NoCand && "failed to find the first candidate");
657 } else if (llvm::ForceBottomUp) {
658 SU = Bot.pickOnlyChoice();
660 SchedCandidate BotCand;
661 CandResult BotResult =
662 pickNodeFromQueue(Bot.Available, DAG->getBotRPTracker(), BotCand);
663 assert(BotResult != NoCand && "failed to find the first candidate");
669 SU = pickNodeBidrectional(IsTopNode);
671 if (SU->isTopReady())
673 if (SU->isBottomReady())
676 DEBUG(dbgs() << "*** " << (IsTopNode ? "Top" : "Bottom")
677 << " Scheduling Instruction in cycle "
678 << (IsTopNode ? Top.CurrCycle : Bot.CurrCycle) << '\n';
683 /// Update the scheduler's state after scheduling a node. This is the same node
684 /// that was just returned by pickNode(). However, VLIWMachineScheduler needs
685 /// to update it's state based on the current cycle before MachineSchedStrategy
687 void ConvergingVLIWScheduler::schedNode(SUnit *SU, bool IsTopNode) {
689 SU->TopReadyCycle = Top.CurrCycle;
692 SU->BotReadyCycle = Bot.CurrCycle;