lib/Target/Hexagon/HexagonIntrinsicsV5.td

   1 //===- HexagonIntrinsicsV5.td - V4 Instruction intrinsics --*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9
  10 def : T_FF_pat<F2_sfadd, int_hexagon_F2_sfadd>;
  11 def : T_FF_pat<F2_sfsub, int_hexagon_F2_sfsub>;
  12 def : T_FF_pat<F2_sfmpy, int_hexagon_F2_sfmpy>;
  13 def : T_FF_pat<F2_sfmax, int_hexagon_F2_sfmax>;
  14 def : T_FF_pat<F2_sfmin, int_hexagon_F2_sfmin>;
  15
  16 def : T_FF_pat<F2_sffixupn, int_hexagon_F2_sffixupn>;
  17 def : T_FF_pat<F2_sffixupd, int_hexagon_F2_sffixupd>;
  18 def : T_F_pat <F2_sffixupr, int_hexagon_F2_sffixupr>;
  19
  20 def : T_P_pat <S5_popcountp, int_hexagon_S5_popcountp>;
  21 def : T_PI_pat <S5_asrhub_sat, int_hexagon_S5_asrhub_sat>;
  22
  23 def : T_PI_pat <S2_asr_i_p_rnd, int_hexagon_S2_asr_i_p_rnd>;
  24 def : T_PI_pat <S2_asr_i_p_rnd_goodsyntax,
  25                 int_hexagon_S2_asr_i_p_rnd_goodsyntax>;
  26
  27 def : T_PI_pat <S5_asrhub_rnd_sat_goodsyntax,
  28                 int_hexagon_S5_asrhub_rnd_sat_goodsyntax>;
  29
  30 def : T_FFF_pat <F2_sffma, int_hexagon_F2_sffma>;
  31 def : T_FFF_pat <F2_sffms, int_hexagon_F2_sffms>;
  32 def : T_FFF_pat <F2_sffma_lib, int_hexagon_F2_sffma_lib>;
  33 def : T_FFF_pat <F2_sffms_lib, int_hexagon_F2_sffms_lib>;
  34 def : T_FFFQ_pat <F2_sffma_sc, int_hexagon_F2_sffma_sc>;
  35
  36 // Compare floating-point value
  37 def : T_FF_pat <F2_sfcmpge, int_hexagon_F2_sfcmpge>;
  38 def : T_FF_pat <F2_sfcmpuo, int_hexagon_F2_sfcmpuo>;
  39 def : T_FF_pat <F2_sfcmpeq, int_hexagon_F2_sfcmpeq>;
  40 def : T_FF_pat <F2_sfcmpgt, int_hexagon_F2_sfcmpgt>;
  41
  42 def : T_DD_pat <F2_dfcmpeq, int_hexagon_F2_dfcmpeq>;
  43 def : T_DD_pat <F2_dfcmpgt, int_hexagon_F2_dfcmpgt>;
  44 def : T_DD_pat <F2_dfcmpge, int_hexagon_F2_dfcmpge>;
  45 def : T_DD_pat <F2_dfcmpuo, int_hexagon_F2_dfcmpuo>;
  46
  47 // Create floating-point value
  48 def : T_I_pat <F2_sfimm_p, int_hexagon_F2_sfimm_p>;
  49 def : T_I_pat <F2_sfimm_n, int_hexagon_F2_sfimm_n>;
  50 def : T_I_pat <F2_dfimm_p, int_hexagon_F2_dfimm_p>;
  51 def : T_I_pat <F2_dfimm_n, int_hexagon_F2_dfimm_n>;
  52
  53 def : T_DI_pat <F2_dfclass, int_hexagon_F2_dfclass>;
  54 def : T_FI_pat <F2_sfclass, int_hexagon_F2_sfclass>;
  55 def : T_F_pat <F2_conv_sf2df, int_hexagon_F2_conv_sf2df>;
  56 def : T_D_pat <F2_conv_df2sf, int_hexagon_F2_conv_df2sf>;
  57 def : T_R_pat <F2_conv_uw2sf, int_hexagon_F2_conv_uw2sf>;
  58 def : T_R_pat <F2_conv_uw2df, int_hexagon_F2_conv_uw2df>;
  59 def : T_R_pat <F2_conv_w2sf,  int_hexagon_F2_conv_w2sf>;
  60 def : T_R_pat <F2_conv_w2df,  int_hexagon_F2_conv_w2df>;
  61 def : T_P_pat <F2_conv_ud2sf, int_hexagon_F2_conv_ud2sf>;
  62 def : T_P_pat <F2_conv_ud2df, int_hexagon_F2_conv_ud2df>;
  63 def : T_P_pat <F2_conv_d2sf,  int_hexagon_F2_conv_d2sf>;
  64 def : T_P_pat <F2_conv_d2df,  int_hexagon_F2_conv_d2df>;
  65 def : T_F_pat <F2_conv_sf2uw, int_hexagon_F2_conv_sf2uw>;
  66 def : T_F_pat <F2_conv_sf2w,  int_hexagon_F2_conv_sf2w>;
  67 def : T_F_pat <F2_conv_sf2ud, int_hexagon_F2_conv_sf2ud>;
  68 def : T_F_pat <F2_conv_sf2d,  int_hexagon_F2_conv_sf2d>;
  69 def : T_D_pat <F2_conv_df2uw, int_hexagon_F2_conv_df2uw>;
  70 def : T_D_pat <F2_conv_df2w,  int_hexagon_F2_conv_df2w>;
  71 def : T_D_pat <F2_conv_df2ud, int_hexagon_F2_conv_df2ud>;
  72 def : T_D_pat <F2_conv_df2d,  int_hexagon_F2_conv_df2d>;
  73 def : T_F_pat <F2_conv_sf2uw_chop, int_hexagon_F2_conv_sf2uw_chop>;
  74 def : T_F_pat <F2_conv_sf2w_chop,  int_hexagon_F2_conv_sf2w_chop>;
  75 def : T_F_pat <F2_conv_sf2ud_chop, int_hexagon_F2_conv_sf2ud_chop>;
  76 def : T_F_pat <F2_conv_sf2d_chop,  int_hexagon_F2_conv_sf2d_chop>;
  77 def : T_D_pat <F2_conv_df2uw_chop, int_hexagon_F2_conv_df2uw_chop>;
  78 def : T_D_pat <F2_conv_df2w_chop,  int_hexagon_F2_conv_df2w_chop>;
  79 def : T_D_pat <F2_conv_df2ud_chop, int_hexagon_F2_conv_df2ud_chop>;
  80 def : T_D_pat <F2_conv_df2d_chop,  int_hexagon_F2_conv_df2d_chop>;
  81
  82 class qi_ALU64_dfdf<string opc, Intrinsic IntID>
  83   : ALU64_rr<(outs PredRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
  84            !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
  85            [(set PredRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
  86
  87 class qi_ALU64_dfu5<string opc, Intrinsic IntID>
  88   : ALU64_ri<(outs PredRegs:$dst), (ins DoubleRegs:$src1, u5Imm:$src2),
  89            !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
  90            [(set PredRegs:$dst, (IntID DoubleRegs:$src1, imm:$src2))]>;
  91
  92 class qi_SInst_sfsf<string opc, Intrinsic IntID>
  93   : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
  94              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
  95              [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
  96
  97 class qi_SInst_sfu5<string opc, Intrinsic IntID>
  98   : MInst<(outs PredRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
  99              !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
 100              [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
 101
 102 class di_MInst_diu4_rnd<string opc, Intrinsic IntID>
 103   : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u4Imm:$src2),
 104           !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2):rnd")),
 105           [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, imm:$src2))]>;
 106
 107 def HEXAGON_C4_fastcorner9:
 108     qi_SInst_qiqi       <"fastcorner9", int_hexagon_C4_fastcorner9>;
 109 def HEXAGON_C4_fastcorner9_not:
 110     qi_SInst_qiqi <"!fastcorner9", int_hexagon_C4_fastcorner9_not>;
 111 def HEXAGON_M5_vrmpybuu:
 112     di_MInst_didi <"vrmpybu", int_hexagon_M5_vrmpybuu>;
 113 def HEXAGON_M5_vrmacbuu:
 114     di_MInst_dididi_acc <"vrmpybu", int_hexagon_M5_vrmacbuu>;
 115 def HEXAGON_M5_vrmpybsu:
 116     di_MInst_didi <"vrmpybsu", int_hexagon_M5_vrmpybsu>;
 117 def HEXAGON_M5_vrmacbsu:
 118     di_MInst_dididi_acc <"vrmpybsu", int_hexagon_M5_vrmacbsu>;
 119 def HEXAGON_M5_vmpybuu:
 120     di_MInst_sisi <"vmpybu", int_hexagon_M5_vmpybuu>;
 121 def HEXAGON_M5_vmpybsu:
 122     di_MInst_sisi <"vmpybsu", int_hexagon_M5_vmpybsu>;
 123 def HEXAGON_M5_vmacbuu:
 124     di_MInst_disisi_acc <"vmpybu", int_hexagon_M5_vmacbuu>;
 125 def HEXAGON_M5_vmacbsu:
 126     di_MInst_disisi_acc <"vmpybsu", int_hexagon_M5_vmacbsu>;
 127 def HEXAGON_M5_vdmpybsu:
 128     di_MInst_didi_sat <"vdmpybsu", int_hexagon_M5_vdmpybsu>;
 129 def HEXAGON_M5_vdmacbsu:
 130     di_MInst_dididi_acc_sat <"vdmpybsu", int_hexagon_M5_vdmacbsu>;
 131 def HEXAGON_A5_vaddhubs:
 132     si_SInst_didi_sat <"vaddhub", int_hexagon_A5_vaddhubs>;
 133 def HEXAGON_S5_vasrhrnd_goodsyntax:
 134     di_MInst_diu4_rnd <"vasrh", int_hexagon_S5_vasrhrnd_goodsyntax>;
 135 def HEXAGON_F2_sfcmpeq:
 136     qi_SInst_sfsf <"sfcmp.eq", int_hexagon_F2_sfcmpeq>;
 137 def HEXAGON_F2_sfcmpgt:
 138     qi_SInst_sfsf <"sfcmp.gt", int_hexagon_F2_sfcmpgt>;
 139 def HEXAGON_F2_sfcmpge:
 140     qi_SInst_sfsf <"sfcmp.ge", int_hexagon_F2_sfcmpge>;
 141 def HEXAGON_F2_sfcmpuo:
 142     qi_SInst_sfsf <"sfcmp.uo", int_hexagon_F2_sfcmpuo>;