1 //===- HexagonIntrinsicsV4.td - V4 Instruction intrinsics --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
9 // This is populated based on the following specs:
10 // Hexagon V4 Architecture Extensions
11 // Application-Level Specification
15 // Polynomial multiply words
17 def : T_RR_pat <M4_pmpyw, int_hexagon_M4_pmpyw>;
19 def : T_PRR_pat <M4_pmpyw_acc, int_hexagon_M4_pmpyw_acc>;
22 def : T_PPR_pat <S2_asr_r_p_xor, int_hexagon_S2_asr_r_p_xor>;
24 def : T_PPR_pat <S2_asl_r_p_xor, int_hexagon_S2_asl_r_p_xor>;
26 def : T_PPR_pat <S2_lsr_r_p_xor, int_hexagon_S2_lsr_r_p_xor>;
28 def : T_PPR_pat <S2_lsl_r_p_xor, int_hexagon_S2_lsl_r_p_xor>;
30 // Multiply and use upper result
31 def : MType_R32_pat <int_hexagon_M2_mpysu_up, M2_mpysu_up>;
32 def : MType_R32_pat <int_hexagon_M2_mpy_up_s1, M2_mpy_up_s1>;
33 def : MType_R32_pat <int_hexagon_M2_hmmpyh_s1, M2_hmmpyh_s1>;
34 def : MType_R32_pat <int_hexagon_M2_hmmpyl_s1, M2_hmmpyl_s1>;
35 def : MType_R32_pat <int_hexagon_M2_mpy_up_s1_sat, M2_mpy_up_s1_sat>;
37 def : T_P_pat <S2_brevp, int_hexagon_S2_brevp>;
39 def: T_P_pat <S2_ct0p, int_hexagon_S2_ct0p>;
40 def: T_P_pat <S2_ct1p, int_hexagon_S2_ct1p>;
41 def: T_RR_pat<C4_nbitsset, int_hexagon_C4_nbitsset>;
42 def: T_RR_pat<C4_nbitsclr, int_hexagon_C4_nbitsclr>;
43 def: T_RI_pat<C4_nbitsclri, int_hexagon_C4_nbitsclri>;
45 def : T_RR_pat<A4_cmpbeq, int_hexagon_A4_cmpbeq>;
46 def : T_RR_pat<A4_cmpbgt, int_hexagon_A4_cmpbgt>;
47 def : T_RR_pat<A4_cmpbgtu, int_hexagon_A4_cmpbgtu>;
48 def : T_RR_pat<A4_cmpheq, int_hexagon_A4_cmpheq>;
49 def : T_RR_pat<A4_cmphgt, int_hexagon_A4_cmphgt>;
50 def : T_RR_pat<A4_cmphgtu, int_hexagon_A4_cmphgtu>;
52 def : T_RI_pat<A4_cmpbeqi, int_hexagon_A4_cmpbeqi>;
53 def : T_RI_pat<A4_cmpbgti, int_hexagon_A4_cmpbgti>;
54 def : T_RI_pat<A4_cmpbgtui, int_hexagon_A4_cmpbgtui>;
56 def : T_RI_pat<A4_cmpheqi, int_hexagon_A4_cmpheqi>;
57 def : T_RI_pat<A4_cmphgti, int_hexagon_A4_cmphgti>;
58 def : T_RI_pat<A4_cmphgtui, int_hexagon_A4_cmphgtui>;
60 def : T_RP_pat <A4_boundscheck, int_hexagon_A4_boundscheck>;
62 def : T_PR_pat<A4_tlbmatch, int_hexagon_A4_tlbmatch>;
64 def : Pat <(int_hexagon_M4_mpyrr_addr IntRegs:$src1, IntRegs:$src2,
66 (M4_mpyrr_addr IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
68 def : T_IRR_pat <M4_mpyrr_addi, int_hexagon_M4_mpyrr_addi>;
69 def : T_IRI_pat <M4_mpyri_addi, int_hexagon_M4_mpyri_addi>;
70 def : T_RIR_pat <M4_mpyri_addr_u2, int_hexagon_M4_mpyri_addr_u2>;
71 def : T_RRI_pat <M4_mpyri_addr, int_hexagon_M4_mpyri_addr>;
72 // Multiply 32x32 and use upper result
73 def : T_RRR_pat <M4_mac_up_s1_sat, int_hexagon_M4_mac_up_s1_sat>;
74 def : T_RRR_pat <M4_nac_up_s1_sat, int_hexagon_M4_nac_up_s1_sat>;
76 def : T_PP_pat<A4_andnp, int_hexagon_A4_andnp>;
77 def : T_PP_pat<A4_ornp, int_hexagon_A4_ornp>;
80 def : T_PP_pat <S4_extractp_rp, int_hexagon_S4_extractp_rp>;
81 def : T_RP_pat <S4_extract_rp, int_hexagon_S4_extract_rp>;
82 def : T_PII_pat <S4_extractp, int_hexagon_S4_extractp>;
83 def : T_RII_pat <S4_extract, int_hexagon_S4_extract>;
85 // Shift an immediate left by register amount
86 def : T_IR_pat<S4_lsli, int_hexagon_S4_lsli>;
88 // Logical xor with xor accumulation
89 def : T_PPP_pat<M4_xor_xacc, int_hexagon_M4_xor_xacc>;
91 // Shift and add/sub/and/or
92 def : T_IRI_pat <S4_andi_asl_ri, int_hexagon_S4_andi_asl_ri>;
93 def : T_IRI_pat <S4_ori_asl_ri, int_hexagon_S4_ori_asl_ri>;
94 def : T_IRI_pat <S4_addi_asl_ri, int_hexagon_S4_addi_asl_ri>;
95 def : T_IRI_pat <S4_subi_asl_ri, int_hexagon_S4_subi_asl_ri>;
96 def : T_IRI_pat <S4_andi_lsr_ri, int_hexagon_S4_andi_lsr_ri>;
97 def : T_IRI_pat <S4_ori_lsr_ri, int_hexagon_S4_ori_lsr_ri>;
98 def : T_IRI_pat <S4_addi_lsr_ri, int_hexagon_S4_addi_lsr_ri>;
99 def : T_IRI_pat <S4_subi_lsr_ri, int_hexagon_S4_subi_lsr_ri>;
102 def : T_RI_pat <A4_bitspliti, int_hexagon_A4_bitspliti>;
103 def : T_RR_pat <A4_bitsplit, int_hexagon_A4_bitsplit>;
105 def: T_RR_pat<S4_parity, int_hexagon_S4_parity>;
107 def: T_RI_pat<S4_ntstbit_i, int_hexagon_S4_ntstbit_i>;
108 def: T_RR_pat<S4_ntstbit_r, int_hexagon_S4_ntstbit_r>;
110 def: T_RI_pat<S4_clbaddi, int_hexagon_S4_clbaddi>;
111 def: T_PI_pat<S4_clbpaddi, int_hexagon_S4_clbpaddi>;
112 def: T_P_pat <S4_clbpnorm, int_hexagon_S4_clbpnorm>;
114 /********************************************************************
116 *********************************************************************/
118 // ALU32 / ALU / Logical Operations.
119 def: T_RR_pat<A4_andn, int_hexagon_A4_andn>;
120 def: T_RR_pat<A4_orn, int_hexagon_A4_orn>;
122 /********************************************************************
124 *********************************************************************/
126 // Combine Words Into Doublewords.
127 def: T_RI_pat<A4_combineri, int_hexagon_A4_combineri, s8ExtPred>;
128 def: T_IR_pat<A4_combineir, int_hexagon_A4_combineir, s8ExtPred>;
130 /********************************************************************
132 *********************************************************************/
134 def: T_RR_pat<A4_rcmpeq, int_hexagon_A4_rcmpeq>;
135 def: T_RR_pat<A4_rcmpneq, int_hexagon_A4_rcmpneq>;
137 def: T_RI_pat<A4_rcmpeqi, int_hexagon_A4_rcmpeqi>;
138 def: T_RI_pat<A4_rcmpneqi, int_hexagon_A4_rcmpneqi>;
140 /********************************************************************
142 *********************************************************************/
144 // Add And Accumulate.
146 def : T_RRI_pat <S4_addaddi, int_hexagon_S4_addaddi>;
147 def : T_RIR_pat <S4_subaddi, int_hexagon_S4_subaddi>;
150 // XTYPE / ALU / Logical-logical Words.
151 def : T_RRR_pat <M4_or_xor, int_hexagon_M4_or_xor>;
152 def : T_RRR_pat <M4_and_xor, int_hexagon_M4_and_xor>;
153 def : T_RRR_pat <M4_or_and, int_hexagon_M4_or_and>;
154 def : T_RRR_pat <M4_and_and, int_hexagon_M4_and_and>;
155 def : T_RRR_pat <M4_xor_and, int_hexagon_M4_xor_and>;
156 def : T_RRR_pat <M4_or_or, int_hexagon_M4_or_or>;
157 def : T_RRR_pat <M4_and_or, int_hexagon_M4_and_or>;
158 def : T_RRR_pat <M4_xor_or, int_hexagon_M4_xor_or>;
159 def : T_RRR_pat <M4_or_andn, int_hexagon_M4_or_andn>;
160 def : T_RRR_pat <M4_and_andn, int_hexagon_M4_and_andn>;
161 def : T_RRR_pat <M4_xor_andn, int_hexagon_M4_xor_andn>;
163 def : T_RRI_pat <S4_or_andi, int_hexagon_S4_or_andi>;
164 def : T_RRI_pat <S4_or_andix, int_hexagon_S4_or_andix>;
165 def : T_RRI_pat <S4_or_ori, int_hexagon_S4_or_ori>;
168 def : T_RR_pat <A4_modwrapu, int_hexagon_A4_modwrapu>;
170 // Arithmetic/Convergent round
171 // Rd=[cround|round](Rs,Rt)[:sat]
172 // Rd=[cround|round](Rs,#u5)[:sat]
173 def : T_RI_pat <A4_cround_ri, int_hexagon_A4_cround_ri>;
174 def : T_RR_pat <A4_cround_rr, int_hexagon_A4_cround_rr>;
176 def : T_RI_pat <A4_round_ri, int_hexagon_A4_round_ri>;
177 def : T_RR_pat <A4_round_rr, int_hexagon_A4_round_rr>;
179 def : T_RI_pat <A4_round_ri_sat, int_hexagon_A4_round_ri_sat>;
180 def : T_RR_pat <A4_round_rr_sat, int_hexagon_A4_round_rr_sat>;
182 def : T_P_pat <A2_roundsat, int_hexagon_A2_roundsat>;
184 class qi_neg_ALU32_sisi<string opc, Intrinsic IntID>
185 : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
186 !strconcat("$dst = !", !strconcat(opc , "($src1, $src2)")),
187 [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
189 class qi_neg_ALU32_sis10<string opc, Intrinsic IntID>
190 : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, s10Imm:$src2),
191 !strconcat("$dst = !", !strconcat(opc , "($src1, #$src2)")),
192 [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
194 class qi_neg_ALU32_siu9<string opc, Intrinsic IntID>
195 : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, u9Imm:$src2),
196 !strconcat("$dst = !", !strconcat(opc , "($src1, #$src2)")),
197 [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
202 class qi_neg_SInst_qiqi<string opc, Intrinsic IntID>
203 : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
204 !strconcat("$dst = !", !strconcat(opc , "($src1, $src2)")),
205 [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
207 class qi_SInst_qi_andqiqi_neg<string opc, Intrinsic IntID>
208 : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2,
210 !strconcat("$dst = ", !strconcat(opc ,
211 "($src1, and($src2, !$src3)")),
212 [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2,
215 class qi_SInst_qi_andqiqi<string opc, Intrinsic IntID>
216 : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2,
218 !strconcat("$dst = ", !strconcat(opc ,
219 "($src1, and($src2, $src3)")),
220 [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2,
223 class qi_SInst_qi_orqiqi_neg<string opc, Intrinsic IntID>
224 : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2,
226 !strconcat("$dst = ", !strconcat(opc ,
227 "($src1, or($src2, !$src3)")),
228 [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2,
231 class qi_SInst_qi_orqiqi<string opc, Intrinsic IntID>
232 : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2,
234 !strconcat("$dst = ", !strconcat(opc ,
235 "($src1, or($src2, $src3)")),
236 [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2,
239 /********************************************************************
241 *********************************************************************/
243 // ALU32 / PRED / Conditional Shift Halfword.
244 // ALU32 / PRED / Conditional Sign Extend.
245 // ALU32 / PRED / Conditional Zero Extend.
246 // ALU32 / PRED / Compare.
247 def Hexagon_C4_cmpltei : qi_neg_ALU32_sis10 <"cmp.gt", int_hexagon_C4_cmpltei>;
248 def Hexagon_C4_cmplte : qi_neg_ALU32_sisi <"cmp.gt", int_hexagon_C4_cmplte>;
249 def Hexagon_C4_cmplteu : qi_neg_ALU32_sisi <"cmp.gtu",int_hexagon_C4_cmplteu>;
251 def: T_RI_pat<C4_cmpneqi, int_hexagon_C4_cmpneqi>;
252 def: T_RI_pat<C4_cmpltei, int_hexagon_C4_cmpltei>;
253 def: T_RI_pat<C4_cmplteui, int_hexagon_C4_cmplteui>;
256 /********************************************************************
258 *********************************************************************/
260 // CR / Corner Detection Acceleration.
261 def Hexagon_C4_fastcorner9:
262 qi_SInst_qiqi<"fastcorner9", int_hexagon_C4_fastcorner9>;
263 def Hexagon_C4_fastcorner9_not:
264 qi_neg_SInst_qiqi<"fastcorner9",int_hexagon_C4_fastcorner9_not>;
266 // CR / Logical Operations On Predicates.
267 def Hexagon_C4_and_andn:
268 qi_SInst_qi_andqiqi_neg <"and", int_hexagon_C4_and_andn>;
269 def Hexagon_C4_and_and:
270 qi_SInst_qi_andqiqi <"and", int_hexagon_C4_and_and>;
271 def Hexagon_C4_and_orn:
272 qi_SInst_qi_orqiqi_neg <"and", int_hexagon_C4_and_orn>;
273 def Hexagon_C4_and_or:
274 qi_SInst_qi_orqiqi <"and", int_hexagon_C4_and_or>;
275 def Hexagon_C4_or_andn:
276 qi_SInst_qi_andqiqi_neg <"or", int_hexagon_C4_or_andn>;
277 def Hexagon_C4_or_and:
278 qi_SInst_qi_andqiqi <"or", int_hexagon_C4_or_and>;
279 def Hexagon_C4_or_orn:
280 qi_SInst_qi_orqiqi_neg <"or", int_hexagon_C4_or_orn>;
281 def Hexagon_C4_or_or:
282 qi_SInst_qi_orqiqi <"or", int_hexagon_C4_or_or>;