lib/Target/Hexagon/HexagonIntrinsics.td

   1 //===-- HexagonIntrinsics.td - Instruction intrinsics ------*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 // This is populated based on the following specs:
  10 // Hexagon V2 Architecture
  11 // Application-Level Specification
  12 // 80-V9418-8 Rev. B
  13 // March 4, 2008
  14 //===----------------------------------------------------------------------===//
  15
  16 class T_RR_pat <InstHexagon MI, Intrinsic IntID>
  17   : Pat <(IntID I32:$Rs, I32:$Rt),
  18          (MI I32:$Rs, I32:$Rt)>;
  19
  20 class T_RRR_pat <InstHexagon MI, Intrinsic IntID>
  21   : Pat <(IntID I32:$Rs, I32:$Rt, I32:$Ru),
  22          (MI I32:$Rs, I32:$Rt, I32:$Ru)>;
  23
  24 class T_PRR_pat <InstHexagon MI, Intrinsic IntID>
  25   : Pat <(IntID I64:$Rs, I32:$Rt, I32:$Ru),
  26          (MI DoubleRegs:$Rs, I32:$Rt, I32:$Ru)>;
  27
  28 //===----------------------------------------------------------------------===//
  29 // MPYS / Multipy signed/unsigned halfwords
  30 //Rd=mpy[u](Rs.[H|L],Rt.[H|L])[:<<1][:rnd][:sat]
  31 //===----------------------------------------------------------------------===//
  32
  33 def : T_RR_pat <M2_mpy_ll_s1, int_hexagon_M2_mpy_ll_s1>;
  34 def : T_RR_pat <M2_mpy_ll_s0, int_hexagon_M2_mpy_ll_s0>;
  35 def : T_RR_pat <M2_mpy_lh_s1, int_hexagon_M2_mpy_lh_s1>;
  36 def : T_RR_pat <M2_mpy_lh_s0, int_hexagon_M2_mpy_lh_s0>;
  37 def : T_RR_pat <M2_mpy_hl_s1, int_hexagon_M2_mpy_hl_s1>;
  38 def : T_RR_pat <M2_mpy_hl_s0, int_hexagon_M2_mpy_hl_s0>;
  39 def : T_RR_pat <M2_mpy_hh_s1, int_hexagon_M2_mpy_hh_s1>;
  40 def : T_RR_pat <M2_mpy_hh_s0, int_hexagon_M2_mpy_hh_s0>;
  41
  42 def : T_RR_pat <M2_mpyu_ll_s1, int_hexagon_M2_mpyu_ll_s1>;
  43 def : T_RR_pat <M2_mpyu_ll_s0, int_hexagon_M2_mpyu_ll_s0>;
  44 def : T_RR_pat <M2_mpyu_lh_s1, int_hexagon_M2_mpyu_lh_s1>;
  45 def : T_RR_pat <M2_mpyu_lh_s0, int_hexagon_M2_mpyu_lh_s0>;
  46 def : T_RR_pat <M2_mpyu_hl_s1, int_hexagon_M2_mpyu_hl_s1>;
  47 def : T_RR_pat <M2_mpyu_hl_s0, int_hexagon_M2_mpyu_hl_s0>;
  48 def : T_RR_pat <M2_mpyu_hh_s1, int_hexagon_M2_mpyu_hh_s1>;
  49 def : T_RR_pat <M2_mpyu_hh_s0, int_hexagon_M2_mpyu_hh_s0>;
  50
  51 def : T_RR_pat <M2_mpy_sat_ll_s1, int_hexagon_M2_mpy_sat_ll_s1>;
  52 def : T_RR_pat <M2_mpy_sat_ll_s0, int_hexagon_M2_mpy_sat_ll_s0>;
  53 def : T_RR_pat <M2_mpy_sat_lh_s1, int_hexagon_M2_mpy_sat_lh_s1>;
  54 def : T_RR_pat <M2_mpy_sat_lh_s0, int_hexagon_M2_mpy_sat_lh_s0>;
  55 def : T_RR_pat <M2_mpy_sat_hl_s1, int_hexagon_M2_mpy_sat_hl_s1>;
  56 def : T_RR_pat <M2_mpy_sat_hl_s0, int_hexagon_M2_mpy_sat_hl_s0>;
  57 def : T_RR_pat <M2_mpy_sat_hh_s1, int_hexagon_M2_mpy_sat_hh_s1>;
  58 def : T_RR_pat <M2_mpy_sat_hh_s0, int_hexagon_M2_mpy_sat_hh_s0>;
  59
  60 def : T_RR_pat <M2_mpy_rnd_ll_s1, int_hexagon_M2_mpy_rnd_ll_s1>;
  61 def : T_RR_pat <M2_mpy_rnd_ll_s0, int_hexagon_M2_mpy_rnd_ll_s0>;
  62 def : T_RR_pat <M2_mpy_rnd_lh_s1, int_hexagon_M2_mpy_rnd_lh_s1>;
  63 def : T_RR_pat <M2_mpy_rnd_lh_s0, int_hexagon_M2_mpy_rnd_lh_s0>;
  64 def : T_RR_pat <M2_mpy_rnd_hl_s1, int_hexagon_M2_mpy_rnd_hl_s1>;
  65 def : T_RR_pat <M2_mpy_rnd_hl_s0, int_hexagon_M2_mpy_rnd_hl_s0>;
  66 def : T_RR_pat <M2_mpy_rnd_hh_s1, int_hexagon_M2_mpy_rnd_hh_s1>;
  67 def : T_RR_pat <M2_mpy_rnd_hh_s0, int_hexagon_M2_mpy_rnd_hh_s0>;
  68
  69 def : T_RR_pat <M2_mpy_sat_rnd_ll_s1, int_hexagon_M2_mpy_sat_rnd_ll_s1>;
  70 def : T_RR_pat <M2_mpy_sat_rnd_ll_s0, int_hexagon_M2_mpy_sat_rnd_ll_s0>;
  71 def : T_RR_pat <M2_mpy_sat_rnd_lh_s1, int_hexagon_M2_mpy_sat_rnd_lh_s1>;
  72 def : T_RR_pat <M2_mpy_sat_rnd_lh_s0, int_hexagon_M2_mpy_sat_rnd_lh_s0>;
  73 def : T_RR_pat <M2_mpy_sat_rnd_hl_s1, int_hexagon_M2_mpy_sat_rnd_hl_s1>;
  74 def : T_RR_pat <M2_mpy_sat_rnd_hl_s0, int_hexagon_M2_mpy_sat_rnd_hl_s0>;
  75 def : T_RR_pat <M2_mpy_sat_rnd_hh_s1, int_hexagon_M2_mpy_sat_rnd_hh_s1>;
  76 def : T_RR_pat <M2_mpy_sat_rnd_hh_s0, int_hexagon_M2_mpy_sat_rnd_hh_s0>;
  77
  78
  79 //===----------------------------------------------------------------------===//
  80 // MPYS / Multipy signed/unsigned halfwords and add/subtract the
  81 // result from the accumulator.
  82 //Rx [-+]= mpy[u](Rs.[H|L],Rt.[H|L])[:<<1][:sat]
  83 //===----------------------------------------------------------------------===//
  84
  85 def : T_RRR_pat <M2_mpy_acc_ll_s1, int_hexagon_M2_mpy_acc_ll_s1>;
  86 def : T_RRR_pat <M2_mpy_acc_ll_s0, int_hexagon_M2_mpy_acc_ll_s0>;
  87 def : T_RRR_pat <M2_mpy_acc_lh_s1, int_hexagon_M2_mpy_acc_lh_s1>;
  88 def : T_RRR_pat <M2_mpy_acc_lh_s0, int_hexagon_M2_mpy_acc_lh_s0>;
  89 def : T_RRR_pat <M2_mpy_acc_hl_s1, int_hexagon_M2_mpy_acc_hl_s1>;
  90 def : T_RRR_pat <M2_mpy_acc_hl_s0, int_hexagon_M2_mpy_acc_hl_s0>;
  91 def : T_RRR_pat <M2_mpy_acc_hh_s1, int_hexagon_M2_mpy_acc_hh_s1>;
  92 def : T_RRR_pat <M2_mpy_acc_hh_s0, int_hexagon_M2_mpy_acc_hh_s0>;
  93
  94 def : T_RRR_pat <M2_mpyu_acc_ll_s1, int_hexagon_M2_mpyu_acc_ll_s1>;
  95 def : T_RRR_pat <M2_mpyu_acc_ll_s0, int_hexagon_M2_mpyu_acc_ll_s0>;
  96 def : T_RRR_pat <M2_mpyu_acc_lh_s1, int_hexagon_M2_mpyu_acc_lh_s1>;
  97 def : T_RRR_pat <M2_mpyu_acc_lh_s0, int_hexagon_M2_mpyu_acc_lh_s0>;
  98 def : T_RRR_pat <M2_mpyu_acc_hl_s1, int_hexagon_M2_mpyu_acc_hl_s1>;
  99 def : T_RRR_pat <M2_mpyu_acc_hl_s0, int_hexagon_M2_mpyu_acc_hl_s0>;
 100 def : T_RRR_pat <M2_mpyu_acc_hh_s1, int_hexagon_M2_mpyu_acc_hh_s1>;
 101 def : T_RRR_pat <M2_mpyu_acc_hh_s0, int_hexagon_M2_mpyu_acc_hh_s0>;
 102
 103 def : T_RRR_pat <M2_mpy_nac_ll_s1, int_hexagon_M2_mpy_nac_ll_s1>;
 104 def : T_RRR_pat <M2_mpy_nac_ll_s0, int_hexagon_M2_mpy_nac_ll_s0>;
 105 def : T_RRR_pat <M2_mpy_nac_lh_s1, int_hexagon_M2_mpy_nac_lh_s1>;
 106 def : T_RRR_pat <M2_mpy_nac_lh_s0, int_hexagon_M2_mpy_nac_lh_s0>;
 107 def : T_RRR_pat <M2_mpy_nac_hl_s1, int_hexagon_M2_mpy_nac_hl_s1>;
 108 def : T_RRR_pat <M2_mpy_nac_hl_s0, int_hexagon_M2_mpy_nac_hl_s0>;
 109 def : T_RRR_pat <M2_mpy_nac_hh_s1, int_hexagon_M2_mpy_nac_hh_s1>;
 110 def : T_RRR_pat <M2_mpy_nac_hh_s0, int_hexagon_M2_mpy_nac_hh_s0>;
 111
 112 def : T_RRR_pat <M2_mpyu_nac_ll_s1, int_hexagon_M2_mpyu_nac_ll_s1>;
 113 def : T_RRR_pat <M2_mpyu_nac_ll_s0, int_hexagon_M2_mpyu_nac_ll_s0>;
 114 def : T_RRR_pat <M2_mpyu_nac_lh_s1, int_hexagon_M2_mpyu_nac_lh_s1>;
 115 def : T_RRR_pat <M2_mpyu_nac_lh_s0, int_hexagon_M2_mpyu_nac_lh_s0>;
 116 def : T_RRR_pat <M2_mpyu_nac_hl_s1, int_hexagon_M2_mpyu_nac_hl_s1>;
 117 def : T_RRR_pat <M2_mpyu_nac_hl_s0, int_hexagon_M2_mpyu_nac_hl_s0>;
 118 def : T_RRR_pat <M2_mpyu_nac_hh_s1, int_hexagon_M2_mpyu_nac_hh_s1>;
 119 def : T_RRR_pat <M2_mpyu_nac_hh_s0, int_hexagon_M2_mpyu_nac_hh_s0>;
 120
 121 def : T_RRR_pat <M2_mpy_acc_sat_ll_s1, int_hexagon_M2_mpy_acc_sat_ll_s1>;
 122 def : T_RRR_pat <M2_mpy_acc_sat_ll_s0, int_hexagon_M2_mpy_acc_sat_ll_s0>;
 123 def : T_RRR_pat <M2_mpy_acc_sat_lh_s1, int_hexagon_M2_mpy_acc_sat_lh_s1>;
 124 def : T_RRR_pat <M2_mpy_acc_sat_lh_s0, int_hexagon_M2_mpy_acc_sat_lh_s0>;
 125 def : T_RRR_pat <M2_mpy_acc_sat_hl_s1, int_hexagon_M2_mpy_acc_sat_hl_s1>;
 126 def : T_RRR_pat <M2_mpy_acc_sat_hl_s0, int_hexagon_M2_mpy_acc_sat_hl_s0>;
 127 def : T_RRR_pat <M2_mpy_acc_sat_hh_s1, int_hexagon_M2_mpy_acc_sat_hh_s1>;
 128 def : T_RRR_pat <M2_mpy_acc_sat_hh_s0, int_hexagon_M2_mpy_acc_sat_hh_s0>;
 129
 130 def : T_RRR_pat <M2_mpy_nac_sat_ll_s1, int_hexagon_M2_mpy_nac_sat_ll_s1>;
 131 def : T_RRR_pat <M2_mpy_nac_sat_ll_s0, int_hexagon_M2_mpy_nac_sat_ll_s0>;
 132 def : T_RRR_pat <M2_mpy_nac_sat_lh_s1, int_hexagon_M2_mpy_nac_sat_lh_s1>;
 133 def : T_RRR_pat <M2_mpy_nac_sat_lh_s0, int_hexagon_M2_mpy_nac_sat_lh_s0>;
 134 def : T_RRR_pat <M2_mpy_nac_sat_hl_s1, int_hexagon_M2_mpy_nac_sat_hl_s1>;
 135 def : T_RRR_pat <M2_mpy_nac_sat_hl_s0, int_hexagon_M2_mpy_nac_sat_hl_s0>;
 136 def : T_RRR_pat <M2_mpy_nac_sat_hh_s1, int_hexagon_M2_mpy_nac_sat_hh_s1>;
 137 def : T_RRR_pat <M2_mpy_nac_sat_hh_s0, int_hexagon_M2_mpy_nac_sat_hh_s0>;
 138
 139
 140 //===----------------------------------------------------------------------===//
 141 // Multiply signed/unsigned halfwords with and without saturation and rounding
 142 // into a 64-bits destination register.
 143 //===----------------------------------------------------------------------===//
 144
 145 def : T_RR_pat <M2_mpyd_hh_s0, int_hexagon_M2_mpyd_hh_s0>;
 146 def : T_RR_pat <M2_mpyd_hl_s0, int_hexagon_M2_mpyd_hl_s0>;
 147 def : T_RR_pat <M2_mpyd_lh_s0, int_hexagon_M2_mpyd_lh_s0>;
 148 def : T_RR_pat <M2_mpyd_ll_s0, int_hexagon_M2_mpyd_ll_s0>;
 149 def : T_RR_pat <M2_mpyd_hh_s1, int_hexagon_M2_mpyd_hh_s1>;
 150 def : T_RR_pat <M2_mpyd_hl_s1, int_hexagon_M2_mpyd_hl_s1>;
 151 def : T_RR_pat <M2_mpyd_lh_s1, int_hexagon_M2_mpyd_lh_s1>;
 152 def : T_RR_pat <M2_mpyd_ll_s1, int_hexagon_M2_mpyd_ll_s1>;
 153
 154 def : T_RR_pat <M2_mpyd_rnd_hh_s0, int_hexagon_M2_mpyd_rnd_hh_s0>;
 155 def : T_RR_pat <M2_mpyd_rnd_hl_s0, int_hexagon_M2_mpyd_rnd_hl_s0>;
 156 def : T_RR_pat <M2_mpyd_rnd_lh_s0, int_hexagon_M2_mpyd_rnd_lh_s0>;
 157 def : T_RR_pat <M2_mpyd_rnd_ll_s0, int_hexagon_M2_mpyd_rnd_ll_s0>;
 158 def : T_RR_pat <M2_mpyd_rnd_hh_s1, int_hexagon_M2_mpyd_rnd_hh_s1>;
 159 def : T_RR_pat <M2_mpyd_rnd_hl_s1, int_hexagon_M2_mpyd_rnd_hl_s1>;
 160 def : T_RR_pat <M2_mpyd_rnd_lh_s1, int_hexagon_M2_mpyd_rnd_lh_s1>;
 161 def : T_RR_pat <M2_mpyd_rnd_ll_s1, int_hexagon_M2_mpyd_rnd_ll_s1>;
 162
 163 def : T_RR_pat <M2_mpyud_hh_s0, int_hexagon_M2_mpyud_hh_s0>;
 164 def : T_RR_pat <M2_mpyud_hl_s0, int_hexagon_M2_mpyud_hl_s0>;
 165 def : T_RR_pat <M2_mpyud_lh_s0, int_hexagon_M2_mpyud_lh_s0>;
 166 def : T_RR_pat <M2_mpyud_ll_s0, int_hexagon_M2_mpyud_ll_s0>;
 167 def : T_RR_pat <M2_mpyud_hh_s1, int_hexagon_M2_mpyud_hh_s1>;
 168 def : T_RR_pat <M2_mpyud_hl_s1, int_hexagon_M2_mpyud_hl_s1>;
 169 def : T_RR_pat <M2_mpyud_lh_s1, int_hexagon_M2_mpyud_lh_s1>;
 170 def : T_RR_pat <M2_mpyud_ll_s1, int_hexagon_M2_mpyud_ll_s1>;
 171
 172 //===----------------------------------------------------------------------===//
 173 // MPYS / Multipy signed/unsigned halfwords and add/subtract the
 174 // result from the 64-bit destination register.
 175 //Rxx [-+]= mpy[u](Rs.[H|L],Rt.[H|L])[:<<1][:sat]
 176 //===----------------------------------------------------------------------===//
 177
 178 def : T_PRR_pat <M2_mpyd_acc_hh_s0, int_hexagon_M2_mpyd_acc_hh_s0>;
 179 def : T_PRR_pat <M2_mpyd_acc_hl_s0, int_hexagon_M2_mpyd_acc_hl_s0>;
 180 def : T_PRR_pat <M2_mpyd_acc_lh_s0, int_hexagon_M2_mpyd_acc_lh_s0>;
 181 def : T_PRR_pat <M2_mpyd_acc_ll_s0, int_hexagon_M2_mpyd_acc_ll_s0>;
 182
 183 def : T_PRR_pat <M2_mpyd_acc_hh_s1, int_hexagon_M2_mpyd_acc_hh_s1>;
 184 def : T_PRR_pat <M2_mpyd_acc_hl_s1, int_hexagon_M2_mpyd_acc_hl_s1>;
 185 def : T_PRR_pat <M2_mpyd_acc_lh_s1, int_hexagon_M2_mpyd_acc_lh_s1>;
 186 def : T_PRR_pat <M2_mpyd_acc_ll_s1, int_hexagon_M2_mpyd_acc_ll_s1>;
 187
 188 def : T_PRR_pat <M2_mpyd_nac_hh_s0, int_hexagon_M2_mpyd_nac_hh_s0>;
 189 def : T_PRR_pat <M2_mpyd_nac_hl_s0, int_hexagon_M2_mpyd_nac_hl_s0>;
 190 def : T_PRR_pat <M2_mpyd_nac_lh_s0, int_hexagon_M2_mpyd_nac_lh_s0>;
 191 def : T_PRR_pat <M2_mpyd_nac_ll_s0, int_hexagon_M2_mpyd_nac_ll_s0>;
 192
 193 def : T_PRR_pat <M2_mpyd_nac_hh_s1, int_hexagon_M2_mpyd_nac_hh_s1>;
 194 def : T_PRR_pat <M2_mpyd_nac_hl_s1, int_hexagon_M2_mpyd_nac_hl_s1>;
 195 def : T_PRR_pat <M2_mpyd_nac_lh_s1, int_hexagon_M2_mpyd_nac_lh_s1>;
 196 def : T_PRR_pat <M2_mpyd_nac_ll_s1, int_hexagon_M2_mpyd_nac_ll_s1>;
 197
 198 def : T_PRR_pat <M2_mpyud_acc_hh_s0, int_hexagon_M2_mpyud_acc_hh_s0>;
 199 def : T_PRR_pat <M2_mpyud_acc_hl_s0, int_hexagon_M2_mpyud_acc_hl_s0>;
 200 def : T_PRR_pat <M2_mpyud_acc_lh_s0, int_hexagon_M2_mpyud_acc_lh_s0>;
 201 def : T_PRR_pat <M2_mpyud_acc_ll_s0, int_hexagon_M2_mpyud_acc_ll_s0>;
 202
 203 def : T_PRR_pat <M2_mpyud_acc_hh_s1, int_hexagon_M2_mpyud_acc_hh_s1>;
 204 def : T_PRR_pat <M2_mpyud_acc_hl_s1, int_hexagon_M2_mpyud_acc_hl_s1>;
 205 def : T_PRR_pat <M2_mpyud_acc_lh_s1, int_hexagon_M2_mpyud_acc_lh_s1>;
 206 def : T_PRR_pat <M2_mpyud_acc_ll_s1, int_hexagon_M2_mpyud_acc_ll_s1>;
 207
 208 def : T_PRR_pat <M2_mpyud_nac_hh_s0, int_hexagon_M2_mpyud_nac_hh_s0>;
 209 def : T_PRR_pat <M2_mpyud_nac_hl_s0, int_hexagon_M2_mpyud_nac_hl_s0>;
 210 def : T_PRR_pat <M2_mpyud_nac_lh_s0, int_hexagon_M2_mpyud_nac_lh_s0>;
 211 def : T_PRR_pat <M2_mpyud_nac_ll_s0, int_hexagon_M2_mpyud_nac_ll_s0>;
 212
 213 def : T_PRR_pat <M2_mpyud_nac_hh_s1, int_hexagon_M2_mpyud_nac_hh_s1>;
 214 def : T_PRR_pat <M2_mpyud_nac_hl_s1, int_hexagon_M2_mpyud_nac_hl_s1>;
 215 def : T_PRR_pat <M2_mpyud_nac_lh_s1, int_hexagon_M2_mpyud_nac_lh_s1>;
 216 def : T_PRR_pat <M2_mpyud_nac_ll_s1, int_hexagon_M2_mpyud_nac_ll_s1>;
 217
 218 //
 219 // ALU 32 types.
 220 //
 221
 222 class qi_ALU32_sisi<string opc, Intrinsic IntID>
 223   : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 224              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
 225              [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 226
 227 class qi_ALU32_sis10<string opc, Intrinsic IntID>
 228   : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, s10Imm:$src2),
 229              !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
 230              [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
 231
 232 class qi_ALU32_sis8<string opc, Intrinsic IntID>
 233   : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, s8Imm:$src2),
 234              !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
 235              [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
 236
 237 class qi_ALU32_siu8<string opc, Intrinsic IntID>
 238   : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, u8Imm:$src2),
 239              !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
 240              [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
 241
 242 class qi_ALU32_siu9<string opc, Intrinsic IntID>
 243   : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, u9Imm:$src2),
 244              !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
 245              [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
 246
 247 class si_ALU32_qisisi<string opc, Intrinsic IntID>
 248   : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2,
 249                                       IntRegs:$src3),
 250              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2, $src3)")),
 251              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2,
 252                                         IntRegs:$src3))]>;
 253
 254 class si_ALU32_qis8si<string opc, Intrinsic IntID>
 255   : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, s8Imm:$src2,
 256                                        IntRegs:$src3),
 257              !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2, $src3)")),
 258              [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2,
 259                                         IntRegs:$src3))]>;
 260
 261 class si_ALU32_qisis8<string opc, Intrinsic IntID>
 262   : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2,
 263                                        s8Imm:$src3),
 264              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2, #$src3)")),
 265              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2,
 266                                         imm:$src3))]>;
 267
 268 class si_ALU32_qis8s8<string opc, Intrinsic IntID>
 269   : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, s8Imm:$src2, s8Imm:$src3),
 270              !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2, #$src3)")),
 271              [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2, imm:$src3))]>;
 272
 273 class si_ALU32_sisi<string opc, Intrinsic IntID>
 274   : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 275              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
 276              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 277
 278 class si_ALU32_sisi_sat<string opc, Intrinsic IntID>
 279   : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 280              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):sat")),
 281              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 282
 283 class si_ALU32_sisi_rnd<string opc, Intrinsic IntID>
 284   : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 285              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):rnd")),
 286              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 287
 288 class si_ALU32_sis16<string opc, Intrinsic IntID>
 289   : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, s16Imm:$src2),
 290              !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
 291              [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
 292
 293 class si_ALU32_sis10<string opc, Intrinsic IntID>
 294   : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, s10Imm:$src2),
 295              !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
 296              [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
 297
 298 class si_ALU32_s10si<string opc, Intrinsic IntID>
 299   : ALU32_rr<(outs IntRegs:$dst), (ins s10Imm:$src1, IntRegs:$src2),
 300              !strconcat("$dst = ", !strconcat(opc , "(#$src1, $src2)")),
 301              [(set IntRegs:$dst, (IntID imm:$src1, IntRegs:$src2))]>;
 302
 303 class si_lo_ALU32_siu16<string opc, Intrinsic IntID>
 304   : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u16Imm:$src2),
 305              !strconcat("$dst.l = ", !strconcat(opc , "#$src2")),
 306              [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
 307
 308 class si_hi_ALU32_siu16<string opc, Intrinsic IntID>
 309   : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u16Imm:$src2),
 310              !strconcat("$dst.h = ", !strconcat(opc , "#$src2")),
 311              [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
 312
 313 class si_ALU32_s16<string opc, Intrinsic IntID>
 314   : ALU32_rr<(outs IntRegs:$dst), (ins s16Imm:$src1),
 315              !strconcat("$dst = ", !strconcat(opc , "#$src1")),
 316              [(set IntRegs:$dst, (IntID imm:$src1))]>;
 317
 318 class di_ALU32_s8<string opc, Intrinsic IntID>
 319   : ALU32_rr<(outs DoubleRegs:$dst), (ins s8Imm:$src1),
 320              !strconcat("$dst = ", !strconcat(opc , "#$src1")),
 321              [(set DoubleRegs:$dst, (IntID imm:$src1))]>;
 322
 323 class di_ALU64_di<string opc, Intrinsic IntID>
 324   : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src),
 325              !strconcat("$dst = ", !strconcat(opc , "$src")),
 326              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src))]>;
 327
 328 class si_ALU32_si<string opc, Intrinsic IntID>
 329   : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src),
 330              !strconcat("$dst = ", !strconcat(opc , "($src)")),
 331              [(set IntRegs:$dst, (IntID IntRegs:$src))]>;
 332
 333 class si_ALU32_si_tfr<string opc, Intrinsic IntID>
 334   : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src),
 335              !strconcat("$dst = ", !strconcat(opc , "$src")),
 336              [(set IntRegs:$dst, (IntID IntRegs:$src))]>;
 337
 338 //
 339 // ALU 64 types.
 340 //
 341
 342 class si_ALU64_si_sat<string opc, Intrinsic IntID>
 343   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src),
 344              !strconcat("$dst = ", !strconcat(opc , "($src):sat")),
 345              [(set IntRegs:$dst, (IntID IntRegs:$src))]>;
 346
 347 class si_ALU64_didi<string opc, Intrinsic IntID>
 348   : ALU64_rr<(outs IntRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
 349              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
 350              [(set IntRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
 351
 352 class di_ALU64_sidi<string opc, Intrinsic IntID>
 353   : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src1, DoubleRegs:$src2),
 354              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
 355              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, DoubleRegs:$src2))]>;
 356
 357 class di_ALU64_didi<string opc, Intrinsic IntID>
 358   : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
 359              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
 360              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
 361                                            DoubleRegs:$src2))]>;
 362
 363 class di_ALU64_qididi<string opc, Intrinsic IntID>
 364   : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src1, DoubleRegs:$src2,
 365                                           DoubleRegs:$src3),
 366              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2, $src3)")),
 367              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, DoubleRegs:$src2,
 368                                            DoubleRegs:$src3))]>;
 369
 370 class di_ALU64_sisi<string opc, Intrinsic IntID>
 371   : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 372              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
 373              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 374
 375 class di_ALU64_didi_sat<string opc, Intrinsic IntID>
 376   : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
 377              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):sat")),
 378              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
 379                                            DoubleRegs:$src2))]>;
 380
 381 class di_ALU64_didi_rnd<string opc, Intrinsic IntID>
 382   : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
 383              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):rnd")),
 384              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
 385                                            DoubleRegs:$src2))]>;
 386
 387 class di_ALU64_didi_crnd<string opc, Intrinsic IntID>
 388   : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
 389              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):crnd")),
 390              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
 391                                            DoubleRegs:$src2))]>;
 392
 393 class di_ALU64_didi_rnd_sat<string opc, Intrinsic IntID>
 394   : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
 395              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):rnd:sat")),
 396              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
 397                                            DoubleRegs:$src2))]>;
 398
 399 class di_ALU64_didi_crnd_sat<string opc, Intrinsic IntID>
 400   : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
 401              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):crnd:sat")),
 402              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
 403                                            DoubleRegs:$src2))]>;
 404
 405 class qi_ALU64_didi<string opc, Intrinsic IntID>
 406   : ALU64_rr<(outs PredRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
 407              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
 408              [(set PredRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
 409
 410 class si_ALU64_sisi<string opc, Intrinsic IntID>
 411   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 412              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
 413              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 414
 415 class si_ALU64_sisi_sat_lh<string opc, Intrinsic IntID>
 416   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 417              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H):sat")),
 418              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 419
 420 class si_ALU64_sisi_l16_sat_hh<string opc, Intrinsic IntID>
 421   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 422              !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.H):sat")),
 423              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 424
 425 class si_ALU64_sisi_l16_sat_lh<string opc, Intrinsic IntID>
 426   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 427              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H):sat")),
 428              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 429
 430 class si_ALU64_sisi_l16_sat_hl<string opc, Intrinsic IntID>
 431   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 432              !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.L):sat")),
 433              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 434
 435 class si_ALU64_sisi_l16_sat_ll<string opc, Intrinsic IntID>
 436   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 437              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L):sat")),
 438              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 439
 440 class si_ALU64_sisi_l16_hh<string opc, Intrinsic IntID>
 441   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 442              !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.H)")),
 443              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 444
 445 class si_ALU64_sisi_l16_hl<string opc, Intrinsic IntID>
 446   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 447              !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.L)")),
 448              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 449
 450 class si_ALU64_sisi_l16_lh<string opc, Intrinsic IntID>
 451   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 452              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H)")),
 453              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 454
 455 class si_ALU64_sisi_l16_ll<string opc, Intrinsic IntID>
 456   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 457              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L)")),
 458              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 459
 460 class si_ALU64_sisi_h16_sat_hh<string opc, Intrinsic IntID>
 461   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 462              !strconcat("$dst = ", !strconcat(opc ,
 463                                               "($src1.H, $src2.H):sat:<<16")),
 464              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 465
 466 class si_ALU64_sisi_h16_sat_lh<string opc, Intrinsic IntID>
 467   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 468              !strconcat("$dst = ", !strconcat(opc ,
 469                                               "($src1.L, $src2.H):sat:<<16")),
 470              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 471
 472 class si_ALU64_sisi_h16_sat_hl<string opc, Intrinsic IntID>
 473   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 474              !strconcat("$dst = ", !strconcat(opc ,
 475                                               "($src1.H, $src2.L):sat:<<16")),
 476              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 477
 478 class si_ALU64_sisi_h16_sat_ll<string opc, Intrinsic IntID>
 479   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 480              !strconcat("$dst = ", !strconcat(opc ,
 481                                               "($src1.L, $src2.L):sat:<<16")),
 482              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 483
 484 class si_ALU64_sisi_h16_hh<string opc, Intrinsic IntID>
 485   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 486              !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.H):<<16")),
 487              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 488
 489 class si_ALU64_sisi_h16_hl<string opc, Intrinsic IntID>
 490   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 491              !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.L):<<16")),
 492              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 493
 494 class si_ALU64_sisi_h16_lh<string opc, Intrinsic IntID>
 495   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 496              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H):<<16")),
 497              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 498
 499 class si_ALU64_sisi_h16_ll<string opc, Intrinsic IntID>
 500   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 501              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L):<<16")),
 502              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 503
 504 class si_ALU64_sisi_lh<string opc, Intrinsic IntID>
 505   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 506              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H)")),
 507              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 508
 509 class si_ALU64_sisi_ll<string opc, Intrinsic IntID>
 510   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 511              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L)")),
 512              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 513
 514 class si_ALU64_sisi_sat<string opc, Intrinsic IntID>
 515   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 516              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):sat")),
 517              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 518
 519 //
 520 // SInst classes.
 521 //
 522
 523 class qi_SInst_qi<string opc, Intrinsic IntID>
 524   : SInst<(outs PredRegs:$dst), (ins IntRegs:$src),
 525              !strconcat("$dst = ", !strconcat(opc , "($src)")),
 526              [(set PredRegs:$dst, (IntID IntRegs:$src))]>;
 527
 528 class qi_SInst_qi_pxfer<string opc, Intrinsic IntID>
 529   : SInst<(outs PredRegs:$dst), (ins IntRegs:$src),
 530              !strconcat("$dst = ", !strconcat(opc , "$src")),
 531              [(set PredRegs:$dst, (IntID IntRegs:$src))]>;
 532
 533 class qi_SInst_qiqi<string opc, Intrinsic IntID>
 534   : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 535              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
 536              [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 537
 538 class qi_SInst_qiqi_neg<string opc, Intrinsic IntID>
 539   : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 540              !strconcat("$dst = ", !strconcat(opc , "($src1, !$src2)")),
 541              [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 542
 543 class di_SInst_di<string opc, Intrinsic IntID>
 544   : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src),
 545              !strconcat("$dst = ", !strconcat(opc , "($src)")),
 546              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src))]>;
 547
 548 class di_SInst_di_sat<string opc, Intrinsic IntID>
 549   : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src),
 550              !strconcat("$dst = ", !strconcat(opc , "($src):sat")),
 551              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src))]>;
 552
 553 class si_SInst_di<string opc, Intrinsic IntID>
 554   : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src),
 555           !strconcat("$dst = ", !strconcat(opc , "($src)")),
 556           [(set IntRegs:$dst, (IntID DoubleRegs:$src))]>;
 557
 558 class si_SInst_di_sat<string opc, Intrinsic IntID>
 559   : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src),
 560           !strconcat("$dst = ", !strconcat(opc , "($src):sat")),
 561           [(set IntRegs:$dst, (IntID DoubleRegs:$src))]>;
 562
 563 class di_SInst_disi<string opc, Intrinsic IntID>
 564   : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
 565           !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
 566           [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, IntRegs:$src2))]>;
 567
 568 class di_SInst_didi<string opc, Intrinsic IntID>
 569   : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
 570           !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
 571           [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
 572
 573 class di_SInst_si<string opc, Intrinsic IntID>
 574   : SInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1),
 575           !strconcat("$dst = ", !strconcat(opc , "($src1)")),
 576           [(set DoubleRegs:$dst, (IntID IntRegs:$src1))]>;
 577
 578 class si_SInst_sisiu3<string opc, Intrinsic IntID>
 579   : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2, u3Imm:$src3),
 580           !strconcat("$dst = ", !strconcat(opc , "($src1, $src2, #$src3)")),
 581           [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2,
 582                                      imm:$src3))]>;
 583
 584 class si_SInst_diu5<string opc, Intrinsic IntID>
 585   : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, u5Imm:$src2),
 586           !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
 587           [(set IntRegs:$dst, (IntID DoubleRegs:$src1, imm:$src2))]>;
 588
 589 class si_SInst_disi<string opc, Intrinsic IntID>
 590   : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
 591           !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
 592           [(set IntRegs:$dst, (IntID DoubleRegs:$src1, IntRegs:$src2))]>;
 593
 594 class si_SInst_sidi<string opc, Intrinsic IntID>
 595   : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, DoubleRegs:$src2),
 596           !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
 597           [(set IntRegs:$dst, (IntID IntRegs:$src1, DoubleRegs:$src2))]>;
 598
 599 class di_SInst_disisi<string opc, Intrinsic IntID>
 600   : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2,
 601                                        IntRegs:$src3),
 602           !strconcat("$dst = ", !strconcat(opc , "($src1, $src2, $src3)")),
 603           [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, IntRegs:$src2,
 604                                         IntRegs:$src3))]>;
 605
 606 class di_SInst_sisi<string opc, Intrinsic IntID>
 607   : SInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 608           !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
 609           [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 610
 611 class qi_SInst_siu5<string opc, Intrinsic IntID>
 612   : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
 613           !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
 614           [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
 615
 616 class qi_SInst_siu6<string opc, Intrinsic IntID>
 617   : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, u6Imm:$src2),
 618           !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
 619           [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
 620
 621 class qi_SInst_sisi<string opc, Intrinsic IntID>
 622   : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 623           !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
 624           [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 625
 626 class si_SInst_si<string opc, Intrinsic IntID>
 627   : SInst<(outs IntRegs:$dst), (ins IntRegs:$src),
 628           !strconcat("$dst = ", !strconcat(opc , "($src)")),
 629           [(set IntRegs:$dst, (IntID IntRegs:$src))]>;
 630
 631 class si_SInst_si_sat<string opc, Intrinsic IntID>
 632   : SInst<(outs IntRegs:$dst), (ins IntRegs:$src),
 633           !strconcat("$dst = ", !strconcat(opc , "($src):sat")),
 634           [(set IntRegs:$dst, (IntID IntRegs:$src))]>;
 635
 636 class di_SInst_qi<string opc, Intrinsic IntID>
 637   : SInst<(outs DoubleRegs:$dst), (ins IntRegs:$src),
 638           !strconcat("$dst = ", !strconcat(opc , "($src)")),
 639           [(set DoubleRegs:$dst, (IntID IntRegs:$src))]>;
 640
 641 class si_SInst_qi<string opc, Intrinsic IntID>
 642   : SInst<(outs IntRegs:$dst), (ins IntRegs:$src),
 643           !strconcat("$dst = ", !strconcat(opc , "$src")),
 644           [(set IntRegs:$dst, (IntID IntRegs:$src))]>;
 645
 646 class si_SInst_qiqi<string opc, Intrinsic IntID>
 647   : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 648           !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
 649           [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 650
 651 class qi_SInst_si<string opc, Intrinsic IntID>
 652   : SInst<(outs PredRegs:$dst), (ins IntRegs:$src),
 653           !strconcat("$dst = ", !strconcat(opc , "$src")),
 654           [(set PredRegs:$dst, (IntID IntRegs:$src))]>;
 655
 656 class si_SInst_sisi<string opc, Intrinsic IntID>
 657   : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 658           !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
 659           [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 660
 661 class di_SInst_diu6<string opc, Intrinsic IntID>
 662   : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u6Imm:$src2),
 663           !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
 664           [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, imm:$src2))]>;
 665
 666 class si_SInst_siu5<string opc, Intrinsic IntID>
 667   : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
 668           !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
 669           [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
 670
 671 class si_SInst_siu5_rnd<string opc, Intrinsic IntID>
 672   : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
 673           !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2):rnd")),
 674           [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
 675
 676 class si_SInst_siu5u5<string opc, Intrinsic IntID>
 677   : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2, u5Imm:$src3),
 678           !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2, #$src3)")),
 679           [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2, imm:$src3))]>;
 680
 681 class si_SInst_sisisi_acc<string opc, Intrinsic IntID>
 682   : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
 683                                         IntRegs:$src2),
 684               !strconcat("$dst += ", !strconcat(opc , "($src1, $src2)")),
 685               [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
 686                                          IntRegs:$src2))],
 687               "$dst2 = $dst">;
 688
 689 class si_SInst_sisisi_nac<string opc, Intrinsic IntID>
 690   : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
 691                                         IntRegs:$src2),
 692               !strconcat("$dst -= ", !strconcat(opc , "($src1, $src2)")),
 693               [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
 694                                          IntRegs:$src2))],
 695               "$dst2 = $dst">;
 696
 697 class di_SInst_didisi_acc<string opc, Intrinsic IntID>
 698   : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
 699                                            IntRegs:$src2),
 700                !strconcat("$dst += ", !strconcat(opc , "($src1, $src2)")),
 701                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
 702                                              DoubleRegs:$src1,
 703                                              IntRegs:$src2))],
 704                "$dst2 = $dst">;
 705
 706 class di_SInst_didisi_nac<string opc, Intrinsic IntID>
 707   : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
 708                                            IntRegs:$src2),
 709           !strconcat("$dst -= ", !strconcat(opc , "($src1, $src2)")),
 710           [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
 711                                         DoubleRegs:$src1, IntRegs:$src2))],
 712           "$dst2 = $dst">;
 713
 714 class si_SInst_sisiu5u5<string opc, Intrinsic IntID>
 715   : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
 716                                         u5Imm:$src2, u5Imm:$src3),
 717               !strconcat("$dst = ", !strconcat(opc ,
 718                                                "($src1, #$src2, #$src3)")),
 719               [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
 720                                          imm:$src2, imm:$src3))],
 721               "$dst2 = $dst">;
 722
 723 class si_SInst_sisidi<string opc, Intrinsic IntID>
 724   : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
 725                                         DoubleRegs:$src2),
 726               !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
 727               [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
 728                                          DoubleRegs:$src2))],
 729               "$dst2 = $dst">;
 730
 731 class di_SInst_didiu6u6<string opc, Intrinsic IntID>
 732   : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
 733                                            u6Imm:$src2, u6Imm:$src3),
 734               !strconcat("$dst = ", !strconcat(opc ,
 735                                                "($src1, #$src2, #$src3)")),
 736               [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, DoubleRegs:$src1,
 737                                             imm:$src2, imm:$src3))],
 738               "$dst2 = $dst">;
 739
 740 class di_SInst_dididi<string opc, Intrinsic IntID>
 741   : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
 742                                            DoubleRegs:$src2),
 743               !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
 744               [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
 745                                             DoubleRegs:$src1,
 746                                             DoubleRegs:$src2))],
 747               "$dst2 = $dst">;
 748
 749 class di_SInst_diu6u6<string opc, Intrinsic IntID>
 750   : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u6Imm:$src2,
 751                                        u6Imm:$src3),
 752           !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2, #$src3)")),
 753           [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, imm:$src2,
 754                                         imm:$src3))]>;
 755
 756 class di_SInst_didiqi<string opc, Intrinsic IntID>
 757   : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2,
 758                                        IntRegs:$src3),
 759           !strconcat("$dst = ", !strconcat(opc , "($src1, $src2, $src3)")),
 760           [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2,
 761                                         IntRegs:$src3))]>;
 762
 763 class di_SInst_didiu3<string opc, Intrinsic IntID>
 764   : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2,
 765                                        u3Imm:$src3),
 766           !strconcat("$dst = ", !strconcat(opc , "($src1, $src2, #$src3)")),
 767           [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2,
 768                                         imm:$src3))]>;
 769
 770 class di_SInst_didisi_or<string opc, Intrinsic IntID>
 771   : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
 772                                            IntRegs:$src2),
 773           !strconcat("$dst |= ", !strconcat(opc , "($src1, $src2)")),
 774           [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, DoubleRegs:$src1,
 775                                         IntRegs:$src2))],
 776           "$dst2 = $dst">;
 777
 778 class di_SInst_didisi_and<string opc, Intrinsic IntID>
 779   : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
 780                                            IntRegs:$src2),
 781           !strconcat("$dst &= ", !strconcat(opc , "($src1, $src2)")),
 782           [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, DoubleRegs:$src1,
 783                                         IntRegs:$src2))],
 784           "$dst2 = $dst">;
 785
 786 class di_SInst_didiu6_and<string opc, Intrinsic IntID>
 787   : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
 788                                            u6Imm:$src2),
 789           !strconcat("$dst &= ", !strconcat(opc , "($src1, #$src2)")),
 790           [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, DoubleRegs:$src1,
 791                                         imm:$src2))],
 792           "$dst2 = $dst">;
 793
 794 class di_SInst_didiu6_or<string opc, Intrinsic IntID>
 795   : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
 796                                            u6Imm:$src2),
 797           !strconcat("$dst |= ", !strconcat(opc , "($src1, #$src2)")),
 798           [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, DoubleRegs:$src1,
 799                                         imm:$src2))],
 800           "$dst2 = $dst">;
 801
 802 class di_SInst_didiu6_xor<string opc, Intrinsic IntID>
 803   : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
 804                                            u6Imm:$src2),
 805           !strconcat("$dst ^= ", !strconcat(opc , "($src1, #$src2)")),
 806           [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, DoubleRegs:$src1,
 807                                         imm:$src2))],
 808           "$dst2 = $dst">;
 809
 810 class si_SInst_sisisi_and<string opc, Intrinsic IntID>
 811   : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
 812                                         IntRegs:$src2),
 813               !strconcat("$dst &= ", !strconcat(opc , "($src1, $src2)")),
 814               [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
 815                                          IntRegs:$src2))],
 816               "$dst2 = $dst">;
 817
 818 class si_SInst_sisisi_or<string opc, Intrinsic IntID>
 819   : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
 820                                         IntRegs:$src2),
 821               !strconcat("$dst |= ", !strconcat(opc , "($src1, $src2)")),
 822               [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
 823                                          IntRegs:$src2))],
 824               "$dst2 = $dst">;
 825
 826
 827 class si_SInst_sisiu5_and<string opc, Intrinsic IntID>
 828   : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
 829                                         u5Imm:$src2),
 830               !strconcat("$dst &= ", !strconcat(opc , "($src1, #$src2)")),
 831               [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
 832                                          imm:$src2))],
 833               "$dst2 = $dst">;
 834
 835 class si_SInst_sisiu5_or<string opc, Intrinsic IntID>
 836   : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
 837                                         u5Imm:$src2),
 838               !strconcat("$dst |= ", !strconcat(opc , "($src1, #$src2)")),
 839               [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
 840                                          imm:$src2))],
 841               "$dst2 = $dst">;
 842
 843 class si_SInst_sisiu5_xor<string opc, Intrinsic IntID>
 844   : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
 845                                         u5Imm:$src2),
 846               !strconcat("$dst ^= ", !strconcat(opc , "($src1, #$src2)")),
 847               [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
 848                                          imm:$src2))],
 849               "$dst2 = $dst">;
 850
 851 class si_SInst_sisiu5_acc<string opc, Intrinsic IntID>
 852   : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
 853                                         u5Imm:$src2),
 854               !strconcat("$dst += ", !strconcat(opc , "($src1, #$src2)")),
 855               [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
 856                                          imm:$src2))],
 857               "$dst2 = $dst">;
 858
 859 class si_SInst_sisiu5_nac<string opc, Intrinsic IntID>
 860   : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
 861                                         u5Imm:$src2),
 862               !strconcat("$dst -= ", !strconcat(opc , "($src1, #$src2)")),
 863               [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
 864                                          imm:$src2))],
 865               "$dst2 = $dst">;
 866
 867 class di_SInst_didiu6_acc<string opc, Intrinsic IntID>
 868   : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
 869                                            u5Imm:$src2),
 870               !strconcat("$dst += ", !strconcat(opc , "($src1, #$src2)")),
 871               [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
 872                                             DoubleRegs:$src1, imm:$src2))],
 873               "$dst2 = $dst">;
 874
 875 class di_SInst_didiu6_nac<string opc, Intrinsic IntID>
 876   : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
 877                                            u5Imm:$src2),
 878               !strconcat("$dst -= ", !strconcat(opc , "($src1, #$src2)")),
 879               [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, DoubleRegs:$src1,
 880                                             imm:$src2))],
 881               "$dst2 = $dst">;
 882
 883
 884 //
 885 // MInst classes.
 886 //
 887
 888 class di_MInst_sisi_rnd_hh_s1<string opc, Intrinsic IntID>
 889   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 890                !strconcat("$dst = ", !strconcat(opc ,
 891                                                 "($src1.H, $src2.H):<<1:rnd")),
 892                [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 893
 894 class di_MInst_sisi_rnd_hh<string opc, Intrinsic IntID>
 895   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 896                !strconcat("$dst = ", !strconcat(opc ,
 897                                                 "($src1.H, $src2.H):rnd")),
 898                [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 899
 900 class di_MInst_sisi_rnd_hl_s1<string opc, Intrinsic IntID>
 901   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 902                !strconcat("$dst = ", !strconcat(opc ,
 903                                                 "($src1.H, $src2.L):<<1:rnd")),
 904                [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 905
 906 class di_MInst_sisi_rnd_hl<string opc, Intrinsic IntID>
 907   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 908                !strconcat("$dst = ", !strconcat(opc ,
 909                                                 "($src1.H, $src2.L):rnd")),
 910                [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 911
 912 class di_MInst_sisi_rnd_lh_s1<string opc, Intrinsic IntID>
 913   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 914                !strconcat("$dst = ", !strconcat(opc ,
 915                                                 "($src1.L, $src2.H):<<1:rnd")),
 916                [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 917
 918 class di_MInst_sisi_rnd_lh<string opc, Intrinsic IntID>
 919   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 920                !strconcat("$dst = ", !strconcat(opc ,
 921                                                 "($src1.L, $src2.H):rnd")),
 922                [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 923
 924 class di_MInst_sisi_rnd_ll_s1<string opc, Intrinsic IntID>
 925   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 926                !strconcat("$dst = ", !strconcat(opc ,
 927                                                 "($src1.L, $src2.L):<<1:rnd")),
 928                [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 929
 930 class di_MInst_sisi_rnd_ll<string opc, Intrinsic IntID>
 931   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 932                !strconcat("$dst = ", !strconcat(opc ,
 933                                                 "($src1.L, $src2.L):rnd")),
 934                [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 935
 936 class di_MInst_disisi_acc<string opc, Intrinsic IntID>
 937   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
 938                                            IntRegs:$src2),
 939              !strconcat("$dst += ", !strconcat(opc , "($src1, $src2)")),
 940              [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
 941                                            IntRegs:$src2))],
 942              "$dst2 = $dst">;
 943
 944 class di_MInst_disisi_nac<string opc, Intrinsic IntID>
 945   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
 946                                            IntRegs:$src2),
 947              !strconcat("$dst -= ", !strconcat(opc , "($src1, $src2)")),
 948              [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
 949                                            IntRegs:$src2))],
 950              "$dst2 = $dst">;
 951
 952 class di_MInst_disisi_acc_sat<string opc, Intrinsic IntID>
 953   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
 954                                            IntRegs:$src2),
 955              !strconcat("$dst += ", !strconcat(opc , "($src1, $src2):sat")),
 956              [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
 957                                            IntRegs:$src2))],
 958              "$dst2 = $dst">;
 959
 960 class di_MInst_disisi_nac_sat<string opc, Intrinsic IntID>
 961   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
 962                                            IntRegs:$src2),
 963              !strconcat("$dst -= ", !strconcat(opc , "($src1, $src2):sat")),
 964              [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
 965                                            IntRegs:$src2))],
 966              "$dst2 = $dst">;
 967
 968 class di_MInst_disisi_acc_sat_conj<string opc, Intrinsic IntID>
 969   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
 970                                            IntRegs:$src2),
 971              !strconcat("$dst += ", !strconcat(opc , "($src1, $src2*):sat")),
 972              [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
 973                                            IntRegs:$src2))],
 974              "$dst2 = $dst">;
 975
 976 class di_MInst_disisi_nac_sat_conj<string opc, Intrinsic IntID>
 977   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
 978                                            IntRegs:$src2),
 979              !strconcat("$dst -= ", !strconcat(opc , "($src1, $src2*):sat")),
 980              [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
 981                                            IntRegs:$src2))],
 982              "$dst2 = $dst">;
 983
 984 class di_MInst_disisi_nac_s1_sat<string opc, Intrinsic IntID>
 985   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
 986                                            IntRegs:$src2),
 987              !strconcat("$dst -= ", !strconcat(opc ,
 988                                                "($src1, $src2):<<1:sat")),
 989              [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
 990                                            IntRegs:$src2))],
 991              "$dst2 = $dst">;
 992
 993 class di_MInst_disisi_acc_s1_sat_conj<string opc, Intrinsic IntID>
 994   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
 995                                            IntRegs:$src2),
 996              !strconcat("$dst += ", !strconcat(opc ,
 997                                                "($src1, $src2*):<<1:sat")),
 998              [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
 999                                            IntRegs:$src2))],
1000              "$dst2 = $dst">;
1001
1002 class di_MInst_disisi_nac_s1_sat_conj<string opc, Intrinsic IntID>
1003   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1004                                            IntRegs:$src2),
1005              !strconcat("$dst -= ", !strconcat(opc ,
1006                                                "($src1, $src2*):<<1:sat")),
1007              [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1008                                            IntRegs:$src2))],
1009              "$dst2 = $dst">;
1010
1011 class di_MInst_s8s8<string opc, Intrinsic IntID>
1012   : MInst<(outs DoubleRegs:$dst), (ins s8Imm:$src1, s8Imm:$src2),
1013              !strconcat("$dst = ", !strconcat(opc , "(#$src1, #$src2)")),
1014              [(set DoubleRegs:$dst, (IntID imm:$src1, imm:$src2))]>;
1015
1016 class si_MInst_sis9<string opc, Intrinsic IntID>
1017   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, s9Imm:$src2),
1018              !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
1019              [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
1020
1021 class si_MInst_sisi<string opc, Intrinsic IntID>
1022   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1023              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
1024              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1025
1026 class di_MInst_sisi_hh<string opc, Intrinsic IntID>
1027   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1028              !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.H)")),
1029              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1030
1031 class di_MInst_sisi_hh_s1<string opc, Intrinsic IntID>
1032   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1033              !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.H):<<1")),
1034              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1035
1036 class di_MInst_sisi_lh<string opc, Intrinsic IntID>
1037   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1038              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H)")),
1039              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1040
1041 class di_MInst_sisi_lh_s1<string opc, Intrinsic IntID>
1042   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1043              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H):<<1")),
1044              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1045
1046 class di_MInst_sisi_hl<string opc, Intrinsic IntID>
1047   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1048              !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.L)")),
1049              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1050
1051 class di_MInst_sisi_hl_s1<string opc, Intrinsic IntID>
1052   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1053              !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.L):<<1")),
1054              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1055
1056 class di_MInst_sisi_ll<string opc, Intrinsic IntID>
1057   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1058              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L)")),
1059              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1060
1061 class di_MInst_sisi_ll_s1<string opc, Intrinsic IntID>
1062   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1063              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L):<<1")),
1064              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1065
1066
1067 class si_MInst_sisi_hh<string opc, Intrinsic IntID>
1068   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1069              !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.H)")),
1070              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1071
1072 class si_MInst_sisi_hh_s1<string opc, Intrinsic IntID>
1073   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1074              !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.H):<<1")),
1075              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1076
1077 class si_MInst_sisi_lh<string opc, Intrinsic IntID>
1078   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1079              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H)")),
1080              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1081
1082 class si_MInst_sisi_lh_s1<string opc, Intrinsic IntID>
1083   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1084              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H):<<1")),
1085              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1086
1087 class si_MInst_sisi_hl<string opc, Intrinsic IntID>
1088   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1089              !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.L)")),
1090              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1091
1092 class si_MInst_sisi_hl_s1<string opc, Intrinsic IntID>
1093   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1094              !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.L):<<1")),
1095              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1096
1097 class si_MInst_sisi_ll<string opc, Intrinsic IntID>
1098   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1099              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L)")),
1100              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1101
1102 class si_MInst_sisi_ll_s1<string opc, Intrinsic IntID>
1103   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1104              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L):<<1")),
1105              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1106
1107 class si_MInst_sisi_up<string opc, Intrinsic IntID>
1108   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1109              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
1110              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1111
1112 class di_MInst_didi<string opc, Intrinsic IntID>
1113   : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1114              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
1115              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
1116                                            DoubleRegs:$src2))]>;
1117
1118 class di_MInst_didi_conj<string opc, Intrinsic IntID>
1119   : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1120              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2*)")),
1121              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
1122                                            DoubleRegs:$src2))]>;
1123
1124 class di_MInst_sisi_s1_sat_conj<string opc, Intrinsic IntID>
1125   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1126              !strconcat("$dst = ", !strconcat(opc ,
1127                                               "($src1, $src2*):<<1:sat")),
1128              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1129
1130 class di_MInst_didi_s1_rnd_sat<string opc, Intrinsic IntID>
1131   : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1132              !strconcat("$dst = ", !strconcat(opc ,
1133                                               "($src1, $src2):<<1:rnd:sat")),
1134              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
1135                                            DoubleRegs:$src2))]>;
1136
1137 class di_MInst_didi_sat<string opc, Intrinsic IntID>
1138   : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1139              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):sat")),
1140              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
1141                                            DoubleRegs:$src2))]>;
1142
1143 class di_MInst_didi_rnd_sat<string opc, Intrinsic IntID>
1144   : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1145              !strconcat("$dst = ", !strconcat(opc ,
1146                                               "($src1, $src2):rnd:sat")),
1147              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
1148                                            DoubleRegs:$src2))]>;
1149
1150 class si_SInst_sisi_sat<string opc, Intrinsic IntID>
1151   : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1152           !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):sat")),
1153           [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1154
1155 class si_SInst_didi_sat<string opc, Intrinsic IntID>
1156   : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1157           !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):sat")),
1158           [(set IntRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
1159
1160 class si_SInst_disi_s1_rnd_sat<string opc, Intrinsic IntID>
1161   : MInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
1162              !strconcat("$dst = ", !strconcat(opc ,
1163                                               "($src1, $src2):<<1:rnd:sat")),
1164              [(set IntRegs:$dst, (IntID DoubleRegs:$src1, IntRegs:$src2))]>;
1165
1166 class si_MInst_sisi_s1_rnd_sat<string opc, Intrinsic IntID>
1167   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1168              !strconcat("$dst = ", !strconcat(opc ,
1169                                               "($src1, $src2):<<1:rnd:sat")),
1170              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1171
1172 class si_MInst_sisi_l_s1_rnd_sat<string opc, Intrinsic IntID>
1173   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1174              !strconcat("$dst = ", !strconcat(opc ,
1175                                               "($src1, $src2.L):<<1:rnd:sat")),
1176              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1177
1178 class si_MInst_sisi_h_s1_rnd_sat<string opc, Intrinsic IntID>
1179   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1180              !strconcat("$dst = ", !strconcat(opc ,
1181                                               "($src1, $src2.H):<<1:rnd:sat")),
1182              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1183
1184 class si_MInst_sisi_rnd_sat_conj<string opc, Intrinsic IntID>
1185   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1186              !strconcat("$dst = ", !strconcat(opc ,
1187                                               "($src1, $src2*):rnd:sat")),
1188              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1189
1190 class si_MInst_sisi_s1_rnd_sat_conj<string opc, Intrinsic IntID>
1191   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1192              !strconcat("$dst = ", !strconcat(opc ,
1193                                               "($src1, $src2*):<<1:rnd:sat")),
1194              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1195
1196 class si_MInst_sisi_rnd_sat<string opc, Intrinsic IntID>
1197   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1198              !strconcat("$dst = ", !strconcat(opc ,
1199                                               "($src1, $src2):rnd:sat")),
1200              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1201
1202 class si_MInst_sisi_rnd<string opc, Intrinsic IntID>
1203   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1204              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):rnd")),
1205              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1206
1207 class si_MInst_sisisi_xacc<string opc, Intrinsic IntID>
1208   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src2,
1209                                         IntRegs:$src3),
1210              !strconcat("$dst ^= ", !strconcat(opc , "($src2, $src3)")),
1211              [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src2,
1212                                         IntRegs:$src3))],
1213              "$dst2 = $dst">;
1214
1215 class si_MInst_sisisi_acc<string opc, Intrinsic IntID>
1216   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src2,
1217                                         IntRegs:$src3),
1218              !strconcat("$dst += ", !strconcat(opc , "($src2, $src3)")),
1219              [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src2,
1220                                         IntRegs:$src3))],
1221              "$dst2 = $dst">;
1222
1223 class si_MInst_sisisi_nac<string opc, Intrinsic IntID>
1224   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src2,
1225                                         IntRegs:$src3),
1226              !strconcat("$dst -= ", !strconcat(opc , "($src2, $src3)")),
1227              [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src2,
1228                                         IntRegs:$src3))],
1229              "$dst2 = $dst">;
1230
1231 class si_MInst_sisis8_acc<string opc, Intrinsic IntID>
1232   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src2,
1233                                         s8Imm:$src3),
1234              !strconcat("$dst += ", !strconcat(opc , "($src2, #$src3)")),
1235              [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src2,
1236                                         imm:$src3))],
1237              "$dst2 = $dst">;
1238
1239 class si_MInst_sisis8_nac<string opc, Intrinsic IntID>
1240   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src2,
1241                                         s8Imm:$src3),
1242              !strconcat("$dst -= ", !strconcat(opc , "($src2, #$src3)")),
1243              [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src2,
1244                                         imm:$src3))],
1245              "$dst2 = $dst">;
1246
1247 class si_MInst_sisiu4u5<string opc, Intrinsic IntID>
1248   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1249                                         u4Imm:$src2, u5Imm:$src3),
1250                !strconcat("$dst = ", !strconcat(opc ,
1251                                                 "($src1, #$src2, #$src3)")),
1252                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1253                                           imm:$src2, imm:$src3))],
1254                "$dst2 = $dst">;
1255
1256 class si_MInst_sisiu8_acc<string opc, Intrinsic IntID>
1257   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src2,
1258                                         u8Imm:$src3),
1259                !strconcat("$dst += ", !strconcat(opc , "($src2, #$src3)")),
1260                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src2,
1261                                           imm:$src3))],
1262                "$dst2 = $dst">;
1263
1264 class si_MInst_sisiu8_nac<string opc, Intrinsic IntID>
1265   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src2,
1266                                         u8Imm:$src3),
1267                !strconcat("$dst -= ", !strconcat(opc , "($src2, #$src3)")),
1268                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src2,
1269                                           imm:$src3))],
1270                "$dst2 = $dst">;
1271
1272 class si_MInst_sisisi_acc_hh<string opc, Intrinsic IntID>
1273   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1274                                         IntRegs:$src2),
1275                !strconcat("$dst += ", !strconcat(opc , "($src1.H, $src2.H)")),
1276                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1277                                           IntRegs:$src2))],
1278                "$dst2 = $dst">;
1279
1280 class si_MInst_sisisi_acc_sat_lh<string opc, Intrinsic IntID>
1281   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1282                                         IntRegs:$src2),
1283                !strconcat("$dst += ", !strconcat(opc ,
1284                                                  "($src1.L, $src2.H):sat")),
1285                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1286                                           IntRegs:$src2))],
1287                "$dst2 = $dst">;
1288
1289 class si_MInst_sisisi_acc_sat_lh_s1<string opc, Intrinsic IntID>
1290   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1291                                         IntRegs:$src2),
1292                !strconcat("$dst += ", !strconcat(opc ,
1293                                                  "($src1.L, $src2.H):<<1:sat")),
1294                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1295                                           IntRegs:$src2))],
1296                "$dst2 = $dst">;
1297
1298 class si_MInst_sisisi_acc_sat_hh<string opc, Intrinsic IntID>
1299   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1300                                         IntRegs:$src2),
1301                !strconcat("$dst += ", !strconcat(opc ,
1302                                                  "($src1.H, $src2.H):sat")),
1303                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1304                                           IntRegs:$src2))],
1305                "$dst2 = $dst">;
1306
1307 class si_MInst_sisisi_acc_sat_hh_s1<string opc, Intrinsic IntID>
1308   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1309                                         IntRegs:$src2),
1310                !strconcat("$dst += ", !strconcat(opc ,
1311                                                  "($src1.H, $src2.H):<<1:sat")),
1312                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1313                                           IntRegs:$src2))],
1314                "$dst2 = $dst">;
1315
1316 class si_MInst_sisisi_acc_hh_s1<string opc, Intrinsic IntID>
1317   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1318                                         IntRegs:$src2),
1319                !strconcat("$dst += ", !strconcat(opc ,
1320                                                  "($src1.H, $src2.H):<<1")),
1321                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1322                                           IntRegs:$src2))],
1323                "$dst2 = $dst">;
1324
1325 class si_MInst_sisisi_nac_hh<string opc, Intrinsic IntID>
1326   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1327                                         IntRegs:$src2),
1328                !strconcat("$dst -= ", !strconcat(opc , "($src1.H, $src2.H)")),
1329                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1330                                           IntRegs:$src2))],
1331                "$dst2 = $dst">;
1332
1333 class si_MInst_sisisi_nac_sat_hh_s1<string opc, Intrinsic IntID>
1334   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1335                                         IntRegs:$src2),
1336                !strconcat("$dst -= ", !strconcat(opc ,
1337                                                  "($src1.H, $src2.H):<<1:sat")),
1338                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1339                                           IntRegs:$src2))],
1340                "$dst2 = $dst">;
1341
1342 class si_MInst_sisisi_nac_sat_hh<string opc, Intrinsic IntID>
1343   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1344                                         IntRegs:$src2),
1345                !strconcat("$dst -= ", !strconcat(opc ,
1346                                                  "($src1.H, $src2.H):sat")),
1347                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1348                                           IntRegs:$src2))],
1349                "$dst2 = $dst">;
1350
1351 class si_MInst_sisisi_nac_sat_hl_s1<string opc, Intrinsic IntID>
1352   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1353                                         IntRegs:$src2),
1354                !strconcat("$dst -= ", !strconcat(opc ,
1355                                                  "($src1.H, $src2.L):<<1:sat")),
1356                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1357                                           IntRegs:$src2))],
1358                "$dst2 = $dst">;
1359
1360 class si_MInst_sisisi_nac_sat_hl<string opc, Intrinsic IntID>
1361   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1362                                         IntRegs:$src2),
1363                !strconcat("$dst -= ", !strconcat(opc ,
1364                                                  "($src1.H, $src2.L):sat")),
1365                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1366                                           IntRegs:$src2))],
1367                "$dst2 = $dst">;
1368
1369 class si_MInst_sisisi_nac_sat_lh_s1<string opc, Intrinsic IntID>
1370   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1371                                         IntRegs:$src2),
1372                !strconcat("$dst -= ", !strconcat(opc ,
1373                                                  "($src1.L, $src2.H):<<1:sat")),
1374                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1375                                           IntRegs:$src2))],
1376                "$dst2 = $dst">;
1377
1378 class si_MInst_sisisi_nac_sat_lh<string opc, Intrinsic IntID>
1379   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1380                                         IntRegs:$src2),
1381                !strconcat("$dst -= ", !strconcat(opc ,
1382                                                  "($src1.L, $src2.H):sat")),
1383                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1384                                           IntRegs:$src2))],
1385                "$dst2 = $dst">;
1386
1387 class si_MInst_sisisi_nac_sat_ll_s1<string opc, Intrinsic IntID>
1388   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1389                                         IntRegs:$src2),
1390                !strconcat("$dst -= ", !strconcat(opc ,
1391                                                  "($src1.L, $src2.L):<<1:sat")),
1392                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1393                                           IntRegs:$src2))],
1394                "$dst2 = $dst">;
1395
1396 class si_MInst_sisisi_nac_sat_ll<string opc, Intrinsic IntID>
1397   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1398                                         IntRegs:$src2),
1399                !strconcat("$dst -= ", !strconcat(opc ,
1400                                                  "($src1.L, $src2.L):sat")),
1401                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1402                                           IntRegs:$src2))],
1403                "$dst2 = $dst">;
1404
1405 class si_MInst_sisisi_nac_hh_s1<string opc, Intrinsic IntID>
1406   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1407                                         IntRegs:$src2),
1408                !strconcat("$dst -= ", !strconcat(opc ,
1409                                                  "($src1.H, $src2.H):<<1")),
1410                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1411                                           IntRegs:$src2))],
1412                "$dst2 = $dst">;
1413
1414 class si_MInst_sisisi_acc_hl<string opc, Intrinsic IntID>
1415   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1416                                         IntRegs:$src2),
1417                !strconcat("$dst += ", !strconcat(opc , "($src1.H, $src2.L)")),
1418                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1419                                           IntRegs:$src2))],
1420                "$dst2 = $dst">;
1421
1422 class si_MInst_sisisi_acc_hl_s1<string opc, Intrinsic IntID>
1423   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1424                                         IntRegs:$src2),
1425                !strconcat("$dst += ", !strconcat(opc ,
1426                                                  "($src1.H, $src2.L):<<1")),
1427                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1428                                           IntRegs:$src2))],
1429                "$dst2 = $dst">;
1430
1431 class si_MInst_sisisi_nac_hl<string opc, Intrinsic IntID>
1432   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1433                                         IntRegs:$src2),
1434                !strconcat("$dst -= ", !strconcat(opc , "($src1.H, $src2.L)")),
1435                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1436                                           IntRegs:$src2))],
1437                "$dst2 = $dst">;
1438
1439 class si_MInst_sisisi_nac_hl_s1<string opc, Intrinsic IntID>
1440   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1441                                         IntRegs:$src2),
1442                !strconcat("$dst -= ", !strconcat(opc ,
1443                                                  "($src1.H, $src2.L):<<1")),
1444                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1445                                           IntRegs:$src2))],
1446                "$dst2 = $dst">;
1447
1448 class si_MInst_sisisi_acc_lh<string opc, Intrinsic IntID>
1449   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1450                                         IntRegs:$src2),
1451                !strconcat("$dst += ", !strconcat(opc , "($src1.L, $src2.H)")),
1452                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1453                                           IntRegs:$src2))],
1454                "$dst2 = $dst">;
1455
1456 class si_MInst_sisisi_acc_lh_s1<string opc, Intrinsic IntID>
1457   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1458                                         IntRegs:$src2),
1459                !strconcat("$dst += ", !strconcat(opc ,
1460                                                  "($src1.L, $src2.H):<<1")),
1461                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1462                                           IntRegs:$src2))],
1463                "$dst2 = $dst">;
1464
1465 class si_MInst_sisisi_nac_lh<string opc, Intrinsic IntID>
1466   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1467                                         IntRegs:$src2),
1468                !strconcat("$dst -= ", !strconcat(opc , "($src1.L, $src2.H)")),
1469                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1470                                           IntRegs:$src2))],
1471                "$dst2 = $dst">;
1472
1473 class si_MInst_sisisi_nac_lh_s1<string opc, Intrinsic IntID>
1474   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1475                                         IntRegs:$src2),
1476                !strconcat("$dst -= ", !strconcat(opc ,
1477                                                  "($src1.L, $src2.H):<<1")),
1478                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1479                                           IntRegs:$src2))],
1480                "$dst2 = $dst">;
1481
1482 class si_MInst_sisisi_acc_ll<string opc, Intrinsic IntID>
1483   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1484                                         IntRegs:$src2),
1485                !strconcat("$dst += ", !strconcat(opc , "($src1.L, $src2.L)")),
1486                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1487                                           IntRegs:$src2))],
1488                "$dst2 = $dst">;
1489
1490 class si_MInst_sisisi_acc_ll_s1<string opc, Intrinsic IntID>
1491   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1492                                         IntRegs:$src2),
1493                !strconcat("$dst += ", !strconcat(opc ,
1494                                                  "($src1.L, $src2.L):<<1")),
1495                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1496                                           IntRegs:$src2))],
1497                "$dst2 = $dst">;
1498
1499 class si_MInst_sisisi_acc_sat_ll_s1<string opc, Intrinsic IntID>
1500   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1501                                         IntRegs:$src2),
1502                !strconcat("$dst += ", !strconcat(opc ,
1503                                                  "($src1.L, $src2.L):<<1:sat")),
1504                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1505                                           IntRegs:$src2))],
1506                "$dst2 = $dst">;
1507
1508 class si_MInst_sisisi_acc_sat_hl_s1<string opc, Intrinsic IntID>
1509   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1510                                         IntRegs:$src2),
1511                !strconcat("$dst += ", !strconcat(opc ,
1512                                                  "($src1.H, $src2.L):<<1:sat")),
1513                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1514                                           IntRegs:$src2))],
1515                "$dst2 = $dst">;
1516
1517 class si_MInst_sisisi_acc_sat_ll<string opc, Intrinsic IntID>
1518   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1519                                         IntRegs:$src2),
1520                !strconcat("$dst += ", !strconcat(opc ,
1521                                                  "($src1.L, $src2.L):sat")),
1522                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1523                                           IntRegs:$src2))],
1524                "$dst2 = $dst">;
1525
1526 class si_MInst_sisisi_acc_sat_hl<string opc, Intrinsic IntID>
1527   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1528                                         IntRegs:$src2),
1529                !strconcat("$dst += ", !strconcat(opc ,
1530                                                  "($src1.H, $src2.L):sat")),
1531                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1532                                           IntRegs:$src2))],
1533                "$dst2 = $dst">;
1534
1535 class si_MInst_sisisi_nac_ll<string opc, Intrinsic IntID>
1536   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1537                                         IntRegs:$src2),
1538                !strconcat("$dst -= ", !strconcat(opc , "($src1.L, $src2.L)")),
1539                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1540                                           IntRegs:$src2))],
1541                "$dst2 = $dst">;
1542
1543 class si_MInst_sisisi_nac_ll_s1<string opc, Intrinsic IntID>
1544   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1545                                         IntRegs:$src2),
1546                !strconcat("$dst -= ", !strconcat(opc ,
1547                                                  "($src1.L, $src2.L):<<1")),
1548                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1549                                           IntRegs:$src2))],
1550                "$dst2 = $dst">;
1551
1552 class si_MInst_sisisi_nac_hh_sat<string opc, Intrinsic IntID>
1553   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1554                                         IntRegs:$src2),
1555                !strconcat("$dst -= ", !strconcat(opc ,
1556                                                  "($src1.H, $src2.H):sat")),
1557                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1558                                           IntRegs:$src2))],
1559                "$dst2 = $dst">;
1560
1561 class si_MInst_sisisi_nac_hh_s1_sat<string opc, Intrinsic IntID>
1562   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1563                                         IntRegs:$src2),
1564                !strconcat("$dst -= ", !strconcat(opc ,
1565                                                  "($src1.H, $src2.H):<<1:sat")),
1566                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1567                                           IntRegs:$src2))],
1568                "$dst2 = $dst">;
1569
1570 class si_MInst_sisisi_nac_hl_sat<string opc, Intrinsic IntID>
1571   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1572                                         IntRegs:$src2),
1573                !strconcat("$dst -= ", !strconcat(opc ,
1574                                                  "($src1.H, $src2.L):sat")),
1575                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1576                                           IntRegs:$src2))],
1577                "$dst2 = $dst">;
1578
1579 class si_MInst_sisisi_nac_hl_s1_sat<string opc, Intrinsic IntID>
1580   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1581                                         IntRegs:$src2),
1582                !strconcat("$dst -= ", !strconcat(opc ,
1583                                                  "($src1.H, $src2.L):<<1:sat")),
1584                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1585                                           IntRegs:$src2))],
1586                "$dst2 = $dst">;
1587
1588 class si_MInst_sisisi_nac_lh_sat<string opc, Intrinsic IntID>
1589   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1590                                         IntRegs:$src2),
1591                !strconcat("$dst -= ", !strconcat(opc ,
1592                                                  "($src1.L, $src2.H):sat")),
1593                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1594                                           IntRegs:$src2))],
1595                "$dst2 = $dst">;
1596
1597 class si_MInst_sisisi_nac_lh_s1_sat<string opc, Intrinsic IntID>
1598   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1599                                         IntRegs:$src2),
1600                !strconcat("$dst -= ", !strconcat(opc ,
1601                                                  "($src1.L, $src2.H):<<1:sat")),
1602                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1603                                           IntRegs:$src2))],
1604                "$dst2 = $dst">;
1605
1606 class si_MInst_sisisi_nac_ll_sat<string opc, Intrinsic IntID>
1607   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1608                                         IntRegs:$src2),
1609                !strconcat("$dst -= ", !strconcat(opc ,
1610                                                  "($src1.L, $src2.L):sat")),
1611                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1612                                           IntRegs:$src2))],
1613                "$dst2 = $dst">;
1614
1615 class si_MInst_sisisi_nac_ll_s1_sat<string opc, Intrinsic IntID>
1616   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1617                                         IntRegs:$src2),
1618                !strconcat("$dst -= ", !strconcat(opc ,
1619                                                  "($src1.L, $src2.L):<<1:sat")),
1620                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1621                                           IntRegs:$src2))],
1622                "$dst2 = $dst">;
1623
1624 class di_ALU32_sisi<string opc, Intrinsic IntID>
1625   : ALU32_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1626              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
1627              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1628
1629 class di_MInst_sisi<string opc, Intrinsic IntID>
1630   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1631              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
1632              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1633
1634 class di_MInst_sisi_sat<string opc, Intrinsic IntID>
1635   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1636              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):sat")),
1637              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1638
1639 class di_MInst_sisi_sat_conj<string opc, Intrinsic IntID>
1640   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1641              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2*):sat")),
1642              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1643
1644 class di_MInst_sisi_s1_sat<string opc, Intrinsic IntID>
1645   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1646              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):<<1:sat")),
1647              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1648
1649 class di_MInst_didi_s1_sat<string opc, Intrinsic IntID>
1650   : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1651              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):<<1:sat")),
1652              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
1653                                            DoubleRegs:$src2))]>;
1654
1655 class si_MInst_didi_s1_rnd_sat<string opc, Intrinsic IntID>
1656   : MInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1657              !strconcat("$dst = ", !strconcat(opc ,
1658                                               "($src1, $src2):<<1:rnd:sat")),
1659              [(set IntRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
1660
1661 class si_MInst_didi_rnd_sat<string opc, Intrinsic IntID>
1662   : MInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1663              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):rnd:sat")),
1664              [(set IntRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
1665
1666 class si_MInst_sisi_sat_hh<string opc, Intrinsic IntID>
1667   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1668              !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.H):sat")),
1669              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1670
1671 class si_MInst_sisi_sat_hh_s1<string opc, Intrinsic IntID>
1672   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1673                !strconcat("$dst = ", !strconcat(opc ,
1674                                                 "($src1.H, $src2.H):<<1:sat")),
1675                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1676
1677 class si_MInst_sisi_sat_hl<string opc, Intrinsic IntID>
1678   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1679              !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.L):sat")),
1680              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1681
1682 class si_MInst_sisi_sat_hl_s1<string opc, Intrinsic IntID>
1683   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1684                !strconcat("$dst = ", !strconcat(opc ,
1685                                                 "($src1.H, $src2.L):<<1:sat")),
1686                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1687
1688 class si_MInst_sisi_sat_lh<string opc, Intrinsic IntID>
1689   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1690              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H):sat")),
1691              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1692
1693 class si_MInst_sisi_sat_lh_s1<string opc, Intrinsic IntID>
1694   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1695                !strconcat("$dst = ", !strconcat(opc ,
1696                                                 "($src1.L, $src2.H):<<1:sat")),
1697                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1698
1699 class si_MInst_sisi_sat_ll<string opc, Intrinsic IntID>
1700   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1701              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L):sat")),
1702              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1703
1704 class si_MInst_sisi_sat_ll_s1<string opc, Intrinsic IntID>
1705   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1706                !strconcat("$dst = ", !strconcat(opc ,
1707                                                 "($src1.L, $src2.L):<<1:sat")),
1708                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1709
1710 class si_MInst_sisi_sat_rnd_hh<string opc, Intrinsic IntID>
1711   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1712                !strconcat("$dst = ", !strconcat(opc ,
1713                                                 "($src1.H, $src2.H):rnd:sat")),
1714                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1715
1716 class si_MInst_sisi_rnd_hh<string opc, Intrinsic IntID>
1717   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1718                !strconcat("$dst = ", !strconcat(opc ,
1719                                                 "($src1.H, $src2.H):rnd")),
1720                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1721
1722 class si_MInst_sisi_rnd_hh_s1<string opc, Intrinsic IntID>
1723   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1724                !strconcat("$dst = ", !strconcat(opc ,
1725                                                 "($src1.H, $src2.H):<<1:rnd")),
1726                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1727
1728 class si_MInst_sisi_sat_rnd_hh_s1<string opc, Intrinsic IntID>
1729   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1730                !strconcat("$dst = ",
1731                           !strconcat(opc ,
1732                                      "($src1.H, $src2.H):<<1:rnd:sat")),
1733                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1734
1735 class si_MInst_sisi_rnd_hl<string opc, Intrinsic IntID>
1736   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1737                !strconcat("$dst = ",
1738                           !strconcat(opc , "($src1.H, $src2.L):rnd")),
1739                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1740
1741 class si_MInst_sisi_rnd_hl_s1<string opc, Intrinsic IntID>
1742   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1743                !strconcat("$dst = ",
1744                           !strconcat(opc , "($src1.H, $src2.L):<<1:rnd")),
1745                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1746
1747 class si_MInst_sisi_sat_rnd_hl<string opc, Intrinsic IntID>
1748   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1749                !strconcat("$dst = ",
1750                           !strconcat(opc , "($src1.H, $src2.L):rnd:sat")),
1751                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1752
1753 class si_MInst_sisi_sat_rnd_hl_s1<string opc, Intrinsic IntID>
1754   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1755                !strconcat("$dst = ",
1756                           !strconcat(opc , "($src1.H, $src2.L):<<1:rnd:sat")),
1757                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1758
1759 class si_MInst_sisi_rnd_lh<string opc, Intrinsic IntID>
1760   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1761                !strconcat("$dst = ",
1762                           !strconcat(opc , "($src1.L, $src2.H):rnd")),
1763                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1764
1765 class si_MInst_sisi_sat_rnd_lh<string opc, Intrinsic IntID>
1766   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1767                !strconcat("$dst = ",
1768                           !strconcat(opc , "($src1.L, $src2.H):rnd:sat")),
1769                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1770
1771 class si_MInst_sisi_sat_rnd_lh_s1<string opc, Intrinsic IntID>
1772   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1773                !strconcat("$dst = ",
1774                           !strconcat(opc , "($src1.L, $src2.H):<<1:rnd:sat")),
1775                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1776
1777 class si_MInst_sisi_rnd_lh_s1<string opc, Intrinsic IntID>
1778   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1779                !strconcat("$dst = ",
1780                           !strconcat(opc , "($src1.L, $src2.H):<<1:rnd")),
1781                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1782
1783 class si_MInst_sisi_sat_rnd_ll<string opc, Intrinsic IntID>
1784   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1785                !strconcat("$dst = ",
1786                           !strconcat(opc , "($src1.L, $src2.L):rnd:sat")),
1787                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1788
1789 class si_MInst_sisi_sat_rnd_ll_s1<string opc, Intrinsic IntID>
1790   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1791                !strconcat("$dst = ",
1792                           !strconcat(opc , "($src1.L, $src2.L):<<1:rnd:sat")),
1793                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1794
1795 class si_MInst_sisi_rnd_ll<string opc, Intrinsic IntID>
1796   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1797                !strconcat("$dst = ",
1798                           !strconcat(opc , "($src1.L, $src2.L):rnd")),
1799                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1800
1801 class si_MInst_sisi_rnd_ll_s1<string opc, Intrinsic IntID>
1802   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1803                !strconcat("$dst = ",
1804                           !strconcat(opc , "($src1.L, $src2.L):<<1:rnd")),
1805                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1806
1807 class di_MInst_dididi_acc_sat<string opc, Intrinsic IntID>
1808   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2,
1809                                            DoubleRegs:$src1, DoubleRegs:$src2),
1810                !strconcat("$dst += ", !strconcat(opc , "($src1, $src2):sat")),
1811                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
1812                                              DoubleRegs:$src1,
1813                                              DoubleRegs:$src2))],
1814                "$dst2 = $dst">;
1815
1816 class di_MInst_dididi_acc_rnd_sat<string opc, Intrinsic IntID>
1817   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
1818                                            DoubleRegs:$src2),
1819                !strconcat("$dst += ",
1820                           !strconcat(opc , "($src1, $src2):rnd:sat")),
1821                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
1822                                              DoubleRegs:$src1,
1823                                              DoubleRegs:$src2))],
1824                "$dst2 = $dst">;
1825
1826 class di_MInst_dididi_acc_s1<string opc, Intrinsic IntID>
1827   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2,
1828                                            DoubleRegs:$src1,
1829                                            DoubleRegs:$src2),
1830                !strconcat("$dst += ",
1831                           !strconcat(opc , "($src1, $src2):<<1")),
1832                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
1833                                              DoubleRegs:$src1,
1834                                              DoubleRegs:$src2))],
1835                "$dst2 = $dst">;
1836
1837
1838 class di_MInst_dididi_acc_s1_sat<string opc, Intrinsic IntID>
1839   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2,
1840                                            DoubleRegs:$src1,
1841                                            DoubleRegs:$src2),
1842                !strconcat("$dst += ",
1843                           !strconcat(opc , "($src1, $src2):<<1:sat")),
1844                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
1845                                              DoubleRegs:$src1,
1846                                              DoubleRegs:$src2))],
1847                "$dst2 = $dst">;
1848
1849 class di_MInst_dididi_acc_s1_rnd_sat<string opc, Intrinsic IntID>
1850   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
1851                                            DoubleRegs:$src2),
1852                !strconcat("$dst += ",
1853                           !strconcat(opc , "($src1, $src2):<<1:rnd:sat")),
1854                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
1855                                              DoubleRegs:$src1,
1856                                              DoubleRegs:$src2))],
1857                "$dst2 = $dst">;
1858
1859 class di_MInst_dididi_acc<string opc, Intrinsic IntID>
1860   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
1861                                            DoubleRegs:$src2),
1862                !strconcat("$dst += ", !strconcat(opc , "($src1, $src2)")),
1863                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
1864                                              DoubleRegs:$src1,
1865                                              DoubleRegs:$src2))],
1866                "$dst2 = $dst">;
1867
1868 class di_MInst_dididi_acc_conj<string opc, Intrinsic IntID>
1869   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
1870                                            DoubleRegs:$src2),
1871                !strconcat("$dst += ", !strconcat(opc , "($src1, $src2*)")),
1872                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
1873                                              DoubleRegs:$src1,
1874                                              DoubleRegs:$src2))],
1875                "$dst2 = $dst">;
1876
1877 class di_MInst_disisi_acc_hh<string opc, Intrinsic IntID>
1878   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1879                                            IntRegs:$src2),
1880                !strconcat("$dst += ", !strconcat(opc , "($src1.H, $src2.H)")),
1881                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1882                                              IntRegs:$src2))],
1883                "$dst2 = $dst">;
1884
1885 class di_MInst_disisi_acc_hl<string opc, Intrinsic IntID>
1886   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1887                                            IntRegs:$src2),
1888                !strconcat("$dst += ", !strconcat(opc , "($src1.H, $src2.L)")),
1889                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1890                                              IntRegs:$src2))],
1891                "$dst2 = $dst">;
1892
1893 class di_MInst_disisi_acc_lh<string opc, Intrinsic IntID>
1894   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1895                                            IntRegs:$src2),
1896                !strconcat("$dst += ", !strconcat(opc , "($src1.L, $src2.H)")),
1897                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1898                                              IntRegs:$src2))],
1899                "$dst2 = $dst">;
1900
1901 class di_MInst_disisi_acc_ll<string opc, Intrinsic IntID>
1902   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1903                                            IntRegs:$src2),
1904                !strconcat("$dst += ", !strconcat(opc , "($src1.L, $src2.L)")),
1905                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1906                                              IntRegs:$src2))],
1907                "$dst2 = $dst">;
1908
1909 class di_MInst_disisi_acc_hh_s1<string opc, Intrinsic IntID>
1910   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1911                                            IntRegs:$src2),
1912                !strconcat("$dst += ",
1913                           !strconcat(opc , "($src1.H, $src2.H):<<1")),
1914                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1915                                              IntRegs:$src2))],
1916                "$dst2 = $dst">;
1917
1918 class di_MInst_disisi_acc_hl_s1<string opc, Intrinsic IntID>
1919   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1920                                            IntRegs:$src2),
1921                !strconcat("$dst += ",
1922                           !strconcat(opc , "($src1.H, $src2.L):<<1")),
1923                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1924                                              IntRegs:$src2))],
1925                "$dst2 = $dst">;
1926
1927 class di_MInst_disisi_acc_lh_s1<string opc, Intrinsic IntID>
1928   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1929                                            IntRegs:$src2),
1930                !strconcat("$dst += ",
1931                           !strconcat(opc , "($src1.L, $src2.H):<<1")),
1932                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1933                                              IntRegs:$src2))],
1934                "$dst2 = $dst">;
1935
1936 class di_MInst_disisi_acc_ll_s1<string opc, Intrinsic IntID>
1937   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1938                                            IntRegs:$src2),
1939                !strconcat("$dst += ",
1940                           !strconcat(opc , "($src1.L, $src2.L):<<1")),
1941                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1942                                              IntRegs:$src2))],
1943                "$dst2 = $dst">;
1944
1945 class di_MInst_disisi_nac_hh<string opc, Intrinsic IntID>
1946   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1947                                            IntRegs:$src2),
1948                !strconcat("$dst -= ", !strconcat(opc , "($src1.H, $src2.H)")),
1949                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1950                                              IntRegs:$src2))],
1951                "$dst2 = $dst">;
1952
1953 class di_MInst_disisi_nac_hl<string opc, Intrinsic IntID>
1954   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1955                                            IntRegs:$src2),
1956                !strconcat("$dst -= ", !strconcat(opc , "($src1.H, $src2.L)")),
1957                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1958                                              IntRegs:$src2))],
1959                "$dst2 = $dst">;
1960
1961 class di_MInst_disisi_nac_lh<string opc, Intrinsic IntID>
1962   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1963                                            IntRegs:$src2),
1964                !strconcat("$dst -= ", !strconcat(opc , "($src1.L, $src2.H)")),
1965                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1966                                              IntRegs:$src2))],
1967                "$dst2 = $dst">;
1968
1969 class di_MInst_disisi_nac_ll<string opc, Intrinsic IntID>
1970   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1971                                            IntRegs:$src2),
1972                !strconcat("$dst -= ", !strconcat(opc , "($src1.L, $src2.L)")),
1973                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1974                                              IntRegs:$src2))],
1975                "$dst2 = $dst">;
1976
1977 class di_MInst_disisi_nac_hh_s1<string opc, Intrinsic IntID>
1978   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1979                                            IntRegs:$src2),
1980                !strconcat("$dst -= ",
1981                           !strconcat(opc , "($src1.H, $src2.H):<<1")),
1982                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1983                                              IntRegs:$src2))],
1984                "$dst2 = $dst">;
1985
1986 class di_MInst_disisi_nac_hl_s1<string opc, Intrinsic IntID>
1987   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1988                                            IntRegs:$src2),
1989                !strconcat("$dst -= ",
1990                           !strconcat(opc , "($src1.H, $src2.L):<<1")),
1991                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1992                                              IntRegs:$src2))],
1993                "$dst2 = $dst">;
1994
1995 class di_MInst_disisi_nac_lh_s1<string opc, Intrinsic IntID>
1996   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1997                                            IntRegs:$src2),
1998                !strconcat("$dst -= ",
1999                           !strconcat(opc , "($src1.L, $src2.H):<<1")),
2000                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
2001                                              IntRegs:$src2))],
2002                "$dst2 = $dst">;
2003
2004 class di_MInst_disisi_nac_ll_s1<string opc, Intrinsic IntID>
2005   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
2006                                            IntRegs:$src2),
2007                !strconcat("$dst -= ",
2008                           !strconcat(opc , "($src1.L, $src2.L):<<1")),
2009                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
2010                                              IntRegs:$src2))],
2011                "$dst2 = $dst">;
2012
2013 class di_MInst_disisi_acc_s1_sat<string opc, Intrinsic IntID>
2014   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
2015                                            IntRegs:$src2),
2016                !strconcat("$dst += ",
2017                           !strconcat(opc , "($src1, $src2):<<1:sat")),
2018                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
2019                                              IntRegs:$src2))],
2020                "$dst2 = $dst">;
2021
2022 class di_MInst_disi_s1_sat<string opc, Intrinsic IntID>
2023   : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
2024              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):<<1:sat")),
2025              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, IntRegs:$src2))]>;
2026
2027 class di_MInst_didisi_acc_s1_sat<string opc, Intrinsic IntID>
2028   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
2029                                            IntRegs:$src2),
2030                !strconcat("$dst += ",
2031                           !strconcat(opc , "($src1, $src2):<<1:sat")),
2032                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
2033                                              DoubleRegs:$src1,
2034                                              IntRegs:$src2))],
2035                "$dst2 = $dst">;
2036
2037 class si_MInst_disi_s1_rnd_sat<string opc, Intrinsic IntID>
2038   : MInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
2039              !strconcat("$dst = ",
2040                         !strconcat(opc , "($src1, $src2):<<1:rnd:sat")),
2041              [(set IntRegs:$dst, (IntID DoubleRegs:$src1, IntRegs:$src2))]>;
2042
2043 class si_MInst_didi<string opc, Intrinsic IntID>
2044   : MInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
2045              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
2046              [(set IntRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
2047
2048
2049 class T_RI_pat <InstHexagon MI, Intrinsic IntID>
2050   : Pat<(IntID (i32 IntRegs:$Rs), imm:$It),
2051         (MI IntRegs:$Rs, imm:$It)>;
2052
2053 //
2054 // LDInst classes.
2055 //
2056 let mayLoad = 1, hasSideEffects = 0 in
2057 class di_LDInstPI_diu4<string opc, Intrinsic IntID>
2058   : LDInstPI<(outs IntRegs:$dst, DoubleRegs:$dst2),
2059            (ins IntRegs:$src1, IntRegs:$src2, CtrRegs:$src3, s4Imm:$offset),
2060            "$dst2 = memd($src1++#$offset:circ($src3))",
2061            [],
2062            "$src1 = $dst">;
2063
2064 /********************************************************************
2065 *            ALU32/ALU                                              *
2066 *********************************************************************/
2067
2068 // ALU32 / ALU / Add.
2069 def HEXAGON_A2_add:
2070   si_ALU32_sisi                   <"add",      int_hexagon_A2_add>;
2071 def HEXAGON_A2_addi:
2072   si_ALU32_sis16                  <"add",      int_hexagon_A2_addi>;
2073
2074 // ALU32 / ALU / Logical operations.
2075 def HEXAGON_A2_and:
2076   si_ALU32_sisi                   <"and",      int_hexagon_A2_and>;
2077 def HEXAGON_A2_andir:
2078   si_ALU32_sis10                  <"and",      int_hexagon_A2_andir>;
2079 def HEXAGON_A2_not:
2080   si_ALU32_si                     <"not",      int_hexagon_A2_not>;
2081 def HEXAGON_A2_or:
2082   si_ALU32_sisi                   <"or",       int_hexagon_A2_or>;
2083 def HEXAGON_A2_orir:
2084   si_ALU32_sis10                  <"or",       int_hexagon_A2_orir>;
2085 def HEXAGON_A2_xor:
2086   si_ALU32_sisi                   <"xor",      int_hexagon_A2_xor>;
2087
2088 // ALU32 / ALU / Negate.
2089 def HEXAGON_A2_neg:
2090   si_ALU32_si                     <"neg",      int_hexagon_A2_neg>;
2091
2092 // ALU32 / ALU / Subtract.
2093 def HEXAGON_A2_sub:
2094   si_ALU32_sisi                   <"sub",      int_hexagon_A2_sub>;
2095 def HEXAGON_A2_subri:
2096   si_ALU32_s10si                  <"sub",      int_hexagon_A2_subri>;
2097
2098 // ALU32 / ALU / Transfer Immediate.
2099 def HEXAGON_A2_tfril:
2100   si_lo_ALU32_siu16               <"",         int_hexagon_A2_tfril>;
2101 def HEXAGON_A2_tfrih:
2102   si_hi_ALU32_siu16               <"",         int_hexagon_A2_tfrih>;
2103 def HEXAGON_A2_tfrsi:
2104   si_ALU32_s16                    <"",         int_hexagon_A2_tfrsi>;
2105 def HEXAGON_A2_tfrpi:
2106   di_ALU32_s8                     <"",         int_hexagon_A2_tfrpi>;
2107
2108 // ALU32 / ALU / Transfer Register.
2109 def HEXAGON_A2_tfr:
2110   si_ALU32_si_tfr                  <"",        int_hexagon_A2_tfr>;
2111
2112 /********************************************************************
2113 *            ALU32/PERM                                             *
2114 *********************************************************************/
2115
2116 // ALU32 / PERM / Combine.
2117 def HEXAGON_A2_combinew:
2118   di_ALU32_sisi                   <"combine",  int_hexagon_A2_combinew>;
2119 def HEXAGON_A2_combine_hh:
2120   si_MInst_sisi_hh                <"combine",  int_hexagon_A2_combine_hh>;
2121 def HEXAGON_A2_combine_lh:
2122   si_MInst_sisi_lh                <"combine",  int_hexagon_A2_combine_lh>;
2123 def HEXAGON_A2_combine_hl:
2124   si_MInst_sisi_hl                <"combine",  int_hexagon_A2_combine_hl>;
2125 def HEXAGON_A2_combine_ll:
2126   si_MInst_sisi_ll                <"combine",  int_hexagon_A2_combine_ll>;
2127 def HEXAGON_A2_combineii:
2128   di_MInst_s8s8                   <"combine",  int_hexagon_A2_combineii>;
2129
2130 // ALU32 / PERM / Mux.
2131 def HEXAGON_C2_mux:
2132   si_ALU32_qisisi                 <"mux",      int_hexagon_C2_mux>;
2133 def HEXAGON_C2_muxri:
2134   si_ALU32_qis8si                 <"mux",      int_hexagon_C2_muxri>;
2135 def HEXAGON_C2_muxir:
2136   si_ALU32_qisis8                 <"mux",      int_hexagon_C2_muxir>;
2137 def HEXAGON_C2_muxii:
2138   si_ALU32_qis8s8                 <"mux",      int_hexagon_C2_muxii>;
2139
2140 // ALU32 / PERM / Shift halfword.
2141 def HEXAGON_A2_aslh:
2142   si_ALU32_si                     <"aslh",     int_hexagon_A2_aslh>;
2143 def HEXAGON_A2_asrh:
2144   si_ALU32_si                     <"asrh",     int_hexagon_A2_asrh>;
2145 def SI_to_SXTHI_asrh:
2146   si_ALU32_si                     <"asrh",     int_hexagon_SI_to_SXTHI_asrh>;
2147
2148 // ALU32 / PERM / Sign/zero extend.
2149 def HEXAGON_A2_sxth:
2150   si_ALU32_si                     <"sxth",     int_hexagon_A2_sxth>;
2151 def HEXAGON_A2_sxtb:
2152   si_ALU32_si                     <"sxtb",     int_hexagon_A2_sxtb>;
2153 def HEXAGON_A2_zxth:
2154   si_ALU32_si                     <"zxth",     int_hexagon_A2_zxth>;
2155 def HEXAGON_A2_zxtb:
2156   si_ALU32_si                     <"zxtb",     int_hexagon_A2_zxtb>;
2157
2158 /********************************************************************
2159 *            ALU32/PRED                                             *
2160 *********************************************************************/
2161
2162 // ALU32 / PRED / Compare.
2163 def HEXAGON_C2_cmpeq:
2164   qi_ALU32_sisi                   <"cmp.eq",   int_hexagon_C2_cmpeq>;
2165 def HEXAGON_C2_cmpeqi:
2166   qi_ALU32_sis10                  <"cmp.eq",   int_hexagon_C2_cmpeqi>;
2167 def HEXAGON_C2_cmpgei:
2168   qi_ALU32_sis8                   <"cmp.ge",   int_hexagon_C2_cmpgei>;
2169 def HEXAGON_C2_cmpgeui:
2170   qi_ALU32_siu8                   <"cmp.geu",  int_hexagon_C2_cmpgeui>;
2171 def HEXAGON_C2_cmpgt:
2172   qi_ALU32_sisi                   <"cmp.gt",   int_hexagon_C2_cmpgt>;
2173 def HEXAGON_C2_cmpgti:
2174   qi_ALU32_sis10                  <"cmp.gt",   int_hexagon_C2_cmpgti>;
2175 def HEXAGON_C2_cmpgtu:
2176   qi_ALU32_sisi                   <"cmp.gtu",  int_hexagon_C2_cmpgtu>;
2177 def HEXAGON_C2_cmpgtui:
2178   qi_ALU32_siu9                   <"cmp.gtu",  int_hexagon_C2_cmpgtui>;
2179 def HEXAGON_C2_cmplt:
2180   qi_ALU32_sisi                   <"cmp.lt",   int_hexagon_C2_cmplt>;
2181 def HEXAGON_C2_cmpltu:
2182   qi_ALU32_sisi                   <"cmp.ltu",  int_hexagon_C2_cmpltu>;
2183
2184 /********************************************************************
2185 *            ALU32/VH                                               *
2186 *********************************************************************/
2187
2188 // ALU32 / VH / Vector add halfwords.
2189 // Rd32=vadd[u]h(Rs32,Rt32:sat]
2190 def HEXAGON_A2_svaddh:
2191   si_ALU32_sisi                   <"vaddh",    int_hexagon_A2_svaddh>;
2192 def HEXAGON_A2_svaddhs:
2193   si_ALU32_sisi_sat               <"vaddh",    int_hexagon_A2_svaddhs>;
2194 def HEXAGON_A2_svadduhs:
2195   si_ALU32_sisi_sat               <"vadduh",   int_hexagon_A2_svadduhs>;
2196
2197 // ALU32 / VH / Vector average halfwords.
2198 def HEXAGON_A2_svavgh:
2199   si_ALU32_sisi                   <"vavgh",    int_hexagon_A2_svavgh>;
2200 def HEXAGON_A2_svavghs:
2201   si_ALU32_sisi_rnd               <"vavgh",    int_hexagon_A2_svavghs>;
2202 def HEXAGON_A2_svnavgh:
2203   si_ALU32_sisi                   <"vnavgh",   int_hexagon_A2_svnavgh>;
2204
2205 // ALU32 / VH / Vector subtract halfwords.
2206 def HEXAGON_A2_svsubh:
2207   si_ALU32_sisi                   <"vsubh",    int_hexagon_A2_svsubh>;
2208 def HEXAGON_A2_svsubhs:
2209   si_ALU32_sisi_sat               <"vsubh",    int_hexagon_A2_svsubhs>;
2210 def HEXAGON_A2_svsubuhs:
2211   si_ALU32_sisi_sat               <"vsubuh",   int_hexagon_A2_svsubuhs>;
2212
2213 /********************************************************************
2214 *            ALU64/ALU                                              *
2215 *********************************************************************/
2216
2217 // ALU64 / ALU / Add.
2218 def HEXAGON_A2_addp:
2219   di_ALU64_didi                   <"add",      int_hexagon_A2_addp>;
2220 def HEXAGON_A2_addsat:
2221   si_ALU64_sisi_sat               <"add",      int_hexagon_A2_addsat>;
2222
2223 // ALU64 / ALU / Add halfword.
2224 // Even though the definition says hl, it should be lh -
2225 //so DON'T change the class " si_ALU64_sisi_l16_lh " it inherits.
2226 def HEXAGON_A2_addh_l16_hl:
2227   si_ALU64_sisi_l16_lh            <"add",      int_hexagon_A2_addh_l16_hl>;
2228 def HEXAGON_A2_addh_l16_ll:
2229   si_ALU64_sisi_l16_ll            <"add",      int_hexagon_A2_addh_l16_ll>;
2230
2231 def HEXAGON_A2_addh_l16_sat_hl:
2232   si_ALU64_sisi_l16_sat_lh        <"add",      int_hexagon_A2_addh_l16_sat_hl>;
2233 def HEXAGON_A2_addh_l16_sat_ll:
2234   si_ALU64_sisi_l16_sat_ll        <"add",      int_hexagon_A2_addh_l16_sat_ll>;
2235
2236 def HEXAGON_A2_addh_h16_hh:
2237   si_ALU64_sisi_h16_hh            <"add",      int_hexagon_A2_addh_h16_hh>;
2238 def HEXAGON_A2_addh_h16_hl:
2239   si_ALU64_sisi_h16_hl            <"add",      int_hexagon_A2_addh_h16_hl>;
2240 def HEXAGON_A2_addh_h16_lh:
2241   si_ALU64_sisi_h16_lh            <"add",      int_hexagon_A2_addh_h16_lh>;
2242 def HEXAGON_A2_addh_h16_ll:
2243   si_ALU64_sisi_h16_ll            <"add",      int_hexagon_A2_addh_h16_ll>;
2244
2245 def HEXAGON_A2_addh_h16_sat_hh:
2246   si_ALU64_sisi_h16_sat_hh        <"add",      int_hexagon_A2_addh_h16_sat_hh>;
2247 def HEXAGON_A2_addh_h16_sat_hl:
2248   si_ALU64_sisi_h16_sat_hl        <"add",      int_hexagon_A2_addh_h16_sat_hl>;
2249 def HEXAGON_A2_addh_h16_sat_lh:
2250   si_ALU64_sisi_h16_sat_lh        <"add",      int_hexagon_A2_addh_h16_sat_lh>;
2251 def HEXAGON_A2_addh_h16_sat_ll:
2252   si_ALU64_sisi_h16_sat_ll        <"add",      int_hexagon_A2_addh_h16_sat_ll>;
2253
2254 // ALU64 / ALU / Compare.
2255 def HEXAGON_C2_cmpeqp:
2256   qi_ALU64_didi                   <"cmp.eq",   int_hexagon_C2_cmpeqp>;
2257 def HEXAGON_C2_cmpgtp:
2258   qi_ALU64_didi                   <"cmp.gt",   int_hexagon_C2_cmpgtp>;
2259 def HEXAGON_C2_cmpgtup:
2260   qi_ALU64_didi                   <"cmp.gtu",  int_hexagon_C2_cmpgtup>;
2261
2262 // ALU64 / ALU / Logical operations.
2263 def HEXAGON_A2_andp:
2264   di_ALU64_didi                   <"and",      int_hexagon_A2_andp>;
2265 def HEXAGON_A2_orp:
2266   di_ALU64_didi                   <"or",       int_hexagon_A2_orp>;
2267 def HEXAGON_A2_xorp:
2268   di_ALU64_didi                   <"xor",      int_hexagon_A2_xorp>;
2269
2270 // ALU64 / ALU / Maximum.
2271 def HEXAGON_A2_max:
2272   si_ALU64_sisi                   <"max",      int_hexagon_A2_max>;
2273 def HEXAGON_A2_maxu:
2274   si_ALU64_sisi                   <"maxu",     int_hexagon_A2_maxu>;
2275
2276 // ALU64 / ALU / Minimum.
2277 def HEXAGON_A2_min:
2278   si_ALU64_sisi                   <"min",      int_hexagon_A2_min>;
2279 def HEXAGON_A2_minu:
2280   si_ALU64_sisi                   <"minu",     int_hexagon_A2_minu>;
2281
2282 // ALU64 / ALU / Subtract.
2283 def HEXAGON_A2_subp:
2284   di_ALU64_didi                   <"sub",      int_hexagon_A2_subp>;
2285 def HEXAGON_A2_subsat:
2286   si_ALU64_sisi_sat               <"sub",      int_hexagon_A2_subsat>;
2287
2288 // ALU64 / ALU / Subtract halfword.
2289 // Even though the definition says hl, it should be lh -
2290 //so DON'T change the class " si_ALU64_sisi_l16_lh " it inherits.
2291 def HEXAGON_A2_subh_l16_hl:
2292   si_ALU64_sisi_l16_lh            <"sub",      int_hexagon_A2_subh_l16_hl>;
2293 def HEXAGON_A2_subh_l16_ll:
2294   si_ALU64_sisi_l16_ll            <"sub",      int_hexagon_A2_subh_l16_ll>;
2295
2296 def HEXAGON_A2_subh_l16_sat_hl:
2297   si_ALU64_sisi_l16_sat_lh        <"sub",      int_hexagon_A2_subh_l16_sat_hl>;
2298 def HEXAGON_A2_subh_l16_sat_ll:
2299   si_ALU64_sisi_l16_sat_ll        <"sub",      int_hexagon_A2_subh_l16_sat_ll>;
2300
2301 def HEXAGON_A2_subh_h16_hh:
2302   si_ALU64_sisi_h16_hh            <"sub",      int_hexagon_A2_subh_h16_hh>;
2303 def HEXAGON_A2_subh_h16_hl:
2304   si_ALU64_sisi_h16_hl            <"sub",      int_hexagon_A2_subh_h16_hl>;
2305 def HEXAGON_A2_subh_h16_lh:
2306   si_ALU64_sisi_h16_lh            <"sub",      int_hexagon_A2_subh_h16_lh>;
2307 def HEXAGON_A2_subh_h16_ll:
2308   si_ALU64_sisi_h16_ll            <"sub",      int_hexagon_A2_subh_h16_ll>;
2309
2310 def HEXAGON_A2_subh_h16_sat_hh:
2311   si_ALU64_sisi_h16_sat_hh        <"sub",      int_hexagon_A2_subh_h16_sat_hh>;
2312 def HEXAGON_A2_subh_h16_sat_hl:
2313   si_ALU64_sisi_h16_sat_hl        <"sub",      int_hexagon_A2_subh_h16_sat_hl>;
2314 def HEXAGON_A2_subh_h16_sat_lh:
2315   si_ALU64_sisi_h16_sat_lh        <"sub",      int_hexagon_A2_subh_h16_sat_lh>;
2316 def HEXAGON_A2_subh_h16_sat_ll:
2317   si_ALU64_sisi_h16_sat_ll        <"sub",      int_hexagon_A2_subh_h16_sat_ll>;
2318
2319 // ALU64 / ALU / Transfer register.
2320 def HEXAGON_A2_tfrp:
2321   di_ALU64_di                     <"",         int_hexagon_A2_tfrp>;
2322
2323 /********************************************************************
2324 *            ALU64/BIT                                              *
2325 *********************************************************************/
2326
2327 // ALU64 / BIT / Masked parity.
2328 def HEXAGON_S2_parityp:
2329   si_ALU64_didi                   <"parity",   int_hexagon_S2_parityp>;
2330
2331 /********************************************************************
2332 *            ALU64/PERM                                             *
2333 *********************************************************************/
2334
2335 // ALU64 / PERM / Vector pack high and low halfwords.
2336 def HEXAGON_S2_packhl:
2337   di_ALU64_sisi                   <"packhl",   int_hexagon_S2_packhl>;
2338
2339 /********************************************************************
2340 *            ALU64/VB                                               *
2341 *********************************************************************/
2342
2343 // ALU64 / VB / Vector add unsigned bytes.
2344 def HEXAGON_A2_vaddub:
2345   di_ALU64_didi                   <"vaddub",   int_hexagon_A2_vaddub>;
2346 def HEXAGON_A2_vaddubs:
2347   di_ALU64_didi_sat               <"vaddub",   int_hexagon_A2_vaddubs>;
2348
2349 // ALU64 / VB / Vector average unsigned bytes.
2350 def HEXAGON_A2_vavgub:
2351   di_ALU64_didi                   <"vavgub",   int_hexagon_A2_vavgub>;
2352 def HEXAGON_A2_vavgubr:
2353   di_ALU64_didi_rnd               <"vavgub",   int_hexagon_A2_vavgubr>;
2354
2355 // ALU64 / VB / Vector compare unsigned bytes.
2356 def HEXAGON_A2_vcmpbeq:
2357   qi_ALU64_didi                   <"vcmpb.eq", int_hexagon_A2_vcmpbeq>;
2358 def HEXAGON_A2_vcmpbgtu:
2359   qi_ALU64_didi                   <"vcmpb.gtu",int_hexagon_A2_vcmpbgtu>;
2360
2361 // ALU64 / VB / Vector maximum/minimum unsigned bytes.
2362 def HEXAGON_A2_vmaxub:
2363   di_ALU64_didi                   <"vmaxub",   int_hexagon_A2_vmaxub>;
2364 def HEXAGON_A2_vminub:
2365   di_ALU64_didi                   <"vminub",   int_hexagon_A2_vminub>;
2366
2367 // ALU64 / VB / Vector subtract unsigned bytes.
2368 def HEXAGON_A2_vsubub:
2369   di_ALU64_didi                   <"vsubub",   int_hexagon_A2_vsubub>;
2370 def HEXAGON_A2_vsububs:
2371   di_ALU64_didi_sat               <"vsubub",   int_hexagon_A2_vsububs>;
2372
2373 // ALU64 / VB / Vector mux.
2374 def HEXAGON_C2_vmux:
2375   di_ALU64_qididi                 <"vmux",     int_hexagon_C2_vmux>;
2376
2377
2378 /********************************************************************
2379 *            ALU64/VH                                               *
2380 *********************************************************************/
2381
2382 // ALU64 / VH / Vector add halfwords.
2383 // Rdd64=vadd[u]h(Rss64,Rtt64:sat]
2384 def HEXAGON_A2_vaddh:
2385   di_ALU64_didi                   <"vaddh",    int_hexagon_A2_vaddh>;
2386 def HEXAGON_A2_vaddhs:
2387   di_ALU64_didi_sat               <"vaddh",    int_hexagon_A2_vaddhs>;
2388 def HEXAGON_A2_vadduhs:
2389   di_ALU64_didi_sat               <"vadduh",   int_hexagon_A2_vadduhs>;
2390
2391 // ALU64 / VH / Vector average halfwords.
2392 // Rdd64=v[n]avg[u]h(Rss64,Rtt64:rnd/:crnd][:sat]
2393 def HEXAGON_A2_vavgh:
2394   di_ALU64_didi                   <"vavgh",    int_hexagon_A2_vavgh>;
2395 def HEXAGON_A2_vavghcr:
2396   di_ALU64_didi_crnd              <"vavgh",    int_hexagon_A2_vavghcr>;
2397 def HEXAGON_A2_vavghr:
2398   di_ALU64_didi_rnd               <"vavgh",    int_hexagon_A2_vavghr>;
2399 def HEXAGON_A2_vavguh:
2400   di_ALU64_didi                   <"vavguh",   int_hexagon_A2_vavguh>;
2401 def HEXAGON_A2_vavguhr:
2402   di_ALU64_didi_rnd               <"vavguh",   int_hexagon_A2_vavguhr>;
2403 def HEXAGON_A2_vnavgh:
2404   di_ALU64_didi                   <"vnavgh",   int_hexagon_A2_vnavgh>;
2405 def HEXAGON_A2_vnavghcr:
2406   di_ALU64_didi_crnd_sat          <"vnavgh",   int_hexagon_A2_vnavghcr>;
2407 def HEXAGON_A2_vnavghr:
2408   di_ALU64_didi_rnd_sat           <"vnavgh",   int_hexagon_A2_vnavghr>;
2409
2410 // ALU64 / VH / Vector compare halfwords.
2411 def HEXAGON_A2_vcmpheq:
2412   qi_ALU64_didi                   <"vcmph.eq", int_hexagon_A2_vcmpheq>;
2413 def HEXAGON_A2_vcmphgt:
2414   qi_ALU64_didi                   <"vcmph.gt", int_hexagon_A2_vcmphgt>;
2415 def HEXAGON_A2_vcmphgtu:
2416   qi_ALU64_didi                   <"vcmph.gtu",int_hexagon_A2_vcmphgtu>;
2417
2418 // ALU64 / VH / Vector maximum halfwords.
2419 def HEXAGON_A2_vmaxh:
2420   di_ALU64_didi                   <"vmaxh",    int_hexagon_A2_vmaxh>;
2421 def HEXAGON_A2_vmaxuh:
2422   di_ALU64_didi                   <"vmaxuh",   int_hexagon_A2_vmaxuh>;
2423
2424 // ALU64 / VH / Vector minimum halfwords.
2425 def HEXAGON_A2_vminh:
2426   di_ALU64_didi                   <"vminh",    int_hexagon_A2_vminh>;
2427 def HEXAGON_A2_vminuh:
2428   di_ALU64_didi                   <"vminuh",   int_hexagon_A2_vminuh>;
2429
2430 // ALU64 / VH / Vector subtract halfwords.
2431 def HEXAGON_A2_vsubh:
2432   di_ALU64_didi                   <"vsubh",    int_hexagon_A2_vsubh>;
2433 def HEXAGON_A2_vsubhs:
2434   di_ALU64_didi_sat               <"vsubh",    int_hexagon_A2_vsubhs>;
2435 def HEXAGON_A2_vsubuhs:
2436   di_ALU64_didi_sat               <"vsubuh",   int_hexagon_A2_vsubuhs>;
2437
2438
2439 /********************************************************************
2440 *            ALU64/VW                                               *
2441 *********************************************************************/
2442
2443 // ALU64 / VW / Vector add words.
2444 // Rdd32=vaddw(Rss32,Rtt32)[:sat]
2445 def HEXAGON_A2_vaddw:
2446   di_ALU64_didi                   <"vaddw",    int_hexagon_A2_vaddw>;
2447 def HEXAGON_A2_vaddws:
2448   di_ALU64_didi_sat               <"vaddw",   int_hexagon_A2_vaddws>;
2449
2450 // ALU64 / VW / Vector average words.
2451 def HEXAGON_A2_vavguw:
2452   di_ALU64_didi                   <"vavguw",   int_hexagon_A2_vavguw>;
2453 def HEXAGON_A2_vavguwr:
2454   di_ALU64_didi_rnd               <"vavguw",   int_hexagon_A2_vavguwr>;
2455 def HEXAGON_A2_vavgw:
2456   di_ALU64_didi                   <"vavgw",    int_hexagon_A2_vavgw>;
2457 def HEXAGON_A2_vavgwcr:
2458   di_ALU64_didi_crnd              <"vavgw",    int_hexagon_A2_vavgwcr>;
2459 def HEXAGON_A2_vavgwr:
2460   di_ALU64_didi_rnd               <"vavgw",    int_hexagon_A2_vavgwr>;
2461 def HEXAGON_A2_vnavgw:
2462   di_ALU64_didi                   <"vnavgw",   int_hexagon_A2_vnavgw>;
2463 def HEXAGON_A2_vnavgwcr:
2464   di_ALU64_didi_crnd_sat          <"vnavgw",   int_hexagon_A2_vnavgwcr>;
2465 def HEXAGON_A2_vnavgwr:
2466   di_ALU64_didi_rnd_sat           <"vnavgw",   int_hexagon_A2_vnavgwr>;
2467
2468 // ALU64 / VW / Vector compare words.
2469 def HEXAGON_A2_vcmpweq:
2470   qi_ALU64_didi                   <"vcmpw.eq", int_hexagon_A2_vcmpweq>;
2471 def HEXAGON_A2_vcmpwgt:
2472   qi_ALU64_didi                   <"vcmpw.gt", int_hexagon_A2_vcmpwgt>;
2473 def HEXAGON_A2_vcmpwgtu:
2474   qi_ALU64_didi                   <"vcmpw.gtu",int_hexagon_A2_vcmpwgtu>;
2475
2476 // ALU64 / VW / Vector maximum words.
2477 def HEXAGON_A2_vmaxw:
2478   di_ALU64_didi                   <"vmaxw",    int_hexagon_A2_vmaxw>;
2479 def HEXAGON_A2_vmaxuw:
2480   di_ALU64_didi                   <"vmaxuw",   int_hexagon_A2_vmaxuw>;
2481
2482 // ALU64 / VW / Vector minimum words.
2483 def HEXAGON_A2_vminw:
2484   di_ALU64_didi                   <"vminw",    int_hexagon_A2_vminw>;
2485 def HEXAGON_A2_vminuw:
2486   di_ALU64_didi                   <"vminuw",   int_hexagon_A2_vminuw>;
2487
2488 // ALU64 / VW / Vector subtract words.
2489 def HEXAGON_A2_vsubw:
2490   di_ALU64_didi                   <"vsubw",    int_hexagon_A2_vsubw>;
2491 def HEXAGON_A2_vsubws:
2492   di_ALU64_didi_sat               <"vsubw",    int_hexagon_A2_vsubws>;
2493
2494
2495 /********************************************************************
2496 *            CR                                                     *
2497 *********************************************************************/
2498
2499 // CR / Logical reductions on predicates.
2500 def HEXAGON_C2_all8:
2501   qi_SInst_qi                     <"all8",     int_hexagon_C2_all8>;
2502 def HEXAGON_C2_any8:
2503   qi_SInst_qi                     <"any8",     int_hexagon_C2_any8>;
2504
2505 // CR / Logical operations on predicates.
2506 def HEXAGON_C2_pxfer_map:
2507   qi_SInst_qi_pxfer               <"",         int_hexagon_C2_pxfer_map>;
2508 def HEXAGON_C2_and:
2509   qi_SInst_qiqi                   <"and",      int_hexagon_C2_and>;
2510 def HEXAGON_C2_andn:
2511   qi_SInst_qiqi_neg               <"and",      int_hexagon_C2_andn>;
2512 def HEXAGON_C2_not:
2513   qi_SInst_qi                     <"not",      int_hexagon_C2_not>;
2514 def HEXAGON_C2_or:
2515   qi_SInst_qiqi                   <"or",       int_hexagon_C2_or>;
2516 def HEXAGON_C2_orn:
2517   qi_SInst_qiqi_neg               <"or",       int_hexagon_C2_orn>;
2518 def HEXAGON_C2_xor:
2519   qi_SInst_qiqi                   <"xor",      int_hexagon_C2_xor>;
2520
2521
2522 /********************************************************************
2523 *            MTYPE/ALU                                              *
2524 *********************************************************************/
2525
2526 // MTYPE / ALU / Add and accumulate.
2527 def HEXAGON_M2_acci:
2528   si_MInst_sisisi_acc             <"add",      int_hexagon_M2_acci>;
2529 def HEXAGON_M2_accii:
2530   si_MInst_sisis8_acc             <"add",      int_hexagon_M2_accii>;
2531 def HEXAGON_M2_nacci:
2532   si_MInst_sisisi_nac             <"add",      int_hexagon_M2_nacci>;
2533 def HEXAGON_M2_naccii:
2534   si_MInst_sisis8_nac             <"add",      int_hexagon_M2_naccii>;
2535
2536 // MTYPE / ALU / Subtract and accumulate.
2537 def HEXAGON_M2_subacc:
2538   si_MInst_sisisi_acc             <"sub",      int_hexagon_M2_subacc>;
2539
2540 // MTYPE / ALU / Vector absolute difference.
2541 def HEXAGON_M2_vabsdiffh:
2542   di_MInst_didi                   <"vabsdiffh",int_hexagon_M2_vabsdiffh>;
2543 def HEXAGON_M2_vabsdiffw:
2544   di_MInst_didi                   <"vabsdiffw",int_hexagon_M2_vabsdiffw>;
2545
2546 // MTYPE / ALU / XOR and xor with destination.
2547 def HEXAGON_M2_xor_xacc:
2548   si_MInst_sisisi_xacc            <"xor",      int_hexagon_M2_xor_xacc>;
2549
2550
2551 /********************************************************************
2552 *            MTYPE/COMPLEX                                          *
2553 *********************************************************************/
2554
2555 // MTYPE / COMPLEX / Complex multiply.
2556 // Rdd[-+]=cmpy(Rs, Rt:<<1]:sat
2557 def HEXAGON_M2_cmpys_s1:
2558   di_MInst_sisi_s1_sat            <"cmpy",     int_hexagon_M2_cmpys_s1>;
2559 def HEXAGON_M2_cmpys_s0:
2560   di_MInst_sisi_sat               <"cmpy",     int_hexagon_M2_cmpys_s0>;
2561 def HEXAGON_M2_cmpysc_s1:
2562   di_MInst_sisi_s1_sat_conj       <"cmpy",     int_hexagon_M2_cmpysc_s1>;
2563 def HEXAGON_M2_cmpysc_s0:
2564   di_MInst_sisi_sat_conj          <"cmpy",     int_hexagon_M2_cmpysc_s0>;
2565
2566 def HEXAGON_M2_cmacs_s1:
2567   di_MInst_disisi_acc_s1_sat      <"cmpy",     int_hexagon_M2_cmacs_s1>;
2568 def HEXAGON_M2_cmacs_s0:
2569   di_MInst_disisi_acc_sat         <"cmpy",     int_hexagon_M2_cmacs_s0>;
2570 def HEXAGON_M2_cmacsc_s1:
2571   di_MInst_disisi_acc_s1_sat_conj <"cmpy",     int_hexagon_M2_cmacsc_s1>;
2572 def HEXAGON_M2_cmacsc_s0:
2573   di_MInst_disisi_acc_sat_conj    <"cmpy",     int_hexagon_M2_cmacsc_s0>;
2574
2575 def HEXAGON_M2_cnacs_s1:
2576   di_MInst_disisi_nac_s1_sat      <"cmpy",     int_hexagon_M2_cnacs_s1>;
2577 def HEXAGON_M2_cnacs_s0:
2578   di_MInst_disisi_nac_sat         <"cmpy",     int_hexagon_M2_cnacs_s0>;
2579 def HEXAGON_M2_cnacsc_s1:
2580   di_MInst_disisi_nac_s1_sat_conj <"cmpy",     int_hexagon_M2_cnacsc_s1>;
2581 def HEXAGON_M2_cnacsc_s0:
2582   di_MInst_disisi_nac_sat_conj    <"cmpy",     int_hexagon_M2_cnacsc_s0>;
2583
2584 // MTYPE / COMPLEX / Complex multiply real or imaginary.
2585 def HEXAGON_M2_cmpyr_s0:
2586   di_MInst_sisi                   <"cmpyr",    int_hexagon_M2_cmpyr_s0>;
2587 def HEXAGON_M2_cmacr_s0:
2588   di_MInst_disisi_acc             <"cmpyr",    int_hexagon_M2_cmacr_s0>;
2589
2590 def HEXAGON_M2_cmpyi_s0:
2591   di_MInst_sisi                   <"cmpyi",    int_hexagon_M2_cmpyi_s0>;
2592 def HEXAGON_M2_cmaci_s0:
2593   di_MInst_disisi_acc             <"cmpyi",    int_hexagon_M2_cmaci_s0>;
2594
2595 // MTYPE / COMPLEX / Complex multiply with round and pack.
2596 // Rxx32+=cmpy(Rs32,[*]Rt32:<<1]:rnd:sat
2597 def HEXAGON_M2_cmpyrs_s0:
2598   si_MInst_sisi_rnd_sat           <"cmpy",     int_hexagon_M2_cmpyrs_s0>;
2599 def HEXAGON_M2_cmpyrs_s1:
2600   si_MInst_sisi_s1_rnd_sat        <"cmpy",     int_hexagon_M2_cmpyrs_s1>;
2601
2602 def HEXAGON_M2_cmpyrsc_s0:
2603   si_MInst_sisi_rnd_sat_conj      <"cmpy",     int_hexagon_M2_cmpyrsc_s0>;
2604 def HEXAGON_M2_cmpyrsc_s1:
2605   si_MInst_sisi_s1_rnd_sat_conj   <"cmpy",     int_hexagon_M2_cmpyrsc_s1>;
2606
2607 //MTYPE / COMPLEX / Vector complex multiply real or imaginary.
2608 def HEXAGON_M2_vcmpy_s0_sat_i:
2609   di_MInst_didi_sat               <"vcmpyi",   int_hexagon_M2_vcmpy_s0_sat_i>;
2610 def HEXAGON_M2_vcmpy_s1_sat_i:
2611   di_MInst_didi_s1_sat            <"vcmpyi",   int_hexagon_M2_vcmpy_s1_sat_i>;
2612
2613 def HEXAGON_M2_vcmpy_s0_sat_r:
2614   di_MInst_didi_sat               <"vcmpyr",   int_hexagon_M2_vcmpy_s0_sat_r>;
2615 def HEXAGON_M2_vcmpy_s1_sat_r:
2616   di_MInst_didi_s1_sat            <"vcmpyr",   int_hexagon_M2_vcmpy_s1_sat_r>;
2617
2618 def HEXAGON_M2_vcmac_s0_sat_i:
2619   di_MInst_dididi_acc_sat         <"vcmpyi",   int_hexagon_M2_vcmac_s0_sat_i>;
2620 def HEXAGON_M2_vcmac_s0_sat_r:
2621   di_MInst_dididi_acc_sat         <"vcmpyr",   int_hexagon_M2_vcmac_s0_sat_r>;
2622
2623 //MTYPE / COMPLEX / Vector reduce complex multiply real or imaginary.
2624 def HEXAGON_M2_vrcmpyi_s0:
2625   di_MInst_didi                   <"vrcmpyi",  int_hexagon_M2_vrcmpyi_s0>;
2626 def HEXAGON_M2_vrcmpyr_s0:
2627   di_MInst_didi                   <"vrcmpyr",  int_hexagon_M2_vrcmpyr_s0>;
2628
2629 def HEXAGON_M2_vrcmpyi_s0c:
2630   di_MInst_didi_conj              <"vrcmpyi",  int_hexagon_M2_vrcmpyi_s0c>;
2631 def HEXAGON_M2_vrcmpyr_s0c:
2632   di_MInst_didi_conj              <"vrcmpyr",  int_hexagon_M2_vrcmpyr_s0c>;
2633
2634 def HEXAGON_M2_vrcmaci_s0:
2635   di_MInst_dididi_acc             <"vrcmpyi",  int_hexagon_M2_vrcmaci_s0>;
2636 def HEXAGON_M2_vrcmacr_s0:
2637   di_MInst_dididi_acc             <"vrcmpyr",  int_hexagon_M2_vrcmacr_s0>;
2638
2639 def HEXAGON_M2_vrcmaci_s0c:
2640   di_MInst_dididi_acc_conj        <"vrcmpyi",  int_hexagon_M2_vrcmaci_s0c>;
2641 def HEXAGON_M2_vrcmacr_s0c:
2642   di_MInst_dididi_acc_conj        <"vrcmpyr",  int_hexagon_M2_vrcmacr_s0c>;
2643
2644
2645 /********************************************************************
2646 *            MTYPE/MPYH                                             *
2647 *********************************************************************/
2648
2649 // MTYPE / MPYH / Multiply and use lower result.
2650 //def HEXAGON_M2_mpysmi:
2651 //FIXME: Hexagon_M2_mpysmi should really by of the type si_MInst_sim9,
2652 // not si_MInst_sis9 - but for now, we will use s9.
2653 // def Hexagon_M2_mpysmi:
2654 //  si_MInst_sim9                   <"mpyi",     int_hexagon_M2_mpysmi>;
2655 def Hexagon_M2_mpysmi:
2656   si_MInst_sis9                   <"mpyi",     int_hexagon_M2_mpysmi>;
2657 def HEXAGON_M2_mpyi:
2658   si_MInst_sisi                   <"mpyi",     int_hexagon_M2_mpyi>;
2659 def HEXAGON_M2_mpyui:
2660   si_MInst_sisi                   <"mpyui",    int_hexagon_M2_mpyui>;
2661 def HEXAGON_M2_macsip:
2662   si_MInst_sisiu8_acc             <"mpyi",     int_hexagon_M2_macsip>;
2663 def HEXAGON_M2_maci:
2664   si_MInst_sisisi_acc             <"mpyi",     int_hexagon_M2_maci>;
2665 def HEXAGON_M2_macsin:
2666   si_MInst_sisiu8_nac             <"mpyi",     int_hexagon_M2_macsin>;
2667
2668 // MTYPE / MPYH / Multiply word by half (32x16).
2669 //Rdd[+]=vmpywoh(Rss,Rtt)[:<<1][:rnd][:sat]
2670 //Rdd[+]=vmpyweh(Rss,Rtt)[:<<1][:rnd][:sat]
2671 def HEXAGON_M2_mmpyl_rs1:
2672   di_MInst_didi_s1_rnd_sat        <"vmpyweh",  int_hexagon_M2_mmpyl_rs1>;
2673 def HEXAGON_M2_mmpyl_s1:
2674   di_MInst_didi_s1_sat            <"vmpyweh",  int_hexagon_M2_mmpyl_s1>;
2675 def HEXAGON_M2_mmpyl_rs0:
2676   di_MInst_didi_rnd_sat           <"vmpyweh",  int_hexagon_M2_mmpyl_rs0>;
2677 def HEXAGON_M2_mmpyl_s0:
2678   di_MInst_didi_sat               <"vmpyweh",  int_hexagon_M2_mmpyl_s0>;
2679 def HEXAGON_M2_mmpyh_rs1:
2680   di_MInst_didi_s1_rnd_sat        <"vmpywoh",  int_hexagon_M2_mmpyh_rs1>;
2681 def HEXAGON_M2_mmpyh_s1:
2682   di_MInst_didi_s1_sat            <"vmpywoh",  int_hexagon_M2_mmpyh_s1>;
2683 def HEXAGON_M2_mmpyh_rs0:
2684   di_MInst_didi_rnd_sat           <"vmpywoh",  int_hexagon_M2_mmpyh_rs0>;
2685 def HEXAGON_M2_mmpyh_s0:
2686   di_MInst_didi_sat               <"vmpywoh",  int_hexagon_M2_mmpyh_s0>;
2687 def HEXAGON_M2_mmacls_rs1:
2688   di_MInst_dididi_acc_s1_rnd_sat  <"vmpyweh",  int_hexagon_M2_mmacls_rs1>;
2689 def HEXAGON_M2_mmacls_s1:
2690   di_MInst_dididi_acc_s1_sat      <"vmpyweh",  int_hexagon_M2_mmacls_s1>;
2691 def HEXAGON_M2_mmacls_rs0:
2692   di_MInst_dididi_acc_rnd_sat     <"vmpyweh",  int_hexagon_M2_mmacls_rs0>;
2693 def HEXAGON_M2_mmacls_s0:
2694   di_MInst_dididi_acc_sat         <"vmpyweh",  int_hexagon_M2_mmacls_s0>;
2695 def HEXAGON_M2_mmachs_rs1:
2696   di_MInst_dididi_acc_s1_rnd_sat  <"vmpywoh",  int_hexagon_M2_mmachs_rs1>;
2697 def HEXAGON_M2_mmachs_s1:
2698   di_MInst_dididi_acc_s1_sat      <"vmpywoh",  int_hexagon_M2_mmachs_s1>;
2699 def HEXAGON_M2_mmachs_rs0:
2700   di_MInst_dididi_acc_rnd_sat     <"vmpywoh",  int_hexagon_M2_mmachs_rs0>;
2701 def HEXAGON_M2_mmachs_s0:
2702   di_MInst_dididi_acc_sat         <"vmpywoh",  int_hexagon_M2_mmachs_s0>;
2703
2704 // MTYPE / MPYH / Multiply word by unsigned half (32x16).
2705 //Rdd[+]=vmpywouh(Rss,Rtt)[:<<1][:rnd][:sat]
2706 //Rdd[+]=vmpyweuh(Rss,Rtt)[:<<1][:rnd][:sat]
2707 def HEXAGON_M2_mmpyul_rs1:
2708   di_MInst_didi_s1_rnd_sat        <"vmpyweuh", int_hexagon_M2_mmpyul_rs1>;
2709 def HEXAGON_M2_mmpyul_s1:
2710   di_MInst_didi_s1_sat            <"vmpyweuh", int_hexagon_M2_mmpyul_s1>;
2711 def HEXAGON_M2_mmpyul_rs0:
2712   di_MInst_didi_rnd_sat           <"vmpyweuh", int_hexagon_M2_mmpyul_rs0>;
2713 def HEXAGON_M2_mmpyul_s0:
2714   di_MInst_didi_sat               <"vmpyweuh", int_hexagon_M2_mmpyul_s0>;
2715 def HEXAGON_M2_mmpyuh_rs1:
2716   di_MInst_didi_s1_rnd_sat        <"vmpywouh", int_hexagon_M2_mmpyuh_rs1>;
2717 def HEXAGON_M2_mmpyuh_s1:
2718   di_MInst_didi_s1_sat            <"vmpywouh", int_hexagon_M2_mmpyuh_s1>;
2719 def HEXAGON_M2_mmpyuh_rs0:
2720   di_MInst_didi_rnd_sat           <"vmpywouh", int_hexagon_M2_mmpyuh_rs0>;
2721 def HEXAGON_M2_mmpyuh_s0:
2722   di_MInst_didi_sat               <"vmpywouh", int_hexagon_M2_mmpyuh_s0>;
2723 def HEXAGON_M2_mmaculs_rs1:
2724   di_MInst_dididi_acc_s1_rnd_sat  <"vmpyweuh", int_hexagon_M2_mmaculs_rs1>;
2725 def HEXAGON_M2_mmaculs_s1:
2726   di_MInst_dididi_acc_s1_sat      <"vmpyweuh", int_hexagon_M2_mmaculs_s1>;
2727 def HEXAGON_M2_mmaculs_rs0:
2728   di_MInst_dididi_acc_rnd_sat     <"vmpyweuh", int_hexagon_M2_mmaculs_rs0>;
2729 def HEXAGON_M2_mmaculs_s0:
2730   di_MInst_dididi_acc_sat         <"vmpyweuh", int_hexagon_M2_mmaculs_s0>;
2731 def HEXAGON_M2_mmacuhs_rs1:
2732   di_MInst_dididi_acc_s1_rnd_sat  <"vmpywouh", int_hexagon_M2_mmacuhs_rs1>;
2733 def HEXAGON_M2_mmacuhs_s1:
2734   di_MInst_dididi_acc_s1_sat      <"vmpywouh", int_hexagon_M2_mmacuhs_s1>;
2735 def HEXAGON_M2_mmacuhs_rs0:
2736   di_MInst_dididi_acc_rnd_sat     <"vmpywouh", int_hexagon_M2_mmacuhs_rs0>;
2737 def HEXAGON_M2_mmacuhs_s0:
2738   di_MInst_dididi_acc_sat         <"vmpywouh", int_hexagon_M2_mmacuhs_s0>;
2739
2740 // MTYPE / MPYH / Multiply and use upper result.
2741 def HEXAGON_M2_hmmpyh_rs1:
2742   si_MInst_sisi_h_s1_rnd_sat      <"mpy",      int_hexagon_M2_hmmpyh_rs1>;
2743 def HEXAGON_M2_hmmpyl_rs1:
2744   si_MInst_sisi_l_s1_rnd_sat      <"mpy",      int_hexagon_M2_hmmpyl_rs1>;
2745 def HEXAGON_M2_mpy_up:
2746   si_MInst_sisi                   <"mpy",      int_hexagon_M2_mpy_up>;
2747 def HEXAGON_M2_dpmpyss_rnd_s0:
2748   si_MInst_sisi_rnd               <"mpy",      int_hexagon_M2_dpmpyss_rnd_s0>;
2749 def HEXAGON_M2_mpyu_up:
2750   si_MInst_sisi                   <"mpyu",     int_hexagon_M2_mpyu_up>;
2751
2752 // MTYPE / MPYH / Multiply and use full result.
2753 def HEXAGON_M2_dpmpyuu_s0:
2754   di_MInst_sisi                   <"mpyu",     int_hexagon_M2_dpmpyuu_s0>;
2755 def HEXAGON_M2_dpmpyuu_acc_s0:
2756   di_MInst_disisi_acc             <"mpyu",     int_hexagon_M2_dpmpyuu_acc_s0>;
2757 def HEXAGON_M2_dpmpyuu_nac_s0:
2758   di_MInst_disisi_nac             <"mpyu",     int_hexagon_M2_dpmpyuu_nac_s0>;
2759 def HEXAGON_M2_dpmpyss_s0:
2760   di_MInst_sisi                   <"mpy",      int_hexagon_M2_dpmpyss_s0>;
2761 def HEXAGON_M2_dpmpyss_acc_s0:
2762   di_MInst_disisi_acc             <"mpy",      int_hexagon_M2_dpmpyss_acc_s0>;
2763 def HEXAGON_M2_dpmpyss_nac_s0:
2764   di_MInst_disisi_nac             <"mpy",      int_hexagon_M2_dpmpyss_nac_s0>;
2765
2766 /********************************************************************
2767 *            MTYPE/VB                                               *
2768 *********************************************************************/
2769
2770 // MTYPE / VB / Vector reduce add unsigned bytes.
2771 def HEXAGON_A2_vraddub:
2772   di_MInst_didi                   <"vraddub", int_hexagon_A2_vraddub>;
2773 def HEXAGON_A2_vraddub_acc:
2774   di_MInst_dididi_acc             <"vraddub", int_hexagon_A2_vraddub_acc>;
2775
2776 // MTYPE / VB / Vector sum of absolute differences unsigned bytes.
2777 def HEXAGON_A2_vrsadub:
2778   di_MInst_didi                   <"vrsadub", int_hexagon_A2_vrsadub>;
2779 def HEXAGON_A2_vrsadub_acc:
2780   di_MInst_dididi_acc             <"vrsadub", int_hexagon_A2_vrsadub_acc>;
2781
2782 /********************************************************************
2783 *            MTYPE/VH                                               *
2784 *********************************************************************/
2785
2786 // MTYPE / VH / Vector dual multiply.
2787 def HEXAGON_M2_vdmpys_s1:
2788   di_MInst_didi_s1_sat            <"vdmpy",   int_hexagon_M2_vdmpys_s1>;
2789 def HEXAGON_M2_vdmpys_s0:
2790   di_MInst_didi_sat               <"vdmpy",   int_hexagon_M2_vdmpys_s0>;
2791 def HEXAGON_M2_vdmacs_s1:
2792   di_MInst_dididi_acc_s1_sat      <"vdmpy",   int_hexagon_M2_vdmacs_s1>;
2793 def HEXAGON_M2_vdmacs_s0:
2794   di_MInst_dididi_acc_sat         <"vdmpy",   int_hexagon_M2_vdmacs_s0>;
2795
2796 // MTYPE / VH / Vector dual multiply with round and pack.
2797 def HEXAGON_M2_vdmpyrs_s0:
2798   si_MInst_didi_rnd_sat           <"vdmpy",   int_hexagon_M2_vdmpyrs_s0>;
2799 def HEXAGON_M2_vdmpyrs_s1:
2800   si_MInst_didi_s1_rnd_sat        <"vdmpy",   int_hexagon_M2_vdmpyrs_s1>;
2801
2802 // MTYPE / VH / Vector multiply even halfwords.
2803 def HEXAGON_M2_vmpy2es_s1:
2804   di_MInst_didi_s1_sat            <"vmpyeh",  int_hexagon_M2_vmpy2es_s1>;
2805 def HEXAGON_M2_vmpy2es_s0:
2806   di_MInst_didi_sat               <"vmpyeh",  int_hexagon_M2_vmpy2es_s0>;
2807 def HEXAGON_M2_vmac2es:
2808   di_MInst_dididi_acc             <"vmpyeh",  int_hexagon_M2_vmac2es>;
2809 def HEXAGON_M2_vmac2es_s1:
2810   di_MInst_dididi_acc_s1_sat      <"vmpyeh",  int_hexagon_M2_vmac2es_s1>;
2811 def HEXAGON_M2_vmac2es_s0:
2812   di_MInst_dididi_acc_sat         <"vmpyeh",  int_hexagon_M2_vmac2es_s0>;
2813
2814 // MTYPE / VH / Vector multiply halfwords.
2815 def HEXAGON_M2_vmpy2s_s0:
2816   di_MInst_sisi_sat               <"vmpyh",   int_hexagon_M2_vmpy2s_s0>;
2817 def HEXAGON_M2_vmpy2s_s1:
2818   di_MInst_sisi_s1_sat            <"vmpyh",   int_hexagon_M2_vmpy2s_s1>;
2819 def HEXAGON_M2_vmac2:
2820   di_MInst_disisi_acc             <"vmpyh",   int_hexagon_M2_vmac2>;
2821 def HEXAGON_M2_vmac2s_s0:
2822   di_MInst_disisi_acc_sat         <"vmpyh",   int_hexagon_M2_vmac2s_s0>;
2823 def HEXAGON_M2_vmac2s_s1:
2824   di_MInst_disisi_acc_s1_sat      <"vmpyh",   int_hexagon_M2_vmac2s_s1>;
2825
2826 // MTYPE / VH / Vector multiply halfwords with round and pack.
2827 def HEXAGON_M2_vmpy2s_s0pack:
2828   si_MInst_sisi_rnd_sat           <"vmpyh",   int_hexagon_M2_vmpy2s_s0pack>;
2829 def HEXAGON_M2_vmpy2s_s1pack:
2830   si_MInst_sisi_s1_rnd_sat        <"vmpyh",   int_hexagon_M2_vmpy2s_s1pack>;
2831
2832 // MTYPE / VH / Vector reduce multiply halfwords.
2833 // Rxx32+=vrmpyh(Rss32,Rtt32)
2834 def HEXAGON_M2_vrmpy_s0:
2835   di_MInst_didi                   <"vrmpyh",  int_hexagon_M2_vrmpy_s0>;
2836 def HEXAGON_M2_vrmac_s0:
2837   di_MInst_dididi_acc             <"vrmpyh",  int_hexagon_M2_vrmac_s0>;
2838
2839
2840 /********************************************************************
2841 *            STYPE/ALU                                              *
2842 *********************************************************************/
2843
2844 // STYPE / ALU / Absolute value.
2845 def HEXAGON_A2_abs:
2846   si_SInst_si                     <"abs",     int_hexagon_A2_abs>;
2847 def HEXAGON_A2_absp:
2848   di_SInst_di                     <"abs",     int_hexagon_A2_absp>;
2849 def HEXAGON_A2_abssat:
2850   si_SInst_si_sat                 <"abs",     int_hexagon_A2_abssat>;
2851
2852 // STYPE / ALU / Negate.
2853 def HEXAGON_A2_negp:
2854   di_SInst_di                     <"neg",     int_hexagon_A2_negp>;
2855 def HEXAGON_A2_negsat:
2856   si_SInst_si_sat                 <"neg",     int_hexagon_A2_negsat>;
2857
2858 // STYPE / ALU / Logical Not.
2859 def HEXAGON_A2_notp:
2860   di_SInst_di                     <"not",     int_hexagon_A2_notp>;
2861
2862 // STYPE / ALU / Sign extend word to doubleword.
2863 def HEXAGON_A2_sxtw:
2864   di_SInst_si                     <"sxtw",     int_hexagon_A2_sxtw>;
2865
2866
2867 /********************************************************************
2868 *            STYPE/BIT                                              *
2869 *********************************************************************/
2870
2871 // STYPE / BIT / Count leading.
2872 def HEXAGON_S2_cl0:
2873   si_SInst_si                     <"cl0",     int_hexagon_S2_cl0>;
2874 def HEXAGON_S2_cl0p:
2875   si_SInst_di                     <"cl0",     int_hexagon_S2_cl0p>;
2876 def HEXAGON_S2_cl1:
2877   si_SInst_si                     <"cl1",     int_hexagon_S2_cl1>;
2878 def HEXAGON_S2_cl1p:
2879   si_SInst_di                     <"cl1",     int_hexagon_S2_cl1p>;
2880 def HEXAGON_S2_clb:
2881   si_SInst_si                     <"clb",     int_hexagon_S2_clb>;
2882 def HEXAGON_S2_clbp:
2883   si_SInst_di                     <"clb",     int_hexagon_S2_clbp>;
2884 def HEXAGON_S2_clbnorm:
2885   si_SInst_si                     <"normamt", int_hexagon_S2_clbnorm>;
2886
2887 // STYPE / BIT / Count trailing.
2888 def HEXAGON_S2_ct0:
2889   si_SInst_si                     <"ct0",     int_hexagon_S2_ct0>;
2890 def HEXAGON_S2_ct1:
2891   si_SInst_si                     <"ct1",     int_hexagon_S2_ct1>;
2892
2893 // STYPE / BIT / Compare bit mask.
2894 def Hexagon_C2_bitsclr:
2895   qi_SInst_sisi                   <"bitsclr", int_hexagon_C2_bitsclr>;
2896 def Hexagon_C2_bitsclri:
2897   qi_SInst_siu6                   <"bitsclr", int_hexagon_C2_bitsclri>;
2898 def Hexagon_C2_bitsset:
2899   qi_SInst_sisi                   <"bitsset", int_hexagon_C2_bitsset>;
2900
2901 // STYPE / BIT / Extract unsigned.
2902 // Rd[d][32/64]=extractu(Rs[s],Rt[t],[imm])
2903 def HEXAGON_S2_extractu:
2904   si_SInst_siu5u5                 <"extractu",int_hexagon_S2_extractu>;
2905 def HEXAGON_S2_extractu_rp:
2906   si_SInst_sidi                   <"extractu",int_hexagon_S2_extractu_rp>;
2907 def HEXAGON_S2_extractup:
2908   di_SInst_diu6u6                 <"extractu",int_hexagon_S2_extractup>;
2909 def HEXAGON_S2_extractup_rp:
2910   di_SInst_didi                   <"extractu",int_hexagon_S2_extractup_rp>;
2911
2912 // STYPE / BIT / Insert bitfield.
2913 def Hexagon_S2_insert:
2914   si_SInst_sisiu5u5               <"insert",  int_hexagon_S2_insert>;
2915 def Hexagon_S2_insert_rp:
2916   si_SInst_sisidi                 <"insert",  int_hexagon_S2_insert_rp>;
2917 def Hexagon_S2_insertp:
2918   di_SInst_didiu6u6               <"insert",  int_hexagon_S2_insertp>;
2919 def Hexagon_S2_insertp_rp:
2920   di_SInst_dididi                 <"insert",  int_hexagon_S2_insertp_rp>;
2921
2922 // STYPE / BIT / Innterleave/deinterleave.
2923 def Hexagon_S2_interleave:
2924   di_SInst_di                     <"interleave", int_hexagon_S2_interleave>;
2925 def Hexagon_S2_deinterleave:
2926   di_SInst_di                     <"deinterleave", int_hexagon_S2_deinterleave>;
2927
2928 // STYPE / BIT / Linear feedback-shift Iteration.
2929 def Hexagon_S2_lfsp:
2930   di_SInst_didi                   <"lfs",     int_hexagon_S2_lfsp>;
2931
2932 // STYPE / BIT / Bit reverse.
2933 def Hexagon_S2_brev:
2934   si_SInst_si                     <"brev",    int_hexagon_S2_brev>;
2935
2936 // STYPE / BIT / Set/Clear/Toggle Bit.
2937 def HEXAGON_S2_setbit_i:
2938   si_SInst_siu5                   <"setbit",  int_hexagon_S2_setbit_i>;
2939 def HEXAGON_S2_togglebit_i:
2940   si_SInst_siu5                   <"togglebit", int_hexagon_S2_togglebit_i>;
2941 def HEXAGON_S2_clrbit_i:
2942   si_SInst_siu5                   <"clrbit",  int_hexagon_S2_clrbit_i>;
2943 def HEXAGON_S2_setbit_r:
2944   si_SInst_sisi                   <"setbit",  int_hexagon_S2_setbit_r>;
2945 def HEXAGON_S2_togglebit_r:
2946   si_SInst_sisi                   <"togglebit", int_hexagon_S2_togglebit_r>;
2947 def HEXAGON_S2_clrbit_r:
2948   si_SInst_sisi                   <"clrbit",  int_hexagon_S2_clrbit_r>;
2949
2950 // STYPE / BIT / Test Bit.
2951 def HEXAGON_S2_tstbit_i:
2952   qi_SInst_siu5                   <"tstbit",  int_hexagon_S2_tstbit_i>;
2953 def HEXAGON_S2_tstbit_r:
2954   qi_SInst_sisi                   <"tstbit",  int_hexagon_S2_tstbit_r>;
2955
2956
2957 /********************************************************************
2958 *            STYPE/COMPLEX                                          *
2959 *********************************************************************/
2960
2961 // STYPE / COMPLEX / Vector Complex conjugate.
2962 def HEXAGON_A2_vconj:
2963   di_SInst_di_sat                 <"vconj",   int_hexagon_A2_vconj>;
2964
2965 // STYPE / COMPLEX / Vector Complex rotate.
2966 def HEXAGON_S2_vcrotate:
2967   di_SInst_disi                   <"vcrotate",int_hexagon_S2_vcrotate>;
2968
2969
2970 /********************************************************************
2971 *            STYPE/PERM                                             *
2972 *********************************************************************/
2973
2974 // STYPE / PERM / Saturate.
2975 def HEXAGON_A2_sat:
2976   si_SInst_di                     <"sat",     int_hexagon_A2_sat>;
2977 def HEXAGON_A2_satb:
2978   si_SInst_si                     <"satb",    int_hexagon_A2_satb>;
2979 def HEXAGON_A2_sath:
2980   si_SInst_si                     <"sath",    int_hexagon_A2_sath>;
2981 def HEXAGON_A2_satub:
2982   si_SInst_si                     <"satub",   int_hexagon_A2_satub>;
2983 def HEXAGON_A2_satuh:
2984   si_SInst_si                     <"satuh",   int_hexagon_A2_satuh>;
2985
2986 // STYPE / PERM / Swizzle bytes.
2987 def HEXAGON_A2_swiz:
2988   si_SInst_si                     <"swiz",    int_hexagon_A2_swiz>;
2989
2990 // STYPE / PERM / Vector align.
2991 // Need custom lowering
2992 def HEXAGON_S2_valignib:
2993   di_SInst_didiu3                 <"valignb", int_hexagon_S2_valignib>;
2994 def HEXAGON_S2_valignrb:
2995   di_SInst_didiqi                 <"valignb", int_hexagon_S2_valignrb>;
2996
2997 // STYPE / PERM / Vector round and pack.
2998 def HEXAGON_S2_vrndpackwh:
2999   si_SInst_di                     <"vrndwh",  int_hexagon_S2_vrndpackwh>;
3000 def HEXAGON_S2_vrndpackwhs:
3001   si_SInst_di_sat                 <"vrndwh",  int_hexagon_S2_vrndpackwhs>;
3002
3003 // STYPE / PERM / Vector saturate and pack.
3004 def HEXAGON_S2_svsathb:
3005   si_SInst_si                     <"vsathb",  int_hexagon_S2_svsathb>;
3006 def HEXAGON_S2_vsathb:
3007   si_SInst_di                     <"vsathb",  int_hexagon_S2_vsathb>;
3008 def HEXAGON_S2_svsathub:
3009   si_SInst_si                     <"vsathub", int_hexagon_S2_svsathub>;
3010 def HEXAGON_S2_vsathub:
3011   si_SInst_di                     <"vsathub", int_hexagon_S2_vsathub>;
3012 def HEXAGON_S2_vsatwh:
3013   si_SInst_di                     <"vsatwh",  int_hexagon_S2_vsatwh>;
3014 def HEXAGON_S2_vsatwuh:
3015   si_SInst_di                     <"vsatwuh", int_hexagon_S2_vsatwuh>;
3016
3017 // STYPE / PERM / Vector saturate without pack.
3018 def HEXAGON_S2_vsathb_nopack:
3019   di_SInst_di                     <"vsathb",  int_hexagon_S2_vsathb_nopack>;
3020 def HEXAGON_S2_vsathub_nopack:
3021   di_SInst_di                     <"vsathub", int_hexagon_S2_vsathub_nopack>;
3022 def HEXAGON_S2_vsatwh_nopack:
3023   di_SInst_di                     <"vsatwh",  int_hexagon_S2_vsatwh_nopack>;
3024 def HEXAGON_S2_vsatwuh_nopack:
3025   di_SInst_di                     <"vsatwuh", int_hexagon_S2_vsatwuh_nopack>;
3026
3027 // STYPE / PERM / Vector shuffle.
3028 def HEXAGON_S2_shuffeb:
3029   di_SInst_didi                   <"shuffeb", int_hexagon_S2_shuffeb>;
3030 def HEXAGON_S2_shuffeh:
3031   di_SInst_didi                   <"shuffeh", int_hexagon_S2_shuffeh>;
3032 def HEXAGON_S2_shuffob:
3033   di_SInst_didi                   <"shuffob", int_hexagon_S2_shuffob>;
3034 def HEXAGON_S2_shuffoh:
3035   di_SInst_didi                   <"shuffoh", int_hexagon_S2_shuffoh>;
3036
3037 // STYPE / PERM / Vector splat bytes.
3038 def HEXAGON_S2_vsplatrb:
3039   si_SInst_si                     <"vsplatb", int_hexagon_S2_vsplatrb>;
3040
3041 // STYPE / PERM / Vector splat halfwords.
3042 def HEXAGON_S2_vsplatrh:
3043   di_SInst_si                     <"vsplath", int_hexagon_S2_vsplatrh>;
3044
3045 // STYPE / PERM / Vector splice.
3046 def Hexagon_S2_vsplicerb:
3047   di_SInst_didiqi                 <"vspliceb",int_hexagon_S2_vsplicerb>;
3048 def Hexagon_S2_vspliceib:
3049   di_SInst_didiu3                 <"vspliceb",int_hexagon_S2_vspliceib>;
3050
3051 // STYPE / PERM / Sign extend.
3052 def HEXAGON_S2_vsxtbh:
3053   di_SInst_si                     <"vsxtbh",  int_hexagon_S2_vsxtbh>;
3054 def HEXAGON_S2_vsxthw:
3055   di_SInst_si                     <"vsxthw",  int_hexagon_S2_vsxthw>;
3056
3057 // STYPE / PERM / Truncate.
3058 def HEXAGON_S2_vtrunehb:
3059   si_SInst_di                     <"vtrunehb",int_hexagon_S2_vtrunehb>;
3060 def HEXAGON_S2_vtrunohb:
3061   si_SInst_di                     <"vtrunohb",int_hexagon_S2_vtrunohb>;
3062 def HEXAGON_S2_vtrunewh:
3063   di_SInst_didi                   <"vtrunewh",int_hexagon_S2_vtrunewh>;
3064 def HEXAGON_S2_vtrunowh:
3065   di_SInst_didi                   <"vtrunowh",int_hexagon_S2_vtrunowh>;
3066
3067 // STYPE / PERM / Zero extend.
3068 def HEXAGON_S2_vzxtbh:
3069   di_SInst_si                     <"vzxtbh",  int_hexagon_S2_vzxtbh>;
3070 def HEXAGON_S2_vzxthw:
3071   di_SInst_si                     <"vzxthw",  int_hexagon_S2_vzxthw>;
3072
3073
3074 /********************************************************************
3075 *            STYPE/PRED                                             *
3076 *********************************************************************/
3077
3078 // STYPE / PRED / Mask generate from predicate.
3079 def HEXAGON_C2_mask:
3080   di_SInst_qi                     <"mask",   int_hexagon_C2_mask>;
3081
3082 // STYPE / PRED / Predicate transfer.
3083 def HEXAGON_C2_tfrpr:
3084   si_SInst_qi                     <"",       int_hexagon_C2_tfrpr>;
3085 def HEXAGON_C2_tfrrp:
3086   qi_SInst_si                     <"",       int_hexagon_C2_tfrrp>;
3087
3088 // STYPE / PRED / Viterbi pack even and odd predicate bits.
3089 def HEXAGON_C2_vitpack:
3090   si_SInst_qiqi                   <"vitpack",int_hexagon_C2_vitpack>;
3091
3092
3093 /********************************************************************
3094 *            STYPE/SHIFT                                            *
3095 *********************************************************************/
3096
3097 // STYPE / SHIFT / Shift by immediate.
3098 def HEXAGON_S2_asl_i_r:
3099   si_SInst_siu5                   <"asl",     int_hexagon_S2_asl_i_r>;
3100 def HEXAGON_S2_asr_i_r:
3101   si_SInst_siu5                   <"asr",     int_hexagon_S2_asr_i_r>;
3102 def HEXAGON_S2_lsr_i_r:
3103   si_SInst_siu5                   <"lsr",     int_hexagon_S2_lsr_i_r>;
3104 def HEXAGON_S2_asl_i_p:
3105   di_SInst_diu6                   <"asl",     int_hexagon_S2_asl_i_p>;
3106 def HEXAGON_S2_asr_i_p:
3107   di_SInst_diu6                   <"asr",     int_hexagon_S2_asr_i_p>;
3108 def HEXAGON_S2_lsr_i_p:
3109   di_SInst_diu6                   <"lsr",     int_hexagon_S2_lsr_i_p>;
3110
3111 // STYPE / SHIFT / Shift by immediate and accumulate.
3112 def HEXAGON_S2_asl_i_r_acc:
3113   si_SInst_sisiu5_acc             <"asl",     int_hexagon_S2_asl_i_r_acc>;
3114 def HEXAGON_S2_asr_i_r_acc:
3115   si_SInst_sisiu5_acc             <"asr",     int_hexagon_S2_asr_i_r_acc>;
3116 def HEXAGON_S2_lsr_i_r_acc:
3117   si_SInst_sisiu5_acc             <"lsr",     int_hexagon_S2_lsr_i_r_acc>;
3118 def HEXAGON_S2_asl_i_r_nac:
3119   si_SInst_sisiu5_nac             <"asl",     int_hexagon_S2_asl_i_r_nac>;
3120 def HEXAGON_S2_asr_i_r_nac:
3121   si_SInst_sisiu5_nac             <"asr",     int_hexagon_S2_asr_i_r_nac>;
3122 def HEXAGON_S2_lsr_i_r_nac:
3123   si_SInst_sisiu5_nac             <"lsr",     int_hexagon_S2_lsr_i_r_nac>;
3124 def HEXAGON_S2_asl_i_p_acc:
3125   di_SInst_didiu6_acc             <"asl",     int_hexagon_S2_asl_i_p_acc>;
3126 def HEXAGON_S2_asr_i_p_acc:
3127   di_SInst_didiu6_acc             <"asr",     int_hexagon_S2_asr_i_p_acc>;
3128 def HEXAGON_S2_lsr_i_p_acc:
3129   di_SInst_didiu6_acc             <"lsr",     int_hexagon_S2_lsr_i_p_acc>;
3130 def HEXAGON_S2_asl_i_p_nac:
3131   di_SInst_didiu6_nac             <"asl",     int_hexagon_S2_asl_i_p_nac>;
3132 def HEXAGON_S2_asr_i_p_nac:
3133   di_SInst_didiu6_nac             <"asr",     int_hexagon_S2_asr_i_p_nac>;
3134 def HEXAGON_S2_lsr_i_p_nac:
3135   di_SInst_didiu6_nac             <"lsr",     int_hexagon_S2_lsr_i_p_nac>;
3136
3137 // STYPE / SHIFT / Shift by immediate and add.
3138 def HEXAGON_S2_addasl_rrri:
3139   si_SInst_sisiu3                 <"addasl",  int_hexagon_S2_addasl_rrri>;
3140
3141 // STYPE / SHIFT / Shift by immediate and logical.
3142 def HEXAGON_S2_asl_i_r_and:
3143   si_SInst_sisiu5_and             <"asl",     int_hexagon_S2_asl_i_r_and>;
3144 def HEXAGON_S2_asr_i_r_and:
3145   si_SInst_sisiu5_and             <"asr",     int_hexagon_S2_asr_i_r_and>;
3146 def HEXAGON_S2_lsr_i_r_and:
3147   si_SInst_sisiu5_and             <"lsr",     int_hexagon_S2_lsr_i_r_and>;
3148
3149 def HEXAGON_S2_asl_i_r_xacc:
3150   si_SInst_sisiu5_xor             <"asl",     int_hexagon_S2_asl_i_r_xacc>;
3151 def HEXAGON_S2_lsr_i_r_xacc:
3152   si_SInst_sisiu5_xor             <"lsr",     int_hexagon_S2_lsr_i_r_xacc>;
3153
3154 def HEXAGON_S2_asl_i_r_or:
3155   si_SInst_sisiu5_or              <"asl",     int_hexagon_S2_asl_i_r_or>;
3156 def HEXAGON_S2_asr_i_r_or:
3157   si_SInst_sisiu5_or              <"asr",     int_hexagon_S2_asr_i_r_or>;
3158 def HEXAGON_S2_lsr_i_r_or:
3159   si_SInst_sisiu5_or              <"lsr",     int_hexagon_S2_lsr_i_r_or>;
3160
3161 def HEXAGON_S2_asl_i_p_and:
3162   di_SInst_didiu6_and             <"asl",     int_hexagon_S2_asl_i_p_and>;
3163 def HEXAGON_S2_asr_i_p_and:
3164   di_SInst_didiu6_and             <"asr",     int_hexagon_S2_asr_i_p_and>;
3165 def HEXAGON_S2_lsr_i_p_and:
3166   di_SInst_didiu6_and             <"lsr",     int_hexagon_S2_lsr_i_p_and>;
3167
3168 def HEXAGON_S2_asl_i_p_xacc:
3169   di_SInst_didiu6_xor             <"asl",     int_hexagon_S2_asl_i_p_xacc>;
3170 def HEXAGON_S2_lsr_i_p_xacc:
3171   di_SInst_didiu6_xor             <"lsr",     int_hexagon_S2_lsr_i_p_xacc>;
3172
3173 def HEXAGON_S2_asl_i_p_or:
3174   di_SInst_didiu6_or              <"asl",     int_hexagon_S2_asl_i_p_or>;
3175 def HEXAGON_S2_asr_i_p_or:
3176   di_SInst_didiu6_or              <"asr",     int_hexagon_S2_asr_i_p_or>;
3177 def HEXAGON_S2_lsr_i_p_or:
3178   di_SInst_didiu6_or              <"lsr",     int_hexagon_S2_lsr_i_p_or>;
3179
3180 // STYPE / SHIFT / Shift right by immediate with rounding.
3181 def HEXAGON_S2_asr_i_r_rnd:
3182   si_SInst_siu5_rnd               <"asr",     int_hexagon_S2_asr_i_r_rnd>;
3183 def HEXAGON_S2_asr_i_r_rnd_goodsyntax:
3184   si_SInst_siu5              <"asrrnd",  int_hexagon_S2_asr_i_r_rnd_goodsyntax>;
3185
3186 // STYPE / SHIFT / Shift left by immediate with saturation.
3187 def HEXAGON_S2_asl_i_r_sat:
3188   si_SInst_sisi_sat               <"asl",     int_hexagon_S2_asl_i_r_sat>;
3189
3190 // STYPE / SHIFT / Shift by register.
3191 def HEXAGON_S2_asl_r_r:
3192   si_SInst_sisi                   <"asl",     int_hexagon_S2_asl_r_r>;
3193 def HEXAGON_S2_asr_r_r:
3194   si_SInst_sisi                   <"asr",     int_hexagon_S2_asr_r_r>;
3195 def HEXAGON_S2_lsl_r_r:
3196   si_SInst_sisi                   <"lsl",     int_hexagon_S2_lsl_r_r>;
3197 def HEXAGON_S2_lsr_r_r:
3198   si_SInst_sisi                   <"lsr",     int_hexagon_S2_lsr_r_r>;
3199 def HEXAGON_S2_asl_r_p:
3200   di_SInst_disi                   <"asl",     int_hexagon_S2_asl_r_p>;
3201 def HEXAGON_S2_asr_r_p:
3202   di_SInst_disi                   <"asr",     int_hexagon_S2_asr_r_p>;
3203 def HEXAGON_S2_lsl_r_p:
3204   di_SInst_disi                   <"lsl",     int_hexagon_S2_lsl_r_p>;
3205 def HEXAGON_S2_lsr_r_p:
3206   di_SInst_disi                   <"lsr",     int_hexagon_S2_lsr_r_p>;
3207
3208 // STYPE / SHIFT / Shift by register and accumulate.
3209 def HEXAGON_S2_asl_r_r_acc:
3210   si_SInst_sisisi_acc             <"asl",     int_hexagon_S2_asl_r_r_acc>;
3211 def HEXAGON_S2_asr_r_r_acc:
3212   si_SInst_sisisi_acc             <"asr",     int_hexagon_S2_asr_r_r_acc>;
3213 def HEXAGON_S2_lsl_r_r_acc:
3214   si_SInst_sisisi_acc             <"lsl",     int_hexagon_S2_lsl_r_r_acc>;
3215 def HEXAGON_S2_lsr_r_r_acc:
3216   si_SInst_sisisi_acc             <"lsr",     int_hexagon_S2_lsr_r_r_acc>;
3217 def HEXAGON_S2_asl_r_p_acc:
3218   di_SInst_didisi_acc             <"asl",     int_hexagon_S2_asl_r_p_acc>;
3219 def HEXAGON_S2_asr_r_p_acc:
3220   di_SInst_didisi_acc             <"asr",     int_hexagon_S2_asr_r_p_acc>;
3221 def HEXAGON_S2_lsl_r_p_acc:
3222   di_SInst_didisi_acc             <"lsl",     int_hexagon_S2_lsl_r_p_acc>;
3223 def HEXAGON_S2_lsr_r_p_acc:
3224   di_SInst_didisi_acc             <"lsr",     int_hexagon_S2_lsr_r_p_acc>;
3225
3226 def HEXAGON_S2_asl_r_r_nac:
3227   si_SInst_sisisi_nac             <"asl",     int_hexagon_S2_asl_r_r_nac>;
3228 def HEXAGON_S2_asr_r_r_nac:
3229   si_SInst_sisisi_nac             <"asr",     int_hexagon_S2_asr_r_r_nac>;
3230 def HEXAGON_S2_lsl_r_r_nac:
3231   si_SInst_sisisi_nac             <"lsl",     int_hexagon_S2_lsl_r_r_nac>;
3232 def HEXAGON_S2_lsr_r_r_nac:
3233   si_SInst_sisisi_nac             <"lsr",     int_hexagon_S2_lsr_r_r_nac>;
3234 def HEXAGON_S2_asl_r_p_nac:
3235   di_SInst_didisi_nac             <"asl",     int_hexagon_S2_asl_r_p_nac>;
3236 def HEXAGON_S2_asr_r_p_nac:
3237   di_SInst_didisi_nac             <"asr",     int_hexagon_S2_asr_r_p_nac>;
3238 def HEXAGON_S2_lsl_r_p_nac:
3239   di_SInst_didisi_nac             <"lsl",     int_hexagon_S2_lsl_r_p_nac>;
3240 def HEXAGON_S2_lsr_r_p_nac:
3241   di_SInst_didisi_nac             <"lsr",     int_hexagon_S2_lsr_r_p_nac>;
3242
3243 // STYPE / SHIFT / Shift by register and logical.
3244 def HEXAGON_S2_asl_r_r_and:
3245   si_SInst_sisisi_and             <"asl",     int_hexagon_S2_asl_r_r_and>;
3246 def HEXAGON_S2_asr_r_r_and:
3247   si_SInst_sisisi_and             <"asr",     int_hexagon_S2_asr_r_r_and>;
3248 def HEXAGON_S2_lsl_r_r_and:
3249   si_SInst_sisisi_and             <"lsl",     int_hexagon_S2_lsl_r_r_and>;
3250 def HEXAGON_S2_lsr_r_r_and:
3251   si_SInst_sisisi_and             <"lsr",     int_hexagon_S2_lsr_r_r_and>;
3252
3253 def HEXAGON_S2_asl_r_r_or:
3254   si_SInst_sisisi_or              <"asl",     int_hexagon_S2_asl_r_r_or>;
3255 def HEXAGON_S2_asr_r_r_or:
3256   si_SInst_sisisi_or              <"asr",     int_hexagon_S2_asr_r_r_or>;
3257 def HEXAGON_S2_lsl_r_r_or:
3258   si_SInst_sisisi_or              <"lsl",     int_hexagon_S2_lsl_r_r_or>;
3259 def HEXAGON_S2_lsr_r_r_or:
3260   si_SInst_sisisi_or              <"lsr",     int_hexagon_S2_lsr_r_r_or>;
3261
3262 def HEXAGON_S2_asl_r_p_and:
3263   di_SInst_didisi_and             <"asl",     int_hexagon_S2_asl_r_p_and>;
3264 def HEXAGON_S2_asr_r_p_and:
3265   di_SInst_didisi_and             <"asr",     int_hexagon_S2_asr_r_p_and>;
3266 def HEXAGON_S2_lsl_r_p_and:
3267   di_SInst_didisi_and             <"lsl",     int_hexagon_S2_lsl_r_p_and>;
3268 def HEXAGON_S2_lsr_r_p_and:
3269   di_SInst_didisi_and             <"lsr",     int_hexagon_S2_lsr_r_p_and>;
3270
3271 def HEXAGON_S2_asl_r_p_or:
3272   di_SInst_didisi_or              <"asl",     int_hexagon_S2_asl_r_p_or>;
3273 def HEXAGON_S2_asr_r_p_or:
3274   di_SInst_didisi_or              <"asr",     int_hexagon_S2_asr_r_p_or>;
3275 def HEXAGON_S2_lsl_r_p_or:
3276   di_SInst_didisi_or              <"lsl",     int_hexagon_S2_lsl_r_p_or>;
3277 def HEXAGON_S2_lsr_r_p_or:
3278   di_SInst_didisi_or              <"lsr",     int_hexagon_S2_lsr_r_p_or>;
3279
3280 // STYPE / SHIFT / Shift by register with saturation.
3281 def HEXAGON_S2_asl_r_r_sat:
3282   si_SInst_sisi_sat               <"asl",     int_hexagon_S2_asl_r_r_sat>;
3283 def HEXAGON_S2_asr_r_r_sat:
3284   si_SInst_sisi_sat               <"asr",     int_hexagon_S2_asr_r_r_sat>;
3285
3286 // STYPE / SHIFT / Table Index.
3287 def Hexagon_S2_tableidxb_goodsyntax:
3288   si_MInst_sisiu4u5          <"tableidxb",int_hexagon_S2_tableidxb_goodsyntax>;
3289 def Hexagon_S2_tableidxd_goodsyntax:
3290   si_MInst_sisiu4u5          <"tableidxd",int_hexagon_S2_tableidxd_goodsyntax>;
3291 def Hexagon_S2_tableidxh_goodsyntax:
3292   si_MInst_sisiu4u5          <"tableidxh",int_hexagon_S2_tableidxh_goodsyntax>;
3293 def Hexagon_S2_tableidxw_goodsyntax:
3294   si_MInst_sisiu4u5          <"tableidxw",int_hexagon_S2_tableidxw_goodsyntax>;
3295
3296
3297 /********************************************************************
3298 *            STYPE/VH                                               *
3299 *********************************************************************/
3300
3301 // STYPE / VH / Vector absolute value halfwords.
3302 // Rdd64=vabsh(Rss64)
3303 def HEXAGON_A2_vabsh:
3304   di_SInst_di                     <"vabsh",   int_hexagon_A2_vabsh>;
3305 def HEXAGON_A2_vabshsat:
3306   di_SInst_di_sat                 <"vabsh",   int_hexagon_A2_vabshsat>;
3307
3308 // STYPE / VH / Vector shift halfwords by immediate.
3309 // Rdd64=v[asl/asr/lsr]h(Rss64,Rt32)
3310 def HEXAGON_S2_asl_i_vh:
3311   di_SInst_disi                   <"vaslh",   int_hexagon_S2_asl_i_vh>;
3312 def HEXAGON_S2_asr_i_vh:
3313   di_SInst_disi                   <"vasrh",   int_hexagon_S2_asr_i_vh>;
3314 def HEXAGON_S2_lsr_i_vh:
3315   di_SInst_disi                   <"vlsrh",   int_hexagon_S2_lsr_i_vh>;
3316
3317 // STYPE / VH / Vector shift halfwords by register.
3318 // Rdd64=v[asl/asr/lsl/lsr]w(Rss64,Rt32)
3319 def HEXAGON_S2_asl_r_vh:
3320   di_SInst_disi                   <"vaslh",   int_hexagon_S2_asl_r_vh>;
3321 def HEXAGON_S2_asr_r_vh:
3322   di_SInst_disi                   <"vasrh",   int_hexagon_S2_asr_r_vh>;
3323 def HEXAGON_S2_lsl_r_vh:
3324   di_SInst_disi                   <"vlslh",   int_hexagon_S2_lsl_r_vh>;
3325 def HEXAGON_S2_lsr_r_vh:
3326   di_SInst_disi                   <"vlsrh",   int_hexagon_S2_lsr_r_vh>;
3327
3328
3329 /********************************************************************
3330 *            STYPE/VW                                               *
3331 *********************************************************************/
3332
3333 // STYPE / VW / Vector absolute value words.
3334 def HEXAGON_A2_vabsw:
3335   di_SInst_di                     <"vabsw",   int_hexagon_A2_vabsw>;
3336 def HEXAGON_A2_vabswsat:
3337   di_SInst_di_sat                 <"vabsw",   int_hexagon_A2_vabswsat>;
3338
3339 // STYPE / VW / Vector shift words by immediate.
3340 // Rdd64=v[asl/vsl]w(Rss64,Rt32)
3341 def HEXAGON_S2_asl_i_vw:
3342   di_SInst_disi                   <"vaslw",   int_hexagon_S2_asl_i_vw>;
3343 def HEXAGON_S2_asr_i_vw:
3344   di_SInst_disi                   <"vasrw",   int_hexagon_S2_asr_i_vw>;
3345 def HEXAGON_S2_lsr_i_vw:
3346   di_SInst_disi                   <"vlsrw",   int_hexagon_S2_lsr_i_vw>;
3347
3348 // STYPE / VW / Vector shift words by register.
3349 // Rdd64=v[asl/vsl]w(Rss64,Rt32)
3350 def HEXAGON_S2_asl_r_vw:
3351   di_SInst_disi                   <"vaslw",   int_hexagon_S2_asl_r_vw>;
3352 def HEXAGON_S2_asr_r_vw:
3353   di_SInst_disi                   <"vasrw",   int_hexagon_S2_asr_r_vw>;
3354 def HEXAGON_S2_lsl_r_vw:
3355   di_SInst_disi                   <"vlslw",   int_hexagon_S2_lsl_r_vw>;
3356 def HEXAGON_S2_lsr_r_vw:
3357   di_SInst_disi                   <"vlsrw",   int_hexagon_S2_lsr_r_vw>;
3358
3359 // STYPE / VW / Vector shift words with truncate and pack.
3360 def HEXAGON_S2_asr_r_svw_trun:
3361   si_SInst_disi                   <"vasrw",   int_hexagon_S2_asr_r_svw_trun>;
3362 def HEXAGON_S2_asr_i_svw_trun:
3363   si_SInst_diu5                   <"vasrw",   int_hexagon_S2_asr_i_svw_trun>;
3364
3365 // LD / Circular loads.
3366 def HEXAGON_circ_ldd:
3367   di_LDInstPI_diu4                <"circ_ldd", int_hexagon_circ_ldd>;
3368
3369 include "HexagonIntrinsicsV3.td"
3370 include "HexagonIntrinsicsV4.td"
3371 include "HexagonIntrinsicsV5.td"