lib/Target/Hexagon/HexagonIntrinsics.td

   1 //===-- HexagonIntrinsics.td - Instruction intrinsics ------*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 // This is populated based on the following specs:
  10 // Hexagon V2 Architecture
  11 // Application-Level Specification
  12 // 80-V9418-8 Rev. B
  13 // March 4, 2008
  14 //===----------------------------------------------------------------------===//
  15
  16 class T_RI_pat <InstHexagon MI, Intrinsic IntID, PatLeaf ImmPred = PatLeaf<(i32 imm)>>
  17   : Pat<(IntID I32:$Rs, ImmPred:$It),
  18         (MI I32:$Rs, ImmPred:$It)>;
  19
  20 class T_IR_pat <InstHexagon MI, Intrinsic IntID, PatFrag ImmPred = PatLeaf<(i32 imm)>>
  21   : Pat<(IntID ImmPred:$Is, I32:$Rt),
  22         (MI ImmPred:$Is, I32:$Rt)>;
  23
  24 class T_RR_pat <InstHexagon MI, Intrinsic IntID>
  25   : Pat <(IntID I32:$Rs, I32:$Rt),
  26          (MI I32:$Rs, I32:$Rt)>;
  27
  28 class T_RRR_pat <InstHexagon MI, Intrinsic IntID>
  29   : Pat <(IntID I32:$Rs, I32:$Rt, I32:$Ru),
  30          (MI I32:$Rs, I32:$Rt, I32:$Ru)>;
  31
  32 class T_PRR_pat <InstHexagon MI, Intrinsic IntID>
  33   : Pat <(IntID I64:$Rs, I32:$Rt, I32:$Ru),
  34          (MI DoubleRegs:$Rs, I32:$Rt, I32:$Ru)>;
  35
  36 //===----------------------------------------------------------------------===//
  37 // MPYS / Multipy signed/unsigned halfwords
  38 //Rd=mpy[u](Rs.[H|L],Rt.[H|L])[:<<1][:rnd][:sat]
  39 //===----------------------------------------------------------------------===//
  40
  41 def : T_RR_pat <M2_mpy_ll_s1, int_hexagon_M2_mpy_ll_s1>;
  42 def : T_RR_pat <M2_mpy_ll_s0, int_hexagon_M2_mpy_ll_s0>;
  43 def : T_RR_pat <M2_mpy_lh_s1, int_hexagon_M2_mpy_lh_s1>;
  44 def : T_RR_pat <M2_mpy_lh_s0, int_hexagon_M2_mpy_lh_s0>;
  45 def : T_RR_pat <M2_mpy_hl_s1, int_hexagon_M2_mpy_hl_s1>;
  46 def : T_RR_pat <M2_mpy_hl_s0, int_hexagon_M2_mpy_hl_s0>;
  47 def : T_RR_pat <M2_mpy_hh_s1, int_hexagon_M2_mpy_hh_s1>;
  48 def : T_RR_pat <M2_mpy_hh_s0, int_hexagon_M2_mpy_hh_s0>;
  49
  50 def : T_RR_pat <M2_mpyu_ll_s1, int_hexagon_M2_mpyu_ll_s1>;
  51 def : T_RR_pat <M2_mpyu_ll_s0, int_hexagon_M2_mpyu_ll_s0>;
  52 def : T_RR_pat <M2_mpyu_lh_s1, int_hexagon_M2_mpyu_lh_s1>;
  53 def : T_RR_pat <M2_mpyu_lh_s0, int_hexagon_M2_mpyu_lh_s0>;
  54 def : T_RR_pat <M2_mpyu_hl_s1, int_hexagon_M2_mpyu_hl_s1>;
  55 def : T_RR_pat <M2_mpyu_hl_s0, int_hexagon_M2_mpyu_hl_s0>;
  56 def : T_RR_pat <M2_mpyu_hh_s1, int_hexagon_M2_mpyu_hh_s1>;
  57 def : T_RR_pat <M2_mpyu_hh_s0, int_hexagon_M2_mpyu_hh_s0>;
  58
  59 def : T_RR_pat <M2_mpy_sat_ll_s1, int_hexagon_M2_mpy_sat_ll_s1>;
  60 def : T_RR_pat <M2_mpy_sat_ll_s0, int_hexagon_M2_mpy_sat_ll_s0>;
  61 def : T_RR_pat <M2_mpy_sat_lh_s1, int_hexagon_M2_mpy_sat_lh_s1>;
  62 def : T_RR_pat <M2_mpy_sat_lh_s0, int_hexagon_M2_mpy_sat_lh_s0>;
  63 def : T_RR_pat <M2_mpy_sat_hl_s1, int_hexagon_M2_mpy_sat_hl_s1>;
  64 def : T_RR_pat <M2_mpy_sat_hl_s0, int_hexagon_M2_mpy_sat_hl_s0>;
  65 def : T_RR_pat <M2_mpy_sat_hh_s1, int_hexagon_M2_mpy_sat_hh_s1>;
  66 def : T_RR_pat <M2_mpy_sat_hh_s0, int_hexagon_M2_mpy_sat_hh_s0>;
  67
  68 def : T_RR_pat <M2_mpy_rnd_ll_s1, int_hexagon_M2_mpy_rnd_ll_s1>;
  69 def : T_RR_pat <M2_mpy_rnd_ll_s0, int_hexagon_M2_mpy_rnd_ll_s0>;
  70 def : T_RR_pat <M2_mpy_rnd_lh_s1, int_hexagon_M2_mpy_rnd_lh_s1>;
  71 def : T_RR_pat <M2_mpy_rnd_lh_s0, int_hexagon_M2_mpy_rnd_lh_s0>;
  72 def : T_RR_pat <M2_mpy_rnd_hl_s1, int_hexagon_M2_mpy_rnd_hl_s1>;
  73 def : T_RR_pat <M2_mpy_rnd_hl_s0, int_hexagon_M2_mpy_rnd_hl_s0>;
  74 def : T_RR_pat <M2_mpy_rnd_hh_s1, int_hexagon_M2_mpy_rnd_hh_s1>;
  75 def : T_RR_pat <M2_mpy_rnd_hh_s0, int_hexagon_M2_mpy_rnd_hh_s0>;
  76
  77 def : T_RR_pat <M2_mpy_sat_rnd_ll_s1, int_hexagon_M2_mpy_sat_rnd_ll_s1>;
  78 def : T_RR_pat <M2_mpy_sat_rnd_ll_s0, int_hexagon_M2_mpy_sat_rnd_ll_s0>;
  79 def : T_RR_pat <M2_mpy_sat_rnd_lh_s1, int_hexagon_M2_mpy_sat_rnd_lh_s1>;
  80 def : T_RR_pat <M2_mpy_sat_rnd_lh_s0, int_hexagon_M2_mpy_sat_rnd_lh_s0>;
  81 def : T_RR_pat <M2_mpy_sat_rnd_hl_s1, int_hexagon_M2_mpy_sat_rnd_hl_s1>;
  82 def : T_RR_pat <M2_mpy_sat_rnd_hl_s0, int_hexagon_M2_mpy_sat_rnd_hl_s0>;
  83 def : T_RR_pat <M2_mpy_sat_rnd_hh_s1, int_hexagon_M2_mpy_sat_rnd_hh_s1>;
  84 def : T_RR_pat <M2_mpy_sat_rnd_hh_s0, int_hexagon_M2_mpy_sat_rnd_hh_s0>;
  85
  86
  87 //===----------------------------------------------------------------------===//
  88 // MPYS / Multipy signed/unsigned halfwords and add/subtract the
  89 // result from the accumulator.
  90 //Rx [-+]= mpy[u](Rs.[H|L],Rt.[H|L])[:<<1][:sat]
  91 //===----------------------------------------------------------------------===//
  92
  93 def : T_RRR_pat <M2_mpy_acc_ll_s1, int_hexagon_M2_mpy_acc_ll_s1>;
  94 def : T_RRR_pat <M2_mpy_acc_ll_s0, int_hexagon_M2_mpy_acc_ll_s0>;
  95 def : T_RRR_pat <M2_mpy_acc_lh_s1, int_hexagon_M2_mpy_acc_lh_s1>;
  96 def : T_RRR_pat <M2_mpy_acc_lh_s0, int_hexagon_M2_mpy_acc_lh_s0>;
  97 def : T_RRR_pat <M2_mpy_acc_hl_s1, int_hexagon_M2_mpy_acc_hl_s1>;
  98 def : T_RRR_pat <M2_mpy_acc_hl_s0, int_hexagon_M2_mpy_acc_hl_s0>;
  99 def : T_RRR_pat <M2_mpy_acc_hh_s1, int_hexagon_M2_mpy_acc_hh_s1>;
 100 def : T_RRR_pat <M2_mpy_acc_hh_s0, int_hexagon_M2_mpy_acc_hh_s0>;
 101
 102 def : T_RRR_pat <M2_mpyu_acc_ll_s1, int_hexagon_M2_mpyu_acc_ll_s1>;
 103 def : T_RRR_pat <M2_mpyu_acc_ll_s0, int_hexagon_M2_mpyu_acc_ll_s0>;
 104 def : T_RRR_pat <M2_mpyu_acc_lh_s1, int_hexagon_M2_mpyu_acc_lh_s1>;
 105 def : T_RRR_pat <M2_mpyu_acc_lh_s0, int_hexagon_M2_mpyu_acc_lh_s0>;
 106 def : T_RRR_pat <M2_mpyu_acc_hl_s1, int_hexagon_M2_mpyu_acc_hl_s1>;
 107 def : T_RRR_pat <M2_mpyu_acc_hl_s0, int_hexagon_M2_mpyu_acc_hl_s0>;
 108 def : T_RRR_pat <M2_mpyu_acc_hh_s1, int_hexagon_M2_mpyu_acc_hh_s1>;
 109 def : T_RRR_pat <M2_mpyu_acc_hh_s0, int_hexagon_M2_mpyu_acc_hh_s0>;
 110
 111 def : T_RRR_pat <M2_mpy_nac_ll_s1, int_hexagon_M2_mpy_nac_ll_s1>;
 112 def : T_RRR_pat <M2_mpy_nac_ll_s0, int_hexagon_M2_mpy_nac_ll_s0>;
 113 def : T_RRR_pat <M2_mpy_nac_lh_s1, int_hexagon_M2_mpy_nac_lh_s1>;
 114 def : T_RRR_pat <M2_mpy_nac_lh_s0, int_hexagon_M2_mpy_nac_lh_s0>;
 115 def : T_RRR_pat <M2_mpy_nac_hl_s1, int_hexagon_M2_mpy_nac_hl_s1>;
 116 def : T_RRR_pat <M2_mpy_nac_hl_s0, int_hexagon_M2_mpy_nac_hl_s0>;
 117 def : T_RRR_pat <M2_mpy_nac_hh_s1, int_hexagon_M2_mpy_nac_hh_s1>;
 118 def : T_RRR_pat <M2_mpy_nac_hh_s0, int_hexagon_M2_mpy_nac_hh_s0>;
 119
 120 def : T_RRR_pat <M2_mpyu_nac_ll_s1, int_hexagon_M2_mpyu_nac_ll_s1>;
 121 def : T_RRR_pat <M2_mpyu_nac_ll_s0, int_hexagon_M2_mpyu_nac_ll_s0>;
 122 def : T_RRR_pat <M2_mpyu_nac_lh_s1, int_hexagon_M2_mpyu_nac_lh_s1>;
 123 def : T_RRR_pat <M2_mpyu_nac_lh_s0, int_hexagon_M2_mpyu_nac_lh_s0>;
 124 def : T_RRR_pat <M2_mpyu_nac_hl_s1, int_hexagon_M2_mpyu_nac_hl_s1>;
 125 def : T_RRR_pat <M2_mpyu_nac_hl_s0, int_hexagon_M2_mpyu_nac_hl_s0>;
 126 def : T_RRR_pat <M2_mpyu_nac_hh_s1, int_hexagon_M2_mpyu_nac_hh_s1>;
 127 def : T_RRR_pat <M2_mpyu_nac_hh_s0, int_hexagon_M2_mpyu_nac_hh_s0>;
 128
 129 def : T_RRR_pat <M2_mpy_acc_sat_ll_s1, int_hexagon_M2_mpy_acc_sat_ll_s1>;
 130 def : T_RRR_pat <M2_mpy_acc_sat_ll_s0, int_hexagon_M2_mpy_acc_sat_ll_s0>;
 131 def : T_RRR_pat <M2_mpy_acc_sat_lh_s1, int_hexagon_M2_mpy_acc_sat_lh_s1>;
 132 def : T_RRR_pat <M2_mpy_acc_sat_lh_s0, int_hexagon_M2_mpy_acc_sat_lh_s0>;
 133 def : T_RRR_pat <M2_mpy_acc_sat_hl_s1, int_hexagon_M2_mpy_acc_sat_hl_s1>;
 134 def : T_RRR_pat <M2_mpy_acc_sat_hl_s0, int_hexagon_M2_mpy_acc_sat_hl_s0>;
 135 def : T_RRR_pat <M2_mpy_acc_sat_hh_s1, int_hexagon_M2_mpy_acc_sat_hh_s1>;
 136 def : T_RRR_pat <M2_mpy_acc_sat_hh_s0, int_hexagon_M2_mpy_acc_sat_hh_s0>;
 137
 138 def : T_RRR_pat <M2_mpy_nac_sat_ll_s1, int_hexagon_M2_mpy_nac_sat_ll_s1>;
 139 def : T_RRR_pat <M2_mpy_nac_sat_ll_s0, int_hexagon_M2_mpy_nac_sat_ll_s0>;
 140 def : T_RRR_pat <M2_mpy_nac_sat_lh_s1, int_hexagon_M2_mpy_nac_sat_lh_s1>;
 141 def : T_RRR_pat <M2_mpy_nac_sat_lh_s0, int_hexagon_M2_mpy_nac_sat_lh_s0>;
 142 def : T_RRR_pat <M2_mpy_nac_sat_hl_s1, int_hexagon_M2_mpy_nac_sat_hl_s1>;
 143 def : T_RRR_pat <M2_mpy_nac_sat_hl_s0, int_hexagon_M2_mpy_nac_sat_hl_s0>;
 144 def : T_RRR_pat <M2_mpy_nac_sat_hh_s1, int_hexagon_M2_mpy_nac_sat_hh_s1>;
 145 def : T_RRR_pat <M2_mpy_nac_sat_hh_s0, int_hexagon_M2_mpy_nac_sat_hh_s0>;
 146
 147
 148 //===----------------------------------------------------------------------===//
 149 // Multiply signed/unsigned halfwords with and without saturation and rounding
 150 // into a 64-bits destination register.
 151 //===----------------------------------------------------------------------===//
 152
 153 def : T_RR_pat <M2_mpyd_hh_s0, int_hexagon_M2_mpyd_hh_s0>;
 154 def : T_RR_pat <M2_mpyd_hl_s0, int_hexagon_M2_mpyd_hl_s0>;
 155 def : T_RR_pat <M2_mpyd_lh_s0, int_hexagon_M2_mpyd_lh_s0>;
 156 def : T_RR_pat <M2_mpyd_ll_s0, int_hexagon_M2_mpyd_ll_s0>;
 157 def : T_RR_pat <M2_mpyd_hh_s1, int_hexagon_M2_mpyd_hh_s1>;
 158 def : T_RR_pat <M2_mpyd_hl_s1, int_hexagon_M2_mpyd_hl_s1>;
 159 def : T_RR_pat <M2_mpyd_lh_s1, int_hexagon_M2_mpyd_lh_s1>;
 160 def : T_RR_pat <M2_mpyd_ll_s1, int_hexagon_M2_mpyd_ll_s1>;
 161
 162 def : T_RR_pat <M2_mpyd_rnd_hh_s0, int_hexagon_M2_mpyd_rnd_hh_s0>;
 163 def : T_RR_pat <M2_mpyd_rnd_hl_s0, int_hexagon_M2_mpyd_rnd_hl_s0>;
 164 def : T_RR_pat <M2_mpyd_rnd_lh_s0, int_hexagon_M2_mpyd_rnd_lh_s0>;
 165 def : T_RR_pat <M2_mpyd_rnd_ll_s0, int_hexagon_M2_mpyd_rnd_ll_s0>;
 166 def : T_RR_pat <M2_mpyd_rnd_hh_s1, int_hexagon_M2_mpyd_rnd_hh_s1>;
 167 def : T_RR_pat <M2_mpyd_rnd_hl_s1, int_hexagon_M2_mpyd_rnd_hl_s1>;
 168 def : T_RR_pat <M2_mpyd_rnd_lh_s1, int_hexagon_M2_mpyd_rnd_lh_s1>;
 169 def : T_RR_pat <M2_mpyd_rnd_ll_s1, int_hexagon_M2_mpyd_rnd_ll_s1>;
 170
 171 def : T_RR_pat <M2_mpyud_hh_s0, int_hexagon_M2_mpyud_hh_s0>;
 172 def : T_RR_pat <M2_mpyud_hl_s0, int_hexagon_M2_mpyud_hl_s0>;
 173 def : T_RR_pat <M2_mpyud_lh_s0, int_hexagon_M2_mpyud_lh_s0>;
 174 def : T_RR_pat <M2_mpyud_ll_s0, int_hexagon_M2_mpyud_ll_s0>;
 175 def : T_RR_pat <M2_mpyud_hh_s1, int_hexagon_M2_mpyud_hh_s1>;
 176 def : T_RR_pat <M2_mpyud_hl_s1, int_hexagon_M2_mpyud_hl_s1>;
 177 def : T_RR_pat <M2_mpyud_lh_s1, int_hexagon_M2_mpyud_lh_s1>;
 178 def : T_RR_pat <M2_mpyud_ll_s1, int_hexagon_M2_mpyud_ll_s1>;
 179
 180 //===----------------------------------------------------------------------===//
 181 // MPYS / Multipy signed/unsigned halfwords and add/subtract the
 182 // result from the 64-bit destination register.
 183 //Rxx [-+]= mpy[u](Rs.[H|L],Rt.[H|L])[:<<1][:sat]
 184 //===----------------------------------------------------------------------===//
 185
 186 def : T_PRR_pat <M2_mpyd_acc_hh_s0, int_hexagon_M2_mpyd_acc_hh_s0>;
 187 def : T_PRR_pat <M2_mpyd_acc_hl_s0, int_hexagon_M2_mpyd_acc_hl_s0>;
 188 def : T_PRR_pat <M2_mpyd_acc_lh_s0, int_hexagon_M2_mpyd_acc_lh_s0>;
 189 def : T_PRR_pat <M2_mpyd_acc_ll_s0, int_hexagon_M2_mpyd_acc_ll_s0>;
 190
 191 def : T_PRR_pat <M2_mpyd_acc_hh_s1, int_hexagon_M2_mpyd_acc_hh_s1>;
 192 def : T_PRR_pat <M2_mpyd_acc_hl_s1, int_hexagon_M2_mpyd_acc_hl_s1>;
 193 def : T_PRR_pat <M2_mpyd_acc_lh_s1, int_hexagon_M2_mpyd_acc_lh_s1>;
 194 def : T_PRR_pat <M2_mpyd_acc_ll_s1, int_hexagon_M2_mpyd_acc_ll_s1>;
 195
 196 def : T_PRR_pat <M2_mpyd_nac_hh_s0, int_hexagon_M2_mpyd_nac_hh_s0>;
 197 def : T_PRR_pat <M2_mpyd_nac_hl_s0, int_hexagon_M2_mpyd_nac_hl_s0>;
 198 def : T_PRR_pat <M2_mpyd_nac_lh_s0, int_hexagon_M2_mpyd_nac_lh_s0>;
 199 def : T_PRR_pat <M2_mpyd_nac_ll_s0, int_hexagon_M2_mpyd_nac_ll_s0>;
 200
 201 def : T_PRR_pat <M2_mpyd_nac_hh_s1, int_hexagon_M2_mpyd_nac_hh_s1>;
 202 def : T_PRR_pat <M2_mpyd_nac_hl_s1, int_hexagon_M2_mpyd_nac_hl_s1>;
 203 def : T_PRR_pat <M2_mpyd_nac_lh_s1, int_hexagon_M2_mpyd_nac_lh_s1>;
 204 def : T_PRR_pat <M2_mpyd_nac_ll_s1, int_hexagon_M2_mpyd_nac_ll_s1>;
 205
 206 def : T_PRR_pat <M2_mpyud_acc_hh_s0, int_hexagon_M2_mpyud_acc_hh_s0>;
 207 def : T_PRR_pat <M2_mpyud_acc_hl_s0, int_hexagon_M2_mpyud_acc_hl_s0>;
 208 def : T_PRR_pat <M2_mpyud_acc_lh_s0, int_hexagon_M2_mpyud_acc_lh_s0>;
 209 def : T_PRR_pat <M2_mpyud_acc_ll_s0, int_hexagon_M2_mpyud_acc_ll_s0>;
 210
 211 def : T_PRR_pat <M2_mpyud_acc_hh_s1, int_hexagon_M2_mpyud_acc_hh_s1>;
 212 def : T_PRR_pat <M2_mpyud_acc_hl_s1, int_hexagon_M2_mpyud_acc_hl_s1>;
 213 def : T_PRR_pat <M2_mpyud_acc_lh_s1, int_hexagon_M2_mpyud_acc_lh_s1>;
 214 def : T_PRR_pat <M2_mpyud_acc_ll_s1, int_hexagon_M2_mpyud_acc_ll_s1>;
 215
 216 def : T_PRR_pat <M2_mpyud_nac_hh_s0, int_hexagon_M2_mpyud_nac_hh_s0>;
 217 def : T_PRR_pat <M2_mpyud_nac_hl_s0, int_hexagon_M2_mpyud_nac_hl_s0>;
 218 def : T_PRR_pat <M2_mpyud_nac_lh_s0, int_hexagon_M2_mpyud_nac_lh_s0>;
 219 def : T_PRR_pat <M2_mpyud_nac_ll_s0, int_hexagon_M2_mpyud_nac_ll_s0>;
 220
 221 def : T_PRR_pat <M2_mpyud_nac_hh_s1, int_hexagon_M2_mpyud_nac_hh_s1>;
 222 def : T_PRR_pat <M2_mpyud_nac_hl_s1, int_hexagon_M2_mpyud_nac_hl_s1>;
 223 def : T_PRR_pat <M2_mpyud_nac_lh_s1, int_hexagon_M2_mpyud_nac_lh_s1>;
 224 def : T_PRR_pat <M2_mpyud_nac_ll_s1, int_hexagon_M2_mpyud_nac_ll_s1>;
 225
 226 /********************************************************************
 227 *            ALU32/ALU                                              *
 228 *********************************************************************/
 229 def : T_RR_pat<A2_add,      int_hexagon_A2_add>;
 230 def : T_RI_pat<ADD_ri,      int_hexagon_A2_addi>;
 231 def : T_RR_pat<A2_sub,      int_hexagon_A2_sub>;
 232 def : T_IR_pat<SUB_ri,      int_hexagon_A2_subri>;
 233 def : T_RR_pat<A2_and,      int_hexagon_A2_and>;
 234 def : T_RI_pat<AND_ri,      int_hexagon_A2_andir>;
 235 def : T_RR_pat<A2_or,       int_hexagon_A2_or>;
 236 def : T_RI_pat<OR_ri,       int_hexagon_A2_orir>;
 237 def : T_RR_pat<A2_xor,      int_hexagon_A2_xor>;
 238 def : T_RR_pat<A2_combinew, int_hexagon_A2_combinew>;
 239
 240 //
 241 // ALU 32 types.
 242 //
 243
 244 class qi_ALU32_sisi<string opc, Intrinsic IntID>
 245   : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 246              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
 247              [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 248
 249 class qi_ALU32_sis10<string opc, Intrinsic IntID>
 250   : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, s10Imm:$src2),
 251              !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
 252              [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
 253
 254 class qi_ALU32_sis8<string opc, Intrinsic IntID>
 255   : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, s8Imm:$src2),
 256              !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
 257              [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
 258
 259 class qi_ALU32_siu8<string opc, Intrinsic IntID>
 260   : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, u8Imm:$src2),
 261              !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
 262              [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
 263
 264 class qi_ALU32_siu9<string opc, Intrinsic IntID>
 265   : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, u9Imm:$src2),
 266              !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
 267              [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
 268
 269 class si_ALU32_qisisi<string opc, Intrinsic IntID>
 270   : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2,
 271                                       IntRegs:$src3),
 272              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2, $src3)")),
 273              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2,
 274                                         IntRegs:$src3))]>;
 275
 276 class si_ALU32_qis8si<string opc, Intrinsic IntID>
 277   : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, s8Imm:$src2,
 278                                        IntRegs:$src3),
 279              !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2, $src3)")),
 280              [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2,
 281                                         IntRegs:$src3))]>;
 282
 283 class si_ALU32_qisis8<string opc, Intrinsic IntID>
 284   : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2,
 285                                        s8Imm:$src3),
 286              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2, #$src3)")),
 287              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2,
 288                                         imm:$src3))]>;
 289
 290 class si_ALU32_qis8s8<string opc, Intrinsic IntID>
 291   : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, s8Imm:$src2, s8Imm:$src3),
 292              !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2, #$src3)")),
 293              [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2, imm:$src3))]>;
 294
 295 class si_ALU32_sisi<string opc, Intrinsic IntID>
 296   : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 297              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
 298              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 299
 300 class si_ALU32_sisi_sat<string opc, Intrinsic IntID>
 301   : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 302              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):sat")),
 303              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 304
 305 class si_ALU32_sisi_rnd<string opc, Intrinsic IntID>
 306   : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 307              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):rnd")),
 308              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 309
 310 class si_ALU32_sis16<string opc, Intrinsic IntID>
 311   : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, s16Imm:$src2),
 312              !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
 313              [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
 314
 315 class si_ALU32_sis10<string opc, Intrinsic IntID>
 316   : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, s10Imm:$src2),
 317              !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
 318              [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
 319
 320 class si_ALU32_s10si<string opc, Intrinsic IntID>
 321   : ALU32_rr<(outs IntRegs:$dst), (ins s10Imm:$src1, IntRegs:$src2),
 322              !strconcat("$dst = ", !strconcat(opc , "(#$src1, $src2)")),
 323              [(set IntRegs:$dst, (IntID imm:$src1, IntRegs:$src2))]>;
 324
 325 class si_lo_ALU32_siu16<string opc, Intrinsic IntID>
 326   : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u16Imm:$src2),
 327              !strconcat("$dst.l = ", !strconcat(opc , "#$src2")),
 328              [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
 329
 330 class si_hi_ALU32_siu16<string opc, Intrinsic IntID>
 331   : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u16Imm:$src2),
 332              !strconcat("$dst.h = ", !strconcat(opc , "#$src2")),
 333              [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
 334
 335 class si_ALU32_s16<string opc, Intrinsic IntID>
 336   : ALU32_rr<(outs IntRegs:$dst), (ins s16Imm:$src1),
 337              !strconcat("$dst = ", !strconcat(opc , "#$src1")),
 338              [(set IntRegs:$dst, (IntID imm:$src1))]>;
 339
 340 class di_ALU32_s8<string opc, Intrinsic IntID>
 341   : ALU32_rr<(outs DoubleRegs:$dst), (ins s8Imm:$src1),
 342              !strconcat("$dst = ", !strconcat(opc , "#$src1")),
 343              [(set DoubleRegs:$dst, (IntID imm:$src1))]>;
 344
 345 class di_ALU64_di<string opc, Intrinsic IntID>
 346   : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src),
 347              !strconcat("$dst = ", !strconcat(opc , "$src")),
 348              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src))]>;
 349
 350 class si_ALU32_si<string opc, Intrinsic IntID>
 351   : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src),
 352              !strconcat("$dst = ", !strconcat(opc , "($src)")),
 353              [(set IntRegs:$dst, (IntID IntRegs:$src))]>;
 354
 355 class si_ALU32_si_tfr<string opc, Intrinsic IntID>
 356   : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src),
 357              !strconcat("$dst = ", !strconcat(opc , "$src")),
 358              [(set IntRegs:$dst, (IntID IntRegs:$src))]>;
 359
 360 //
 361 // ALU 64 types.
 362 //
 363
 364 class si_ALU64_si_sat<string opc, Intrinsic IntID>
 365   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src),
 366              !strconcat("$dst = ", !strconcat(opc , "($src):sat")),
 367              [(set IntRegs:$dst, (IntID IntRegs:$src))]>;
 368
 369 class si_ALU64_didi<string opc, Intrinsic IntID>
 370   : ALU64_rr<(outs IntRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
 371              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
 372              [(set IntRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
 373
 374 class di_ALU64_sidi<string opc, Intrinsic IntID>
 375   : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src1, DoubleRegs:$src2),
 376              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
 377              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, DoubleRegs:$src2))]>;
 378
 379 class di_ALU64_didi<string opc, Intrinsic IntID>
 380   : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
 381              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
 382              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
 383                                            DoubleRegs:$src2))]>;
 384
 385 class di_ALU64_qididi<string opc, Intrinsic IntID>
 386   : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src1, DoubleRegs:$src2,
 387                                           DoubleRegs:$src3),
 388              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2, $src3)")),
 389              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, DoubleRegs:$src2,
 390                                            DoubleRegs:$src3))]>;
 391
 392 class di_ALU64_sisi<string opc, Intrinsic IntID>
 393   : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 394              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
 395              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 396
 397 class di_ALU64_didi_sat<string opc, Intrinsic IntID>
 398   : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
 399              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):sat")),
 400              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
 401                                            DoubleRegs:$src2))]>;
 402
 403 class di_ALU64_didi_rnd<string opc, Intrinsic IntID>
 404   : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
 405              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):rnd")),
 406              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
 407                                            DoubleRegs:$src2))]>;
 408
 409 class di_ALU64_didi_crnd<string opc, Intrinsic IntID>
 410   : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
 411              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):crnd")),
 412              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
 413                                            DoubleRegs:$src2))]>;
 414
 415 class di_ALU64_didi_rnd_sat<string opc, Intrinsic IntID>
 416   : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
 417              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):rnd:sat")),
 418              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
 419                                            DoubleRegs:$src2))]>;
 420
 421 class di_ALU64_didi_crnd_sat<string opc, Intrinsic IntID>
 422   : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
 423              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):crnd:sat")),
 424              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
 425                                            DoubleRegs:$src2))]>;
 426
 427 class qi_ALU64_didi<string opc, Intrinsic IntID>
 428   : ALU64_rr<(outs PredRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
 429              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
 430              [(set PredRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
 431
 432 class si_ALU64_sisi<string opc, Intrinsic IntID>
 433   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 434              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
 435              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 436
 437 class si_ALU64_sisi_sat_lh<string opc, Intrinsic IntID>
 438   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 439              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H):sat")),
 440              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 441
 442 class si_ALU64_sisi_l16_sat_hh<string opc, Intrinsic IntID>
 443   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 444              !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.H):sat")),
 445              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 446
 447 class si_ALU64_sisi_l16_sat_lh<string opc, Intrinsic IntID>
 448   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 449              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H):sat")),
 450              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 451
 452 class si_ALU64_sisi_l16_sat_hl<string opc, Intrinsic IntID>
 453   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 454              !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.L):sat")),
 455              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 456
 457 class si_ALU64_sisi_l16_sat_ll<string opc, Intrinsic IntID>
 458   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 459              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L):sat")),
 460              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 461
 462 class si_ALU64_sisi_l16_hh<string opc, Intrinsic IntID>
 463   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 464              !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.H)")),
 465              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 466
 467 class si_ALU64_sisi_l16_hl<string opc, Intrinsic IntID>
 468   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 469              !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.L)")),
 470              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 471
 472 class si_ALU64_sisi_l16_lh<string opc, Intrinsic IntID>
 473   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 474              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H)")),
 475              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 476
 477 class si_ALU64_sisi_l16_ll<string opc, Intrinsic IntID>
 478   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 479              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L)")),
 480              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 481
 482 class si_ALU64_sisi_h16_sat_hh<string opc, Intrinsic IntID>
 483   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 484              !strconcat("$dst = ", !strconcat(opc ,
 485                                               "($src1.H, $src2.H):sat:<<16")),
 486              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 487
 488 class si_ALU64_sisi_h16_sat_lh<string opc, Intrinsic IntID>
 489   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 490              !strconcat("$dst = ", !strconcat(opc ,
 491                                               "($src1.L, $src2.H):sat:<<16")),
 492              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 493
 494 class si_ALU64_sisi_h16_sat_hl<string opc, Intrinsic IntID>
 495   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 496              !strconcat("$dst = ", !strconcat(opc ,
 497                                               "($src1.H, $src2.L):sat:<<16")),
 498              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 499
 500 class si_ALU64_sisi_h16_sat_ll<string opc, Intrinsic IntID>
 501   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 502              !strconcat("$dst = ", !strconcat(opc ,
 503                                               "($src1.L, $src2.L):sat:<<16")),
 504              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 505
 506 class si_ALU64_sisi_h16_hh<string opc, Intrinsic IntID>
 507   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 508              !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.H):<<16")),
 509              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 510
 511 class si_ALU64_sisi_h16_hl<string opc, Intrinsic IntID>
 512   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 513              !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.L):<<16")),
 514              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 515
 516 class si_ALU64_sisi_h16_lh<string opc, Intrinsic IntID>
 517   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 518              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H):<<16")),
 519              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 520
 521 class si_ALU64_sisi_h16_ll<string opc, Intrinsic IntID>
 522   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 523              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L):<<16")),
 524              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 525
 526 class si_ALU64_sisi_lh<string opc, Intrinsic IntID>
 527   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 528              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H)")),
 529              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 530
 531 class si_ALU64_sisi_ll<string opc, Intrinsic IntID>
 532   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 533              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L)")),
 534              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 535
 536 class si_ALU64_sisi_sat<string opc, Intrinsic IntID>
 537   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 538              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):sat")),
 539              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 540
 541 //
 542 // SInst classes.
 543 //
 544
 545 class qi_SInst_qi<string opc, Intrinsic IntID>
 546   : SInst<(outs PredRegs:$dst), (ins IntRegs:$src),
 547              !strconcat("$dst = ", !strconcat(opc , "($src)")),
 548              [(set PredRegs:$dst, (IntID IntRegs:$src))]>;
 549
 550 class qi_SInst_qi_pxfer<string opc, Intrinsic IntID>
 551   : SInst<(outs PredRegs:$dst), (ins IntRegs:$src),
 552              !strconcat("$dst = ", !strconcat(opc , "$src")),
 553              [(set PredRegs:$dst, (IntID IntRegs:$src))]>;
 554
 555 class qi_SInst_qiqi<string opc, Intrinsic IntID>
 556   : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 557              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
 558              [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 559
 560 class qi_SInst_qiqi_neg<string opc, Intrinsic IntID>
 561   : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 562              !strconcat("$dst = ", !strconcat(opc , "($src1, !$src2)")),
 563              [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 564
 565 class di_SInst_di<string opc, Intrinsic IntID>
 566   : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src),
 567              !strconcat("$dst = ", !strconcat(opc , "($src)")),
 568              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src))]>;
 569
 570 class di_SInst_di_sat<string opc, Intrinsic IntID>
 571   : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src),
 572              !strconcat("$dst = ", !strconcat(opc , "($src):sat")),
 573              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src))]>;
 574
 575 class si_SInst_di<string opc, Intrinsic IntID>
 576   : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src),
 577           !strconcat("$dst = ", !strconcat(opc , "($src)")),
 578           [(set IntRegs:$dst, (IntID DoubleRegs:$src))]>;
 579
 580 class si_SInst_di_sat<string opc, Intrinsic IntID>
 581   : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src),
 582           !strconcat("$dst = ", !strconcat(opc , "($src):sat")),
 583           [(set IntRegs:$dst, (IntID DoubleRegs:$src))]>;
 584
 585 class di_SInst_disi<string opc, Intrinsic IntID>
 586   : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
 587           !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
 588           [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, IntRegs:$src2))]>;
 589
 590 class di_SInst_didi<string opc, Intrinsic IntID>
 591   : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
 592           !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
 593           [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
 594
 595 class di_SInst_si<string opc, Intrinsic IntID>
 596   : SInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1),
 597           !strconcat("$dst = ", !strconcat(opc , "($src1)")),
 598           [(set DoubleRegs:$dst, (IntID IntRegs:$src1))]>;
 599
 600 class si_SInst_sisiu3<string opc, Intrinsic IntID>
 601   : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2, u3Imm:$src3),
 602           !strconcat("$dst = ", !strconcat(opc , "($src1, $src2, #$src3)")),
 603           [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2,
 604                                      imm:$src3))]>;
 605
 606 class si_SInst_diu5<string opc, Intrinsic IntID>
 607   : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, u5Imm:$src2),
 608           !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
 609           [(set IntRegs:$dst, (IntID DoubleRegs:$src1, imm:$src2))]>;
 610
 611 class si_SInst_disi<string opc, Intrinsic IntID>
 612   : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
 613           !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
 614           [(set IntRegs:$dst, (IntID DoubleRegs:$src1, IntRegs:$src2))]>;
 615
 616 class si_SInst_sidi<string opc, Intrinsic IntID>
 617   : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, DoubleRegs:$src2),
 618           !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
 619           [(set IntRegs:$dst, (IntID IntRegs:$src1, DoubleRegs:$src2))]>;
 620
 621 class di_SInst_disisi<string opc, Intrinsic IntID>
 622   : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2,
 623                                        IntRegs:$src3),
 624           !strconcat("$dst = ", !strconcat(opc , "($src1, $src2, $src3)")),
 625           [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, IntRegs:$src2,
 626                                         IntRegs:$src3))]>;
 627
 628 class di_SInst_sisi<string opc, Intrinsic IntID>
 629   : SInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 630           !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
 631           [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 632
 633 class qi_SInst_siu5<string opc, Intrinsic IntID>
 634   : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
 635           !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
 636           [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
 637
 638 class qi_SInst_siu6<string opc, Intrinsic IntID>
 639   : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, u6Imm:$src2),
 640           !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
 641           [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
 642
 643 class qi_SInst_sisi<string opc, Intrinsic IntID>
 644   : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 645           !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
 646           [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 647
 648 class si_SInst_si<string opc, Intrinsic IntID>
 649   : SInst<(outs IntRegs:$dst), (ins IntRegs:$src),
 650           !strconcat("$dst = ", !strconcat(opc , "($src)")),
 651           [(set IntRegs:$dst, (IntID IntRegs:$src))]>;
 652
 653 class si_SInst_si_sat<string opc, Intrinsic IntID>
 654   : SInst<(outs IntRegs:$dst), (ins IntRegs:$src),
 655           !strconcat("$dst = ", !strconcat(opc , "($src):sat")),
 656           [(set IntRegs:$dst, (IntID IntRegs:$src))]>;
 657
 658 class di_SInst_qi<string opc, Intrinsic IntID>
 659   : SInst<(outs DoubleRegs:$dst), (ins IntRegs:$src),
 660           !strconcat("$dst = ", !strconcat(opc , "($src)")),
 661           [(set DoubleRegs:$dst, (IntID IntRegs:$src))]>;
 662
 663 class si_SInst_qi<string opc, Intrinsic IntID>
 664   : SInst<(outs IntRegs:$dst), (ins IntRegs:$src),
 665           !strconcat("$dst = ", !strconcat(opc , "$src")),
 666           [(set IntRegs:$dst, (IntID IntRegs:$src))]>;
 667
 668 class si_SInst_qiqi<string opc, Intrinsic IntID>
 669   : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 670           !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
 671           [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 672
 673 class qi_SInst_si<string opc, Intrinsic IntID>
 674   : SInst<(outs PredRegs:$dst), (ins IntRegs:$src),
 675           !strconcat("$dst = ", !strconcat(opc , "$src")),
 676           [(set PredRegs:$dst, (IntID IntRegs:$src))]>;
 677
 678 class si_SInst_sisi<string opc, Intrinsic IntID>
 679   : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 680           !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
 681           [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 682
 683 class di_SInst_diu6<string opc, Intrinsic IntID>
 684   : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u6Imm:$src2),
 685           !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
 686           [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, imm:$src2))]>;
 687
 688 class si_SInst_siu5<string opc, Intrinsic IntID>
 689   : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
 690           !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
 691           [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
 692
 693 class si_SInst_siu5_rnd<string opc, Intrinsic IntID>
 694   : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
 695           !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2):rnd")),
 696           [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
 697
 698 class si_SInst_siu5u5<string opc, Intrinsic IntID>
 699   : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2, u5Imm:$src3),
 700           !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2, #$src3)")),
 701           [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2, imm:$src3))]>;
 702
 703 class si_SInst_sisisi_acc<string opc, Intrinsic IntID>
 704   : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
 705                                         IntRegs:$src2),
 706               !strconcat("$dst += ", !strconcat(opc , "($src1, $src2)")),
 707               [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
 708                                          IntRegs:$src2))],
 709               "$dst2 = $dst">;
 710
 711 class si_SInst_sisisi_nac<string opc, Intrinsic IntID>
 712   : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
 713                                         IntRegs:$src2),
 714               !strconcat("$dst -= ", !strconcat(opc , "($src1, $src2)")),
 715               [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
 716                                          IntRegs:$src2))],
 717               "$dst2 = $dst">;
 718
 719 class di_SInst_didisi_acc<string opc, Intrinsic IntID>
 720   : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
 721                                            IntRegs:$src2),
 722                !strconcat("$dst += ", !strconcat(opc , "($src1, $src2)")),
 723                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
 724                                              DoubleRegs:$src1,
 725                                              IntRegs:$src2))],
 726                "$dst2 = $dst">;
 727
 728 class di_SInst_didisi_nac<string opc, Intrinsic IntID>
 729   : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
 730                                            IntRegs:$src2),
 731           !strconcat("$dst -= ", !strconcat(opc , "($src1, $src2)")),
 732           [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
 733                                         DoubleRegs:$src1, IntRegs:$src2))],
 734           "$dst2 = $dst">;
 735
 736 class si_SInst_sisiu5u5<string opc, Intrinsic IntID>
 737   : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
 738                                         u5Imm:$src2, u5Imm:$src3),
 739               !strconcat("$dst = ", !strconcat(opc ,
 740                                                "($src1, #$src2, #$src3)")),
 741               [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
 742                                          imm:$src2, imm:$src3))],
 743               "$dst2 = $dst">;
 744
 745 class si_SInst_sisidi<string opc, Intrinsic IntID>
 746   : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
 747                                         DoubleRegs:$src2),
 748               !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
 749               [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
 750                                          DoubleRegs:$src2))],
 751               "$dst2 = $dst">;
 752
 753 class di_SInst_didiu6u6<string opc, Intrinsic IntID>
 754   : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
 755                                            u6Imm:$src2, u6Imm:$src3),
 756               !strconcat("$dst = ", !strconcat(opc ,
 757                                                "($src1, #$src2, #$src3)")),
 758               [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, DoubleRegs:$src1,
 759                                             imm:$src2, imm:$src3))],
 760               "$dst2 = $dst">;
 761
 762 class di_SInst_dididi<string opc, Intrinsic IntID>
 763   : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
 764                                            DoubleRegs:$src2),
 765               !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
 766               [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
 767                                             DoubleRegs:$src1,
 768                                             DoubleRegs:$src2))],
 769               "$dst2 = $dst">;
 770
 771 class di_SInst_diu6u6<string opc, Intrinsic IntID>
 772   : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u6Imm:$src2,
 773                                        u6Imm:$src3),
 774           !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2, #$src3)")),
 775           [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, imm:$src2,
 776                                         imm:$src3))]>;
 777
 778 class di_SInst_didiqi<string opc, Intrinsic IntID>
 779   : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2,
 780                                        IntRegs:$src3),
 781           !strconcat("$dst = ", !strconcat(opc , "($src1, $src2, $src3)")),
 782           [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2,
 783                                         IntRegs:$src3))]>;
 784
 785 class di_SInst_didiu3<string opc, Intrinsic IntID>
 786   : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2,
 787                                        u3Imm:$src3),
 788           !strconcat("$dst = ", !strconcat(opc , "($src1, $src2, #$src3)")),
 789           [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2,
 790                                         imm:$src3))]>;
 791
 792 class di_SInst_didisi_or<string opc, Intrinsic IntID>
 793   : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
 794                                            IntRegs:$src2),
 795           !strconcat("$dst |= ", !strconcat(opc , "($src1, $src2)")),
 796           [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, DoubleRegs:$src1,
 797                                         IntRegs:$src2))],
 798           "$dst2 = $dst">;
 799
 800 class di_SInst_didisi_and<string opc, Intrinsic IntID>
 801   : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
 802                                            IntRegs:$src2),
 803           !strconcat("$dst &= ", !strconcat(opc , "($src1, $src2)")),
 804           [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, DoubleRegs:$src1,
 805                                         IntRegs:$src2))],
 806           "$dst2 = $dst">;
 807
 808 class di_SInst_didiu6_and<string opc, Intrinsic IntID>
 809   : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
 810                                            u6Imm:$src2),
 811           !strconcat("$dst &= ", !strconcat(opc , "($src1, #$src2)")),
 812           [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, DoubleRegs:$src1,
 813                                         imm:$src2))],
 814           "$dst2 = $dst">;
 815
 816 class di_SInst_didiu6_or<string opc, Intrinsic IntID>
 817   : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
 818                                            u6Imm:$src2),
 819           !strconcat("$dst |= ", !strconcat(opc , "($src1, #$src2)")),
 820           [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, DoubleRegs:$src1,
 821                                         imm:$src2))],
 822           "$dst2 = $dst">;
 823
 824 class di_SInst_didiu6_xor<string opc, Intrinsic IntID>
 825   : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
 826                                            u6Imm:$src2),
 827           !strconcat("$dst ^= ", !strconcat(opc , "($src1, #$src2)")),
 828           [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, DoubleRegs:$src1,
 829                                         imm:$src2))],
 830           "$dst2 = $dst">;
 831
 832 class si_SInst_sisisi_and<string opc, Intrinsic IntID>
 833   : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
 834                                         IntRegs:$src2),
 835               !strconcat("$dst &= ", !strconcat(opc , "($src1, $src2)")),
 836               [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
 837                                          IntRegs:$src2))],
 838               "$dst2 = $dst">;
 839
 840 class si_SInst_sisisi_or<string opc, Intrinsic IntID>
 841   : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
 842                                         IntRegs:$src2),
 843               !strconcat("$dst |= ", !strconcat(opc , "($src1, $src2)")),
 844               [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
 845                                          IntRegs:$src2))],
 846               "$dst2 = $dst">;
 847
 848
 849 class si_SInst_sisiu5_and<string opc, Intrinsic IntID>
 850   : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
 851                                         u5Imm:$src2),
 852               !strconcat("$dst &= ", !strconcat(opc , "($src1, #$src2)")),
 853               [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
 854                                          imm:$src2))],
 855               "$dst2 = $dst">;
 856
 857 class si_SInst_sisiu5_or<string opc, Intrinsic IntID>
 858   : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
 859                                         u5Imm:$src2),
 860               !strconcat("$dst |= ", !strconcat(opc , "($src1, #$src2)")),
 861               [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
 862                                          imm:$src2))],
 863               "$dst2 = $dst">;
 864
 865 class si_SInst_sisiu5_xor<string opc, Intrinsic IntID>
 866   : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
 867                                         u5Imm:$src2),
 868               !strconcat("$dst ^= ", !strconcat(opc , "($src1, #$src2)")),
 869               [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
 870                                          imm:$src2))],
 871               "$dst2 = $dst">;
 872
 873 class si_SInst_sisiu5_acc<string opc, Intrinsic IntID>
 874   : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
 875                                         u5Imm:$src2),
 876               !strconcat("$dst += ", !strconcat(opc , "($src1, #$src2)")),
 877               [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
 878                                          imm:$src2))],
 879               "$dst2 = $dst">;
 880
 881 class si_SInst_sisiu5_nac<string opc, Intrinsic IntID>
 882   : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
 883                                         u5Imm:$src2),
 884               !strconcat("$dst -= ", !strconcat(opc , "($src1, #$src2)")),
 885               [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
 886                                          imm:$src2))],
 887               "$dst2 = $dst">;
 888
 889 class di_SInst_didiu6_acc<string opc, Intrinsic IntID>
 890   : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
 891                                            u5Imm:$src2),
 892               !strconcat("$dst += ", !strconcat(opc , "($src1, #$src2)")),
 893               [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
 894                                             DoubleRegs:$src1, imm:$src2))],
 895               "$dst2 = $dst">;
 896
 897 class di_SInst_didiu6_nac<string opc, Intrinsic IntID>
 898   : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
 899                                            u5Imm:$src2),
 900               !strconcat("$dst -= ", !strconcat(opc , "($src1, #$src2)")),
 901               [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, DoubleRegs:$src1,
 902                                             imm:$src2))],
 903               "$dst2 = $dst">;
 904
 905
 906 //
 907 // MInst classes.
 908 //
 909
 910 class di_MInst_sisi_rnd_hh_s1<string opc, Intrinsic IntID>
 911   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 912                !strconcat("$dst = ", !strconcat(opc ,
 913                                                 "($src1.H, $src2.H):<<1:rnd")),
 914                [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 915
 916 class di_MInst_sisi_rnd_hh<string opc, Intrinsic IntID>
 917   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 918                !strconcat("$dst = ", !strconcat(opc ,
 919                                                 "($src1.H, $src2.H):rnd")),
 920                [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 921
 922 class di_MInst_sisi_rnd_hl_s1<string opc, Intrinsic IntID>
 923   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 924                !strconcat("$dst = ", !strconcat(opc ,
 925                                                 "($src1.H, $src2.L):<<1:rnd")),
 926                [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 927
 928 class di_MInst_sisi_rnd_hl<string opc, Intrinsic IntID>
 929   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 930                !strconcat("$dst = ", !strconcat(opc ,
 931                                                 "($src1.H, $src2.L):rnd")),
 932                [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 933
 934 class di_MInst_sisi_rnd_lh_s1<string opc, Intrinsic IntID>
 935   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 936                !strconcat("$dst = ", !strconcat(opc ,
 937                                                 "($src1.L, $src2.H):<<1:rnd")),
 938                [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 939
 940 class di_MInst_sisi_rnd_lh<string opc, Intrinsic IntID>
 941   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 942                !strconcat("$dst = ", !strconcat(opc ,
 943                                                 "($src1.L, $src2.H):rnd")),
 944                [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 945
 946 class di_MInst_sisi_rnd_ll_s1<string opc, Intrinsic IntID>
 947   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 948                !strconcat("$dst = ", !strconcat(opc ,
 949                                                 "($src1.L, $src2.L):<<1:rnd")),
 950                [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 951
 952 class di_MInst_sisi_rnd_ll<string opc, Intrinsic IntID>
 953   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 954                !strconcat("$dst = ", !strconcat(opc ,
 955                                                 "($src1.L, $src2.L):rnd")),
 956                [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 957
 958 class di_MInst_disisi_acc<string opc, Intrinsic IntID>
 959   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
 960                                            IntRegs:$src2),
 961              !strconcat("$dst += ", !strconcat(opc , "($src1, $src2)")),
 962              [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
 963                                            IntRegs:$src2))],
 964              "$dst2 = $dst">;
 965
 966 class di_MInst_disisi_nac<string opc, Intrinsic IntID>
 967   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
 968                                            IntRegs:$src2),
 969              !strconcat("$dst -= ", !strconcat(opc , "($src1, $src2)")),
 970              [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
 971                                            IntRegs:$src2))],
 972              "$dst2 = $dst">;
 973
 974 class di_MInst_disisi_acc_sat<string opc, Intrinsic IntID>
 975   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
 976                                            IntRegs:$src2),
 977              !strconcat("$dst += ", !strconcat(opc , "($src1, $src2):sat")),
 978              [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
 979                                            IntRegs:$src2))],
 980              "$dst2 = $dst">;
 981
 982 class di_MInst_disisi_nac_sat<string opc, Intrinsic IntID>
 983   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
 984                                            IntRegs:$src2),
 985              !strconcat("$dst -= ", !strconcat(opc , "($src1, $src2):sat")),
 986              [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
 987                                            IntRegs:$src2))],
 988              "$dst2 = $dst">;
 989
 990 class di_MInst_disisi_acc_sat_conj<string opc, Intrinsic IntID>
 991   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
 992                                            IntRegs:$src2),
 993              !strconcat("$dst += ", !strconcat(opc , "($src1, $src2*):sat")),
 994              [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
 995                                            IntRegs:$src2))],
 996              "$dst2 = $dst">;
 997
 998 class di_MInst_disisi_nac_sat_conj<string opc, Intrinsic IntID>
 999   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1000                                            IntRegs:$src2),
1001              !strconcat("$dst -= ", !strconcat(opc , "($src1, $src2*):sat")),
1002              [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1003                                            IntRegs:$src2))],
1004              "$dst2 = $dst">;
1005
1006 class di_MInst_disisi_nac_s1_sat<string opc, Intrinsic IntID>
1007   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1008                                            IntRegs:$src2),
1009              !strconcat("$dst -= ", !strconcat(opc ,
1010                                                "($src1, $src2):<<1:sat")),
1011              [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1012                                            IntRegs:$src2))],
1013              "$dst2 = $dst">;
1014
1015 class di_MInst_disisi_acc_s1_sat_conj<string opc, Intrinsic IntID>
1016   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1017                                            IntRegs:$src2),
1018              !strconcat("$dst += ", !strconcat(opc ,
1019                                                "($src1, $src2*):<<1:sat")),
1020              [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1021                                            IntRegs:$src2))],
1022              "$dst2 = $dst">;
1023
1024 class di_MInst_disisi_nac_s1_sat_conj<string opc, Intrinsic IntID>
1025   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1026                                            IntRegs:$src2),
1027              !strconcat("$dst -= ", !strconcat(opc ,
1028                                                "($src1, $src2*):<<1:sat")),
1029              [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1030                                            IntRegs:$src2))],
1031              "$dst2 = $dst">;
1032
1033 class di_MInst_s8s8<string opc, Intrinsic IntID>
1034   : MInst<(outs DoubleRegs:$dst), (ins s8Imm:$src1, s8Imm:$src2),
1035              !strconcat("$dst = ", !strconcat(opc , "(#$src1, #$src2)")),
1036              [(set DoubleRegs:$dst, (IntID imm:$src1, imm:$src2))]>;
1037
1038 class si_MInst_sis9<string opc, Intrinsic IntID>
1039   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, s9Imm:$src2),
1040              !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
1041              [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
1042
1043 class si_MInst_sisi<string opc, Intrinsic IntID>
1044   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1045              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
1046              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1047
1048 class di_MInst_sisi_hh<string opc, Intrinsic IntID>
1049   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1050              !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.H)")),
1051              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1052
1053 class di_MInst_sisi_hh_s1<string opc, Intrinsic IntID>
1054   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1055              !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.H):<<1")),
1056              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1057
1058 class di_MInst_sisi_lh<string opc, Intrinsic IntID>
1059   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1060              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H)")),
1061              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1062
1063 class di_MInst_sisi_lh_s1<string opc, Intrinsic IntID>
1064   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1065              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H):<<1")),
1066              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1067
1068 class di_MInst_sisi_hl<string opc, Intrinsic IntID>
1069   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1070              !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.L)")),
1071              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1072
1073 class di_MInst_sisi_hl_s1<string opc, Intrinsic IntID>
1074   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1075              !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.L):<<1")),
1076              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1077
1078 class di_MInst_sisi_ll<string opc, Intrinsic IntID>
1079   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1080              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L)")),
1081              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1082
1083 class di_MInst_sisi_ll_s1<string opc, Intrinsic IntID>
1084   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1085              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L):<<1")),
1086              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1087
1088
1089 class si_MInst_sisi_hh<string opc, Intrinsic IntID>
1090   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1091              !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.H)")),
1092              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1093
1094 class si_MInst_sisi_hh_s1<string opc, Intrinsic IntID>
1095   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1096              !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.H):<<1")),
1097              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1098
1099 class si_MInst_sisi_lh<string opc, Intrinsic IntID>
1100   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1101              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H)")),
1102              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1103
1104 class si_MInst_sisi_lh_s1<string opc, Intrinsic IntID>
1105   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1106              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H):<<1")),
1107              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1108
1109 class si_MInst_sisi_hl<string opc, Intrinsic IntID>
1110   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1111              !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.L)")),
1112              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1113
1114 class si_MInst_sisi_hl_s1<string opc, Intrinsic IntID>
1115   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1116              !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.L):<<1")),
1117              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1118
1119 class si_MInst_sisi_ll<string opc, Intrinsic IntID>
1120   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1121              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L)")),
1122              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1123
1124 class si_MInst_sisi_ll_s1<string opc, Intrinsic IntID>
1125   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1126              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L):<<1")),
1127              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1128
1129 class si_MInst_sisi_up<string opc, Intrinsic IntID>
1130   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1131              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
1132              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1133
1134 class di_MInst_didi<string opc, Intrinsic IntID>
1135   : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1136              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
1137              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
1138                                            DoubleRegs:$src2))]>;
1139
1140 class di_MInst_didi_conj<string opc, Intrinsic IntID>
1141   : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1142              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2*)")),
1143              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
1144                                            DoubleRegs:$src2))]>;
1145
1146 class di_MInst_sisi_s1_sat_conj<string opc, Intrinsic IntID>
1147   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1148              !strconcat("$dst = ", !strconcat(opc ,
1149                                               "($src1, $src2*):<<1:sat")),
1150              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1151
1152 class di_MInst_didi_s1_rnd_sat<string opc, Intrinsic IntID>
1153   : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1154              !strconcat("$dst = ", !strconcat(opc ,
1155                                               "($src1, $src2):<<1:rnd:sat")),
1156              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
1157                                            DoubleRegs:$src2))]>;
1158
1159 class di_MInst_didi_sat<string opc, Intrinsic IntID>
1160   : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1161              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):sat")),
1162              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
1163                                            DoubleRegs:$src2))]>;
1164
1165 class di_MInst_didi_rnd_sat<string opc, Intrinsic IntID>
1166   : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1167              !strconcat("$dst = ", !strconcat(opc ,
1168                                               "($src1, $src2):rnd:sat")),
1169              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
1170                                            DoubleRegs:$src2))]>;
1171
1172 class si_SInst_sisi_sat<string opc, Intrinsic IntID>
1173   : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1174           !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):sat")),
1175           [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1176
1177 class si_SInst_didi_sat<string opc, Intrinsic IntID>
1178   : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1179           !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):sat")),
1180           [(set IntRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
1181
1182 class si_SInst_disi_s1_rnd_sat<string opc, Intrinsic IntID>
1183   : MInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
1184              !strconcat("$dst = ", !strconcat(opc ,
1185                                               "($src1, $src2):<<1:rnd:sat")),
1186              [(set IntRegs:$dst, (IntID DoubleRegs:$src1, IntRegs:$src2))]>;
1187
1188 class si_MInst_sisi_s1_rnd_sat<string opc, Intrinsic IntID>
1189   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1190              !strconcat("$dst = ", !strconcat(opc ,
1191                                               "($src1, $src2):<<1:rnd:sat")),
1192              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1193
1194 class si_MInst_sisi_l_s1_rnd_sat<string opc, Intrinsic IntID>
1195   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1196              !strconcat("$dst = ", !strconcat(opc ,
1197                                               "($src1, $src2.L):<<1:rnd:sat")),
1198              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1199
1200 class si_MInst_sisi_h_s1_rnd_sat<string opc, Intrinsic IntID>
1201   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1202              !strconcat("$dst = ", !strconcat(opc ,
1203                                               "($src1, $src2.H):<<1:rnd:sat")),
1204              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1205
1206 class si_MInst_sisi_rnd_sat_conj<string opc, Intrinsic IntID>
1207   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1208              !strconcat("$dst = ", !strconcat(opc ,
1209                                               "($src1, $src2*):rnd:sat")),
1210              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1211
1212 class si_MInst_sisi_s1_rnd_sat_conj<string opc, Intrinsic IntID>
1213   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1214              !strconcat("$dst = ", !strconcat(opc ,
1215                                               "($src1, $src2*):<<1:rnd:sat")),
1216              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1217
1218 class si_MInst_sisi_rnd_sat<string opc, Intrinsic IntID>
1219   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1220              !strconcat("$dst = ", !strconcat(opc ,
1221                                               "($src1, $src2):rnd:sat")),
1222              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1223
1224 class si_MInst_sisi_rnd<string opc, Intrinsic IntID>
1225   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1226              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):rnd")),
1227              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1228
1229 class si_MInst_sisisi_xacc<string opc, Intrinsic IntID>
1230   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src2,
1231                                         IntRegs:$src3),
1232              !strconcat("$dst ^= ", !strconcat(opc , "($src2, $src3)")),
1233              [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src2,
1234                                         IntRegs:$src3))],
1235              "$dst2 = $dst">;
1236
1237 class si_MInst_sisisi_acc<string opc, Intrinsic IntID>
1238   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src2,
1239                                         IntRegs:$src3),
1240              !strconcat("$dst += ", !strconcat(opc , "($src2, $src3)")),
1241              [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src2,
1242                                         IntRegs:$src3))],
1243              "$dst2 = $dst">;
1244
1245 class si_MInst_sisisi_nac<string opc, Intrinsic IntID>
1246   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src2,
1247                                         IntRegs:$src3),
1248              !strconcat("$dst -= ", !strconcat(opc , "($src2, $src3)")),
1249              [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src2,
1250                                         IntRegs:$src3))],
1251              "$dst2 = $dst">;
1252
1253 class si_MInst_sisis8_acc<string opc, Intrinsic IntID>
1254   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src2,
1255                                         s8Imm:$src3),
1256              !strconcat("$dst += ", !strconcat(opc , "($src2, #$src3)")),
1257              [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src2,
1258                                         imm:$src3))],
1259              "$dst2 = $dst">;
1260
1261 class si_MInst_sisis8_nac<string opc, Intrinsic IntID>
1262   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src2,
1263                                         s8Imm:$src3),
1264              !strconcat("$dst -= ", !strconcat(opc , "($src2, #$src3)")),
1265              [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src2,
1266                                         imm:$src3))],
1267              "$dst2 = $dst">;
1268
1269 class si_MInst_sisiu4u5<string opc, Intrinsic IntID>
1270   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1271                                         u4Imm:$src2, u5Imm:$src3),
1272                !strconcat("$dst = ", !strconcat(opc ,
1273                                                 "($src1, #$src2, #$src3)")),
1274                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1275                                           imm:$src2, imm:$src3))],
1276                "$dst2 = $dst">;
1277
1278 class si_MInst_sisiu8_acc<string opc, Intrinsic IntID>
1279   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src2,
1280                                         u8Imm:$src3),
1281                !strconcat("$dst += ", !strconcat(opc , "($src2, #$src3)")),
1282                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src2,
1283                                           imm:$src3))],
1284                "$dst2 = $dst">;
1285
1286 class si_MInst_sisiu8_nac<string opc, Intrinsic IntID>
1287   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src2,
1288                                         u8Imm:$src3),
1289                !strconcat("$dst -= ", !strconcat(opc , "($src2, #$src3)")),
1290                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src2,
1291                                           imm:$src3))],
1292                "$dst2 = $dst">;
1293
1294 class si_MInst_sisisi_acc_hh<string opc, Intrinsic IntID>
1295   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1296                                         IntRegs:$src2),
1297                !strconcat("$dst += ", !strconcat(opc , "($src1.H, $src2.H)")),
1298                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1299                                           IntRegs:$src2))],
1300                "$dst2 = $dst">;
1301
1302 class si_MInst_sisisi_acc_sat_lh<string opc, Intrinsic IntID>
1303   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1304                                         IntRegs:$src2),
1305                !strconcat("$dst += ", !strconcat(opc ,
1306                                                  "($src1.L, $src2.H):sat")),
1307                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1308                                           IntRegs:$src2))],
1309                "$dst2 = $dst">;
1310
1311 class si_MInst_sisisi_acc_sat_lh_s1<string opc, Intrinsic IntID>
1312   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1313                                         IntRegs:$src2),
1314                !strconcat("$dst += ", !strconcat(opc ,
1315                                                  "($src1.L, $src2.H):<<1:sat")),
1316                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1317                                           IntRegs:$src2))],
1318                "$dst2 = $dst">;
1319
1320 class si_MInst_sisisi_acc_sat_hh<string opc, Intrinsic IntID>
1321   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1322                                         IntRegs:$src2),
1323                !strconcat("$dst += ", !strconcat(opc ,
1324                                                  "($src1.H, $src2.H):sat")),
1325                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1326                                           IntRegs:$src2))],
1327                "$dst2 = $dst">;
1328
1329 class si_MInst_sisisi_acc_sat_hh_s1<string opc, Intrinsic IntID>
1330   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1331                                         IntRegs:$src2),
1332                !strconcat("$dst += ", !strconcat(opc ,
1333                                                  "($src1.H, $src2.H):<<1:sat")),
1334                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1335                                           IntRegs:$src2))],
1336                "$dst2 = $dst">;
1337
1338 class si_MInst_sisisi_acc_hh_s1<string opc, Intrinsic IntID>
1339   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1340                                         IntRegs:$src2),
1341                !strconcat("$dst += ", !strconcat(opc ,
1342                                                  "($src1.H, $src2.H):<<1")),
1343                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1344                                           IntRegs:$src2))],
1345                "$dst2 = $dst">;
1346
1347 class si_MInst_sisisi_nac_hh<string opc, Intrinsic IntID>
1348   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1349                                         IntRegs:$src2),
1350                !strconcat("$dst -= ", !strconcat(opc , "($src1.H, $src2.H)")),
1351                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1352                                           IntRegs:$src2))],
1353                "$dst2 = $dst">;
1354
1355 class si_MInst_sisisi_nac_sat_hh_s1<string opc, Intrinsic IntID>
1356   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1357                                         IntRegs:$src2),
1358                !strconcat("$dst -= ", !strconcat(opc ,
1359                                                  "($src1.H, $src2.H):<<1:sat")),
1360                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1361                                           IntRegs:$src2))],
1362                "$dst2 = $dst">;
1363
1364 class si_MInst_sisisi_nac_sat_hh<string opc, Intrinsic IntID>
1365   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1366                                         IntRegs:$src2),
1367                !strconcat("$dst -= ", !strconcat(opc ,
1368                                                  "($src1.H, $src2.H):sat")),
1369                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1370                                           IntRegs:$src2))],
1371                "$dst2 = $dst">;
1372
1373 class si_MInst_sisisi_nac_sat_hl_s1<string opc, Intrinsic IntID>
1374   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1375                                         IntRegs:$src2),
1376                !strconcat("$dst -= ", !strconcat(opc ,
1377                                                  "($src1.H, $src2.L):<<1:sat")),
1378                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1379                                           IntRegs:$src2))],
1380                "$dst2 = $dst">;
1381
1382 class si_MInst_sisisi_nac_sat_hl<string opc, Intrinsic IntID>
1383   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1384                                         IntRegs:$src2),
1385                !strconcat("$dst -= ", !strconcat(opc ,
1386                                                  "($src1.H, $src2.L):sat")),
1387                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1388                                           IntRegs:$src2))],
1389                "$dst2 = $dst">;
1390
1391 class si_MInst_sisisi_nac_sat_lh_s1<string opc, Intrinsic IntID>
1392   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1393                                         IntRegs:$src2),
1394                !strconcat("$dst -= ", !strconcat(opc ,
1395                                                  "($src1.L, $src2.H):<<1:sat")),
1396                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1397                                           IntRegs:$src2))],
1398                "$dst2 = $dst">;
1399
1400 class si_MInst_sisisi_nac_sat_lh<string opc, Intrinsic IntID>
1401   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1402                                         IntRegs:$src2),
1403                !strconcat("$dst -= ", !strconcat(opc ,
1404                                                  "($src1.L, $src2.H):sat")),
1405                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1406                                           IntRegs:$src2))],
1407                "$dst2 = $dst">;
1408
1409 class si_MInst_sisisi_nac_sat_ll_s1<string opc, Intrinsic IntID>
1410   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1411                                         IntRegs:$src2),
1412                !strconcat("$dst -= ", !strconcat(opc ,
1413                                                  "($src1.L, $src2.L):<<1:sat")),
1414                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1415                                           IntRegs:$src2))],
1416                "$dst2 = $dst">;
1417
1418 class si_MInst_sisisi_nac_sat_ll<string opc, Intrinsic IntID>
1419   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1420                                         IntRegs:$src2),
1421                !strconcat("$dst -= ", !strconcat(opc ,
1422                                                  "($src1.L, $src2.L):sat")),
1423                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1424                                           IntRegs:$src2))],
1425                "$dst2 = $dst">;
1426
1427 class si_MInst_sisisi_nac_hh_s1<string opc, Intrinsic IntID>
1428   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1429                                         IntRegs:$src2),
1430                !strconcat("$dst -= ", !strconcat(opc ,
1431                                                  "($src1.H, $src2.H):<<1")),
1432                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1433                                           IntRegs:$src2))],
1434                "$dst2 = $dst">;
1435
1436 class si_MInst_sisisi_acc_hl<string opc, Intrinsic IntID>
1437   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1438                                         IntRegs:$src2),
1439                !strconcat("$dst += ", !strconcat(opc , "($src1.H, $src2.L)")),
1440                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1441                                           IntRegs:$src2))],
1442                "$dst2 = $dst">;
1443
1444 class si_MInst_sisisi_acc_hl_s1<string opc, Intrinsic IntID>
1445   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1446                                         IntRegs:$src2),
1447                !strconcat("$dst += ", !strconcat(opc ,
1448                                                  "($src1.H, $src2.L):<<1")),
1449                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1450                                           IntRegs:$src2))],
1451                "$dst2 = $dst">;
1452
1453 class si_MInst_sisisi_nac_hl<string opc, Intrinsic IntID>
1454   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1455                                         IntRegs:$src2),
1456                !strconcat("$dst -= ", !strconcat(opc , "($src1.H, $src2.L)")),
1457                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1458                                           IntRegs:$src2))],
1459                "$dst2 = $dst">;
1460
1461 class si_MInst_sisisi_nac_hl_s1<string opc, Intrinsic IntID>
1462   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1463                                         IntRegs:$src2),
1464                !strconcat("$dst -= ", !strconcat(opc ,
1465                                                  "($src1.H, $src2.L):<<1")),
1466                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1467                                           IntRegs:$src2))],
1468                "$dst2 = $dst">;
1469
1470 class si_MInst_sisisi_acc_lh<string opc, Intrinsic IntID>
1471   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1472                                         IntRegs:$src2),
1473                !strconcat("$dst += ", !strconcat(opc , "($src1.L, $src2.H)")),
1474                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1475                                           IntRegs:$src2))],
1476                "$dst2 = $dst">;
1477
1478 class si_MInst_sisisi_acc_lh_s1<string opc, Intrinsic IntID>
1479   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1480                                         IntRegs:$src2),
1481                !strconcat("$dst += ", !strconcat(opc ,
1482                                                  "($src1.L, $src2.H):<<1")),
1483                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1484                                           IntRegs:$src2))],
1485                "$dst2 = $dst">;
1486
1487 class si_MInst_sisisi_nac_lh<string opc, Intrinsic IntID>
1488   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1489                                         IntRegs:$src2),
1490                !strconcat("$dst -= ", !strconcat(opc , "($src1.L, $src2.H)")),
1491                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1492                                           IntRegs:$src2))],
1493                "$dst2 = $dst">;
1494
1495 class si_MInst_sisisi_nac_lh_s1<string opc, Intrinsic IntID>
1496   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1497                                         IntRegs:$src2),
1498                !strconcat("$dst -= ", !strconcat(opc ,
1499                                                  "($src1.L, $src2.H):<<1")),
1500                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1501                                           IntRegs:$src2))],
1502                "$dst2 = $dst">;
1503
1504 class si_MInst_sisisi_acc_ll<string opc, Intrinsic IntID>
1505   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1506                                         IntRegs:$src2),
1507                !strconcat("$dst += ", !strconcat(opc , "($src1.L, $src2.L)")),
1508                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1509                                           IntRegs:$src2))],
1510                "$dst2 = $dst">;
1511
1512 class si_MInst_sisisi_acc_ll_s1<string opc, Intrinsic IntID>
1513   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1514                                         IntRegs:$src2),
1515                !strconcat("$dst += ", !strconcat(opc ,
1516                                                  "($src1.L, $src2.L):<<1")),
1517                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1518                                           IntRegs:$src2))],
1519                "$dst2 = $dst">;
1520
1521 class si_MInst_sisisi_acc_sat_ll_s1<string opc, Intrinsic IntID>
1522   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1523                                         IntRegs:$src2),
1524                !strconcat("$dst += ", !strconcat(opc ,
1525                                                  "($src1.L, $src2.L):<<1:sat")),
1526                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1527                                           IntRegs:$src2))],
1528                "$dst2 = $dst">;
1529
1530 class si_MInst_sisisi_acc_sat_hl_s1<string opc, Intrinsic IntID>
1531   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1532                                         IntRegs:$src2),
1533                !strconcat("$dst += ", !strconcat(opc ,
1534                                                  "($src1.H, $src2.L):<<1:sat")),
1535                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1536                                           IntRegs:$src2))],
1537                "$dst2 = $dst">;
1538
1539 class si_MInst_sisisi_acc_sat_ll<string opc, Intrinsic IntID>
1540   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1541                                         IntRegs:$src2),
1542                !strconcat("$dst += ", !strconcat(opc ,
1543                                                  "($src1.L, $src2.L):sat")),
1544                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1545                                           IntRegs:$src2))],
1546                "$dst2 = $dst">;
1547
1548 class si_MInst_sisisi_acc_sat_hl<string opc, Intrinsic IntID>
1549   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1550                                         IntRegs:$src2),
1551                !strconcat("$dst += ", !strconcat(opc ,
1552                                                  "($src1.H, $src2.L):sat")),
1553                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1554                                           IntRegs:$src2))],
1555                "$dst2 = $dst">;
1556
1557 class si_MInst_sisisi_nac_ll<string opc, Intrinsic IntID>
1558   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1559                                         IntRegs:$src2),
1560                !strconcat("$dst -= ", !strconcat(opc , "($src1.L, $src2.L)")),
1561                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1562                                           IntRegs:$src2))],
1563                "$dst2 = $dst">;
1564
1565 class si_MInst_sisisi_nac_ll_s1<string opc, Intrinsic IntID>
1566   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1567                                         IntRegs:$src2),
1568                !strconcat("$dst -= ", !strconcat(opc ,
1569                                                  "($src1.L, $src2.L):<<1")),
1570                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1571                                           IntRegs:$src2))],
1572                "$dst2 = $dst">;
1573
1574 class si_MInst_sisisi_nac_hh_sat<string opc, Intrinsic IntID>
1575   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1576                                         IntRegs:$src2),
1577                !strconcat("$dst -= ", !strconcat(opc ,
1578                                                  "($src1.H, $src2.H):sat")),
1579                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1580                                           IntRegs:$src2))],
1581                "$dst2 = $dst">;
1582
1583 class si_MInst_sisisi_nac_hh_s1_sat<string opc, Intrinsic IntID>
1584   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1585                                         IntRegs:$src2),
1586                !strconcat("$dst -= ", !strconcat(opc ,
1587                                                  "($src1.H, $src2.H):<<1:sat")),
1588                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1589                                           IntRegs:$src2))],
1590                "$dst2 = $dst">;
1591
1592 class si_MInst_sisisi_nac_hl_sat<string opc, Intrinsic IntID>
1593   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1594                                         IntRegs:$src2),
1595                !strconcat("$dst -= ", !strconcat(opc ,
1596                                                  "($src1.H, $src2.L):sat")),
1597                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1598                                           IntRegs:$src2))],
1599                "$dst2 = $dst">;
1600
1601 class si_MInst_sisisi_nac_hl_s1_sat<string opc, Intrinsic IntID>
1602   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1603                                         IntRegs:$src2),
1604                !strconcat("$dst -= ", !strconcat(opc ,
1605                                                  "($src1.H, $src2.L):<<1:sat")),
1606                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1607                                           IntRegs:$src2))],
1608                "$dst2 = $dst">;
1609
1610 class si_MInst_sisisi_nac_lh_sat<string opc, Intrinsic IntID>
1611   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1612                                         IntRegs:$src2),
1613                !strconcat("$dst -= ", !strconcat(opc ,
1614                                                  "($src1.L, $src2.H):sat")),
1615                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1616                                           IntRegs:$src2))],
1617                "$dst2 = $dst">;
1618
1619 class si_MInst_sisisi_nac_lh_s1_sat<string opc, Intrinsic IntID>
1620   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1621                                         IntRegs:$src2),
1622                !strconcat("$dst -= ", !strconcat(opc ,
1623                                                  "($src1.L, $src2.H):<<1:sat")),
1624                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1625                                           IntRegs:$src2))],
1626                "$dst2 = $dst">;
1627
1628 class si_MInst_sisisi_nac_ll_sat<string opc, Intrinsic IntID>
1629   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1630                                         IntRegs:$src2),
1631                !strconcat("$dst -= ", !strconcat(opc ,
1632                                                  "($src1.L, $src2.L):sat")),
1633                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1634                                           IntRegs:$src2))],
1635                "$dst2 = $dst">;
1636
1637 class si_MInst_sisisi_nac_ll_s1_sat<string opc, Intrinsic IntID>
1638   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1639                                         IntRegs:$src2),
1640                !strconcat("$dst -= ", !strconcat(opc ,
1641                                                  "($src1.L, $src2.L):<<1:sat")),
1642                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1643                                           IntRegs:$src2))],
1644                "$dst2 = $dst">;
1645
1646 class di_ALU32_sisi<string opc, Intrinsic IntID>
1647   : ALU32_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1648              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
1649              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1650
1651 class di_MInst_sisi<string opc, Intrinsic IntID>
1652   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1653              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
1654              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1655
1656 class di_MInst_sisi_sat<string opc, Intrinsic IntID>
1657   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1658              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):sat")),
1659              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1660
1661 class di_MInst_sisi_sat_conj<string opc, Intrinsic IntID>
1662   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1663              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2*):sat")),
1664              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1665
1666 class di_MInst_sisi_s1_sat<string opc, Intrinsic IntID>
1667   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1668              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):<<1:sat")),
1669              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1670
1671 class di_MInst_didi_s1_sat<string opc, Intrinsic IntID>
1672   : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1673              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):<<1:sat")),
1674              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
1675                                            DoubleRegs:$src2))]>;
1676
1677 class si_MInst_didi_s1_rnd_sat<string opc, Intrinsic IntID>
1678   : MInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1679              !strconcat("$dst = ", !strconcat(opc ,
1680                                               "($src1, $src2):<<1:rnd:sat")),
1681              [(set IntRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
1682
1683 class si_MInst_didi_rnd_sat<string opc, Intrinsic IntID>
1684   : MInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1685              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):rnd:sat")),
1686              [(set IntRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
1687
1688 class si_MInst_sisi_sat_hh<string opc, Intrinsic IntID>
1689   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1690              !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.H):sat")),
1691              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1692
1693 class si_MInst_sisi_sat_hh_s1<string opc, Intrinsic IntID>
1694   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1695                !strconcat("$dst = ", !strconcat(opc ,
1696                                                 "($src1.H, $src2.H):<<1:sat")),
1697                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1698
1699 class si_MInst_sisi_sat_hl<string opc, Intrinsic IntID>
1700   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1701              !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.L):sat")),
1702              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1703
1704 class si_MInst_sisi_sat_hl_s1<string opc, Intrinsic IntID>
1705   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1706                !strconcat("$dst = ", !strconcat(opc ,
1707                                                 "($src1.H, $src2.L):<<1:sat")),
1708                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1709
1710 class si_MInst_sisi_sat_lh<string opc, Intrinsic IntID>
1711   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1712              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H):sat")),
1713              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1714
1715 class si_MInst_sisi_sat_lh_s1<string opc, Intrinsic IntID>
1716   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1717                !strconcat("$dst = ", !strconcat(opc ,
1718                                                 "($src1.L, $src2.H):<<1:sat")),
1719                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1720
1721 class si_MInst_sisi_sat_ll<string opc, Intrinsic IntID>
1722   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1723              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L):sat")),
1724              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1725
1726 class si_MInst_sisi_sat_ll_s1<string opc, Intrinsic IntID>
1727   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1728                !strconcat("$dst = ", !strconcat(opc ,
1729                                                 "($src1.L, $src2.L):<<1:sat")),
1730                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1731
1732 class si_MInst_sisi_sat_rnd_hh<string opc, Intrinsic IntID>
1733   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1734                !strconcat("$dst = ", !strconcat(opc ,
1735                                                 "($src1.H, $src2.H):rnd:sat")),
1736                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1737
1738 class si_MInst_sisi_rnd_hh<string opc, Intrinsic IntID>
1739   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1740                !strconcat("$dst = ", !strconcat(opc ,
1741                                                 "($src1.H, $src2.H):rnd")),
1742                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1743
1744 class si_MInst_sisi_rnd_hh_s1<string opc, Intrinsic IntID>
1745   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1746                !strconcat("$dst = ", !strconcat(opc ,
1747                                                 "($src1.H, $src2.H):<<1:rnd")),
1748                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1749
1750 class si_MInst_sisi_sat_rnd_hh_s1<string opc, Intrinsic IntID>
1751   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1752                !strconcat("$dst = ",
1753                           !strconcat(opc ,
1754                                      "($src1.H, $src2.H):<<1:rnd:sat")),
1755                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1756
1757 class si_MInst_sisi_rnd_hl<string opc, Intrinsic IntID>
1758   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1759                !strconcat("$dst = ",
1760                           !strconcat(opc , "($src1.H, $src2.L):rnd")),
1761                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1762
1763 class si_MInst_sisi_rnd_hl_s1<string opc, Intrinsic IntID>
1764   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1765                !strconcat("$dst = ",
1766                           !strconcat(opc , "($src1.H, $src2.L):<<1:rnd")),
1767                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1768
1769 class si_MInst_sisi_sat_rnd_hl<string opc, Intrinsic IntID>
1770   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1771                !strconcat("$dst = ",
1772                           !strconcat(opc , "($src1.H, $src2.L):rnd:sat")),
1773                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1774
1775 class si_MInst_sisi_sat_rnd_hl_s1<string opc, Intrinsic IntID>
1776   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1777                !strconcat("$dst = ",
1778                           !strconcat(opc , "($src1.H, $src2.L):<<1:rnd:sat")),
1779                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1780
1781 class si_MInst_sisi_rnd_lh<string opc, Intrinsic IntID>
1782   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1783                !strconcat("$dst = ",
1784                           !strconcat(opc , "($src1.L, $src2.H):rnd")),
1785                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1786
1787 class si_MInst_sisi_sat_rnd_lh<string opc, Intrinsic IntID>
1788   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1789                !strconcat("$dst = ",
1790                           !strconcat(opc , "($src1.L, $src2.H):rnd:sat")),
1791                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1792
1793 class si_MInst_sisi_sat_rnd_lh_s1<string opc, Intrinsic IntID>
1794   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1795                !strconcat("$dst = ",
1796                           !strconcat(opc , "($src1.L, $src2.H):<<1:rnd:sat")),
1797                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1798
1799 class si_MInst_sisi_rnd_lh_s1<string opc, Intrinsic IntID>
1800   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1801                !strconcat("$dst = ",
1802                           !strconcat(opc , "($src1.L, $src2.H):<<1:rnd")),
1803                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1804
1805 class si_MInst_sisi_sat_rnd_ll<string opc, Intrinsic IntID>
1806   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1807                !strconcat("$dst = ",
1808                           !strconcat(opc , "($src1.L, $src2.L):rnd:sat")),
1809                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1810
1811 class si_MInst_sisi_sat_rnd_ll_s1<string opc, Intrinsic IntID>
1812   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1813                !strconcat("$dst = ",
1814                           !strconcat(opc , "($src1.L, $src2.L):<<1:rnd:sat")),
1815                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1816
1817 class si_MInst_sisi_rnd_ll<string opc, Intrinsic IntID>
1818   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1819                !strconcat("$dst = ",
1820                           !strconcat(opc , "($src1.L, $src2.L):rnd")),
1821                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1822
1823 class si_MInst_sisi_rnd_ll_s1<string opc, Intrinsic IntID>
1824   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1825                !strconcat("$dst = ",
1826                           !strconcat(opc , "($src1.L, $src2.L):<<1:rnd")),
1827                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1828
1829 class di_MInst_dididi_acc_sat<string opc, Intrinsic IntID>
1830   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2,
1831                                            DoubleRegs:$src1, DoubleRegs:$src2),
1832                !strconcat("$dst += ", !strconcat(opc , "($src1, $src2):sat")),
1833                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
1834                                              DoubleRegs:$src1,
1835                                              DoubleRegs:$src2))],
1836                "$dst2 = $dst">;
1837
1838 class di_MInst_dididi_acc_rnd_sat<string opc, Intrinsic IntID>
1839   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
1840                                            DoubleRegs:$src2),
1841                !strconcat("$dst += ",
1842                           !strconcat(opc , "($src1, $src2):rnd:sat")),
1843                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
1844                                              DoubleRegs:$src1,
1845                                              DoubleRegs:$src2))],
1846                "$dst2 = $dst">;
1847
1848 class di_MInst_dididi_acc_s1<string opc, Intrinsic IntID>
1849   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2,
1850                                            DoubleRegs:$src1,
1851                                            DoubleRegs:$src2),
1852                !strconcat("$dst += ",
1853                           !strconcat(opc , "($src1, $src2):<<1")),
1854                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
1855                                              DoubleRegs:$src1,
1856                                              DoubleRegs:$src2))],
1857                "$dst2 = $dst">;
1858
1859
1860 class di_MInst_dididi_acc_s1_sat<string opc, Intrinsic IntID>
1861   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2,
1862                                            DoubleRegs:$src1,
1863                                            DoubleRegs:$src2),
1864                !strconcat("$dst += ",
1865                           !strconcat(opc , "($src1, $src2):<<1:sat")),
1866                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
1867                                              DoubleRegs:$src1,
1868                                              DoubleRegs:$src2))],
1869                "$dst2 = $dst">;
1870
1871 class di_MInst_dididi_acc_s1_rnd_sat<string opc, Intrinsic IntID>
1872   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
1873                                            DoubleRegs:$src2),
1874                !strconcat("$dst += ",
1875                           !strconcat(opc , "($src1, $src2):<<1:rnd:sat")),
1876                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
1877                                              DoubleRegs:$src1,
1878                                              DoubleRegs:$src2))],
1879                "$dst2 = $dst">;
1880
1881 class di_MInst_dididi_acc<string opc, Intrinsic IntID>
1882   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
1883                                            DoubleRegs:$src2),
1884                !strconcat("$dst += ", !strconcat(opc , "($src1, $src2)")),
1885                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
1886                                              DoubleRegs:$src1,
1887                                              DoubleRegs:$src2))],
1888                "$dst2 = $dst">;
1889
1890 class di_MInst_dididi_acc_conj<string opc, Intrinsic IntID>
1891   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
1892                                            DoubleRegs:$src2),
1893                !strconcat("$dst += ", !strconcat(opc , "($src1, $src2*)")),
1894                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
1895                                              DoubleRegs:$src1,
1896                                              DoubleRegs:$src2))],
1897                "$dst2 = $dst">;
1898
1899 class di_MInst_disisi_acc_hh<string opc, Intrinsic IntID>
1900   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1901                                            IntRegs:$src2),
1902                !strconcat("$dst += ", !strconcat(opc , "($src1.H, $src2.H)")),
1903                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1904                                              IntRegs:$src2))],
1905                "$dst2 = $dst">;
1906
1907 class di_MInst_disisi_acc_hl<string opc, Intrinsic IntID>
1908   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1909                                            IntRegs:$src2),
1910                !strconcat("$dst += ", !strconcat(opc , "($src1.H, $src2.L)")),
1911                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1912                                              IntRegs:$src2))],
1913                "$dst2 = $dst">;
1914
1915 class di_MInst_disisi_acc_lh<string opc, Intrinsic IntID>
1916   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1917                                            IntRegs:$src2),
1918                !strconcat("$dst += ", !strconcat(opc , "($src1.L, $src2.H)")),
1919                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1920                                              IntRegs:$src2))],
1921                "$dst2 = $dst">;
1922
1923 class di_MInst_disisi_acc_ll<string opc, Intrinsic IntID>
1924   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1925                                            IntRegs:$src2),
1926                !strconcat("$dst += ", !strconcat(opc , "($src1.L, $src2.L)")),
1927                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1928                                              IntRegs:$src2))],
1929                "$dst2 = $dst">;
1930
1931 class di_MInst_disisi_acc_hh_s1<string opc, Intrinsic IntID>
1932   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1933                                            IntRegs:$src2),
1934                !strconcat("$dst += ",
1935                           !strconcat(opc , "($src1.H, $src2.H):<<1")),
1936                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1937                                              IntRegs:$src2))],
1938                "$dst2 = $dst">;
1939
1940 class di_MInst_disisi_acc_hl_s1<string opc, Intrinsic IntID>
1941   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1942                                            IntRegs:$src2),
1943                !strconcat("$dst += ",
1944                           !strconcat(opc , "($src1.H, $src2.L):<<1")),
1945                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1946                                              IntRegs:$src2))],
1947                "$dst2 = $dst">;
1948
1949 class di_MInst_disisi_acc_lh_s1<string opc, Intrinsic IntID>
1950   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1951                                            IntRegs:$src2),
1952                !strconcat("$dst += ",
1953                           !strconcat(opc , "($src1.L, $src2.H):<<1")),
1954                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1955                                              IntRegs:$src2))],
1956                "$dst2 = $dst">;
1957
1958 class di_MInst_disisi_acc_ll_s1<string opc, Intrinsic IntID>
1959   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1960                                            IntRegs:$src2),
1961                !strconcat("$dst += ",
1962                           !strconcat(opc , "($src1.L, $src2.L):<<1")),
1963                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1964                                              IntRegs:$src2))],
1965                "$dst2 = $dst">;
1966
1967 class di_MInst_disisi_nac_hh<string opc, Intrinsic IntID>
1968   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1969                                            IntRegs:$src2),
1970                !strconcat("$dst -= ", !strconcat(opc , "($src1.H, $src2.H)")),
1971                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1972                                              IntRegs:$src2))],
1973                "$dst2 = $dst">;
1974
1975 class di_MInst_disisi_nac_hl<string opc, Intrinsic IntID>
1976   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1977                                            IntRegs:$src2),
1978                !strconcat("$dst -= ", !strconcat(opc , "($src1.H, $src2.L)")),
1979                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1980                                              IntRegs:$src2))],
1981                "$dst2 = $dst">;
1982
1983 class di_MInst_disisi_nac_lh<string opc, Intrinsic IntID>
1984   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1985                                            IntRegs:$src2),
1986                !strconcat("$dst -= ", !strconcat(opc , "($src1.L, $src2.H)")),
1987                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1988                                              IntRegs:$src2))],
1989                "$dst2 = $dst">;
1990
1991 class di_MInst_disisi_nac_ll<string opc, Intrinsic IntID>
1992   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1993                                            IntRegs:$src2),
1994                !strconcat("$dst -= ", !strconcat(opc , "($src1.L, $src2.L)")),
1995                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1996                                              IntRegs:$src2))],
1997                "$dst2 = $dst">;
1998
1999 class di_MInst_disisi_nac_hh_s1<string opc, Intrinsic IntID>
2000   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
2001                                            IntRegs:$src2),
2002                !strconcat("$dst -= ",
2003                           !strconcat(opc , "($src1.H, $src2.H):<<1")),
2004                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
2005                                              IntRegs:$src2))],
2006                "$dst2 = $dst">;
2007
2008 class di_MInst_disisi_nac_hl_s1<string opc, Intrinsic IntID>
2009   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
2010                                            IntRegs:$src2),
2011                !strconcat("$dst -= ",
2012                           !strconcat(opc , "($src1.H, $src2.L):<<1")),
2013                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
2014                                              IntRegs:$src2))],
2015                "$dst2 = $dst">;
2016
2017 class di_MInst_disisi_nac_lh_s1<string opc, Intrinsic IntID>
2018   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
2019                                            IntRegs:$src2),
2020                !strconcat("$dst -= ",
2021                           !strconcat(opc , "($src1.L, $src2.H):<<1")),
2022                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
2023                                              IntRegs:$src2))],
2024                "$dst2 = $dst">;
2025
2026 class di_MInst_disisi_nac_ll_s1<string opc, Intrinsic IntID>
2027   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
2028                                            IntRegs:$src2),
2029                !strconcat("$dst -= ",
2030                           !strconcat(opc , "($src1.L, $src2.L):<<1")),
2031                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
2032                                              IntRegs:$src2))],
2033                "$dst2 = $dst">;
2034
2035 class di_MInst_disisi_acc_s1_sat<string opc, Intrinsic IntID>
2036   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
2037                                            IntRegs:$src2),
2038                !strconcat("$dst += ",
2039                           !strconcat(opc , "($src1, $src2):<<1:sat")),
2040                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
2041                                              IntRegs:$src2))],
2042                "$dst2 = $dst">;
2043
2044 class di_MInst_disi_s1_sat<string opc, Intrinsic IntID>
2045   : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
2046              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):<<1:sat")),
2047              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, IntRegs:$src2))]>;
2048
2049 class di_MInst_didisi_acc_s1_sat<string opc, Intrinsic IntID>
2050   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
2051                                            IntRegs:$src2),
2052                !strconcat("$dst += ",
2053                           !strconcat(opc , "($src1, $src2):<<1:sat")),
2054                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
2055                                              DoubleRegs:$src1,
2056                                              IntRegs:$src2))],
2057                "$dst2 = $dst">;
2058
2059 class si_MInst_disi_s1_rnd_sat<string opc, Intrinsic IntID>
2060   : MInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
2061              !strconcat("$dst = ",
2062                         !strconcat(opc , "($src1, $src2):<<1:rnd:sat")),
2063              [(set IntRegs:$dst, (IntID DoubleRegs:$src1, IntRegs:$src2))]>;
2064
2065 class si_MInst_didi<string opc, Intrinsic IntID>
2066   : MInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
2067              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
2068              [(set IntRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
2069
2070 //
2071 // LDInst classes.
2072 //
2073 let mayLoad = 1, hasSideEffects = 0 in
2074 class di_LDInstPI_diu4<string opc, Intrinsic IntID>
2075   : LDInstPI<(outs IntRegs:$dst, DoubleRegs:$dst2),
2076            (ins IntRegs:$src1, IntRegs:$src2, CtrRegs:$src3, s4Imm:$offset),
2077            "$dst2 = memd($src1++#$offset:circ($src3))",
2078            [],
2079            "$src1 = $dst">;
2080
2081 /********************************************************************
2082 *            ALU32/ALU                                              *
2083 *********************************************************************/
2084
2085
2086 // ALU32 / ALU / Negate.
2087 def HEXAGON_A2_neg:
2088   si_ALU32_si                     <"neg",      int_hexagon_A2_neg>;
2089
2090 // ALU32 / ALU / Transfer Immediate.
2091 def HEXAGON_A2_tfril:
2092   si_lo_ALU32_siu16               <"",         int_hexagon_A2_tfril>;
2093 def HEXAGON_A2_tfrih:
2094   si_hi_ALU32_siu16               <"",         int_hexagon_A2_tfrih>;
2095 def HEXAGON_A2_tfrsi:
2096   si_ALU32_s16                    <"",         int_hexagon_A2_tfrsi>;
2097 def HEXAGON_A2_tfrpi:
2098   di_ALU32_s8                     <"",         int_hexagon_A2_tfrpi>;
2099
2100 // ALU32 / ALU / Transfer Register.
2101 def HEXAGON_A2_tfr:
2102   si_ALU32_si_tfr                  <"",        int_hexagon_A2_tfr>;
2103
2104 /********************************************************************
2105 *            ALU32/PERM                                             *
2106 *********************************************************************/
2107
2108 // ALU32 / PERM / Combine.
2109 def HEXAGON_A2_combinew:
2110   di_ALU32_sisi                   <"combine",  int_hexagon_A2_combinew>;
2111 def HEXAGON_A2_combine_hh:
2112   si_MInst_sisi_hh                <"combine",  int_hexagon_A2_combine_hh>;
2113 def HEXAGON_A2_combine_lh:
2114   si_MInst_sisi_lh                <"combine",  int_hexagon_A2_combine_lh>;
2115 def HEXAGON_A2_combine_hl:
2116   si_MInst_sisi_hl                <"combine",  int_hexagon_A2_combine_hl>;
2117 def HEXAGON_A2_combine_ll:
2118   si_MInst_sisi_ll                <"combine",  int_hexagon_A2_combine_ll>;
2119 def HEXAGON_A2_combineii:
2120   di_MInst_s8s8                   <"combine",  int_hexagon_A2_combineii>;
2121
2122 // ALU32 / PERM / Mux.
2123 def HEXAGON_C2_mux:
2124   si_ALU32_qisisi                 <"mux",      int_hexagon_C2_mux>;
2125 def HEXAGON_C2_muxri:
2126   si_ALU32_qis8si                 <"mux",      int_hexagon_C2_muxri>;
2127 def HEXAGON_C2_muxir:
2128   si_ALU32_qisis8                 <"mux",      int_hexagon_C2_muxir>;
2129 def HEXAGON_C2_muxii:
2130   si_ALU32_qis8s8                 <"mux",      int_hexagon_C2_muxii>;
2131
2132 // ALU32 / PERM / Shift halfword.
2133 def HEXAGON_A2_aslh:
2134   si_ALU32_si                     <"aslh",     int_hexagon_A2_aslh>;
2135 def HEXAGON_A2_asrh:
2136   si_ALU32_si                     <"asrh",     int_hexagon_A2_asrh>;
2137 def SI_to_SXTHI_asrh:
2138   si_ALU32_si                     <"asrh",     int_hexagon_SI_to_SXTHI_asrh>;
2139
2140 // ALU32 / PERM / Sign/zero extend.
2141 def HEXAGON_A2_sxth:
2142   si_ALU32_si                     <"sxth",     int_hexagon_A2_sxth>;
2143 def HEXAGON_A2_sxtb:
2144   si_ALU32_si                     <"sxtb",     int_hexagon_A2_sxtb>;
2145 def HEXAGON_A2_zxth:
2146   si_ALU32_si                     <"zxth",     int_hexagon_A2_zxth>;
2147 def HEXAGON_A2_zxtb:
2148   si_ALU32_si                     <"zxtb",     int_hexagon_A2_zxtb>;
2149
2150 /********************************************************************
2151 *            ALU32/PRED                                             *
2152 *********************************************************************/
2153
2154 // ALU32 / PRED / Compare.
2155 def HEXAGON_C2_cmpeq:
2156   qi_ALU32_sisi                   <"cmp.eq",   int_hexagon_C2_cmpeq>;
2157 def HEXAGON_C2_cmpeqi:
2158   qi_ALU32_sis10                  <"cmp.eq",   int_hexagon_C2_cmpeqi>;
2159 def HEXAGON_C2_cmpgei:
2160   qi_ALU32_sis8                   <"cmp.ge",   int_hexagon_C2_cmpgei>;
2161 def HEXAGON_C2_cmpgeui:
2162   qi_ALU32_siu8                   <"cmp.geu",  int_hexagon_C2_cmpgeui>;
2163 def HEXAGON_C2_cmpgt:
2164   qi_ALU32_sisi                   <"cmp.gt",   int_hexagon_C2_cmpgt>;
2165 def HEXAGON_C2_cmpgti:
2166   qi_ALU32_sis10                  <"cmp.gt",   int_hexagon_C2_cmpgti>;
2167 def HEXAGON_C2_cmpgtu:
2168   qi_ALU32_sisi                   <"cmp.gtu",  int_hexagon_C2_cmpgtu>;
2169 def HEXAGON_C2_cmpgtui:
2170   qi_ALU32_siu9                   <"cmp.gtu",  int_hexagon_C2_cmpgtui>;
2171 def HEXAGON_C2_cmplt:
2172   qi_ALU32_sisi                   <"cmp.lt",   int_hexagon_C2_cmplt>;
2173 def HEXAGON_C2_cmpltu:
2174   qi_ALU32_sisi                   <"cmp.ltu",  int_hexagon_C2_cmpltu>;
2175
2176 /********************************************************************
2177 *            ALU32/VH                                               *
2178 *********************************************************************/
2179
2180 // ALU32 / VH / Vector add halfwords.
2181 // Rd32=vadd[u]h(Rs32,Rt32:sat]
2182 def HEXAGON_A2_svaddh:
2183   si_ALU32_sisi                   <"vaddh",    int_hexagon_A2_svaddh>;
2184 def HEXAGON_A2_svaddhs:
2185   si_ALU32_sisi_sat               <"vaddh",    int_hexagon_A2_svaddhs>;
2186 def HEXAGON_A2_svadduhs:
2187   si_ALU32_sisi_sat               <"vadduh",   int_hexagon_A2_svadduhs>;
2188
2189 // ALU32 / VH / Vector average halfwords.
2190 def HEXAGON_A2_svavgh:
2191   si_ALU32_sisi                   <"vavgh",    int_hexagon_A2_svavgh>;
2192 def HEXAGON_A2_svavghs:
2193   si_ALU32_sisi_rnd               <"vavgh",    int_hexagon_A2_svavghs>;
2194 def HEXAGON_A2_svnavgh:
2195   si_ALU32_sisi                   <"vnavgh",   int_hexagon_A2_svnavgh>;
2196
2197 // ALU32 / VH / Vector subtract halfwords.
2198 def HEXAGON_A2_svsubh:
2199   si_ALU32_sisi                   <"vsubh",    int_hexagon_A2_svsubh>;
2200 def HEXAGON_A2_svsubhs:
2201   si_ALU32_sisi_sat               <"vsubh",    int_hexagon_A2_svsubhs>;
2202 def HEXAGON_A2_svsubuhs:
2203   si_ALU32_sisi_sat               <"vsubuh",   int_hexagon_A2_svsubuhs>;
2204
2205 /********************************************************************
2206 *            ALU64/ALU                                              *
2207 *********************************************************************/
2208
2209 // ALU64 / ALU / Add.
2210 def HEXAGON_A2_addp:
2211   di_ALU64_didi                   <"add",      int_hexagon_A2_addp>;
2212 def HEXAGON_A2_addsat:
2213   si_ALU64_sisi_sat               <"add",      int_hexagon_A2_addsat>;
2214
2215 // ALU64 / ALU / Add halfword.
2216 // Even though the definition says hl, it should be lh -
2217 //so DON'T change the class " si_ALU64_sisi_l16_lh " it inherits.
2218 def HEXAGON_A2_addh_l16_hl:
2219   si_ALU64_sisi_l16_lh            <"add",      int_hexagon_A2_addh_l16_hl>;
2220 def HEXAGON_A2_addh_l16_ll:
2221   si_ALU64_sisi_l16_ll            <"add",      int_hexagon_A2_addh_l16_ll>;
2222
2223 def HEXAGON_A2_addh_l16_sat_hl:
2224   si_ALU64_sisi_l16_sat_lh        <"add",      int_hexagon_A2_addh_l16_sat_hl>;
2225 def HEXAGON_A2_addh_l16_sat_ll:
2226   si_ALU64_sisi_l16_sat_ll        <"add",      int_hexagon_A2_addh_l16_sat_ll>;
2227
2228 def HEXAGON_A2_addh_h16_hh:
2229   si_ALU64_sisi_h16_hh            <"add",      int_hexagon_A2_addh_h16_hh>;
2230 def HEXAGON_A2_addh_h16_hl:
2231   si_ALU64_sisi_h16_hl            <"add",      int_hexagon_A2_addh_h16_hl>;
2232 def HEXAGON_A2_addh_h16_lh:
2233   si_ALU64_sisi_h16_lh            <"add",      int_hexagon_A2_addh_h16_lh>;
2234 def HEXAGON_A2_addh_h16_ll:
2235   si_ALU64_sisi_h16_ll            <"add",      int_hexagon_A2_addh_h16_ll>;
2236
2237 def HEXAGON_A2_addh_h16_sat_hh:
2238   si_ALU64_sisi_h16_sat_hh        <"add",      int_hexagon_A2_addh_h16_sat_hh>;
2239 def HEXAGON_A2_addh_h16_sat_hl:
2240   si_ALU64_sisi_h16_sat_hl        <"add",      int_hexagon_A2_addh_h16_sat_hl>;
2241 def HEXAGON_A2_addh_h16_sat_lh:
2242   si_ALU64_sisi_h16_sat_lh        <"add",      int_hexagon_A2_addh_h16_sat_lh>;
2243 def HEXAGON_A2_addh_h16_sat_ll:
2244   si_ALU64_sisi_h16_sat_ll        <"add",      int_hexagon_A2_addh_h16_sat_ll>;
2245
2246 // ALU64 / ALU / Compare.
2247 def HEXAGON_C2_cmpeqp:
2248   qi_ALU64_didi                   <"cmp.eq",   int_hexagon_C2_cmpeqp>;
2249 def HEXAGON_C2_cmpgtp:
2250   qi_ALU64_didi                   <"cmp.gt",   int_hexagon_C2_cmpgtp>;
2251 def HEXAGON_C2_cmpgtup:
2252   qi_ALU64_didi                   <"cmp.gtu",  int_hexagon_C2_cmpgtup>;
2253
2254 // ALU64 / ALU / Logical operations.
2255 def HEXAGON_A2_andp:
2256   di_ALU64_didi                   <"and",      int_hexagon_A2_andp>;
2257 def HEXAGON_A2_orp:
2258   di_ALU64_didi                   <"or",       int_hexagon_A2_orp>;
2259 def HEXAGON_A2_xorp:
2260   di_ALU64_didi                   <"xor",      int_hexagon_A2_xorp>;
2261
2262 // ALU64 / ALU / Maximum.
2263 def HEXAGON_A2_max:
2264   si_ALU64_sisi                   <"max",      int_hexagon_A2_max>;
2265 def HEXAGON_A2_maxu:
2266   si_ALU64_sisi                   <"maxu",     int_hexagon_A2_maxu>;
2267
2268 // ALU64 / ALU / Minimum.
2269 def HEXAGON_A2_min:
2270   si_ALU64_sisi                   <"min",      int_hexagon_A2_min>;
2271 def HEXAGON_A2_minu:
2272   si_ALU64_sisi                   <"minu",     int_hexagon_A2_minu>;
2273
2274 // ALU64 / ALU / Subtract.
2275 def HEXAGON_A2_subp:
2276   di_ALU64_didi                   <"sub",      int_hexagon_A2_subp>;
2277 def HEXAGON_A2_subsat:
2278   si_ALU64_sisi_sat               <"sub",      int_hexagon_A2_subsat>;
2279
2280 // ALU64 / ALU / Subtract halfword.
2281 // Even though the definition says hl, it should be lh -
2282 //so DON'T change the class " si_ALU64_sisi_l16_lh " it inherits.
2283 def HEXAGON_A2_subh_l16_hl:
2284   si_ALU64_sisi_l16_lh            <"sub",      int_hexagon_A2_subh_l16_hl>;
2285 def HEXAGON_A2_subh_l16_ll:
2286   si_ALU64_sisi_l16_ll            <"sub",      int_hexagon_A2_subh_l16_ll>;
2287
2288 def HEXAGON_A2_subh_l16_sat_hl:
2289   si_ALU64_sisi_l16_sat_lh        <"sub",      int_hexagon_A2_subh_l16_sat_hl>;
2290 def HEXAGON_A2_subh_l16_sat_ll:
2291   si_ALU64_sisi_l16_sat_ll        <"sub",      int_hexagon_A2_subh_l16_sat_ll>;
2292
2293 def HEXAGON_A2_subh_h16_hh:
2294   si_ALU64_sisi_h16_hh            <"sub",      int_hexagon_A2_subh_h16_hh>;
2295 def HEXAGON_A2_subh_h16_hl:
2296   si_ALU64_sisi_h16_hl            <"sub",      int_hexagon_A2_subh_h16_hl>;
2297 def HEXAGON_A2_subh_h16_lh:
2298   si_ALU64_sisi_h16_lh            <"sub",      int_hexagon_A2_subh_h16_lh>;
2299 def HEXAGON_A2_subh_h16_ll:
2300   si_ALU64_sisi_h16_ll            <"sub",      int_hexagon_A2_subh_h16_ll>;
2301
2302 def HEXAGON_A2_subh_h16_sat_hh:
2303   si_ALU64_sisi_h16_sat_hh        <"sub",      int_hexagon_A2_subh_h16_sat_hh>;
2304 def HEXAGON_A2_subh_h16_sat_hl:
2305   si_ALU64_sisi_h16_sat_hl        <"sub",      int_hexagon_A2_subh_h16_sat_hl>;
2306 def HEXAGON_A2_subh_h16_sat_lh:
2307   si_ALU64_sisi_h16_sat_lh        <"sub",      int_hexagon_A2_subh_h16_sat_lh>;
2308 def HEXAGON_A2_subh_h16_sat_ll:
2309   si_ALU64_sisi_h16_sat_ll        <"sub",      int_hexagon_A2_subh_h16_sat_ll>;
2310
2311 // ALU64 / ALU / Transfer register.
2312 def HEXAGON_A2_tfrp:
2313   di_ALU64_di                     <"",         int_hexagon_A2_tfrp>;
2314
2315 /********************************************************************
2316 *            ALU64/BIT                                              *
2317 *********************************************************************/
2318
2319 // ALU64 / BIT / Masked parity.
2320 def HEXAGON_S2_parityp:
2321   si_ALU64_didi                   <"parity",   int_hexagon_S2_parityp>;
2322
2323 /********************************************************************
2324 *            ALU64/PERM                                             *
2325 *********************************************************************/
2326
2327 // ALU64 / PERM / Vector pack high and low halfwords.
2328 def HEXAGON_S2_packhl:
2329   di_ALU64_sisi                   <"packhl",   int_hexagon_S2_packhl>;
2330
2331 /********************************************************************
2332 *            ALU64/VB                                               *
2333 *********************************************************************/
2334
2335 // ALU64 / VB / Vector add unsigned bytes.
2336 def HEXAGON_A2_vaddub:
2337   di_ALU64_didi                   <"vaddub",   int_hexagon_A2_vaddub>;
2338 def HEXAGON_A2_vaddubs:
2339   di_ALU64_didi_sat               <"vaddub",   int_hexagon_A2_vaddubs>;
2340
2341 // ALU64 / VB / Vector average unsigned bytes.
2342 def HEXAGON_A2_vavgub:
2343   di_ALU64_didi                   <"vavgub",   int_hexagon_A2_vavgub>;
2344 def HEXAGON_A2_vavgubr:
2345   di_ALU64_didi_rnd               <"vavgub",   int_hexagon_A2_vavgubr>;
2346
2347 // ALU64 / VB / Vector compare unsigned bytes.
2348 def HEXAGON_A2_vcmpbeq:
2349   qi_ALU64_didi                   <"vcmpb.eq", int_hexagon_A2_vcmpbeq>;
2350 def HEXAGON_A2_vcmpbgtu:
2351   qi_ALU64_didi                   <"vcmpb.gtu",int_hexagon_A2_vcmpbgtu>;
2352
2353 // ALU64 / VB / Vector maximum/minimum unsigned bytes.
2354 def HEXAGON_A2_vmaxub:
2355   di_ALU64_didi                   <"vmaxub",   int_hexagon_A2_vmaxub>;
2356 def HEXAGON_A2_vminub:
2357   di_ALU64_didi                   <"vminub",   int_hexagon_A2_vminub>;
2358
2359 // ALU64 / VB / Vector subtract unsigned bytes.
2360 def HEXAGON_A2_vsubub:
2361   di_ALU64_didi                   <"vsubub",   int_hexagon_A2_vsubub>;
2362 def HEXAGON_A2_vsububs:
2363   di_ALU64_didi_sat               <"vsubub",   int_hexagon_A2_vsububs>;
2364
2365 // ALU64 / VB / Vector mux.
2366 def HEXAGON_C2_vmux:
2367   di_ALU64_qididi                 <"vmux",     int_hexagon_C2_vmux>;
2368
2369
2370 /********************************************************************
2371 *            ALU64/VH                                               *
2372 *********************************************************************/
2373
2374 // ALU64 / VH / Vector add halfwords.
2375 // Rdd64=vadd[u]h(Rss64,Rtt64:sat]
2376 def HEXAGON_A2_vaddh:
2377   di_ALU64_didi                   <"vaddh",    int_hexagon_A2_vaddh>;
2378 def HEXAGON_A2_vaddhs:
2379   di_ALU64_didi_sat               <"vaddh",    int_hexagon_A2_vaddhs>;
2380 def HEXAGON_A2_vadduhs:
2381   di_ALU64_didi_sat               <"vadduh",   int_hexagon_A2_vadduhs>;
2382
2383 // ALU64 / VH / Vector average halfwords.
2384 // Rdd64=v[n]avg[u]h(Rss64,Rtt64:rnd/:crnd][:sat]
2385 def HEXAGON_A2_vavgh:
2386   di_ALU64_didi                   <"vavgh",    int_hexagon_A2_vavgh>;
2387 def HEXAGON_A2_vavghcr:
2388   di_ALU64_didi_crnd              <"vavgh",    int_hexagon_A2_vavghcr>;
2389 def HEXAGON_A2_vavghr:
2390   di_ALU64_didi_rnd               <"vavgh",    int_hexagon_A2_vavghr>;
2391 def HEXAGON_A2_vavguh:
2392   di_ALU64_didi                   <"vavguh",   int_hexagon_A2_vavguh>;
2393 def HEXAGON_A2_vavguhr:
2394   di_ALU64_didi_rnd               <"vavguh",   int_hexagon_A2_vavguhr>;
2395 def HEXAGON_A2_vnavgh:
2396   di_ALU64_didi                   <"vnavgh",   int_hexagon_A2_vnavgh>;
2397 def HEXAGON_A2_vnavghcr:
2398   di_ALU64_didi_crnd_sat          <"vnavgh",   int_hexagon_A2_vnavghcr>;
2399 def HEXAGON_A2_vnavghr:
2400   di_ALU64_didi_rnd_sat           <"vnavgh",   int_hexagon_A2_vnavghr>;
2401
2402 // ALU64 / VH / Vector compare halfwords.
2403 def HEXAGON_A2_vcmpheq:
2404   qi_ALU64_didi                   <"vcmph.eq", int_hexagon_A2_vcmpheq>;
2405 def HEXAGON_A2_vcmphgt:
2406   qi_ALU64_didi                   <"vcmph.gt", int_hexagon_A2_vcmphgt>;
2407 def HEXAGON_A2_vcmphgtu:
2408   qi_ALU64_didi                   <"vcmph.gtu",int_hexagon_A2_vcmphgtu>;
2409
2410 // ALU64 / VH / Vector maximum halfwords.
2411 def HEXAGON_A2_vmaxh:
2412   di_ALU64_didi                   <"vmaxh",    int_hexagon_A2_vmaxh>;
2413 def HEXAGON_A2_vmaxuh:
2414   di_ALU64_didi                   <"vmaxuh",   int_hexagon_A2_vmaxuh>;
2415
2416 // ALU64 / VH / Vector minimum halfwords.
2417 def HEXAGON_A2_vminh:
2418   di_ALU64_didi                   <"vminh",    int_hexagon_A2_vminh>;
2419 def HEXAGON_A2_vminuh:
2420   di_ALU64_didi                   <"vminuh",   int_hexagon_A2_vminuh>;
2421
2422 // ALU64 / VH / Vector subtract halfwords.
2423 def HEXAGON_A2_vsubh:
2424   di_ALU64_didi                   <"vsubh",    int_hexagon_A2_vsubh>;
2425 def HEXAGON_A2_vsubhs:
2426   di_ALU64_didi_sat               <"vsubh",    int_hexagon_A2_vsubhs>;
2427 def HEXAGON_A2_vsubuhs:
2428   di_ALU64_didi_sat               <"vsubuh",   int_hexagon_A2_vsubuhs>;
2429
2430
2431 /********************************************************************
2432 *            ALU64/VW                                               *
2433 *********************************************************************/
2434
2435 // ALU64 / VW / Vector add words.
2436 // Rdd32=vaddw(Rss32,Rtt32)[:sat]
2437 def HEXAGON_A2_vaddw:
2438   di_ALU64_didi                   <"vaddw",    int_hexagon_A2_vaddw>;
2439 def HEXAGON_A2_vaddws:
2440   di_ALU64_didi_sat               <"vaddw",   int_hexagon_A2_vaddws>;
2441
2442 // ALU64 / VW / Vector average words.
2443 def HEXAGON_A2_vavguw:
2444   di_ALU64_didi                   <"vavguw",   int_hexagon_A2_vavguw>;
2445 def HEXAGON_A2_vavguwr:
2446   di_ALU64_didi_rnd               <"vavguw",   int_hexagon_A2_vavguwr>;
2447 def HEXAGON_A2_vavgw:
2448   di_ALU64_didi                   <"vavgw",    int_hexagon_A2_vavgw>;
2449 def HEXAGON_A2_vavgwcr:
2450   di_ALU64_didi_crnd              <"vavgw",    int_hexagon_A2_vavgwcr>;
2451 def HEXAGON_A2_vavgwr:
2452   di_ALU64_didi_rnd               <"vavgw",    int_hexagon_A2_vavgwr>;
2453 def HEXAGON_A2_vnavgw:
2454   di_ALU64_didi                   <"vnavgw",   int_hexagon_A2_vnavgw>;
2455 def HEXAGON_A2_vnavgwcr:
2456   di_ALU64_didi_crnd_sat          <"vnavgw",   int_hexagon_A2_vnavgwcr>;
2457 def HEXAGON_A2_vnavgwr:
2458   di_ALU64_didi_rnd_sat           <"vnavgw",   int_hexagon_A2_vnavgwr>;
2459
2460 // ALU64 / VW / Vector compare words.
2461 def HEXAGON_A2_vcmpweq:
2462   qi_ALU64_didi                   <"vcmpw.eq", int_hexagon_A2_vcmpweq>;
2463 def HEXAGON_A2_vcmpwgt:
2464   qi_ALU64_didi                   <"vcmpw.gt", int_hexagon_A2_vcmpwgt>;
2465 def HEXAGON_A2_vcmpwgtu:
2466   qi_ALU64_didi                   <"vcmpw.gtu",int_hexagon_A2_vcmpwgtu>;
2467
2468 // ALU64 / VW / Vector maximum words.
2469 def HEXAGON_A2_vmaxw:
2470   di_ALU64_didi                   <"vmaxw",    int_hexagon_A2_vmaxw>;
2471 def HEXAGON_A2_vmaxuw:
2472   di_ALU64_didi                   <"vmaxuw",   int_hexagon_A2_vmaxuw>;
2473
2474 // ALU64 / VW / Vector minimum words.
2475 def HEXAGON_A2_vminw:
2476   di_ALU64_didi                   <"vminw",    int_hexagon_A2_vminw>;
2477 def HEXAGON_A2_vminuw:
2478   di_ALU64_didi                   <"vminuw",   int_hexagon_A2_vminuw>;
2479
2480 // ALU64 / VW / Vector subtract words.
2481 def HEXAGON_A2_vsubw:
2482   di_ALU64_didi                   <"vsubw",    int_hexagon_A2_vsubw>;
2483 def HEXAGON_A2_vsubws:
2484   di_ALU64_didi_sat               <"vsubw",    int_hexagon_A2_vsubws>;
2485
2486
2487 /********************************************************************
2488 *            CR                                                     *
2489 *********************************************************************/
2490
2491 // CR / Logical reductions on predicates.
2492 def HEXAGON_C2_all8:
2493   qi_SInst_qi                     <"all8",     int_hexagon_C2_all8>;
2494 def HEXAGON_C2_any8:
2495   qi_SInst_qi                     <"any8",     int_hexagon_C2_any8>;
2496
2497 // CR / Logical operations on predicates.
2498 def HEXAGON_C2_pxfer_map:
2499   qi_SInst_qi_pxfer               <"",         int_hexagon_C2_pxfer_map>;
2500 def HEXAGON_C2_and:
2501   qi_SInst_qiqi                   <"and",      int_hexagon_C2_and>;
2502 def HEXAGON_C2_andn:
2503   qi_SInst_qiqi_neg               <"and",      int_hexagon_C2_andn>;
2504 def HEXAGON_C2_not:
2505   qi_SInst_qi                     <"not",      int_hexagon_C2_not>;
2506 def HEXAGON_C2_or:
2507   qi_SInst_qiqi                   <"or",       int_hexagon_C2_or>;
2508 def HEXAGON_C2_orn:
2509   qi_SInst_qiqi_neg               <"or",       int_hexagon_C2_orn>;
2510 def HEXAGON_C2_xor:
2511   qi_SInst_qiqi                   <"xor",      int_hexagon_C2_xor>;
2512
2513
2514 /********************************************************************
2515 *            MTYPE/ALU                                              *
2516 *********************************************************************/
2517
2518 // MTYPE / ALU / Add and accumulate.
2519 def HEXAGON_M2_acci:
2520   si_MInst_sisisi_acc             <"add",      int_hexagon_M2_acci>;
2521 def HEXAGON_M2_accii:
2522   si_MInst_sisis8_acc             <"add",      int_hexagon_M2_accii>;
2523 def HEXAGON_M2_nacci:
2524   si_MInst_sisisi_nac             <"add",      int_hexagon_M2_nacci>;
2525 def HEXAGON_M2_naccii:
2526   si_MInst_sisis8_nac             <"add",      int_hexagon_M2_naccii>;
2527
2528 // MTYPE / ALU / Subtract and accumulate.
2529 def HEXAGON_M2_subacc:
2530   si_MInst_sisisi_acc             <"sub",      int_hexagon_M2_subacc>;
2531
2532 // MTYPE / ALU / Vector absolute difference.
2533 def HEXAGON_M2_vabsdiffh:
2534   di_MInst_didi                   <"vabsdiffh",int_hexagon_M2_vabsdiffh>;
2535 def HEXAGON_M2_vabsdiffw:
2536   di_MInst_didi                   <"vabsdiffw",int_hexagon_M2_vabsdiffw>;
2537
2538 // MTYPE / ALU / XOR and xor with destination.
2539 def HEXAGON_M2_xor_xacc:
2540   si_MInst_sisisi_xacc            <"xor",      int_hexagon_M2_xor_xacc>;
2541
2542
2543 /********************************************************************
2544 *            MTYPE/COMPLEX                                          *
2545 *********************************************************************/
2546
2547 // MTYPE / COMPLEX / Complex multiply.
2548 // Rdd[-+]=cmpy(Rs, Rt:<<1]:sat
2549 def HEXAGON_M2_cmpys_s1:
2550   di_MInst_sisi_s1_sat            <"cmpy",     int_hexagon_M2_cmpys_s1>;
2551 def HEXAGON_M2_cmpys_s0:
2552   di_MInst_sisi_sat               <"cmpy",     int_hexagon_M2_cmpys_s0>;
2553 def HEXAGON_M2_cmpysc_s1:
2554   di_MInst_sisi_s1_sat_conj       <"cmpy",     int_hexagon_M2_cmpysc_s1>;
2555 def HEXAGON_M2_cmpysc_s0:
2556   di_MInst_sisi_sat_conj          <"cmpy",     int_hexagon_M2_cmpysc_s0>;
2557
2558 def HEXAGON_M2_cmacs_s1:
2559   di_MInst_disisi_acc_s1_sat      <"cmpy",     int_hexagon_M2_cmacs_s1>;
2560 def HEXAGON_M2_cmacs_s0:
2561   di_MInst_disisi_acc_sat         <"cmpy",     int_hexagon_M2_cmacs_s0>;
2562 def HEXAGON_M2_cmacsc_s1:
2563   di_MInst_disisi_acc_s1_sat_conj <"cmpy",     int_hexagon_M2_cmacsc_s1>;
2564 def HEXAGON_M2_cmacsc_s0:
2565   di_MInst_disisi_acc_sat_conj    <"cmpy",     int_hexagon_M2_cmacsc_s0>;
2566
2567 def HEXAGON_M2_cnacs_s1:
2568   di_MInst_disisi_nac_s1_sat      <"cmpy",     int_hexagon_M2_cnacs_s1>;
2569 def HEXAGON_M2_cnacs_s0:
2570   di_MInst_disisi_nac_sat         <"cmpy",     int_hexagon_M2_cnacs_s0>;
2571 def HEXAGON_M2_cnacsc_s1:
2572   di_MInst_disisi_nac_s1_sat_conj <"cmpy",     int_hexagon_M2_cnacsc_s1>;
2573 def HEXAGON_M2_cnacsc_s0:
2574   di_MInst_disisi_nac_sat_conj    <"cmpy",     int_hexagon_M2_cnacsc_s0>;
2575
2576 // MTYPE / COMPLEX / Complex multiply real or imaginary.
2577 def HEXAGON_M2_cmpyr_s0:
2578   di_MInst_sisi                   <"cmpyr",    int_hexagon_M2_cmpyr_s0>;
2579 def HEXAGON_M2_cmacr_s0:
2580   di_MInst_disisi_acc             <"cmpyr",    int_hexagon_M2_cmacr_s0>;
2581
2582 def HEXAGON_M2_cmpyi_s0:
2583   di_MInst_sisi                   <"cmpyi",    int_hexagon_M2_cmpyi_s0>;
2584 def HEXAGON_M2_cmaci_s0:
2585   di_MInst_disisi_acc             <"cmpyi",    int_hexagon_M2_cmaci_s0>;
2586
2587 // MTYPE / COMPLEX / Complex multiply with round and pack.
2588 // Rxx32+=cmpy(Rs32,[*]Rt32:<<1]:rnd:sat
2589 def HEXAGON_M2_cmpyrs_s0:
2590   si_MInst_sisi_rnd_sat           <"cmpy",     int_hexagon_M2_cmpyrs_s0>;
2591 def HEXAGON_M2_cmpyrs_s1:
2592   si_MInst_sisi_s1_rnd_sat        <"cmpy",     int_hexagon_M2_cmpyrs_s1>;
2593
2594 def HEXAGON_M2_cmpyrsc_s0:
2595   si_MInst_sisi_rnd_sat_conj      <"cmpy",     int_hexagon_M2_cmpyrsc_s0>;
2596 def HEXAGON_M2_cmpyrsc_s1:
2597   si_MInst_sisi_s1_rnd_sat_conj   <"cmpy",     int_hexagon_M2_cmpyrsc_s1>;
2598
2599 //MTYPE / COMPLEX / Vector complex multiply real or imaginary.
2600 def HEXAGON_M2_vcmpy_s0_sat_i:
2601   di_MInst_didi_sat               <"vcmpyi",   int_hexagon_M2_vcmpy_s0_sat_i>;
2602 def HEXAGON_M2_vcmpy_s1_sat_i:
2603   di_MInst_didi_s1_sat            <"vcmpyi",   int_hexagon_M2_vcmpy_s1_sat_i>;
2604
2605 def HEXAGON_M2_vcmpy_s0_sat_r:
2606   di_MInst_didi_sat               <"vcmpyr",   int_hexagon_M2_vcmpy_s0_sat_r>;
2607 def HEXAGON_M2_vcmpy_s1_sat_r:
2608   di_MInst_didi_s1_sat            <"vcmpyr",   int_hexagon_M2_vcmpy_s1_sat_r>;
2609
2610 def HEXAGON_M2_vcmac_s0_sat_i:
2611   di_MInst_dididi_acc_sat         <"vcmpyi",   int_hexagon_M2_vcmac_s0_sat_i>;
2612 def HEXAGON_M2_vcmac_s0_sat_r:
2613   di_MInst_dididi_acc_sat         <"vcmpyr",   int_hexagon_M2_vcmac_s0_sat_r>;
2614
2615 //MTYPE / COMPLEX / Vector reduce complex multiply real or imaginary.
2616 def HEXAGON_M2_vrcmpyi_s0:
2617   di_MInst_didi                   <"vrcmpyi",  int_hexagon_M2_vrcmpyi_s0>;
2618 def HEXAGON_M2_vrcmpyr_s0:
2619   di_MInst_didi                   <"vrcmpyr",  int_hexagon_M2_vrcmpyr_s0>;
2620
2621 def HEXAGON_M2_vrcmpyi_s0c:
2622   di_MInst_didi_conj              <"vrcmpyi",  int_hexagon_M2_vrcmpyi_s0c>;
2623 def HEXAGON_M2_vrcmpyr_s0c:
2624   di_MInst_didi_conj              <"vrcmpyr",  int_hexagon_M2_vrcmpyr_s0c>;
2625
2626 def HEXAGON_M2_vrcmaci_s0:
2627   di_MInst_dididi_acc             <"vrcmpyi",  int_hexagon_M2_vrcmaci_s0>;
2628 def HEXAGON_M2_vrcmacr_s0:
2629   di_MInst_dididi_acc             <"vrcmpyr",  int_hexagon_M2_vrcmacr_s0>;
2630
2631 def HEXAGON_M2_vrcmaci_s0c:
2632   di_MInst_dididi_acc_conj        <"vrcmpyi",  int_hexagon_M2_vrcmaci_s0c>;
2633 def HEXAGON_M2_vrcmacr_s0c:
2634   di_MInst_dididi_acc_conj        <"vrcmpyr",  int_hexagon_M2_vrcmacr_s0c>;
2635
2636
2637 /********************************************************************
2638 *            MTYPE/MPYH                                             *
2639 *********************************************************************/
2640
2641 // MTYPE / MPYH / Multiply and use lower result.
2642 //def HEXAGON_M2_mpysmi:
2643 //FIXME: Hexagon_M2_mpysmi should really by of the type si_MInst_sim9,
2644 // not si_MInst_sis9 - but for now, we will use s9.
2645 // def Hexagon_M2_mpysmi:
2646 //  si_MInst_sim9                   <"mpyi",     int_hexagon_M2_mpysmi>;
2647 def Hexagon_M2_mpysmi:
2648   si_MInst_sis9                   <"mpyi",     int_hexagon_M2_mpysmi>;
2649 def HEXAGON_M2_mpyi:
2650   si_MInst_sisi                   <"mpyi",     int_hexagon_M2_mpyi>;
2651 def HEXAGON_M2_mpyui:
2652   si_MInst_sisi                   <"mpyui",    int_hexagon_M2_mpyui>;
2653 def HEXAGON_M2_macsip:
2654   si_MInst_sisiu8_acc             <"mpyi",     int_hexagon_M2_macsip>;
2655 def HEXAGON_M2_maci:
2656   si_MInst_sisisi_acc             <"mpyi",     int_hexagon_M2_maci>;
2657 def HEXAGON_M2_macsin:
2658   si_MInst_sisiu8_nac             <"mpyi",     int_hexagon_M2_macsin>;
2659
2660 // MTYPE / MPYH / Multiply word by half (32x16).
2661 //Rdd[+]=vmpywoh(Rss,Rtt)[:<<1][:rnd][:sat]
2662 //Rdd[+]=vmpyweh(Rss,Rtt)[:<<1][:rnd][:sat]
2663 def HEXAGON_M2_mmpyl_rs1:
2664   di_MInst_didi_s1_rnd_sat        <"vmpyweh",  int_hexagon_M2_mmpyl_rs1>;
2665 def HEXAGON_M2_mmpyl_s1:
2666   di_MInst_didi_s1_sat            <"vmpyweh",  int_hexagon_M2_mmpyl_s1>;
2667 def HEXAGON_M2_mmpyl_rs0:
2668   di_MInst_didi_rnd_sat           <"vmpyweh",  int_hexagon_M2_mmpyl_rs0>;
2669 def HEXAGON_M2_mmpyl_s0:
2670   di_MInst_didi_sat               <"vmpyweh",  int_hexagon_M2_mmpyl_s0>;
2671 def HEXAGON_M2_mmpyh_rs1:
2672   di_MInst_didi_s1_rnd_sat        <"vmpywoh",  int_hexagon_M2_mmpyh_rs1>;
2673 def HEXAGON_M2_mmpyh_s1:
2674   di_MInst_didi_s1_sat            <"vmpywoh",  int_hexagon_M2_mmpyh_s1>;
2675 def HEXAGON_M2_mmpyh_rs0:
2676   di_MInst_didi_rnd_sat           <"vmpywoh",  int_hexagon_M2_mmpyh_rs0>;
2677 def HEXAGON_M2_mmpyh_s0:
2678   di_MInst_didi_sat               <"vmpywoh",  int_hexagon_M2_mmpyh_s0>;
2679 def HEXAGON_M2_mmacls_rs1:
2680   di_MInst_dididi_acc_s1_rnd_sat  <"vmpyweh",  int_hexagon_M2_mmacls_rs1>;
2681 def HEXAGON_M2_mmacls_s1:
2682   di_MInst_dididi_acc_s1_sat      <"vmpyweh",  int_hexagon_M2_mmacls_s1>;
2683 def HEXAGON_M2_mmacls_rs0:
2684   di_MInst_dididi_acc_rnd_sat     <"vmpyweh",  int_hexagon_M2_mmacls_rs0>;
2685 def HEXAGON_M2_mmacls_s0:
2686   di_MInst_dididi_acc_sat         <"vmpyweh",  int_hexagon_M2_mmacls_s0>;
2687 def HEXAGON_M2_mmachs_rs1:
2688   di_MInst_dididi_acc_s1_rnd_sat  <"vmpywoh",  int_hexagon_M2_mmachs_rs1>;
2689 def HEXAGON_M2_mmachs_s1:
2690   di_MInst_dididi_acc_s1_sat      <"vmpywoh",  int_hexagon_M2_mmachs_s1>;
2691 def HEXAGON_M2_mmachs_rs0:
2692   di_MInst_dididi_acc_rnd_sat     <"vmpywoh",  int_hexagon_M2_mmachs_rs0>;
2693 def HEXAGON_M2_mmachs_s0:
2694   di_MInst_dididi_acc_sat         <"vmpywoh",  int_hexagon_M2_mmachs_s0>;
2695
2696 // MTYPE / MPYH / Multiply word by unsigned half (32x16).
2697 //Rdd[+]=vmpywouh(Rss,Rtt)[:<<1][:rnd][:sat]
2698 //Rdd[+]=vmpyweuh(Rss,Rtt)[:<<1][:rnd][:sat]
2699 def HEXAGON_M2_mmpyul_rs1:
2700   di_MInst_didi_s1_rnd_sat        <"vmpyweuh", int_hexagon_M2_mmpyul_rs1>;
2701 def HEXAGON_M2_mmpyul_s1:
2702   di_MInst_didi_s1_sat            <"vmpyweuh", int_hexagon_M2_mmpyul_s1>;
2703 def HEXAGON_M2_mmpyul_rs0:
2704   di_MInst_didi_rnd_sat           <"vmpyweuh", int_hexagon_M2_mmpyul_rs0>;
2705 def HEXAGON_M2_mmpyul_s0:
2706   di_MInst_didi_sat               <"vmpyweuh", int_hexagon_M2_mmpyul_s0>;
2707 def HEXAGON_M2_mmpyuh_rs1:
2708   di_MInst_didi_s1_rnd_sat        <"vmpywouh", int_hexagon_M2_mmpyuh_rs1>;
2709 def HEXAGON_M2_mmpyuh_s1:
2710   di_MInst_didi_s1_sat            <"vmpywouh", int_hexagon_M2_mmpyuh_s1>;
2711 def HEXAGON_M2_mmpyuh_rs0:
2712   di_MInst_didi_rnd_sat           <"vmpywouh", int_hexagon_M2_mmpyuh_rs0>;
2713 def HEXAGON_M2_mmpyuh_s0:
2714   di_MInst_didi_sat               <"vmpywouh", int_hexagon_M2_mmpyuh_s0>;
2715 def HEXAGON_M2_mmaculs_rs1:
2716   di_MInst_dididi_acc_s1_rnd_sat  <"vmpyweuh", int_hexagon_M2_mmaculs_rs1>;
2717 def HEXAGON_M2_mmaculs_s1:
2718   di_MInst_dididi_acc_s1_sat      <"vmpyweuh", int_hexagon_M2_mmaculs_s1>;
2719 def HEXAGON_M2_mmaculs_rs0:
2720   di_MInst_dididi_acc_rnd_sat     <"vmpyweuh", int_hexagon_M2_mmaculs_rs0>;
2721 def HEXAGON_M2_mmaculs_s0:
2722   di_MInst_dididi_acc_sat         <"vmpyweuh", int_hexagon_M2_mmaculs_s0>;
2723 def HEXAGON_M2_mmacuhs_rs1:
2724   di_MInst_dididi_acc_s1_rnd_sat  <"vmpywouh", int_hexagon_M2_mmacuhs_rs1>;
2725 def HEXAGON_M2_mmacuhs_s1:
2726   di_MInst_dididi_acc_s1_sat      <"vmpywouh", int_hexagon_M2_mmacuhs_s1>;
2727 def HEXAGON_M2_mmacuhs_rs0:
2728   di_MInst_dididi_acc_rnd_sat     <"vmpywouh", int_hexagon_M2_mmacuhs_rs0>;
2729 def HEXAGON_M2_mmacuhs_s0:
2730   di_MInst_dididi_acc_sat         <"vmpywouh", int_hexagon_M2_mmacuhs_s0>;
2731
2732 // MTYPE / MPYH / Multiply and use upper result.
2733 def HEXAGON_M2_hmmpyh_rs1:
2734   si_MInst_sisi_h_s1_rnd_sat      <"mpy",      int_hexagon_M2_hmmpyh_rs1>;
2735 def HEXAGON_M2_hmmpyl_rs1:
2736   si_MInst_sisi_l_s1_rnd_sat      <"mpy",      int_hexagon_M2_hmmpyl_rs1>;
2737 def HEXAGON_M2_mpy_up:
2738   si_MInst_sisi                   <"mpy",      int_hexagon_M2_mpy_up>;
2739 def HEXAGON_M2_dpmpyss_rnd_s0:
2740   si_MInst_sisi_rnd               <"mpy",      int_hexagon_M2_dpmpyss_rnd_s0>;
2741 def HEXAGON_M2_mpyu_up:
2742   si_MInst_sisi                   <"mpyu",     int_hexagon_M2_mpyu_up>;
2743
2744 // MTYPE / MPYH / Multiply and use full result.
2745 def HEXAGON_M2_dpmpyuu_s0:
2746   di_MInst_sisi                   <"mpyu",     int_hexagon_M2_dpmpyuu_s0>;
2747 def HEXAGON_M2_dpmpyuu_acc_s0:
2748   di_MInst_disisi_acc             <"mpyu",     int_hexagon_M2_dpmpyuu_acc_s0>;
2749 def HEXAGON_M2_dpmpyuu_nac_s0:
2750   di_MInst_disisi_nac             <"mpyu",     int_hexagon_M2_dpmpyuu_nac_s0>;
2751 def HEXAGON_M2_dpmpyss_s0:
2752   di_MInst_sisi                   <"mpy",      int_hexagon_M2_dpmpyss_s0>;
2753 def HEXAGON_M2_dpmpyss_acc_s0:
2754   di_MInst_disisi_acc             <"mpy",      int_hexagon_M2_dpmpyss_acc_s0>;
2755 def HEXAGON_M2_dpmpyss_nac_s0:
2756   di_MInst_disisi_nac             <"mpy",      int_hexagon_M2_dpmpyss_nac_s0>;
2757
2758 /********************************************************************
2759 *            MTYPE/VB                                               *
2760 *********************************************************************/
2761
2762 // MTYPE / VB / Vector reduce add unsigned bytes.
2763 def HEXAGON_A2_vraddub:
2764   di_MInst_didi                   <"vraddub", int_hexagon_A2_vraddub>;
2765 def HEXAGON_A2_vraddub_acc:
2766   di_MInst_dididi_acc             <"vraddub", int_hexagon_A2_vraddub_acc>;
2767
2768 // MTYPE / VB / Vector sum of absolute differences unsigned bytes.
2769 def HEXAGON_A2_vrsadub:
2770   di_MInst_didi                   <"vrsadub", int_hexagon_A2_vrsadub>;
2771 def HEXAGON_A2_vrsadub_acc:
2772   di_MInst_dididi_acc             <"vrsadub", int_hexagon_A2_vrsadub_acc>;
2773
2774 /********************************************************************
2775 *            MTYPE/VH                                               *
2776 *********************************************************************/
2777
2778 // MTYPE / VH / Vector dual multiply.
2779 def HEXAGON_M2_vdmpys_s1:
2780   di_MInst_didi_s1_sat            <"vdmpy",   int_hexagon_M2_vdmpys_s1>;
2781 def HEXAGON_M2_vdmpys_s0:
2782   di_MInst_didi_sat               <"vdmpy",   int_hexagon_M2_vdmpys_s0>;
2783 def HEXAGON_M2_vdmacs_s1:
2784   di_MInst_dididi_acc_s1_sat      <"vdmpy",   int_hexagon_M2_vdmacs_s1>;
2785 def HEXAGON_M2_vdmacs_s0:
2786   di_MInst_dididi_acc_sat         <"vdmpy",   int_hexagon_M2_vdmacs_s0>;
2787
2788 // MTYPE / VH / Vector dual multiply with round and pack.
2789 def HEXAGON_M2_vdmpyrs_s0:
2790   si_MInst_didi_rnd_sat           <"vdmpy",   int_hexagon_M2_vdmpyrs_s0>;
2791 def HEXAGON_M2_vdmpyrs_s1:
2792   si_MInst_didi_s1_rnd_sat        <"vdmpy",   int_hexagon_M2_vdmpyrs_s1>;
2793
2794 // MTYPE / VH / Vector multiply even halfwords.
2795 def HEXAGON_M2_vmpy2es_s1:
2796   di_MInst_didi_s1_sat            <"vmpyeh",  int_hexagon_M2_vmpy2es_s1>;
2797 def HEXAGON_M2_vmpy2es_s0:
2798   di_MInst_didi_sat               <"vmpyeh",  int_hexagon_M2_vmpy2es_s0>;
2799 def HEXAGON_M2_vmac2es:
2800   di_MInst_dididi_acc             <"vmpyeh",  int_hexagon_M2_vmac2es>;
2801 def HEXAGON_M2_vmac2es_s1:
2802   di_MInst_dididi_acc_s1_sat      <"vmpyeh",  int_hexagon_M2_vmac2es_s1>;
2803 def HEXAGON_M2_vmac2es_s0:
2804   di_MInst_dididi_acc_sat         <"vmpyeh",  int_hexagon_M2_vmac2es_s0>;
2805
2806 // MTYPE / VH / Vector multiply halfwords.
2807 def HEXAGON_M2_vmpy2s_s0:
2808   di_MInst_sisi_sat               <"vmpyh",   int_hexagon_M2_vmpy2s_s0>;
2809 def HEXAGON_M2_vmpy2s_s1:
2810   di_MInst_sisi_s1_sat            <"vmpyh",   int_hexagon_M2_vmpy2s_s1>;
2811 def HEXAGON_M2_vmac2:
2812   di_MInst_disisi_acc             <"vmpyh",   int_hexagon_M2_vmac2>;
2813 def HEXAGON_M2_vmac2s_s0:
2814   di_MInst_disisi_acc_sat         <"vmpyh",   int_hexagon_M2_vmac2s_s0>;
2815 def HEXAGON_M2_vmac2s_s1:
2816   di_MInst_disisi_acc_s1_sat      <"vmpyh",   int_hexagon_M2_vmac2s_s1>;
2817
2818 // MTYPE / VH / Vector multiply halfwords with round and pack.
2819 def HEXAGON_M2_vmpy2s_s0pack:
2820   si_MInst_sisi_rnd_sat           <"vmpyh",   int_hexagon_M2_vmpy2s_s0pack>;
2821 def HEXAGON_M2_vmpy2s_s1pack:
2822   si_MInst_sisi_s1_rnd_sat        <"vmpyh",   int_hexagon_M2_vmpy2s_s1pack>;
2823
2824 // MTYPE / VH / Vector reduce multiply halfwords.
2825 // Rxx32+=vrmpyh(Rss32,Rtt32)
2826 def HEXAGON_M2_vrmpy_s0:
2827   di_MInst_didi                   <"vrmpyh",  int_hexagon_M2_vrmpy_s0>;
2828 def HEXAGON_M2_vrmac_s0:
2829   di_MInst_dididi_acc             <"vrmpyh",  int_hexagon_M2_vrmac_s0>;
2830
2831
2832 /********************************************************************
2833 *            STYPE/ALU                                              *
2834 *********************************************************************/
2835
2836 // STYPE / ALU / Absolute value.
2837 def HEXAGON_A2_abs:
2838   si_SInst_si                     <"abs",     int_hexagon_A2_abs>;
2839 def HEXAGON_A2_absp:
2840   di_SInst_di                     <"abs",     int_hexagon_A2_absp>;
2841 def HEXAGON_A2_abssat:
2842   si_SInst_si_sat                 <"abs",     int_hexagon_A2_abssat>;
2843
2844 // STYPE / ALU / Negate.
2845 def HEXAGON_A2_negp:
2846   di_SInst_di                     <"neg",     int_hexagon_A2_negp>;
2847 def HEXAGON_A2_negsat:
2848   si_SInst_si_sat                 <"neg",     int_hexagon_A2_negsat>;
2849
2850 // STYPE / ALU / Logical Not.
2851 def HEXAGON_A2_notp:
2852   di_SInst_di                     <"not",     int_hexagon_A2_notp>;
2853
2854 // STYPE / ALU / Sign extend word to doubleword.
2855 def HEXAGON_A2_sxtw:
2856   di_SInst_si                     <"sxtw",     int_hexagon_A2_sxtw>;
2857
2858
2859 /********************************************************************
2860 *            STYPE/BIT                                              *
2861 *********************************************************************/
2862
2863 // STYPE / BIT / Count leading.
2864 def HEXAGON_S2_cl0:
2865   si_SInst_si                     <"cl0",     int_hexagon_S2_cl0>;
2866 def HEXAGON_S2_cl0p:
2867   si_SInst_di                     <"cl0",     int_hexagon_S2_cl0p>;
2868 def HEXAGON_S2_cl1:
2869   si_SInst_si                     <"cl1",     int_hexagon_S2_cl1>;
2870 def HEXAGON_S2_cl1p:
2871   si_SInst_di                     <"cl1",     int_hexagon_S2_cl1p>;
2872 def HEXAGON_S2_clb:
2873   si_SInst_si                     <"clb",     int_hexagon_S2_clb>;
2874 def HEXAGON_S2_clbp:
2875   si_SInst_di                     <"clb",     int_hexagon_S2_clbp>;
2876 def HEXAGON_S2_clbnorm:
2877   si_SInst_si                     <"normamt", int_hexagon_S2_clbnorm>;
2878
2879 // STYPE / BIT / Count trailing.
2880 def HEXAGON_S2_ct0:
2881   si_SInst_si                     <"ct0",     int_hexagon_S2_ct0>;
2882 def HEXAGON_S2_ct1:
2883   si_SInst_si                     <"ct1",     int_hexagon_S2_ct1>;
2884
2885 // STYPE / BIT / Compare bit mask.
2886 def Hexagon_C2_bitsclr:
2887   qi_SInst_sisi                   <"bitsclr", int_hexagon_C2_bitsclr>;
2888 def Hexagon_C2_bitsclri:
2889   qi_SInst_siu6                   <"bitsclr", int_hexagon_C2_bitsclri>;
2890 def Hexagon_C2_bitsset:
2891   qi_SInst_sisi                   <"bitsset", int_hexagon_C2_bitsset>;
2892
2893 // STYPE / BIT / Extract unsigned.
2894 // Rd[d][32/64]=extractu(Rs[s],Rt[t],[imm])
2895 def HEXAGON_S2_extractu:
2896   si_SInst_siu5u5                 <"extractu",int_hexagon_S2_extractu>;
2897 def HEXAGON_S2_extractu_rp:
2898   si_SInst_sidi                   <"extractu",int_hexagon_S2_extractu_rp>;
2899 def HEXAGON_S2_extractup:
2900   di_SInst_diu6u6                 <"extractu",int_hexagon_S2_extractup>;
2901 def HEXAGON_S2_extractup_rp:
2902   di_SInst_didi                   <"extractu",int_hexagon_S2_extractup_rp>;
2903
2904 // STYPE / BIT / Insert bitfield.
2905 def Hexagon_S2_insert:
2906   si_SInst_sisiu5u5               <"insert",  int_hexagon_S2_insert>;
2907 def Hexagon_S2_insert_rp:
2908   si_SInst_sisidi                 <"insert",  int_hexagon_S2_insert_rp>;
2909 def Hexagon_S2_insertp:
2910   di_SInst_didiu6u6               <"insert",  int_hexagon_S2_insertp>;
2911 def Hexagon_S2_insertp_rp:
2912   di_SInst_dididi                 <"insert",  int_hexagon_S2_insertp_rp>;
2913
2914 // STYPE / BIT / Innterleave/deinterleave.
2915 def Hexagon_S2_interleave:
2916   di_SInst_di                     <"interleave", int_hexagon_S2_interleave>;
2917 def Hexagon_S2_deinterleave:
2918   di_SInst_di                     <"deinterleave", int_hexagon_S2_deinterleave>;
2919
2920 // STYPE / BIT / Linear feedback-shift Iteration.
2921 def Hexagon_S2_lfsp:
2922   di_SInst_didi                   <"lfs",     int_hexagon_S2_lfsp>;
2923
2924 // STYPE / BIT / Bit reverse.
2925 def Hexagon_S2_brev:
2926   si_SInst_si                     <"brev",    int_hexagon_S2_brev>;
2927
2928 // STYPE / BIT / Set/Clear/Toggle Bit.
2929 def HEXAGON_S2_setbit_i:
2930   si_SInst_siu5                   <"setbit",  int_hexagon_S2_setbit_i>;
2931 def HEXAGON_S2_togglebit_i:
2932   si_SInst_siu5                   <"togglebit", int_hexagon_S2_togglebit_i>;
2933 def HEXAGON_S2_clrbit_i:
2934   si_SInst_siu5                   <"clrbit",  int_hexagon_S2_clrbit_i>;
2935 def HEXAGON_S2_setbit_r:
2936   si_SInst_sisi                   <"setbit",  int_hexagon_S2_setbit_r>;
2937 def HEXAGON_S2_togglebit_r:
2938   si_SInst_sisi                   <"togglebit", int_hexagon_S2_togglebit_r>;
2939 def HEXAGON_S2_clrbit_r:
2940   si_SInst_sisi                   <"clrbit",  int_hexagon_S2_clrbit_r>;
2941
2942 // STYPE / BIT / Test Bit.
2943 def HEXAGON_S2_tstbit_i:
2944   qi_SInst_siu5                   <"tstbit",  int_hexagon_S2_tstbit_i>;
2945 def HEXAGON_S2_tstbit_r:
2946   qi_SInst_sisi                   <"tstbit",  int_hexagon_S2_tstbit_r>;
2947
2948
2949 /********************************************************************
2950 *            STYPE/COMPLEX                                          *
2951 *********************************************************************/
2952
2953 // STYPE / COMPLEX / Vector Complex conjugate.
2954 def HEXAGON_A2_vconj:
2955   di_SInst_di_sat                 <"vconj",   int_hexagon_A2_vconj>;
2956
2957 // STYPE / COMPLEX / Vector Complex rotate.
2958 def HEXAGON_S2_vcrotate:
2959   di_SInst_disi                   <"vcrotate",int_hexagon_S2_vcrotate>;
2960
2961
2962 /********************************************************************
2963 *            STYPE/PERM                                             *
2964 *********************************************************************/
2965
2966 // STYPE / PERM / Saturate.
2967 def HEXAGON_A2_sat:
2968   si_SInst_di                     <"sat",     int_hexagon_A2_sat>;
2969 def HEXAGON_A2_satb:
2970   si_SInst_si                     <"satb",    int_hexagon_A2_satb>;
2971 def HEXAGON_A2_sath:
2972   si_SInst_si                     <"sath",    int_hexagon_A2_sath>;
2973 def HEXAGON_A2_satub:
2974   si_SInst_si                     <"satub",   int_hexagon_A2_satub>;
2975 def HEXAGON_A2_satuh:
2976   si_SInst_si                     <"satuh",   int_hexagon_A2_satuh>;
2977
2978 // STYPE / PERM / Swizzle bytes.
2979 def HEXAGON_A2_swiz:
2980   si_SInst_si                     <"swiz",    int_hexagon_A2_swiz>;
2981
2982 // STYPE / PERM / Vector align.
2983 // Need custom lowering
2984 def HEXAGON_S2_valignib:
2985   di_SInst_didiu3                 <"valignb", int_hexagon_S2_valignib>;
2986 def HEXAGON_S2_valignrb:
2987   di_SInst_didiqi                 <"valignb", int_hexagon_S2_valignrb>;
2988
2989 // STYPE / PERM / Vector round and pack.
2990 def HEXAGON_S2_vrndpackwh:
2991   si_SInst_di                     <"vrndwh",  int_hexagon_S2_vrndpackwh>;
2992 def HEXAGON_S2_vrndpackwhs:
2993   si_SInst_di_sat                 <"vrndwh",  int_hexagon_S2_vrndpackwhs>;
2994
2995 // STYPE / PERM / Vector saturate and pack.
2996 def HEXAGON_S2_svsathb:
2997   si_SInst_si                     <"vsathb",  int_hexagon_S2_svsathb>;
2998 def HEXAGON_S2_vsathb:
2999   si_SInst_di                     <"vsathb",  int_hexagon_S2_vsathb>;
3000 def HEXAGON_S2_svsathub:
3001   si_SInst_si                     <"vsathub", int_hexagon_S2_svsathub>;
3002 def HEXAGON_S2_vsathub:
3003   si_SInst_di                     <"vsathub", int_hexagon_S2_vsathub>;
3004 def HEXAGON_S2_vsatwh:
3005   si_SInst_di                     <"vsatwh",  int_hexagon_S2_vsatwh>;
3006 def HEXAGON_S2_vsatwuh:
3007   si_SInst_di                     <"vsatwuh", int_hexagon_S2_vsatwuh>;
3008
3009 // STYPE / PERM / Vector saturate without pack.
3010 def HEXAGON_S2_vsathb_nopack:
3011   di_SInst_di                     <"vsathb",  int_hexagon_S2_vsathb_nopack>;
3012 def HEXAGON_S2_vsathub_nopack:
3013   di_SInst_di                     <"vsathub", int_hexagon_S2_vsathub_nopack>;
3014 def HEXAGON_S2_vsatwh_nopack:
3015   di_SInst_di                     <"vsatwh",  int_hexagon_S2_vsatwh_nopack>;
3016 def HEXAGON_S2_vsatwuh_nopack:
3017   di_SInst_di                     <"vsatwuh", int_hexagon_S2_vsatwuh_nopack>;
3018
3019 // STYPE / PERM / Vector shuffle.
3020 def HEXAGON_S2_shuffeb:
3021   di_SInst_didi                   <"shuffeb", int_hexagon_S2_shuffeb>;
3022 def HEXAGON_S2_shuffeh:
3023   di_SInst_didi                   <"shuffeh", int_hexagon_S2_shuffeh>;
3024 def HEXAGON_S2_shuffob:
3025   di_SInst_didi                   <"shuffob", int_hexagon_S2_shuffob>;
3026 def HEXAGON_S2_shuffoh:
3027   di_SInst_didi                   <"shuffoh", int_hexagon_S2_shuffoh>;
3028
3029 // STYPE / PERM / Vector splat bytes.
3030 def HEXAGON_S2_vsplatrb:
3031   si_SInst_si                     <"vsplatb", int_hexagon_S2_vsplatrb>;
3032
3033 // STYPE / PERM / Vector splat halfwords.
3034 def HEXAGON_S2_vsplatrh:
3035   di_SInst_si                     <"vsplath", int_hexagon_S2_vsplatrh>;
3036
3037 // STYPE / PERM / Vector splice.
3038 def Hexagon_S2_vsplicerb:
3039   di_SInst_didiqi                 <"vspliceb",int_hexagon_S2_vsplicerb>;
3040 def Hexagon_S2_vspliceib:
3041   di_SInst_didiu3                 <"vspliceb",int_hexagon_S2_vspliceib>;
3042
3043 // STYPE / PERM / Sign extend.
3044 def HEXAGON_S2_vsxtbh:
3045   di_SInst_si                     <"vsxtbh",  int_hexagon_S2_vsxtbh>;
3046 def HEXAGON_S2_vsxthw:
3047   di_SInst_si                     <"vsxthw",  int_hexagon_S2_vsxthw>;
3048
3049 // STYPE / PERM / Truncate.
3050 def HEXAGON_S2_vtrunehb:
3051   si_SInst_di                     <"vtrunehb",int_hexagon_S2_vtrunehb>;
3052 def HEXAGON_S2_vtrunohb:
3053   si_SInst_di                     <"vtrunohb",int_hexagon_S2_vtrunohb>;
3054 def HEXAGON_S2_vtrunewh:
3055   di_SInst_didi                   <"vtrunewh",int_hexagon_S2_vtrunewh>;
3056 def HEXAGON_S2_vtrunowh:
3057   di_SInst_didi                   <"vtrunowh",int_hexagon_S2_vtrunowh>;
3058
3059 // STYPE / PERM / Zero extend.
3060 def HEXAGON_S2_vzxtbh:
3061   di_SInst_si                     <"vzxtbh",  int_hexagon_S2_vzxtbh>;
3062 def HEXAGON_S2_vzxthw:
3063   di_SInst_si                     <"vzxthw",  int_hexagon_S2_vzxthw>;
3064
3065
3066 /********************************************************************
3067 *            STYPE/PRED                                             *
3068 *********************************************************************/
3069
3070 // STYPE / PRED / Mask generate from predicate.
3071 def HEXAGON_C2_mask:
3072   di_SInst_qi                     <"mask",   int_hexagon_C2_mask>;
3073
3074 // STYPE / PRED / Predicate transfer.
3075 def HEXAGON_C2_tfrpr:
3076   si_SInst_qi                     <"",       int_hexagon_C2_tfrpr>;
3077 def HEXAGON_C2_tfrrp:
3078   qi_SInst_si                     <"",       int_hexagon_C2_tfrrp>;
3079
3080 // STYPE / PRED / Viterbi pack even and odd predicate bits.
3081 def HEXAGON_C2_vitpack:
3082   si_SInst_qiqi                   <"vitpack",int_hexagon_C2_vitpack>;
3083
3084
3085 /********************************************************************
3086 *            STYPE/SHIFT                                            *
3087 *********************************************************************/
3088
3089 // STYPE / SHIFT / Shift by immediate.
3090 def HEXAGON_S2_asl_i_r:
3091   si_SInst_siu5                   <"asl",     int_hexagon_S2_asl_i_r>;
3092 def HEXAGON_S2_asr_i_r:
3093   si_SInst_siu5                   <"asr",     int_hexagon_S2_asr_i_r>;
3094 def HEXAGON_S2_lsr_i_r:
3095   si_SInst_siu5                   <"lsr",     int_hexagon_S2_lsr_i_r>;
3096 def HEXAGON_S2_asl_i_p:
3097   di_SInst_diu6                   <"asl",     int_hexagon_S2_asl_i_p>;
3098 def HEXAGON_S2_asr_i_p:
3099   di_SInst_diu6                   <"asr",     int_hexagon_S2_asr_i_p>;
3100 def HEXAGON_S2_lsr_i_p:
3101   di_SInst_diu6                   <"lsr",     int_hexagon_S2_lsr_i_p>;
3102
3103 // STYPE / SHIFT / Shift by immediate and accumulate.
3104 def HEXAGON_S2_asl_i_r_acc:
3105   si_SInst_sisiu5_acc             <"asl",     int_hexagon_S2_asl_i_r_acc>;
3106 def HEXAGON_S2_asr_i_r_acc:
3107   si_SInst_sisiu5_acc             <"asr",     int_hexagon_S2_asr_i_r_acc>;
3108 def HEXAGON_S2_lsr_i_r_acc:
3109   si_SInst_sisiu5_acc             <"lsr",     int_hexagon_S2_lsr_i_r_acc>;
3110 def HEXAGON_S2_asl_i_r_nac:
3111   si_SInst_sisiu5_nac             <"asl",     int_hexagon_S2_asl_i_r_nac>;
3112 def HEXAGON_S2_asr_i_r_nac:
3113   si_SInst_sisiu5_nac             <"asr",     int_hexagon_S2_asr_i_r_nac>;
3114 def HEXAGON_S2_lsr_i_r_nac:
3115   si_SInst_sisiu5_nac             <"lsr",     int_hexagon_S2_lsr_i_r_nac>;
3116 def HEXAGON_S2_asl_i_p_acc:
3117   di_SInst_didiu6_acc             <"asl",     int_hexagon_S2_asl_i_p_acc>;
3118 def HEXAGON_S2_asr_i_p_acc:
3119   di_SInst_didiu6_acc             <"asr",     int_hexagon_S2_asr_i_p_acc>;
3120 def HEXAGON_S2_lsr_i_p_acc:
3121   di_SInst_didiu6_acc             <"lsr",     int_hexagon_S2_lsr_i_p_acc>;
3122 def HEXAGON_S2_asl_i_p_nac:
3123   di_SInst_didiu6_nac             <"asl",     int_hexagon_S2_asl_i_p_nac>;
3124 def HEXAGON_S2_asr_i_p_nac:
3125   di_SInst_didiu6_nac             <"asr",     int_hexagon_S2_asr_i_p_nac>;
3126 def HEXAGON_S2_lsr_i_p_nac:
3127   di_SInst_didiu6_nac             <"lsr",     int_hexagon_S2_lsr_i_p_nac>;
3128
3129 // STYPE / SHIFT / Shift by immediate and add.
3130 def HEXAGON_S2_addasl_rrri:
3131   si_SInst_sisiu3                 <"addasl",  int_hexagon_S2_addasl_rrri>;
3132
3133 // STYPE / SHIFT / Shift by immediate and logical.
3134 def HEXAGON_S2_asl_i_r_and:
3135   si_SInst_sisiu5_and             <"asl",     int_hexagon_S2_asl_i_r_and>;
3136 def HEXAGON_S2_asr_i_r_and:
3137   si_SInst_sisiu5_and             <"asr",     int_hexagon_S2_asr_i_r_and>;
3138 def HEXAGON_S2_lsr_i_r_and:
3139   si_SInst_sisiu5_and             <"lsr",     int_hexagon_S2_lsr_i_r_and>;
3140
3141 def HEXAGON_S2_asl_i_r_xacc:
3142   si_SInst_sisiu5_xor             <"asl",     int_hexagon_S2_asl_i_r_xacc>;
3143 def HEXAGON_S2_lsr_i_r_xacc:
3144   si_SInst_sisiu5_xor             <"lsr",     int_hexagon_S2_lsr_i_r_xacc>;
3145
3146 def HEXAGON_S2_asl_i_r_or:
3147   si_SInst_sisiu5_or              <"asl",     int_hexagon_S2_asl_i_r_or>;
3148 def HEXAGON_S2_asr_i_r_or:
3149   si_SInst_sisiu5_or              <"asr",     int_hexagon_S2_asr_i_r_or>;
3150 def HEXAGON_S2_lsr_i_r_or:
3151   si_SInst_sisiu5_or              <"lsr",     int_hexagon_S2_lsr_i_r_or>;
3152
3153 def HEXAGON_S2_asl_i_p_and:
3154   di_SInst_didiu6_and             <"asl",     int_hexagon_S2_asl_i_p_and>;
3155 def HEXAGON_S2_asr_i_p_and:
3156   di_SInst_didiu6_and             <"asr",     int_hexagon_S2_asr_i_p_and>;
3157 def HEXAGON_S2_lsr_i_p_and:
3158   di_SInst_didiu6_and             <"lsr",     int_hexagon_S2_lsr_i_p_and>;
3159
3160 def HEXAGON_S2_asl_i_p_xacc:
3161   di_SInst_didiu6_xor             <"asl",     int_hexagon_S2_asl_i_p_xacc>;
3162 def HEXAGON_S2_lsr_i_p_xacc:
3163   di_SInst_didiu6_xor             <"lsr",     int_hexagon_S2_lsr_i_p_xacc>;
3164
3165 def HEXAGON_S2_asl_i_p_or:
3166   di_SInst_didiu6_or              <"asl",     int_hexagon_S2_asl_i_p_or>;
3167 def HEXAGON_S2_asr_i_p_or:
3168   di_SInst_didiu6_or              <"asr",     int_hexagon_S2_asr_i_p_or>;
3169 def HEXAGON_S2_lsr_i_p_or:
3170   di_SInst_didiu6_or              <"lsr",     int_hexagon_S2_lsr_i_p_or>;
3171
3172 // STYPE / SHIFT / Shift right by immediate with rounding.
3173 def HEXAGON_S2_asr_i_r_rnd:
3174   si_SInst_siu5_rnd               <"asr",     int_hexagon_S2_asr_i_r_rnd>;
3175 def HEXAGON_S2_asr_i_r_rnd_goodsyntax:
3176   si_SInst_siu5              <"asrrnd",  int_hexagon_S2_asr_i_r_rnd_goodsyntax>;
3177
3178 // STYPE / SHIFT / Shift left by immediate with saturation.
3179 def HEXAGON_S2_asl_i_r_sat:
3180   si_SInst_sisi_sat               <"asl",     int_hexagon_S2_asl_i_r_sat>;
3181
3182 // STYPE / SHIFT / Shift by register.
3183 def HEXAGON_S2_asl_r_r:
3184   si_SInst_sisi                   <"asl",     int_hexagon_S2_asl_r_r>;
3185 def HEXAGON_S2_asr_r_r:
3186   si_SInst_sisi                   <"asr",     int_hexagon_S2_asr_r_r>;
3187 def HEXAGON_S2_lsl_r_r:
3188   si_SInst_sisi                   <"lsl",     int_hexagon_S2_lsl_r_r>;
3189 def HEXAGON_S2_lsr_r_r:
3190   si_SInst_sisi                   <"lsr",     int_hexagon_S2_lsr_r_r>;
3191 def HEXAGON_S2_asl_r_p:
3192   di_SInst_disi                   <"asl",     int_hexagon_S2_asl_r_p>;
3193 def HEXAGON_S2_asr_r_p:
3194   di_SInst_disi                   <"asr",     int_hexagon_S2_asr_r_p>;
3195 def HEXAGON_S2_lsl_r_p:
3196   di_SInst_disi                   <"lsl",     int_hexagon_S2_lsl_r_p>;
3197 def HEXAGON_S2_lsr_r_p:
3198   di_SInst_disi                   <"lsr",     int_hexagon_S2_lsr_r_p>;
3199
3200 // STYPE / SHIFT / Shift by register and accumulate.
3201 def HEXAGON_S2_asl_r_r_acc:
3202   si_SInst_sisisi_acc             <"asl",     int_hexagon_S2_asl_r_r_acc>;
3203 def HEXAGON_S2_asr_r_r_acc:
3204   si_SInst_sisisi_acc             <"asr",     int_hexagon_S2_asr_r_r_acc>;
3205 def HEXAGON_S2_lsl_r_r_acc:
3206   si_SInst_sisisi_acc             <"lsl",     int_hexagon_S2_lsl_r_r_acc>;
3207 def HEXAGON_S2_lsr_r_r_acc:
3208   si_SInst_sisisi_acc             <"lsr",     int_hexagon_S2_lsr_r_r_acc>;
3209 def HEXAGON_S2_asl_r_p_acc:
3210   di_SInst_didisi_acc             <"asl",     int_hexagon_S2_asl_r_p_acc>;
3211 def HEXAGON_S2_asr_r_p_acc:
3212   di_SInst_didisi_acc             <"asr",     int_hexagon_S2_asr_r_p_acc>;
3213 def HEXAGON_S2_lsl_r_p_acc:
3214   di_SInst_didisi_acc             <"lsl",     int_hexagon_S2_lsl_r_p_acc>;
3215 def HEXAGON_S2_lsr_r_p_acc:
3216   di_SInst_didisi_acc             <"lsr",     int_hexagon_S2_lsr_r_p_acc>;
3217
3218 def HEXAGON_S2_asl_r_r_nac:
3219   si_SInst_sisisi_nac             <"asl",     int_hexagon_S2_asl_r_r_nac>;
3220 def HEXAGON_S2_asr_r_r_nac:
3221   si_SInst_sisisi_nac             <"asr",     int_hexagon_S2_asr_r_r_nac>;
3222 def HEXAGON_S2_lsl_r_r_nac:
3223   si_SInst_sisisi_nac             <"lsl",     int_hexagon_S2_lsl_r_r_nac>;
3224 def HEXAGON_S2_lsr_r_r_nac:
3225   si_SInst_sisisi_nac             <"lsr",     int_hexagon_S2_lsr_r_r_nac>;
3226 def HEXAGON_S2_asl_r_p_nac:
3227   di_SInst_didisi_nac             <"asl",     int_hexagon_S2_asl_r_p_nac>;
3228 def HEXAGON_S2_asr_r_p_nac:
3229   di_SInst_didisi_nac             <"asr",     int_hexagon_S2_asr_r_p_nac>;
3230 def HEXAGON_S2_lsl_r_p_nac:
3231   di_SInst_didisi_nac             <"lsl",     int_hexagon_S2_lsl_r_p_nac>;
3232 def HEXAGON_S2_lsr_r_p_nac:
3233   di_SInst_didisi_nac             <"lsr",     int_hexagon_S2_lsr_r_p_nac>;
3234
3235 // STYPE / SHIFT / Shift by register and logical.
3236 def HEXAGON_S2_asl_r_r_and:
3237   si_SInst_sisisi_and             <"asl",     int_hexagon_S2_asl_r_r_and>;
3238 def HEXAGON_S2_asr_r_r_and:
3239   si_SInst_sisisi_and             <"asr",     int_hexagon_S2_asr_r_r_and>;
3240 def HEXAGON_S2_lsl_r_r_and:
3241   si_SInst_sisisi_and             <"lsl",     int_hexagon_S2_lsl_r_r_and>;
3242 def HEXAGON_S2_lsr_r_r_and:
3243   si_SInst_sisisi_and             <"lsr",     int_hexagon_S2_lsr_r_r_and>;
3244
3245 def HEXAGON_S2_asl_r_r_or:
3246   si_SInst_sisisi_or              <"asl",     int_hexagon_S2_asl_r_r_or>;
3247 def HEXAGON_S2_asr_r_r_or:
3248   si_SInst_sisisi_or              <"asr",     int_hexagon_S2_asr_r_r_or>;
3249 def HEXAGON_S2_lsl_r_r_or:
3250   si_SInst_sisisi_or              <"lsl",     int_hexagon_S2_lsl_r_r_or>;
3251 def HEXAGON_S2_lsr_r_r_or:
3252   si_SInst_sisisi_or              <"lsr",     int_hexagon_S2_lsr_r_r_or>;
3253
3254 def HEXAGON_S2_asl_r_p_and:
3255   di_SInst_didisi_and             <"asl",     int_hexagon_S2_asl_r_p_and>;
3256 def HEXAGON_S2_asr_r_p_and:
3257   di_SInst_didisi_and             <"asr",     int_hexagon_S2_asr_r_p_and>;
3258 def HEXAGON_S2_lsl_r_p_and:
3259   di_SInst_didisi_and             <"lsl",     int_hexagon_S2_lsl_r_p_and>;
3260 def HEXAGON_S2_lsr_r_p_and:
3261   di_SInst_didisi_and             <"lsr",     int_hexagon_S2_lsr_r_p_and>;
3262
3263 def HEXAGON_S2_asl_r_p_or:
3264   di_SInst_didisi_or              <"asl",     int_hexagon_S2_asl_r_p_or>;
3265 def HEXAGON_S2_asr_r_p_or:
3266   di_SInst_didisi_or              <"asr",     int_hexagon_S2_asr_r_p_or>;
3267 def HEXAGON_S2_lsl_r_p_or:
3268   di_SInst_didisi_or              <"lsl",     int_hexagon_S2_lsl_r_p_or>;
3269 def HEXAGON_S2_lsr_r_p_or:
3270   di_SInst_didisi_or              <"lsr",     int_hexagon_S2_lsr_r_p_or>;
3271
3272 // STYPE / SHIFT / Shift by register with saturation.
3273 def HEXAGON_S2_asl_r_r_sat:
3274   si_SInst_sisi_sat               <"asl",     int_hexagon_S2_asl_r_r_sat>;
3275 def HEXAGON_S2_asr_r_r_sat:
3276   si_SInst_sisi_sat               <"asr",     int_hexagon_S2_asr_r_r_sat>;
3277
3278 // STYPE / SHIFT / Table Index.
3279 def Hexagon_S2_tableidxb_goodsyntax:
3280   si_MInst_sisiu4u5          <"tableidxb",int_hexagon_S2_tableidxb_goodsyntax>;
3281 def Hexagon_S2_tableidxd_goodsyntax:
3282   si_MInst_sisiu4u5          <"tableidxd",int_hexagon_S2_tableidxd_goodsyntax>;
3283 def Hexagon_S2_tableidxh_goodsyntax:
3284   si_MInst_sisiu4u5          <"tableidxh",int_hexagon_S2_tableidxh_goodsyntax>;
3285 def Hexagon_S2_tableidxw_goodsyntax:
3286   si_MInst_sisiu4u5          <"tableidxw",int_hexagon_S2_tableidxw_goodsyntax>;
3287
3288
3289 /********************************************************************
3290 *            STYPE/VH                                               *
3291 *********************************************************************/
3292
3293 // STYPE / VH / Vector absolute value halfwords.
3294 // Rdd64=vabsh(Rss64)
3295 def HEXAGON_A2_vabsh:
3296   di_SInst_di                     <"vabsh",   int_hexagon_A2_vabsh>;
3297 def HEXAGON_A2_vabshsat:
3298   di_SInst_di_sat                 <"vabsh",   int_hexagon_A2_vabshsat>;
3299
3300 // STYPE / VH / Vector shift halfwords by immediate.
3301 // Rdd64=v[asl/asr/lsr]h(Rss64,Rt32)
3302 def HEXAGON_S2_asl_i_vh:
3303   di_SInst_disi                   <"vaslh",   int_hexagon_S2_asl_i_vh>;
3304 def HEXAGON_S2_asr_i_vh:
3305   di_SInst_disi                   <"vasrh",   int_hexagon_S2_asr_i_vh>;
3306 def HEXAGON_S2_lsr_i_vh:
3307   di_SInst_disi                   <"vlsrh",   int_hexagon_S2_lsr_i_vh>;
3308
3309 // STYPE / VH / Vector shift halfwords by register.
3310 // Rdd64=v[asl/asr/lsl/lsr]w(Rss64,Rt32)
3311 def HEXAGON_S2_asl_r_vh:
3312   di_SInst_disi                   <"vaslh",   int_hexagon_S2_asl_r_vh>;
3313 def HEXAGON_S2_asr_r_vh:
3314   di_SInst_disi                   <"vasrh",   int_hexagon_S2_asr_r_vh>;
3315 def HEXAGON_S2_lsl_r_vh:
3316   di_SInst_disi                   <"vlslh",   int_hexagon_S2_lsl_r_vh>;
3317 def HEXAGON_S2_lsr_r_vh:
3318   di_SInst_disi                   <"vlsrh",   int_hexagon_S2_lsr_r_vh>;
3319
3320
3321 /********************************************************************
3322 *            STYPE/VW                                               *
3323 *********************************************************************/
3324
3325 // STYPE / VW / Vector absolute value words.
3326 def HEXAGON_A2_vabsw:
3327   di_SInst_di                     <"vabsw",   int_hexagon_A2_vabsw>;
3328 def HEXAGON_A2_vabswsat:
3329   di_SInst_di_sat                 <"vabsw",   int_hexagon_A2_vabswsat>;
3330
3331 // STYPE / VW / Vector shift words by immediate.
3332 // Rdd64=v[asl/vsl]w(Rss64,Rt32)
3333 def HEXAGON_S2_asl_i_vw:
3334   di_SInst_disi                   <"vaslw",   int_hexagon_S2_asl_i_vw>;
3335 def HEXAGON_S2_asr_i_vw:
3336   di_SInst_disi                   <"vasrw",   int_hexagon_S2_asr_i_vw>;
3337 def HEXAGON_S2_lsr_i_vw:
3338   di_SInst_disi                   <"vlsrw",   int_hexagon_S2_lsr_i_vw>;
3339
3340 // STYPE / VW / Vector shift words by register.
3341 // Rdd64=v[asl/vsl]w(Rss64,Rt32)
3342 def HEXAGON_S2_asl_r_vw:
3343   di_SInst_disi                   <"vaslw",   int_hexagon_S2_asl_r_vw>;
3344 def HEXAGON_S2_asr_r_vw:
3345   di_SInst_disi                   <"vasrw",   int_hexagon_S2_asr_r_vw>;
3346 def HEXAGON_S2_lsl_r_vw:
3347   di_SInst_disi                   <"vlslw",   int_hexagon_S2_lsl_r_vw>;
3348 def HEXAGON_S2_lsr_r_vw:
3349   di_SInst_disi                   <"vlsrw",   int_hexagon_S2_lsr_r_vw>;
3350
3351 // STYPE / VW / Vector shift words with truncate and pack.
3352 def HEXAGON_S2_asr_r_svw_trun:
3353   si_SInst_disi                   <"vasrw",   int_hexagon_S2_asr_r_svw_trun>;
3354 def HEXAGON_S2_asr_i_svw_trun:
3355   si_SInst_diu5                   <"vasrw",   int_hexagon_S2_asr_i_svw_trun>;
3356
3357 // LD / Circular loads.
3358 def HEXAGON_circ_ldd:
3359   di_LDInstPI_diu4                <"circ_ldd", int_hexagon_circ_ldd>;
3360
3361 include "HexagonIntrinsicsV3.td"
3362 include "HexagonIntrinsicsV4.td"
3363 include "HexagonIntrinsicsV5.td"