lib/Target/Hexagon/HexagonIntrinsics.td

   1 //===-- HexagonIntrinsics.td - Instruction intrinsics ------*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 // This is populated based on the following specs:
  10 // Hexagon V2 Architecture
  11 // Application-Level Specification
  12 // 80-V9418-8 Rev. B
  13 // March 4, 2008
  14 //===----------------------------------------------------------------------===//
  15
  16 class T_I_pat <InstHexagon MI, Intrinsic IntID>
  17   : Pat <(IntID imm:$Is),
  18          (MI imm:$Is)>;
  19
  20 class T_R_pat <InstHexagon MI, Intrinsic IntID>
  21   : Pat <(IntID I32:$Rs),
  22          (MI I32:$Rs)>;
  23
  24 class T_II_pat <InstHexagon MI, Intrinsic IntID, PatFrag Imm1, PatFrag Imm2>
  25   : Pat<(IntID Imm1:$Is, Imm2:$It),
  26         (MI Imm1:$Is, Imm2:$It)>;
  27
  28 class T_RI_pat <InstHexagon MI, Intrinsic IntID, PatLeaf ImmPred = PatLeaf<(i32 imm)>>
  29   : Pat<(IntID I32:$Rs, ImmPred:$It),
  30         (MI I32:$Rs, ImmPred:$It)>;
  31
  32 class T_IR_pat <InstHexagon MI, Intrinsic IntID, PatFrag ImmPred = PatLeaf<(i32 imm)>>
  33   : Pat<(IntID ImmPred:$Is, I32:$Rt),
  34         (MI ImmPred:$Is, I32:$Rt)>;
  35
  36 class T_RR_pat <InstHexagon MI, Intrinsic IntID>
  37   : Pat <(IntID I32:$Rs, I32:$Rt),
  38          (MI I32:$Rs, I32:$Rt)>;
  39
  40 class T_PP_pat <InstHexagon MI, Intrinsic IntID>
  41   : Pat <(IntID I64:$Rs, I64:$Rt),
  42          (MI DoubleRegs:$Rs, DoubleRegs:$Rt)>;
  43
  44 class T_QII_pat <InstHexagon MI, Intrinsic IntID, PatFrag Imm1, PatFrag Imm2>
  45   : Pat <(IntID (i32 PredRegs:$Ps), Imm1:$Is, Imm2:$It),
  46          (MI PredRegs:$Ps, Imm1:$Is, Imm2:$It)>;
  47
  48 class T_QRI_pat <InstHexagon MI, Intrinsic IntID, PatFrag ImmPred>
  49   : Pat <(IntID (i32 PredRegs:$Ps), I32:$Rs, ImmPred:$Is),
  50          (MI PredRegs:$Ps, I32:$Rs, ImmPred:$Is)>;
  51
  52 class T_QIR_pat <InstHexagon MI, Intrinsic IntID, PatFrag ImmPred>
  53   : Pat <(IntID (i32 PredRegs:$Ps), ImmPred:$Is, I32:$Rs),
  54          (MI PredRegs:$Ps, ImmPred:$Is, I32:$Rs)>;
  55
  56 class T_RRI_pat <InstHexagon MI, Intrinsic IntID>
  57   : Pat <(IntID I32:$Rs, I32:$Rt, imm:$Iu),
  58          (MI I32:$Rs, I32:$Rt, imm:$Iu)>;
  59
  60 class T_RRR_pat <InstHexagon MI, Intrinsic IntID>
  61   : Pat <(IntID I32:$Rs, I32:$Rt, I32:$Ru),
  62          (MI I32:$Rs, I32:$Rt, I32:$Ru)>;
  63
  64 class T_PRR_pat <InstHexagon MI, Intrinsic IntID>
  65   : Pat <(IntID I64:$Rs, I32:$Rt, I32:$Ru),
  66          (MI DoubleRegs:$Rs, I32:$Rt, I32:$Ru)>;
  67
  68 //===----------------------------------------------------------------------===//
  69 // MPYS / Multipy signed/unsigned halfwords
  70 //Rd=mpy[u](Rs.[H|L],Rt.[H|L])[:<<1][:rnd][:sat]
  71 //===----------------------------------------------------------------------===//
  72
  73 def : T_RR_pat <M2_mpy_ll_s1, int_hexagon_M2_mpy_ll_s1>;
  74 def : T_RR_pat <M2_mpy_ll_s0, int_hexagon_M2_mpy_ll_s0>;
  75 def : T_RR_pat <M2_mpy_lh_s1, int_hexagon_M2_mpy_lh_s1>;
  76 def : T_RR_pat <M2_mpy_lh_s0, int_hexagon_M2_mpy_lh_s0>;
  77 def : T_RR_pat <M2_mpy_hl_s1, int_hexagon_M2_mpy_hl_s1>;
  78 def : T_RR_pat <M2_mpy_hl_s0, int_hexagon_M2_mpy_hl_s0>;
  79 def : T_RR_pat <M2_mpy_hh_s1, int_hexagon_M2_mpy_hh_s1>;
  80 def : T_RR_pat <M2_mpy_hh_s0, int_hexagon_M2_mpy_hh_s0>;
  81
  82 def : T_RR_pat <M2_mpyu_ll_s1, int_hexagon_M2_mpyu_ll_s1>;
  83 def : T_RR_pat <M2_mpyu_ll_s0, int_hexagon_M2_mpyu_ll_s0>;
  84 def : T_RR_pat <M2_mpyu_lh_s1, int_hexagon_M2_mpyu_lh_s1>;
  85 def : T_RR_pat <M2_mpyu_lh_s0, int_hexagon_M2_mpyu_lh_s0>;
  86 def : T_RR_pat <M2_mpyu_hl_s1, int_hexagon_M2_mpyu_hl_s1>;
  87 def : T_RR_pat <M2_mpyu_hl_s0, int_hexagon_M2_mpyu_hl_s0>;
  88 def : T_RR_pat <M2_mpyu_hh_s1, int_hexagon_M2_mpyu_hh_s1>;
  89 def : T_RR_pat <M2_mpyu_hh_s0, int_hexagon_M2_mpyu_hh_s0>;
  90
  91 def : T_RR_pat <M2_mpy_sat_ll_s1, int_hexagon_M2_mpy_sat_ll_s1>;
  92 def : T_RR_pat <M2_mpy_sat_ll_s0, int_hexagon_M2_mpy_sat_ll_s0>;
  93 def : T_RR_pat <M2_mpy_sat_lh_s1, int_hexagon_M2_mpy_sat_lh_s1>;
  94 def : T_RR_pat <M2_mpy_sat_lh_s0, int_hexagon_M2_mpy_sat_lh_s0>;
  95 def : T_RR_pat <M2_mpy_sat_hl_s1, int_hexagon_M2_mpy_sat_hl_s1>;
  96 def : T_RR_pat <M2_mpy_sat_hl_s0, int_hexagon_M2_mpy_sat_hl_s0>;
  97 def : T_RR_pat <M2_mpy_sat_hh_s1, int_hexagon_M2_mpy_sat_hh_s1>;
  98 def : T_RR_pat <M2_mpy_sat_hh_s0, int_hexagon_M2_mpy_sat_hh_s0>;
  99
 100 def : T_RR_pat <M2_mpy_rnd_ll_s1, int_hexagon_M2_mpy_rnd_ll_s1>;
 101 def : T_RR_pat <M2_mpy_rnd_ll_s0, int_hexagon_M2_mpy_rnd_ll_s0>;
 102 def : T_RR_pat <M2_mpy_rnd_lh_s1, int_hexagon_M2_mpy_rnd_lh_s1>;
 103 def : T_RR_pat <M2_mpy_rnd_lh_s0, int_hexagon_M2_mpy_rnd_lh_s0>;
 104 def : T_RR_pat <M2_mpy_rnd_hl_s1, int_hexagon_M2_mpy_rnd_hl_s1>;
 105 def : T_RR_pat <M2_mpy_rnd_hl_s0, int_hexagon_M2_mpy_rnd_hl_s0>;
 106 def : T_RR_pat <M2_mpy_rnd_hh_s1, int_hexagon_M2_mpy_rnd_hh_s1>;
 107 def : T_RR_pat <M2_mpy_rnd_hh_s0, int_hexagon_M2_mpy_rnd_hh_s0>;
 108
 109 def : T_RR_pat <M2_mpy_sat_rnd_ll_s1, int_hexagon_M2_mpy_sat_rnd_ll_s1>;
 110 def : T_RR_pat <M2_mpy_sat_rnd_ll_s0, int_hexagon_M2_mpy_sat_rnd_ll_s0>;
 111 def : T_RR_pat <M2_mpy_sat_rnd_lh_s1, int_hexagon_M2_mpy_sat_rnd_lh_s1>;
 112 def : T_RR_pat <M2_mpy_sat_rnd_lh_s0, int_hexagon_M2_mpy_sat_rnd_lh_s0>;
 113 def : T_RR_pat <M2_mpy_sat_rnd_hl_s1, int_hexagon_M2_mpy_sat_rnd_hl_s1>;
 114 def : T_RR_pat <M2_mpy_sat_rnd_hl_s0, int_hexagon_M2_mpy_sat_rnd_hl_s0>;
 115 def : T_RR_pat <M2_mpy_sat_rnd_hh_s1, int_hexagon_M2_mpy_sat_rnd_hh_s1>;
 116 def : T_RR_pat <M2_mpy_sat_rnd_hh_s0, int_hexagon_M2_mpy_sat_rnd_hh_s0>;
 117
 118
 119 //===----------------------------------------------------------------------===//
 120 // MPYS / Multipy signed/unsigned halfwords and add/subtract the
 121 // result from the accumulator.
 122 //Rx [-+]= mpy[u](Rs.[H|L],Rt.[H|L])[:<<1][:sat]
 123 //===----------------------------------------------------------------------===//
 124
 125 def : T_RRR_pat <M2_mpy_acc_ll_s1, int_hexagon_M2_mpy_acc_ll_s1>;
 126 def : T_RRR_pat <M2_mpy_acc_ll_s0, int_hexagon_M2_mpy_acc_ll_s0>;
 127 def : T_RRR_pat <M2_mpy_acc_lh_s1, int_hexagon_M2_mpy_acc_lh_s1>;
 128 def : T_RRR_pat <M2_mpy_acc_lh_s0, int_hexagon_M2_mpy_acc_lh_s0>;
 129 def : T_RRR_pat <M2_mpy_acc_hl_s1, int_hexagon_M2_mpy_acc_hl_s1>;
 130 def : T_RRR_pat <M2_mpy_acc_hl_s0, int_hexagon_M2_mpy_acc_hl_s0>;
 131 def : T_RRR_pat <M2_mpy_acc_hh_s1, int_hexagon_M2_mpy_acc_hh_s1>;
 132 def : T_RRR_pat <M2_mpy_acc_hh_s0, int_hexagon_M2_mpy_acc_hh_s0>;
 133
 134 def : T_RRR_pat <M2_mpyu_acc_ll_s1, int_hexagon_M2_mpyu_acc_ll_s1>;
 135 def : T_RRR_pat <M2_mpyu_acc_ll_s0, int_hexagon_M2_mpyu_acc_ll_s0>;
 136 def : T_RRR_pat <M2_mpyu_acc_lh_s1, int_hexagon_M2_mpyu_acc_lh_s1>;
 137 def : T_RRR_pat <M2_mpyu_acc_lh_s0, int_hexagon_M2_mpyu_acc_lh_s0>;
 138 def : T_RRR_pat <M2_mpyu_acc_hl_s1, int_hexagon_M2_mpyu_acc_hl_s1>;
 139 def : T_RRR_pat <M2_mpyu_acc_hl_s0, int_hexagon_M2_mpyu_acc_hl_s0>;
 140 def : T_RRR_pat <M2_mpyu_acc_hh_s1, int_hexagon_M2_mpyu_acc_hh_s1>;
 141 def : T_RRR_pat <M2_mpyu_acc_hh_s0, int_hexagon_M2_mpyu_acc_hh_s0>;
 142
 143 def : T_RRR_pat <M2_mpy_nac_ll_s1, int_hexagon_M2_mpy_nac_ll_s1>;
 144 def : T_RRR_pat <M2_mpy_nac_ll_s0, int_hexagon_M2_mpy_nac_ll_s0>;
 145 def : T_RRR_pat <M2_mpy_nac_lh_s1, int_hexagon_M2_mpy_nac_lh_s1>;
 146 def : T_RRR_pat <M2_mpy_nac_lh_s0, int_hexagon_M2_mpy_nac_lh_s0>;
 147 def : T_RRR_pat <M2_mpy_nac_hl_s1, int_hexagon_M2_mpy_nac_hl_s1>;
 148 def : T_RRR_pat <M2_mpy_nac_hl_s0, int_hexagon_M2_mpy_nac_hl_s0>;
 149 def : T_RRR_pat <M2_mpy_nac_hh_s1, int_hexagon_M2_mpy_nac_hh_s1>;
 150 def : T_RRR_pat <M2_mpy_nac_hh_s0, int_hexagon_M2_mpy_nac_hh_s0>;
 151
 152 def : T_RRR_pat <M2_mpyu_nac_ll_s1, int_hexagon_M2_mpyu_nac_ll_s1>;
 153 def : T_RRR_pat <M2_mpyu_nac_ll_s0, int_hexagon_M2_mpyu_nac_ll_s0>;
 154 def : T_RRR_pat <M2_mpyu_nac_lh_s1, int_hexagon_M2_mpyu_nac_lh_s1>;
 155 def : T_RRR_pat <M2_mpyu_nac_lh_s0, int_hexagon_M2_mpyu_nac_lh_s0>;
 156 def : T_RRR_pat <M2_mpyu_nac_hl_s1, int_hexagon_M2_mpyu_nac_hl_s1>;
 157 def : T_RRR_pat <M2_mpyu_nac_hl_s0, int_hexagon_M2_mpyu_nac_hl_s0>;
 158 def : T_RRR_pat <M2_mpyu_nac_hh_s1, int_hexagon_M2_mpyu_nac_hh_s1>;
 159 def : T_RRR_pat <M2_mpyu_nac_hh_s0, int_hexagon_M2_mpyu_nac_hh_s0>;
 160
 161 def : T_RRR_pat <M2_mpy_acc_sat_ll_s1, int_hexagon_M2_mpy_acc_sat_ll_s1>;
 162 def : T_RRR_pat <M2_mpy_acc_sat_ll_s0, int_hexagon_M2_mpy_acc_sat_ll_s0>;
 163 def : T_RRR_pat <M2_mpy_acc_sat_lh_s1, int_hexagon_M2_mpy_acc_sat_lh_s1>;
 164 def : T_RRR_pat <M2_mpy_acc_sat_lh_s0, int_hexagon_M2_mpy_acc_sat_lh_s0>;
 165 def : T_RRR_pat <M2_mpy_acc_sat_hl_s1, int_hexagon_M2_mpy_acc_sat_hl_s1>;
 166 def : T_RRR_pat <M2_mpy_acc_sat_hl_s0, int_hexagon_M2_mpy_acc_sat_hl_s0>;
 167 def : T_RRR_pat <M2_mpy_acc_sat_hh_s1, int_hexagon_M2_mpy_acc_sat_hh_s1>;
 168 def : T_RRR_pat <M2_mpy_acc_sat_hh_s0, int_hexagon_M2_mpy_acc_sat_hh_s0>;
 169
 170 def : T_RRR_pat <M2_mpy_nac_sat_ll_s1, int_hexagon_M2_mpy_nac_sat_ll_s1>;
 171 def : T_RRR_pat <M2_mpy_nac_sat_ll_s0, int_hexagon_M2_mpy_nac_sat_ll_s0>;
 172 def : T_RRR_pat <M2_mpy_nac_sat_lh_s1, int_hexagon_M2_mpy_nac_sat_lh_s1>;
 173 def : T_RRR_pat <M2_mpy_nac_sat_lh_s0, int_hexagon_M2_mpy_nac_sat_lh_s0>;
 174 def : T_RRR_pat <M2_mpy_nac_sat_hl_s1, int_hexagon_M2_mpy_nac_sat_hl_s1>;
 175 def : T_RRR_pat <M2_mpy_nac_sat_hl_s0, int_hexagon_M2_mpy_nac_sat_hl_s0>;
 176 def : T_RRR_pat <M2_mpy_nac_sat_hh_s1, int_hexagon_M2_mpy_nac_sat_hh_s1>;
 177 def : T_RRR_pat <M2_mpy_nac_sat_hh_s0, int_hexagon_M2_mpy_nac_sat_hh_s0>;
 178
 179
 180 //===----------------------------------------------------------------------===//
 181 // Multiply signed/unsigned halfwords with and without saturation and rounding
 182 // into a 64-bits destination register.
 183 //===----------------------------------------------------------------------===//
 184
 185 def : T_RR_pat <M2_mpyd_hh_s0, int_hexagon_M2_mpyd_hh_s0>;
 186 def : T_RR_pat <M2_mpyd_hl_s0, int_hexagon_M2_mpyd_hl_s0>;
 187 def : T_RR_pat <M2_mpyd_lh_s0, int_hexagon_M2_mpyd_lh_s0>;
 188 def : T_RR_pat <M2_mpyd_ll_s0, int_hexagon_M2_mpyd_ll_s0>;
 189 def : T_RR_pat <M2_mpyd_hh_s1, int_hexagon_M2_mpyd_hh_s1>;
 190 def : T_RR_pat <M2_mpyd_hl_s1, int_hexagon_M2_mpyd_hl_s1>;
 191 def : T_RR_pat <M2_mpyd_lh_s1, int_hexagon_M2_mpyd_lh_s1>;
 192 def : T_RR_pat <M2_mpyd_ll_s1, int_hexagon_M2_mpyd_ll_s1>;
 193
 194 def : T_RR_pat <M2_mpyd_rnd_hh_s0, int_hexagon_M2_mpyd_rnd_hh_s0>;
 195 def : T_RR_pat <M2_mpyd_rnd_hl_s0, int_hexagon_M2_mpyd_rnd_hl_s0>;
 196 def : T_RR_pat <M2_mpyd_rnd_lh_s0, int_hexagon_M2_mpyd_rnd_lh_s0>;
 197 def : T_RR_pat <M2_mpyd_rnd_ll_s0, int_hexagon_M2_mpyd_rnd_ll_s0>;
 198 def : T_RR_pat <M2_mpyd_rnd_hh_s1, int_hexagon_M2_mpyd_rnd_hh_s1>;
 199 def : T_RR_pat <M2_mpyd_rnd_hl_s1, int_hexagon_M2_mpyd_rnd_hl_s1>;
 200 def : T_RR_pat <M2_mpyd_rnd_lh_s1, int_hexagon_M2_mpyd_rnd_lh_s1>;
 201 def : T_RR_pat <M2_mpyd_rnd_ll_s1, int_hexagon_M2_mpyd_rnd_ll_s1>;
 202
 203 def : T_RR_pat <M2_mpyud_hh_s0, int_hexagon_M2_mpyud_hh_s0>;
 204 def : T_RR_pat <M2_mpyud_hl_s0, int_hexagon_M2_mpyud_hl_s0>;
 205 def : T_RR_pat <M2_mpyud_lh_s0, int_hexagon_M2_mpyud_lh_s0>;
 206 def : T_RR_pat <M2_mpyud_ll_s0, int_hexagon_M2_mpyud_ll_s0>;
 207 def : T_RR_pat <M2_mpyud_hh_s1, int_hexagon_M2_mpyud_hh_s1>;
 208 def : T_RR_pat <M2_mpyud_hl_s1, int_hexagon_M2_mpyud_hl_s1>;
 209 def : T_RR_pat <M2_mpyud_lh_s1, int_hexagon_M2_mpyud_lh_s1>;
 210 def : T_RR_pat <M2_mpyud_ll_s1, int_hexagon_M2_mpyud_ll_s1>;
 211
 212 //===----------------------------------------------------------------------===//
 213 // MPYS / Multipy signed/unsigned halfwords and add/subtract the
 214 // result from the 64-bit destination register.
 215 //Rxx [-+]= mpy[u](Rs.[H|L],Rt.[H|L])[:<<1][:sat]
 216 //===----------------------------------------------------------------------===//
 217
 218 def : T_PRR_pat <M2_mpyd_acc_hh_s0, int_hexagon_M2_mpyd_acc_hh_s0>;
 219 def : T_PRR_pat <M2_mpyd_acc_hl_s0, int_hexagon_M2_mpyd_acc_hl_s0>;
 220 def : T_PRR_pat <M2_mpyd_acc_lh_s0, int_hexagon_M2_mpyd_acc_lh_s0>;
 221 def : T_PRR_pat <M2_mpyd_acc_ll_s0, int_hexagon_M2_mpyd_acc_ll_s0>;
 222
 223 def : T_PRR_pat <M2_mpyd_acc_hh_s1, int_hexagon_M2_mpyd_acc_hh_s1>;
 224 def : T_PRR_pat <M2_mpyd_acc_hl_s1, int_hexagon_M2_mpyd_acc_hl_s1>;
 225 def : T_PRR_pat <M2_mpyd_acc_lh_s1, int_hexagon_M2_mpyd_acc_lh_s1>;
 226 def : T_PRR_pat <M2_mpyd_acc_ll_s1, int_hexagon_M2_mpyd_acc_ll_s1>;
 227
 228 def : T_PRR_pat <M2_mpyd_nac_hh_s0, int_hexagon_M2_mpyd_nac_hh_s0>;
 229 def : T_PRR_pat <M2_mpyd_nac_hl_s0, int_hexagon_M2_mpyd_nac_hl_s0>;
 230 def : T_PRR_pat <M2_mpyd_nac_lh_s0, int_hexagon_M2_mpyd_nac_lh_s0>;
 231 def : T_PRR_pat <M2_mpyd_nac_ll_s0, int_hexagon_M2_mpyd_nac_ll_s0>;
 232
 233 def : T_PRR_pat <M2_mpyd_nac_hh_s1, int_hexagon_M2_mpyd_nac_hh_s1>;
 234 def : T_PRR_pat <M2_mpyd_nac_hl_s1, int_hexagon_M2_mpyd_nac_hl_s1>;
 235 def : T_PRR_pat <M2_mpyd_nac_lh_s1, int_hexagon_M2_mpyd_nac_lh_s1>;
 236 def : T_PRR_pat <M2_mpyd_nac_ll_s1, int_hexagon_M2_mpyd_nac_ll_s1>;
 237
 238 def : T_PRR_pat <M2_mpyud_acc_hh_s0, int_hexagon_M2_mpyud_acc_hh_s0>;
 239 def : T_PRR_pat <M2_mpyud_acc_hl_s0, int_hexagon_M2_mpyud_acc_hl_s0>;
 240 def : T_PRR_pat <M2_mpyud_acc_lh_s0, int_hexagon_M2_mpyud_acc_lh_s0>;
 241 def : T_PRR_pat <M2_mpyud_acc_ll_s0, int_hexagon_M2_mpyud_acc_ll_s0>;
 242
 243 def : T_PRR_pat <M2_mpyud_acc_hh_s1, int_hexagon_M2_mpyud_acc_hh_s1>;
 244 def : T_PRR_pat <M2_mpyud_acc_hl_s1, int_hexagon_M2_mpyud_acc_hl_s1>;
 245 def : T_PRR_pat <M2_mpyud_acc_lh_s1, int_hexagon_M2_mpyud_acc_lh_s1>;
 246 def : T_PRR_pat <M2_mpyud_acc_ll_s1, int_hexagon_M2_mpyud_acc_ll_s1>;
 247
 248 def : T_PRR_pat <M2_mpyud_nac_hh_s0, int_hexagon_M2_mpyud_nac_hh_s0>;
 249 def : T_PRR_pat <M2_mpyud_nac_hl_s0, int_hexagon_M2_mpyud_nac_hl_s0>;
 250 def : T_PRR_pat <M2_mpyud_nac_lh_s0, int_hexagon_M2_mpyud_nac_lh_s0>;
 251 def : T_PRR_pat <M2_mpyud_nac_ll_s0, int_hexagon_M2_mpyud_nac_ll_s0>;
 252
 253 def : T_PRR_pat <M2_mpyud_nac_hh_s1, int_hexagon_M2_mpyud_nac_hh_s1>;
 254 def : T_PRR_pat <M2_mpyud_nac_hl_s1, int_hexagon_M2_mpyud_nac_hl_s1>;
 255 def : T_PRR_pat <M2_mpyud_nac_lh_s1, int_hexagon_M2_mpyud_nac_lh_s1>;
 256 def : T_PRR_pat <M2_mpyud_nac_ll_s1, int_hexagon_M2_mpyud_nac_ll_s1>;
 257
 258 /********************************************************************
 259 *            ALU32/ALU                                              *
 260 *********************************************************************/
 261 def : T_RR_pat<A2_add,      int_hexagon_A2_add>;
 262 def : T_RI_pat<ADD_ri,      int_hexagon_A2_addi>;
 263 def : T_RR_pat<A2_sub,      int_hexagon_A2_sub>;
 264 def : T_IR_pat<SUB_ri,      int_hexagon_A2_subri>;
 265 def : T_RR_pat<A2_and,      int_hexagon_A2_and>;
 266 def : T_RI_pat<AND_ri,      int_hexagon_A2_andir>;
 267 def : T_RR_pat<A2_or,       int_hexagon_A2_or>;
 268 def : T_RI_pat<OR_ri,       int_hexagon_A2_orir>;
 269 def : T_RR_pat<A2_xor,      int_hexagon_A2_xor>;
 270 def : T_RR_pat<A2_combinew, int_hexagon_A2_combinew>;
 271
 272 // Assembler mapped from Rd32=not(Rs32) to Rd32=sub(#-1,Rs32)
 273 def : Pat <(int_hexagon_A2_not (I32:$Rs)),
 274            (SUB_ri -1, IntRegs:$Rs)>;
 275
 276 // Assembler mapped from Rd32=neg(Rs32) to Rd32=sub(#0,Rs32)
 277 def : Pat <(int_hexagon_A2_neg IntRegs:$Rs),
 278            (SUB_ri 0, IntRegs:$Rs)>;
 279
 280 // Transfer immediate
 281 def  : Pat <(int_hexagon_A2_tfril (I32:$Rs), u16_0ImmPred:$Is),
 282             (A2_tfril IntRegs:$Rs, u16_0ImmPred:$Is)>;
 283 def  : Pat <(int_hexagon_A2_tfrih (I32:$Rs), u16_0ImmPred:$Is),
 284             (A2_tfrih IntRegs:$Rs, u16_0ImmPred:$Is)>;
 285
 286 //  Transfer Register/immediate.
 287 def : T_R_pat <A2_tfr, int_hexagon_A2_tfr>;
 288 def : T_I_pat <A2_tfrsi, int_hexagon_A2_tfrsi>;
 289
 290 // Assembler mapped from Rdd32=Rss32 to Rdd32=combine(Rss.H32,Rss.L32)
 291 def : Pat<(int_hexagon_A2_tfrp DoubleRegs:$src),
 292           (A2_combinew (HiReg DoubleRegs:$src), (LoReg DoubleRegs:$src))>;
 293
 294 /********************************************************************
 295 *            ALU32/PERM                                             *
 296 *********************************************************************/
 297 // Combine
 298 def: T_RR_pat<A2_combine_hh, int_hexagon_A2_combine_hh>;
 299 def: T_RR_pat<A2_combine_hl, int_hexagon_A2_combine_hl>;
 300 def: T_RR_pat<A2_combine_lh, int_hexagon_A2_combine_lh>;
 301 def: T_RR_pat<A2_combine_ll, int_hexagon_A2_combine_ll>;
 302
 303 def: T_II_pat<A2_combineii, int_hexagon_A2_combineii, s8ExtPred, s8ImmPred>;
 304
 305 def: Pat<(i32 (int_hexagon_C2_mux (I32:$Rp), (I32:$Rs),
 306                                                      (I32:$Rt))),
 307          (i32 (C2_mux (C2_tfrrp IntRegs:$Rp), IntRegs:$Rs, IntRegs:$Rt))>;
 308
 309 // Mux
 310 def : T_QRI_pat<C2_muxir, int_hexagon_C2_muxir, s8ExtPred>;
 311 def : T_QIR_pat<C2_muxri, int_hexagon_C2_muxri, s8ExtPred>;
 312 def : T_QII_pat<C2_muxii, int_hexagon_C2_muxii, s8ExtPred, s8ImmPred>;
 313
 314 // Shift halfword
 315 def : T_R_pat<A2_aslh, int_hexagon_A2_aslh>;
 316 def : T_R_pat<A2_asrh, int_hexagon_A2_asrh>;
 317 def : T_R_pat<A2_asrh, int_hexagon_SI_to_SXTHI_asrh>;
 318
 319 // Sign/zero extend
 320 def : T_R_pat<A2_sxth, int_hexagon_A2_sxth>;
 321 def : T_R_pat<A2_sxtb, int_hexagon_A2_sxtb>;
 322 def : T_R_pat<A2_zxth, int_hexagon_A2_zxth>;
 323 def : T_R_pat<A2_zxtb, int_hexagon_A2_zxtb>;
 324
 325 /********************************************************************
 326 *            ALU64/ALU                                              *
 327 *********************************************************************/
 328 def: T_RR_pat<A2_addsat,   int_hexagon_A2_addsat>;
 329 def: T_RR_pat<A2_subsat,   int_hexagon_A2_subsat>;
 330 def: T_PP_pat<A2_addp,     int_hexagon_A2_addp>;
 331 def: T_PP_pat<A2_subp,     int_hexagon_A2_subp>;
 332
 333 def: T_PP_pat<A2_andp,     int_hexagon_A2_andp>;
 334 def: T_PP_pat<A2_orp,      int_hexagon_A2_orp>;
 335 def: T_PP_pat<A2_xorp,     int_hexagon_A2_xorp>;
 336
 337 def: T_PP_pat<S2_parityp,  int_hexagon_S2_parityp>;
 338 def: T_RR_pat<S2_packhl,   int_hexagon_S2_packhl>;
 339
 340 // Multiply 32x32 and use lower result
 341 def : T_RRI_pat <M2_macsip, int_hexagon_M2_macsip>;
 342 def : T_RRI_pat <M2_macsin, int_hexagon_M2_macsin>;
 343 def : T_RRR_pat <M2_maci, int_hexagon_M2_maci>;
 344
 345 // Subtract and accumulate
 346 def : T_RRR_pat <M2_subacc, int_hexagon_M2_subacc>;
 347
 348 // Add and accumulate
 349 def : T_RRR_pat <M2_acci,   int_hexagon_M2_acci>;
 350 def : T_RRR_pat <M2_nacci,  int_hexagon_M2_nacci>;
 351 def : T_RRI_pat <M2_accii,  int_hexagon_M2_accii>;
 352 def : T_RRI_pat <M2_naccii, int_hexagon_M2_naccii>;
 353
 354 // XOR and XOR with destination
 355 def : T_RRR_pat <M2_xor_xacc, int_hexagon_M2_xor_xacc>;
 356
 357 //
 358 // ALU 32 types.
 359 //
 360
 361 class qi_ALU32_sisi<string opc, Intrinsic IntID>
 362   : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 363              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
 364              [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 365
 366 class qi_ALU32_sis10<string opc, Intrinsic IntID>
 367   : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, s10Imm:$src2),
 368              !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
 369              [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
 370
 371 class qi_ALU32_sis8<string opc, Intrinsic IntID>
 372   : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, s8Imm:$src2),
 373              !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
 374              [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
 375
 376 class qi_ALU32_siu8<string opc, Intrinsic IntID>
 377   : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, u8Imm:$src2),
 378              !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
 379              [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
 380
 381 class qi_ALU32_siu9<string opc, Intrinsic IntID>
 382   : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, u9Imm:$src2),
 383              !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
 384              [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
 385
 386 class si_ALU32_qisisi<string opc, Intrinsic IntID>
 387   : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2,
 388                                       IntRegs:$src3),
 389              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2, $src3)")),
 390              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2,
 391                                         IntRegs:$src3))]>;
 392
 393 class si_ALU32_qis8si<string opc, Intrinsic IntID>
 394   : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, s8Imm:$src2,
 395                                        IntRegs:$src3),
 396              !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2, $src3)")),
 397              [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2,
 398                                         IntRegs:$src3))]>;
 399
 400 class si_ALU32_qisis8<string opc, Intrinsic IntID>
 401   : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2,
 402                                        s8Imm:$src3),
 403              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2, #$src3)")),
 404              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2,
 405                                         imm:$src3))]>;
 406
 407 class si_ALU32_qis8s8<string opc, Intrinsic IntID>
 408   : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, s8Imm:$src2, s8Imm:$src3),
 409              !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2, #$src3)")),
 410              [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2, imm:$src3))]>;
 411
 412 class si_ALU32_sisi<string opc, Intrinsic IntID>
 413   : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 414              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
 415              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 416
 417 class si_ALU32_sisi_sat<string opc, Intrinsic IntID>
 418   : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 419              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):sat")),
 420              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 421
 422 class si_ALU32_sisi_rnd<string opc, Intrinsic IntID>
 423   : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 424              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):rnd")),
 425              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 426
 427 class si_ALU32_sis16<string opc, Intrinsic IntID>
 428   : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, s16Imm:$src2),
 429              !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
 430              [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
 431
 432 class si_ALU32_sis10<string opc, Intrinsic IntID>
 433   : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, s10Imm:$src2),
 434              !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
 435              [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
 436
 437 class si_ALU32_s10si<string opc, Intrinsic IntID>
 438   : ALU32_rr<(outs IntRegs:$dst), (ins s10Imm:$src1, IntRegs:$src2),
 439              !strconcat("$dst = ", !strconcat(opc , "(#$src1, $src2)")),
 440              [(set IntRegs:$dst, (IntID imm:$src1, IntRegs:$src2))]>;
 441
 442 class si_lo_ALU32_siu16<string opc, Intrinsic IntID>
 443   : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u16Imm:$src2),
 444              !strconcat("$dst.l = ", !strconcat(opc , "#$src2")),
 445              [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
 446
 447 class si_hi_ALU32_siu16<string opc, Intrinsic IntID>
 448   : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u16Imm:$src2),
 449              !strconcat("$dst.h = ", !strconcat(opc , "#$src2")),
 450              [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
 451
 452 class si_ALU32_s16<string opc, Intrinsic IntID>
 453   : ALU32_rr<(outs IntRegs:$dst), (ins s16Imm:$src1),
 454              !strconcat("$dst = ", !strconcat(opc , "#$src1")),
 455              [(set IntRegs:$dst, (IntID imm:$src1))]>;
 456
 457 class di_ALU32_s8<string opc, Intrinsic IntID>
 458   : ALU32_rr<(outs DoubleRegs:$dst), (ins s8Imm:$src1),
 459              !strconcat("$dst = ", !strconcat(opc , "#$src1")),
 460              [(set DoubleRegs:$dst, (IntID imm:$src1))]>;
 461
 462 class di_ALU64_di<string opc, Intrinsic IntID>
 463   : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src),
 464              !strconcat("$dst = ", !strconcat(opc , "$src")),
 465              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src))]>;
 466
 467 class si_ALU32_si<string opc, Intrinsic IntID>
 468   : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src),
 469              !strconcat("$dst = ", !strconcat(opc , "($src)")),
 470              [(set IntRegs:$dst, (IntID IntRegs:$src))]>;
 471
 472 class si_ALU32_si_tfr<string opc, Intrinsic IntID>
 473   : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src),
 474              !strconcat("$dst = ", !strconcat(opc , "$src")),
 475              [(set IntRegs:$dst, (IntID IntRegs:$src))]>;
 476
 477 //
 478 // ALU 64 types.
 479 //
 480
 481 class si_ALU64_si_sat<string opc, Intrinsic IntID>
 482   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src),
 483              !strconcat("$dst = ", !strconcat(opc , "($src):sat")),
 484              [(set IntRegs:$dst, (IntID IntRegs:$src))]>;
 485
 486 class si_ALU64_didi<string opc, Intrinsic IntID>
 487   : ALU64_rr<(outs IntRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
 488              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
 489              [(set IntRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
 490
 491 class di_ALU64_sidi<string opc, Intrinsic IntID>
 492   : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src1, DoubleRegs:$src2),
 493              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
 494              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, DoubleRegs:$src2))]>;
 495
 496 class di_ALU64_didi<string opc, Intrinsic IntID>
 497   : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
 498              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
 499              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
 500                                            DoubleRegs:$src2))]>;
 501
 502 class di_ALU64_qididi<string opc, Intrinsic IntID>
 503   : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src1, DoubleRegs:$src2,
 504                                           DoubleRegs:$src3),
 505              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2, $src3)")),
 506              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, DoubleRegs:$src2,
 507                                            DoubleRegs:$src3))]>;
 508
 509 class di_ALU64_sisi<string opc, Intrinsic IntID>
 510   : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 511              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
 512              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 513
 514 class di_ALU64_didi_sat<string opc, Intrinsic IntID>
 515   : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
 516              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):sat")),
 517              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
 518                                            DoubleRegs:$src2))]>;
 519
 520 class di_ALU64_didi_rnd<string opc, Intrinsic IntID>
 521   : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
 522              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):rnd")),
 523              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
 524                                            DoubleRegs:$src2))]>;
 525
 526 class di_ALU64_didi_crnd<string opc, Intrinsic IntID>
 527   : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
 528              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):crnd")),
 529              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
 530                                            DoubleRegs:$src2))]>;
 531
 532 class di_ALU64_didi_rnd_sat<string opc, Intrinsic IntID>
 533   : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
 534              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):rnd:sat")),
 535              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
 536                                            DoubleRegs:$src2))]>;
 537
 538 class di_ALU64_didi_crnd_sat<string opc, Intrinsic IntID>
 539   : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
 540              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):crnd:sat")),
 541              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
 542                                            DoubleRegs:$src2))]>;
 543
 544 class qi_ALU64_didi<string opc, Intrinsic IntID>
 545   : ALU64_rr<(outs PredRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
 546              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
 547              [(set PredRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
 548
 549 class si_ALU64_sisi<string opc, Intrinsic IntID>
 550   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 551              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
 552              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 553
 554 class si_ALU64_sisi_sat_lh<string opc, Intrinsic IntID>
 555   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 556              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H):sat")),
 557              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 558
 559 class si_ALU64_sisi_l16_sat_hh<string opc, Intrinsic IntID>
 560   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 561              !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.H):sat")),
 562              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 563
 564 class si_ALU64_sisi_l16_sat_lh<string opc, Intrinsic IntID>
 565   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 566              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H):sat")),
 567              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 568
 569 class si_ALU64_sisi_l16_sat_hl<string opc, Intrinsic IntID>
 570   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 571              !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.L):sat")),
 572              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 573
 574 class si_ALU64_sisi_l16_sat_ll<string opc, Intrinsic IntID>
 575   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 576              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L):sat")),
 577              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 578
 579 class si_ALU64_sisi_l16_hh<string opc, Intrinsic IntID>
 580   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 581              !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.H)")),
 582              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 583
 584 class si_ALU64_sisi_l16_hl<string opc, Intrinsic IntID>
 585   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 586              !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.L)")),
 587              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 588
 589 class si_ALU64_sisi_l16_lh<string opc, Intrinsic IntID>
 590   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 591              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H)")),
 592              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 593
 594 class si_ALU64_sisi_l16_ll<string opc, Intrinsic IntID>
 595   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 596              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L)")),
 597              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 598
 599 class si_ALU64_sisi_h16_sat_hh<string opc, Intrinsic IntID>
 600   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 601              !strconcat("$dst = ", !strconcat(opc ,
 602                                               "($src1.H, $src2.H):sat:<<16")),
 603              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 604
 605 class si_ALU64_sisi_h16_sat_lh<string opc, Intrinsic IntID>
 606   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 607              !strconcat("$dst = ", !strconcat(opc ,
 608                                               "($src1.L, $src2.H):sat:<<16")),
 609              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 610
 611 class si_ALU64_sisi_h16_sat_hl<string opc, Intrinsic IntID>
 612   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 613              !strconcat("$dst = ", !strconcat(opc ,
 614                                               "($src1.H, $src2.L):sat:<<16")),
 615              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 616
 617 class si_ALU64_sisi_h16_sat_ll<string opc, Intrinsic IntID>
 618   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 619              !strconcat("$dst = ", !strconcat(opc ,
 620                                               "($src1.L, $src2.L):sat:<<16")),
 621              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 622
 623 class si_ALU64_sisi_h16_hh<string opc, Intrinsic IntID>
 624   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 625              !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.H):<<16")),
 626              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 627
 628 class si_ALU64_sisi_h16_hl<string opc, Intrinsic IntID>
 629   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 630              !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.L):<<16")),
 631              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 632
 633 class si_ALU64_sisi_h16_lh<string opc, Intrinsic IntID>
 634   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 635              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H):<<16")),
 636              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 637
 638 class si_ALU64_sisi_h16_ll<string opc, Intrinsic IntID>
 639   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 640              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L):<<16")),
 641              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 642
 643 class si_ALU64_sisi_lh<string opc, Intrinsic IntID>
 644   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 645              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H)")),
 646              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 647
 648 class si_ALU64_sisi_ll<string opc, Intrinsic IntID>
 649   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 650              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L)")),
 651              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 652
 653 class si_ALU64_sisi_sat<string opc, Intrinsic IntID>
 654   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 655              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):sat")),
 656              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 657
 658 //
 659 // SInst classes.
 660 //
 661
 662 class qi_SInst_qi<string opc, Intrinsic IntID>
 663   : SInst<(outs PredRegs:$dst), (ins IntRegs:$src),
 664              !strconcat("$dst = ", !strconcat(opc , "($src)")),
 665              [(set PredRegs:$dst, (IntID IntRegs:$src))]>;
 666
 667 class qi_SInst_qi_pxfer<string opc, Intrinsic IntID>
 668   : SInst<(outs PredRegs:$dst), (ins IntRegs:$src),
 669              !strconcat("$dst = ", !strconcat(opc , "$src")),
 670              [(set PredRegs:$dst, (IntID IntRegs:$src))]>;
 671
 672 class qi_SInst_qiqi<string opc, Intrinsic IntID>
 673   : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 674              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
 675              [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 676
 677 class qi_SInst_qiqi_neg<string opc, Intrinsic IntID>
 678   : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 679              !strconcat("$dst = ", !strconcat(opc , "($src1, !$src2)")),
 680              [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 681
 682 class di_SInst_di<string opc, Intrinsic IntID>
 683   : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src),
 684              !strconcat("$dst = ", !strconcat(opc , "($src)")),
 685              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src))]>;
 686
 687 class di_SInst_di_sat<string opc, Intrinsic IntID>
 688   : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src),
 689              !strconcat("$dst = ", !strconcat(opc , "($src):sat")),
 690              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src))]>;
 691
 692 class si_SInst_di<string opc, Intrinsic IntID>
 693   : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src),
 694           !strconcat("$dst = ", !strconcat(opc , "($src)")),
 695           [(set IntRegs:$dst, (IntID DoubleRegs:$src))]>;
 696
 697 class si_SInst_di_sat<string opc, Intrinsic IntID>
 698   : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src),
 699           !strconcat("$dst = ", !strconcat(opc , "($src):sat")),
 700           [(set IntRegs:$dst, (IntID DoubleRegs:$src))]>;
 701
 702 class di_SInst_disi<string opc, Intrinsic IntID>
 703   : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
 704           !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
 705           [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, IntRegs:$src2))]>;
 706
 707 class di_SInst_didi<string opc, Intrinsic IntID>
 708   : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
 709           !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
 710           [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
 711
 712 class di_SInst_si<string opc, Intrinsic IntID>
 713   : SInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1),
 714           !strconcat("$dst = ", !strconcat(opc , "($src1)")),
 715           [(set DoubleRegs:$dst, (IntID IntRegs:$src1))]>;
 716
 717 class si_SInst_sisiu3<string opc, Intrinsic IntID>
 718   : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2, u3Imm:$src3),
 719           !strconcat("$dst = ", !strconcat(opc , "($src1, $src2, #$src3)")),
 720           [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2,
 721                                      imm:$src3))]>;
 722
 723 class si_SInst_diu5<string opc, Intrinsic IntID>
 724   : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, u5Imm:$src2),
 725           !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
 726           [(set IntRegs:$dst, (IntID DoubleRegs:$src1, imm:$src2))]>;
 727
 728 class si_SInst_disi<string opc, Intrinsic IntID>
 729   : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
 730           !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
 731           [(set IntRegs:$dst, (IntID DoubleRegs:$src1, IntRegs:$src2))]>;
 732
 733 class si_SInst_sidi<string opc, Intrinsic IntID>
 734   : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, DoubleRegs:$src2),
 735           !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
 736           [(set IntRegs:$dst, (IntID IntRegs:$src1, DoubleRegs:$src2))]>;
 737
 738 class di_SInst_disisi<string opc, Intrinsic IntID>
 739   : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2,
 740                                        IntRegs:$src3),
 741           !strconcat("$dst = ", !strconcat(opc , "($src1, $src2, $src3)")),
 742           [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, IntRegs:$src2,
 743                                         IntRegs:$src3))]>;
 744
 745 class di_SInst_sisi<string opc, Intrinsic IntID>
 746   : SInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 747           !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
 748           [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 749
 750 class qi_SInst_siu5<string opc, Intrinsic IntID>
 751   : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
 752           !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
 753           [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
 754
 755 class qi_SInst_siu6<string opc, Intrinsic IntID>
 756   : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, u6Imm:$src2),
 757           !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
 758           [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
 759
 760 class qi_SInst_sisi<string opc, Intrinsic IntID>
 761   : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 762           !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
 763           [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 764
 765 class si_SInst_si<string opc, Intrinsic IntID>
 766   : SInst<(outs IntRegs:$dst), (ins IntRegs:$src),
 767           !strconcat("$dst = ", !strconcat(opc , "($src)")),
 768           [(set IntRegs:$dst, (IntID IntRegs:$src))]>;
 769
 770 class si_SInst_si_sat<string opc, Intrinsic IntID>
 771   : SInst<(outs IntRegs:$dst), (ins IntRegs:$src),
 772           !strconcat("$dst = ", !strconcat(opc , "($src):sat")),
 773           [(set IntRegs:$dst, (IntID IntRegs:$src))]>;
 774
 775 class di_SInst_qi<string opc, Intrinsic IntID>
 776   : SInst<(outs DoubleRegs:$dst), (ins IntRegs:$src),
 777           !strconcat("$dst = ", !strconcat(opc , "($src)")),
 778           [(set DoubleRegs:$dst, (IntID IntRegs:$src))]>;
 779
 780 class si_SInst_qi<string opc, Intrinsic IntID>
 781   : SInst<(outs IntRegs:$dst), (ins IntRegs:$src),
 782           !strconcat("$dst = ", !strconcat(opc , "$src")),
 783           [(set IntRegs:$dst, (IntID IntRegs:$src))]>;
 784
 785 class si_SInst_qiqi<string opc, Intrinsic IntID>
 786   : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 787           !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
 788           [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 789
 790 class qi_SInst_si<string opc, Intrinsic IntID>
 791   : SInst<(outs PredRegs:$dst), (ins IntRegs:$src),
 792           !strconcat("$dst = ", !strconcat(opc , "$src")),
 793           [(set PredRegs:$dst, (IntID IntRegs:$src))]>;
 794
 795 class si_SInst_sisi<string opc, Intrinsic IntID>
 796   : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 797           !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
 798           [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 799
 800 class di_SInst_diu6<string opc, Intrinsic IntID>
 801   : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u6Imm:$src2),
 802           !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
 803           [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, imm:$src2))]>;
 804
 805 class si_SInst_siu5<string opc, Intrinsic IntID>
 806   : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
 807           !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
 808           [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
 809
 810 class si_SInst_siu5_rnd<string opc, Intrinsic IntID>
 811   : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
 812           !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2):rnd")),
 813           [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
 814
 815 class si_SInst_siu5u5<string opc, Intrinsic IntID>
 816   : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2, u5Imm:$src3),
 817           !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2, #$src3)")),
 818           [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2, imm:$src3))]>;
 819
 820 class si_SInst_sisisi_acc<string opc, Intrinsic IntID>
 821   : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
 822                                         IntRegs:$src2),
 823               !strconcat("$dst += ", !strconcat(opc , "($src1, $src2)")),
 824               [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
 825                                          IntRegs:$src2))],
 826               "$dst2 = $dst">;
 827
 828 class si_SInst_sisisi_nac<string opc, Intrinsic IntID>
 829   : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
 830                                         IntRegs:$src2),
 831               !strconcat("$dst -= ", !strconcat(opc , "($src1, $src2)")),
 832               [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
 833                                          IntRegs:$src2))],
 834               "$dst2 = $dst">;
 835
 836 class di_SInst_didisi_acc<string opc, Intrinsic IntID>
 837   : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
 838                                            IntRegs:$src2),
 839                !strconcat("$dst += ", !strconcat(opc , "($src1, $src2)")),
 840                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
 841                                              DoubleRegs:$src1,
 842                                              IntRegs:$src2))],
 843                "$dst2 = $dst">;
 844
 845 class di_SInst_didisi_nac<string opc, Intrinsic IntID>
 846   : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
 847                                            IntRegs:$src2),
 848           !strconcat("$dst -= ", !strconcat(opc , "($src1, $src2)")),
 849           [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
 850                                         DoubleRegs:$src1, IntRegs:$src2))],
 851           "$dst2 = $dst">;
 852
 853 class si_SInst_sisiu5u5<string opc, Intrinsic IntID>
 854   : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
 855                                         u5Imm:$src2, u5Imm:$src3),
 856               !strconcat("$dst = ", !strconcat(opc ,
 857                                                "($src1, #$src2, #$src3)")),
 858               [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
 859                                          imm:$src2, imm:$src3))],
 860               "$dst2 = $dst">;
 861
 862 class si_SInst_sisidi<string opc, Intrinsic IntID>
 863   : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
 864                                         DoubleRegs:$src2),
 865               !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
 866               [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
 867                                          DoubleRegs:$src2))],
 868               "$dst2 = $dst">;
 869
 870 class di_SInst_didiu6u6<string opc, Intrinsic IntID>
 871   : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
 872                                            u6Imm:$src2, u6Imm:$src3),
 873               !strconcat("$dst = ", !strconcat(opc ,
 874                                                "($src1, #$src2, #$src3)")),
 875               [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, DoubleRegs:$src1,
 876                                             imm:$src2, imm:$src3))],
 877               "$dst2 = $dst">;
 878
 879 class di_SInst_dididi<string opc, Intrinsic IntID>
 880   : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
 881                                            DoubleRegs:$src2),
 882               !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
 883               [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
 884                                             DoubleRegs:$src1,
 885                                             DoubleRegs:$src2))],
 886               "$dst2 = $dst">;
 887
 888 class di_SInst_diu6u6<string opc, Intrinsic IntID>
 889   : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u6Imm:$src2,
 890                                        u6Imm:$src3),
 891           !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2, #$src3)")),
 892           [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, imm:$src2,
 893                                         imm:$src3))]>;
 894
 895 class di_SInst_didiqi<string opc, Intrinsic IntID>
 896   : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2,
 897                                        IntRegs:$src3),
 898           !strconcat("$dst = ", !strconcat(opc , "($src1, $src2, $src3)")),
 899           [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2,
 900                                         IntRegs:$src3))]>;
 901
 902 class di_SInst_didiu3<string opc, Intrinsic IntID>
 903   : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2,
 904                                        u3Imm:$src3),
 905           !strconcat("$dst = ", !strconcat(opc , "($src1, $src2, #$src3)")),
 906           [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2,
 907                                         imm:$src3))]>;
 908
 909 class di_SInst_didisi_or<string opc, Intrinsic IntID>
 910   : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
 911                                            IntRegs:$src2),
 912           !strconcat("$dst |= ", !strconcat(opc , "($src1, $src2)")),
 913           [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, DoubleRegs:$src1,
 914                                         IntRegs:$src2))],
 915           "$dst2 = $dst">;
 916
 917 class di_SInst_didisi_and<string opc, Intrinsic IntID>
 918   : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
 919                                            IntRegs:$src2),
 920           !strconcat("$dst &= ", !strconcat(opc , "($src1, $src2)")),
 921           [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, DoubleRegs:$src1,
 922                                         IntRegs:$src2))],
 923           "$dst2 = $dst">;
 924
 925 class di_SInst_didiu6_and<string opc, Intrinsic IntID>
 926   : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
 927                                            u6Imm:$src2),
 928           !strconcat("$dst &= ", !strconcat(opc , "($src1, #$src2)")),
 929           [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, DoubleRegs:$src1,
 930                                         imm:$src2))],
 931           "$dst2 = $dst">;
 932
 933 class di_SInst_didiu6_or<string opc, Intrinsic IntID>
 934   : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
 935                                            u6Imm:$src2),
 936           !strconcat("$dst |= ", !strconcat(opc , "($src1, #$src2)")),
 937           [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, DoubleRegs:$src1,
 938                                         imm:$src2))],
 939           "$dst2 = $dst">;
 940
 941 class di_SInst_didiu6_xor<string opc, Intrinsic IntID>
 942   : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
 943                                            u6Imm:$src2),
 944           !strconcat("$dst ^= ", !strconcat(opc , "($src1, #$src2)")),
 945           [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, DoubleRegs:$src1,
 946                                         imm:$src2))],
 947           "$dst2 = $dst">;
 948
 949 class si_SInst_sisisi_and<string opc, Intrinsic IntID>
 950   : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
 951                                         IntRegs:$src2),
 952               !strconcat("$dst &= ", !strconcat(opc , "($src1, $src2)")),
 953               [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
 954                                          IntRegs:$src2))],
 955               "$dst2 = $dst">;
 956
 957 class si_SInst_sisisi_or<string opc, Intrinsic IntID>
 958   : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
 959                                         IntRegs:$src2),
 960               !strconcat("$dst |= ", !strconcat(opc , "($src1, $src2)")),
 961               [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
 962                                          IntRegs:$src2))],
 963               "$dst2 = $dst">;
 964
 965
 966 class si_SInst_sisiu5_and<string opc, Intrinsic IntID>
 967   : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
 968                                         u5Imm:$src2),
 969               !strconcat("$dst &= ", !strconcat(opc , "($src1, #$src2)")),
 970               [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
 971                                          imm:$src2))],
 972               "$dst2 = $dst">;
 973
 974 class si_SInst_sisiu5_or<string opc, Intrinsic IntID>
 975   : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
 976                                         u5Imm:$src2),
 977               !strconcat("$dst |= ", !strconcat(opc , "($src1, #$src2)")),
 978               [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
 979                                          imm:$src2))],
 980               "$dst2 = $dst">;
 981
 982 class si_SInst_sisiu5_xor<string opc, Intrinsic IntID>
 983   : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
 984                                         u5Imm:$src2),
 985               !strconcat("$dst ^= ", !strconcat(opc , "($src1, #$src2)")),
 986               [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
 987                                          imm:$src2))],
 988               "$dst2 = $dst">;
 989
 990 class si_SInst_sisiu5_acc<string opc, Intrinsic IntID>
 991   : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
 992                                         u5Imm:$src2),
 993               !strconcat("$dst += ", !strconcat(opc , "($src1, #$src2)")),
 994               [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
 995                                          imm:$src2))],
 996               "$dst2 = $dst">;
 997
 998 class si_SInst_sisiu5_nac<string opc, Intrinsic IntID>
 999   : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1000                                         u5Imm:$src2),
1001               !strconcat("$dst -= ", !strconcat(opc , "($src1, #$src2)")),
1002               [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1003                                          imm:$src2))],
1004               "$dst2 = $dst">;
1005
1006 class di_SInst_didiu6_acc<string opc, Intrinsic IntID>
1007   : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
1008                                            u5Imm:$src2),
1009               !strconcat("$dst += ", !strconcat(opc , "($src1, #$src2)")),
1010               [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
1011                                             DoubleRegs:$src1, imm:$src2))],
1012               "$dst2 = $dst">;
1013
1014 class di_SInst_didiu6_nac<string opc, Intrinsic IntID>
1015   : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
1016                                            u5Imm:$src2),
1017               !strconcat("$dst -= ", !strconcat(opc , "($src1, #$src2)")),
1018               [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, DoubleRegs:$src1,
1019                                             imm:$src2))],
1020               "$dst2 = $dst">;
1021
1022
1023 //
1024 // MInst classes.
1025 //
1026
1027 class di_MInst_sisi_rnd_hh_s1<string opc, Intrinsic IntID>
1028   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1029                !strconcat("$dst = ", !strconcat(opc ,
1030                                                 "($src1.H, $src2.H):<<1:rnd")),
1031                [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1032
1033 class di_MInst_sisi_rnd_hh<string opc, Intrinsic IntID>
1034   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1035                !strconcat("$dst = ", !strconcat(opc ,
1036                                                 "($src1.H, $src2.H):rnd")),
1037                [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1038
1039 class di_MInst_sisi_rnd_hl_s1<string opc, Intrinsic IntID>
1040   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1041                !strconcat("$dst = ", !strconcat(opc ,
1042                                                 "($src1.H, $src2.L):<<1:rnd")),
1043                [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1044
1045 class di_MInst_sisi_rnd_hl<string opc, Intrinsic IntID>
1046   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1047                !strconcat("$dst = ", !strconcat(opc ,
1048                                                 "($src1.H, $src2.L):rnd")),
1049                [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1050
1051 class di_MInst_sisi_rnd_lh_s1<string opc, Intrinsic IntID>
1052   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1053                !strconcat("$dst = ", !strconcat(opc ,
1054                                                 "($src1.L, $src2.H):<<1:rnd")),
1055                [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1056
1057 class di_MInst_sisi_rnd_lh<string opc, Intrinsic IntID>
1058   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1059                !strconcat("$dst = ", !strconcat(opc ,
1060                                                 "($src1.L, $src2.H):rnd")),
1061                [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1062
1063 class di_MInst_sisi_rnd_ll_s1<string opc, Intrinsic IntID>
1064   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1065                !strconcat("$dst = ", !strconcat(opc ,
1066                                                 "($src1.L, $src2.L):<<1:rnd")),
1067                [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1068
1069 class di_MInst_sisi_rnd_ll<string opc, Intrinsic IntID>
1070   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1071                !strconcat("$dst = ", !strconcat(opc ,
1072                                                 "($src1.L, $src2.L):rnd")),
1073                [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1074
1075 class di_MInst_disisi_acc<string opc, Intrinsic IntID>
1076   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1077                                            IntRegs:$src2),
1078              !strconcat("$dst += ", !strconcat(opc , "($src1, $src2)")),
1079              [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1080                                            IntRegs:$src2))],
1081              "$dst2 = $dst">;
1082
1083 class di_MInst_disisi_nac<string opc, Intrinsic IntID>
1084   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1085                                            IntRegs:$src2),
1086              !strconcat("$dst -= ", !strconcat(opc , "($src1, $src2)")),
1087              [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1088                                            IntRegs:$src2))],
1089              "$dst2 = $dst">;
1090
1091 class di_MInst_disisi_acc_sat<string opc, Intrinsic IntID>
1092   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1093                                            IntRegs:$src2),
1094              !strconcat("$dst += ", !strconcat(opc , "($src1, $src2):sat")),
1095              [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1096                                            IntRegs:$src2))],
1097              "$dst2 = $dst">;
1098
1099 class di_MInst_disisi_nac_sat<string opc, Intrinsic IntID>
1100   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1101                                            IntRegs:$src2),
1102              !strconcat("$dst -= ", !strconcat(opc , "($src1, $src2):sat")),
1103              [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1104                                            IntRegs:$src2))],
1105              "$dst2 = $dst">;
1106
1107 class di_MInst_disisi_acc_sat_conj<string opc, Intrinsic IntID>
1108   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1109                                            IntRegs:$src2),
1110              !strconcat("$dst += ", !strconcat(opc , "($src1, $src2*):sat")),
1111              [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1112                                            IntRegs:$src2))],
1113              "$dst2 = $dst">;
1114
1115 class di_MInst_disisi_nac_sat_conj<string opc, Intrinsic IntID>
1116   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1117                                            IntRegs:$src2),
1118              !strconcat("$dst -= ", !strconcat(opc , "($src1, $src2*):sat")),
1119              [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1120                                            IntRegs:$src2))],
1121              "$dst2 = $dst">;
1122
1123 class di_MInst_disisi_nac_s1_sat<string opc, Intrinsic IntID>
1124   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1125                                            IntRegs:$src2),
1126              !strconcat("$dst -= ", !strconcat(opc ,
1127                                                "($src1, $src2):<<1:sat")),
1128              [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1129                                            IntRegs:$src2))],
1130              "$dst2 = $dst">;
1131
1132 class di_MInst_disisi_acc_s1_sat_conj<string opc, Intrinsic IntID>
1133   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1134                                            IntRegs:$src2),
1135              !strconcat("$dst += ", !strconcat(opc ,
1136                                                "($src1, $src2*):<<1:sat")),
1137              [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1138                                            IntRegs:$src2))],
1139              "$dst2 = $dst">;
1140
1141 class di_MInst_disisi_nac_s1_sat_conj<string opc, Intrinsic IntID>
1142   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1143                                            IntRegs:$src2),
1144              !strconcat("$dst -= ", !strconcat(opc ,
1145                                                "($src1, $src2*):<<1:sat")),
1146              [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1147                                            IntRegs:$src2))],
1148              "$dst2 = $dst">;
1149
1150 class di_MInst_s8s8<string opc, Intrinsic IntID>
1151   : MInst<(outs DoubleRegs:$dst), (ins s8Imm:$src1, s8Imm:$src2),
1152              !strconcat("$dst = ", !strconcat(opc , "(#$src1, #$src2)")),
1153              [(set DoubleRegs:$dst, (IntID imm:$src1, imm:$src2))]>;
1154
1155 class si_MInst_sis9<string opc, Intrinsic IntID>
1156   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, s9Imm:$src2),
1157              !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
1158              [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
1159
1160 class si_MInst_sisi<string opc, Intrinsic IntID>
1161   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1162              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
1163              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1164
1165 class di_MInst_sisi_hh<string opc, Intrinsic IntID>
1166   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1167              !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.H)")),
1168              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1169
1170 class di_MInst_sisi_hh_s1<string opc, Intrinsic IntID>
1171   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1172              !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.H):<<1")),
1173              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1174
1175 class di_MInst_sisi_lh<string opc, Intrinsic IntID>
1176   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1177              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H)")),
1178              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1179
1180 class di_MInst_sisi_lh_s1<string opc, Intrinsic IntID>
1181   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1182              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H):<<1")),
1183              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1184
1185 class di_MInst_sisi_hl<string opc, Intrinsic IntID>
1186   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1187              !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.L)")),
1188              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1189
1190 class di_MInst_sisi_hl_s1<string opc, Intrinsic IntID>
1191   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1192              !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.L):<<1")),
1193              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1194
1195 class di_MInst_sisi_ll<string opc, Intrinsic IntID>
1196   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1197              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L)")),
1198              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1199
1200 class di_MInst_sisi_ll_s1<string opc, Intrinsic IntID>
1201   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1202              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L):<<1")),
1203              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1204
1205
1206 class si_MInst_sisi_hh<string opc, Intrinsic IntID>
1207   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1208              !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.H)")),
1209              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1210
1211 class si_MInst_sisi_hh_s1<string opc, Intrinsic IntID>
1212   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1213              !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.H):<<1")),
1214              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1215
1216 class si_MInst_sisi_lh<string opc, Intrinsic IntID>
1217   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1218              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H)")),
1219              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1220
1221 class si_MInst_sisi_lh_s1<string opc, Intrinsic IntID>
1222   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1223              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H):<<1")),
1224              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1225
1226 class si_MInst_sisi_hl<string opc, Intrinsic IntID>
1227   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1228              !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.L)")),
1229              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1230
1231 class si_MInst_sisi_hl_s1<string opc, Intrinsic IntID>
1232   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1233              !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.L):<<1")),
1234              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1235
1236 class si_MInst_sisi_ll<string opc, Intrinsic IntID>
1237   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1238              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L)")),
1239              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1240
1241 class si_MInst_sisi_ll_s1<string opc, Intrinsic IntID>
1242   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1243              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L):<<1")),
1244              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1245
1246 class si_MInst_sisi_up<string opc, Intrinsic IntID>
1247   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1248              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
1249              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1250
1251 class di_MInst_didi<string opc, Intrinsic IntID>
1252   : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1253              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
1254              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
1255                                            DoubleRegs:$src2))]>;
1256
1257 class di_MInst_didi_conj<string opc, Intrinsic IntID>
1258   : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1259              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2*)")),
1260              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
1261                                            DoubleRegs:$src2))]>;
1262
1263 class di_MInst_sisi_s1_sat_conj<string opc, Intrinsic IntID>
1264   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1265              !strconcat("$dst = ", !strconcat(opc ,
1266                                               "($src1, $src2*):<<1:sat")),
1267              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1268
1269 class di_MInst_didi_s1_rnd_sat<string opc, Intrinsic IntID>
1270   : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1271              !strconcat("$dst = ", !strconcat(opc ,
1272                                               "($src1, $src2):<<1:rnd:sat")),
1273              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
1274                                            DoubleRegs:$src2))]>;
1275
1276 class di_MInst_didi_sat<string opc, Intrinsic IntID>
1277   : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1278              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):sat")),
1279              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
1280                                            DoubleRegs:$src2))]>;
1281
1282 class di_MInst_didi_rnd_sat<string opc, Intrinsic IntID>
1283   : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1284              !strconcat("$dst = ", !strconcat(opc ,
1285                                               "($src1, $src2):rnd:sat")),
1286              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
1287                                            DoubleRegs:$src2))]>;
1288
1289 class si_SInst_sisi_sat<string opc, Intrinsic IntID>
1290   : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1291           !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):sat")),
1292           [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1293
1294 class si_SInst_didi_sat<string opc, Intrinsic IntID>
1295   : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1296           !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):sat")),
1297           [(set IntRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
1298
1299 class si_SInst_disi_s1_rnd_sat<string opc, Intrinsic IntID>
1300   : MInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
1301              !strconcat("$dst = ", !strconcat(opc ,
1302                                               "($src1, $src2):<<1:rnd:sat")),
1303              [(set IntRegs:$dst, (IntID DoubleRegs:$src1, IntRegs:$src2))]>;
1304
1305 class si_MInst_sisi_s1_rnd_sat<string opc, Intrinsic IntID>
1306   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1307              !strconcat("$dst = ", !strconcat(opc ,
1308                                               "($src1, $src2):<<1:rnd:sat")),
1309              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1310
1311 class si_MInst_sisi_l_s1_rnd_sat<string opc, Intrinsic IntID>
1312   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1313              !strconcat("$dst = ", !strconcat(opc ,
1314                                               "($src1, $src2.L):<<1:rnd:sat")),
1315              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1316
1317 class si_MInst_sisi_h_s1_rnd_sat<string opc, Intrinsic IntID>
1318   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1319              !strconcat("$dst = ", !strconcat(opc ,
1320                                               "($src1, $src2.H):<<1:rnd:sat")),
1321              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1322
1323 class si_MInst_sisi_rnd_sat_conj<string opc, Intrinsic IntID>
1324   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1325              !strconcat("$dst = ", !strconcat(opc ,
1326                                               "($src1, $src2*):rnd:sat")),
1327              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1328
1329 class si_MInst_sisi_s1_rnd_sat_conj<string opc, Intrinsic IntID>
1330   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1331              !strconcat("$dst = ", !strconcat(opc ,
1332                                               "($src1, $src2*):<<1:rnd:sat")),
1333              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1334
1335 class si_MInst_sisi_rnd_sat<string opc, Intrinsic IntID>
1336   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1337              !strconcat("$dst = ", !strconcat(opc ,
1338                                               "($src1, $src2):rnd:sat")),
1339              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1340
1341 class si_MInst_sisi_rnd<string opc, Intrinsic IntID>
1342   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1343              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):rnd")),
1344              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1345
1346 class si_MInst_sisisi_xacc<string opc, Intrinsic IntID>
1347   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src2,
1348                                         IntRegs:$src3),
1349              !strconcat("$dst ^= ", !strconcat(opc , "($src2, $src3)")),
1350              [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src2,
1351                                         IntRegs:$src3))],
1352              "$dst2 = $dst">;
1353
1354 class si_MInst_sisisi_acc<string opc, Intrinsic IntID>
1355   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src2,
1356                                         IntRegs:$src3),
1357              !strconcat("$dst += ", !strconcat(opc , "($src2, $src3)")),
1358              [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src2,
1359                                         IntRegs:$src3))],
1360              "$dst2 = $dst">;
1361
1362 class si_MInst_sisisi_nac<string opc, Intrinsic IntID>
1363   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src2,
1364                                         IntRegs:$src3),
1365              !strconcat("$dst -= ", !strconcat(opc , "($src2, $src3)")),
1366              [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src2,
1367                                         IntRegs:$src3))],
1368              "$dst2 = $dst">;
1369
1370 class si_MInst_sisis8_acc<string opc, Intrinsic IntID>
1371   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src2,
1372                                         s8Imm:$src3),
1373              !strconcat("$dst += ", !strconcat(opc , "($src2, #$src3)")),
1374              [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src2,
1375                                         imm:$src3))],
1376              "$dst2 = $dst">;
1377
1378 class si_MInst_sisis8_nac<string opc, Intrinsic IntID>
1379   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src2,
1380                                         s8Imm:$src3),
1381              !strconcat("$dst -= ", !strconcat(opc , "($src2, #$src3)")),
1382              [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src2,
1383                                         imm:$src3))],
1384              "$dst2 = $dst">;
1385
1386 class si_MInst_sisiu4u5<string opc, Intrinsic IntID>
1387   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1388                                         u4Imm:$src2, u5Imm:$src3),
1389                !strconcat("$dst = ", !strconcat(opc ,
1390                                                 "($src1, #$src2, #$src3)")),
1391                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1392                                           imm:$src2, imm:$src3))],
1393                "$dst2 = $dst">;
1394
1395 class si_MInst_sisiu8_acc<string opc, Intrinsic IntID>
1396   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src2,
1397                                         u8Imm:$src3),
1398                !strconcat("$dst += ", !strconcat(opc , "($src2, #$src3)")),
1399                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src2,
1400                                           imm:$src3))],
1401                "$dst2 = $dst">;
1402
1403 class si_MInst_sisiu8_nac<string opc, Intrinsic IntID>
1404   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src2,
1405                                         u8Imm:$src3),
1406                !strconcat("$dst -= ", !strconcat(opc , "($src2, #$src3)")),
1407                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src2,
1408                                           imm:$src3))],
1409                "$dst2 = $dst">;
1410
1411 class si_MInst_sisisi_acc_hh<string opc, Intrinsic IntID>
1412   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1413                                         IntRegs:$src2),
1414                !strconcat("$dst += ", !strconcat(opc , "($src1.H, $src2.H)")),
1415                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1416                                           IntRegs:$src2))],
1417                "$dst2 = $dst">;
1418
1419 class si_MInst_sisisi_acc_sat_lh<string opc, Intrinsic IntID>
1420   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1421                                         IntRegs:$src2),
1422                !strconcat("$dst += ", !strconcat(opc ,
1423                                                  "($src1.L, $src2.H):sat")),
1424                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1425                                           IntRegs:$src2))],
1426                "$dst2 = $dst">;
1427
1428 class si_MInst_sisisi_acc_sat_lh_s1<string opc, Intrinsic IntID>
1429   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1430                                         IntRegs:$src2),
1431                !strconcat("$dst += ", !strconcat(opc ,
1432                                                  "($src1.L, $src2.H):<<1:sat")),
1433                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1434                                           IntRegs:$src2))],
1435                "$dst2 = $dst">;
1436
1437 class si_MInst_sisisi_acc_sat_hh<string opc, Intrinsic IntID>
1438   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1439                                         IntRegs:$src2),
1440                !strconcat("$dst += ", !strconcat(opc ,
1441                                                  "($src1.H, $src2.H):sat")),
1442                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1443                                           IntRegs:$src2))],
1444                "$dst2 = $dst">;
1445
1446 class si_MInst_sisisi_acc_sat_hh_s1<string opc, Intrinsic IntID>
1447   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1448                                         IntRegs:$src2),
1449                !strconcat("$dst += ", !strconcat(opc ,
1450                                                  "($src1.H, $src2.H):<<1:sat")),
1451                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1452                                           IntRegs:$src2))],
1453                "$dst2 = $dst">;
1454
1455 class si_MInst_sisisi_acc_hh_s1<string opc, Intrinsic IntID>
1456   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1457                                         IntRegs:$src2),
1458                !strconcat("$dst += ", !strconcat(opc ,
1459                                                  "($src1.H, $src2.H):<<1")),
1460                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1461                                           IntRegs:$src2))],
1462                "$dst2 = $dst">;
1463
1464 class si_MInst_sisisi_nac_hh<string opc, Intrinsic IntID>
1465   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1466                                         IntRegs:$src2),
1467                !strconcat("$dst -= ", !strconcat(opc , "($src1.H, $src2.H)")),
1468                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1469                                           IntRegs:$src2))],
1470                "$dst2 = $dst">;
1471
1472 class si_MInst_sisisi_nac_sat_hh_s1<string opc, Intrinsic IntID>
1473   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1474                                         IntRegs:$src2),
1475                !strconcat("$dst -= ", !strconcat(opc ,
1476                                                  "($src1.H, $src2.H):<<1:sat")),
1477                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1478                                           IntRegs:$src2))],
1479                "$dst2 = $dst">;
1480
1481 class si_MInst_sisisi_nac_sat_hh<string opc, Intrinsic IntID>
1482   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1483                                         IntRegs:$src2),
1484                !strconcat("$dst -= ", !strconcat(opc ,
1485                                                  "($src1.H, $src2.H):sat")),
1486                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1487                                           IntRegs:$src2))],
1488                "$dst2 = $dst">;
1489
1490 class si_MInst_sisisi_nac_sat_hl_s1<string opc, Intrinsic IntID>
1491   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1492                                         IntRegs:$src2),
1493                !strconcat("$dst -= ", !strconcat(opc ,
1494                                                  "($src1.H, $src2.L):<<1:sat")),
1495                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1496                                           IntRegs:$src2))],
1497                "$dst2 = $dst">;
1498
1499 class si_MInst_sisisi_nac_sat_hl<string opc, Intrinsic IntID>
1500   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1501                                         IntRegs:$src2),
1502                !strconcat("$dst -= ", !strconcat(opc ,
1503                                                  "($src1.H, $src2.L):sat")),
1504                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1505                                           IntRegs:$src2))],
1506                "$dst2 = $dst">;
1507
1508 class si_MInst_sisisi_nac_sat_lh_s1<string opc, Intrinsic IntID>
1509   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1510                                         IntRegs:$src2),
1511                !strconcat("$dst -= ", !strconcat(opc ,
1512                                                  "($src1.L, $src2.H):<<1:sat")),
1513                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1514                                           IntRegs:$src2))],
1515                "$dst2 = $dst">;
1516
1517 class si_MInst_sisisi_nac_sat_lh<string opc, Intrinsic IntID>
1518   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1519                                         IntRegs:$src2),
1520                !strconcat("$dst -= ", !strconcat(opc ,
1521                                                  "($src1.L, $src2.H):sat")),
1522                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1523                                           IntRegs:$src2))],
1524                "$dst2 = $dst">;
1525
1526 class si_MInst_sisisi_nac_sat_ll_s1<string opc, Intrinsic IntID>
1527   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1528                                         IntRegs:$src2),
1529                !strconcat("$dst -= ", !strconcat(opc ,
1530                                                  "($src1.L, $src2.L):<<1:sat")),
1531                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1532                                           IntRegs:$src2))],
1533                "$dst2 = $dst">;
1534
1535 class si_MInst_sisisi_nac_sat_ll<string opc, Intrinsic IntID>
1536   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1537                                         IntRegs:$src2),
1538                !strconcat("$dst -= ", !strconcat(opc ,
1539                                                  "($src1.L, $src2.L):sat")),
1540                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1541                                           IntRegs:$src2))],
1542                "$dst2 = $dst">;
1543
1544 class si_MInst_sisisi_nac_hh_s1<string opc, Intrinsic IntID>
1545   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1546                                         IntRegs:$src2),
1547                !strconcat("$dst -= ", !strconcat(opc ,
1548                                                  "($src1.H, $src2.H):<<1")),
1549                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1550                                           IntRegs:$src2))],
1551                "$dst2 = $dst">;
1552
1553 class si_MInst_sisisi_acc_hl<string opc, Intrinsic IntID>
1554   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1555                                         IntRegs:$src2),
1556                !strconcat("$dst += ", !strconcat(opc , "($src1.H, $src2.L)")),
1557                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1558                                           IntRegs:$src2))],
1559                "$dst2 = $dst">;
1560
1561 class si_MInst_sisisi_acc_hl_s1<string opc, Intrinsic IntID>
1562   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1563                                         IntRegs:$src2),
1564                !strconcat("$dst += ", !strconcat(opc ,
1565                                                  "($src1.H, $src2.L):<<1")),
1566                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1567                                           IntRegs:$src2))],
1568                "$dst2 = $dst">;
1569
1570 class si_MInst_sisisi_nac_hl<string opc, Intrinsic IntID>
1571   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1572                                         IntRegs:$src2),
1573                !strconcat("$dst -= ", !strconcat(opc , "($src1.H, $src2.L)")),
1574                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1575                                           IntRegs:$src2))],
1576                "$dst2 = $dst">;
1577
1578 class si_MInst_sisisi_nac_hl_s1<string opc, Intrinsic IntID>
1579   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1580                                         IntRegs:$src2),
1581                !strconcat("$dst -= ", !strconcat(opc ,
1582                                                  "($src1.H, $src2.L):<<1")),
1583                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1584                                           IntRegs:$src2))],
1585                "$dst2 = $dst">;
1586
1587 class si_MInst_sisisi_acc_lh<string opc, Intrinsic IntID>
1588   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1589                                         IntRegs:$src2),
1590                !strconcat("$dst += ", !strconcat(opc , "($src1.L, $src2.H)")),
1591                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1592                                           IntRegs:$src2))],
1593                "$dst2 = $dst">;
1594
1595 class si_MInst_sisisi_acc_lh_s1<string opc, Intrinsic IntID>
1596   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1597                                         IntRegs:$src2),
1598                !strconcat("$dst += ", !strconcat(opc ,
1599                                                  "($src1.L, $src2.H):<<1")),
1600                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1601                                           IntRegs:$src2))],
1602                "$dst2 = $dst">;
1603
1604 class si_MInst_sisisi_nac_lh<string opc, Intrinsic IntID>
1605   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1606                                         IntRegs:$src2),
1607                !strconcat("$dst -= ", !strconcat(opc , "($src1.L, $src2.H)")),
1608                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1609                                           IntRegs:$src2))],
1610                "$dst2 = $dst">;
1611
1612 class si_MInst_sisisi_nac_lh_s1<string opc, Intrinsic IntID>
1613   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1614                                         IntRegs:$src2),
1615                !strconcat("$dst -= ", !strconcat(opc ,
1616                                                  "($src1.L, $src2.H):<<1")),
1617                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1618                                           IntRegs:$src2))],
1619                "$dst2 = $dst">;
1620
1621 class si_MInst_sisisi_acc_ll<string opc, Intrinsic IntID>
1622   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1623                                         IntRegs:$src2),
1624                !strconcat("$dst += ", !strconcat(opc , "($src1.L, $src2.L)")),
1625                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1626                                           IntRegs:$src2))],
1627                "$dst2 = $dst">;
1628
1629 class si_MInst_sisisi_acc_ll_s1<string opc, Intrinsic IntID>
1630   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1631                                         IntRegs:$src2),
1632                !strconcat("$dst += ", !strconcat(opc ,
1633                                                  "($src1.L, $src2.L):<<1")),
1634                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1635                                           IntRegs:$src2))],
1636                "$dst2 = $dst">;
1637
1638 class si_MInst_sisisi_acc_sat_ll_s1<string opc, Intrinsic IntID>
1639   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1640                                         IntRegs:$src2),
1641                !strconcat("$dst += ", !strconcat(opc ,
1642                                                  "($src1.L, $src2.L):<<1:sat")),
1643                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1644                                           IntRegs:$src2))],
1645                "$dst2 = $dst">;
1646
1647 class si_MInst_sisisi_acc_sat_hl_s1<string opc, Intrinsic IntID>
1648   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1649                                         IntRegs:$src2),
1650                !strconcat("$dst += ", !strconcat(opc ,
1651                                                  "($src1.H, $src2.L):<<1:sat")),
1652                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1653                                           IntRegs:$src2))],
1654                "$dst2 = $dst">;
1655
1656 class si_MInst_sisisi_acc_sat_ll<string opc, Intrinsic IntID>
1657   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1658                                         IntRegs:$src2),
1659                !strconcat("$dst += ", !strconcat(opc ,
1660                                                  "($src1.L, $src2.L):sat")),
1661                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1662                                           IntRegs:$src2))],
1663                "$dst2 = $dst">;
1664
1665 class si_MInst_sisisi_acc_sat_hl<string opc, Intrinsic IntID>
1666   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1667                                         IntRegs:$src2),
1668                !strconcat("$dst += ", !strconcat(opc ,
1669                                                  "($src1.H, $src2.L):sat")),
1670                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1671                                           IntRegs:$src2))],
1672                "$dst2 = $dst">;
1673
1674 class si_MInst_sisisi_nac_ll<string opc, Intrinsic IntID>
1675   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1676                                         IntRegs:$src2),
1677                !strconcat("$dst -= ", !strconcat(opc , "($src1.L, $src2.L)")),
1678                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1679                                           IntRegs:$src2))],
1680                "$dst2 = $dst">;
1681
1682 class si_MInst_sisisi_nac_ll_s1<string opc, Intrinsic IntID>
1683   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1684                                         IntRegs:$src2),
1685                !strconcat("$dst -= ", !strconcat(opc ,
1686                                                  "($src1.L, $src2.L):<<1")),
1687                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1688                                           IntRegs:$src2))],
1689                "$dst2 = $dst">;
1690
1691 class si_MInst_sisisi_nac_hh_sat<string opc, Intrinsic IntID>
1692   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1693                                         IntRegs:$src2),
1694                !strconcat("$dst -= ", !strconcat(opc ,
1695                                                  "($src1.H, $src2.H):sat")),
1696                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1697                                           IntRegs:$src2))],
1698                "$dst2 = $dst">;
1699
1700 class si_MInst_sisisi_nac_hh_s1_sat<string opc, Intrinsic IntID>
1701   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1702                                         IntRegs:$src2),
1703                !strconcat("$dst -= ", !strconcat(opc ,
1704                                                  "($src1.H, $src2.H):<<1:sat")),
1705                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1706                                           IntRegs:$src2))],
1707                "$dst2 = $dst">;
1708
1709 class si_MInst_sisisi_nac_hl_sat<string opc, Intrinsic IntID>
1710   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1711                                         IntRegs:$src2),
1712                !strconcat("$dst -= ", !strconcat(opc ,
1713                                                  "($src1.H, $src2.L):sat")),
1714                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1715                                           IntRegs:$src2))],
1716                "$dst2 = $dst">;
1717
1718 class si_MInst_sisisi_nac_hl_s1_sat<string opc, Intrinsic IntID>
1719   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1720                                         IntRegs:$src2),
1721                !strconcat("$dst -= ", !strconcat(opc ,
1722                                                  "($src1.H, $src2.L):<<1:sat")),
1723                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1724                                           IntRegs:$src2))],
1725                "$dst2 = $dst">;
1726
1727 class si_MInst_sisisi_nac_lh_sat<string opc, Intrinsic IntID>
1728   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1729                                         IntRegs:$src2),
1730                !strconcat("$dst -= ", !strconcat(opc ,
1731                                                  "($src1.L, $src2.H):sat")),
1732                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1733                                           IntRegs:$src2))],
1734                "$dst2 = $dst">;
1735
1736 class si_MInst_sisisi_nac_lh_s1_sat<string opc, Intrinsic IntID>
1737   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1738                                         IntRegs:$src2),
1739                !strconcat("$dst -= ", !strconcat(opc ,
1740                                                  "($src1.L, $src2.H):<<1:sat")),
1741                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1742                                           IntRegs:$src2))],
1743                "$dst2 = $dst">;
1744
1745 class si_MInst_sisisi_nac_ll_sat<string opc, Intrinsic IntID>
1746   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1747                                         IntRegs:$src2),
1748                !strconcat("$dst -= ", !strconcat(opc ,
1749                                                  "($src1.L, $src2.L):sat")),
1750                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1751                                           IntRegs:$src2))],
1752                "$dst2 = $dst">;
1753
1754 class si_MInst_sisisi_nac_ll_s1_sat<string opc, Intrinsic IntID>
1755   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1756                                         IntRegs:$src2),
1757                !strconcat("$dst -= ", !strconcat(opc ,
1758                                                  "($src1.L, $src2.L):<<1:sat")),
1759                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1760                                           IntRegs:$src2))],
1761                "$dst2 = $dst">;
1762
1763 class di_ALU32_sisi<string opc, Intrinsic IntID>
1764   : ALU32_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1765              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
1766              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1767
1768 class di_MInst_sisi<string opc, Intrinsic IntID>
1769   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1770              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
1771              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1772
1773 class di_MInst_sisi_sat<string opc, Intrinsic IntID>
1774   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1775              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):sat")),
1776              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1777
1778 class di_MInst_sisi_sat_conj<string opc, Intrinsic IntID>
1779   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1780              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2*):sat")),
1781              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1782
1783 class di_MInst_sisi_s1_sat<string opc, Intrinsic IntID>
1784   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1785              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):<<1:sat")),
1786              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1787
1788 class di_MInst_didi_s1_sat<string opc, Intrinsic IntID>
1789   : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1790              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):<<1:sat")),
1791              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
1792                                            DoubleRegs:$src2))]>;
1793
1794 class si_MInst_didi_s1_rnd_sat<string opc, Intrinsic IntID>
1795   : MInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1796              !strconcat("$dst = ", !strconcat(opc ,
1797                                               "($src1, $src2):<<1:rnd:sat")),
1798              [(set IntRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
1799
1800 class si_MInst_didi_rnd_sat<string opc, Intrinsic IntID>
1801   : MInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1802              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):rnd:sat")),
1803              [(set IntRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
1804
1805 class si_MInst_sisi_sat_hh<string opc, Intrinsic IntID>
1806   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1807              !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.H):sat")),
1808              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1809
1810 class si_MInst_sisi_sat_hh_s1<string opc, Intrinsic IntID>
1811   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1812                !strconcat("$dst = ", !strconcat(opc ,
1813                                                 "($src1.H, $src2.H):<<1:sat")),
1814                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1815
1816 class si_MInst_sisi_sat_hl<string opc, Intrinsic IntID>
1817   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1818              !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.L):sat")),
1819              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1820
1821 class si_MInst_sisi_sat_hl_s1<string opc, Intrinsic IntID>
1822   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1823                !strconcat("$dst = ", !strconcat(opc ,
1824                                                 "($src1.H, $src2.L):<<1:sat")),
1825                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1826
1827 class si_MInst_sisi_sat_lh<string opc, Intrinsic IntID>
1828   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1829              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H):sat")),
1830              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1831
1832 class si_MInst_sisi_sat_lh_s1<string opc, Intrinsic IntID>
1833   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1834                !strconcat("$dst = ", !strconcat(opc ,
1835                                                 "($src1.L, $src2.H):<<1:sat")),
1836                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1837
1838 class si_MInst_sisi_sat_ll<string opc, Intrinsic IntID>
1839   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1840              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L):sat")),
1841              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1842
1843 class si_MInst_sisi_sat_ll_s1<string opc, Intrinsic IntID>
1844   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1845                !strconcat("$dst = ", !strconcat(opc ,
1846                                                 "($src1.L, $src2.L):<<1:sat")),
1847                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1848
1849 class si_MInst_sisi_sat_rnd_hh<string opc, Intrinsic IntID>
1850   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1851                !strconcat("$dst = ", !strconcat(opc ,
1852                                                 "($src1.H, $src2.H):rnd:sat")),
1853                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1854
1855 class si_MInst_sisi_rnd_hh<string opc, Intrinsic IntID>
1856   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1857                !strconcat("$dst = ", !strconcat(opc ,
1858                                                 "($src1.H, $src2.H):rnd")),
1859                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1860
1861 class si_MInst_sisi_rnd_hh_s1<string opc, Intrinsic IntID>
1862   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1863                !strconcat("$dst = ", !strconcat(opc ,
1864                                                 "($src1.H, $src2.H):<<1:rnd")),
1865                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1866
1867 class si_MInst_sisi_sat_rnd_hh_s1<string opc, Intrinsic IntID>
1868   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1869                !strconcat("$dst = ",
1870                           !strconcat(opc ,
1871                                      "($src1.H, $src2.H):<<1:rnd:sat")),
1872                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1873
1874 class si_MInst_sisi_rnd_hl<string opc, Intrinsic IntID>
1875   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1876                !strconcat("$dst = ",
1877                           !strconcat(opc , "($src1.H, $src2.L):rnd")),
1878                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1879
1880 class si_MInst_sisi_rnd_hl_s1<string opc, Intrinsic IntID>
1881   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1882                !strconcat("$dst = ",
1883                           !strconcat(opc , "($src1.H, $src2.L):<<1:rnd")),
1884                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1885
1886 class si_MInst_sisi_sat_rnd_hl<string opc, Intrinsic IntID>
1887   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1888                !strconcat("$dst = ",
1889                           !strconcat(opc , "($src1.H, $src2.L):rnd:sat")),
1890                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1891
1892 class si_MInst_sisi_sat_rnd_hl_s1<string opc, Intrinsic IntID>
1893   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1894                !strconcat("$dst = ",
1895                           !strconcat(opc , "($src1.H, $src2.L):<<1:rnd:sat")),
1896                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1897
1898 class si_MInst_sisi_rnd_lh<string opc, Intrinsic IntID>
1899   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1900                !strconcat("$dst = ",
1901                           !strconcat(opc , "($src1.L, $src2.H):rnd")),
1902                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1903
1904 class si_MInst_sisi_sat_rnd_lh<string opc, Intrinsic IntID>
1905   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1906                !strconcat("$dst = ",
1907                           !strconcat(opc , "($src1.L, $src2.H):rnd:sat")),
1908                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1909
1910 class si_MInst_sisi_sat_rnd_lh_s1<string opc, Intrinsic IntID>
1911   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1912                !strconcat("$dst = ",
1913                           !strconcat(opc , "($src1.L, $src2.H):<<1:rnd:sat")),
1914                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1915
1916 class si_MInst_sisi_rnd_lh_s1<string opc, Intrinsic IntID>
1917   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1918                !strconcat("$dst = ",
1919                           !strconcat(opc , "($src1.L, $src2.H):<<1:rnd")),
1920                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1921
1922 class si_MInst_sisi_sat_rnd_ll<string opc, Intrinsic IntID>
1923   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1924                !strconcat("$dst = ",
1925                           !strconcat(opc , "($src1.L, $src2.L):rnd:sat")),
1926                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1927
1928 class si_MInst_sisi_sat_rnd_ll_s1<string opc, Intrinsic IntID>
1929   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1930                !strconcat("$dst = ",
1931                           !strconcat(opc , "($src1.L, $src2.L):<<1:rnd:sat")),
1932                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1933
1934 class si_MInst_sisi_rnd_ll<string opc, Intrinsic IntID>
1935   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1936                !strconcat("$dst = ",
1937                           !strconcat(opc , "($src1.L, $src2.L):rnd")),
1938                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1939
1940 class si_MInst_sisi_rnd_ll_s1<string opc, Intrinsic IntID>
1941   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1942                !strconcat("$dst = ",
1943                           !strconcat(opc , "($src1.L, $src2.L):<<1:rnd")),
1944                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1945
1946 class di_MInst_dididi_acc_sat<string opc, Intrinsic IntID>
1947   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2,
1948                                            DoubleRegs:$src1, DoubleRegs:$src2),
1949                !strconcat("$dst += ", !strconcat(opc , "($src1, $src2):sat")),
1950                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
1951                                              DoubleRegs:$src1,
1952                                              DoubleRegs:$src2))],
1953                "$dst2 = $dst">;
1954
1955 class di_MInst_dididi_acc_rnd_sat<string opc, Intrinsic IntID>
1956   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
1957                                            DoubleRegs:$src2),
1958                !strconcat("$dst += ",
1959                           !strconcat(opc , "($src1, $src2):rnd:sat")),
1960                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
1961                                              DoubleRegs:$src1,
1962                                              DoubleRegs:$src2))],
1963                "$dst2 = $dst">;
1964
1965 class di_MInst_dididi_acc_s1<string opc, Intrinsic IntID>
1966   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2,
1967                                            DoubleRegs:$src1,
1968                                            DoubleRegs:$src2),
1969                !strconcat("$dst += ",
1970                           !strconcat(opc , "($src1, $src2):<<1")),
1971                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
1972                                              DoubleRegs:$src1,
1973                                              DoubleRegs:$src2))],
1974                "$dst2 = $dst">;
1975
1976
1977 class di_MInst_dididi_acc_s1_sat<string opc, Intrinsic IntID>
1978   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2,
1979                                            DoubleRegs:$src1,
1980                                            DoubleRegs:$src2),
1981                !strconcat("$dst += ",
1982                           !strconcat(opc , "($src1, $src2):<<1:sat")),
1983                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
1984                                              DoubleRegs:$src1,
1985                                              DoubleRegs:$src2))],
1986                "$dst2 = $dst">;
1987
1988 class di_MInst_dididi_acc_s1_rnd_sat<string opc, Intrinsic IntID>
1989   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
1990                                            DoubleRegs:$src2),
1991                !strconcat("$dst += ",
1992                           !strconcat(opc , "($src1, $src2):<<1:rnd:sat")),
1993                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
1994                                              DoubleRegs:$src1,
1995                                              DoubleRegs:$src2))],
1996                "$dst2 = $dst">;
1997
1998 class di_MInst_dididi_acc<string opc, Intrinsic IntID>
1999   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
2000                                            DoubleRegs:$src2),
2001                !strconcat("$dst += ", !strconcat(opc , "($src1, $src2)")),
2002                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
2003                                              DoubleRegs:$src1,
2004                                              DoubleRegs:$src2))],
2005                "$dst2 = $dst">;
2006
2007 class di_MInst_dididi_acc_conj<string opc, Intrinsic IntID>
2008   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
2009                                            DoubleRegs:$src2),
2010                !strconcat("$dst += ", !strconcat(opc , "($src1, $src2*)")),
2011                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
2012                                              DoubleRegs:$src1,
2013                                              DoubleRegs:$src2))],
2014                "$dst2 = $dst">;
2015
2016 class di_MInst_disisi_acc_hh<string opc, Intrinsic IntID>
2017   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
2018                                            IntRegs:$src2),
2019                !strconcat("$dst += ", !strconcat(opc , "($src1.H, $src2.H)")),
2020                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
2021                                              IntRegs:$src2))],
2022                "$dst2 = $dst">;
2023
2024 class di_MInst_disisi_acc_hl<string opc, Intrinsic IntID>
2025   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
2026                                            IntRegs:$src2),
2027                !strconcat("$dst += ", !strconcat(opc , "($src1.H, $src2.L)")),
2028                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
2029                                              IntRegs:$src2))],
2030                "$dst2 = $dst">;
2031
2032 class di_MInst_disisi_acc_lh<string opc, Intrinsic IntID>
2033   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
2034                                            IntRegs:$src2),
2035                !strconcat("$dst += ", !strconcat(opc , "($src1.L, $src2.H)")),
2036                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
2037                                              IntRegs:$src2))],
2038                "$dst2 = $dst">;
2039
2040 class di_MInst_disisi_acc_ll<string opc, Intrinsic IntID>
2041   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
2042                                            IntRegs:$src2),
2043                !strconcat("$dst += ", !strconcat(opc , "($src1.L, $src2.L)")),
2044                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
2045                                              IntRegs:$src2))],
2046                "$dst2 = $dst">;
2047
2048 class di_MInst_disisi_acc_hh_s1<string opc, Intrinsic IntID>
2049   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
2050                                            IntRegs:$src2),
2051                !strconcat("$dst += ",
2052                           !strconcat(opc , "($src1.H, $src2.H):<<1")),
2053                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
2054                                              IntRegs:$src2))],
2055                "$dst2 = $dst">;
2056
2057 class di_MInst_disisi_acc_hl_s1<string opc, Intrinsic IntID>
2058   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
2059                                            IntRegs:$src2),
2060                !strconcat("$dst += ",
2061                           !strconcat(opc , "($src1.H, $src2.L):<<1")),
2062                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
2063                                              IntRegs:$src2))],
2064                "$dst2 = $dst">;
2065
2066 class di_MInst_disisi_acc_lh_s1<string opc, Intrinsic IntID>
2067   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
2068                                            IntRegs:$src2),
2069                !strconcat("$dst += ",
2070                           !strconcat(opc , "($src1.L, $src2.H):<<1")),
2071                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
2072                                              IntRegs:$src2))],
2073                "$dst2 = $dst">;
2074
2075 class di_MInst_disisi_acc_ll_s1<string opc, Intrinsic IntID>
2076   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
2077                                            IntRegs:$src2),
2078                !strconcat("$dst += ",
2079                           !strconcat(opc , "($src1.L, $src2.L):<<1")),
2080                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
2081                                              IntRegs:$src2))],
2082                "$dst2 = $dst">;
2083
2084 class di_MInst_disisi_nac_hh<string opc, Intrinsic IntID>
2085   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
2086                                            IntRegs:$src2),
2087                !strconcat("$dst -= ", !strconcat(opc , "($src1.H, $src2.H)")),
2088                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
2089                                              IntRegs:$src2))],
2090                "$dst2 = $dst">;
2091
2092 class di_MInst_disisi_nac_hl<string opc, Intrinsic IntID>
2093   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
2094                                            IntRegs:$src2),
2095                !strconcat("$dst -= ", !strconcat(opc , "($src1.H, $src2.L)")),
2096                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
2097                                              IntRegs:$src2))],
2098                "$dst2 = $dst">;
2099
2100 class di_MInst_disisi_nac_lh<string opc, Intrinsic IntID>
2101   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
2102                                            IntRegs:$src2),
2103                !strconcat("$dst -= ", !strconcat(opc , "($src1.L, $src2.H)")),
2104                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
2105                                              IntRegs:$src2))],
2106                "$dst2 = $dst">;
2107
2108 class di_MInst_disisi_nac_ll<string opc, Intrinsic IntID>
2109   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
2110                                            IntRegs:$src2),
2111                !strconcat("$dst -= ", !strconcat(opc , "($src1.L, $src2.L)")),
2112                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
2113                                              IntRegs:$src2))],
2114                "$dst2 = $dst">;
2115
2116 class di_MInst_disisi_nac_hh_s1<string opc, Intrinsic IntID>
2117   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
2118                                            IntRegs:$src2),
2119                !strconcat("$dst -= ",
2120                           !strconcat(opc , "($src1.H, $src2.H):<<1")),
2121                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
2122                                              IntRegs:$src2))],
2123                "$dst2 = $dst">;
2124
2125 class di_MInst_disisi_nac_hl_s1<string opc, Intrinsic IntID>
2126   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
2127                                            IntRegs:$src2),
2128                !strconcat("$dst -= ",
2129                           !strconcat(opc , "($src1.H, $src2.L):<<1")),
2130                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
2131                                              IntRegs:$src2))],
2132                "$dst2 = $dst">;
2133
2134 class di_MInst_disisi_nac_lh_s1<string opc, Intrinsic IntID>
2135   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
2136                                            IntRegs:$src2),
2137                !strconcat("$dst -= ",
2138                           !strconcat(opc , "($src1.L, $src2.H):<<1")),
2139                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
2140                                              IntRegs:$src2))],
2141                "$dst2 = $dst">;
2142
2143 class di_MInst_disisi_nac_ll_s1<string opc, Intrinsic IntID>
2144   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
2145                                            IntRegs:$src2),
2146                !strconcat("$dst -= ",
2147                           !strconcat(opc , "($src1.L, $src2.L):<<1")),
2148                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
2149                                              IntRegs:$src2))],
2150                "$dst2 = $dst">;
2151
2152 class di_MInst_disisi_acc_s1_sat<string opc, Intrinsic IntID>
2153   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
2154                                            IntRegs:$src2),
2155                !strconcat("$dst += ",
2156                           !strconcat(opc , "($src1, $src2):<<1:sat")),
2157                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
2158                                              IntRegs:$src2))],
2159                "$dst2 = $dst">;
2160
2161 class di_MInst_disi_s1_sat<string opc, Intrinsic IntID>
2162   : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
2163              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):<<1:sat")),
2164              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, IntRegs:$src2))]>;
2165
2166 class di_MInst_didisi_acc_s1_sat<string opc, Intrinsic IntID>
2167   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
2168                                            IntRegs:$src2),
2169                !strconcat("$dst += ",
2170                           !strconcat(opc , "($src1, $src2):<<1:sat")),
2171                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
2172                                              DoubleRegs:$src1,
2173                                              IntRegs:$src2))],
2174                "$dst2 = $dst">;
2175
2176 class si_MInst_disi_s1_rnd_sat<string opc, Intrinsic IntID>
2177   : MInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
2178              !strconcat("$dst = ",
2179                         !strconcat(opc , "($src1, $src2):<<1:rnd:sat")),
2180              [(set IntRegs:$dst, (IntID DoubleRegs:$src1, IntRegs:$src2))]>;
2181
2182 class si_MInst_didi<string opc, Intrinsic IntID>
2183   : MInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
2184              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
2185              [(set IntRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
2186
2187 //
2188 // LDInst classes.
2189 //
2190 let mayLoad = 1, hasSideEffects = 0 in
2191 class di_LDInstPI_diu4<string opc, Intrinsic IntID>
2192   : LDInstPI<(outs IntRegs:$dst, DoubleRegs:$dst2),
2193            (ins IntRegs:$src1, IntRegs:$src2, CtrRegs:$src3, s4Imm:$offset),
2194            "$dst2 = memd($src1++#$offset:circ($src3))",
2195            [],
2196            "$src1 = $dst">;
2197
2198 /********************************************************************
2199 *            ALU32/PERM                                             *
2200 *********************************************************************/
2201
2202 // ALU32 / PERM / Combine.
2203 def HEXAGON_A2_combinew:
2204   di_ALU32_sisi                   <"combine",  int_hexagon_A2_combinew>;
2205 def HEXAGON_A2_combine_hh:
2206   si_MInst_sisi_hh                <"combine",  int_hexagon_A2_combine_hh>;
2207 def HEXAGON_A2_combine_lh:
2208   si_MInst_sisi_lh                <"combine",  int_hexagon_A2_combine_lh>;
2209 def HEXAGON_A2_combine_hl:
2210   si_MInst_sisi_hl                <"combine",  int_hexagon_A2_combine_hl>;
2211 def HEXAGON_A2_combine_ll:
2212   si_MInst_sisi_ll                <"combine",  int_hexagon_A2_combine_ll>;
2213 def HEXAGON_A2_combineii:
2214   di_MInst_s8s8                   <"combine",  int_hexagon_A2_combineii>;
2215
2216 // ALU32 / PERM / Mux.
2217 def HEXAGON_C2_mux:
2218   si_ALU32_qisisi                 <"mux",      int_hexagon_C2_mux>;
2219
2220 // ALU32 / PERM / Shift halfword.
2221 def HEXAGON_A2_aslh:
2222   si_ALU32_si                     <"aslh",     int_hexagon_A2_aslh>;
2223 def HEXAGON_A2_asrh:
2224   si_ALU32_si                     <"asrh",     int_hexagon_A2_asrh>;
2225 def SI_to_SXTHI_asrh:
2226   si_ALU32_si                     <"asrh",     int_hexagon_SI_to_SXTHI_asrh>;
2227
2228 // ALU32 / PERM / Sign/zero extend.
2229 def HEXAGON_A2_sxth:
2230   si_ALU32_si                     <"sxth",     int_hexagon_A2_sxth>;
2231 def HEXAGON_A2_sxtb:
2232   si_ALU32_si                     <"sxtb",     int_hexagon_A2_sxtb>;
2233 def HEXAGON_A2_zxth:
2234   si_ALU32_si                     <"zxth",     int_hexagon_A2_zxth>;
2235 def HEXAGON_A2_zxtb:
2236   si_ALU32_si                     <"zxtb",     int_hexagon_A2_zxtb>;
2237
2238 /********************************************************************
2239 *            ALU32/PRED                                             *
2240 *********************************************************************/
2241
2242 // ALU32 / PRED / Compare.
2243 def HEXAGON_C2_cmpeq:
2244   qi_ALU32_sisi                   <"cmp.eq",   int_hexagon_C2_cmpeq>;
2245 def HEXAGON_C2_cmpeqi:
2246   qi_ALU32_sis10                  <"cmp.eq",   int_hexagon_C2_cmpeqi>;
2247 def HEXAGON_C2_cmpgei:
2248   qi_ALU32_sis8                   <"cmp.ge",   int_hexagon_C2_cmpgei>;
2249 def HEXAGON_C2_cmpgeui:
2250   qi_ALU32_siu8                   <"cmp.geu",  int_hexagon_C2_cmpgeui>;
2251 def HEXAGON_C2_cmpgt:
2252   qi_ALU32_sisi                   <"cmp.gt",   int_hexagon_C2_cmpgt>;
2253 def HEXAGON_C2_cmpgti:
2254   qi_ALU32_sis10                  <"cmp.gt",   int_hexagon_C2_cmpgti>;
2255 def HEXAGON_C2_cmpgtu:
2256   qi_ALU32_sisi                   <"cmp.gtu",  int_hexagon_C2_cmpgtu>;
2257 def HEXAGON_C2_cmpgtui:
2258   qi_ALU32_siu9                   <"cmp.gtu",  int_hexagon_C2_cmpgtui>;
2259 def HEXAGON_C2_cmplt:
2260   qi_ALU32_sisi                   <"cmp.lt",   int_hexagon_C2_cmplt>;
2261 def HEXAGON_C2_cmpltu:
2262   qi_ALU32_sisi                   <"cmp.ltu",  int_hexagon_C2_cmpltu>;
2263
2264 /********************************************************************
2265 *            ALU32/VH                                               *
2266 *********************************************************************/
2267
2268 // ALU32 / VH / Vector add halfwords.
2269 // Rd32=vadd[u]h(Rs32,Rt32:sat]
2270 def HEXAGON_A2_svaddh:
2271   si_ALU32_sisi                   <"vaddh",    int_hexagon_A2_svaddh>;
2272 def HEXAGON_A2_svaddhs:
2273   si_ALU32_sisi_sat               <"vaddh",    int_hexagon_A2_svaddhs>;
2274 def HEXAGON_A2_svadduhs:
2275   si_ALU32_sisi_sat               <"vadduh",   int_hexagon_A2_svadduhs>;
2276
2277 // ALU32 / VH / Vector average halfwords.
2278 def HEXAGON_A2_svavgh:
2279   si_ALU32_sisi                   <"vavgh",    int_hexagon_A2_svavgh>;
2280 def HEXAGON_A2_svavghs:
2281   si_ALU32_sisi_rnd               <"vavgh",    int_hexagon_A2_svavghs>;
2282 def HEXAGON_A2_svnavgh:
2283   si_ALU32_sisi                   <"vnavgh",   int_hexagon_A2_svnavgh>;
2284
2285 // ALU32 / VH / Vector subtract halfwords.
2286 def HEXAGON_A2_svsubh:
2287   si_ALU32_sisi                   <"vsubh",    int_hexagon_A2_svsubh>;
2288 def HEXAGON_A2_svsubhs:
2289   si_ALU32_sisi_sat               <"vsubh",    int_hexagon_A2_svsubhs>;
2290 def HEXAGON_A2_svsubuhs:
2291   si_ALU32_sisi_sat               <"vsubuh",   int_hexagon_A2_svsubuhs>;
2292
2293 /********************************************************************
2294 *            ALU64/ALU                                              *
2295 *********************************************************************/
2296
2297 // ALU64 / ALU / Add.
2298 def HEXAGON_A2_addp:
2299   di_ALU64_didi                   <"add",      int_hexagon_A2_addp>;
2300 def HEXAGON_A2_addsat:
2301   si_ALU64_sisi_sat               <"add",      int_hexagon_A2_addsat>;
2302
2303 // ALU64 / ALU / Add halfword.
2304 // Even though the definition says hl, it should be lh -
2305 //so DON'T change the class " si_ALU64_sisi_l16_lh " it inherits.
2306 def HEXAGON_A2_addh_l16_hl:
2307   si_ALU64_sisi_l16_lh            <"add",      int_hexagon_A2_addh_l16_hl>;
2308 def HEXAGON_A2_addh_l16_ll:
2309   si_ALU64_sisi_l16_ll            <"add",      int_hexagon_A2_addh_l16_ll>;
2310
2311 def HEXAGON_A2_addh_l16_sat_hl:
2312   si_ALU64_sisi_l16_sat_lh        <"add",      int_hexagon_A2_addh_l16_sat_hl>;
2313 def HEXAGON_A2_addh_l16_sat_ll:
2314   si_ALU64_sisi_l16_sat_ll        <"add",      int_hexagon_A2_addh_l16_sat_ll>;
2315
2316 def HEXAGON_A2_addh_h16_hh:
2317   si_ALU64_sisi_h16_hh            <"add",      int_hexagon_A2_addh_h16_hh>;
2318 def HEXAGON_A2_addh_h16_hl:
2319   si_ALU64_sisi_h16_hl            <"add",      int_hexagon_A2_addh_h16_hl>;
2320 def HEXAGON_A2_addh_h16_lh:
2321   si_ALU64_sisi_h16_lh            <"add",      int_hexagon_A2_addh_h16_lh>;
2322 def HEXAGON_A2_addh_h16_ll:
2323   si_ALU64_sisi_h16_ll            <"add",      int_hexagon_A2_addh_h16_ll>;
2324
2325 def HEXAGON_A2_addh_h16_sat_hh:
2326   si_ALU64_sisi_h16_sat_hh        <"add",      int_hexagon_A2_addh_h16_sat_hh>;
2327 def HEXAGON_A2_addh_h16_sat_hl:
2328   si_ALU64_sisi_h16_sat_hl        <"add",      int_hexagon_A2_addh_h16_sat_hl>;
2329 def HEXAGON_A2_addh_h16_sat_lh:
2330   si_ALU64_sisi_h16_sat_lh        <"add",      int_hexagon_A2_addh_h16_sat_lh>;
2331 def HEXAGON_A2_addh_h16_sat_ll:
2332   si_ALU64_sisi_h16_sat_ll        <"add",      int_hexagon_A2_addh_h16_sat_ll>;
2333
2334 // ALU64 / ALU / Compare.
2335 def HEXAGON_C2_cmpeqp:
2336   qi_ALU64_didi                   <"cmp.eq",   int_hexagon_C2_cmpeqp>;
2337 def HEXAGON_C2_cmpgtp:
2338   qi_ALU64_didi                   <"cmp.gt",   int_hexagon_C2_cmpgtp>;
2339 def HEXAGON_C2_cmpgtup:
2340   qi_ALU64_didi                   <"cmp.gtu",  int_hexagon_C2_cmpgtup>;
2341
2342 // ALU64 / ALU / Logical operations.
2343 def HEXAGON_A2_andp:
2344   di_ALU64_didi                   <"and",      int_hexagon_A2_andp>;
2345 def HEXAGON_A2_orp:
2346   di_ALU64_didi                   <"or",       int_hexagon_A2_orp>;
2347 def HEXAGON_A2_xorp:
2348   di_ALU64_didi                   <"xor",      int_hexagon_A2_xorp>;
2349
2350 // ALU64 / ALU / Maximum.
2351 def HEXAGON_A2_max:
2352   si_ALU64_sisi                   <"max",      int_hexagon_A2_max>;
2353 def HEXAGON_A2_maxu:
2354   si_ALU64_sisi                   <"maxu",     int_hexagon_A2_maxu>;
2355
2356 // ALU64 / ALU / Minimum.
2357 def HEXAGON_A2_min:
2358   si_ALU64_sisi                   <"min",      int_hexagon_A2_min>;
2359 def HEXAGON_A2_minu:
2360   si_ALU64_sisi                   <"minu",     int_hexagon_A2_minu>;
2361
2362 // ALU64 / ALU / Subtract.
2363 def HEXAGON_A2_subp:
2364   di_ALU64_didi                   <"sub",      int_hexagon_A2_subp>;
2365 def HEXAGON_A2_subsat:
2366   si_ALU64_sisi_sat               <"sub",      int_hexagon_A2_subsat>;
2367
2368 // ALU64 / ALU / Subtract halfword.
2369 // Even though the definition says hl, it should be lh -
2370 //so DON'T change the class " si_ALU64_sisi_l16_lh " it inherits.
2371 def HEXAGON_A2_subh_l16_hl:
2372   si_ALU64_sisi_l16_lh            <"sub",      int_hexagon_A2_subh_l16_hl>;
2373 def HEXAGON_A2_subh_l16_ll:
2374   si_ALU64_sisi_l16_ll            <"sub",      int_hexagon_A2_subh_l16_ll>;
2375
2376 def HEXAGON_A2_subh_l16_sat_hl:
2377   si_ALU64_sisi_l16_sat_lh        <"sub",      int_hexagon_A2_subh_l16_sat_hl>;
2378 def HEXAGON_A2_subh_l16_sat_ll:
2379   si_ALU64_sisi_l16_sat_ll        <"sub",      int_hexagon_A2_subh_l16_sat_ll>;
2380
2381 def HEXAGON_A2_subh_h16_hh:
2382   si_ALU64_sisi_h16_hh            <"sub",      int_hexagon_A2_subh_h16_hh>;
2383 def HEXAGON_A2_subh_h16_hl:
2384   si_ALU64_sisi_h16_hl            <"sub",      int_hexagon_A2_subh_h16_hl>;
2385 def HEXAGON_A2_subh_h16_lh:
2386   si_ALU64_sisi_h16_lh            <"sub",      int_hexagon_A2_subh_h16_lh>;
2387 def HEXAGON_A2_subh_h16_ll:
2388   si_ALU64_sisi_h16_ll            <"sub",      int_hexagon_A2_subh_h16_ll>;
2389
2390 def HEXAGON_A2_subh_h16_sat_hh:
2391   si_ALU64_sisi_h16_sat_hh        <"sub",      int_hexagon_A2_subh_h16_sat_hh>;
2392 def HEXAGON_A2_subh_h16_sat_hl:
2393   si_ALU64_sisi_h16_sat_hl        <"sub",      int_hexagon_A2_subh_h16_sat_hl>;
2394 def HEXAGON_A2_subh_h16_sat_lh:
2395   si_ALU64_sisi_h16_sat_lh        <"sub",      int_hexagon_A2_subh_h16_sat_lh>;
2396 def HEXAGON_A2_subh_h16_sat_ll:
2397   si_ALU64_sisi_h16_sat_ll        <"sub",      int_hexagon_A2_subh_h16_sat_ll>;
2398
2399 // ALU64 / ALU / Transfer register.
2400 def HEXAGON_A2_tfrp:
2401   di_ALU64_di                     <"",         int_hexagon_A2_tfrp>;
2402
2403 /********************************************************************
2404 *            ALU64/BIT                                              *
2405 *********************************************************************/
2406
2407 // ALU64 / BIT / Masked parity.
2408 def HEXAGON_S2_parityp:
2409   si_ALU64_didi                   <"parity",   int_hexagon_S2_parityp>;
2410
2411 /********************************************************************
2412 *            ALU64/PERM                                             *
2413 *********************************************************************/
2414
2415 // ALU64 / PERM / Vector pack high and low halfwords.
2416 def HEXAGON_S2_packhl:
2417   di_ALU64_sisi                   <"packhl",   int_hexagon_S2_packhl>;
2418
2419 /********************************************************************
2420 *            ALU64/VB                                               *
2421 *********************************************************************/
2422
2423 // ALU64 / VB / Vector add unsigned bytes.
2424 def HEXAGON_A2_vaddub:
2425   di_ALU64_didi                   <"vaddub",   int_hexagon_A2_vaddub>;
2426 def HEXAGON_A2_vaddubs:
2427   di_ALU64_didi_sat               <"vaddub",   int_hexagon_A2_vaddubs>;
2428
2429 // ALU64 / VB / Vector average unsigned bytes.
2430 def HEXAGON_A2_vavgub:
2431   di_ALU64_didi                   <"vavgub",   int_hexagon_A2_vavgub>;
2432 def HEXAGON_A2_vavgubr:
2433   di_ALU64_didi_rnd               <"vavgub",   int_hexagon_A2_vavgubr>;
2434
2435 // ALU64 / VB / Vector compare unsigned bytes.
2436 def HEXAGON_A2_vcmpbeq:
2437   qi_ALU64_didi                   <"vcmpb.eq", int_hexagon_A2_vcmpbeq>;
2438 def HEXAGON_A2_vcmpbgtu:
2439   qi_ALU64_didi                   <"vcmpb.gtu",int_hexagon_A2_vcmpbgtu>;
2440
2441 // ALU64 / VB / Vector maximum/minimum unsigned bytes.
2442 def HEXAGON_A2_vmaxub:
2443   di_ALU64_didi                   <"vmaxub",   int_hexagon_A2_vmaxub>;
2444 def HEXAGON_A2_vminub:
2445   di_ALU64_didi                   <"vminub",   int_hexagon_A2_vminub>;
2446
2447 // ALU64 / VB / Vector subtract unsigned bytes.
2448 def HEXAGON_A2_vsubub:
2449   di_ALU64_didi                   <"vsubub",   int_hexagon_A2_vsubub>;
2450 def HEXAGON_A2_vsububs:
2451   di_ALU64_didi_sat               <"vsubub",   int_hexagon_A2_vsububs>;
2452
2453 // ALU64 / VB / Vector mux.
2454 def HEXAGON_C2_vmux:
2455   di_ALU64_qididi                 <"vmux",     int_hexagon_C2_vmux>;
2456
2457
2458 /********************************************************************
2459 *            ALU64/VH                                               *
2460 *********************************************************************/
2461
2462 // ALU64 / VH / Vector add halfwords.
2463 // Rdd64=vadd[u]h(Rss64,Rtt64:sat]
2464 def HEXAGON_A2_vaddh:
2465   di_ALU64_didi                   <"vaddh",    int_hexagon_A2_vaddh>;
2466 def HEXAGON_A2_vaddhs:
2467   di_ALU64_didi_sat               <"vaddh",    int_hexagon_A2_vaddhs>;
2468 def HEXAGON_A2_vadduhs:
2469   di_ALU64_didi_sat               <"vadduh",   int_hexagon_A2_vadduhs>;
2470
2471 // ALU64 / VH / Vector average halfwords.
2472 // Rdd64=v[n]avg[u]h(Rss64,Rtt64:rnd/:crnd][:sat]
2473 def HEXAGON_A2_vavgh:
2474   di_ALU64_didi                   <"vavgh",    int_hexagon_A2_vavgh>;
2475 def HEXAGON_A2_vavghcr:
2476   di_ALU64_didi_crnd              <"vavgh",    int_hexagon_A2_vavghcr>;
2477 def HEXAGON_A2_vavghr:
2478   di_ALU64_didi_rnd               <"vavgh",    int_hexagon_A2_vavghr>;
2479 def HEXAGON_A2_vavguh:
2480   di_ALU64_didi                   <"vavguh",   int_hexagon_A2_vavguh>;
2481 def HEXAGON_A2_vavguhr:
2482   di_ALU64_didi_rnd               <"vavguh",   int_hexagon_A2_vavguhr>;
2483 def HEXAGON_A2_vnavgh:
2484   di_ALU64_didi                   <"vnavgh",   int_hexagon_A2_vnavgh>;
2485 def HEXAGON_A2_vnavghcr:
2486   di_ALU64_didi_crnd_sat          <"vnavgh",   int_hexagon_A2_vnavghcr>;
2487 def HEXAGON_A2_vnavghr:
2488   di_ALU64_didi_rnd_sat           <"vnavgh",   int_hexagon_A2_vnavghr>;
2489
2490 // ALU64 / VH / Vector compare halfwords.
2491 def HEXAGON_A2_vcmpheq:
2492   qi_ALU64_didi                   <"vcmph.eq", int_hexagon_A2_vcmpheq>;
2493 def HEXAGON_A2_vcmphgt:
2494   qi_ALU64_didi                   <"vcmph.gt", int_hexagon_A2_vcmphgt>;
2495 def HEXAGON_A2_vcmphgtu:
2496   qi_ALU64_didi                   <"vcmph.gtu",int_hexagon_A2_vcmphgtu>;
2497
2498 // ALU64 / VH / Vector maximum halfwords.
2499 def HEXAGON_A2_vmaxh:
2500   di_ALU64_didi                   <"vmaxh",    int_hexagon_A2_vmaxh>;
2501 def HEXAGON_A2_vmaxuh:
2502   di_ALU64_didi                   <"vmaxuh",   int_hexagon_A2_vmaxuh>;
2503
2504 // ALU64 / VH / Vector minimum halfwords.
2505 def HEXAGON_A2_vminh:
2506   di_ALU64_didi                   <"vminh",    int_hexagon_A2_vminh>;
2507 def HEXAGON_A2_vminuh:
2508   di_ALU64_didi                   <"vminuh",   int_hexagon_A2_vminuh>;
2509
2510 // ALU64 / VH / Vector subtract halfwords.
2511 def HEXAGON_A2_vsubh:
2512   di_ALU64_didi                   <"vsubh",    int_hexagon_A2_vsubh>;
2513 def HEXAGON_A2_vsubhs:
2514   di_ALU64_didi_sat               <"vsubh",    int_hexagon_A2_vsubhs>;
2515 def HEXAGON_A2_vsubuhs:
2516   di_ALU64_didi_sat               <"vsubuh",   int_hexagon_A2_vsubuhs>;
2517
2518
2519 /********************************************************************
2520 *            ALU64/VW                                               *
2521 *********************************************************************/
2522
2523 // ALU64 / VW / Vector add words.
2524 // Rdd32=vaddw(Rss32,Rtt32)[:sat]
2525 def HEXAGON_A2_vaddw:
2526   di_ALU64_didi                   <"vaddw",    int_hexagon_A2_vaddw>;
2527 def HEXAGON_A2_vaddws:
2528   di_ALU64_didi_sat               <"vaddw",   int_hexagon_A2_vaddws>;
2529
2530 // ALU64 / VW / Vector average words.
2531 def HEXAGON_A2_vavguw:
2532   di_ALU64_didi                   <"vavguw",   int_hexagon_A2_vavguw>;
2533 def HEXAGON_A2_vavguwr:
2534   di_ALU64_didi_rnd               <"vavguw",   int_hexagon_A2_vavguwr>;
2535 def HEXAGON_A2_vavgw:
2536   di_ALU64_didi                   <"vavgw",    int_hexagon_A2_vavgw>;
2537 def HEXAGON_A2_vavgwcr:
2538   di_ALU64_didi_crnd              <"vavgw",    int_hexagon_A2_vavgwcr>;
2539 def HEXAGON_A2_vavgwr:
2540   di_ALU64_didi_rnd               <"vavgw",    int_hexagon_A2_vavgwr>;
2541 def HEXAGON_A2_vnavgw:
2542   di_ALU64_didi                   <"vnavgw",   int_hexagon_A2_vnavgw>;
2543 def HEXAGON_A2_vnavgwcr:
2544   di_ALU64_didi_crnd_sat          <"vnavgw",   int_hexagon_A2_vnavgwcr>;
2545 def HEXAGON_A2_vnavgwr:
2546   di_ALU64_didi_rnd_sat           <"vnavgw",   int_hexagon_A2_vnavgwr>;
2547
2548 // ALU64 / VW / Vector compare words.
2549 def HEXAGON_A2_vcmpweq:
2550   qi_ALU64_didi                   <"vcmpw.eq", int_hexagon_A2_vcmpweq>;
2551 def HEXAGON_A2_vcmpwgt:
2552   qi_ALU64_didi                   <"vcmpw.gt", int_hexagon_A2_vcmpwgt>;
2553 def HEXAGON_A2_vcmpwgtu:
2554   qi_ALU64_didi                   <"vcmpw.gtu",int_hexagon_A2_vcmpwgtu>;
2555
2556 // ALU64 / VW / Vector maximum words.
2557 def HEXAGON_A2_vmaxw:
2558   di_ALU64_didi                   <"vmaxw",    int_hexagon_A2_vmaxw>;
2559 def HEXAGON_A2_vmaxuw:
2560   di_ALU64_didi                   <"vmaxuw",   int_hexagon_A2_vmaxuw>;
2561
2562 // ALU64 / VW / Vector minimum words.
2563 def HEXAGON_A2_vminw:
2564   di_ALU64_didi                   <"vminw",    int_hexagon_A2_vminw>;
2565 def HEXAGON_A2_vminuw:
2566   di_ALU64_didi                   <"vminuw",   int_hexagon_A2_vminuw>;
2567
2568 // ALU64 / VW / Vector subtract words.
2569 def HEXAGON_A2_vsubw:
2570   di_ALU64_didi                   <"vsubw",    int_hexagon_A2_vsubw>;
2571 def HEXAGON_A2_vsubws:
2572   di_ALU64_didi_sat               <"vsubw",    int_hexagon_A2_vsubws>;
2573
2574
2575 /********************************************************************
2576 *            CR                                                     *
2577 *********************************************************************/
2578
2579 // CR / Logical reductions on predicates.
2580 def HEXAGON_C2_all8:
2581   qi_SInst_qi                     <"all8",     int_hexagon_C2_all8>;
2582 def HEXAGON_C2_any8:
2583   qi_SInst_qi                     <"any8",     int_hexagon_C2_any8>;
2584
2585 // CR / Logical operations on predicates.
2586 def HEXAGON_C2_pxfer_map:
2587   qi_SInst_qi_pxfer               <"",         int_hexagon_C2_pxfer_map>;
2588 def HEXAGON_C2_and:
2589   qi_SInst_qiqi                   <"and",      int_hexagon_C2_and>;
2590 def HEXAGON_C2_andn:
2591   qi_SInst_qiqi_neg               <"and",      int_hexagon_C2_andn>;
2592 def HEXAGON_C2_not:
2593   qi_SInst_qi                     <"not",      int_hexagon_C2_not>;
2594 def HEXAGON_C2_or:
2595   qi_SInst_qiqi                   <"or",       int_hexagon_C2_or>;
2596 def HEXAGON_C2_orn:
2597   qi_SInst_qiqi_neg               <"or",       int_hexagon_C2_orn>;
2598 def HEXAGON_C2_xor:
2599   qi_SInst_qiqi                   <"xor",      int_hexagon_C2_xor>;
2600
2601
2602 /********************************************************************
2603 *            MTYPE/ALU                                              *
2604 *********************************************************************/
2605
2606 // MTYPE / ALU / Add and accumulate.
2607 def HEXAGON_M2_acci:
2608   si_MInst_sisisi_acc             <"add",      int_hexagon_M2_acci>;
2609 def HEXAGON_M2_accii:
2610   si_MInst_sisis8_acc             <"add",      int_hexagon_M2_accii>;
2611 def HEXAGON_M2_nacci:
2612   si_MInst_sisisi_nac             <"add",      int_hexagon_M2_nacci>;
2613 def HEXAGON_M2_naccii:
2614   si_MInst_sisis8_nac             <"add",      int_hexagon_M2_naccii>;
2615
2616 // MTYPE / ALU / Subtract and accumulate.
2617 def HEXAGON_M2_subacc:
2618   si_MInst_sisisi_acc             <"sub",      int_hexagon_M2_subacc>;
2619
2620 // MTYPE / ALU / Vector absolute difference.
2621 def HEXAGON_M2_vabsdiffh:
2622   di_MInst_didi                   <"vabsdiffh",int_hexagon_M2_vabsdiffh>;
2623 def HEXAGON_M2_vabsdiffw:
2624   di_MInst_didi                   <"vabsdiffw",int_hexagon_M2_vabsdiffw>;
2625
2626 // MTYPE / ALU / XOR and xor with destination.
2627 def HEXAGON_M2_xor_xacc:
2628   si_MInst_sisisi_xacc            <"xor",      int_hexagon_M2_xor_xacc>;
2629
2630
2631 /********************************************************************
2632 *            MTYPE/COMPLEX                                          *
2633 *********************************************************************/
2634
2635 // MTYPE / COMPLEX / Complex multiply.
2636 // Rdd[-+]=cmpy(Rs, Rt:<<1]:sat
2637 def HEXAGON_M2_cmpys_s1:
2638   di_MInst_sisi_s1_sat            <"cmpy",     int_hexagon_M2_cmpys_s1>;
2639 def HEXAGON_M2_cmpys_s0:
2640   di_MInst_sisi_sat               <"cmpy",     int_hexagon_M2_cmpys_s0>;
2641 def HEXAGON_M2_cmpysc_s1:
2642   di_MInst_sisi_s1_sat_conj       <"cmpy",     int_hexagon_M2_cmpysc_s1>;
2643 def HEXAGON_M2_cmpysc_s0:
2644   di_MInst_sisi_sat_conj          <"cmpy",     int_hexagon_M2_cmpysc_s0>;
2645
2646 def HEXAGON_M2_cmacs_s1:
2647   di_MInst_disisi_acc_s1_sat      <"cmpy",     int_hexagon_M2_cmacs_s1>;
2648 def HEXAGON_M2_cmacs_s0:
2649   di_MInst_disisi_acc_sat         <"cmpy",     int_hexagon_M2_cmacs_s0>;
2650 def HEXAGON_M2_cmacsc_s1:
2651   di_MInst_disisi_acc_s1_sat_conj <"cmpy",     int_hexagon_M2_cmacsc_s1>;
2652 def HEXAGON_M2_cmacsc_s0:
2653   di_MInst_disisi_acc_sat_conj    <"cmpy",     int_hexagon_M2_cmacsc_s0>;
2654
2655 def HEXAGON_M2_cnacs_s1:
2656   di_MInst_disisi_nac_s1_sat      <"cmpy",     int_hexagon_M2_cnacs_s1>;
2657 def HEXAGON_M2_cnacs_s0:
2658   di_MInst_disisi_nac_sat         <"cmpy",     int_hexagon_M2_cnacs_s0>;
2659 def HEXAGON_M2_cnacsc_s1:
2660   di_MInst_disisi_nac_s1_sat_conj <"cmpy",     int_hexagon_M2_cnacsc_s1>;
2661 def HEXAGON_M2_cnacsc_s0:
2662   di_MInst_disisi_nac_sat_conj    <"cmpy",     int_hexagon_M2_cnacsc_s0>;
2663
2664 // MTYPE / COMPLEX / Complex multiply real or imaginary.
2665 def HEXAGON_M2_cmpyr_s0:
2666   di_MInst_sisi                   <"cmpyr",    int_hexagon_M2_cmpyr_s0>;
2667 def HEXAGON_M2_cmacr_s0:
2668   di_MInst_disisi_acc             <"cmpyr",    int_hexagon_M2_cmacr_s0>;
2669
2670 def HEXAGON_M2_cmpyi_s0:
2671   di_MInst_sisi                   <"cmpyi",    int_hexagon_M2_cmpyi_s0>;
2672 def HEXAGON_M2_cmaci_s0:
2673   di_MInst_disisi_acc             <"cmpyi",    int_hexagon_M2_cmaci_s0>;
2674
2675 // MTYPE / COMPLEX / Complex multiply with round and pack.
2676 // Rxx32+=cmpy(Rs32,[*]Rt32:<<1]:rnd:sat
2677 def HEXAGON_M2_cmpyrs_s0:
2678   si_MInst_sisi_rnd_sat           <"cmpy",     int_hexagon_M2_cmpyrs_s0>;
2679 def HEXAGON_M2_cmpyrs_s1:
2680   si_MInst_sisi_s1_rnd_sat        <"cmpy",     int_hexagon_M2_cmpyrs_s1>;
2681
2682 def HEXAGON_M2_cmpyrsc_s0:
2683   si_MInst_sisi_rnd_sat_conj      <"cmpy",     int_hexagon_M2_cmpyrsc_s0>;
2684 def HEXAGON_M2_cmpyrsc_s1:
2685   si_MInst_sisi_s1_rnd_sat_conj   <"cmpy",     int_hexagon_M2_cmpyrsc_s1>;
2686
2687 //MTYPE / COMPLEX / Vector complex multiply real or imaginary.
2688 def HEXAGON_M2_vcmpy_s0_sat_i:
2689   di_MInst_didi_sat               <"vcmpyi",   int_hexagon_M2_vcmpy_s0_sat_i>;
2690 def HEXAGON_M2_vcmpy_s1_sat_i:
2691   di_MInst_didi_s1_sat            <"vcmpyi",   int_hexagon_M2_vcmpy_s1_sat_i>;
2692
2693 def HEXAGON_M2_vcmpy_s0_sat_r:
2694   di_MInst_didi_sat               <"vcmpyr",   int_hexagon_M2_vcmpy_s0_sat_r>;
2695 def HEXAGON_M2_vcmpy_s1_sat_r:
2696   di_MInst_didi_s1_sat            <"vcmpyr",   int_hexagon_M2_vcmpy_s1_sat_r>;
2697
2698 def HEXAGON_M2_vcmac_s0_sat_i:
2699   di_MInst_dididi_acc_sat         <"vcmpyi",   int_hexagon_M2_vcmac_s0_sat_i>;
2700 def HEXAGON_M2_vcmac_s0_sat_r:
2701   di_MInst_dididi_acc_sat         <"vcmpyr",   int_hexagon_M2_vcmac_s0_sat_r>;
2702
2703 //MTYPE / COMPLEX / Vector reduce complex multiply real or imaginary.
2704 def HEXAGON_M2_vrcmpyi_s0:
2705   di_MInst_didi                   <"vrcmpyi",  int_hexagon_M2_vrcmpyi_s0>;
2706 def HEXAGON_M2_vrcmpyr_s0:
2707   di_MInst_didi                   <"vrcmpyr",  int_hexagon_M2_vrcmpyr_s0>;
2708
2709 def HEXAGON_M2_vrcmpyi_s0c:
2710   di_MInst_didi_conj              <"vrcmpyi",  int_hexagon_M2_vrcmpyi_s0c>;
2711 def HEXAGON_M2_vrcmpyr_s0c:
2712   di_MInst_didi_conj              <"vrcmpyr",  int_hexagon_M2_vrcmpyr_s0c>;
2713
2714 def HEXAGON_M2_vrcmaci_s0:
2715   di_MInst_dididi_acc             <"vrcmpyi",  int_hexagon_M2_vrcmaci_s0>;
2716 def HEXAGON_M2_vrcmacr_s0:
2717   di_MInst_dididi_acc             <"vrcmpyr",  int_hexagon_M2_vrcmacr_s0>;
2718
2719 def HEXAGON_M2_vrcmaci_s0c:
2720   di_MInst_dididi_acc_conj        <"vrcmpyi",  int_hexagon_M2_vrcmaci_s0c>;
2721 def HEXAGON_M2_vrcmacr_s0c:
2722   di_MInst_dididi_acc_conj        <"vrcmpyr",  int_hexagon_M2_vrcmacr_s0c>;
2723
2724
2725 /********************************************************************
2726 *            MTYPE/MPYH                                             *
2727 *********************************************************************/
2728
2729 // MTYPE / MPYH / Multiply and use lower result.
2730 //def HEXAGON_M2_mpysmi:
2731 //FIXME: Hexagon_M2_mpysmi should really by of the type si_MInst_sim9,
2732 // not si_MInst_sis9 - but for now, we will use s9.
2733 // def Hexagon_M2_mpysmi:
2734 //  si_MInst_sim9                   <"mpyi",     int_hexagon_M2_mpysmi>;
2735 def Hexagon_M2_mpysmi:
2736   si_MInst_sis9                   <"mpyi",     int_hexagon_M2_mpysmi>;
2737 def HEXAGON_M2_mpyi:
2738   si_MInst_sisi                   <"mpyi",     int_hexagon_M2_mpyi>;
2739 def HEXAGON_M2_mpyui:
2740   si_MInst_sisi                   <"mpyui",    int_hexagon_M2_mpyui>;
2741 def HEXAGON_M2_macsip:
2742   si_MInst_sisiu8_acc             <"mpyi",     int_hexagon_M2_macsip>;
2743 def HEXAGON_M2_maci:
2744   si_MInst_sisisi_acc             <"mpyi",     int_hexagon_M2_maci>;
2745 def HEXAGON_M2_macsin:
2746   si_MInst_sisiu8_nac             <"mpyi",     int_hexagon_M2_macsin>;
2747
2748 // MTYPE / MPYH / Multiply word by half (32x16).
2749 //Rdd[+]=vmpywoh(Rss,Rtt)[:<<1][:rnd][:sat]
2750 //Rdd[+]=vmpyweh(Rss,Rtt)[:<<1][:rnd][:sat]
2751 def HEXAGON_M2_mmpyl_rs1:
2752   di_MInst_didi_s1_rnd_sat        <"vmpyweh",  int_hexagon_M2_mmpyl_rs1>;
2753 def HEXAGON_M2_mmpyl_s1:
2754   di_MInst_didi_s1_sat            <"vmpyweh",  int_hexagon_M2_mmpyl_s1>;
2755 def HEXAGON_M2_mmpyl_rs0:
2756   di_MInst_didi_rnd_sat           <"vmpyweh",  int_hexagon_M2_mmpyl_rs0>;
2757 def HEXAGON_M2_mmpyl_s0:
2758   di_MInst_didi_sat               <"vmpyweh",  int_hexagon_M2_mmpyl_s0>;
2759 def HEXAGON_M2_mmpyh_rs1:
2760   di_MInst_didi_s1_rnd_sat        <"vmpywoh",  int_hexagon_M2_mmpyh_rs1>;
2761 def HEXAGON_M2_mmpyh_s1:
2762   di_MInst_didi_s1_sat            <"vmpywoh",  int_hexagon_M2_mmpyh_s1>;
2763 def HEXAGON_M2_mmpyh_rs0:
2764   di_MInst_didi_rnd_sat           <"vmpywoh",  int_hexagon_M2_mmpyh_rs0>;
2765 def HEXAGON_M2_mmpyh_s0:
2766   di_MInst_didi_sat               <"vmpywoh",  int_hexagon_M2_mmpyh_s0>;
2767 def HEXAGON_M2_mmacls_rs1:
2768   di_MInst_dididi_acc_s1_rnd_sat  <"vmpyweh",  int_hexagon_M2_mmacls_rs1>;
2769 def HEXAGON_M2_mmacls_s1:
2770   di_MInst_dididi_acc_s1_sat      <"vmpyweh",  int_hexagon_M2_mmacls_s1>;
2771 def HEXAGON_M2_mmacls_rs0:
2772   di_MInst_dididi_acc_rnd_sat     <"vmpyweh",  int_hexagon_M2_mmacls_rs0>;
2773 def HEXAGON_M2_mmacls_s0:
2774   di_MInst_dididi_acc_sat         <"vmpyweh",  int_hexagon_M2_mmacls_s0>;
2775 def HEXAGON_M2_mmachs_rs1:
2776   di_MInst_dididi_acc_s1_rnd_sat  <"vmpywoh",  int_hexagon_M2_mmachs_rs1>;
2777 def HEXAGON_M2_mmachs_s1:
2778   di_MInst_dididi_acc_s1_sat      <"vmpywoh",  int_hexagon_M2_mmachs_s1>;
2779 def HEXAGON_M2_mmachs_rs0:
2780   di_MInst_dididi_acc_rnd_sat     <"vmpywoh",  int_hexagon_M2_mmachs_rs0>;
2781 def HEXAGON_M2_mmachs_s0:
2782   di_MInst_dididi_acc_sat         <"vmpywoh",  int_hexagon_M2_mmachs_s0>;
2783
2784 // MTYPE / MPYH / Multiply word by unsigned half (32x16).
2785 //Rdd[+]=vmpywouh(Rss,Rtt)[:<<1][:rnd][:sat]
2786 //Rdd[+]=vmpyweuh(Rss,Rtt)[:<<1][:rnd][:sat]
2787 def HEXAGON_M2_mmpyul_rs1:
2788   di_MInst_didi_s1_rnd_sat        <"vmpyweuh", int_hexagon_M2_mmpyul_rs1>;
2789 def HEXAGON_M2_mmpyul_s1:
2790   di_MInst_didi_s1_sat            <"vmpyweuh", int_hexagon_M2_mmpyul_s1>;
2791 def HEXAGON_M2_mmpyul_rs0:
2792   di_MInst_didi_rnd_sat           <"vmpyweuh", int_hexagon_M2_mmpyul_rs0>;
2793 def HEXAGON_M2_mmpyul_s0:
2794   di_MInst_didi_sat               <"vmpyweuh", int_hexagon_M2_mmpyul_s0>;
2795 def HEXAGON_M2_mmpyuh_rs1:
2796   di_MInst_didi_s1_rnd_sat        <"vmpywouh", int_hexagon_M2_mmpyuh_rs1>;
2797 def HEXAGON_M2_mmpyuh_s1:
2798   di_MInst_didi_s1_sat            <"vmpywouh", int_hexagon_M2_mmpyuh_s1>;
2799 def HEXAGON_M2_mmpyuh_rs0:
2800   di_MInst_didi_rnd_sat           <"vmpywouh", int_hexagon_M2_mmpyuh_rs0>;
2801 def HEXAGON_M2_mmpyuh_s0:
2802   di_MInst_didi_sat               <"vmpywouh", int_hexagon_M2_mmpyuh_s0>;
2803 def HEXAGON_M2_mmaculs_rs1:
2804   di_MInst_dididi_acc_s1_rnd_sat  <"vmpyweuh", int_hexagon_M2_mmaculs_rs1>;
2805 def HEXAGON_M2_mmaculs_s1:
2806   di_MInst_dididi_acc_s1_sat      <"vmpyweuh", int_hexagon_M2_mmaculs_s1>;
2807 def HEXAGON_M2_mmaculs_rs0:
2808   di_MInst_dididi_acc_rnd_sat     <"vmpyweuh", int_hexagon_M2_mmaculs_rs0>;
2809 def HEXAGON_M2_mmaculs_s0:
2810   di_MInst_dididi_acc_sat         <"vmpyweuh", int_hexagon_M2_mmaculs_s0>;
2811 def HEXAGON_M2_mmacuhs_rs1:
2812   di_MInst_dididi_acc_s1_rnd_sat  <"vmpywouh", int_hexagon_M2_mmacuhs_rs1>;
2813 def HEXAGON_M2_mmacuhs_s1:
2814   di_MInst_dididi_acc_s1_sat      <"vmpywouh", int_hexagon_M2_mmacuhs_s1>;
2815 def HEXAGON_M2_mmacuhs_rs0:
2816   di_MInst_dididi_acc_rnd_sat     <"vmpywouh", int_hexagon_M2_mmacuhs_rs0>;
2817 def HEXAGON_M2_mmacuhs_s0:
2818   di_MInst_dididi_acc_sat         <"vmpywouh", int_hexagon_M2_mmacuhs_s0>;
2819
2820 // MTYPE / MPYH / Multiply and use upper result.
2821 def HEXAGON_M2_hmmpyh_rs1:
2822   si_MInst_sisi_h_s1_rnd_sat      <"mpy",      int_hexagon_M2_hmmpyh_rs1>;
2823 def HEXAGON_M2_hmmpyl_rs1:
2824   si_MInst_sisi_l_s1_rnd_sat      <"mpy",      int_hexagon_M2_hmmpyl_rs1>;
2825 def HEXAGON_M2_mpy_up:
2826   si_MInst_sisi                   <"mpy",      int_hexagon_M2_mpy_up>;
2827 def HEXAGON_M2_dpmpyss_rnd_s0:
2828   si_MInst_sisi_rnd               <"mpy",      int_hexagon_M2_dpmpyss_rnd_s0>;
2829 def HEXAGON_M2_mpyu_up:
2830   si_MInst_sisi                   <"mpyu",     int_hexagon_M2_mpyu_up>;
2831
2832 // MTYPE / MPYH / Multiply and use full result.
2833 def HEXAGON_M2_dpmpyuu_s0:
2834   di_MInst_sisi                   <"mpyu",     int_hexagon_M2_dpmpyuu_s0>;
2835 def HEXAGON_M2_dpmpyuu_acc_s0:
2836   di_MInst_disisi_acc             <"mpyu",     int_hexagon_M2_dpmpyuu_acc_s0>;
2837 def HEXAGON_M2_dpmpyuu_nac_s0:
2838   di_MInst_disisi_nac             <"mpyu",     int_hexagon_M2_dpmpyuu_nac_s0>;
2839 def HEXAGON_M2_dpmpyss_s0:
2840   di_MInst_sisi                   <"mpy",      int_hexagon_M2_dpmpyss_s0>;
2841 def HEXAGON_M2_dpmpyss_acc_s0:
2842   di_MInst_disisi_acc             <"mpy",      int_hexagon_M2_dpmpyss_acc_s0>;
2843 def HEXAGON_M2_dpmpyss_nac_s0:
2844   di_MInst_disisi_nac             <"mpy",      int_hexagon_M2_dpmpyss_nac_s0>;
2845
2846 /********************************************************************
2847 *            MTYPE/VB                                               *
2848 *********************************************************************/
2849
2850 // MTYPE / VB / Vector reduce add unsigned bytes.
2851 def HEXAGON_A2_vraddub:
2852   di_MInst_didi                   <"vraddub", int_hexagon_A2_vraddub>;
2853 def HEXAGON_A2_vraddub_acc:
2854   di_MInst_dididi_acc             <"vraddub", int_hexagon_A2_vraddub_acc>;
2855
2856 // MTYPE / VB / Vector sum of absolute differences unsigned bytes.
2857 def HEXAGON_A2_vrsadub:
2858   di_MInst_didi                   <"vrsadub", int_hexagon_A2_vrsadub>;
2859 def HEXAGON_A2_vrsadub_acc:
2860   di_MInst_dididi_acc             <"vrsadub", int_hexagon_A2_vrsadub_acc>;
2861
2862 /********************************************************************
2863 *            MTYPE/VH                                               *
2864 *********************************************************************/
2865
2866 // MTYPE / VH / Vector dual multiply.
2867 def HEXAGON_M2_vdmpys_s1:
2868   di_MInst_didi_s1_sat            <"vdmpy",   int_hexagon_M2_vdmpys_s1>;
2869 def HEXAGON_M2_vdmpys_s0:
2870   di_MInst_didi_sat               <"vdmpy",   int_hexagon_M2_vdmpys_s0>;
2871 def HEXAGON_M2_vdmacs_s1:
2872   di_MInst_dididi_acc_s1_sat      <"vdmpy",   int_hexagon_M2_vdmacs_s1>;
2873 def HEXAGON_M2_vdmacs_s0:
2874   di_MInst_dididi_acc_sat         <"vdmpy",   int_hexagon_M2_vdmacs_s0>;
2875
2876 // MTYPE / VH / Vector dual multiply with round and pack.
2877 def HEXAGON_M2_vdmpyrs_s0:
2878   si_MInst_didi_rnd_sat           <"vdmpy",   int_hexagon_M2_vdmpyrs_s0>;
2879 def HEXAGON_M2_vdmpyrs_s1:
2880   si_MInst_didi_s1_rnd_sat        <"vdmpy",   int_hexagon_M2_vdmpyrs_s1>;
2881
2882 // MTYPE / VH / Vector multiply even halfwords.
2883 def HEXAGON_M2_vmpy2es_s1:
2884   di_MInst_didi_s1_sat            <"vmpyeh",  int_hexagon_M2_vmpy2es_s1>;
2885 def HEXAGON_M2_vmpy2es_s0:
2886   di_MInst_didi_sat               <"vmpyeh",  int_hexagon_M2_vmpy2es_s0>;
2887 def HEXAGON_M2_vmac2es:
2888   di_MInst_dididi_acc             <"vmpyeh",  int_hexagon_M2_vmac2es>;
2889 def HEXAGON_M2_vmac2es_s1:
2890   di_MInst_dididi_acc_s1_sat      <"vmpyeh",  int_hexagon_M2_vmac2es_s1>;
2891 def HEXAGON_M2_vmac2es_s0:
2892   di_MInst_dididi_acc_sat         <"vmpyeh",  int_hexagon_M2_vmac2es_s0>;
2893
2894 // MTYPE / VH / Vector multiply halfwords.
2895 def HEXAGON_M2_vmpy2s_s0:
2896   di_MInst_sisi_sat               <"vmpyh",   int_hexagon_M2_vmpy2s_s0>;
2897 def HEXAGON_M2_vmpy2s_s1:
2898   di_MInst_sisi_s1_sat            <"vmpyh",   int_hexagon_M2_vmpy2s_s1>;
2899 def HEXAGON_M2_vmac2:
2900   di_MInst_disisi_acc             <"vmpyh",   int_hexagon_M2_vmac2>;
2901 def HEXAGON_M2_vmac2s_s0:
2902   di_MInst_disisi_acc_sat         <"vmpyh",   int_hexagon_M2_vmac2s_s0>;
2903 def HEXAGON_M2_vmac2s_s1:
2904   di_MInst_disisi_acc_s1_sat      <"vmpyh",   int_hexagon_M2_vmac2s_s1>;
2905
2906 // MTYPE / VH / Vector multiply halfwords with round and pack.
2907 def HEXAGON_M2_vmpy2s_s0pack:
2908   si_MInst_sisi_rnd_sat           <"vmpyh",   int_hexagon_M2_vmpy2s_s0pack>;
2909 def HEXAGON_M2_vmpy2s_s1pack:
2910   si_MInst_sisi_s1_rnd_sat        <"vmpyh",   int_hexagon_M2_vmpy2s_s1pack>;
2911
2912 // MTYPE / VH / Vector reduce multiply halfwords.
2913 // Rxx32+=vrmpyh(Rss32,Rtt32)
2914 def HEXAGON_M2_vrmpy_s0:
2915   di_MInst_didi                   <"vrmpyh",  int_hexagon_M2_vrmpy_s0>;
2916 def HEXAGON_M2_vrmac_s0:
2917   di_MInst_dididi_acc             <"vrmpyh",  int_hexagon_M2_vrmac_s0>;
2918
2919
2920 /********************************************************************
2921 *            STYPE/ALU                                              *
2922 *********************************************************************/
2923
2924 // STYPE / ALU / Absolute value.
2925 def HEXAGON_A2_abs:
2926   si_SInst_si                     <"abs",     int_hexagon_A2_abs>;
2927 def HEXAGON_A2_absp:
2928   di_SInst_di                     <"abs",     int_hexagon_A2_absp>;
2929 def HEXAGON_A2_abssat:
2930   si_SInst_si_sat                 <"abs",     int_hexagon_A2_abssat>;
2931
2932 // STYPE / ALU / Logical Not.
2933 def HEXAGON_A2_notp:
2934   di_SInst_di                     <"not",     int_hexagon_A2_notp>;
2935
2936 // STYPE / ALU / Sign extend word to doubleword.
2937 def HEXAGON_A2_sxtw:
2938   di_SInst_si                     <"sxtw",     int_hexagon_A2_sxtw>;
2939
2940
2941 /********************************************************************
2942 *            STYPE/BIT                                              *
2943 *********************************************************************/
2944
2945 // STYPE / BIT / Count leading.
2946 def HEXAGON_S2_cl0:
2947   si_SInst_si                     <"cl0",     int_hexagon_S2_cl0>;
2948 def HEXAGON_S2_cl0p:
2949   si_SInst_di                     <"cl0",     int_hexagon_S2_cl0p>;
2950 def HEXAGON_S2_cl1:
2951   si_SInst_si                     <"cl1",     int_hexagon_S2_cl1>;
2952 def HEXAGON_S2_cl1p:
2953   si_SInst_di                     <"cl1",     int_hexagon_S2_cl1p>;
2954 def HEXAGON_S2_clb:
2955   si_SInst_si                     <"clb",     int_hexagon_S2_clb>;
2956 def HEXAGON_S2_clbp:
2957   si_SInst_di                     <"clb",     int_hexagon_S2_clbp>;
2958 def HEXAGON_S2_clbnorm:
2959   si_SInst_si                     <"normamt", int_hexagon_S2_clbnorm>;
2960
2961 // STYPE / BIT / Count trailing.
2962 def HEXAGON_S2_ct0:
2963   si_SInst_si                     <"ct0",     int_hexagon_S2_ct0>;
2964 def HEXAGON_S2_ct1:
2965   si_SInst_si                     <"ct1",     int_hexagon_S2_ct1>;
2966
2967 // STYPE / BIT / Compare bit mask.
2968 def Hexagon_C2_bitsclr:
2969   qi_SInst_sisi                   <"bitsclr", int_hexagon_C2_bitsclr>;
2970 def Hexagon_C2_bitsclri:
2971   qi_SInst_siu6                   <"bitsclr", int_hexagon_C2_bitsclri>;
2972 def Hexagon_C2_bitsset:
2973   qi_SInst_sisi                   <"bitsset", int_hexagon_C2_bitsset>;
2974
2975 // STYPE / BIT / Extract unsigned.
2976 // Rd[d][32/64]=extractu(Rs[s],Rt[t],[imm])
2977 def HEXAGON_S2_extractu:
2978   si_SInst_siu5u5                 <"extractu",int_hexagon_S2_extractu>;
2979 def HEXAGON_S2_extractu_rp:
2980   si_SInst_sidi                   <"extractu",int_hexagon_S2_extractu_rp>;
2981 def HEXAGON_S2_extractup:
2982   di_SInst_diu6u6                 <"extractu",int_hexagon_S2_extractup>;
2983 def HEXAGON_S2_extractup_rp:
2984   di_SInst_didi                   <"extractu",int_hexagon_S2_extractup_rp>;
2985
2986 // STYPE / BIT / Insert bitfield.
2987 def Hexagon_S2_insert:
2988   si_SInst_sisiu5u5               <"insert",  int_hexagon_S2_insert>;
2989 def Hexagon_S2_insert_rp:
2990   si_SInst_sisidi                 <"insert",  int_hexagon_S2_insert_rp>;
2991 def Hexagon_S2_insertp:
2992   di_SInst_didiu6u6               <"insert",  int_hexagon_S2_insertp>;
2993 def Hexagon_S2_insertp_rp:
2994   di_SInst_dididi                 <"insert",  int_hexagon_S2_insertp_rp>;
2995
2996 // STYPE / BIT / Innterleave/deinterleave.
2997 def Hexagon_S2_interleave:
2998   di_SInst_di                     <"interleave", int_hexagon_S2_interleave>;
2999 def Hexagon_S2_deinterleave:
3000   di_SInst_di                     <"deinterleave", int_hexagon_S2_deinterleave>;
3001
3002 // STYPE / BIT / Linear feedback-shift Iteration.
3003 def Hexagon_S2_lfsp:
3004   di_SInst_didi                   <"lfs",     int_hexagon_S2_lfsp>;
3005
3006 // STYPE / BIT / Bit reverse.
3007 def Hexagon_S2_brev:
3008   si_SInst_si                     <"brev",    int_hexagon_S2_brev>;
3009
3010 // STYPE / BIT / Set/Clear/Toggle Bit.
3011 def HEXAGON_S2_setbit_i:
3012   si_SInst_siu5                   <"setbit",  int_hexagon_S2_setbit_i>;
3013 def HEXAGON_S2_togglebit_i:
3014   si_SInst_siu5                   <"togglebit", int_hexagon_S2_togglebit_i>;
3015 def HEXAGON_S2_clrbit_i:
3016   si_SInst_siu5                   <"clrbit",  int_hexagon_S2_clrbit_i>;
3017 def HEXAGON_S2_setbit_r:
3018   si_SInst_sisi                   <"setbit",  int_hexagon_S2_setbit_r>;
3019 def HEXAGON_S2_togglebit_r:
3020   si_SInst_sisi                   <"togglebit", int_hexagon_S2_togglebit_r>;
3021 def HEXAGON_S2_clrbit_r:
3022   si_SInst_sisi                   <"clrbit",  int_hexagon_S2_clrbit_r>;
3023
3024 // STYPE / BIT / Test Bit.
3025 def HEXAGON_S2_tstbit_i:
3026   qi_SInst_siu5                   <"tstbit",  int_hexagon_S2_tstbit_i>;
3027 def HEXAGON_S2_tstbit_r:
3028   qi_SInst_sisi                   <"tstbit",  int_hexagon_S2_tstbit_r>;
3029
3030
3031 /********************************************************************
3032 *            STYPE/COMPLEX                                          *
3033 *********************************************************************/
3034
3035 // STYPE / COMPLEX / Vector Complex conjugate.
3036 def HEXAGON_A2_vconj:
3037   di_SInst_di_sat                 <"vconj",   int_hexagon_A2_vconj>;
3038
3039 // STYPE / COMPLEX / Vector Complex rotate.
3040 def HEXAGON_S2_vcrotate:
3041   di_SInst_disi                   <"vcrotate",int_hexagon_S2_vcrotate>;
3042
3043
3044 /********************************************************************
3045 *            STYPE/PERM                                             *
3046 *********************************************************************/
3047
3048 // STYPE / PERM / Saturate.
3049 def HEXAGON_A2_sat:
3050   si_SInst_di                     <"sat",     int_hexagon_A2_sat>;
3051 def HEXAGON_A2_satb:
3052   si_SInst_si                     <"satb",    int_hexagon_A2_satb>;
3053 def HEXAGON_A2_sath:
3054   si_SInst_si                     <"sath",    int_hexagon_A2_sath>;
3055 def HEXAGON_A2_satub:
3056   si_SInst_si                     <"satub",   int_hexagon_A2_satub>;
3057 def HEXAGON_A2_satuh:
3058   si_SInst_si                     <"satuh",   int_hexagon_A2_satuh>;
3059
3060 // STYPE / PERM / Swizzle bytes.
3061 def HEXAGON_A2_swiz:
3062   si_SInst_si                     <"swiz",    int_hexagon_A2_swiz>;
3063
3064 // STYPE / PERM / Vector align.
3065 // Need custom lowering
3066 def HEXAGON_S2_valignib:
3067   di_SInst_didiu3                 <"valignb", int_hexagon_S2_valignib>;
3068 def HEXAGON_S2_valignrb:
3069   di_SInst_didiqi                 <"valignb", int_hexagon_S2_valignrb>;
3070
3071 // STYPE / PERM / Vector round and pack.
3072 def HEXAGON_S2_vrndpackwh:
3073   si_SInst_di                     <"vrndwh",  int_hexagon_S2_vrndpackwh>;
3074 def HEXAGON_S2_vrndpackwhs:
3075   si_SInst_di_sat                 <"vrndwh",  int_hexagon_S2_vrndpackwhs>;
3076
3077 // STYPE / PERM / Vector saturate and pack.
3078 def HEXAGON_S2_svsathb:
3079   si_SInst_si                     <"vsathb",  int_hexagon_S2_svsathb>;
3080 def HEXAGON_S2_vsathb:
3081   si_SInst_di                     <"vsathb",  int_hexagon_S2_vsathb>;
3082 def HEXAGON_S2_svsathub:
3083   si_SInst_si                     <"vsathub", int_hexagon_S2_svsathub>;
3084 def HEXAGON_S2_vsathub:
3085   si_SInst_di                     <"vsathub", int_hexagon_S2_vsathub>;
3086 def HEXAGON_S2_vsatwh:
3087   si_SInst_di                     <"vsatwh",  int_hexagon_S2_vsatwh>;
3088 def HEXAGON_S2_vsatwuh:
3089   si_SInst_di                     <"vsatwuh", int_hexagon_S2_vsatwuh>;
3090
3091 // STYPE / PERM / Vector saturate without pack.
3092 def HEXAGON_S2_vsathb_nopack:
3093   di_SInst_di                     <"vsathb",  int_hexagon_S2_vsathb_nopack>;
3094 def HEXAGON_S2_vsathub_nopack:
3095   di_SInst_di                     <"vsathub", int_hexagon_S2_vsathub_nopack>;
3096 def HEXAGON_S2_vsatwh_nopack:
3097   di_SInst_di                     <"vsatwh",  int_hexagon_S2_vsatwh_nopack>;
3098 def HEXAGON_S2_vsatwuh_nopack:
3099   di_SInst_di                     <"vsatwuh", int_hexagon_S2_vsatwuh_nopack>;
3100
3101 // STYPE / PERM / Vector shuffle.
3102 def HEXAGON_S2_shuffeb:
3103   di_SInst_didi                   <"shuffeb", int_hexagon_S2_shuffeb>;
3104 def HEXAGON_S2_shuffeh:
3105   di_SInst_didi                   <"shuffeh", int_hexagon_S2_shuffeh>;
3106 def HEXAGON_S2_shuffob:
3107   di_SInst_didi                   <"shuffob", int_hexagon_S2_shuffob>;
3108 def HEXAGON_S2_shuffoh:
3109   di_SInst_didi                   <"shuffoh", int_hexagon_S2_shuffoh>;
3110
3111 // STYPE / PERM / Vector splat bytes.
3112 def HEXAGON_S2_vsplatrb:
3113   si_SInst_si                     <"vsplatb", int_hexagon_S2_vsplatrb>;
3114
3115 // STYPE / PERM / Vector splat halfwords.
3116 def HEXAGON_S2_vsplatrh:
3117   di_SInst_si                     <"vsplath", int_hexagon_S2_vsplatrh>;
3118
3119 // STYPE / PERM / Vector splice.
3120 def Hexagon_S2_vsplicerb:
3121   di_SInst_didiqi                 <"vspliceb",int_hexagon_S2_vsplicerb>;
3122 def Hexagon_S2_vspliceib:
3123   di_SInst_didiu3                 <"vspliceb",int_hexagon_S2_vspliceib>;
3124
3125 // STYPE / PERM / Sign extend.
3126 def HEXAGON_S2_vsxtbh:
3127   di_SInst_si                     <"vsxtbh",  int_hexagon_S2_vsxtbh>;
3128 def HEXAGON_S2_vsxthw:
3129   di_SInst_si                     <"vsxthw",  int_hexagon_S2_vsxthw>;
3130
3131 // STYPE / PERM / Truncate.
3132 def HEXAGON_S2_vtrunehb:
3133   si_SInst_di                     <"vtrunehb",int_hexagon_S2_vtrunehb>;
3134 def HEXAGON_S2_vtrunohb:
3135   si_SInst_di                     <"vtrunohb",int_hexagon_S2_vtrunohb>;
3136 def HEXAGON_S2_vtrunewh:
3137   di_SInst_didi                   <"vtrunewh",int_hexagon_S2_vtrunewh>;
3138 def HEXAGON_S2_vtrunowh:
3139   di_SInst_didi                   <"vtrunowh",int_hexagon_S2_vtrunowh>;
3140
3141 // STYPE / PERM / Zero extend.
3142 def HEXAGON_S2_vzxtbh:
3143   di_SInst_si                     <"vzxtbh",  int_hexagon_S2_vzxtbh>;
3144 def HEXAGON_S2_vzxthw:
3145   di_SInst_si                     <"vzxthw",  int_hexagon_S2_vzxthw>;
3146
3147
3148 /********************************************************************
3149 *            STYPE/PRED                                             *
3150 *********************************************************************/
3151
3152 // STYPE / PRED / Mask generate from predicate.
3153 def HEXAGON_C2_mask:
3154   di_SInst_qi                     <"mask",   int_hexagon_C2_mask>;
3155
3156 // STYPE / PRED / Predicate transfer.
3157 def HEXAGON_C2_tfrpr:
3158   si_SInst_qi                     <"",       int_hexagon_C2_tfrpr>;
3159 def HEXAGON_C2_tfrrp:
3160   qi_SInst_si                     <"",       int_hexagon_C2_tfrrp>;
3161
3162 // STYPE / PRED / Viterbi pack even and odd predicate bits.
3163 def HEXAGON_C2_vitpack:
3164   si_SInst_qiqi                   <"vitpack",int_hexagon_C2_vitpack>;
3165
3166
3167 /********************************************************************
3168 *            STYPE/SHIFT                                            *
3169 *********************************************************************/
3170
3171 // STYPE / SHIFT / Shift by immediate.
3172 def HEXAGON_S2_asl_i_r:
3173   si_SInst_siu5                   <"asl",     int_hexagon_S2_asl_i_r>;
3174 def HEXAGON_S2_asr_i_r:
3175   si_SInst_siu5                   <"asr",     int_hexagon_S2_asr_i_r>;
3176 def HEXAGON_S2_lsr_i_r:
3177   si_SInst_siu5                   <"lsr",     int_hexagon_S2_lsr_i_r>;
3178 def HEXAGON_S2_asl_i_p:
3179   di_SInst_diu6                   <"asl",     int_hexagon_S2_asl_i_p>;
3180 def HEXAGON_S2_asr_i_p:
3181   di_SInst_diu6                   <"asr",     int_hexagon_S2_asr_i_p>;
3182 def HEXAGON_S2_lsr_i_p:
3183   di_SInst_diu6                   <"lsr",     int_hexagon_S2_lsr_i_p>;
3184
3185 // STYPE / SHIFT / Shift by immediate and accumulate.
3186 def HEXAGON_S2_asl_i_r_acc:
3187   si_SInst_sisiu5_acc             <"asl",     int_hexagon_S2_asl_i_r_acc>;
3188 def HEXAGON_S2_asr_i_r_acc:
3189   si_SInst_sisiu5_acc             <"asr",     int_hexagon_S2_asr_i_r_acc>;
3190 def HEXAGON_S2_lsr_i_r_acc:
3191   si_SInst_sisiu5_acc             <"lsr",     int_hexagon_S2_lsr_i_r_acc>;
3192 def HEXAGON_S2_asl_i_r_nac:
3193   si_SInst_sisiu5_nac             <"asl",     int_hexagon_S2_asl_i_r_nac>;
3194 def HEXAGON_S2_asr_i_r_nac:
3195   si_SInst_sisiu5_nac             <"asr",     int_hexagon_S2_asr_i_r_nac>;
3196 def HEXAGON_S2_lsr_i_r_nac:
3197   si_SInst_sisiu5_nac             <"lsr",     int_hexagon_S2_lsr_i_r_nac>;
3198 def HEXAGON_S2_asl_i_p_acc:
3199   di_SInst_didiu6_acc             <"asl",     int_hexagon_S2_asl_i_p_acc>;
3200 def HEXAGON_S2_asr_i_p_acc:
3201   di_SInst_didiu6_acc             <"asr",     int_hexagon_S2_asr_i_p_acc>;
3202 def HEXAGON_S2_lsr_i_p_acc:
3203   di_SInst_didiu6_acc             <"lsr",     int_hexagon_S2_lsr_i_p_acc>;
3204 def HEXAGON_S2_asl_i_p_nac:
3205   di_SInst_didiu6_nac             <"asl",     int_hexagon_S2_asl_i_p_nac>;
3206 def HEXAGON_S2_asr_i_p_nac:
3207   di_SInst_didiu6_nac             <"asr",     int_hexagon_S2_asr_i_p_nac>;
3208 def HEXAGON_S2_lsr_i_p_nac:
3209   di_SInst_didiu6_nac             <"lsr",     int_hexagon_S2_lsr_i_p_nac>;
3210
3211 // STYPE / SHIFT / Shift by immediate and add.
3212 def HEXAGON_S2_addasl_rrri:
3213   si_SInst_sisiu3                 <"addasl",  int_hexagon_S2_addasl_rrri>;
3214
3215 // STYPE / SHIFT / Shift by immediate and logical.
3216 def HEXAGON_S2_asl_i_r_and:
3217   si_SInst_sisiu5_and             <"asl",     int_hexagon_S2_asl_i_r_and>;
3218 def HEXAGON_S2_asr_i_r_and:
3219   si_SInst_sisiu5_and             <"asr",     int_hexagon_S2_asr_i_r_and>;
3220 def HEXAGON_S2_lsr_i_r_and:
3221   si_SInst_sisiu5_and             <"lsr",     int_hexagon_S2_lsr_i_r_and>;
3222
3223 def HEXAGON_S2_asl_i_r_xacc:
3224   si_SInst_sisiu5_xor             <"asl",     int_hexagon_S2_asl_i_r_xacc>;
3225 def HEXAGON_S2_lsr_i_r_xacc:
3226   si_SInst_sisiu5_xor             <"lsr",     int_hexagon_S2_lsr_i_r_xacc>;
3227
3228 def HEXAGON_S2_asl_i_r_or:
3229   si_SInst_sisiu5_or              <"asl",     int_hexagon_S2_asl_i_r_or>;
3230 def HEXAGON_S2_asr_i_r_or:
3231   si_SInst_sisiu5_or              <"asr",     int_hexagon_S2_asr_i_r_or>;
3232 def HEXAGON_S2_lsr_i_r_or:
3233   si_SInst_sisiu5_or              <"lsr",     int_hexagon_S2_lsr_i_r_or>;
3234
3235 def HEXAGON_S2_asl_i_p_and:
3236   di_SInst_didiu6_and             <"asl",     int_hexagon_S2_asl_i_p_and>;
3237 def HEXAGON_S2_asr_i_p_and:
3238   di_SInst_didiu6_and             <"asr",     int_hexagon_S2_asr_i_p_and>;
3239 def HEXAGON_S2_lsr_i_p_and:
3240   di_SInst_didiu6_and             <"lsr",     int_hexagon_S2_lsr_i_p_and>;
3241
3242 def HEXAGON_S2_asl_i_p_xacc:
3243   di_SInst_didiu6_xor             <"asl",     int_hexagon_S2_asl_i_p_xacc>;
3244 def HEXAGON_S2_lsr_i_p_xacc:
3245   di_SInst_didiu6_xor             <"lsr",     int_hexagon_S2_lsr_i_p_xacc>;
3246
3247 def HEXAGON_S2_asl_i_p_or:
3248   di_SInst_didiu6_or              <"asl",     int_hexagon_S2_asl_i_p_or>;
3249 def HEXAGON_S2_asr_i_p_or:
3250   di_SInst_didiu6_or              <"asr",     int_hexagon_S2_asr_i_p_or>;
3251 def HEXAGON_S2_lsr_i_p_or:
3252   di_SInst_didiu6_or              <"lsr",     int_hexagon_S2_lsr_i_p_or>;
3253
3254 // STYPE / SHIFT / Shift right by immediate with rounding.
3255 def HEXAGON_S2_asr_i_r_rnd:
3256   si_SInst_siu5_rnd               <"asr",     int_hexagon_S2_asr_i_r_rnd>;
3257 def HEXAGON_S2_asr_i_r_rnd_goodsyntax:
3258   si_SInst_siu5              <"asrrnd",  int_hexagon_S2_asr_i_r_rnd_goodsyntax>;
3259
3260 // STYPE / SHIFT / Shift left by immediate with saturation.
3261 def HEXAGON_S2_asl_i_r_sat:
3262   si_SInst_sisi_sat               <"asl",     int_hexagon_S2_asl_i_r_sat>;
3263
3264 // STYPE / SHIFT / Shift by register.
3265 def HEXAGON_S2_asl_r_r:
3266   si_SInst_sisi                   <"asl",     int_hexagon_S2_asl_r_r>;
3267 def HEXAGON_S2_asr_r_r:
3268   si_SInst_sisi                   <"asr",     int_hexagon_S2_asr_r_r>;
3269 def HEXAGON_S2_lsl_r_r:
3270   si_SInst_sisi                   <"lsl",     int_hexagon_S2_lsl_r_r>;
3271 def HEXAGON_S2_lsr_r_r:
3272   si_SInst_sisi                   <"lsr",     int_hexagon_S2_lsr_r_r>;
3273 def HEXAGON_S2_asl_r_p:
3274   di_SInst_disi                   <"asl",     int_hexagon_S2_asl_r_p>;
3275 def HEXAGON_S2_asr_r_p:
3276   di_SInst_disi                   <"asr",     int_hexagon_S2_asr_r_p>;
3277 def HEXAGON_S2_lsl_r_p:
3278   di_SInst_disi                   <"lsl",     int_hexagon_S2_lsl_r_p>;
3279 def HEXAGON_S2_lsr_r_p:
3280   di_SInst_disi                   <"lsr",     int_hexagon_S2_lsr_r_p>;
3281
3282 // STYPE / SHIFT / Shift by register and accumulate.
3283 def HEXAGON_S2_asl_r_r_acc:
3284   si_SInst_sisisi_acc             <"asl",     int_hexagon_S2_asl_r_r_acc>;
3285 def HEXAGON_S2_asr_r_r_acc:
3286   si_SInst_sisisi_acc             <"asr",     int_hexagon_S2_asr_r_r_acc>;
3287 def HEXAGON_S2_lsl_r_r_acc:
3288   si_SInst_sisisi_acc             <"lsl",     int_hexagon_S2_lsl_r_r_acc>;
3289 def HEXAGON_S2_lsr_r_r_acc:
3290   si_SInst_sisisi_acc             <"lsr",     int_hexagon_S2_lsr_r_r_acc>;
3291 def HEXAGON_S2_asl_r_p_acc:
3292   di_SInst_didisi_acc             <"asl",     int_hexagon_S2_asl_r_p_acc>;
3293 def HEXAGON_S2_asr_r_p_acc:
3294   di_SInst_didisi_acc             <"asr",     int_hexagon_S2_asr_r_p_acc>;
3295 def HEXAGON_S2_lsl_r_p_acc:
3296   di_SInst_didisi_acc             <"lsl",     int_hexagon_S2_lsl_r_p_acc>;
3297 def HEXAGON_S2_lsr_r_p_acc:
3298   di_SInst_didisi_acc             <"lsr",     int_hexagon_S2_lsr_r_p_acc>;
3299
3300 def HEXAGON_S2_asl_r_r_nac:
3301   si_SInst_sisisi_nac             <"asl",     int_hexagon_S2_asl_r_r_nac>;
3302 def HEXAGON_S2_asr_r_r_nac:
3303   si_SInst_sisisi_nac             <"asr",     int_hexagon_S2_asr_r_r_nac>;
3304 def HEXAGON_S2_lsl_r_r_nac:
3305   si_SInst_sisisi_nac             <"lsl",     int_hexagon_S2_lsl_r_r_nac>;
3306 def HEXAGON_S2_lsr_r_r_nac:
3307   si_SInst_sisisi_nac             <"lsr",     int_hexagon_S2_lsr_r_r_nac>;
3308 def HEXAGON_S2_asl_r_p_nac:
3309   di_SInst_didisi_nac             <"asl",     int_hexagon_S2_asl_r_p_nac>;
3310 def HEXAGON_S2_asr_r_p_nac:
3311   di_SInst_didisi_nac             <"asr",     int_hexagon_S2_asr_r_p_nac>;
3312 def HEXAGON_S2_lsl_r_p_nac:
3313   di_SInst_didisi_nac             <"lsl",     int_hexagon_S2_lsl_r_p_nac>;
3314 def HEXAGON_S2_lsr_r_p_nac:
3315   di_SInst_didisi_nac             <"lsr",     int_hexagon_S2_lsr_r_p_nac>;
3316
3317 // STYPE / SHIFT / Shift by register and logical.
3318 def HEXAGON_S2_asl_r_r_and:
3319   si_SInst_sisisi_and             <"asl",     int_hexagon_S2_asl_r_r_and>;
3320 def HEXAGON_S2_asr_r_r_and:
3321   si_SInst_sisisi_and             <"asr",     int_hexagon_S2_asr_r_r_and>;
3322 def HEXAGON_S2_lsl_r_r_and:
3323   si_SInst_sisisi_and             <"lsl",     int_hexagon_S2_lsl_r_r_and>;
3324 def HEXAGON_S2_lsr_r_r_and:
3325   si_SInst_sisisi_and             <"lsr",     int_hexagon_S2_lsr_r_r_and>;
3326
3327 def HEXAGON_S2_asl_r_r_or:
3328   si_SInst_sisisi_or              <"asl",     int_hexagon_S2_asl_r_r_or>;
3329 def HEXAGON_S2_asr_r_r_or:
3330   si_SInst_sisisi_or              <"asr",     int_hexagon_S2_asr_r_r_or>;
3331 def HEXAGON_S2_lsl_r_r_or:
3332   si_SInst_sisisi_or              <"lsl",     int_hexagon_S2_lsl_r_r_or>;
3333 def HEXAGON_S2_lsr_r_r_or:
3334   si_SInst_sisisi_or              <"lsr",     int_hexagon_S2_lsr_r_r_or>;
3335
3336 def HEXAGON_S2_asl_r_p_and:
3337   di_SInst_didisi_and             <"asl",     int_hexagon_S2_asl_r_p_and>;
3338 def HEXAGON_S2_asr_r_p_and:
3339   di_SInst_didisi_and             <"asr",     int_hexagon_S2_asr_r_p_and>;
3340 def HEXAGON_S2_lsl_r_p_and:
3341   di_SInst_didisi_and             <"lsl",     int_hexagon_S2_lsl_r_p_and>;
3342 def HEXAGON_S2_lsr_r_p_and:
3343   di_SInst_didisi_and             <"lsr",     int_hexagon_S2_lsr_r_p_and>;
3344
3345 def HEXAGON_S2_asl_r_p_or:
3346   di_SInst_didisi_or              <"asl",     int_hexagon_S2_asl_r_p_or>;
3347 def HEXAGON_S2_asr_r_p_or:
3348   di_SInst_didisi_or              <"asr",     int_hexagon_S2_asr_r_p_or>;
3349 def HEXAGON_S2_lsl_r_p_or:
3350   di_SInst_didisi_or              <"lsl",     int_hexagon_S2_lsl_r_p_or>;
3351 def HEXAGON_S2_lsr_r_p_or:
3352   di_SInst_didisi_or              <"lsr",     int_hexagon_S2_lsr_r_p_or>;
3353
3354 // STYPE / SHIFT / Shift by register with saturation.
3355 def HEXAGON_S2_asl_r_r_sat:
3356   si_SInst_sisi_sat               <"asl",     int_hexagon_S2_asl_r_r_sat>;
3357 def HEXAGON_S2_asr_r_r_sat:
3358   si_SInst_sisi_sat               <"asr",     int_hexagon_S2_asr_r_r_sat>;
3359
3360 // STYPE / SHIFT / Table Index.
3361 def Hexagon_S2_tableidxb_goodsyntax:
3362   si_MInst_sisiu4u5          <"tableidxb",int_hexagon_S2_tableidxb_goodsyntax>;
3363 def Hexagon_S2_tableidxd_goodsyntax:
3364   si_MInst_sisiu4u5          <"tableidxd",int_hexagon_S2_tableidxd_goodsyntax>;
3365 def Hexagon_S2_tableidxh_goodsyntax:
3366   si_MInst_sisiu4u5          <"tableidxh",int_hexagon_S2_tableidxh_goodsyntax>;
3367 def Hexagon_S2_tableidxw_goodsyntax:
3368   si_MInst_sisiu4u5          <"tableidxw",int_hexagon_S2_tableidxw_goodsyntax>;
3369
3370
3371 /********************************************************************
3372 *            STYPE/VH                                               *
3373 *********************************************************************/
3374
3375 // STYPE / VH / Vector absolute value halfwords.
3376 // Rdd64=vabsh(Rss64)
3377 def HEXAGON_A2_vabsh:
3378   di_SInst_di                     <"vabsh",   int_hexagon_A2_vabsh>;
3379 def HEXAGON_A2_vabshsat:
3380   di_SInst_di_sat                 <"vabsh",   int_hexagon_A2_vabshsat>;
3381
3382 // STYPE / VH / Vector shift halfwords by immediate.
3383 // Rdd64=v[asl/asr/lsr]h(Rss64,Rt32)
3384 def HEXAGON_S2_asl_i_vh:
3385   di_SInst_disi                   <"vaslh",   int_hexagon_S2_asl_i_vh>;
3386 def HEXAGON_S2_asr_i_vh:
3387   di_SInst_disi                   <"vasrh",   int_hexagon_S2_asr_i_vh>;
3388 def HEXAGON_S2_lsr_i_vh:
3389   di_SInst_disi                   <"vlsrh",   int_hexagon_S2_lsr_i_vh>;
3390
3391 // STYPE / VH / Vector shift halfwords by register.
3392 // Rdd64=v[asl/asr/lsl/lsr]w(Rss64,Rt32)
3393 def HEXAGON_S2_asl_r_vh:
3394   di_SInst_disi                   <"vaslh",   int_hexagon_S2_asl_r_vh>;
3395 def HEXAGON_S2_asr_r_vh:
3396   di_SInst_disi                   <"vasrh",   int_hexagon_S2_asr_r_vh>;
3397 def HEXAGON_S2_lsl_r_vh:
3398   di_SInst_disi                   <"vlslh",   int_hexagon_S2_lsl_r_vh>;
3399 def HEXAGON_S2_lsr_r_vh:
3400   di_SInst_disi                   <"vlsrh",   int_hexagon_S2_lsr_r_vh>;
3401
3402
3403 /********************************************************************
3404 *            STYPE/VW                                               *
3405 *********************************************************************/
3406
3407 // STYPE / VW / Vector absolute value words.
3408 def HEXAGON_A2_vabsw:
3409   di_SInst_di                     <"vabsw",   int_hexagon_A2_vabsw>;
3410 def HEXAGON_A2_vabswsat:
3411   di_SInst_di_sat                 <"vabsw",   int_hexagon_A2_vabswsat>;
3412
3413 // STYPE / VW / Vector shift words by immediate.
3414 // Rdd64=v[asl/vsl]w(Rss64,Rt32)
3415 def HEXAGON_S2_asl_i_vw:
3416   di_SInst_disi                   <"vaslw",   int_hexagon_S2_asl_i_vw>;
3417 def HEXAGON_S2_asr_i_vw:
3418   di_SInst_disi                   <"vasrw",   int_hexagon_S2_asr_i_vw>;
3419 def HEXAGON_S2_lsr_i_vw:
3420   di_SInst_disi                   <"vlsrw",   int_hexagon_S2_lsr_i_vw>;
3421
3422 // STYPE / VW / Vector shift words by register.
3423 // Rdd64=v[asl/vsl]w(Rss64,Rt32)
3424 def HEXAGON_S2_asl_r_vw:
3425   di_SInst_disi                   <"vaslw",   int_hexagon_S2_asl_r_vw>;
3426 def HEXAGON_S2_asr_r_vw:
3427   di_SInst_disi                   <"vasrw",   int_hexagon_S2_asr_r_vw>;
3428 def HEXAGON_S2_lsl_r_vw:
3429   di_SInst_disi                   <"vlslw",   int_hexagon_S2_lsl_r_vw>;
3430 def HEXAGON_S2_lsr_r_vw:
3431   di_SInst_disi                   <"vlsrw",   int_hexagon_S2_lsr_r_vw>;
3432
3433 // STYPE / VW / Vector shift words with truncate and pack.
3434 def HEXAGON_S2_asr_r_svw_trun:
3435   si_SInst_disi                   <"vasrw",   int_hexagon_S2_asr_r_svw_trun>;
3436 def HEXAGON_S2_asr_i_svw_trun:
3437   si_SInst_diu5                   <"vasrw",   int_hexagon_S2_asr_i_svw_trun>;
3438
3439 // LD / Circular loads.
3440 def HEXAGON_circ_ldd:
3441   di_LDInstPI_diu4                <"circ_ldd", int_hexagon_circ_ldd>;
3442
3443 include "HexagonIntrinsicsV3.td"
3444 include "HexagonIntrinsicsV4.td"
3445 include "HexagonIntrinsicsV5.td"