lib/Target/Hexagon/HexagonIntrinsics.td

   1 //===-- HexagonIntrinsics.td - Instruction intrinsics ------*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 // This is populated based on the following specs:
  10 // Hexagon V2 Architecture
  11 // Application-Level Specification
  12 // 80-V9418-8 Rev. B
  13 // March 4, 2008
  14 //===----------------------------------------------------------------------===//
  15
  16 class T_I_pat <InstHexagon MI, Intrinsic IntID>
  17   : Pat <(IntID imm:$Is),
  18          (MI imm:$Is)>;
  19
  20 class T_R_pat <InstHexagon MI, Intrinsic IntID>
  21   : Pat <(IntID I32:$Rs),
  22          (MI I32:$Rs)>;
  23
  24 class T_P_pat <InstHexagon MI, Intrinsic IntID>
  25   : Pat <(IntID I64:$Rs),
  26          (MI DoubleRegs:$Rs)>;
  27
  28 class T_II_pat <InstHexagon MI, Intrinsic IntID, PatFrag Imm1, PatFrag Imm2>
  29   : Pat<(IntID Imm1:$Is, Imm2:$It),
  30         (MI Imm1:$Is, Imm2:$It)>;
  31
  32 class T_RI_pat <InstHexagon MI, Intrinsic IntID, PatLeaf ImmPred = PatLeaf<(i32 imm)>>
  33   : Pat<(IntID I32:$Rs, ImmPred:$It),
  34         (MI I32:$Rs, ImmPred:$It)>;
  35
  36 class T_IR_pat <InstHexagon MI, Intrinsic IntID, PatFrag ImmPred = PatLeaf<(i32 imm)>>
  37   : Pat<(IntID ImmPred:$Is, I32:$Rt),
  38         (MI ImmPred:$Is, I32:$Rt)>;
  39
  40 class T_PI_pat <InstHexagon MI, Intrinsic IntID>
  41   : Pat<(IntID I64:$Rs, imm:$It),
  42         (MI DoubleRegs:$Rs, imm:$It)>;
  43
  44 class T_RP_pat <InstHexagon MI, Intrinsic IntID>
  45   : Pat<(IntID I32:$Rs, I64:$Rt),
  46         (MI I32:$Rs, DoubleRegs:$Rt)>;
  47
  48 class T_RR_pat <InstHexagon MI, Intrinsic IntID>
  49   : Pat <(IntID I32:$Rs, I32:$Rt),
  50          (MI I32:$Rs, I32:$Rt)>;
  51
  52 class T_PP_pat <InstHexagon MI, Intrinsic IntID>
  53   : Pat <(IntID I64:$Rs, I64:$Rt),
  54          (MI DoubleRegs:$Rs, DoubleRegs:$Rt)>;
  55
  56 class T_QII_pat <InstHexagon MI, Intrinsic IntID, PatFrag Imm1, PatFrag Imm2>
  57   : Pat <(IntID (i32 PredRegs:$Ps), Imm1:$Is, Imm2:$It),
  58          (MI PredRegs:$Ps, Imm1:$Is, Imm2:$It)>;
  59
  60 class T_QRI_pat <InstHexagon MI, Intrinsic IntID, PatFrag ImmPred>
  61   : Pat <(IntID (i32 PredRegs:$Ps), I32:$Rs, ImmPred:$Is),
  62          (MI PredRegs:$Ps, I32:$Rs, ImmPred:$Is)>;
  63
  64 class T_QIR_pat <InstHexagon MI, Intrinsic IntID, PatFrag ImmPred>
  65   : Pat <(IntID (i32 PredRegs:$Ps), ImmPred:$Is, I32:$Rs),
  66          (MI PredRegs:$Ps, ImmPred:$Is, I32:$Rs)>;
  67
  68 class T_RRI_pat <InstHexagon MI, Intrinsic IntID>
  69   : Pat <(IntID I32:$Rs, I32:$Rt, imm:$Iu),
  70          (MI I32:$Rs, I32:$Rt, imm:$Iu)>;
  71
  72 class T_RII_pat <InstHexagon MI, Intrinsic IntID>
  73   : Pat <(IntID I32:$Rs, imm:$It, imm:$Iu),
  74          (MI I32:$Rs, imm:$It, imm:$Iu)>;
  75
  76 class T_IRI_pat <InstHexagon MI, Intrinsic IntID>
  77   : Pat <(IntID imm:$It, I32:$Rs, imm:$Iu),
  78          (MI imm:$It, I32:$Rs, imm:$Iu)>;
  79
  80 class T_IRR_pat <InstHexagon MI, Intrinsic IntID>
  81   : Pat <(IntID imm:$Is, I32:$Rs, I32:$Rt),
  82          (MI imm:$Is, I32:$Rs, I32:$Rt)>;
  83
  84 class T_RIR_pat <InstHexagon MI, Intrinsic IntID>
  85   : Pat <(IntID I32:$Rs, imm:$Is, I32:$Rt),
  86          (MI I32:$Rs, imm:$Is, I32:$Rt)>;
  87
  88 class T_RRR_pat <InstHexagon MI, Intrinsic IntID>
  89   : Pat <(IntID I32:$Rs, I32:$Rt, I32:$Ru),
  90          (MI I32:$Rs, I32:$Rt, I32:$Ru)>;
  91
  92 class T_PPI_pat <InstHexagon MI, Intrinsic IntID>
  93   : Pat <(IntID I64:$Rs, I64:$Rt, imm:$Iu),
  94          (MI DoubleRegs:$Rs, DoubleRegs:$Rt, imm:$Iu)>;
  95
  96 class T_PII_pat <InstHexagon MI, Intrinsic IntID>
  97   : Pat <(IntID I64:$Rs, imm:$It, imm:$Iu),
  98          (MI DoubleRegs:$Rs, imm:$It, imm:$Iu)>;
  99
 100 class T_PPP_pat <InstHexagon MI, Intrinsic IntID>
 101   : Pat <(IntID I64:$Rs, I64:$Rt, I64:$Ru),
 102          (MI DoubleRegs:$Rs, DoubleRegs:$Rt, DoubleRegs:$Ru)>;
 103
 104 class T_PPR_pat <InstHexagon MI, Intrinsic IntID>
 105   : Pat <(IntID I64:$Rs, I64:$Rt, I32:$Ru),
 106          (MI DoubleRegs:$Rs, DoubleRegs:$Rt, I32:$Ru)>;
 107
 108 class T_PRR_pat <InstHexagon MI, Intrinsic IntID>
 109   : Pat <(IntID I64:$Rs, I32:$Rt, I32:$Ru),
 110          (MI DoubleRegs:$Rs, I32:$Rt, I32:$Ru)>;
 111
 112 class T_PR_pat <InstHexagon MI, Intrinsic IntID>
 113   : Pat <(IntID I64:$Rs, I32:$Rt),
 114          (MI DoubleRegs:$Rs, I32:$Rt)>;
 115
 116 class T_D_pat <InstHexagon MI, Intrinsic IntID>
 117   : Pat<(IntID (F64:$Rs)),
 118         (MI (F64:$Rs))>;
 119
 120 class T_DI_pat <InstHexagon MI, Intrinsic IntID,
 121                 PatLeaf ImmPred = PatLeaf<(i32 imm)>>
 122   : Pat<(IntID F64:$Rs, ImmPred:$It),
 123         (MI F64:$Rs, ImmPred:$It)>;
 124
 125 class T_F_pat <InstHexagon MI, Intrinsic IntID>
 126   : Pat<(IntID F32:$Rs),
 127         (MI F32:$Rs)>;
 128
 129 class T_FI_pat <InstHexagon MI, Intrinsic IntID,
 130                  PatLeaf ImmPred = PatLeaf<(i32 imm)>>
 131   : Pat<(IntID F32:$Rs, ImmPred:$It),
 132         (MI F32:$Rs, ImmPred:$It)>;
 133
 134 class T_FF_pat <InstHexagon MI, Intrinsic IntID>
 135   : Pat<(IntID F32:$Rs, F32:$Rt),
 136         (MI F32:$Rs, F32:$Rt)>;
 137
 138 class T_DD_pat <InstHexagon MI, Intrinsic IntID>
 139   : Pat<(IntID F64:$Rs, F64:$Rt),
 140         (MI F64:$Rs, F64:$Rt)>;
 141
 142 class T_FFF_pat <InstHexagon MI, Intrinsic IntID>
 143   : Pat<(IntID F32:$Rs, F32:$Rt, F32:$Ru),
 144         (MI F32:$Rs, F32:$Rt, F32:$Ru)>;
 145
 146 class T_FFFQ_pat <InstHexagon MI, Intrinsic IntID>
 147   : Pat <(IntID F32:$Rs, F32:$Rt, F32:$Ru, (i32 PredRegs:$Rx)),
 148          (MI F32:$Rs, F32:$Rt, F32:$Ru, PredRegs:$Rx)>;
 149
 150 //===----------------------------------------------------------------------===//
 151 // MPYS / Multipy signed/unsigned halfwords
 152 //Rd=mpy[u](Rs.[H|L],Rt.[H|L])[:<<1][:rnd][:sat]
 153 //===----------------------------------------------------------------------===//
 154
 155 def : T_RR_pat <M2_mpy_ll_s1, int_hexagon_M2_mpy_ll_s1>;
 156 def : T_RR_pat <M2_mpy_ll_s0, int_hexagon_M2_mpy_ll_s0>;
 157 def : T_RR_pat <M2_mpy_lh_s1, int_hexagon_M2_mpy_lh_s1>;
 158 def : T_RR_pat <M2_mpy_lh_s0, int_hexagon_M2_mpy_lh_s0>;
 159 def : T_RR_pat <M2_mpy_hl_s1, int_hexagon_M2_mpy_hl_s1>;
 160 def : T_RR_pat <M2_mpy_hl_s0, int_hexagon_M2_mpy_hl_s0>;
 161 def : T_RR_pat <M2_mpy_hh_s1, int_hexagon_M2_mpy_hh_s1>;
 162 def : T_RR_pat <M2_mpy_hh_s0, int_hexagon_M2_mpy_hh_s0>;
 163
 164 def : T_RR_pat <M2_mpyu_ll_s1, int_hexagon_M2_mpyu_ll_s1>;
 165 def : T_RR_pat <M2_mpyu_ll_s0, int_hexagon_M2_mpyu_ll_s0>;
 166 def : T_RR_pat <M2_mpyu_lh_s1, int_hexagon_M2_mpyu_lh_s1>;
 167 def : T_RR_pat <M2_mpyu_lh_s0, int_hexagon_M2_mpyu_lh_s0>;
 168 def : T_RR_pat <M2_mpyu_hl_s1, int_hexagon_M2_mpyu_hl_s1>;
 169 def : T_RR_pat <M2_mpyu_hl_s0, int_hexagon_M2_mpyu_hl_s0>;
 170 def : T_RR_pat <M2_mpyu_hh_s1, int_hexagon_M2_mpyu_hh_s1>;
 171 def : T_RR_pat <M2_mpyu_hh_s0, int_hexagon_M2_mpyu_hh_s0>;
 172
 173 def : T_RR_pat <M2_mpy_sat_ll_s1, int_hexagon_M2_mpy_sat_ll_s1>;
 174 def : T_RR_pat <M2_mpy_sat_ll_s0, int_hexagon_M2_mpy_sat_ll_s0>;
 175 def : T_RR_pat <M2_mpy_sat_lh_s1, int_hexagon_M2_mpy_sat_lh_s1>;
 176 def : T_RR_pat <M2_mpy_sat_lh_s0, int_hexagon_M2_mpy_sat_lh_s0>;
 177 def : T_RR_pat <M2_mpy_sat_hl_s1, int_hexagon_M2_mpy_sat_hl_s1>;
 178 def : T_RR_pat <M2_mpy_sat_hl_s0, int_hexagon_M2_mpy_sat_hl_s0>;
 179 def : T_RR_pat <M2_mpy_sat_hh_s1, int_hexagon_M2_mpy_sat_hh_s1>;
 180 def : T_RR_pat <M2_mpy_sat_hh_s0, int_hexagon_M2_mpy_sat_hh_s0>;
 181
 182 def : T_RR_pat <M2_mpy_rnd_ll_s1, int_hexagon_M2_mpy_rnd_ll_s1>;
 183 def : T_RR_pat <M2_mpy_rnd_ll_s0, int_hexagon_M2_mpy_rnd_ll_s0>;
 184 def : T_RR_pat <M2_mpy_rnd_lh_s1, int_hexagon_M2_mpy_rnd_lh_s1>;
 185 def : T_RR_pat <M2_mpy_rnd_lh_s0, int_hexagon_M2_mpy_rnd_lh_s0>;
 186 def : T_RR_pat <M2_mpy_rnd_hl_s1, int_hexagon_M2_mpy_rnd_hl_s1>;
 187 def : T_RR_pat <M2_mpy_rnd_hl_s0, int_hexagon_M2_mpy_rnd_hl_s0>;
 188 def : T_RR_pat <M2_mpy_rnd_hh_s1, int_hexagon_M2_mpy_rnd_hh_s1>;
 189 def : T_RR_pat <M2_mpy_rnd_hh_s0, int_hexagon_M2_mpy_rnd_hh_s0>;
 190
 191 def : T_RR_pat <M2_mpy_sat_rnd_ll_s1, int_hexagon_M2_mpy_sat_rnd_ll_s1>;
 192 def : T_RR_pat <M2_mpy_sat_rnd_ll_s0, int_hexagon_M2_mpy_sat_rnd_ll_s0>;
 193 def : T_RR_pat <M2_mpy_sat_rnd_lh_s1, int_hexagon_M2_mpy_sat_rnd_lh_s1>;
 194 def : T_RR_pat <M2_mpy_sat_rnd_lh_s0, int_hexagon_M2_mpy_sat_rnd_lh_s0>;
 195 def : T_RR_pat <M2_mpy_sat_rnd_hl_s1, int_hexagon_M2_mpy_sat_rnd_hl_s1>;
 196 def : T_RR_pat <M2_mpy_sat_rnd_hl_s0, int_hexagon_M2_mpy_sat_rnd_hl_s0>;
 197 def : T_RR_pat <M2_mpy_sat_rnd_hh_s1, int_hexagon_M2_mpy_sat_rnd_hh_s1>;
 198 def : T_RR_pat <M2_mpy_sat_rnd_hh_s0, int_hexagon_M2_mpy_sat_rnd_hh_s0>;
 199
 200
 201 //===----------------------------------------------------------------------===//
 202 // MPYS / Multipy signed/unsigned halfwords and add/subtract the
 203 // result from the accumulator.
 204 //Rx [-+]= mpy[u](Rs.[H|L],Rt.[H|L])[:<<1][:sat]
 205 //===----------------------------------------------------------------------===//
 206
 207 def : T_RRR_pat <M2_mpy_acc_ll_s1, int_hexagon_M2_mpy_acc_ll_s1>;
 208 def : T_RRR_pat <M2_mpy_acc_ll_s0, int_hexagon_M2_mpy_acc_ll_s0>;
 209 def : T_RRR_pat <M2_mpy_acc_lh_s1, int_hexagon_M2_mpy_acc_lh_s1>;
 210 def : T_RRR_pat <M2_mpy_acc_lh_s0, int_hexagon_M2_mpy_acc_lh_s0>;
 211 def : T_RRR_pat <M2_mpy_acc_hl_s1, int_hexagon_M2_mpy_acc_hl_s1>;
 212 def : T_RRR_pat <M2_mpy_acc_hl_s0, int_hexagon_M2_mpy_acc_hl_s0>;
 213 def : T_RRR_pat <M2_mpy_acc_hh_s1, int_hexagon_M2_mpy_acc_hh_s1>;
 214 def : T_RRR_pat <M2_mpy_acc_hh_s0, int_hexagon_M2_mpy_acc_hh_s0>;
 215
 216 def : T_RRR_pat <M2_mpyu_acc_ll_s1, int_hexagon_M2_mpyu_acc_ll_s1>;
 217 def : T_RRR_pat <M2_mpyu_acc_ll_s0, int_hexagon_M2_mpyu_acc_ll_s0>;
 218 def : T_RRR_pat <M2_mpyu_acc_lh_s1, int_hexagon_M2_mpyu_acc_lh_s1>;
 219 def : T_RRR_pat <M2_mpyu_acc_lh_s0, int_hexagon_M2_mpyu_acc_lh_s0>;
 220 def : T_RRR_pat <M2_mpyu_acc_hl_s1, int_hexagon_M2_mpyu_acc_hl_s1>;
 221 def : T_RRR_pat <M2_mpyu_acc_hl_s0, int_hexagon_M2_mpyu_acc_hl_s0>;
 222 def : T_RRR_pat <M2_mpyu_acc_hh_s1, int_hexagon_M2_mpyu_acc_hh_s1>;
 223 def : T_RRR_pat <M2_mpyu_acc_hh_s0, int_hexagon_M2_mpyu_acc_hh_s0>;
 224
 225 def : T_RRR_pat <M2_mpy_nac_ll_s1, int_hexagon_M2_mpy_nac_ll_s1>;
 226 def : T_RRR_pat <M2_mpy_nac_ll_s0, int_hexagon_M2_mpy_nac_ll_s0>;
 227 def : T_RRR_pat <M2_mpy_nac_lh_s1, int_hexagon_M2_mpy_nac_lh_s1>;
 228 def : T_RRR_pat <M2_mpy_nac_lh_s0, int_hexagon_M2_mpy_nac_lh_s0>;
 229 def : T_RRR_pat <M2_mpy_nac_hl_s1, int_hexagon_M2_mpy_nac_hl_s1>;
 230 def : T_RRR_pat <M2_mpy_nac_hl_s0, int_hexagon_M2_mpy_nac_hl_s0>;
 231 def : T_RRR_pat <M2_mpy_nac_hh_s1, int_hexagon_M2_mpy_nac_hh_s1>;
 232 def : T_RRR_pat <M2_mpy_nac_hh_s0, int_hexagon_M2_mpy_nac_hh_s0>;
 233
 234 def : T_RRR_pat <M2_mpyu_nac_ll_s1, int_hexagon_M2_mpyu_nac_ll_s1>;
 235 def : T_RRR_pat <M2_mpyu_nac_ll_s0, int_hexagon_M2_mpyu_nac_ll_s0>;
 236 def : T_RRR_pat <M2_mpyu_nac_lh_s1, int_hexagon_M2_mpyu_nac_lh_s1>;
 237 def : T_RRR_pat <M2_mpyu_nac_lh_s0, int_hexagon_M2_mpyu_nac_lh_s0>;
 238 def : T_RRR_pat <M2_mpyu_nac_hl_s1, int_hexagon_M2_mpyu_nac_hl_s1>;
 239 def : T_RRR_pat <M2_mpyu_nac_hl_s0, int_hexagon_M2_mpyu_nac_hl_s0>;
 240 def : T_RRR_pat <M2_mpyu_nac_hh_s1, int_hexagon_M2_mpyu_nac_hh_s1>;
 241 def : T_RRR_pat <M2_mpyu_nac_hh_s0, int_hexagon_M2_mpyu_nac_hh_s0>;
 242
 243 def : T_RRR_pat <M2_mpy_acc_sat_ll_s1, int_hexagon_M2_mpy_acc_sat_ll_s1>;
 244 def : T_RRR_pat <M2_mpy_acc_sat_ll_s0, int_hexagon_M2_mpy_acc_sat_ll_s0>;
 245 def : T_RRR_pat <M2_mpy_acc_sat_lh_s1, int_hexagon_M2_mpy_acc_sat_lh_s1>;
 246 def : T_RRR_pat <M2_mpy_acc_sat_lh_s0, int_hexagon_M2_mpy_acc_sat_lh_s0>;
 247 def : T_RRR_pat <M2_mpy_acc_sat_hl_s1, int_hexagon_M2_mpy_acc_sat_hl_s1>;
 248 def : T_RRR_pat <M2_mpy_acc_sat_hl_s0, int_hexagon_M2_mpy_acc_sat_hl_s0>;
 249 def : T_RRR_pat <M2_mpy_acc_sat_hh_s1, int_hexagon_M2_mpy_acc_sat_hh_s1>;
 250 def : T_RRR_pat <M2_mpy_acc_sat_hh_s0, int_hexagon_M2_mpy_acc_sat_hh_s0>;
 251
 252 def : T_RRR_pat <M2_mpy_nac_sat_ll_s1, int_hexagon_M2_mpy_nac_sat_ll_s1>;
 253 def : T_RRR_pat <M2_mpy_nac_sat_ll_s0, int_hexagon_M2_mpy_nac_sat_ll_s0>;
 254 def : T_RRR_pat <M2_mpy_nac_sat_lh_s1, int_hexagon_M2_mpy_nac_sat_lh_s1>;
 255 def : T_RRR_pat <M2_mpy_nac_sat_lh_s0, int_hexagon_M2_mpy_nac_sat_lh_s0>;
 256 def : T_RRR_pat <M2_mpy_nac_sat_hl_s1, int_hexagon_M2_mpy_nac_sat_hl_s1>;
 257 def : T_RRR_pat <M2_mpy_nac_sat_hl_s0, int_hexagon_M2_mpy_nac_sat_hl_s0>;
 258 def : T_RRR_pat <M2_mpy_nac_sat_hh_s1, int_hexagon_M2_mpy_nac_sat_hh_s1>;
 259 def : T_RRR_pat <M2_mpy_nac_sat_hh_s0, int_hexagon_M2_mpy_nac_sat_hh_s0>;
 260
 261
 262 //===----------------------------------------------------------------------===//
 263 // Multiply signed/unsigned halfwords with and without saturation and rounding
 264 // into a 64-bits destination register.
 265 //===----------------------------------------------------------------------===//
 266
 267 def : T_RR_pat <M2_mpyd_hh_s0, int_hexagon_M2_mpyd_hh_s0>;
 268 def : T_RR_pat <M2_mpyd_hl_s0, int_hexagon_M2_mpyd_hl_s0>;
 269 def : T_RR_pat <M2_mpyd_lh_s0, int_hexagon_M2_mpyd_lh_s0>;
 270 def : T_RR_pat <M2_mpyd_ll_s0, int_hexagon_M2_mpyd_ll_s0>;
 271 def : T_RR_pat <M2_mpyd_hh_s1, int_hexagon_M2_mpyd_hh_s1>;
 272 def : T_RR_pat <M2_mpyd_hl_s1, int_hexagon_M2_mpyd_hl_s1>;
 273 def : T_RR_pat <M2_mpyd_lh_s1, int_hexagon_M2_mpyd_lh_s1>;
 274 def : T_RR_pat <M2_mpyd_ll_s1, int_hexagon_M2_mpyd_ll_s1>;
 275
 276 def : T_RR_pat <M2_mpyd_rnd_hh_s0, int_hexagon_M2_mpyd_rnd_hh_s0>;
 277 def : T_RR_pat <M2_mpyd_rnd_hl_s0, int_hexagon_M2_mpyd_rnd_hl_s0>;
 278 def : T_RR_pat <M2_mpyd_rnd_lh_s0, int_hexagon_M2_mpyd_rnd_lh_s0>;
 279 def : T_RR_pat <M2_mpyd_rnd_ll_s0, int_hexagon_M2_mpyd_rnd_ll_s0>;
 280 def : T_RR_pat <M2_mpyd_rnd_hh_s1, int_hexagon_M2_mpyd_rnd_hh_s1>;
 281 def : T_RR_pat <M2_mpyd_rnd_hl_s1, int_hexagon_M2_mpyd_rnd_hl_s1>;
 282 def : T_RR_pat <M2_mpyd_rnd_lh_s1, int_hexagon_M2_mpyd_rnd_lh_s1>;
 283 def : T_RR_pat <M2_mpyd_rnd_ll_s1, int_hexagon_M2_mpyd_rnd_ll_s1>;
 284
 285 def : T_RR_pat <M2_mpyud_hh_s0, int_hexagon_M2_mpyud_hh_s0>;
 286 def : T_RR_pat <M2_mpyud_hl_s0, int_hexagon_M2_mpyud_hl_s0>;
 287 def : T_RR_pat <M2_mpyud_lh_s0, int_hexagon_M2_mpyud_lh_s0>;
 288 def : T_RR_pat <M2_mpyud_ll_s0, int_hexagon_M2_mpyud_ll_s0>;
 289 def : T_RR_pat <M2_mpyud_hh_s1, int_hexagon_M2_mpyud_hh_s1>;
 290 def : T_RR_pat <M2_mpyud_hl_s1, int_hexagon_M2_mpyud_hl_s1>;
 291 def : T_RR_pat <M2_mpyud_lh_s1, int_hexagon_M2_mpyud_lh_s1>;
 292 def : T_RR_pat <M2_mpyud_ll_s1, int_hexagon_M2_mpyud_ll_s1>;
 293
 294 //===----------------------------------------------------------------------===//
 295 // MPYS / Multipy signed/unsigned halfwords and add/subtract the
 296 // result from the 64-bit destination register.
 297 //Rxx [-+]= mpy[u](Rs.[H|L],Rt.[H|L])[:<<1][:sat]
 298 //===----------------------------------------------------------------------===//
 299
 300 def : T_PRR_pat <M2_mpyd_acc_hh_s0, int_hexagon_M2_mpyd_acc_hh_s0>;
 301 def : T_PRR_pat <M2_mpyd_acc_hl_s0, int_hexagon_M2_mpyd_acc_hl_s0>;
 302 def : T_PRR_pat <M2_mpyd_acc_lh_s0, int_hexagon_M2_mpyd_acc_lh_s0>;
 303 def : T_PRR_pat <M2_mpyd_acc_ll_s0, int_hexagon_M2_mpyd_acc_ll_s0>;
 304
 305 def : T_PRR_pat <M2_mpyd_acc_hh_s1, int_hexagon_M2_mpyd_acc_hh_s1>;
 306 def : T_PRR_pat <M2_mpyd_acc_hl_s1, int_hexagon_M2_mpyd_acc_hl_s1>;
 307 def : T_PRR_pat <M2_mpyd_acc_lh_s1, int_hexagon_M2_mpyd_acc_lh_s1>;
 308 def : T_PRR_pat <M2_mpyd_acc_ll_s1, int_hexagon_M2_mpyd_acc_ll_s1>;
 309
 310 def : T_PRR_pat <M2_mpyd_nac_hh_s0, int_hexagon_M2_mpyd_nac_hh_s0>;
 311 def : T_PRR_pat <M2_mpyd_nac_hl_s0, int_hexagon_M2_mpyd_nac_hl_s0>;
 312 def : T_PRR_pat <M2_mpyd_nac_lh_s0, int_hexagon_M2_mpyd_nac_lh_s0>;
 313 def : T_PRR_pat <M2_mpyd_nac_ll_s0, int_hexagon_M2_mpyd_nac_ll_s0>;
 314
 315 def : T_PRR_pat <M2_mpyd_nac_hh_s1, int_hexagon_M2_mpyd_nac_hh_s1>;
 316 def : T_PRR_pat <M2_mpyd_nac_hl_s1, int_hexagon_M2_mpyd_nac_hl_s1>;
 317 def : T_PRR_pat <M2_mpyd_nac_lh_s1, int_hexagon_M2_mpyd_nac_lh_s1>;
 318 def : T_PRR_pat <M2_mpyd_nac_ll_s1, int_hexagon_M2_mpyd_nac_ll_s1>;
 319
 320 def : T_PRR_pat <M2_mpyud_acc_hh_s0, int_hexagon_M2_mpyud_acc_hh_s0>;
 321 def : T_PRR_pat <M2_mpyud_acc_hl_s0, int_hexagon_M2_mpyud_acc_hl_s0>;
 322 def : T_PRR_pat <M2_mpyud_acc_lh_s0, int_hexagon_M2_mpyud_acc_lh_s0>;
 323 def : T_PRR_pat <M2_mpyud_acc_ll_s0, int_hexagon_M2_mpyud_acc_ll_s0>;
 324
 325 def : T_PRR_pat <M2_mpyud_acc_hh_s1, int_hexagon_M2_mpyud_acc_hh_s1>;
 326 def : T_PRR_pat <M2_mpyud_acc_hl_s1, int_hexagon_M2_mpyud_acc_hl_s1>;
 327 def : T_PRR_pat <M2_mpyud_acc_lh_s1, int_hexagon_M2_mpyud_acc_lh_s1>;
 328 def : T_PRR_pat <M2_mpyud_acc_ll_s1, int_hexagon_M2_mpyud_acc_ll_s1>;
 329
 330 def : T_PRR_pat <M2_mpyud_nac_hh_s0, int_hexagon_M2_mpyud_nac_hh_s0>;
 331 def : T_PRR_pat <M2_mpyud_nac_hl_s0, int_hexagon_M2_mpyud_nac_hl_s0>;
 332 def : T_PRR_pat <M2_mpyud_nac_lh_s0, int_hexagon_M2_mpyud_nac_lh_s0>;
 333 def : T_PRR_pat <M2_mpyud_nac_ll_s0, int_hexagon_M2_mpyud_nac_ll_s0>;
 334
 335 def : T_PRR_pat <M2_mpyud_nac_hh_s1, int_hexagon_M2_mpyud_nac_hh_s1>;
 336 def : T_PRR_pat <M2_mpyud_nac_hl_s1, int_hexagon_M2_mpyud_nac_hl_s1>;
 337 def : T_PRR_pat <M2_mpyud_nac_lh_s1, int_hexagon_M2_mpyud_nac_lh_s1>;
 338 def : T_PRR_pat <M2_mpyud_nac_ll_s1, int_hexagon_M2_mpyud_nac_ll_s1>;
 339
 340
 341 //===----------------------------------------------------------------------===//
 342 // Add/Subtract halfword
 343 // Rd=add(Rt.L,Rs.[HL])[:sat]
 344 // Rd=sub(Rt.L,Rs.[HL])[:sat]
 345 // Rd=add(Rt.[LH],Rs.[HL])[:sat][:<16]
 346 // Rd=sub(Rt.[LH],Rs.[HL])[:sat][:<16]
 347 //===----------------------------------------------------------------------===//
 348
 349 //Rd=add(Rt.L,Rs.[LH])
 350 def : T_RR_pat <A2_addh_l16_ll,     int_hexagon_A2_addh_l16_ll>;
 351 def : T_RR_pat <A2_addh_l16_hl,     int_hexagon_A2_addh_l16_hl>;
 352
 353 //Rd=add(Rt.L,Rs.[LH]):sat
 354 def : T_RR_pat <A2_addh_l16_sat_ll, int_hexagon_A2_addh_l16_sat_ll>;
 355 def : T_RR_pat <A2_addh_l16_sat_hl, int_hexagon_A2_addh_l16_sat_hl>;
 356
 357 //Rd=sub(Rt.L,Rs.[LH])
 358 def : T_RR_pat <A2_subh_l16_ll,     int_hexagon_A2_subh_l16_ll>;
 359 def : T_RR_pat <A2_subh_l16_hl,     int_hexagon_A2_subh_l16_hl>;
 360
 361 //Rd=sub(Rt.L,Rs.[LH]):sat
 362 def : T_RR_pat <A2_subh_l16_sat_ll, int_hexagon_A2_subh_l16_sat_ll>;
 363 def : T_RR_pat <A2_subh_l16_sat_hl, int_hexagon_A2_subh_l16_sat_hl>;
 364
 365 //Rd=add(Rt.[LH],Rs.[LH]):<<16
 366 def : T_RR_pat <A2_addh_h16_ll,     int_hexagon_A2_addh_h16_ll>;
 367 def : T_RR_pat <A2_addh_h16_lh,     int_hexagon_A2_addh_h16_lh>;
 368 def : T_RR_pat <A2_addh_h16_hl,     int_hexagon_A2_addh_h16_hl>;
 369 def : T_RR_pat <A2_addh_h16_hh,     int_hexagon_A2_addh_h16_hh>;
 370
 371 //Rd=sub(Rt.[LH],Rs.[LH]):<<16
 372 def : T_RR_pat <A2_subh_h16_ll,     int_hexagon_A2_subh_h16_ll>;
 373 def : T_RR_pat <A2_subh_h16_lh,     int_hexagon_A2_subh_h16_lh>;
 374 def : T_RR_pat <A2_subh_h16_hl,     int_hexagon_A2_subh_h16_hl>;
 375 def : T_RR_pat <A2_subh_h16_hh,     int_hexagon_A2_subh_h16_hh>;
 376
 377 //Rd=add(Rt.[LH],Rs.[LH]):sat:<<16
 378 def : T_RR_pat <A2_addh_h16_sat_ll, int_hexagon_A2_addh_h16_sat_ll>;
 379 def : T_RR_pat <A2_addh_h16_sat_lh, int_hexagon_A2_addh_h16_sat_lh>;
 380 def : T_RR_pat <A2_addh_h16_sat_hl, int_hexagon_A2_addh_h16_sat_hl>;
 381 def : T_RR_pat <A2_addh_h16_sat_hh, int_hexagon_A2_addh_h16_sat_hh>;
 382
 383 //Rd=sub(Rt.[LH],Rs.[LH]):sat:<<16
 384 def : T_RR_pat <A2_subh_h16_sat_ll, int_hexagon_A2_subh_h16_sat_ll>;
 385 def : T_RR_pat <A2_subh_h16_sat_lh, int_hexagon_A2_subh_h16_sat_lh>;
 386 def : T_RR_pat <A2_subh_h16_sat_hl, int_hexagon_A2_subh_h16_sat_hl>;
 387 def : T_RR_pat <A2_subh_h16_sat_hh, int_hexagon_A2_subh_h16_sat_hh>;
 388
 389 // ALU64 / ALU / min max
 390 def : T_RR_pat<A2_max,  int_hexagon_A2_max>;
 391 def : T_RR_pat<A2_min,  int_hexagon_A2_min>;
 392 def : T_RR_pat<A2_maxu, int_hexagon_A2_maxu>;
 393 def : T_RR_pat<A2_minu, int_hexagon_A2_minu>;
 394
 395 // Shift and accumulate
 396 def : T_RRI_pat <S2_asr_i_r_nac,  int_hexagon_S2_asr_i_r_nac>;
 397 def : T_RRI_pat <S2_lsr_i_r_nac,  int_hexagon_S2_lsr_i_r_nac>;
 398 def : T_RRI_pat <S2_asl_i_r_nac,  int_hexagon_S2_asl_i_r_nac>;
 399 def : T_RRI_pat <S2_asr_i_r_acc,  int_hexagon_S2_asr_i_r_acc>;
 400 def : T_RRI_pat <S2_lsr_i_r_acc,  int_hexagon_S2_lsr_i_r_acc>;
 401 def : T_RRI_pat <S2_asl_i_r_acc,  int_hexagon_S2_asl_i_r_acc>;
 402
 403 def : T_RRI_pat <S2_asr_i_r_and,  int_hexagon_S2_asr_i_r_and>;
 404 def : T_RRI_pat <S2_lsr_i_r_and,  int_hexagon_S2_lsr_i_r_and>;
 405 def : T_RRI_pat <S2_asl_i_r_and,  int_hexagon_S2_asl_i_r_and>;
 406 def : T_RRI_pat <S2_asr_i_r_or,   int_hexagon_S2_asr_i_r_or>;
 407 def : T_RRI_pat <S2_lsr_i_r_or,   int_hexagon_S2_lsr_i_r_or>;
 408 def : T_RRI_pat <S2_asl_i_r_or,   int_hexagon_S2_asl_i_r_or>;
 409 def : T_RRI_pat <S2_lsr_i_r_xacc, int_hexagon_S2_lsr_i_r_xacc>;
 410 def : T_RRI_pat <S2_asl_i_r_xacc, int_hexagon_S2_asl_i_r_xacc>;
 411
 412 def : T_PPI_pat <S2_asr_i_p_nac,  int_hexagon_S2_asr_i_p_nac>;
 413 def : T_PPI_pat <S2_lsr_i_p_nac,  int_hexagon_S2_lsr_i_p_nac>;
 414 def : T_PPI_pat <S2_asl_i_p_nac,  int_hexagon_S2_asl_i_p_nac>;
 415 def : T_PPI_pat <S2_asr_i_p_acc,  int_hexagon_S2_asr_i_p_acc>;
 416 def : T_PPI_pat <S2_lsr_i_p_acc,  int_hexagon_S2_lsr_i_p_acc>;
 417 def : T_PPI_pat <S2_asl_i_p_acc,  int_hexagon_S2_asl_i_p_acc>;
 418
 419 def : T_PPI_pat <S2_asr_i_p_and,  int_hexagon_S2_asr_i_p_and>;
 420 def : T_PPI_pat <S2_lsr_i_p_and,  int_hexagon_S2_lsr_i_p_and>;
 421 def : T_PPI_pat <S2_asl_i_p_and,  int_hexagon_S2_asl_i_p_and>;
 422 def : T_PPI_pat <S2_asr_i_p_or,   int_hexagon_S2_asr_i_p_or>;
 423 def : T_PPI_pat <S2_lsr_i_p_or,   int_hexagon_S2_lsr_i_p_or>;
 424 def : T_PPI_pat <S2_asl_i_p_or,   int_hexagon_S2_asl_i_p_or>;
 425 def : T_PPI_pat <S2_lsr_i_p_xacc, int_hexagon_S2_lsr_i_p_xacc>;
 426 def : T_PPI_pat <S2_asl_i_p_xacc, int_hexagon_S2_asl_i_p_xacc>;
 427
 428 def : T_RRR_pat <S2_asr_r_r_nac,  int_hexagon_S2_asr_r_r_nac>;
 429 def : T_RRR_pat <S2_lsr_r_r_nac,  int_hexagon_S2_lsr_r_r_nac>;
 430 def : T_RRR_pat <S2_asl_r_r_nac,  int_hexagon_S2_asl_r_r_nac>;
 431 def : T_RRR_pat <S2_lsl_r_r_nac,  int_hexagon_S2_lsl_r_r_nac>;
 432 def : T_RRR_pat <S2_asr_r_r_acc,  int_hexagon_S2_asr_r_r_acc>;
 433 def : T_RRR_pat <S2_lsr_r_r_acc,  int_hexagon_S2_lsr_r_r_acc>;
 434 def : T_RRR_pat <S2_asl_r_r_acc,  int_hexagon_S2_asl_r_r_acc>;
 435 def : T_RRR_pat <S2_lsl_r_r_acc,  int_hexagon_S2_lsl_r_r_acc>;
 436
 437 def : T_RRR_pat <S2_asr_r_r_and,  int_hexagon_S2_asr_r_r_and>;
 438 def : T_RRR_pat <S2_lsr_r_r_and,  int_hexagon_S2_lsr_r_r_and>;
 439 def : T_RRR_pat <S2_asl_r_r_and,  int_hexagon_S2_asl_r_r_and>;
 440 def : T_RRR_pat <S2_lsl_r_r_and,  int_hexagon_S2_lsl_r_r_and>;
 441 def : T_RRR_pat <S2_asr_r_r_or,   int_hexagon_S2_asr_r_r_or>;
 442 def : T_RRR_pat <S2_lsr_r_r_or,   int_hexagon_S2_lsr_r_r_or>;
 443 def : T_RRR_pat <S2_asl_r_r_or,   int_hexagon_S2_asl_r_r_or>;
 444 def : T_RRR_pat <S2_lsl_r_r_or,   int_hexagon_S2_lsl_r_r_or>;
 445
 446 def : T_PPR_pat <S2_asr_r_p_nac,  int_hexagon_S2_asr_r_p_nac>;
 447 def : T_PPR_pat <S2_lsr_r_p_nac,  int_hexagon_S2_lsr_r_p_nac>;
 448 def : T_PPR_pat <S2_asl_r_p_nac,  int_hexagon_S2_asl_r_p_nac>;
 449 def : T_PPR_pat <S2_lsl_r_p_nac,  int_hexagon_S2_lsl_r_p_nac>;
 450 def : T_PPR_pat <S2_asr_r_p_acc,  int_hexagon_S2_asr_r_p_acc>;
 451 def : T_PPR_pat <S2_lsr_r_p_acc,  int_hexagon_S2_lsr_r_p_acc>;
 452 def : T_PPR_pat <S2_asl_r_p_acc,  int_hexagon_S2_asl_r_p_acc>;
 453 def : T_PPR_pat <S2_lsl_r_p_acc,  int_hexagon_S2_lsl_r_p_acc>;
 454
 455 def : T_PPR_pat <S2_asr_r_p_and,  int_hexagon_S2_asr_r_p_and>;
 456 def : T_PPR_pat <S2_lsr_r_p_and,  int_hexagon_S2_lsr_r_p_and>;
 457 def : T_PPR_pat <S2_asl_r_p_and,  int_hexagon_S2_asl_r_p_and>;
 458 def : T_PPR_pat <S2_lsl_r_p_and,  int_hexagon_S2_lsl_r_p_and>;
 459 def : T_PPR_pat <S2_asr_r_p_or,   int_hexagon_S2_asr_r_p_or>;
 460 def : T_PPR_pat <S2_lsr_r_p_or,   int_hexagon_S2_lsr_r_p_or>;
 461 def : T_PPR_pat <S2_asl_r_p_or,   int_hexagon_S2_asl_r_p_or>;
 462 def : T_PPR_pat <S2_lsl_r_p_or,   int_hexagon_S2_lsl_r_p_or>;
 463
 464 def : T_RRI_pat <S2_asr_i_r_nac,  int_hexagon_S2_asr_i_r_nac>;
 465 def : T_RRI_pat <S2_lsr_i_r_nac,  int_hexagon_S2_lsr_i_r_nac>;
 466 def : T_RRI_pat <S2_asl_i_r_nac,  int_hexagon_S2_asl_i_r_nac>;
 467 def : T_RRI_pat <S2_asr_i_r_acc,  int_hexagon_S2_asr_i_r_acc>;
 468 def : T_RRI_pat <S2_lsr_i_r_acc,  int_hexagon_S2_lsr_i_r_acc>;
 469 def : T_RRI_pat <S2_asl_i_r_acc,  int_hexagon_S2_asl_i_r_acc>;
 470
 471 def : T_RRI_pat <S2_asr_i_r_and,  int_hexagon_S2_asr_i_r_and>;
 472 def : T_RRI_pat <S2_lsr_i_r_and,  int_hexagon_S2_lsr_i_r_and>;
 473 def : T_RRI_pat <S2_asl_i_r_and,  int_hexagon_S2_asl_i_r_and>;
 474 def : T_RRI_pat <S2_asr_i_r_or,   int_hexagon_S2_asr_i_r_or>;
 475 def : T_RRI_pat <S2_lsr_i_r_or,   int_hexagon_S2_lsr_i_r_or>;
 476 def : T_RRI_pat <S2_asl_i_r_or,   int_hexagon_S2_asl_i_r_or>;
 477 def : T_RRI_pat <S2_lsr_i_r_xacc, int_hexagon_S2_lsr_i_r_xacc>;
 478 def : T_RRI_pat <S2_asl_i_r_xacc, int_hexagon_S2_asl_i_r_xacc>;
 479
 480 def : T_PPI_pat <S2_asr_i_p_nac,  int_hexagon_S2_asr_i_p_nac>;
 481 def : T_PPI_pat <S2_lsr_i_p_nac,  int_hexagon_S2_lsr_i_p_nac>;
 482 def : T_PPI_pat <S2_asl_i_p_nac,  int_hexagon_S2_asl_i_p_nac>;
 483 def : T_PPI_pat <S2_asr_i_p_acc,  int_hexagon_S2_asr_i_p_acc>;
 484 def : T_PPI_pat <S2_lsr_i_p_acc,  int_hexagon_S2_lsr_i_p_acc>;
 485 def : T_PPI_pat <S2_asl_i_p_acc,  int_hexagon_S2_asl_i_p_acc>;
 486
 487 def : T_PPI_pat <S2_asr_i_p_and,  int_hexagon_S2_asr_i_p_and>;
 488 def : T_PPI_pat <S2_lsr_i_p_and,  int_hexagon_S2_lsr_i_p_and>;
 489 def : T_PPI_pat <S2_asl_i_p_and,  int_hexagon_S2_asl_i_p_and>;
 490 def : T_PPI_pat <S2_asr_i_p_or,   int_hexagon_S2_asr_i_p_or>;
 491 def : T_PPI_pat <S2_lsr_i_p_or,   int_hexagon_S2_lsr_i_p_or>;
 492 def : T_PPI_pat <S2_asl_i_p_or,   int_hexagon_S2_asl_i_p_or>;
 493 def : T_PPI_pat <S2_lsr_i_p_xacc, int_hexagon_S2_lsr_i_p_xacc>;
 494 def : T_PPI_pat <S2_asl_i_p_xacc, int_hexagon_S2_asl_i_p_xacc>;
 495
 496 def : T_RRR_pat <S2_asr_r_r_nac,  int_hexagon_S2_asr_r_r_nac>;
 497 def : T_RRR_pat <S2_lsr_r_r_nac,  int_hexagon_S2_lsr_r_r_nac>;
 498 def : T_RRR_pat <S2_asl_r_r_nac,  int_hexagon_S2_asl_r_r_nac>;
 499 def : T_RRR_pat <S2_lsl_r_r_nac,  int_hexagon_S2_lsl_r_r_nac>;
 500 def : T_RRR_pat <S2_asr_r_r_acc,  int_hexagon_S2_asr_r_r_acc>;
 501 def : T_RRR_pat <S2_lsr_r_r_acc,  int_hexagon_S2_lsr_r_r_acc>;
 502 def : T_RRR_pat <S2_asl_r_r_acc,  int_hexagon_S2_asl_r_r_acc>;
 503 def : T_RRR_pat <S2_lsl_r_r_acc,  int_hexagon_S2_lsl_r_r_acc>;
 504
 505 def : T_RRR_pat <S2_asr_r_r_and,  int_hexagon_S2_asr_r_r_and>;
 506 def : T_RRR_pat <S2_lsr_r_r_and,  int_hexagon_S2_lsr_r_r_and>;
 507 def : T_RRR_pat <S2_asl_r_r_and,  int_hexagon_S2_asl_r_r_and>;
 508 def : T_RRR_pat <S2_lsl_r_r_and,  int_hexagon_S2_lsl_r_r_and>;
 509 def : T_RRR_pat <S2_asr_r_r_or,   int_hexagon_S2_asr_r_r_or>;
 510 def : T_RRR_pat <S2_lsr_r_r_or,   int_hexagon_S2_lsr_r_r_or>;
 511 def : T_RRR_pat <S2_asl_r_r_or,   int_hexagon_S2_asl_r_r_or>;
 512 def : T_RRR_pat <S2_lsl_r_r_or,   int_hexagon_S2_lsl_r_r_or>;
 513
 514 def : T_PPR_pat <S2_asr_r_p_nac,  int_hexagon_S2_asr_r_p_nac>;
 515 def : T_PPR_pat <S2_lsr_r_p_nac,  int_hexagon_S2_lsr_r_p_nac>;
 516 def : T_PPR_pat <S2_asl_r_p_nac,  int_hexagon_S2_asl_r_p_nac>;
 517 def : T_PPR_pat <S2_lsl_r_p_nac,  int_hexagon_S2_lsl_r_p_nac>;
 518 def : T_PPR_pat <S2_asr_r_p_acc,  int_hexagon_S2_asr_r_p_acc>;
 519 def : T_PPR_pat <S2_lsr_r_p_acc,  int_hexagon_S2_lsr_r_p_acc>;
 520 def : T_PPR_pat <S2_asl_r_p_acc,  int_hexagon_S2_asl_r_p_acc>;
 521 def : T_PPR_pat <S2_lsl_r_p_acc,  int_hexagon_S2_lsl_r_p_acc>;
 522
 523 def : T_PPR_pat <S2_asr_r_p_and,  int_hexagon_S2_asr_r_p_and>;
 524 def : T_PPR_pat <S2_lsr_r_p_and,  int_hexagon_S2_lsr_r_p_and>;
 525 def : T_PPR_pat <S2_asl_r_p_and,  int_hexagon_S2_asl_r_p_and>;
 526 def : T_PPR_pat <S2_lsl_r_p_and,  int_hexagon_S2_lsl_r_p_and>;
 527 def : T_PPR_pat <S2_asr_r_p_or,   int_hexagon_S2_asr_r_p_or>;
 528 def : T_PPR_pat <S2_lsr_r_p_or,   int_hexagon_S2_lsr_r_p_or>;
 529 def : T_PPR_pat <S2_asl_r_p_or,   int_hexagon_S2_asl_r_p_or>;
 530 def : T_PPR_pat <S2_lsl_r_p_or,   int_hexagon_S2_lsl_r_p_or>;
 531
 532 /********************************************************************
 533 *            ALU32/ALU                                              *
 534 *********************************************************************/
 535 def : T_RR_pat<A2_add,      int_hexagon_A2_add>;
 536 def : T_RI_pat<ADD_ri,      int_hexagon_A2_addi>;
 537 def : T_RR_pat<A2_sub,      int_hexagon_A2_sub>;
 538 def : T_IR_pat<SUB_ri,      int_hexagon_A2_subri>;
 539 def : T_RR_pat<A2_and,      int_hexagon_A2_and>;
 540 def : T_RI_pat<AND_ri,      int_hexagon_A2_andir>;
 541 def : T_RR_pat<A2_or,       int_hexagon_A2_or>;
 542 def : T_RI_pat<OR_ri,       int_hexagon_A2_orir>;
 543 def : T_RR_pat<A2_xor,      int_hexagon_A2_xor>;
 544 def : T_RR_pat<A2_combinew, int_hexagon_A2_combinew>;
 545
 546 // Assembler mapped from Rd32=not(Rs32) to Rd32=sub(#-1,Rs32)
 547 def : Pat <(int_hexagon_A2_not (I32:$Rs)),
 548            (SUB_ri -1, IntRegs:$Rs)>;
 549
 550 // Assembler mapped from Rd32=neg(Rs32) to Rd32=sub(#0,Rs32)
 551 def : Pat <(int_hexagon_A2_neg IntRegs:$Rs),
 552            (SUB_ri 0, IntRegs:$Rs)>;
 553
 554 // Transfer immediate
 555 def  : Pat <(int_hexagon_A2_tfril (I32:$Rs), u16_0ImmPred:$Is),
 556             (A2_tfril IntRegs:$Rs, u16_0ImmPred:$Is)>;
 557 def  : Pat <(int_hexagon_A2_tfrih (I32:$Rs), u16_0ImmPred:$Is),
 558             (A2_tfrih IntRegs:$Rs, u16_0ImmPred:$Is)>;
 559
 560 //  Transfer Register/immediate.
 561 def : T_R_pat <A2_tfr, int_hexagon_A2_tfr>;
 562 def : T_I_pat <A2_tfrsi, int_hexagon_A2_tfrsi>;
 563
 564 // Assembler mapped from Rdd32=Rss32 to Rdd32=combine(Rss.H32,Rss.L32)
 565 def : Pat<(int_hexagon_A2_tfrp DoubleRegs:$src),
 566           (A2_combinew (HiReg DoubleRegs:$src), (LoReg DoubleRegs:$src))>;
 567
 568 /********************************************************************
 569 *            ALU32/PERM                                             *
 570 *********************************************************************/
 571 // Combine
 572 def: T_RR_pat<A2_combine_hh, int_hexagon_A2_combine_hh>;
 573 def: T_RR_pat<A2_combine_hl, int_hexagon_A2_combine_hl>;
 574 def: T_RR_pat<A2_combine_lh, int_hexagon_A2_combine_lh>;
 575 def: T_RR_pat<A2_combine_ll, int_hexagon_A2_combine_ll>;
 576
 577 def: T_II_pat<A2_combineii, int_hexagon_A2_combineii, s8ExtPred, s8ImmPred>;
 578
 579 def: Pat<(i32 (int_hexagon_C2_mux (I32:$Rp), (I32:$Rs),
 580                                                      (I32:$Rt))),
 581          (i32 (C2_mux (C2_tfrrp IntRegs:$Rp), IntRegs:$Rs, IntRegs:$Rt))>;
 582
 583 // Mux
 584 def : T_QRI_pat<C2_muxir, int_hexagon_C2_muxir, s8ExtPred>;
 585 def : T_QIR_pat<C2_muxri, int_hexagon_C2_muxri, s8ExtPred>;
 586 def : T_QII_pat<C2_muxii, int_hexagon_C2_muxii, s8ExtPred, s8ImmPred>;
 587
 588 // Shift halfword
 589 def : T_R_pat<A2_aslh, int_hexagon_A2_aslh>;
 590 def : T_R_pat<A2_asrh, int_hexagon_A2_asrh>;
 591 def : T_R_pat<A2_asrh, int_hexagon_SI_to_SXTHI_asrh>;
 592
 593 // Sign/zero extend
 594 def : T_R_pat<A2_sxth, int_hexagon_A2_sxth>;
 595 def : T_R_pat<A2_sxtb, int_hexagon_A2_sxtb>;
 596 def : T_R_pat<A2_zxth, int_hexagon_A2_zxth>;
 597 def : T_R_pat<A2_zxtb, int_hexagon_A2_zxtb>;
 598
 599 /********************************************************************
 600 *            ALU32/PRED                                             *
 601 *********************************************************************/
 602 // Compare
 603 def : T_RR_pat<C2_cmpeq,  int_hexagon_C2_cmpeq>;
 604 def : T_RR_pat<C2_cmpgt,  int_hexagon_C2_cmpgt>;
 605 def : T_RR_pat<C2_cmpgtu, int_hexagon_C2_cmpgtu>;
 606
 607 def : T_RI_pat<C2_cmpeqi, int_hexagon_C2_cmpeqi, s10ExtPred>;
 608 def : T_RI_pat<C2_cmpgti, int_hexagon_C2_cmpgti, s10ExtPred>;
 609 def : T_RI_pat<C2_cmpgtui, int_hexagon_C2_cmpgtui, u9ExtPred>;
 610
 611 def : Pat <(i32 (int_hexagon_C2_cmpgei (I32:$src1), s8ExtPred:$src2)),
 612       (i32 (C2_cmpgti (I32:$src1),
 613                       (DEC_CONST_SIGNED s8ExtPred:$src2)))>;
 614
 615 def : Pat <(i32 (int_hexagon_C2_cmpgeui (I32:$src1), u8ExtPred:$src2)),
 616       (i32 (C2_cmpgtui (I32:$src1),
 617                        (DEC_CONST_UNSIGNED u8ExtPred:$src2)))>;
 618
 619 // The instruction, Pd=cmp.geu(Rs, #u8) -> Pd=cmp.eq(Rs,Rs) when #u8 == 0.
 620 def : Pat <(i32 (int_hexagon_C2_cmpgeui (I32:$src1), 0)),
 621       (i32 (C2_cmpeq (I32:$src1), (I32:$src1)))>;
 622
 623 def : Pat <(i32 (int_hexagon_C2_cmplt (I32:$src1),
 624                                       (I32:$src2))),
 625       (i32 (C2_cmpgt (I32:$src2), (I32:$src1)))>;
 626
 627 def : Pat <(i32 (int_hexagon_C2_cmpltu (I32:$src1),
 628                                        (I32:$src2))),
 629       (i32 (C2_cmpgtu (I32:$src2), (I32:$src1)))>;
 630
 631 /********************************************************************
 632 *            ALU32/VH                                               *
 633 *********************************************************************/
 634 // Vector add, subtract, average halfwords
 635 def: T_RR_pat<A2_svaddh,   int_hexagon_A2_svaddh>;
 636 def: T_RR_pat<A2_svaddhs,  int_hexagon_A2_svaddhs>;
 637 def: T_RR_pat<A2_svadduhs, int_hexagon_A2_svadduhs>;
 638
 639 def: T_RR_pat<A2_svsubh,   int_hexagon_A2_svsubh>;
 640 def: T_RR_pat<A2_svsubhs,  int_hexagon_A2_svsubhs>;
 641 def: T_RR_pat<A2_svsubuhs, int_hexagon_A2_svsubuhs>;
 642
 643 def: T_RR_pat<A2_svavgh,   int_hexagon_A2_svavgh>;
 644 def: T_RR_pat<A2_svavghs,  int_hexagon_A2_svavghs>;
 645 def: T_RR_pat<A2_svnavgh,  int_hexagon_A2_svnavgh>;
 646
 647 /********************************************************************
 648 *            ALU64/ALU                                              *
 649 *********************************************************************/
 650 def: T_RR_pat<A2_addsat,   int_hexagon_A2_addsat>;
 651 def: T_RR_pat<A2_subsat,   int_hexagon_A2_subsat>;
 652 def: T_PP_pat<A2_addp,     int_hexagon_A2_addp>;
 653 def: T_PP_pat<A2_subp,     int_hexagon_A2_subp>;
 654
 655 def: T_PP_pat<A2_andp,     int_hexagon_A2_andp>;
 656 def: T_PP_pat<A2_orp,      int_hexagon_A2_orp>;
 657 def: T_PP_pat<A2_xorp,     int_hexagon_A2_xorp>;
 658
 659 def: T_PP_pat<C2_cmpeqp,   int_hexagon_C2_cmpeqp>;
 660 def: T_PP_pat<C2_cmpgtp,   int_hexagon_C2_cmpgtp>;
 661 def: T_PP_pat<C2_cmpgtup,  int_hexagon_C2_cmpgtup>;
 662
 663 def: T_PP_pat<S2_parityp,  int_hexagon_S2_parityp>;
 664 def: T_RR_pat<S2_packhl,   int_hexagon_S2_packhl>;
 665
 666 /********************************************************************
 667 *            ALU64/VB                                               *
 668 *********************************************************************/
 669 // ALU64 - Vector add
 670 def : T_PP_pat <A2_vaddub,   int_hexagon_A2_vaddub>;
 671 def : T_PP_pat <A2_vaddubs,  int_hexagon_A2_vaddubs>;
 672 def : T_PP_pat <A2_vaddh,    int_hexagon_A2_vaddh>;
 673 def : T_PP_pat <A2_vaddhs,   int_hexagon_A2_vaddhs>;
 674 def : T_PP_pat <A2_vadduhs,  int_hexagon_A2_vadduhs>;
 675 def : T_PP_pat <A2_vaddw,    int_hexagon_A2_vaddw>;
 676 def : T_PP_pat <A2_vaddws,   int_hexagon_A2_vaddws>;
 677
 678 // ALU64 - Vector average
 679 def : T_PP_pat <A2_vavgub,   int_hexagon_A2_vavgub>;
 680 def : T_PP_pat <A2_vavgubr,  int_hexagon_A2_vavgubr>;
 681 def : T_PP_pat <A2_vavgh,    int_hexagon_A2_vavgh>;
 682 def : T_PP_pat <A2_vavghr,   int_hexagon_A2_vavghr>;
 683 def : T_PP_pat <A2_vavghcr,  int_hexagon_A2_vavghcr>;
 684 def : T_PP_pat <A2_vavguh,   int_hexagon_A2_vavguh>;
 685 def : T_PP_pat <A2_vavguhr,  int_hexagon_A2_vavguhr>;
 686
 687 def : T_PP_pat <A2_vavgw,    int_hexagon_A2_vavgw>;
 688 def : T_PP_pat <A2_vavgwr,   int_hexagon_A2_vavgwr>;
 689 def : T_PP_pat <A2_vavgwcr,  int_hexagon_A2_vavgwcr>;
 690 def : T_PP_pat <A2_vavguw,   int_hexagon_A2_vavguw>;
 691 def : T_PP_pat <A2_vavguwr,  int_hexagon_A2_vavguwr>;
 692
 693 // ALU64 - Vector negative average
 694 def : T_PP_pat <A2_vnavgh,   int_hexagon_A2_vnavgh>;
 695 def : T_PP_pat <A2_vnavghr,  int_hexagon_A2_vnavghr>;
 696 def : T_PP_pat <A2_vnavghcr, int_hexagon_A2_vnavghcr>;
 697 def : T_PP_pat <A2_vnavgw,   int_hexagon_A2_vnavgw>;
 698 def : T_PP_pat <A2_vnavgwr,  int_hexagon_A2_vnavgwr>;
 699 def : T_PP_pat <A2_vnavgwcr, int_hexagon_A2_vnavgwcr>;
 700
 701 // ALU64 - Vector max
 702 def : T_PP_pat <A2_vmaxh,    int_hexagon_A2_vmaxh>;
 703 def : T_PP_pat <A2_vmaxw,    int_hexagon_A2_vmaxw>;
 704 def : T_PP_pat <A2_vmaxub,   int_hexagon_A2_vmaxub>;
 705 def : T_PP_pat <A2_vmaxuh,   int_hexagon_A2_vmaxuh>;
 706 def : T_PP_pat <A2_vmaxuw,   int_hexagon_A2_vmaxuw>;
 707
 708 // ALU64 - Vector min
 709 def : T_PP_pat <A2_vminh,    int_hexagon_A2_vminh>;
 710 def : T_PP_pat <A2_vminw,    int_hexagon_A2_vminw>;
 711 def : T_PP_pat <A2_vminub,   int_hexagon_A2_vminub>;
 712 def : T_PP_pat <A2_vminuh,   int_hexagon_A2_vminuh>;
 713 def : T_PP_pat <A2_vminuw,   int_hexagon_A2_vminuw>;
 714
 715 // ALU64 - Vector sub
 716 def : T_PP_pat <A2_vsubub,   int_hexagon_A2_vsubub>;
 717 def : T_PP_pat <A2_vsububs,  int_hexagon_A2_vsububs>;
 718 def : T_PP_pat <A2_vsubh,    int_hexagon_A2_vsubh>;
 719 def : T_PP_pat <A2_vsubhs,   int_hexagon_A2_vsubhs>;
 720 def : T_PP_pat <A2_vsubuhs,  int_hexagon_A2_vsubuhs>;
 721 def : T_PP_pat <A2_vsubw,    int_hexagon_A2_vsubw>;
 722 def : T_PP_pat <A2_vsubws,   int_hexagon_A2_vsubws>;
 723
 724 // ALU64 - Vector compare bytes
 725 def : T_PP_pat <A2_vcmpbeq,  int_hexagon_A2_vcmpbeq>;
 726 def : T_PP_pat <A4_vcmpbgt,  int_hexagon_A4_vcmpbgt>;
 727 def : T_PP_pat <A2_vcmpbgtu, int_hexagon_A2_vcmpbgtu>;
 728
 729 // ALU64 - Vector compare halfwords
 730 def : T_PP_pat <A2_vcmpheq,  int_hexagon_A2_vcmpheq>;
 731 def : T_PP_pat <A2_vcmphgt,  int_hexagon_A2_vcmphgt>;
 732 def : T_PP_pat <A2_vcmphgtu, int_hexagon_A2_vcmphgtu>;
 733
 734 // ALU64 - Vector compare words
 735 def : T_PP_pat <A2_vcmpweq,  int_hexagon_A2_vcmpweq>;
 736 def : T_PP_pat <A2_vcmpwgt,  int_hexagon_A2_vcmpwgt>;
 737 def : T_PP_pat <A2_vcmpwgtu, int_hexagon_A2_vcmpwgtu>;
 738
 739 // ALU64 / VB / Vector mux.
 740 def : Pat<(int_hexagon_C2_vmux PredRegs:$Pu, DoubleRegs:$Rs, DoubleRegs:$Rt),
 741           (C2_vmux PredRegs:$Pu, DoubleRegs:$Rs, DoubleRegs:$Rt)>;
 742
 743 // MPY - Multiply and use full result
 744 // Rdd = mpy[u](Rs, Rt)
 745 def : T_RR_pat <M2_dpmpyss_s0, int_hexagon_M2_dpmpyss_s0>;
 746 def : T_RR_pat <M2_dpmpyuu_s0, int_hexagon_M2_dpmpyuu_s0>;
 747
 748 // Rxx[+-]= mpy[u](Rs,Rt)
 749 def : T_PRR_pat <M2_dpmpyss_acc_s0, int_hexagon_M2_dpmpyss_acc_s0>;
 750 def : T_PRR_pat <M2_dpmpyss_nac_s0, int_hexagon_M2_dpmpyss_nac_s0>;
 751 def : T_PRR_pat <M2_dpmpyuu_acc_s0, int_hexagon_M2_dpmpyuu_acc_s0>;
 752 def : T_PRR_pat <M2_dpmpyuu_nac_s0, int_hexagon_M2_dpmpyuu_nac_s0>;
 753
 754 /********************************************************************
 755 *            CR                                                     *
 756 *********************************************************************/
 757 class qi_CRInst_qi_pat<InstHexagon Inst, Intrinsic IntID> :
 758   Pat<(i32 (IntID IntRegs:$Rs)),
 759       (i32 (C2_tfrpr (Inst (C2_tfrrp IntRegs:$Rs))))>;
 760
 761 class qi_CRInst_qiqi_pat<InstHexagon Inst, Intrinsic IntID> :
 762   Pat<(i32 (IntID IntRegs:$Rs, IntRegs:$Rt)),
 763       (i32 (C2_tfrpr (Inst (C2_tfrrp IntRegs:$Rs), (C2_tfrrp IntRegs:$Rt))))>;
 764
 765 def: qi_CRInst_qi_pat<C2_not,     int_hexagon_C2_not>;
 766 def: qi_CRInst_qi_pat<C2_all8,    int_hexagon_C2_all8>;
 767 def: qi_CRInst_qi_pat<C2_any8,    int_hexagon_C2_any8>;
 768
 769 def: qi_CRInst_qiqi_pat<C2_and,   int_hexagon_C2_and>;
 770 def: qi_CRInst_qiqi_pat<C2_andn,  int_hexagon_C2_andn>;
 771 def: qi_CRInst_qiqi_pat<C2_or,    int_hexagon_C2_or>;
 772 def: qi_CRInst_qiqi_pat<C2_orn,   int_hexagon_C2_orn>;
 773 def: qi_CRInst_qiqi_pat<C2_xor,   int_hexagon_C2_xor>;
 774
 775 // Multiply 32x32 and use lower result
 776 def : T_RRI_pat <M2_macsip, int_hexagon_M2_macsip>;
 777 def : T_RRI_pat <M2_macsin, int_hexagon_M2_macsin>;
 778 def : T_RRR_pat <M2_maci, int_hexagon_M2_maci>;
 779
 780 // Subtract and accumulate
 781 def : T_RRR_pat <M2_subacc, int_hexagon_M2_subacc>;
 782
 783 // Add and accumulate
 784 def : T_RRR_pat <M2_acci,   int_hexagon_M2_acci>;
 785 def : T_RRR_pat <M2_nacci,  int_hexagon_M2_nacci>;
 786 def : T_RRI_pat <M2_accii,  int_hexagon_M2_accii>;
 787 def : T_RRI_pat <M2_naccii, int_hexagon_M2_naccii>;
 788
 789 // XOR and XOR with destination
 790 def : T_RRR_pat <M2_xor_xacc, int_hexagon_M2_xor_xacc>;
 791
 792 class MType_R32_pat <Intrinsic IntID, InstHexagon OutputInst> :
 793       Pat <(IntID IntRegs:$src1, IntRegs:$src2),
 794            (OutputInst IntRegs:$src1, IntRegs:$src2)>;
 795
 796 // Multiply and use lower result
 797 def : MType_R32_pat <int_hexagon_M2_mpyi, M2_mpyi>;
 798 def : T_RI_pat<M2_mpysmi, int_hexagon_M2_mpysmi>;
 799
 800 // Assembler mapped from Rd32=mpyui(Rs32,Rt32) to Rd32=mpyi(Rs32,Rt32)
 801 def : MType_R32_pat <int_hexagon_M2_mpyui, M2_mpyi>;
 802
 803 // Multiply and use upper result
 804 def : MType_R32_pat <int_hexagon_M2_mpy_up, M2_mpy_up>;
 805 def : MType_R32_pat <int_hexagon_M2_mpyu_up, M2_mpyu_up>;
 806 def : MType_R32_pat <int_hexagon_M2_hmmpyh_rs1, M2_hmmpyh_rs1>;
 807 def : MType_R32_pat <int_hexagon_M2_hmmpyl_rs1, M2_hmmpyl_rs1>;
 808 def : MType_R32_pat <int_hexagon_M2_dpmpyss_rnd_s0, M2_dpmpyss_rnd_s0>;
 809
 810 /********************************************************************
 811 *            STYPE/ALU                                              *
 812 *********************************************************************/
 813 def : T_P_pat <A2_absp, int_hexagon_A2_absp>;
 814 def : T_P_pat <A2_negp, int_hexagon_A2_negp>;
 815 def : T_P_pat <A2_notp, int_hexagon_A2_notp>;
 816
 817 /********************************************************************
 818 *            STYPE/BIT                                              *
 819 *********************************************************************/
 820
 821 // Count leading/trailing
 822 def: T_R_pat<S2_cl0,     int_hexagon_S2_cl0>;
 823 def: T_P_pat<S2_cl0p,    int_hexagon_S2_cl0p>;
 824 def: T_R_pat<S2_cl1,     int_hexagon_S2_cl1>;
 825 def: T_P_pat<S2_cl1p,    int_hexagon_S2_cl1p>;
 826 def: T_R_pat<S2_clb,     int_hexagon_S2_clb>;
 827 def: T_P_pat<S2_clbp,    int_hexagon_S2_clbp>;
 828 def: T_R_pat<S2_clbnorm, int_hexagon_S2_clbnorm>;
 829 def: T_R_pat<S2_ct0,     int_hexagon_S2_ct0>;
 830 def: T_R_pat<S2_ct1,     int_hexagon_S2_ct1>;
 831
 832 // Compare bit mask
 833 def: T_RR_pat<C2_bitsclr,  int_hexagon_C2_bitsclr>;
 834 def: T_RI_pat<C2_bitsclri, int_hexagon_C2_bitsclri>;
 835 def: T_RR_pat<C2_bitsset,  int_hexagon_C2_bitsset>;
 836
 837 // Linear feedback-shift Iteration.
 838 def : T_PP_pat <S2_lfsp, int_hexagon_S2_lfsp>;
 839
 840 // Shift by immediate and add
 841 def : T_RRI_pat<S2_addasl_rrri, int_hexagon_S2_addasl_rrri>;
 842
 843 // Extract bitfield
 844 def : T_PII_pat<S2_extractup,    int_hexagon_S2_extractup>;
 845 def : T_RII_pat<S2_extractu,     int_hexagon_S2_extractu>;
 846 def : T_RP_pat <S2_extractu_rp,  int_hexagon_S2_extractu_rp>;
 847 def : T_PP_pat <S2_extractup_rp, int_hexagon_S2_extractup_rp>;
 848
 849 // Insert bitfield
 850 def : Pat <(int_hexagon_S2_insert_rp IntRegs:$src1, IntRegs:$src2,
 851                                      DoubleRegs:$src3),
 852            (S2_insert_rp IntRegs:$src1, IntRegs:$src2, DoubleRegs:$src3)>;
 853
 854 def : Pat<(i64 (int_hexagon_S2_insertp_rp (I64:$src1),
 855                  (I64:$src2), (I64:$src3))),
 856           (i64 (S2_insertp_rp (I64:$src1), (I64:$src2),
 857                               (I64:$src3)))>;
 858
 859 def : Pat<(int_hexagon_S2_insert IntRegs:$src1, IntRegs:$src2,
 860                                  u5ImmPred:$src3, u5ImmPred:$src4),
 861           (S2_insert IntRegs:$src1, IntRegs:$src2,
 862                      u5ImmPred:$src3, u5ImmPred:$src4)>;
 863
 864 def : Pat<(i64 (int_hexagon_S2_insertp (I64:$src1),
 865                  (I64:$src2), u6ImmPred:$src3, u6ImmPred:$src4)),
 866           (i64 (S2_insertp (I64:$src1), (I64:$src2),
 867                            u6ImmPred:$src3, u6ImmPred:$src4))>;
 868
 869
 870 // Innterleave/deinterleave
 871 def : T_P_pat <S2_interleave, int_hexagon_S2_interleave>;
 872 def : T_P_pat <S2_deinterleave, int_hexagon_S2_deinterleave>;
 873
 874 // Set/Clear/Toggle Bit
 875 def: T_RI_pat<S2_setbit_i,    int_hexagon_S2_setbit_i>;
 876 def: T_RI_pat<S2_clrbit_i,    int_hexagon_S2_clrbit_i>;
 877 def: T_RI_pat<S2_togglebit_i, int_hexagon_S2_togglebit_i>;
 878
 879 def: T_RR_pat<S2_setbit_r,    int_hexagon_S2_setbit_r>;
 880 def: T_RR_pat<S2_clrbit_r,    int_hexagon_S2_clrbit_r>;
 881 def: T_RR_pat<S2_togglebit_r, int_hexagon_S2_togglebit_r>;
 882
 883 // Test Bit
 884 def: T_RI_pat<S2_tstbit_i,    int_hexagon_S2_tstbit_i>;
 885 def: T_RR_pat<S2_tstbit_r,    int_hexagon_S2_tstbit_r>;
 886
 887 /********************************************************************
 888 *            STYPE/SHIFT                                            *
 889 *********************************************************************/
 890
 891 def : T_PI_pat <S2_asr_i_p, int_hexagon_S2_asr_i_p>;
 892 def : T_PI_pat <S2_lsr_i_p, int_hexagon_S2_lsr_i_p>;
 893 def : T_PI_pat <S2_asl_i_p, int_hexagon_S2_asl_i_p>;
 894
 895 def : T_PR_pat <S2_asr_r_p, int_hexagon_S2_asr_r_p>;
 896 def : T_PR_pat <S2_lsr_r_p, int_hexagon_S2_lsr_r_p>;
 897 def : T_PR_pat <S2_asl_r_p, int_hexagon_S2_asl_r_p>;
 898 def : T_PR_pat <S2_lsl_r_p, int_hexagon_S2_lsl_r_p>;
 899
 900 def : T_RR_pat <S2_asr_r_r, int_hexagon_S2_asr_r_r>;
 901 def : T_RR_pat <S2_lsr_r_r, int_hexagon_S2_lsr_r_r>;
 902 def : T_RR_pat <S2_asl_r_r, int_hexagon_S2_asl_r_r>;
 903 def : T_RR_pat <S2_lsl_r_r, int_hexagon_S2_lsl_r_r>;
 904
 905 def : T_RR_pat <S2_asr_r_r_sat, int_hexagon_S2_asr_r_r_sat>;
 906 def : T_RR_pat <S2_asl_r_r_sat, int_hexagon_S2_asl_r_r_sat>;
 907
 908 def : T_R_pat <A2_sxtw,     int_hexagon_A2_sxtw>;
 909
 910 def : T_R_pat <S2_brev,        int_hexagon_S2_brev>;
 911
 912 def : T_R_pat <A2_abs,    int_hexagon_A2_abs>;
 913 def : T_R_pat <A2_abssat, int_hexagon_A2_abssat>;
 914 def : T_R_pat <A2_negsat, int_hexagon_A2_negsat>;
 915
 916 def : T_R_pat <A2_swiz,   int_hexagon_A2_swiz>;
 917
 918 def : T_P_pat <A2_sat,    int_hexagon_A2_sat>;
 919 def : T_R_pat <A2_sath,   int_hexagon_A2_sath>;
 920 def : T_R_pat <A2_satuh,  int_hexagon_A2_satuh>;
 921 def : T_R_pat <A2_satub,  int_hexagon_A2_satub>;
 922 def : T_R_pat <A2_satb,   int_hexagon_A2_satb>;
 923
 924 def : T_RI_pat <S2_asr_i_r,     int_hexagon_S2_asr_i_r>;
 925 def : T_RI_pat <S2_lsr_i_r,     int_hexagon_S2_lsr_i_r>;
 926 def : T_RI_pat <S2_asl_i_r,     int_hexagon_S2_asl_i_r>;
 927 def : T_RI_pat <S2_asr_i_r_rnd, int_hexagon_S2_asr_i_r_rnd>;
 928 def : T_RI_pat <S2_asr_i_r_rnd_goodsyntax,
 929                 int_hexagon_S2_asr_i_r_rnd_goodsyntax>;
 930
 931 // Shift left by immediate with saturation.
 932 def : T_RI_pat <S2_asl_i_r_sat, int_hexagon_S2_asl_i_r_sat>;
 933
 934 //===----------------------------------------------------------------------===//
 935 // Template 'def pat' to map tableidx[bhwd] intrinsics to :raw instructions.
 936 //===----------------------------------------------------------------------===//
 937 class S2op_tableidx_pat <Intrinsic IntID, InstHexagon OutputInst,
 938                          SDNodeXForm XformImm>
 939   : Pat <(IntID IntRegs:$src1, IntRegs:$src2, u4ImmPred:$src3, u5ImmPred:$src4),
 940          (OutputInst IntRegs:$src1, IntRegs:$src2, u4ImmPred:$src3,
 941                      (XformImm u5ImmPred:$src4))>;
 942
 943
 944 // Table Index : Extract and insert bits.
 945 // Map to the real hardware instructions after subtracting appropriate
 946 // values from the 4th input operand. Please note that subtraction is not
 947 // needed for int_hexagon_S2_tableidxb_goodsyntax.
 948
 949 def : Pat <(int_hexagon_S2_tableidxb_goodsyntax IntRegs:$src1, IntRegs:$src2,
 950                                               u4ImmPred:$src3, u5ImmPred:$src4),
 951            (S2_tableidxb IntRegs:$src1, IntRegs:$src2,
 952                          u4ImmPred:$src3, u5ImmPred:$src4)>;
 953
 954 def : S2op_tableidx_pat <int_hexagon_S2_tableidxh_goodsyntax, S2_tableidxh,
 955                          DEC_CONST_SIGNED>;
 956 def : S2op_tableidx_pat <int_hexagon_S2_tableidxw_goodsyntax, S2_tableidxw,
 957                          DEC2_CONST_SIGNED>;
 958 def : S2op_tableidx_pat <int_hexagon_S2_tableidxd_goodsyntax, S2_tableidxd,
 959                          DEC3_CONST_SIGNED>;
 960
 961 //
 962 // ALU 32 types.
 963 //
 964
 965 class qi_ALU32_sisi<string opc, Intrinsic IntID>
 966   : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 967              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
 968              [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 969
 970 class qi_ALU32_sis10<string opc, Intrinsic IntID>
 971   : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, s10Imm:$src2),
 972              !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
 973              [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
 974
 975 class qi_ALU32_sis8<string opc, Intrinsic IntID>
 976   : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, s8Imm:$src2),
 977              !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
 978              [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
 979
 980 class qi_ALU32_siu8<string opc, Intrinsic IntID>
 981   : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, u8Imm:$src2),
 982              !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
 983              [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
 984
 985 class qi_ALU32_siu9<string opc, Intrinsic IntID>
 986   : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, u9Imm:$src2),
 987              !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
 988              [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
 989
 990 class si_ALU32_qisisi<string opc, Intrinsic IntID>
 991   : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2,
 992                                       IntRegs:$src3),
 993              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2, $src3)")),
 994              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2,
 995                                         IntRegs:$src3))]>;
 996
 997 class si_ALU32_sisi<string opc, Intrinsic IntID>
 998   : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 999              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
1000              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1001
1002 class si_ALU32_sisi_sat<string opc, Intrinsic IntID>
1003   : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1004              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):sat")),
1005              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1006
1007 class si_ALU32_sisi_rnd<string opc, Intrinsic IntID>
1008   : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1009              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):rnd")),
1010              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1011
1012 class di_ALU64_di<string opc, Intrinsic IntID>
1013   : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src),
1014              !strconcat("$dst = ", !strconcat(opc , "$src")),
1015              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src))]>;
1016
1017 //
1018 // ALU 64 types.
1019 //
1020
1021 class di_ALU64_didi<string opc, Intrinsic IntID>
1022   : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1023              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
1024              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
1025                                            DoubleRegs:$src2))]>;
1026
1027 class di_ALU64_qididi<string opc, Intrinsic IntID>
1028   : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src1, DoubleRegs:$src2,
1029                                           DoubleRegs:$src3),
1030              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2, $src3)")),
1031              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, DoubleRegs:$src2,
1032                                            DoubleRegs:$src3))]>;
1033
1034 class di_ALU64_didi_sat<string opc, Intrinsic IntID>
1035   : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1036              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):sat")),
1037              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
1038                                            DoubleRegs:$src2))]>;
1039
1040 class di_ALU64_didi_rnd<string opc, Intrinsic IntID>
1041   : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1042              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):rnd")),
1043              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
1044                                            DoubleRegs:$src2))]>;
1045
1046 class di_ALU64_didi_crnd<string opc, Intrinsic IntID>
1047   : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1048              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):crnd")),
1049              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
1050                                            DoubleRegs:$src2))]>;
1051
1052 class di_ALU64_didi_rnd_sat<string opc, Intrinsic IntID>
1053   : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1054              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):rnd:sat")),
1055              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
1056                                            DoubleRegs:$src2))]>;
1057
1058 class di_ALU64_didi_crnd_sat<string opc, Intrinsic IntID>
1059   : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1060              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):crnd:sat")),
1061              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
1062                                            DoubleRegs:$src2))]>;
1063
1064 class qi_ALU64_didi<string opc, Intrinsic IntID>
1065   : ALU64_rr<(outs PredRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1066              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
1067              [(set PredRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
1068
1069 //
1070 // SInst classes.
1071 //
1072
1073 class qi_SInst_qi<string opc, Intrinsic IntID>
1074   : SInst<(outs PredRegs:$dst), (ins IntRegs:$src),
1075              !strconcat("$dst = ", !strconcat(opc , "($src)")),
1076              [(set PredRegs:$dst, (IntID IntRegs:$src))]>;
1077
1078 class qi_SInst_qi_pxfer<string opc, Intrinsic IntID>
1079   : SInst<(outs PredRegs:$dst), (ins IntRegs:$src),
1080              !strconcat("$dst = ", !strconcat(opc , "$src")),
1081              [(set PredRegs:$dst, (IntID IntRegs:$src))]>;
1082
1083 class qi_SInst_qiqi<string opc, Intrinsic IntID>
1084   : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1085              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
1086              [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1087
1088 class qi_SInst_qiqi_neg<string opc, Intrinsic IntID>
1089   : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1090              !strconcat("$dst = ", !strconcat(opc , "($src1, !$src2)")),
1091              [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1092
1093 class di_SInst_di<string opc, Intrinsic IntID>
1094   : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src),
1095              !strconcat("$dst = ", !strconcat(opc , "($src)")),
1096              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src))]>;
1097
1098 class di_SInst_di_sat<string opc, Intrinsic IntID>
1099   : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src),
1100              !strconcat("$dst = ", !strconcat(opc , "($src):sat")),
1101              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src))]>;
1102
1103 class si_SInst_di<string opc, Intrinsic IntID>
1104   : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src),
1105           !strconcat("$dst = ", !strconcat(opc , "($src)")),
1106           [(set IntRegs:$dst, (IntID DoubleRegs:$src))]>;
1107
1108 class si_SInst_di_sat<string opc, Intrinsic IntID>
1109   : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src),
1110           !strconcat("$dst = ", !strconcat(opc , "($src):sat")),
1111           [(set IntRegs:$dst, (IntID DoubleRegs:$src))]>;
1112
1113 class di_SInst_disi<string opc, Intrinsic IntID>
1114   : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
1115           !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
1116           [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, IntRegs:$src2))]>;
1117
1118 class di_SInst_didi<string opc, Intrinsic IntID>
1119   : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1120           !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
1121           [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
1122
1123 class di_SInst_si<string opc, Intrinsic IntID>
1124   : SInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1),
1125           !strconcat("$dst = ", !strconcat(opc , "($src1)")),
1126           [(set DoubleRegs:$dst, (IntID IntRegs:$src1))]>;
1127
1128 class si_SInst_diu5<string opc, Intrinsic IntID>
1129   : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, u5Imm:$src2),
1130           !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
1131           [(set IntRegs:$dst, (IntID DoubleRegs:$src1, imm:$src2))]>;
1132
1133 class si_SInst_disi<string opc, Intrinsic IntID>
1134   : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
1135           !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
1136           [(set IntRegs:$dst, (IntID DoubleRegs:$src1, IntRegs:$src2))]>;
1137
1138 class si_SInst_si<string opc, Intrinsic IntID>
1139   : SInst<(outs IntRegs:$dst), (ins IntRegs:$src),
1140           !strconcat("$dst = ", !strconcat(opc , "($src)")),
1141           [(set IntRegs:$dst, (IntID IntRegs:$src))]>;
1142
1143 class di_SInst_qi<string opc, Intrinsic IntID>
1144   : SInst<(outs DoubleRegs:$dst), (ins IntRegs:$src),
1145           !strconcat("$dst = ", !strconcat(opc , "($src)")),
1146           [(set DoubleRegs:$dst, (IntID IntRegs:$src))]>;
1147
1148 class si_SInst_qi<string opc, Intrinsic IntID>
1149   : SInst<(outs IntRegs:$dst), (ins IntRegs:$src),
1150           !strconcat("$dst = ", !strconcat(opc , "$src")),
1151           [(set IntRegs:$dst, (IntID IntRegs:$src))]>;
1152
1153 class si_SInst_qiqi<string opc, Intrinsic IntID>
1154   : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1155           !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
1156           [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1157
1158 class qi_SInst_si<string opc, Intrinsic IntID>
1159   : SInst<(outs PredRegs:$dst), (ins IntRegs:$src),
1160           !strconcat("$dst = ", !strconcat(opc , "$src")),
1161           [(set PredRegs:$dst, (IntID IntRegs:$src))]>;
1162
1163 class di_SInst_didiqi<string opc, Intrinsic IntID>
1164   : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2,
1165                                        IntRegs:$src3),
1166           !strconcat("$dst = ", !strconcat(opc , "($src1, $src2, $src3)")),
1167           [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2,
1168                                         IntRegs:$src3))]>;
1169
1170 class di_SInst_didiu3<string opc, Intrinsic IntID>
1171   : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2,
1172                                        u3Imm:$src3),
1173           !strconcat("$dst = ", !strconcat(opc , "($src1, $src2, #$src3)")),
1174           [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2,
1175                                         imm:$src3))]>;
1176
1177
1178 //
1179 // MInst classes.
1180 //
1181
1182 class di_MInst_disisi_acc<string opc, Intrinsic IntID>
1183   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1184                                            IntRegs:$src2),
1185              !strconcat("$dst += ", !strconcat(opc , "($src1, $src2)")),
1186              [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1187                                            IntRegs:$src2))],
1188              "$dst2 = $dst">;
1189
1190 class di_MInst_disisi_nac<string opc, Intrinsic IntID>
1191   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1192                                            IntRegs:$src2),
1193              !strconcat("$dst -= ", !strconcat(opc , "($src1, $src2)")),
1194              [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1195                                            IntRegs:$src2))],
1196              "$dst2 = $dst">;
1197
1198 class di_MInst_disisi_acc_sat<string opc, Intrinsic IntID>
1199   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1200                                            IntRegs:$src2),
1201              !strconcat("$dst += ", !strconcat(opc , "($src1, $src2):sat")),
1202              [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1203                                            IntRegs:$src2))],
1204              "$dst2 = $dst">;
1205
1206 class di_MInst_disisi_nac_sat<string opc, Intrinsic IntID>
1207   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1208                                            IntRegs:$src2),
1209              !strconcat("$dst -= ", !strconcat(opc , "($src1, $src2):sat")),
1210              [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1211                                            IntRegs:$src2))],
1212              "$dst2 = $dst">;
1213
1214 class di_MInst_disisi_acc_sat_conj<string opc, Intrinsic IntID>
1215   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1216                                            IntRegs:$src2),
1217              !strconcat("$dst += ", !strconcat(opc , "($src1, $src2*):sat")),
1218              [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1219                                            IntRegs:$src2))],
1220              "$dst2 = $dst">;
1221
1222 class di_MInst_disisi_nac_sat_conj<string opc, Intrinsic IntID>
1223   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1224                                            IntRegs:$src2),
1225              !strconcat("$dst -= ", !strconcat(opc , "($src1, $src2*):sat")),
1226              [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1227                                            IntRegs:$src2))],
1228              "$dst2 = $dst">;
1229
1230 class di_MInst_disisi_nac_s1_sat<string opc, Intrinsic IntID>
1231   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1232                                            IntRegs:$src2),
1233              !strconcat("$dst -= ", !strconcat(opc ,
1234                                                "($src1, $src2):<<1:sat")),
1235              [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1236                                            IntRegs:$src2))],
1237              "$dst2 = $dst">;
1238
1239 class di_MInst_disisi_acc_s1_sat_conj<string opc, Intrinsic IntID>
1240   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1241                                            IntRegs:$src2),
1242              !strconcat("$dst += ", !strconcat(opc ,
1243                                                "($src1, $src2*):<<1:sat")),
1244              [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1245                                            IntRegs:$src2))],
1246              "$dst2 = $dst">;
1247
1248 class di_MInst_disisi_nac_s1_sat_conj<string opc, Intrinsic IntID>
1249   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1250                                            IntRegs:$src2),
1251              !strconcat("$dst -= ", !strconcat(opc ,
1252                                                "($src1, $src2*):<<1:sat")),
1253              [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1254                                            IntRegs:$src2))],
1255              "$dst2 = $dst">;
1256
1257 class di_MInst_didi<string opc, Intrinsic IntID>
1258   : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1259              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
1260              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
1261                                            DoubleRegs:$src2))]>;
1262
1263 class di_MInst_didi_conj<string opc, Intrinsic IntID>
1264   : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1265              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2*)")),
1266              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
1267                                            DoubleRegs:$src2))]>;
1268
1269 class di_MInst_sisi_s1_sat_conj<string opc, Intrinsic IntID>
1270   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1271              !strconcat("$dst = ", !strconcat(opc ,
1272                                               "($src1, $src2*):<<1:sat")),
1273              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1274
1275 class di_MInst_didi_s1_rnd_sat<string opc, Intrinsic IntID>
1276   : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1277              !strconcat("$dst = ", !strconcat(opc ,
1278                                               "($src1, $src2):<<1:rnd:sat")),
1279              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
1280                                            DoubleRegs:$src2))]>;
1281
1282 class di_MInst_didi_sat<string opc, Intrinsic IntID>
1283   : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1284              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):sat")),
1285              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
1286                                            DoubleRegs:$src2))]>;
1287
1288 class di_MInst_didi_rnd_sat<string opc, Intrinsic IntID>
1289   : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1290              !strconcat("$dst = ", !strconcat(opc ,
1291                                               "($src1, $src2):rnd:sat")),
1292              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
1293                                            DoubleRegs:$src2))]>;
1294
1295 class si_SInst_didi_sat<string opc, Intrinsic IntID>
1296   : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1297           !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):sat")),
1298           [(set IntRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
1299
1300 class si_SInst_disi_s1_rnd_sat<string opc, Intrinsic IntID>
1301   : MInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
1302              !strconcat("$dst = ", !strconcat(opc ,
1303                                               "($src1, $src2):<<1:rnd:sat")),
1304              [(set IntRegs:$dst, (IntID DoubleRegs:$src1, IntRegs:$src2))]>;
1305
1306 class si_MInst_sisi_s1_rnd_sat<string opc, Intrinsic IntID>
1307   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1308              !strconcat("$dst = ", !strconcat(opc ,
1309                                               "($src1, $src2):<<1:rnd:sat")),
1310              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1311
1312 class si_MInst_sisi_rnd_sat_conj<string opc, Intrinsic IntID>
1313   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1314              !strconcat("$dst = ", !strconcat(opc ,
1315                                               "($src1, $src2*):rnd:sat")),
1316              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1317
1318 class si_MInst_sisi_s1_rnd_sat_conj<string opc, Intrinsic IntID>
1319   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1320              !strconcat("$dst = ", !strconcat(opc ,
1321                                               "($src1, $src2*):<<1:rnd:sat")),
1322              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1323
1324 class si_MInst_sisi_rnd_sat<string opc, Intrinsic IntID>
1325   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1326              !strconcat("$dst = ", !strconcat(opc ,
1327                                               "($src1, $src2):rnd:sat")),
1328              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1329
1330 class di_MInst_sisi<string opc, Intrinsic IntID>
1331   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1332              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
1333              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1334
1335 class di_MInst_sisi_sat<string opc, Intrinsic IntID>
1336   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1337              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):sat")),
1338              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1339
1340 class di_MInst_sisi_sat_conj<string opc, Intrinsic IntID>
1341   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1342              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2*):sat")),
1343              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1344
1345 class di_MInst_sisi_s1_sat<string opc, Intrinsic IntID>
1346   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1347              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):<<1:sat")),
1348              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1349
1350 class di_MInst_didi_s1_sat<string opc, Intrinsic IntID>
1351   : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1352              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):<<1:sat")),
1353              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
1354                                            DoubleRegs:$src2))]>;
1355
1356 class si_MInst_didi_s1_rnd_sat<string opc, Intrinsic IntID>
1357   : MInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1358              !strconcat("$dst = ", !strconcat(opc ,
1359                                               "($src1, $src2):<<1:rnd:sat")),
1360              [(set IntRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
1361
1362 class si_MInst_didi_rnd_sat<string opc, Intrinsic IntID>
1363   : MInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1364              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):rnd:sat")),
1365              [(set IntRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
1366
1367 class di_MInst_dididi_acc_sat<string opc, Intrinsic IntID>
1368   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2,
1369                                            DoubleRegs:$src1, DoubleRegs:$src2),
1370                !strconcat("$dst += ", !strconcat(opc , "($src1, $src2):sat")),
1371                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
1372                                              DoubleRegs:$src1,
1373                                              DoubleRegs:$src2))],
1374                "$dst2 = $dst">;
1375
1376 class di_MInst_dididi_acc_rnd_sat<string opc, Intrinsic IntID>
1377   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
1378                                            DoubleRegs:$src2),
1379                !strconcat("$dst += ",
1380                           !strconcat(opc , "($src1, $src2):rnd:sat")),
1381                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
1382                                              DoubleRegs:$src1,
1383                                              DoubleRegs:$src2))],
1384                "$dst2 = $dst">;
1385
1386 class di_MInst_dididi_acc_s1<string opc, Intrinsic IntID>
1387   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2,
1388                                            DoubleRegs:$src1,
1389                                            DoubleRegs:$src2),
1390                !strconcat("$dst += ",
1391                           !strconcat(opc , "($src1, $src2):<<1")),
1392                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
1393                                              DoubleRegs:$src1,
1394                                              DoubleRegs:$src2))],
1395                "$dst2 = $dst">;
1396
1397
1398 class di_MInst_dididi_acc_s1_sat<string opc, Intrinsic IntID>
1399   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2,
1400                                            DoubleRegs:$src1,
1401                                            DoubleRegs:$src2),
1402                !strconcat("$dst += ",
1403                           !strconcat(opc , "($src1, $src2):<<1:sat")),
1404                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
1405                                              DoubleRegs:$src1,
1406                                              DoubleRegs:$src2))],
1407                "$dst2 = $dst">;
1408
1409 class di_MInst_dididi_acc_s1_rnd_sat<string opc, Intrinsic IntID>
1410   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
1411                                            DoubleRegs:$src2),
1412                !strconcat("$dst += ",
1413                           !strconcat(opc , "($src1, $src2):<<1:rnd:sat")),
1414                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
1415                                              DoubleRegs:$src1,
1416                                              DoubleRegs:$src2))],
1417                "$dst2 = $dst">;
1418
1419 class di_MInst_dididi_acc<string opc, Intrinsic IntID>
1420   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
1421                                            DoubleRegs:$src2),
1422                !strconcat("$dst += ", !strconcat(opc , "($src1, $src2)")),
1423                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
1424                                              DoubleRegs:$src1,
1425                                              DoubleRegs:$src2))],
1426                "$dst2 = $dst">;
1427
1428 class di_MInst_dididi_acc_conj<string opc, Intrinsic IntID>
1429   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
1430                                            DoubleRegs:$src2),
1431                !strconcat("$dst += ", !strconcat(opc , "($src1, $src2*)")),
1432                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
1433                                              DoubleRegs:$src1,
1434                                              DoubleRegs:$src2))],
1435                "$dst2 = $dst">;
1436
1437 class di_MInst_disisi_acc_s1_sat<string opc, Intrinsic IntID>
1438   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1439                                            IntRegs:$src2),
1440                !strconcat("$dst += ",
1441                           !strconcat(opc , "($src1, $src2):<<1:sat")),
1442                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1443                                              IntRegs:$src2))],
1444                "$dst2 = $dst">;
1445
1446 class di_MInst_disi_s1_sat<string opc, Intrinsic IntID>
1447   : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
1448              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):<<1:sat")),
1449              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, IntRegs:$src2))]>;
1450
1451 class di_MInst_didisi_acc_s1_sat<string opc, Intrinsic IntID>
1452   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
1453                                            IntRegs:$src2),
1454                !strconcat("$dst += ",
1455                           !strconcat(opc , "($src1, $src2):<<1:sat")),
1456                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
1457                                              DoubleRegs:$src1,
1458                                              IntRegs:$src2))],
1459                "$dst2 = $dst">;
1460
1461 class si_MInst_disi_s1_rnd_sat<string opc, Intrinsic IntID>
1462   : MInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
1463              !strconcat("$dst = ",
1464                         !strconcat(opc , "($src1, $src2):<<1:rnd:sat")),
1465              [(set IntRegs:$dst, (IntID DoubleRegs:$src1, IntRegs:$src2))]>;
1466
1467 class si_MInst_didi<string opc, Intrinsic IntID>
1468   : MInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1469              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
1470              [(set IntRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
1471
1472 //
1473 // LDInst classes.
1474 //
1475 let mayLoad = 1, hasSideEffects = 0 in
1476 class di_LDInstPI_diu4<string opc, Intrinsic IntID>
1477   : LDInstPI<(outs IntRegs:$dst, DoubleRegs:$dst2),
1478            (ins IntRegs:$src1, IntRegs:$src2, CtrRegs:$src3, s4Imm:$offset),
1479            "$dst2 = memd($src1++#$offset:circ($src3))",
1480            [],
1481            "$src1 = $dst">;
1482
1483
1484 // ALU64 / VB / Vector maximum/minimum unsigned bytes.
1485 def HEXAGON_A2_vmaxub:
1486   di_ALU64_didi                   <"vmaxub",   int_hexagon_A2_vmaxub>;
1487 def HEXAGON_A2_vminub:
1488   di_ALU64_didi                   <"vminub",   int_hexagon_A2_vminub>;
1489
1490 // ALU64 / VB / Vector subtract unsigned bytes.
1491 def HEXAGON_A2_vsubub:
1492   di_ALU64_didi                   <"vsubub",   int_hexagon_A2_vsubub>;
1493 def HEXAGON_A2_vsububs:
1494   di_ALU64_didi_sat               <"vsubub",   int_hexagon_A2_vsububs>;
1495
1496 /********************************************************************
1497 *            MTYPE/ALU                                              *
1498 *********************************************************************/
1499
1500 // MTYPE / ALU / Vector absolute difference.
1501 def HEXAGON_M2_vabsdiffh:
1502   di_MInst_didi                   <"vabsdiffh",int_hexagon_M2_vabsdiffh>;
1503 def HEXAGON_M2_vabsdiffw:
1504   di_MInst_didi                   <"vabsdiffw",int_hexagon_M2_vabsdiffw>;
1505
1506
1507 /********************************************************************
1508 *            MTYPE/COMPLEX                                          *
1509 *********************************************************************/
1510
1511 // MTYPE / COMPLEX / Complex multiply.
1512 // Rdd[-+]=cmpy(Rs, Rt:<<1]:sat
1513 def HEXAGON_M2_cmpys_s1:
1514   di_MInst_sisi_s1_sat            <"cmpy",     int_hexagon_M2_cmpys_s1>;
1515 def HEXAGON_M2_cmpys_s0:
1516   di_MInst_sisi_sat               <"cmpy",     int_hexagon_M2_cmpys_s0>;
1517 def HEXAGON_M2_cmpysc_s1:
1518   di_MInst_sisi_s1_sat_conj       <"cmpy",     int_hexagon_M2_cmpysc_s1>;
1519 def HEXAGON_M2_cmpysc_s0:
1520   di_MInst_sisi_sat_conj          <"cmpy",     int_hexagon_M2_cmpysc_s0>;
1521
1522 def HEXAGON_M2_cmacs_s1:
1523   di_MInst_disisi_acc_s1_sat      <"cmpy",     int_hexagon_M2_cmacs_s1>;
1524 def HEXAGON_M2_cmacs_s0:
1525   di_MInst_disisi_acc_sat         <"cmpy",     int_hexagon_M2_cmacs_s0>;
1526 def HEXAGON_M2_cmacsc_s1:
1527   di_MInst_disisi_acc_s1_sat_conj <"cmpy",     int_hexagon_M2_cmacsc_s1>;
1528 def HEXAGON_M2_cmacsc_s0:
1529   di_MInst_disisi_acc_sat_conj    <"cmpy",     int_hexagon_M2_cmacsc_s0>;
1530
1531 def HEXAGON_M2_cnacs_s1:
1532   di_MInst_disisi_nac_s1_sat      <"cmpy",     int_hexagon_M2_cnacs_s1>;
1533 def HEXAGON_M2_cnacs_s0:
1534   di_MInst_disisi_nac_sat         <"cmpy",     int_hexagon_M2_cnacs_s0>;
1535 def HEXAGON_M2_cnacsc_s1:
1536   di_MInst_disisi_nac_s1_sat_conj <"cmpy",     int_hexagon_M2_cnacsc_s1>;
1537 def HEXAGON_M2_cnacsc_s0:
1538   di_MInst_disisi_nac_sat_conj    <"cmpy",     int_hexagon_M2_cnacsc_s0>;
1539
1540 // MTYPE / COMPLEX / Complex multiply real or imaginary.
1541 def HEXAGON_M2_cmpyr_s0:
1542   di_MInst_sisi                   <"cmpyr",    int_hexagon_M2_cmpyr_s0>;
1543 def HEXAGON_M2_cmacr_s0:
1544   di_MInst_disisi_acc             <"cmpyr",    int_hexagon_M2_cmacr_s0>;
1545
1546 def HEXAGON_M2_cmpyi_s0:
1547   di_MInst_sisi                   <"cmpyi",    int_hexagon_M2_cmpyi_s0>;
1548 def HEXAGON_M2_cmaci_s0:
1549   di_MInst_disisi_acc             <"cmpyi",    int_hexagon_M2_cmaci_s0>;
1550
1551 // MTYPE / COMPLEX / Complex multiply with round and pack.
1552 // Rxx32+=cmpy(Rs32,[*]Rt32:<<1]:rnd:sat
1553 def HEXAGON_M2_cmpyrs_s0:
1554   si_MInst_sisi_rnd_sat           <"cmpy",     int_hexagon_M2_cmpyrs_s0>;
1555 def HEXAGON_M2_cmpyrs_s1:
1556   si_MInst_sisi_s1_rnd_sat        <"cmpy",     int_hexagon_M2_cmpyrs_s1>;
1557
1558 def HEXAGON_M2_cmpyrsc_s0:
1559   si_MInst_sisi_rnd_sat_conj      <"cmpy",     int_hexagon_M2_cmpyrsc_s0>;
1560 def HEXAGON_M2_cmpyrsc_s1:
1561   si_MInst_sisi_s1_rnd_sat_conj   <"cmpy",     int_hexagon_M2_cmpyrsc_s1>;
1562
1563 //MTYPE / COMPLEX / Vector complex multiply real or imaginary.
1564 def HEXAGON_M2_vcmpy_s0_sat_i:
1565   di_MInst_didi_sat               <"vcmpyi",   int_hexagon_M2_vcmpy_s0_sat_i>;
1566 def HEXAGON_M2_vcmpy_s1_sat_i:
1567   di_MInst_didi_s1_sat            <"vcmpyi",   int_hexagon_M2_vcmpy_s1_sat_i>;
1568
1569 def HEXAGON_M2_vcmpy_s0_sat_r:
1570   di_MInst_didi_sat               <"vcmpyr",   int_hexagon_M2_vcmpy_s0_sat_r>;
1571 def HEXAGON_M2_vcmpy_s1_sat_r:
1572   di_MInst_didi_s1_sat            <"vcmpyr",   int_hexagon_M2_vcmpy_s1_sat_r>;
1573
1574 def HEXAGON_M2_vcmac_s0_sat_i:
1575   di_MInst_dididi_acc_sat         <"vcmpyi",   int_hexagon_M2_vcmac_s0_sat_i>;
1576 def HEXAGON_M2_vcmac_s0_sat_r:
1577   di_MInst_dididi_acc_sat         <"vcmpyr",   int_hexagon_M2_vcmac_s0_sat_r>;
1578
1579 //MTYPE / COMPLEX / Vector reduce complex multiply real or imaginary.
1580 def HEXAGON_M2_vrcmpyi_s0:
1581   di_MInst_didi                   <"vrcmpyi",  int_hexagon_M2_vrcmpyi_s0>;
1582 def HEXAGON_M2_vrcmpyr_s0:
1583   di_MInst_didi                   <"vrcmpyr",  int_hexagon_M2_vrcmpyr_s0>;
1584
1585 def HEXAGON_M2_vrcmpyi_s0c:
1586   di_MInst_didi_conj              <"vrcmpyi",  int_hexagon_M2_vrcmpyi_s0c>;
1587 def HEXAGON_M2_vrcmpyr_s0c:
1588   di_MInst_didi_conj              <"vrcmpyr",  int_hexagon_M2_vrcmpyr_s0c>;
1589
1590 def HEXAGON_M2_vrcmaci_s0:
1591   di_MInst_dididi_acc             <"vrcmpyi",  int_hexagon_M2_vrcmaci_s0>;
1592 def HEXAGON_M2_vrcmacr_s0:
1593   di_MInst_dididi_acc             <"vrcmpyr",  int_hexagon_M2_vrcmacr_s0>;
1594
1595 def HEXAGON_M2_vrcmaci_s0c:
1596   di_MInst_dididi_acc_conj        <"vrcmpyi",  int_hexagon_M2_vrcmaci_s0c>;
1597 def HEXAGON_M2_vrcmacr_s0c:
1598   di_MInst_dididi_acc_conj        <"vrcmpyr",  int_hexagon_M2_vrcmacr_s0c>;
1599
1600
1601 /********************************************************************
1602 *            MTYPE/MPYH                                             *
1603 *********************************************************************/
1604
1605 // MTYPE / MPYH / Multiply word by half (32x16).
1606 //Rdd[+]=vmpywoh(Rss,Rtt)[:<<1][:rnd][:sat]
1607 //Rdd[+]=vmpyweh(Rss,Rtt)[:<<1][:rnd][:sat]
1608 def HEXAGON_M2_mmpyl_rs1:
1609   di_MInst_didi_s1_rnd_sat        <"vmpyweh",  int_hexagon_M2_mmpyl_rs1>;
1610 def HEXAGON_M2_mmpyl_s1:
1611   di_MInst_didi_s1_sat            <"vmpyweh",  int_hexagon_M2_mmpyl_s1>;
1612 def HEXAGON_M2_mmpyl_rs0:
1613   di_MInst_didi_rnd_sat           <"vmpyweh",  int_hexagon_M2_mmpyl_rs0>;
1614 def HEXAGON_M2_mmpyl_s0:
1615   di_MInst_didi_sat               <"vmpyweh",  int_hexagon_M2_mmpyl_s0>;
1616 def HEXAGON_M2_mmpyh_rs1:
1617   di_MInst_didi_s1_rnd_sat        <"vmpywoh",  int_hexagon_M2_mmpyh_rs1>;
1618 def HEXAGON_M2_mmpyh_s1:
1619   di_MInst_didi_s1_sat            <"vmpywoh",  int_hexagon_M2_mmpyh_s1>;
1620 def HEXAGON_M2_mmpyh_rs0:
1621   di_MInst_didi_rnd_sat           <"vmpywoh",  int_hexagon_M2_mmpyh_rs0>;
1622 def HEXAGON_M2_mmpyh_s0:
1623   di_MInst_didi_sat               <"vmpywoh",  int_hexagon_M2_mmpyh_s0>;
1624 def HEXAGON_M2_mmacls_rs1:
1625   di_MInst_dididi_acc_s1_rnd_sat  <"vmpyweh",  int_hexagon_M2_mmacls_rs1>;
1626 def HEXAGON_M2_mmacls_s1:
1627   di_MInst_dididi_acc_s1_sat      <"vmpyweh",  int_hexagon_M2_mmacls_s1>;
1628 def HEXAGON_M2_mmacls_rs0:
1629   di_MInst_dididi_acc_rnd_sat     <"vmpyweh",  int_hexagon_M2_mmacls_rs0>;
1630 def HEXAGON_M2_mmacls_s0:
1631   di_MInst_dididi_acc_sat         <"vmpyweh",  int_hexagon_M2_mmacls_s0>;
1632 def HEXAGON_M2_mmachs_rs1:
1633   di_MInst_dididi_acc_s1_rnd_sat  <"vmpywoh",  int_hexagon_M2_mmachs_rs1>;
1634 def HEXAGON_M2_mmachs_s1:
1635   di_MInst_dididi_acc_s1_sat      <"vmpywoh",  int_hexagon_M2_mmachs_s1>;
1636 def HEXAGON_M2_mmachs_rs0:
1637   di_MInst_dididi_acc_rnd_sat     <"vmpywoh",  int_hexagon_M2_mmachs_rs0>;
1638 def HEXAGON_M2_mmachs_s0:
1639   di_MInst_dididi_acc_sat         <"vmpywoh",  int_hexagon_M2_mmachs_s0>;
1640
1641 // MTYPE / MPYH / Multiply word by unsigned half (32x16).
1642 //Rdd[+]=vmpywouh(Rss,Rtt)[:<<1][:rnd][:sat]
1643 //Rdd[+]=vmpyweuh(Rss,Rtt)[:<<1][:rnd][:sat]
1644 def HEXAGON_M2_mmpyul_rs1:
1645   di_MInst_didi_s1_rnd_sat        <"vmpyweuh", int_hexagon_M2_mmpyul_rs1>;
1646 def HEXAGON_M2_mmpyul_s1:
1647   di_MInst_didi_s1_sat            <"vmpyweuh", int_hexagon_M2_mmpyul_s1>;
1648 def HEXAGON_M2_mmpyul_rs0:
1649   di_MInst_didi_rnd_sat           <"vmpyweuh", int_hexagon_M2_mmpyul_rs0>;
1650 def HEXAGON_M2_mmpyul_s0:
1651   di_MInst_didi_sat               <"vmpyweuh", int_hexagon_M2_mmpyul_s0>;
1652 def HEXAGON_M2_mmpyuh_rs1:
1653   di_MInst_didi_s1_rnd_sat        <"vmpywouh", int_hexagon_M2_mmpyuh_rs1>;
1654 def HEXAGON_M2_mmpyuh_s1:
1655   di_MInst_didi_s1_sat            <"vmpywouh", int_hexagon_M2_mmpyuh_s1>;
1656 def HEXAGON_M2_mmpyuh_rs0:
1657   di_MInst_didi_rnd_sat           <"vmpywouh", int_hexagon_M2_mmpyuh_rs0>;
1658 def HEXAGON_M2_mmpyuh_s0:
1659   di_MInst_didi_sat               <"vmpywouh", int_hexagon_M2_mmpyuh_s0>;
1660 def HEXAGON_M2_mmaculs_rs1:
1661   di_MInst_dididi_acc_s1_rnd_sat  <"vmpyweuh", int_hexagon_M2_mmaculs_rs1>;
1662 def HEXAGON_M2_mmaculs_s1:
1663   di_MInst_dididi_acc_s1_sat      <"vmpyweuh", int_hexagon_M2_mmaculs_s1>;
1664 def HEXAGON_M2_mmaculs_rs0:
1665   di_MInst_dididi_acc_rnd_sat     <"vmpyweuh", int_hexagon_M2_mmaculs_rs0>;
1666 def HEXAGON_M2_mmaculs_s0:
1667   di_MInst_dididi_acc_sat         <"vmpyweuh", int_hexagon_M2_mmaculs_s0>;
1668 def HEXAGON_M2_mmacuhs_rs1:
1669   di_MInst_dididi_acc_s1_rnd_sat  <"vmpywouh", int_hexagon_M2_mmacuhs_rs1>;
1670 def HEXAGON_M2_mmacuhs_s1:
1671   di_MInst_dididi_acc_s1_sat      <"vmpywouh", int_hexagon_M2_mmacuhs_s1>;
1672 def HEXAGON_M2_mmacuhs_rs0:
1673   di_MInst_dididi_acc_rnd_sat     <"vmpywouh", int_hexagon_M2_mmacuhs_rs0>;
1674 def HEXAGON_M2_mmacuhs_s0:
1675   di_MInst_dididi_acc_sat         <"vmpywouh", int_hexagon_M2_mmacuhs_s0>;
1676
1677 /********************************************************************
1678 *            MTYPE/VB                                               *
1679 *********************************************************************/
1680
1681 // MTYPE / VB / Vector reduce add unsigned bytes.
1682 def HEXAGON_A2_vraddub:
1683   di_MInst_didi                   <"vraddub", int_hexagon_A2_vraddub>;
1684 def HEXAGON_A2_vraddub_acc:
1685   di_MInst_dididi_acc             <"vraddub", int_hexagon_A2_vraddub_acc>;
1686
1687 // MTYPE / VB / Vector sum of absolute differences unsigned bytes.
1688 def HEXAGON_A2_vrsadub:
1689   di_MInst_didi                   <"vrsadub", int_hexagon_A2_vrsadub>;
1690 def HEXAGON_A2_vrsadub_acc:
1691   di_MInst_dididi_acc             <"vrsadub", int_hexagon_A2_vrsadub_acc>;
1692
1693 /********************************************************************
1694 *            MTYPE/VH                                               *
1695 *********************************************************************/
1696
1697 // MTYPE / VH / Vector dual multiply.
1698 def HEXAGON_M2_vdmpys_s1:
1699   di_MInst_didi_s1_sat            <"vdmpy",   int_hexagon_M2_vdmpys_s1>;
1700 def HEXAGON_M2_vdmpys_s0:
1701   di_MInst_didi_sat               <"vdmpy",   int_hexagon_M2_vdmpys_s0>;
1702 def HEXAGON_M2_vdmacs_s1:
1703   di_MInst_dididi_acc_s1_sat      <"vdmpy",   int_hexagon_M2_vdmacs_s1>;
1704 def HEXAGON_M2_vdmacs_s0:
1705   di_MInst_dididi_acc_sat         <"vdmpy",   int_hexagon_M2_vdmacs_s0>;
1706
1707 // MTYPE / VH / Vector dual multiply with round and pack.
1708 def HEXAGON_M2_vdmpyrs_s0:
1709   si_MInst_didi_rnd_sat           <"vdmpy",   int_hexagon_M2_vdmpyrs_s0>;
1710 def HEXAGON_M2_vdmpyrs_s1:
1711   si_MInst_didi_s1_rnd_sat        <"vdmpy",   int_hexagon_M2_vdmpyrs_s1>;
1712
1713 // MTYPE / VH / Vector multiply even halfwords.
1714 def HEXAGON_M2_vmpy2es_s1:
1715   di_MInst_didi_s1_sat            <"vmpyeh",  int_hexagon_M2_vmpy2es_s1>;
1716 def HEXAGON_M2_vmpy2es_s0:
1717   di_MInst_didi_sat               <"vmpyeh",  int_hexagon_M2_vmpy2es_s0>;
1718 def HEXAGON_M2_vmac2es:
1719   di_MInst_dididi_acc             <"vmpyeh",  int_hexagon_M2_vmac2es>;
1720 def HEXAGON_M2_vmac2es_s1:
1721   di_MInst_dididi_acc_s1_sat      <"vmpyeh",  int_hexagon_M2_vmac2es_s1>;
1722 def HEXAGON_M2_vmac2es_s0:
1723   di_MInst_dididi_acc_sat         <"vmpyeh",  int_hexagon_M2_vmac2es_s0>;
1724
1725 // MTYPE / VH / Vector multiply halfwords.
1726 def HEXAGON_M2_vmpy2s_s0:
1727   di_MInst_sisi_sat               <"vmpyh",   int_hexagon_M2_vmpy2s_s0>;
1728 def HEXAGON_M2_vmpy2s_s1:
1729   di_MInst_sisi_s1_sat            <"vmpyh",   int_hexagon_M2_vmpy2s_s1>;
1730 def HEXAGON_M2_vmac2:
1731   di_MInst_disisi_acc             <"vmpyh",   int_hexagon_M2_vmac2>;
1732 def HEXAGON_M2_vmac2s_s0:
1733   di_MInst_disisi_acc_sat         <"vmpyh",   int_hexagon_M2_vmac2s_s0>;
1734 def HEXAGON_M2_vmac2s_s1:
1735   di_MInst_disisi_acc_s1_sat      <"vmpyh",   int_hexagon_M2_vmac2s_s1>;
1736
1737 // MTYPE / VH / Vector multiply halfwords with round and pack.
1738 def HEXAGON_M2_vmpy2s_s0pack:
1739   si_MInst_sisi_rnd_sat           <"vmpyh",   int_hexagon_M2_vmpy2s_s0pack>;
1740 def HEXAGON_M2_vmpy2s_s1pack:
1741   si_MInst_sisi_s1_rnd_sat        <"vmpyh",   int_hexagon_M2_vmpy2s_s1pack>;
1742
1743 // MTYPE / VH / Vector reduce multiply halfwords.
1744 // Rxx32+=vrmpyh(Rss32,Rtt32)
1745 def HEXAGON_M2_vrmpy_s0:
1746   di_MInst_didi                   <"vrmpyh",  int_hexagon_M2_vrmpy_s0>;
1747 def HEXAGON_M2_vrmac_s0:
1748   di_MInst_dididi_acc             <"vrmpyh",  int_hexagon_M2_vrmac_s0>;
1749
1750 /********************************************************************
1751 *            STYPE/COMPLEX                                          *
1752 *********************************************************************/
1753
1754 // STYPE / COMPLEX / Vector Complex conjugate.
1755 def HEXAGON_A2_vconj:
1756   di_SInst_di_sat                 <"vconj",   int_hexagon_A2_vconj>;
1757
1758 // STYPE / COMPLEX / Vector Complex rotate.
1759 def HEXAGON_S2_vcrotate:
1760   di_SInst_disi                   <"vcrotate",int_hexagon_S2_vcrotate>;
1761
1762
1763 /********************************************************************
1764 *            STYPE/PERM                                             *
1765 *********************************************************************/
1766
1767 // STYPE / PERM / Vector align.
1768 // Need custom lowering
1769 def HEXAGON_S2_valignib:
1770   di_SInst_didiu3                 <"valignb", int_hexagon_S2_valignib>;
1771 def HEXAGON_S2_valignrb:
1772   di_SInst_didiqi                 <"valignb", int_hexagon_S2_valignrb>;
1773
1774 // STYPE / PERM / Vector round and pack.
1775 def HEXAGON_S2_vrndpackwh:
1776   si_SInst_di                     <"vrndwh",  int_hexagon_S2_vrndpackwh>;
1777 def HEXAGON_S2_vrndpackwhs:
1778   si_SInst_di_sat                 <"vrndwh",  int_hexagon_S2_vrndpackwhs>;
1779
1780 // STYPE / PERM / Vector saturate and pack.
1781 def HEXAGON_S2_svsathb:
1782   si_SInst_si                     <"vsathb",  int_hexagon_S2_svsathb>;
1783 def HEXAGON_S2_vsathb:
1784   si_SInst_di                     <"vsathb",  int_hexagon_S2_vsathb>;
1785 def HEXAGON_S2_svsathub:
1786   si_SInst_si                     <"vsathub", int_hexagon_S2_svsathub>;
1787 def HEXAGON_S2_vsathub:
1788   si_SInst_di                     <"vsathub", int_hexagon_S2_vsathub>;
1789 def HEXAGON_S2_vsatwh:
1790   si_SInst_di                     <"vsatwh",  int_hexagon_S2_vsatwh>;
1791 def HEXAGON_S2_vsatwuh:
1792   si_SInst_di                     <"vsatwuh", int_hexagon_S2_vsatwuh>;
1793
1794 // STYPE / PERM / Vector saturate without pack.
1795 def HEXAGON_S2_vsathb_nopack:
1796   di_SInst_di                     <"vsathb",  int_hexagon_S2_vsathb_nopack>;
1797 def HEXAGON_S2_vsathub_nopack:
1798   di_SInst_di                     <"vsathub", int_hexagon_S2_vsathub_nopack>;
1799 def HEXAGON_S2_vsatwh_nopack:
1800   di_SInst_di                     <"vsatwh",  int_hexagon_S2_vsatwh_nopack>;
1801 def HEXAGON_S2_vsatwuh_nopack:
1802   di_SInst_di                     <"vsatwuh", int_hexagon_S2_vsatwuh_nopack>;
1803
1804 // STYPE / PERM / Vector shuffle.
1805 def HEXAGON_S2_shuffeb:
1806   di_SInst_didi                   <"shuffeb", int_hexagon_S2_shuffeb>;
1807 def HEXAGON_S2_shuffeh:
1808   di_SInst_didi                   <"shuffeh", int_hexagon_S2_shuffeh>;
1809 def HEXAGON_S2_shuffob:
1810   di_SInst_didi                   <"shuffob", int_hexagon_S2_shuffob>;
1811 def HEXAGON_S2_shuffoh:
1812   di_SInst_didi                   <"shuffoh", int_hexagon_S2_shuffoh>;
1813
1814 // STYPE / PERM / Vector splat bytes.
1815 def HEXAGON_S2_vsplatrb:
1816   si_SInst_si                     <"vsplatb", int_hexagon_S2_vsplatrb>;
1817
1818 // STYPE / PERM / Vector splat halfwords.
1819 def HEXAGON_S2_vsplatrh:
1820   di_SInst_si                     <"vsplath", int_hexagon_S2_vsplatrh>;
1821
1822 // STYPE / PERM / Vector splice.
1823 def Hexagon_S2_vsplicerb:
1824   di_SInst_didiqi                 <"vspliceb",int_hexagon_S2_vsplicerb>;
1825 def Hexagon_S2_vspliceib:
1826   di_SInst_didiu3                 <"vspliceb",int_hexagon_S2_vspliceib>;
1827
1828 // STYPE / PERM / Sign extend.
1829 def HEXAGON_S2_vsxtbh:
1830   di_SInst_si                     <"vsxtbh",  int_hexagon_S2_vsxtbh>;
1831 def HEXAGON_S2_vsxthw:
1832   di_SInst_si                     <"vsxthw",  int_hexagon_S2_vsxthw>;
1833
1834 // STYPE / PERM / Truncate.
1835 def HEXAGON_S2_vtrunehb:
1836   si_SInst_di                     <"vtrunehb",int_hexagon_S2_vtrunehb>;
1837 def HEXAGON_S2_vtrunohb:
1838   si_SInst_di                     <"vtrunohb",int_hexagon_S2_vtrunohb>;
1839 def HEXAGON_S2_vtrunewh:
1840   di_SInst_didi                   <"vtrunewh",int_hexagon_S2_vtrunewh>;
1841 def HEXAGON_S2_vtrunowh:
1842   di_SInst_didi                   <"vtrunowh",int_hexagon_S2_vtrunowh>;
1843
1844 // STYPE / PERM / Zero extend.
1845 def HEXAGON_S2_vzxtbh:
1846   di_SInst_si                     <"vzxtbh",  int_hexagon_S2_vzxtbh>;
1847 def HEXAGON_S2_vzxthw:
1848   di_SInst_si                     <"vzxthw",  int_hexagon_S2_vzxthw>;
1849
1850
1851 /********************************************************************
1852 *            STYPE/PRED                                             *
1853 *********************************************************************/
1854
1855 // STYPE / PRED / Mask generate from predicate.
1856 def HEXAGON_C2_mask:
1857   di_SInst_qi                     <"mask",   int_hexagon_C2_mask>;
1858
1859 // STYPE / PRED / Predicate transfer.
1860 def HEXAGON_C2_tfrpr:
1861   si_SInst_qi                     <"",       int_hexagon_C2_tfrpr>;
1862 def HEXAGON_C2_tfrrp:
1863   qi_SInst_si                     <"",       int_hexagon_C2_tfrrp>;
1864
1865 // STYPE / PRED / Viterbi pack even and odd predicate bits.
1866 def HEXAGON_C2_vitpack:
1867   si_SInst_qiqi                   <"vitpack",int_hexagon_C2_vitpack>;
1868
1869
1870 /********************************************************************
1871 *            STYPE/VH                                               *
1872 *********************************************************************/
1873
1874 // STYPE / VH / Vector absolute value halfwords.
1875 // Rdd64=vabsh(Rss64)
1876 def HEXAGON_A2_vabsh:
1877   di_SInst_di                     <"vabsh",   int_hexagon_A2_vabsh>;
1878 def HEXAGON_A2_vabshsat:
1879   di_SInst_di_sat                 <"vabsh",   int_hexagon_A2_vabshsat>;
1880
1881 // STYPE / VH / Vector shift halfwords by immediate.
1882 // Rdd64=v[asl/asr/lsr]h(Rss64,Rt32)
1883 def HEXAGON_S2_asl_i_vh:
1884   di_SInst_disi                   <"vaslh",   int_hexagon_S2_asl_i_vh>;
1885 def HEXAGON_S2_asr_i_vh:
1886   di_SInst_disi                   <"vasrh",   int_hexagon_S2_asr_i_vh>;
1887 def HEXAGON_S2_lsr_i_vh:
1888   di_SInst_disi                   <"vlsrh",   int_hexagon_S2_lsr_i_vh>;
1889
1890 // STYPE / VH / Vector shift halfwords by register.
1891 // Rdd64=v[asl/asr/lsl/lsr]w(Rss64,Rt32)
1892 def HEXAGON_S2_asl_r_vh:
1893   di_SInst_disi                   <"vaslh",   int_hexagon_S2_asl_r_vh>;
1894 def HEXAGON_S2_asr_r_vh:
1895   di_SInst_disi                   <"vasrh",   int_hexagon_S2_asr_r_vh>;
1896 def HEXAGON_S2_lsl_r_vh:
1897   di_SInst_disi                   <"vlslh",   int_hexagon_S2_lsl_r_vh>;
1898 def HEXAGON_S2_lsr_r_vh:
1899   di_SInst_disi                   <"vlsrh",   int_hexagon_S2_lsr_r_vh>;
1900
1901
1902 /********************************************************************
1903 *            STYPE/VW                                               *
1904 *********************************************************************/
1905
1906 // STYPE / VW / Vector absolute value words.
1907 def HEXAGON_A2_vabsw:
1908   di_SInst_di                     <"vabsw",   int_hexagon_A2_vabsw>;
1909 def HEXAGON_A2_vabswsat:
1910   di_SInst_di_sat                 <"vabsw",   int_hexagon_A2_vabswsat>;
1911
1912 // STYPE / VW / Vector shift words by immediate.
1913 // Rdd64=v[asl/vsl]w(Rss64,Rt32)
1914 def HEXAGON_S2_asl_i_vw:
1915   di_SInst_disi                   <"vaslw",   int_hexagon_S2_asl_i_vw>;
1916 def HEXAGON_S2_asr_i_vw:
1917   di_SInst_disi                   <"vasrw",   int_hexagon_S2_asr_i_vw>;
1918 def HEXAGON_S2_lsr_i_vw:
1919   di_SInst_disi                   <"vlsrw",   int_hexagon_S2_lsr_i_vw>;
1920
1921 // STYPE / VW / Vector shift words by register.
1922 // Rdd64=v[asl/vsl]w(Rss64,Rt32)
1923 def HEXAGON_S2_asl_r_vw:
1924   di_SInst_disi                   <"vaslw",   int_hexagon_S2_asl_r_vw>;
1925 def HEXAGON_S2_asr_r_vw:
1926   di_SInst_disi                   <"vasrw",   int_hexagon_S2_asr_r_vw>;
1927 def HEXAGON_S2_lsl_r_vw:
1928   di_SInst_disi                   <"vlslw",   int_hexagon_S2_lsl_r_vw>;
1929 def HEXAGON_S2_lsr_r_vw:
1930   di_SInst_disi                   <"vlsrw",   int_hexagon_S2_lsr_r_vw>;
1931
1932 // STYPE / VW / Vector shift words with truncate and pack.
1933 def HEXAGON_S2_asr_r_svw_trun:
1934   si_SInst_disi                   <"vasrw",   int_hexagon_S2_asr_r_svw_trun>;
1935 def HEXAGON_S2_asr_i_svw_trun:
1936   si_SInst_diu5                   <"vasrw",   int_hexagon_S2_asr_i_svw_trun>;
1937
1938 // LD / Circular loads.
1939 def HEXAGON_circ_ldd:
1940   di_LDInstPI_diu4                <"circ_ldd", int_hexagon_circ_ldd>;
1941
1942 include "HexagonIntrinsicsV3.td"
1943 include "HexagonIntrinsicsV4.td"
1944 include "HexagonIntrinsicsV5.td"