lib/Target/Hexagon/HexagonIntrinsics.td

   1 //===-- HexagonIntrinsics.td - Instruction intrinsics ------*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 // This is populated based on the following specs:
  10 // Hexagon V2 Architecture
  11 // Application-Level Specification
  12 // 80-V9418-8 Rev. B
  13 // March 4, 2008
  14 //===----------------------------------------------------------------------===//
  15
  16 class T_I_pat <InstHexagon MI, Intrinsic IntID>
  17   : Pat <(IntID imm:$Is),
  18          (MI imm:$Is)>;
  19
  20 class T_R_pat <InstHexagon MI, Intrinsic IntID>
  21   : Pat <(IntID I32:$Rs),
  22          (MI I32:$Rs)>;
  23
  24 class T_P_pat <InstHexagon MI, Intrinsic IntID>
  25   : Pat <(IntID I64:$Rs),
  26          (MI DoubleRegs:$Rs)>;
  27
  28 class T_II_pat <InstHexagon MI, Intrinsic IntID, PatFrag Imm1, PatFrag Imm2>
  29   : Pat<(IntID Imm1:$Is, Imm2:$It),
  30         (MI Imm1:$Is, Imm2:$It)>;
  31
  32 class T_RI_pat <InstHexagon MI, Intrinsic IntID, PatLeaf ImmPred = PatLeaf<(i32 imm)>>
  33   : Pat<(IntID I32:$Rs, ImmPred:$It),
  34         (MI I32:$Rs, ImmPred:$It)>;
  35
  36 class T_IR_pat <InstHexagon MI, Intrinsic IntID, PatFrag ImmPred = PatLeaf<(i32 imm)>>
  37   : Pat<(IntID ImmPred:$Is, I32:$Rt),
  38         (MI ImmPred:$Is, I32:$Rt)>;
  39
  40 class T_PI_pat <InstHexagon MI, Intrinsic IntID>
  41   : Pat<(IntID I64:$Rs, imm:$It),
  42         (MI DoubleRegs:$Rs, imm:$It)>;
  43
  44 class T_RP_pat <InstHexagon MI, Intrinsic IntID>
  45   : Pat<(IntID I32:$Rs, I64:$Rt),
  46         (MI I32:$Rs, DoubleRegs:$Rt)>;
  47
  48 class T_RR_pat <InstHexagon MI, Intrinsic IntID>
  49   : Pat <(IntID I32:$Rs, I32:$Rt),
  50          (MI I32:$Rs, I32:$Rt)>;
  51
  52 class T_PP_pat <InstHexagon MI, Intrinsic IntID>
  53   : Pat <(IntID I64:$Rs, I64:$Rt),
  54          (MI DoubleRegs:$Rs, DoubleRegs:$Rt)>;
  55
  56 class T_QII_pat <InstHexagon MI, Intrinsic IntID, PatFrag Imm1, PatFrag Imm2>
  57   : Pat <(IntID (i32 PredRegs:$Ps), Imm1:$Is, Imm2:$It),
  58          (MI PredRegs:$Ps, Imm1:$Is, Imm2:$It)>;
  59
  60 class T_QRI_pat <InstHexagon MI, Intrinsic IntID, PatFrag ImmPred>
  61   : Pat <(IntID (i32 PredRegs:$Ps), I32:$Rs, ImmPred:$Is),
  62          (MI PredRegs:$Ps, I32:$Rs, ImmPred:$Is)>;
  63
  64 class T_QIR_pat <InstHexagon MI, Intrinsic IntID, PatFrag ImmPred>
  65   : Pat <(IntID (i32 PredRegs:$Ps), ImmPred:$Is, I32:$Rs),
  66          (MI PredRegs:$Ps, ImmPred:$Is, I32:$Rs)>;
  67
  68 class T_RRI_pat <InstHexagon MI, Intrinsic IntID>
  69   : Pat <(IntID I32:$Rs, I32:$Rt, imm:$Iu),
  70          (MI I32:$Rs, I32:$Rt, imm:$Iu)>;
  71
  72 class T_RII_pat <InstHexagon MI, Intrinsic IntID>
  73   : Pat <(IntID I32:$Rs, imm:$It, imm:$Iu),
  74          (MI I32:$Rs, imm:$It, imm:$Iu)>;
  75
  76 class T_IRI_pat <InstHexagon MI, Intrinsic IntID>
  77   : Pat <(IntID imm:$It, I32:$Rs, imm:$Iu),
  78          (MI imm:$It, I32:$Rs, imm:$Iu)>;
  79
  80 class T_IRR_pat <InstHexagon MI, Intrinsic IntID>
  81   : Pat <(IntID imm:$Is, I32:$Rs, I32:$Rt),
  82          (MI imm:$Is, I32:$Rs, I32:$Rt)>;
  83
  84 class T_RIR_pat <InstHexagon MI, Intrinsic IntID>
  85   : Pat <(IntID I32:$Rs, imm:$Is, I32:$Rt),
  86          (MI I32:$Rs, imm:$Is, I32:$Rt)>;
  87
  88 class T_RRR_pat <InstHexagon MI, Intrinsic IntID>
  89   : Pat <(IntID I32:$Rs, I32:$Rt, I32:$Ru),
  90          (MI I32:$Rs, I32:$Rt, I32:$Ru)>;
  91
  92 class T_PPI_pat <InstHexagon MI, Intrinsic IntID>
  93   : Pat <(IntID I64:$Rs, I64:$Rt, imm:$Iu),
  94          (MI DoubleRegs:$Rs, DoubleRegs:$Rt, imm:$Iu)>;
  95
  96 class T_PII_pat <InstHexagon MI, Intrinsic IntID>
  97   : Pat <(IntID I64:$Rs, imm:$It, imm:$Iu),
  98          (MI DoubleRegs:$Rs, imm:$It, imm:$Iu)>;
  99
 100 class T_PPP_pat <InstHexagon MI, Intrinsic IntID>
 101   : Pat <(IntID I64:$Rs, I64:$Rt, I64:$Ru),
 102          (MI DoubleRegs:$Rs, DoubleRegs:$Rt, DoubleRegs:$Ru)>;
 103
 104 class T_PPR_pat <InstHexagon MI, Intrinsic IntID>
 105   : Pat <(IntID I64:$Rs, I64:$Rt, I32:$Ru),
 106          (MI DoubleRegs:$Rs, DoubleRegs:$Rt, I32:$Ru)>;
 107
 108 class T_PRR_pat <InstHexagon MI, Intrinsic IntID>
 109   : Pat <(IntID I64:$Rs, I32:$Rt, I32:$Ru),
 110          (MI DoubleRegs:$Rs, I32:$Rt, I32:$Ru)>;
 111
 112 class T_PR_pat <InstHexagon MI, Intrinsic IntID>
 113   : Pat <(IntID I64:$Rs, I32:$Rt),
 114          (MI DoubleRegs:$Rs, I32:$Rt)>;
 115
 116 class T_D_pat <InstHexagon MI, Intrinsic IntID>
 117   : Pat<(IntID (F64:$Rs)),
 118         (MI (F64:$Rs))>;
 119
 120 class T_DI_pat <InstHexagon MI, Intrinsic IntID,
 121                 PatLeaf ImmPred = PatLeaf<(i32 imm)>>
 122   : Pat<(IntID F64:$Rs, ImmPred:$It),
 123         (MI F64:$Rs, ImmPred:$It)>;
 124
 125 class T_F_pat <InstHexagon MI, Intrinsic IntID>
 126   : Pat<(IntID F32:$Rs),
 127         (MI F32:$Rs)>;
 128
 129 class T_FI_pat <InstHexagon MI, Intrinsic IntID,
 130                  PatLeaf ImmPred = PatLeaf<(i32 imm)>>
 131   : Pat<(IntID F32:$Rs, ImmPred:$It),
 132         (MI F32:$Rs, ImmPred:$It)>;
 133
 134 class T_FF_pat <InstHexagon MI, Intrinsic IntID>
 135   : Pat<(IntID F32:$Rs, F32:$Rt),
 136         (MI F32:$Rs, F32:$Rt)>;
 137
 138 class T_DD_pat <InstHexagon MI, Intrinsic IntID>
 139   : Pat<(IntID F64:$Rs, F64:$Rt),
 140         (MI F64:$Rs, F64:$Rt)>;
 141
 142 class T_FFF_pat <InstHexagon MI, Intrinsic IntID>
 143   : Pat<(IntID F32:$Rs, F32:$Rt, F32:$Ru),
 144         (MI F32:$Rs, F32:$Rt, F32:$Ru)>;
 145
 146 class T_FFFQ_pat <InstHexagon MI, Intrinsic IntID>
 147   : Pat <(IntID F32:$Rs, F32:$Rt, F32:$Ru, (i32 PredRegs:$Rx)),
 148          (MI F32:$Rs, F32:$Rt, F32:$Ru, PredRegs:$Rx)>;
 149
 150 //===----------------------------------------------------------------------===//
 151 // MPYS / Multipy signed/unsigned halfwords
 152 //Rd=mpy[u](Rs.[H|L],Rt.[H|L])[:<<1][:rnd][:sat]
 153 //===----------------------------------------------------------------------===//
 154
 155 def : T_RR_pat <M2_mpy_ll_s1, int_hexagon_M2_mpy_ll_s1>;
 156 def : T_RR_pat <M2_mpy_ll_s0, int_hexagon_M2_mpy_ll_s0>;
 157 def : T_RR_pat <M2_mpy_lh_s1, int_hexagon_M2_mpy_lh_s1>;
 158 def : T_RR_pat <M2_mpy_lh_s0, int_hexagon_M2_mpy_lh_s0>;
 159 def : T_RR_pat <M2_mpy_hl_s1, int_hexagon_M2_mpy_hl_s1>;
 160 def : T_RR_pat <M2_mpy_hl_s0, int_hexagon_M2_mpy_hl_s0>;
 161 def : T_RR_pat <M2_mpy_hh_s1, int_hexagon_M2_mpy_hh_s1>;
 162 def : T_RR_pat <M2_mpy_hh_s0, int_hexagon_M2_mpy_hh_s0>;
 163
 164 def : T_RR_pat <M2_mpyu_ll_s1, int_hexagon_M2_mpyu_ll_s1>;
 165 def : T_RR_pat <M2_mpyu_ll_s0, int_hexagon_M2_mpyu_ll_s0>;
 166 def : T_RR_pat <M2_mpyu_lh_s1, int_hexagon_M2_mpyu_lh_s1>;
 167 def : T_RR_pat <M2_mpyu_lh_s0, int_hexagon_M2_mpyu_lh_s0>;
 168 def : T_RR_pat <M2_mpyu_hl_s1, int_hexagon_M2_mpyu_hl_s1>;
 169 def : T_RR_pat <M2_mpyu_hl_s0, int_hexagon_M2_mpyu_hl_s0>;
 170 def : T_RR_pat <M2_mpyu_hh_s1, int_hexagon_M2_mpyu_hh_s1>;
 171 def : T_RR_pat <M2_mpyu_hh_s0, int_hexagon_M2_mpyu_hh_s0>;
 172
 173 def : T_RR_pat <M2_mpy_sat_ll_s1, int_hexagon_M2_mpy_sat_ll_s1>;
 174 def : T_RR_pat <M2_mpy_sat_ll_s0, int_hexagon_M2_mpy_sat_ll_s0>;
 175 def : T_RR_pat <M2_mpy_sat_lh_s1, int_hexagon_M2_mpy_sat_lh_s1>;
 176 def : T_RR_pat <M2_mpy_sat_lh_s0, int_hexagon_M2_mpy_sat_lh_s0>;
 177 def : T_RR_pat <M2_mpy_sat_hl_s1, int_hexagon_M2_mpy_sat_hl_s1>;
 178 def : T_RR_pat <M2_mpy_sat_hl_s0, int_hexagon_M2_mpy_sat_hl_s0>;
 179 def : T_RR_pat <M2_mpy_sat_hh_s1, int_hexagon_M2_mpy_sat_hh_s1>;
 180 def : T_RR_pat <M2_mpy_sat_hh_s0, int_hexagon_M2_mpy_sat_hh_s0>;
 181
 182 def : T_RR_pat <M2_mpy_rnd_ll_s1, int_hexagon_M2_mpy_rnd_ll_s1>;
 183 def : T_RR_pat <M2_mpy_rnd_ll_s0, int_hexagon_M2_mpy_rnd_ll_s0>;
 184 def : T_RR_pat <M2_mpy_rnd_lh_s1, int_hexagon_M2_mpy_rnd_lh_s1>;
 185 def : T_RR_pat <M2_mpy_rnd_lh_s0, int_hexagon_M2_mpy_rnd_lh_s0>;
 186 def : T_RR_pat <M2_mpy_rnd_hl_s1, int_hexagon_M2_mpy_rnd_hl_s1>;
 187 def : T_RR_pat <M2_mpy_rnd_hl_s0, int_hexagon_M2_mpy_rnd_hl_s0>;
 188 def : T_RR_pat <M2_mpy_rnd_hh_s1, int_hexagon_M2_mpy_rnd_hh_s1>;
 189 def : T_RR_pat <M2_mpy_rnd_hh_s0, int_hexagon_M2_mpy_rnd_hh_s0>;
 190
 191 def : T_RR_pat <M2_mpy_sat_rnd_ll_s1, int_hexagon_M2_mpy_sat_rnd_ll_s1>;
 192 def : T_RR_pat <M2_mpy_sat_rnd_ll_s0, int_hexagon_M2_mpy_sat_rnd_ll_s0>;
 193 def : T_RR_pat <M2_mpy_sat_rnd_lh_s1, int_hexagon_M2_mpy_sat_rnd_lh_s1>;
 194 def : T_RR_pat <M2_mpy_sat_rnd_lh_s0, int_hexagon_M2_mpy_sat_rnd_lh_s0>;
 195 def : T_RR_pat <M2_mpy_sat_rnd_hl_s1, int_hexagon_M2_mpy_sat_rnd_hl_s1>;
 196 def : T_RR_pat <M2_mpy_sat_rnd_hl_s0, int_hexagon_M2_mpy_sat_rnd_hl_s0>;
 197 def : T_RR_pat <M2_mpy_sat_rnd_hh_s1, int_hexagon_M2_mpy_sat_rnd_hh_s1>;
 198 def : T_RR_pat <M2_mpy_sat_rnd_hh_s0, int_hexagon_M2_mpy_sat_rnd_hh_s0>;
 199
 200
 201 //===----------------------------------------------------------------------===//
 202 // MPYS / Multipy signed/unsigned halfwords and add/subtract the
 203 // result from the accumulator.
 204 //Rx [-+]= mpy[u](Rs.[H|L],Rt.[H|L])[:<<1][:sat]
 205 //===----------------------------------------------------------------------===//
 206
 207 def : T_RRR_pat <M2_mpy_acc_ll_s1, int_hexagon_M2_mpy_acc_ll_s1>;
 208 def : T_RRR_pat <M2_mpy_acc_ll_s0, int_hexagon_M2_mpy_acc_ll_s0>;
 209 def : T_RRR_pat <M2_mpy_acc_lh_s1, int_hexagon_M2_mpy_acc_lh_s1>;
 210 def : T_RRR_pat <M2_mpy_acc_lh_s0, int_hexagon_M2_mpy_acc_lh_s0>;
 211 def : T_RRR_pat <M2_mpy_acc_hl_s1, int_hexagon_M2_mpy_acc_hl_s1>;
 212 def : T_RRR_pat <M2_mpy_acc_hl_s0, int_hexagon_M2_mpy_acc_hl_s0>;
 213 def : T_RRR_pat <M2_mpy_acc_hh_s1, int_hexagon_M2_mpy_acc_hh_s1>;
 214 def : T_RRR_pat <M2_mpy_acc_hh_s0, int_hexagon_M2_mpy_acc_hh_s0>;
 215
 216 def : T_RRR_pat <M2_mpyu_acc_ll_s1, int_hexagon_M2_mpyu_acc_ll_s1>;
 217 def : T_RRR_pat <M2_mpyu_acc_ll_s0, int_hexagon_M2_mpyu_acc_ll_s0>;
 218 def : T_RRR_pat <M2_mpyu_acc_lh_s1, int_hexagon_M2_mpyu_acc_lh_s1>;
 219 def : T_RRR_pat <M2_mpyu_acc_lh_s0, int_hexagon_M2_mpyu_acc_lh_s0>;
 220 def : T_RRR_pat <M2_mpyu_acc_hl_s1, int_hexagon_M2_mpyu_acc_hl_s1>;
 221 def : T_RRR_pat <M2_mpyu_acc_hl_s0, int_hexagon_M2_mpyu_acc_hl_s0>;
 222 def : T_RRR_pat <M2_mpyu_acc_hh_s1, int_hexagon_M2_mpyu_acc_hh_s1>;
 223 def : T_RRR_pat <M2_mpyu_acc_hh_s0, int_hexagon_M2_mpyu_acc_hh_s0>;
 224
 225 def : T_RRR_pat <M2_mpy_nac_ll_s1, int_hexagon_M2_mpy_nac_ll_s1>;
 226 def : T_RRR_pat <M2_mpy_nac_ll_s0, int_hexagon_M2_mpy_nac_ll_s0>;
 227 def : T_RRR_pat <M2_mpy_nac_lh_s1, int_hexagon_M2_mpy_nac_lh_s1>;
 228 def : T_RRR_pat <M2_mpy_nac_lh_s0, int_hexagon_M2_mpy_nac_lh_s0>;
 229 def : T_RRR_pat <M2_mpy_nac_hl_s1, int_hexagon_M2_mpy_nac_hl_s1>;
 230 def : T_RRR_pat <M2_mpy_nac_hl_s0, int_hexagon_M2_mpy_nac_hl_s0>;
 231 def : T_RRR_pat <M2_mpy_nac_hh_s1, int_hexagon_M2_mpy_nac_hh_s1>;
 232 def : T_RRR_pat <M2_mpy_nac_hh_s0, int_hexagon_M2_mpy_nac_hh_s0>;
 233
 234 def : T_RRR_pat <M2_mpyu_nac_ll_s1, int_hexagon_M2_mpyu_nac_ll_s1>;
 235 def : T_RRR_pat <M2_mpyu_nac_ll_s0, int_hexagon_M2_mpyu_nac_ll_s0>;
 236 def : T_RRR_pat <M2_mpyu_nac_lh_s1, int_hexagon_M2_mpyu_nac_lh_s1>;
 237 def : T_RRR_pat <M2_mpyu_nac_lh_s0, int_hexagon_M2_mpyu_nac_lh_s0>;
 238 def : T_RRR_pat <M2_mpyu_nac_hl_s1, int_hexagon_M2_mpyu_nac_hl_s1>;
 239 def : T_RRR_pat <M2_mpyu_nac_hl_s0, int_hexagon_M2_mpyu_nac_hl_s0>;
 240 def : T_RRR_pat <M2_mpyu_nac_hh_s1, int_hexagon_M2_mpyu_nac_hh_s1>;
 241 def : T_RRR_pat <M2_mpyu_nac_hh_s0, int_hexagon_M2_mpyu_nac_hh_s0>;
 242
 243 def : T_RRR_pat <M2_mpy_acc_sat_ll_s1, int_hexagon_M2_mpy_acc_sat_ll_s1>;
 244 def : T_RRR_pat <M2_mpy_acc_sat_ll_s0, int_hexagon_M2_mpy_acc_sat_ll_s0>;
 245 def : T_RRR_pat <M2_mpy_acc_sat_lh_s1, int_hexagon_M2_mpy_acc_sat_lh_s1>;
 246 def : T_RRR_pat <M2_mpy_acc_sat_lh_s0, int_hexagon_M2_mpy_acc_sat_lh_s0>;
 247 def : T_RRR_pat <M2_mpy_acc_sat_hl_s1, int_hexagon_M2_mpy_acc_sat_hl_s1>;
 248 def : T_RRR_pat <M2_mpy_acc_sat_hl_s0, int_hexagon_M2_mpy_acc_sat_hl_s0>;
 249 def : T_RRR_pat <M2_mpy_acc_sat_hh_s1, int_hexagon_M2_mpy_acc_sat_hh_s1>;
 250 def : T_RRR_pat <M2_mpy_acc_sat_hh_s0, int_hexagon_M2_mpy_acc_sat_hh_s0>;
 251
 252 def : T_RRR_pat <M2_mpy_nac_sat_ll_s1, int_hexagon_M2_mpy_nac_sat_ll_s1>;
 253 def : T_RRR_pat <M2_mpy_nac_sat_ll_s0, int_hexagon_M2_mpy_nac_sat_ll_s0>;
 254 def : T_RRR_pat <M2_mpy_nac_sat_lh_s1, int_hexagon_M2_mpy_nac_sat_lh_s1>;
 255 def : T_RRR_pat <M2_mpy_nac_sat_lh_s0, int_hexagon_M2_mpy_nac_sat_lh_s0>;
 256 def : T_RRR_pat <M2_mpy_nac_sat_hl_s1, int_hexagon_M2_mpy_nac_sat_hl_s1>;
 257 def : T_RRR_pat <M2_mpy_nac_sat_hl_s0, int_hexagon_M2_mpy_nac_sat_hl_s0>;
 258 def : T_RRR_pat <M2_mpy_nac_sat_hh_s1, int_hexagon_M2_mpy_nac_sat_hh_s1>;
 259 def : T_RRR_pat <M2_mpy_nac_sat_hh_s0, int_hexagon_M2_mpy_nac_sat_hh_s0>;
 260
 261
 262 //===----------------------------------------------------------------------===//
 263 // Multiply signed/unsigned halfwords with and without saturation and rounding
 264 // into a 64-bits destination register.
 265 //===----------------------------------------------------------------------===//
 266
 267 def : T_RR_pat <M2_mpyd_hh_s0, int_hexagon_M2_mpyd_hh_s0>;
 268 def : T_RR_pat <M2_mpyd_hl_s0, int_hexagon_M2_mpyd_hl_s0>;
 269 def : T_RR_pat <M2_mpyd_lh_s0, int_hexagon_M2_mpyd_lh_s0>;
 270 def : T_RR_pat <M2_mpyd_ll_s0, int_hexagon_M2_mpyd_ll_s0>;
 271 def : T_RR_pat <M2_mpyd_hh_s1, int_hexagon_M2_mpyd_hh_s1>;
 272 def : T_RR_pat <M2_mpyd_hl_s1, int_hexagon_M2_mpyd_hl_s1>;
 273 def : T_RR_pat <M2_mpyd_lh_s1, int_hexagon_M2_mpyd_lh_s1>;
 274 def : T_RR_pat <M2_mpyd_ll_s1, int_hexagon_M2_mpyd_ll_s1>;
 275
 276 def : T_RR_pat <M2_mpyd_rnd_hh_s0, int_hexagon_M2_mpyd_rnd_hh_s0>;
 277 def : T_RR_pat <M2_mpyd_rnd_hl_s0, int_hexagon_M2_mpyd_rnd_hl_s0>;
 278 def : T_RR_pat <M2_mpyd_rnd_lh_s0, int_hexagon_M2_mpyd_rnd_lh_s0>;
 279 def : T_RR_pat <M2_mpyd_rnd_ll_s0, int_hexagon_M2_mpyd_rnd_ll_s0>;
 280 def : T_RR_pat <M2_mpyd_rnd_hh_s1, int_hexagon_M2_mpyd_rnd_hh_s1>;
 281 def : T_RR_pat <M2_mpyd_rnd_hl_s1, int_hexagon_M2_mpyd_rnd_hl_s1>;
 282 def : T_RR_pat <M2_mpyd_rnd_lh_s1, int_hexagon_M2_mpyd_rnd_lh_s1>;
 283 def : T_RR_pat <M2_mpyd_rnd_ll_s1, int_hexagon_M2_mpyd_rnd_ll_s1>;
 284
 285 def : T_RR_pat <M2_mpyud_hh_s0, int_hexagon_M2_mpyud_hh_s0>;
 286 def : T_RR_pat <M2_mpyud_hl_s0, int_hexagon_M2_mpyud_hl_s0>;
 287 def : T_RR_pat <M2_mpyud_lh_s0, int_hexagon_M2_mpyud_lh_s0>;
 288 def : T_RR_pat <M2_mpyud_ll_s0, int_hexagon_M2_mpyud_ll_s0>;
 289 def : T_RR_pat <M2_mpyud_hh_s1, int_hexagon_M2_mpyud_hh_s1>;
 290 def : T_RR_pat <M2_mpyud_hl_s1, int_hexagon_M2_mpyud_hl_s1>;
 291 def : T_RR_pat <M2_mpyud_lh_s1, int_hexagon_M2_mpyud_lh_s1>;
 292 def : T_RR_pat <M2_mpyud_ll_s1, int_hexagon_M2_mpyud_ll_s1>;
 293
 294 //===----------------------------------------------------------------------===//
 295 // MPYS / Multipy signed/unsigned halfwords and add/subtract the
 296 // result from the 64-bit destination register.
 297 //Rxx [-+]= mpy[u](Rs.[H|L],Rt.[H|L])[:<<1][:sat]
 298 //===----------------------------------------------------------------------===//
 299
 300 def : T_PRR_pat <M2_mpyd_acc_hh_s0, int_hexagon_M2_mpyd_acc_hh_s0>;
 301 def : T_PRR_pat <M2_mpyd_acc_hl_s0, int_hexagon_M2_mpyd_acc_hl_s0>;
 302 def : T_PRR_pat <M2_mpyd_acc_lh_s0, int_hexagon_M2_mpyd_acc_lh_s0>;
 303 def : T_PRR_pat <M2_mpyd_acc_ll_s0, int_hexagon_M2_mpyd_acc_ll_s0>;
 304
 305 def : T_PRR_pat <M2_mpyd_acc_hh_s1, int_hexagon_M2_mpyd_acc_hh_s1>;
 306 def : T_PRR_pat <M2_mpyd_acc_hl_s1, int_hexagon_M2_mpyd_acc_hl_s1>;
 307 def : T_PRR_pat <M2_mpyd_acc_lh_s1, int_hexagon_M2_mpyd_acc_lh_s1>;
 308 def : T_PRR_pat <M2_mpyd_acc_ll_s1, int_hexagon_M2_mpyd_acc_ll_s1>;
 309
 310 def : T_PRR_pat <M2_mpyd_nac_hh_s0, int_hexagon_M2_mpyd_nac_hh_s0>;
 311 def : T_PRR_pat <M2_mpyd_nac_hl_s0, int_hexagon_M2_mpyd_nac_hl_s0>;
 312 def : T_PRR_pat <M2_mpyd_nac_lh_s0, int_hexagon_M2_mpyd_nac_lh_s0>;
 313 def : T_PRR_pat <M2_mpyd_nac_ll_s0, int_hexagon_M2_mpyd_nac_ll_s0>;
 314
 315 def : T_PRR_pat <M2_mpyd_nac_hh_s1, int_hexagon_M2_mpyd_nac_hh_s1>;
 316 def : T_PRR_pat <M2_mpyd_nac_hl_s1, int_hexagon_M2_mpyd_nac_hl_s1>;
 317 def : T_PRR_pat <M2_mpyd_nac_lh_s1, int_hexagon_M2_mpyd_nac_lh_s1>;
 318 def : T_PRR_pat <M2_mpyd_nac_ll_s1, int_hexagon_M2_mpyd_nac_ll_s1>;
 319
 320 def : T_PRR_pat <M2_mpyud_acc_hh_s0, int_hexagon_M2_mpyud_acc_hh_s0>;
 321 def : T_PRR_pat <M2_mpyud_acc_hl_s0, int_hexagon_M2_mpyud_acc_hl_s0>;
 322 def : T_PRR_pat <M2_mpyud_acc_lh_s0, int_hexagon_M2_mpyud_acc_lh_s0>;
 323 def : T_PRR_pat <M2_mpyud_acc_ll_s0, int_hexagon_M2_mpyud_acc_ll_s0>;
 324
 325 def : T_PRR_pat <M2_mpyud_acc_hh_s1, int_hexagon_M2_mpyud_acc_hh_s1>;
 326 def : T_PRR_pat <M2_mpyud_acc_hl_s1, int_hexagon_M2_mpyud_acc_hl_s1>;
 327 def : T_PRR_pat <M2_mpyud_acc_lh_s1, int_hexagon_M2_mpyud_acc_lh_s1>;
 328 def : T_PRR_pat <M2_mpyud_acc_ll_s1, int_hexagon_M2_mpyud_acc_ll_s1>;
 329
 330 def : T_PRR_pat <M2_mpyud_nac_hh_s0, int_hexagon_M2_mpyud_nac_hh_s0>;
 331 def : T_PRR_pat <M2_mpyud_nac_hl_s0, int_hexagon_M2_mpyud_nac_hl_s0>;
 332 def : T_PRR_pat <M2_mpyud_nac_lh_s0, int_hexagon_M2_mpyud_nac_lh_s0>;
 333 def : T_PRR_pat <M2_mpyud_nac_ll_s0, int_hexagon_M2_mpyud_nac_ll_s0>;
 334
 335 def : T_PRR_pat <M2_mpyud_nac_hh_s1, int_hexagon_M2_mpyud_nac_hh_s1>;
 336 def : T_PRR_pat <M2_mpyud_nac_hl_s1, int_hexagon_M2_mpyud_nac_hl_s1>;
 337 def : T_PRR_pat <M2_mpyud_nac_lh_s1, int_hexagon_M2_mpyud_nac_lh_s1>;
 338 def : T_PRR_pat <M2_mpyud_nac_ll_s1, int_hexagon_M2_mpyud_nac_ll_s1>;
 339
 340
 341 //===----------------------------------------------------------------------===//
 342 // Add/Subtract halfword
 343 // Rd=add(Rt.L,Rs.[HL])[:sat]
 344 // Rd=sub(Rt.L,Rs.[HL])[:sat]
 345 // Rd=add(Rt.[LH],Rs.[HL])[:sat][:<16]
 346 // Rd=sub(Rt.[LH],Rs.[HL])[:sat][:<16]
 347 //===----------------------------------------------------------------------===//
 348
 349 //Rd=add(Rt.L,Rs.[LH])
 350 def : T_RR_pat <A2_addh_l16_ll,     int_hexagon_A2_addh_l16_ll>;
 351 def : T_RR_pat <A2_addh_l16_hl,     int_hexagon_A2_addh_l16_hl>;
 352
 353 //Rd=add(Rt.L,Rs.[LH]):sat
 354 def : T_RR_pat <A2_addh_l16_sat_ll, int_hexagon_A2_addh_l16_sat_ll>;
 355 def : T_RR_pat <A2_addh_l16_sat_hl, int_hexagon_A2_addh_l16_sat_hl>;
 356
 357 //Rd=sub(Rt.L,Rs.[LH])
 358 def : T_RR_pat <A2_subh_l16_ll,     int_hexagon_A2_subh_l16_ll>;
 359 def : T_RR_pat <A2_subh_l16_hl,     int_hexagon_A2_subh_l16_hl>;
 360
 361 //Rd=sub(Rt.L,Rs.[LH]):sat
 362 def : T_RR_pat <A2_subh_l16_sat_ll, int_hexagon_A2_subh_l16_sat_ll>;
 363 def : T_RR_pat <A2_subh_l16_sat_hl, int_hexagon_A2_subh_l16_sat_hl>;
 364
 365 //Rd=add(Rt.[LH],Rs.[LH]):<<16
 366 def : T_RR_pat <A2_addh_h16_ll,     int_hexagon_A2_addh_h16_ll>;
 367 def : T_RR_pat <A2_addh_h16_lh,     int_hexagon_A2_addh_h16_lh>;
 368 def : T_RR_pat <A2_addh_h16_hl,     int_hexagon_A2_addh_h16_hl>;
 369 def : T_RR_pat <A2_addh_h16_hh,     int_hexagon_A2_addh_h16_hh>;
 370
 371 //Rd=sub(Rt.[LH],Rs.[LH]):<<16
 372 def : T_RR_pat <A2_subh_h16_ll,     int_hexagon_A2_subh_h16_ll>;
 373 def : T_RR_pat <A2_subh_h16_lh,     int_hexagon_A2_subh_h16_lh>;
 374 def : T_RR_pat <A2_subh_h16_hl,     int_hexagon_A2_subh_h16_hl>;
 375 def : T_RR_pat <A2_subh_h16_hh,     int_hexagon_A2_subh_h16_hh>;
 376
 377 //Rd=add(Rt.[LH],Rs.[LH]):sat:<<16
 378 def : T_RR_pat <A2_addh_h16_sat_ll, int_hexagon_A2_addh_h16_sat_ll>;
 379 def : T_RR_pat <A2_addh_h16_sat_lh, int_hexagon_A2_addh_h16_sat_lh>;
 380 def : T_RR_pat <A2_addh_h16_sat_hl, int_hexagon_A2_addh_h16_sat_hl>;
 381 def : T_RR_pat <A2_addh_h16_sat_hh, int_hexagon_A2_addh_h16_sat_hh>;
 382
 383 //Rd=sub(Rt.[LH],Rs.[LH]):sat:<<16
 384 def : T_RR_pat <A2_subh_h16_sat_ll, int_hexagon_A2_subh_h16_sat_ll>;
 385 def : T_RR_pat <A2_subh_h16_sat_lh, int_hexagon_A2_subh_h16_sat_lh>;
 386 def : T_RR_pat <A2_subh_h16_sat_hl, int_hexagon_A2_subh_h16_sat_hl>;
 387 def : T_RR_pat <A2_subh_h16_sat_hh, int_hexagon_A2_subh_h16_sat_hh>;
 388
 389 // ALU64 / ALU / min max
 390 def : T_RR_pat<A2_max,  int_hexagon_A2_max>;
 391 def : T_RR_pat<A2_min,  int_hexagon_A2_min>;
 392 def : T_RR_pat<A2_maxu, int_hexagon_A2_maxu>;
 393 def : T_RR_pat<A2_minu, int_hexagon_A2_minu>;
 394
 395 // Shift and accumulate
 396 def : T_RRI_pat <S2_asr_i_r_nac,  int_hexagon_S2_asr_i_r_nac>;
 397 def : T_RRI_pat <S2_lsr_i_r_nac,  int_hexagon_S2_lsr_i_r_nac>;
 398 def : T_RRI_pat <S2_asl_i_r_nac,  int_hexagon_S2_asl_i_r_nac>;
 399 def : T_RRI_pat <S2_asr_i_r_acc,  int_hexagon_S2_asr_i_r_acc>;
 400 def : T_RRI_pat <S2_lsr_i_r_acc,  int_hexagon_S2_lsr_i_r_acc>;
 401 def : T_RRI_pat <S2_asl_i_r_acc,  int_hexagon_S2_asl_i_r_acc>;
 402
 403 def : T_RRI_pat <S2_asr_i_r_and,  int_hexagon_S2_asr_i_r_and>;
 404 def : T_RRI_pat <S2_lsr_i_r_and,  int_hexagon_S2_lsr_i_r_and>;
 405 def : T_RRI_pat <S2_asl_i_r_and,  int_hexagon_S2_asl_i_r_and>;
 406 def : T_RRI_pat <S2_asr_i_r_or,   int_hexagon_S2_asr_i_r_or>;
 407 def : T_RRI_pat <S2_lsr_i_r_or,   int_hexagon_S2_lsr_i_r_or>;
 408 def : T_RRI_pat <S2_asl_i_r_or,   int_hexagon_S2_asl_i_r_or>;
 409 def : T_RRI_pat <S2_lsr_i_r_xacc, int_hexagon_S2_lsr_i_r_xacc>;
 410 def : T_RRI_pat <S2_asl_i_r_xacc, int_hexagon_S2_asl_i_r_xacc>;
 411
 412 def : T_PPI_pat <S2_asr_i_p_nac,  int_hexagon_S2_asr_i_p_nac>;
 413 def : T_PPI_pat <S2_lsr_i_p_nac,  int_hexagon_S2_lsr_i_p_nac>;
 414 def : T_PPI_pat <S2_asl_i_p_nac,  int_hexagon_S2_asl_i_p_nac>;
 415 def : T_PPI_pat <S2_asr_i_p_acc,  int_hexagon_S2_asr_i_p_acc>;
 416 def : T_PPI_pat <S2_lsr_i_p_acc,  int_hexagon_S2_lsr_i_p_acc>;
 417 def : T_PPI_pat <S2_asl_i_p_acc,  int_hexagon_S2_asl_i_p_acc>;
 418
 419 def : T_PPI_pat <S2_asr_i_p_and,  int_hexagon_S2_asr_i_p_and>;
 420 def : T_PPI_pat <S2_lsr_i_p_and,  int_hexagon_S2_lsr_i_p_and>;
 421 def : T_PPI_pat <S2_asl_i_p_and,  int_hexagon_S2_asl_i_p_and>;
 422 def : T_PPI_pat <S2_asr_i_p_or,   int_hexagon_S2_asr_i_p_or>;
 423 def : T_PPI_pat <S2_lsr_i_p_or,   int_hexagon_S2_lsr_i_p_or>;
 424 def : T_PPI_pat <S2_asl_i_p_or,   int_hexagon_S2_asl_i_p_or>;
 425 def : T_PPI_pat <S2_lsr_i_p_xacc, int_hexagon_S2_lsr_i_p_xacc>;
 426 def : T_PPI_pat <S2_asl_i_p_xacc, int_hexagon_S2_asl_i_p_xacc>;
 427
 428 def : T_RRR_pat <S2_asr_r_r_nac,  int_hexagon_S2_asr_r_r_nac>;
 429 def : T_RRR_pat <S2_lsr_r_r_nac,  int_hexagon_S2_lsr_r_r_nac>;
 430 def : T_RRR_pat <S2_asl_r_r_nac,  int_hexagon_S2_asl_r_r_nac>;
 431 def : T_RRR_pat <S2_lsl_r_r_nac,  int_hexagon_S2_lsl_r_r_nac>;
 432 def : T_RRR_pat <S2_asr_r_r_acc,  int_hexagon_S2_asr_r_r_acc>;
 433 def : T_RRR_pat <S2_lsr_r_r_acc,  int_hexagon_S2_lsr_r_r_acc>;
 434 def : T_RRR_pat <S2_asl_r_r_acc,  int_hexagon_S2_asl_r_r_acc>;
 435 def : T_RRR_pat <S2_lsl_r_r_acc,  int_hexagon_S2_lsl_r_r_acc>;
 436
 437 def : T_RRR_pat <S2_asr_r_r_and,  int_hexagon_S2_asr_r_r_and>;
 438 def : T_RRR_pat <S2_lsr_r_r_and,  int_hexagon_S2_lsr_r_r_and>;
 439 def : T_RRR_pat <S2_asl_r_r_and,  int_hexagon_S2_asl_r_r_and>;
 440 def : T_RRR_pat <S2_lsl_r_r_and,  int_hexagon_S2_lsl_r_r_and>;
 441 def : T_RRR_pat <S2_asr_r_r_or,   int_hexagon_S2_asr_r_r_or>;
 442 def : T_RRR_pat <S2_lsr_r_r_or,   int_hexagon_S2_lsr_r_r_or>;
 443 def : T_RRR_pat <S2_asl_r_r_or,   int_hexagon_S2_asl_r_r_or>;
 444 def : T_RRR_pat <S2_lsl_r_r_or,   int_hexagon_S2_lsl_r_r_or>;
 445
 446 def : T_PPR_pat <S2_asr_r_p_nac,  int_hexagon_S2_asr_r_p_nac>;
 447 def : T_PPR_pat <S2_lsr_r_p_nac,  int_hexagon_S2_lsr_r_p_nac>;
 448 def : T_PPR_pat <S2_asl_r_p_nac,  int_hexagon_S2_asl_r_p_nac>;
 449 def : T_PPR_pat <S2_lsl_r_p_nac,  int_hexagon_S2_lsl_r_p_nac>;
 450 def : T_PPR_pat <S2_asr_r_p_acc,  int_hexagon_S2_asr_r_p_acc>;
 451 def : T_PPR_pat <S2_lsr_r_p_acc,  int_hexagon_S2_lsr_r_p_acc>;
 452 def : T_PPR_pat <S2_asl_r_p_acc,  int_hexagon_S2_asl_r_p_acc>;
 453 def : T_PPR_pat <S2_lsl_r_p_acc,  int_hexagon_S2_lsl_r_p_acc>;
 454
 455 def : T_PPR_pat <S2_asr_r_p_and,  int_hexagon_S2_asr_r_p_and>;
 456 def : T_PPR_pat <S2_lsr_r_p_and,  int_hexagon_S2_lsr_r_p_and>;
 457 def : T_PPR_pat <S2_asl_r_p_and,  int_hexagon_S2_asl_r_p_and>;
 458 def : T_PPR_pat <S2_lsl_r_p_and,  int_hexagon_S2_lsl_r_p_and>;
 459 def : T_PPR_pat <S2_asr_r_p_or,   int_hexagon_S2_asr_r_p_or>;
 460 def : T_PPR_pat <S2_lsr_r_p_or,   int_hexagon_S2_lsr_r_p_or>;
 461 def : T_PPR_pat <S2_asl_r_p_or,   int_hexagon_S2_asl_r_p_or>;
 462 def : T_PPR_pat <S2_lsl_r_p_or,   int_hexagon_S2_lsl_r_p_or>;
 463
 464 def : T_RRI_pat <S2_asr_i_r_nac,  int_hexagon_S2_asr_i_r_nac>;
 465 def : T_RRI_pat <S2_lsr_i_r_nac,  int_hexagon_S2_lsr_i_r_nac>;
 466 def : T_RRI_pat <S2_asl_i_r_nac,  int_hexagon_S2_asl_i_r_nac>;
 467 def : T_RRI_pat <S2_asr_i_r_acc,  int_hexagon_S2_asr_i_r_acc>;
 468 def : T_RRI_pat <S2_lsr_i_r_acc,  int_hexagon_S2_lsr_i_r_acc>;
 469 def : T_RRI_pat <S2_asl_i_r_acc,  int_hexagon_S2_asl_i_r_acc>;
 470
 471 def : T_RRI_pat <S2_asr_i_r_and,  int_hexagon_S2_asr_i_r_and>;
 472 def : T_RRI_pat <S2_lsr_i_r_and,  int_hexagon_S2_lsr_i_r_and>;
 473 def : T_RRI_pat <S2_asl_i_r_and,  int_hexagon_S2_asl_i_r_and>;
 474 def : T_RRI_pat <S2_asr_i_r_or,   int_hexagon_S2_asr_i_r_or>;
 475 def : T_RRI_pat <S2_lsr_i_r_or,   int_hexagon_S2_lsr_i_r_or>;
 476 def : T_RRI_pat <S2_asl_i_r_or,   int_hexagon_S2_asl_i_r_or>;
 477 def : T_RRI_pat <S2_lsr_i_r_xacc, int_hexagon_S2_lsr_i_r_xacc>;
 478 def : T_RRI_pat <S2_asl_i_r_xacc, int_hexagon_S2_asl_i_r_xacc>;
 479
 480 def : T_PPI_pat <S2_asr_i_p_nac,  int_hexagon_S2_asr_i_p_nac>;
 481 def : T_PPI_pat <S2_lsr_i_p_nac,  int_hexagon_S2_lsr_i_p_nac>;
 482 def : T_PPI_pat <S2_asl_i_p_nac,  int_hexagon_S2_asl_i_p_nac>;
 483 def : T_PPI_pat <S2_asr_i_p_acc,  int_hexagon_S2_asr_i_p_acc>;
 484 def : T_PPI_pat <S2_lsr_i_p_acc,  int_hexagon_S2_lsr_i_p_acc>;
 485 def : T_PPI_pat <S2_asl_i_p_acc,  int_hexagon_S2_asl_i_p_acc>;
 486
 487 def : T_PPI_pat <S2_asr_i_p_and,  int_hexagon_S2_asr_i_p_and>;
 488 def : T_PPI_pat <S2_lsr_i_p_and,  int_hexagon_S2_lsr_i_p_and>;
 489 def : T_PPI_pat <S2_asl_i_p_and,  int_hexagon_S2_asl_i_p_and>;
 490 def : T_PPI_pat <S2_asr_i_p_or,   int_hexagon_S2_asr_i_p_or>;
 491 def : T_PPI_pat <S2_lsr_i_p_or,   int_hexagon_S2_lsr_i_p_or>;
 492 def : T_PPI_pat <S2_asl_i_p_or,   int_hexagon_S2_asl_i_p_or>;
 493 def : T_PPI_pat <S2_lsr_i_p_xacc, int_hexagon_S2_lsr_i_p_xacc>;
 494 def : T_PPI_pat <S2_asl_i_p_xacc, int_hexagon_S2_asl_i_p_xacc>;
 495
 496 def : T_RRR_pat <S2_asr_r_r_nac,  int_hexagon_S2_asr_r_r_nac>;
 497 def : T_RRR_pat <S2_lsr_r_r_nac,  int_hexagon_S2_lsr_r_r_nac>;
 498 def : T_RRR_pat <S2_asl_r_r_nac,  int_hexagon_S2_asl_r_r_nac>;
 499 def : T_RRR_pat <S2_lsl_r_r_nac,  int_hexagon_S2_lsl_r_r_nac>;
 500 def : T_RRR_pat <S2_asr_r_r_acc,  int_hexagon_S2_asr_r_r_acc>;
 501 def : T_RRR_pat <S2_lsr_r_r_acc,  int_hexagon_S2_lsr_r_r_acc>;
 502 def : T_RRR_pat <S2_asl_r_r_acc,  int_hexagon_S2_asl_r_r_acc>;
 503 def : T_RRR_pat <S2_lsl_r_r_acc,  int_hexagon_S2_lsl_r_r_acc>;
 504
 505 def : T_RRR_pat <S2_asr_r_r_and,  int_hexagon_S2_asr_r_r_and>;
 506 def : T_RRR_pat <S2_lsr_r_r_and,  int_hexagon_S2_lsr_r_r_and>;
 507 def : T_RRR_pat <S2_asl_r_r_and,  int_hexagon_S2_asl_r_r_and>;
 508 def : T_RRR_pat <S2_lsl_r_r_and,  int_hexagon_S2_lsl_r_r_and>;
 509 def : T_RRR_pat <S2_asr_r_r_or,   int_hexagon_S2_asr_r_r_or>;
 510 def : T_RRR_pat <S2_lsr_r_r_or,   int_hexagon_S2_lsr_r_r_or>;
 511 def : T_RRR_pat <S2_asl_r_r_or,   int_hexagon_S2_asl_r_r_or>;
 512 def : T_RRR_pat <S2_lsl_r_r_or,   int_hexagon_S2_lsl_r_r_or>;
 513
 514 def : T_PPR_pat <S2_asr_r_p_nac,  int_hexagon_S2_asr_r_p_nac>;
 515 def : T_PPR_pat <S2_lsr_r_p_nac,  int_hexagon_S2_lsr_r_p_nac>;
 516 def : T_PPR_pat <S2_asl_r_p_nac,  int_hexagon_S2_asl_r_p_nac>;
 517 def : T_PPR_pat <S2_lsl_r_p_nac,  int_hexagon_S2_lsl_r_p_nac>;
 518 def : T_PPR_pat <S2_asr_r_p_acc,  int_hexagon_S2_asr_r_p_acc>;
 519 def : T_PPR_pat <S2_lsr_r_p_acc,  int_hexagon_S2_lsr_r_p_acc>;
 520 def : T_PPR_pat <S2_asl_r_p_acc,  int_hexagon_S2_asl_r_p_acc>;
 521 def : T_PPR_pat <S2_lsl_r_p_acc,  int_hexagon_S2_lsl_r_p_acc>;
 522
 523 def : T_PPR_pat <S2_asr_r_p_and,  int_hexagon_S2_asr_r_p_and>;
 524 def : T_PPR_pat <S2_lsr_r_p_and,  int_hexagon_S2_lsr_r_p_and>;
 525 def : T_PPR_pat <S2_asl_r_p_and,  int_hexagon_S2_asl_r_p_and>;
 526 def : T_PPR_pat <S2_lsl_r_p_and,  int_hexagon_S2_lsl_r_p_and>;
 527 def : T_PPR_pat <S2_asr_r_p_or,   int_hexagon_S2_asr_r_p_or>;
 528 def : T_PPR_pat <S2_lsr_r_p_or,   int_hexagon_S2_lsr_r_p_or>;
 529 def : T_PPR_pat <S2_asl_r_p_or,   int_hexagon_S2_asl_r_p_or>;
 530 def : T_PPR_pat <S2_lsl_r_p_or,   int_hexagon_S2_lsl_r_p_or>;
 531
 532 /********************************************************************
 533 *            ALU32/ALU                                              *
 534 *********************************************************************/
 535 def : T_RR_pat<A2_add,      int_hexagon_A2_add>;
 536 def : T_RI_pat<ADD_ri,      int_hexagon_A2_addi>;
 537 def : T_RR_pat<A2_sub,      int_hexagon_A2_sub>;
 538 def : T_IR_pat<SUB_ri,      int_hexagon_A2_subri>;
 539 def : T_RR_pat<A2_and,      int_hexagon_A2_and>;
 540 def : T_RI_pat<AND_ri,      int_hexagon_A2_andir>;
 541 def : T_RR_pat<A2_or,       int_hexagon_A2_or>;
 542 def : T_RI_pat<OR_ri,       int_hexagon_A2_orir>;
 543 def : T_RR_pat<A2_xor,      int_hexagon_A2_xor>;
 544 def : T_RR_pat<A2_combinew, int_hexagon_A2_combinew>;
 545
 546 // Assembler mapped from Rd32=not(Rs32) to Rd32=sub(#-1,Rs32)
 547 def : Pat <(int_hexagon_A2_not (I32:$Rs)),
 548            (SUB_ri -1, IntRegs:$Rs)>;
 549
 550 // Assembler mapped from Rd32=neg(Rs32) to Rd32=sub(#0,Rs32)
 551 def : Pat <(int_hexagon_A2_neg IntRegs:$Rs),
 552            (SUB_ri 0, IntRegs:$Rs)>;
 553
 554 // Transfer immediate
 555 def  : Pat <(int_hexagon_A2_tfril (I32:$Rs), u16_0ImmPred:$Is),
 556             (A2_tfril IntRegs:$Rs, u16_0ImmPred:$Is)>;
 557 def  : Pat <(int_hexagon_A2_tfrih (I32:$Rs), u16_0ImmPred:$Is),
 558             (A2_tfrih IntRegs:$Rs, u16_0ImmPred:$Is)>;
 559
 560 //  Transfer Register/immediate.
 561 def : T_R_pat <A2_tfr, int_hexagon_A2_tfr>;
 562 def : T_I_pat <A2_tfrsi, int_hexagon_A2_tfrsi>;
 563
 564 // Assembler mapped from Rdd32=Rss32 to Rdd32=combine(Rss.H32,Rss.L32)
 565 def : Pat<(int_hexagon_A2_tfrp DoubleRegs:$src),
 566           (A2_combinew (HiReg DoubleRegs:$src), (LoReg DoubleRegs:$src))>;
 567
 568 /********************************************************************
 569 *            ALU32/PERM                                             *
 570 *********************************************************************/
 571 // Combine
 572 def: T_RR_pat<A2_combine_hh, int_hexagon_A2_combine_hh>;
 573 def: T_RR_pat<A2_combine_hl, int_hexagon_A2_combine_hl>;
 574 def: T_RR_pat<A2_combine_lh, int_hexagon_A2_combine_lh>;
 575 def: T_RR_pat<A2_combine_ll, int_hexagon_A2_combine_ll>;
 576
 577 def: T_II_pat<A2_combineii, int_hexagon_A2_combineii, s8ExtPred, s8ImmPred>;
 578
 579 def: Pat<(i32 (int_hexagon_C2_mux (I32:$Rp), (I32:$Rs),
 580                                                      (I32:$Rt))),
 581          (i32 (C2_mux (C2_tfrrp IntRegs:$Rp), IntRegs:$Rs, IntRegs:$Rt))>;
 582
 583 // Mux
 584 def : T_QRI_pat<C2_muxir, int_hexagon_C2_muxir, s8ExtPred>;
 585 def : T_QIR_pat<C2_muxri, int_hexagon_C2_muxri, s8ExtPred>;
 586 def : T_QII_pat<C2_muxii, int_hexagon_C2_muxii, s8ExtPred, s8ImmPred>;
 587
 588 // Shift halfword
 589 def : T_R_pat<A2_aslh, int_hexagon_A2_aslh>;
 590 def : T_R_pat<A2_asrh, int_hexagon_A2_asrh>;
 591 def : T_R_pat<A2_asrh, int_hexagon_SI_to_SXTHI_asrh>;
 592
 593 // Sign/zero extend
 594 def : T_R_pat<A2_sxth, int_hexagon_A2_sxth>;
 595 def : T_R_pat<A2_sxtb, int_hexagon_A2_sxtb>;
 596 def : T_R_pat<A2_zxth, int_hexagon_A2_zxth>;
 597 def : T_R_pat<A2_zxtb, int_hexagon_A2_zxtb>;
 598
 599 /********************************************************************
 600 *            ALU64/ALU                                              *
 601 *********************************************************************/
 602 def: T_RR_pat<A2_addsat,   int_hexagon_A2_addsat>;
 603 def: T_RR_pat<A2_subsat,   int_hexagon_A2_subsat>;
 604 def: T_PP_pat<A2_addp,     int_hexagon_A2_addp>;
 605 def: T_PP_pat<A2_subp,     int_hexagon_A2_subp>;
 606
 607 def: T_PP_pat<A2_andp,     int_hexagon_A2_andp>;
 608 def: T_PP_pat<A2_orp,      int_hexagon_A2_orp>;
 609 def: T_PP_pat<A2_xorp,     int_hexagon_A2_xorp>;
 610
 611 def: T_PP_pat<S2_parityp,  int_hexagon_S2_parityp>;
 612 def: T_RR_pat<S2_packhl,   int_hexagon_S2_packhl>;
 613
 614 // MPY - Multiply and use full result
 615 // Rdd = mpy[u](Rs, Rt)
 616 def : T_RR_pat <M2_dpmpyss_s0, int_hexagon_M2_dpmpyss_s0>;
 617 def : T_RR_pat <M2_dpmpyuu_s0, int_hexagon_M2_dpmpyuu_s0>;
 618
 619 // Rxx[+-]= mpy[u](Rs,Rt)
 620 def : T_PRR_pat <M2_dpmpyss_acc_s0, int_hexagon_M2_dpmpyss_acc_s0>;
 621 def : T_PRR_pat <M2_dpmpyss_nac_s0, int_hexagon_M2_dpmpyss_nac_s0>;
 622 def : T_PRR_pat <M2_dpmpyuu_acc_s0, int_hexagon_M2_dpmpyuu_acc_s0>;
 623 def : T_PRR_pat <M2_dpmpyuu_nac_s0, int_hexagon_M2_dpmpyuu_nac_s0>;
 624
 625 // Multiply 32x32 and use lower result
 626 def : T_RRI_pat <M2_macsip, int_hexagon_M2_macsip>;
 627 def : T_RRI_pat <M2_macsin, int_hexagon_M2_macsin>;
 628 def : T_RRR_pat <M2_maci, int_hexagon_M2_maci>;
 629
 630 // Subtract and accumulate
 631 def : T_RRR_pat <M2_subacc, int_hexagon_M2_subacc>;
 632
 633 // Add and accumulate
 634 def : T_RRR_pat <M2_acci,   int_hexagon_M2_acci>;
 635 def : T_RRR_pat <M2_nacci,  int_hexagon_M2_nacci>;
 636 def : T_RRI_pat <M2_accii,  int_hexagon_M2_accii>;
 637 def : T_RRI_pat <M2_naccii, int_hexagon_M2_naccii>;
 638
 639 // XOR and XOR with destination
 640 def : T_RRR_pat <M2_xor_xacc, int_hexagon_M2_xor_xacc>;
 641
 642 class MType_R32_pat <Intrinsic IntID, InstHexagon OutputInst> :
 643       Pat <(IntID IntRegs:$src1, IntRegs:$src2),
 644            (OutputInst IntRegs:$src1, IntRegs:$src2)>;
 645
 646 // Multiply and use lower result
 647 def : MType_R32_pat <int_hexagon_M2_mpyi, M2_mpyi>;
 648 def : T_RI_pat<M2_mpysmi, int_hexagon_M2_mpysmi>;
 649
 650 // Assembler mapped from Rd32=mpyui(Rs32,Rt32) to Rd32=mpyi(Rs32,Rt32)
 651 def : MType_R32_pat <int_hexagon_M2_mpyui, M2_mpyi>;
 652
 653 // Multiply and use upper result
 654 def : MType_R32_pat <int_hexagon_M2_mpy_up, M2_mpy_up>;
 655 def : MType_R32_pat <int_hexagon_M2_mpyu_up, M2_mpyu_up>;
 656 def : MType_R32_pat <int_hexagon_M2_hmmpyh_rs1, M2_hmmpyh_rs1>;
 657 def : MType_R32_pat <int_hexagon_M2_hmmpyl_rs1, M2_hmmpyl_rs1>;
 658 def : MType_R32_pat <int_hexagon_M2_dpmpyss_rnd_s0, M2_dpmpyss_rnd_s0>;
 659
 660 /********************************************************************
 661 *            STYPE/ALU                                              *
 662 *********************************************************************/
 663 def : T_P_pat <A2_absp, int_hexagon_A2_absp>;
 664 def : T_P_pat <A2_negp, int_hexagon_A2_negp>;
 665 def : T_P_pat <A2_notp, int_hexagon_A2_notp>;
 666
 667 /********************************************************************
 668 *            STYPE/BIT                                              *
 669 *********************************************************************/
 670
 671 // Count leading/trailing
 672 def: T_R_pat<S2_cl0,     int_hexagon_S2_cl0>;
 673 def: T_P_pat<S2_cl0p,    int_hexagon_S2_cl0p>;
 674 def: T_R_pat<S2_cl1,     int_hexagon_S2_cl1>;
 675 def: T_P_pat<S2_cl1p,    int_hexagon_S2_cl1p>;
 676 def: T_R_pat<S2_clb,     int_hexagon_S2_clb>;
 677 def: T_P_pat<S2_clbp,    int_hexagon_S2_clbp>;
 678 def: T_R_pat<S2_clbnorm, int_hexagon_S2_clbnorm>;
 679 def: T_R_pat<S2_ct0,     int_hexagon_S2_ct0>;
 680 def: T_R_pat<S2_ct1,     int_hexagon_S2_ct1>;
 681
 682 // Compare bit mask
 683 def: T_RR_pat<C2_bitsclr,  int_hexagon_C2_bitsclr>;
 684 def: T_RI_pat<C2_bitsclri, int_hexagon_C2_bitsclri>;
 685 def: T_RR_pat<C2_bitsset,  int_hexagon_C2_bitsset>;
 686
 687 // Linear feedback-shift Iteration.
 688 def : T_PP_pat <S2_lfsp, int_hexagon_S2_lfsp>;
 689
 690 // Shift by immediate and add
 691 def : T_RRI_pat<S2_addasl_rrri, int_hexagon_S2_addasl_rrri>;
 692
 693 // Extract bitfield
 694 def : T_PII_pat<S2_extractup,    int_hexagon_S2_extractup>;
 695 def : T_RII_pat<S2_extractu,     int_hexagon_S2_extractu>;
 696 def : T_RP_pat <S2_extractu_rp,  int_hexagon_S2_extractu_rp>;
 697 def : T_PP_pat <S2_extractup_rp, int_hexagon_S2_extractup_rp>;
 698
 699 // Insert bitfield
 700 def : Pat <(int_hexagon_S2_insert_rp IntRegs:$src1, IntRegs:$src2,
 701                                      DoubleRegs:$src3),
 702            (S2_insert_rp IntRegs:$src1, IntRegs:$src2, DoubleRegs:$src3)>;
 703
 704 def : Pat<(i64 (int_hexagon_S2_insertp_rp (I64:$src1),
 705                  (I64:$src2), (I64:$src3))),
 706           (i64 (S2_insertp_rp (I64:$src1), (I64:$src2),
 707                               (I64:$src3)))>;
 708
 709 def : Pat<(int_hexagon_S2_insert IntRegs:$src1, IntRegs:$src2,
 710                                  u5ImmPred:$src3, u5ImmPred:$src4),
 711           (S2_insert IntRegs:$src1, IntRegs:$src2,
 712                      u5ImmPred:$src3, u5ImmPred:$src4)>;
 713
 714 def : Pat<(i64 (int_hexagon_S2_insertp (I64:$src1),
 715                  (I64:$src2), u6ImmPred:$src3, u6ImmPred:$src4)),
 716           (i64 (S2_insertp (I64:$src1), (I64:$src2),
 717                            u6ImmPred:$src3, u6ImmPred:$src4))>;
 718
 719
 720 // Innterleave/deinterleave
 721 def : T_P_pat <S2_interleave, int_hexagon_S2_interleave>;
 722 def : T_P_pat <S2_deinterleave, int_hexagon_S2_deinterleave>;
 723
 724 // Set/Clear/Toggle Bit
 725 def: T_RI_pat<S2_setbit_i,    int_hexagon_S2_setbit_i>;
 726 def: T_RI_pat<S2_clrbit_i,    int_hexagon_S2_clrbit_i>;
 727 def: T_RI_pat<S2_togglebit_i, int_hexagon_S2_togglebit_i>;
 728
 729 def: T_RR_pat<S2_setbit_r,    int_hexagon_S2_setbit_r>;
 730 def: T_RR_pat<S2_clrbit_r,    int_hexagon_S2_clrbit_r>;
 731 def: T_RR_pat<S2_togglebit_r, int_hexagon_S2_togglebit_r>;
 732
 733 // Test Bit
 734 def: T_RI_pat<S2_tstbit_i,    int_hexagon_S2_tstbit_i>;
 735 def: T_RR_pat<S2_tstbit_r,    int_hexagon_S2_tstbit_r>;
 736
 737 /********************************************************************
 738 *            STYPE/SHIFT                                            *
 739 *********************************************************************/
 740
 741 def : T_PI_pat <S2_asr_i_p, int_hexagon_S2_asr_i_p>;
 742 def : T_PI_pat <S2_lsr_i_p, int_hexagon_S2_lsr_i_p>;
 743 def : T_PI_pat <S2_asl_i_p, int_hexagon_S2_asl_i_p>;
 744
 745 def : T_PR_pat <S2_asr_r_p, int_hexagon_S2_asr_r_p>;
 746 def : T_PR_pat <S2_lsr_r_p, int_hexagon_S2_lsr_r_p>;
 747 def : T_PR_pat <S2_asl_r_p, int_hexagon_S2_asl_r_p>;
 748 def : T_PR_pat <S2_lsl_r_p, int_hexagon_S2_lsl_r_p>;
 749
 750 def : T_RR_pat <S2_asr_r_r, int_hexagon_S2_asr_r_r>;
 751 def : T_RR_pat <S2_lsr_r_r, int_hexagon_S2_lsr_r_r>;
 752 def : T_RR_pat <S2_asl_r_r, int_hexagon_S2_asl_r_r>;
 753 def : T_RR_pat <S2_lsl_r_r, int_hexagon_S2_lsl_r_r>;
 754
 755 def : T_RR_pat <S2_asr_r_r_sat, int_hexagon_S2_asr_r_r_sat>;
 756 def : T_RR_pat <S2_asl_r_r_sat, int_hexagon_S2_asl_r_r_sat>;
 757
 758 def : T_R_pat <A2_sxtw,     int_hexagon_A2_sxtw>;
 759
 760 def : T_R_pat <S2_brev,        int_hexagon_S2_brev>;
 761
 762 def : T_R_pat <A2_abs,    int_hexagon_A2_abs>;
 763 def : T_R_pat <A2_abssat, int_hexagon_A2_abssat>;
 764 def : T_R_pat <A2_negsat, int_hexagon_A2_negsat>;
 765
 766 def : T_R_pat <A2_swiz,   int_hexagon_A2_swiz>;
 767
 768 def : T_P_pat <A2_sat,    int_hexagon_A2_sat>;
 769 def : T_R_pat <A2_sath,   int_hexagon_A2_sath>;
 770 def : T_R_pat <A2_satuh,  int_hexagon_A2_satuh>;
 771 def : T_R_pat <A2_satub,  int_hexagon_A2_satub>;
 772 def : T_R_pat <A2_satb,   int_hexagon_A2_satb>;
 773
 774 def : T_RI_pat <S2_asr_i_r,     int_hexagon_S2_asr_i_r>;
 775 def : T_RI_pat <S2_lsr_i_r,     int_hexagon_S2_lsr_i_r>;
 776 def : T_RI_pat <S2_asl_i_r,     int_hexagon_S2_asl_i_r>;
 777 def : T_RI_pat <S2_asr_i_r_rnd, int_hexagon_S2_asr_i_r_rnd>;
 778 def : T_RI_pat <S2_asr_i_r_rnd_goodsyntax,
 779                 int_hexagon_S2_asr_i_r_rnd_goodsyntax>;
 780
 781 // Shift left by immediate with saturation.
 782 def : T_RI_pat <S2_asl_i_r_sat, int_hexagon_S2_asl_i_r_sat>;
 783
 784 //===----------------------------------------------------------------------===//
 785 // Template 'def pat' to map tableidx[bhwd] intrinsics to :raw instructions.
 786 //===----------------------------------------------------------------------===//
 787 class S2op_tableidx_pat <Intrinsic IntID, InstHexagon OutputInst,
 788                          SDNodeXForm XformImm>
 789   : Pat <(IntID IntRegs:$src1, IntRegs:$src2, u4ImmPred:$src3, u5ImmPred:$src4),
 790          (OutputInst IntRegs:$src1, IntRegs:$src2, u4ImmPred:$src3,
 791                      (XformImm u5ImmPred:$src4))>;
 792
 793
 794 // Table Index : Extract and insert bits.
 795 // Map to the real hardware instructions after subtracting appropriate
 796 // values from the 4th input operand. Please note that subtraction is not
 797 // needed for int_hexagon_S2_tableidxb_goodsyntax.
 798
 799 def : Pat <(int_hexagon_S2_tableidxb_goodsyntax IntRegs:$src1, IntRegs:$src2,
 800                                               u4ImmPred:$src3, u5ImmPred:$src4),
 801            (S2_tableidxb IntRegs:$src1, IntRegs:$src2,
 802                          u4ImmPred:$src3, u5ImmPred:$src4)>;
 803
 804 def : S2op_tableidx_pat <int_hexagon_S2_tableidxh_goodsyntax, S2_tableidxh,
 805                          DEC_CONST_SIGNED>;
 806 def : S2op_tableidx_pat <int_hexagon_S2_tableidxw_goodsyntax, S2_tableidxw,
 807                          DEC2_CONST_SIGNED>;
 808 def : S2op_tableidx_pat <int_hexagon_S2_tableidxd_goodsyntax, S2_tableidxd,
 809                          DEC3_CONST_SIGNED>;
 810
 811 //
 812 // ALU 32 types.
 813 //
 814
 815 class qi_ALU32_sisi<string opc, Intrinsic IntID>
 816   : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 817              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
 818              [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 819
 820 class qi_ALU32_sis10<string opc, Intrinsic IntID>
 821   : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, s10Imm:$src2),
 822              !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
 823              [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
 824
 825 class qi_ALU32_sis8<string opc, Intrinsic IntID>
 826   : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, s8Imm:$src2),
 827              !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
 828              [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
 829
 830 class qi_ALU32_siu8<string opc, Intrinsic IntID>
 831   : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, u8Imm:$src2),
 832              !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
 833              [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
 834
 835 class qi_ALU32_siu9<string opc, Intrinsic IntID>
 836   : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, u9Imm:$src2),
 837              !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
 838              [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
 839
 840 class si_ALU32_qisisi<string opc, Intrinsic IntID>
 841   : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2,
 842                                       IntRegs:$src3),
 843              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2, $src3)")),
 844              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2,
 845                                         IntRegs:$src3))]>;
 846
 847 class si_ALU32_qis8si<string opc, Intrinsic IntID>
 848   : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, s8Imm:$src2,
 849                                        IntRegs:$src3),
 850              !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2, $src3)")),
 851              [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2,
 852                                         IntRegs:$src3))]>;
 853
 854 class si_ALU32_qisis8<string opc, Intrinsic IntID>
 855   : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2,
 856                                        s8Imm:$src3),
 857              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2, #$src3)")),
 858              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2,
 859                                         imm:$src3))]>;
 860
 861 class si_ALU32_qis8s8<string opc, Intrinsic IntID>
 862   : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, s8Imm:$src2, s8Imm:$src3),
 863              !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2, #$src3)")),
 864              [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2, imm:$src3))]>;
 865
 866 class si_ALU32_sisi<string opc, Intrinsic IntID>
 867   : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 868              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
 869              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 870
 871 class si_ALU32_sisi_sat<string opc, Intrinsic IntID>
 872   : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 873              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):sat")),
 874              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 875
 876 class si_ALU32_sisi_rnd<string opc, Intrinsic IntID>
 877   : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 878              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):rnd")),
 879              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 880
 881 class si_ALU32_sis16<string opc, Intrinsic IntID>
 882   : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, s16Imm:$src2),
 883              !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
 884              [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
 885
 886 class si_ALU32_sis10<string opc, Intrinsic IntID>
 887   : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, s10Imm:$src2),
 888              !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
 889              [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
 890
 891 class si_ALU32_s10si<string opc, Intrinsic IntID>
 892   : ALU32_rr<(outs IntRegs:$dst), (ins s10Imm:$src1, IntRegs:$src2),
 893              !strconcat("$dst = ", !strconcat(opc , "(#$src1, $src2)")),
 894              [(set IntRegs:$dst, (IntID imm:$src1, IntRegs:$src2))]>;
 895
 896 class si_lo_ALU32_siu16<string opc, Intrinsic IntID>
 897   : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u16Imm:$src2),
 898              !strconcat("$dst.l = ", !strconcat(opc , "#$src2")),
 899              [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
 900
 901 class si_hi_ALU32_siu16<string opc, Intrinsic IntID>
 902   : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u16Imm:$src2),
 903              !strconcat("$dst.h = ", !strconcat(opc , "#$src2")),
 904              [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
 905
 906 class si_ALU32_s16<string opc, Intrinsic IntID>
 907   : ALU32_rr<(outs IntRegs:$dst), (ins s16Imm:$src1),
 908              !strconcat("$dst = ", !strconcat(opc , "#$src1")),
 909              [(set IntRegs:$dst, (IntID imm:$src1))]>;
 910
 911 class di_ALU32_s8<string opc, Intrinsic IntID>
 912   : ALU32_rr<(outs DoubleRegs:$dst), (ins s8Imm:$src1),
 913              !strconcat("$dst = ", !strconcat(opc , "#$src1")),
 914              [(set DoubleRegs:$dst, (IntID imm:$src1))]>;
 915
 916 class di_ALU64_di<string opc, Intrinsic IntID>
 917   : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src),
 918              !strconcat("$dst = ", !strconcat(opc , "$src")),
 919              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src))]>;
 920
 921 class si_ALU32_si<string opc, Intrinsic IntID>
 922   : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src),
 923              !strconcat("$dst = ", !strconcat(opc , "($src)")),
 924              [(set IntRegs:$dst, (IntID IntRegs:$src))]>;
 925
 926 class si_ALU32_si_tfr<string opc, Intrinsic IntID>
 927   : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src),
 928              !strconcat("$dst = ", !strconcat(opc , "$src")),
 929              [(set IntRegs:$dst, (IntID IntRegs:$src))]>;
 930
 931 //
 932 // ALU 64 types.
 933 //
 934
 935 class si_ALU64_si_sat<string opc, Intrinsic IntID>
 936   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src),
 937              !strconcat("$dst = ", !strconcat(opc , "($src):sat")),
 938              [(set IntRegs:$dst, (IntID IntRegs:$src))]>;
 939
 940 class si_ALU64_didi<string opc, Intrinsic IntID>
 941   : ALU64_rr<(outs IntRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
 942              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
 943              [(set IntRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
 944
 945 class di_ALU64_sidi<string opc, Intrinsic IntID>
 946   : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src1, DoubleRegs:$src2),
 947              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
 948              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, DoubleRegs:$src2))]>;
 949
 950 class di_ALU64_didi<string opc, Intrinsic IntID>
 951   : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
 952              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
 953              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
 954                                            DoubleRegs:$src2))]>;
 955
 956 class di_ALU64_qididi<string opc, Intrinsic IntID>
 957   : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src1, DoubleRegs:$src2,
 958                                           DoubleRegs:$src3),
 959              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2, $src3)")),
 960              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, DoubleRegs:$src2,
 961                                            DoubleRegs:$src3))]>;
 962
 963 class di_ALU64_sisi<string opc, Intrinsic IntID>
 964   : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 965              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
 966              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 967
 968 class di_ALU64_didi_sat<string opc, Intrinsic IntID>
 969   : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
 970              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):sat")),
 971              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
 972                                            DoubleRegs:$src2))]>;
 973
 974 class di_ALU64_didi_rnd<string opc, Intrinsic IntID>
 975   : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
 976              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):rnd")),
 977              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
 978                                            DoubleRegs:$src2))]>;
 979
 980 class di_ALU64_didi_crnd<string opc, Intrinsic IntID>
 981   : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
 982              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):crnd")),
 983              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
 984                                            DoubleRegs:$src2))]>;
 985
 986 class di_ALU64_didi_rnd_sat<string opc, Intrinsic IntID>
 987   : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
 988              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):rnd:sat")),
 989              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
 990                                            DoubleRegs:$src2))]>;
 991
 992 class di_ALU64_didi_crnd_sat<string opc, Intrinsic IntID>
 993   : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
 994              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):crnd:sat")),
 995              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
 996                                            DoubleRegs:$src2))]>;
 997
 998 class qi_ALU64_didi<string opc, Intrinsic IntID>
 999   : ALU64_rr<(outs PredRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1000              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
1001              [(set PredRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
1002
1003 class si_ALU64_sisi<string opc, Intrinsic IntID>
1004   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1005              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
1006              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1007
1008 class si_ALU64_sisi_sat_lh<string opc, Intrinsic IntID>
1009   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1010              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H):sat")),
1011              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1012
1013 class si_ALU64_sisi_l16_sat_hh<string opc, Intrinsic IntID>
1014   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1015              !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.H):sat")),
1016              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1017
1018 class si_ALU64_sisi_l16_sat_lh<string opc, Intrinsic IntID>
1019   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1020              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H):sat")),
1021              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1022
1023 class si_ALU64_sisi_l16_sat_hl<string opc, Intrinsic IntID>
1024   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1025              !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.L):sat")),
1026              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1027
1028 class si_ALU64_sisi_l16_sat_ll<string opc, Intrinsic IntID>
1029   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1030              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L):sat")),
1031              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1032
1033 class si_ALU64_sisi_l16_hh<string opc, Intrinsic IntID>
1034   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1035              !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.H)")),
1036              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1037
1038 class si_ALU64_sisi_l16_hl<string opc, Intrinsic IntID>
1039   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1040              !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.L)")),
1041              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1042
1043 class si_ALU64_sisi_l16_lh<string opc, Intrinsic IntID>
1044   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1045              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H)")),
1046              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1047
1048 class si_ALU64_sisi_l16_ll<string opc, Intrinsic IntID>
1049   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1050              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L)")),
1051              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1052
1053 class si_ALU64_sisi_h16_sat_hh<string opc, Intrinsic IntID>
1054   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1055              !strconcat("$dst = ", !strconcat(opc ,
1056                                               "($src1.H, $src2.H):sat:<<16")),
1057              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1058
1059 class si_ALU64_sisi_h16_sat_lh<string opc, Intrinsic IntID>
1060   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1061              !strconcat("$dst = ", !strconcat(opc ,
1062                                               "($src1.L, $src2.H):sat:<<16")),
1063              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1064
1065 class si_ALU64_sisi_h16_sat_hl<string opc, Intrinsic IntID>
1066   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1067              !strconcat("$dst = ", !strconcat(opc ,
1068                                               "($src1.H, $src2.L):sat:<<16")),
1069              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1070
1071 class si_ALU64_sisi_h16_sat_ll<string opc, Intrinsic IntID>
1072   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1073              !strconcat("$dst = ", !strconcat(opc ,
1074                                               "($src1.L, $src2.L):sat:<<16")),
1075              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1076
1077 class si_ALU64_sisi_h16_hh<string opc, Intrinsic IntID>
1078   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1079              !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.H):<<16")),
1080              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1081
1082 class si_ALU64_sisi_h16_hl<string opc, Intrinsic IntID>
1083   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1084              !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.L):<<16")),
1085              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1086
1087 class si_ALU64_sisi_h16_lh<string opc, Intrinsic IntID>
1088   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1089              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H):<<16")),
1090              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1091
1092 class si_ALU64_sisi_h16_ll<string opc, Intrinsic IntID>
1093   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1094              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L):<<16")),
1095              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1096
1097 class si_ALU64_sisi_lh<string opc, Intrinsic IntID>
1098   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1099              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H)")),
1100              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1101
1102 class si_ALU64_sisi_ll<string opc, Intrinsic IntID>
1103   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1104              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L)")),
1105              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1106
1107 class si_ALU64_sisi_sat<string opc, Intrinsic IntID>
1108   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1109              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):sat")),
1110              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1111
1112 //
1113 // SInst classes.
1114 //
1115
1116 class qi_SInst_qi<string opc, Intrinsic IntID>
1117   : SInst<(outs PredRegs:$dst), (ins IntRegs:$src),
1118              !strconcat("$dst = ", !strconcat(opc , "($src)")),
1119              [(set PredRegs:$dst, (IntID IntRegs:$src))]>;
1120
1121 class qi_SInst_qi_pxfer<string opc, Intrinsic IntID>
1122   : SInst<(outs PredRegs:$dst), (ins IntRegs:$src),
1123              !strconcat("$dst = ", !strconcat(opc , "$src")),
1124              [(set PredRegs:$dst, (IntID IntRegs:$src))]>;
1125
1126 class qi_SInst_qiqi<string opc, Intrinsic IntID>
1127   : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1128              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
1129              [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1130
1131 class qi_SInst_qiqi_neg<string opc, Intrinsic IntID>
1132   : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1133              !strconcat("$dst = ", !strconcat(opc , "($src1, !$src2)")),
1134              [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1135
1136 class di_SInst_di<string opc, Intrinsic IntID>
1137   : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src),
1138              !strconcat("$dst = ", !strconcat(opc , "($src)")),
1139              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src))]>;
1140
1141 class di_SInst_di_sat<string opc, Intrinsic IntID>
1142   : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src),
1143              !strconcat("$dst = ", !strconcat(opc , "($src):sat")),
1144              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src))]>;
1145
1146 class si_SInst_di<string opc, Intrinsic IntID>
1147   : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src),
1148           !strconcat("$dst = ", !strconcat(opc , "($src)")),
1149           [(set IntRegs:$dst, (IntID DoubleRegs:$src))]>;
1150
1151 class si_SInst_di_sat<string opc, Intrinsic IntID>
1152   : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src),
1153           !strconcat("$dst = ", !strconcat(opc , "($src):sat")),
1154           [(set IntRegs:$dst, (IntID DoubleRegs:$src))]>;
1155
1156 class di_SInst_disi<string opc, Intrinsic IntID>
1157   : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
1158           !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
1159           [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, IntRegs:$src2))]>;
1160
1161 class di_SInst_didi<string opc, Intrinsic IntID>
1162   : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1163           !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
1164           [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
1165
1166 class di_SInst_si<string opc, Intrinsic IntID>
1167   : SInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1),
1168           !strconcat("$dst = ", !strconcat(opc , "($src1)")),
1169           [(set DoubleRegs:$dst, (IntID IntRegs:$src1))]>;
1170
1171 class si_SInst_sisiu3<string opc, Intrinsic IntID>
1172   : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2, u3Imm:$src3),
1173           !strconcat("$dst = ", !strconcat(opc , "($src1, $src2, #$src3)")),
1174           [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2,
1175                                      imm:$src3))]>;
1176
1177 class si_SInst_diu5<string opc, Intrinsic IntID>
1178   : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, u5Imm:$src2),
1179           !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
1180           [(set IntRegs:$dst, (IntID DoubleRegs:$src1, imm:$src2))]>;
1181
1182 class si_SInst_disi<string opc, Intrinsic IntID>
1183   : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
1184           !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
1185           [(set IntRegs:$dst, (IntID DoubleRegs:$src1, IntRegs:$src2))]>;
1186
1187 class si_SInst_sidi<string opc, Intrinsic IntID>
1188   : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, DoubleRegs:$src2),
1189           !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
1190           [(set IntRegs:$dst, (IntID IntRegs:$src1, DoubleRegs:$src2))]>;
1191
1192 class di_SInst_disisi<string opc, Intrinsic IntID>
1193   : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2,
1194                                        IntRegs:$src3),
1195           !strconcat("$dst = ", !strconcat(opc , "($src1, $src2, $src3)")),
1196           [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, IntRegs:$src2,
1197                                         IntRegs:$src3))]>;
1198
1199 class di_SInst_sisi<string opc, Intrinsic IntID>
1200   : SInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1201           !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
1202           [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1203
1204 class qi_SInst_siu5<string opc, Intrinsic IntID>
1205   : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1206           !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
1207           [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
1208
1209 class qi_SInst_siu6<string opc, Intrinsic IntID>
1210   : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, u6Imm:$src2),
1211           !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
1212           [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
1213
1214 class qi_SInst_sisi<string opc, Intrinsic IntID>
1215   : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1216           !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
1217           [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1218
1219 class si_SInst_si<string opc, Intrinsic IntID>
1220   : SInst<(outs IntRegs:$dst), (ins IntRegs:$src),
1221           !strconcat("$dst = ", !strconcat(opc , "($src)")),
1222           [(set IntRegs:$dst, (IntID IntRegs:$src))]>;
1223
1224 class si_SInst_si_sat<string opc, Intrinsic IntID>
1225   : SInst<(outs IntRegs:$dst), (ins IntRegs:$src),
1226           !strconcat("$dst = ", !strconcat(opc , "($src):sat")),
1227           [(set IntRegs:$dst, (IntID IntRegs:$src))]>;
1228
1229 class di_SInst_qi<string opc, Intrinsic IntID>
1230   : SInst<(outs DoubleRegs:$dst), (ins IntRegs:$src),
1231           !strconcat("$dst = ", !strconcat(opc , "($src)")),
1232           [(set DoubleRegs:$dst, (IntID IntRegs:$src))]>;
1233
1234 class si_SInst_qi<string opc, Intrinsic IntID>
1235   : SInst<(outs IntRegs:$dst), (ins IntRegs:$src),
1236           !strconcat("$dst = ", !strconcat(opc , "$src")),
1237           [(set IntRegs:$dst, (IntID IntRegs:$src))]>;
1238
1239 class si_SInst_qiqi<string opc, Intrinsic IntID>
1240   : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1241           !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
1242           [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1243
1244 class qi_SInst_si<string opc, Intrinsic IntID>
1245   : SInst<(outs PredRegs:$dst), (ins IntRegs:$src),
1246           !strconcat("$dst = ", !strconcat(opc , "$src")),
1247           [(set PredRegs:$dst, (IntID IntRegs:$src))]>;
1248
1249 class si_SInst_sisi<string opc, Intrinsic IntID>
1250   : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1251           !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
1252           [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1253
1254 class di_SInst_diu6<string opc, Intrinsic IntID>
1255   : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u6Imm:$src2),
1256           !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
1257           [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, imm:$src2))]>;
1258
1259 class si_SInst_siu5<string opc, Intrinsic IntID>
1260   : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1261           !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
1262           [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
1263
1264 class si_SInst_siu5_rnd<string opc, Intrinsic IntID>
1265   : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1266           !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2):rnd")),
1267           [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
1268
1269 class si_SInst_siu5u5<string opc, Intrinsic IntID>
1270   : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2, u5Imm:$src3),
1271           !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2, #$src3)")),
1272           [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2, imm:$src3))]>;
1273
1274 class si_SInst_sisisi_acc<string opc, Intrinsic IntID>
1275   : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1276                                         IntRegs:$src2),
1277               !strconcat("$dst += ", !strconcat(opc , "($src1, $src2)")),
1278               [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1279                                          IntRegs:$src2))],
1280               "$dst2 = $dst">;
1281
1282 class si_SInst_sisisi_nac<string opc, Intrinsic IntID>
1283   : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1284                                         IntRegs:$src2),
1285               !strconcat("$dst -= ", !strconcat(opc , "($src1, $src2)")),
1286               [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1287                                          IntRegs:$src2))],
1288               "$dst2 = $dst">;
1289
1290 class di_SInst_didisi_acc<string opc, Intrinsic IntID>
1291   : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
1292                                            IntRegs:$src2),
1293                !strconcat("$dst += ", !strconcat(opc , "($src1, $src2)")),
1294                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
1295                                              DoubleRegs:$src1,
1296                                              IntRegs:$src2))],
1297                "$dst2 = $dst">;
1298
1299 class di_SInst_didisi_nac<string opc, Intrinsic IntID>
1300   : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
1301                                            IntRegs:$src2),
1302           !strconcat("$dst -= ", !strconcat(opc , "($src1, $src2)")),
1303           [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
1304                                         DoubleRegs:$src1, IntRegs:$src2))],
1305           "$dst2 = $dst">;
1306
1307 class si_SInst_sisiu5u5<string opc, Intrinsic IntID>
1308   : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1309                                         u5Imm:$src2, u5Imm:$src3),
1310               !strconcat("$dst = ", !strconcat(opc ,
1311                                                "($src1, #$src2, #$src3)")),
1312               [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1313                                          imm:$src2, imm:$src3))],
1314               "$dst2 = $dst">;
1315
1316 class si_SInst_sisidi<string opc, Intrinsic IntID>
1317   : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1318                                         DoubleRegs:$src2),
1319               !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
1320               [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1321                                          DoubleRegs:$src2))],
1322               "$dst2 = $dst">;
1323
1324 class di_SInst_didiu6u6<string opc, Intrinsic IntID>
1325   : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
1326                                            u6Imm:$src2, u6Imm:$src3),
1327               !strconcat("$dst = ", !strconcat(opc ,
1328                                                "($src1, #$src2, #$src3)")),
1329               [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, DoubleRegs:$src1,
1330                                             imm:$src2, imm:$src3))],
1331               "$dst2 = $dst">;
1332
1333 class di_SInst_dididi<string opc, Intrinsic IntID>
1334   : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
1335                                            DoubleRegs:$src2),
1336               !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
1337               [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
1338                                             DoubleRegs:$src1,
1339                                             DoubleRegs:$src2))],
1340               "$dst2 = $dst">;
1341
1342 class di_SInst_diu6u6<string opc, Intrinsic IntID>
1343   : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u6Imm:$src2,
1344                                        u6Imm:$src3),
1345           !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2, #$src3)")),
1346           [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, imm:$src2,
1347                                         imm:$src3))]>;
1348
1349 class di_SInst_didiqi<string opc, Intrinsic IntID>
1350   : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2,
1351                                        IntRegs:$src3),
1352           !strconcat("$dst = ", !strconcat(opc , "($src1, $src2, $src3)")),
1353           [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2,
1354                                         IntRegs:$src3))]>;
1355
1356 class di_SInst_didiu3<string opc, Intrinsic IntID>
1357   : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2,
1358                                        u3Imm:$src3),
1359           !strconcat("$dst = ", !strconcat(opc , "($src1, $src2, #$src3)")),
1360           [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2,
1361                                         imm:$src3))]>;
1362
1363 class di_SInst_didisi_or<string opc, Intrinsic IntID>
1364   : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
1365                                            IntRegs:$src2),
1366           !strconcat("$dst |= ", !strconcat(opc , "($src1, $src2)")),
1367           [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, DoubleRegs:$src1,
1368                                         IntRegs:$src2))],
1369           "$dst2 = $dst">;
1370
1371 class di_SInst_didisi_and<string opc, Intrinsic IntID>
1372   : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
1373                                            IntRegs:$src2),
1374           !strconcat("$dst &= ", !strconcat(opc , "($src1, $src2)")),
1375           [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, DoubleRegs:$src1,
1376                                         IntRegs:$src2))],
1377           "$dst2 = $dst">;
1378
1379 class di_SInst_didiu6_and<string opc, Intrinsic IntID>
1380   : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
1381                                            u6Imm:$src2),
1382           !strconcat("$dst &= ", !strconcat(opc , "($src1, #$src2)")),
1383           [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, DoubleRegs:$src1,
1384                                         imm:$src2))],
1385           "$dst2 = $dst">;
1386
1387 class di_SInst_didiu6_or<string opc, Intrinsic IntID>
1388   : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
1389                                            u6Imm:$src2),
1390           !strconcat("$dst |= ", !strconcat(opc , "($src1, #$src2)")),
1391           [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, DoubleRegs:$src1,
1392                                         imm:$src2))],
1393           "$dst2 = $dst">;
1394
1395 class di_SInst_didiu6_xor<string opc, Intrinsic IntID>
1396   : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
1397                                            u6Imm:$src2),
1398           !strconcat("$dst ^= ", !strconcat(opc , "($src1, #$src2)")),
1399           [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, DoubleRegs:$src1,
1400                                         imm:$src2))],
1401           "$dst2 = $dst">;
1402
1403 class si_SInst_sisisi_and<string opc, Intrinsic IntID>
1404   : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1405                                         IntRegs:$src2),
1406               !strconcat("$dst &= ", !strconcat(opc , "($src1, $src2)")),
1407               [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1408                                          IntRegs:$src2))],
1409               "$dst2 = $dst">;
1410
1411 class si_SInst_sisisi_or<string opc, Intrinsic IntID>
1412   : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1413                                         IntRegs:$src2),
1414               !strconcat("$dst |= ", !strconcat(opc , "($src1, $src2)")),
1415               [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1416                                          IntRegs:$src2))],
1417               "$dst2 = $dst">;
1418
1419
1420 class si_SInst_sisiu5_and<string opc, Intrinsic IntID>
1421   : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1422                                         u5Imm:$src2),
1423               !strconcat("$dst &= ", !strconcat(opc , "($src1, #$src2)")),
1424               [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1425                                          imm:$src2))],
1426               "$dst2 = $dst">;
1427
1428 class si_SInst_sisiu5_or<string opc, Intrinsic IntID>
1429   : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1430                                         u5Imm:$src2),
1431               !strconcat("$dst |= ", !strconcat(opc , "($src1, #$src2)")),
1432               [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1433                                          imm:$src2))],
1434               "$dst2 = $dst">;
1435
1436 class si_SInst_sisiu5_xor<string opc, Intrinsic IntID>
1437   : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1438                                         u5Imm:$src2),
1439               !strconcat("$dst ^= ", !strconcat(opc , "($src1, #$src2)")),
1440               [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1441                                          imm:$src2))],
1442               "$dst2 = $dst">;
1443
1444 class si_SInst_sisiu5_acc<string opc, Intrinsic IntID>
1445   : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1446                                         u5Imm:$src2),
1447               !strconcat("$dst += ", !strconcat(opc , "($src1, #$src2)")),
1448               [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1449                                          imm:$src2))],
1450               "$dst2 = $dst">;
1451
1452 class si_SInst_sisiu5_nac<string opc, Intrinsic IntID>
1453   : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1454                                         u5Imm:$src2),
1455               !strconcat("$dst -= ", !strconcat(opc , "($src1, #$src2)")),
1456               [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1457                                          imm:$src2))],
1458               "$dst2 = $dst">;
1459
1460 class di_SInst_didiu6_acc<string opc, Intrinsic IntID>
1461   : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
1462                                            u5Imm:$src2),
1463               !strconcat("$dst += ", !strconcat(opc , "($src1, #$src2)")),
1464               [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
1465                                             DoubleRegs:$src1, imm:$src2))],
1466               "$dst2 = $dst">;
1467
1468 class di_SInst_didiu6_nac<string opc, Intrinsic IntID>
1469   : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
1470                                            u5Imm:$src2),
1471               !strconcat("$dst -= ", !strconcat(opc , "($src1, #$src2)")),
1472               [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, DoubleRegs:$src1,
1473                                             imm:$src2))],
1474               "$dst2 = $dst">;
1475
1476
1477 //
1478 // MInst classes.
1479 //
1480
1481 class di_MInst_sisi_rnd_hh_s1<string opc, Intrinsic IntID>
1482   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1483                !strconcat("$dst = ", !strconcat(opc ,
1484                                                 "($src1.H, $src2.H):<<1:rnd")),
1485                [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1486
1487 class di_MInst_sisi_rnd_hh<string opc, Intrinsic IntID>
1488   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1489                !strconcat("$dst = ", !strconcat(opc ,
1490                                                 "($src1.H, $src2.H):rnd")),
1491                [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1492
1493 class di_MInst_sisi_rnd_hl_s1<string opc, Intrinsic IntID>
1494   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1495                !strconcat("$dst = ", !strconcat(opc ,
1496                                                 "($src1.H, $src2.L):<<1:rnd")),
1497                [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1498
1499 class di_MInst_sisi_rnd_hl<string opc, Intrinsic IntID>
1500   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1501                !strconcat("$dst = ", !strconcat(opc ,
1502                                                 "($src1.H, $src2.L):rnd")),
1503                [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1504
1505 class di_MInst_sisi_rnd_lh_s1<string opc, Intrinsic IntID>
1506   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1507                !strconcat("$dst = ", !strconcat(opc ,
1508                                                 "($src1.L, $src2.H):<<1:rnd")),
1509                [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1510
1511 class di_MInst_sisi_rnd_lh<string opc, Intrinsic IntID>
1512   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1513                !strconcat("$dst = ", !strconcat(opc ,
1514                                                 "($src1.L, $src2.H):rnd")),
1515                [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1516
1517 class di_MInst_sisi_rnd_ll_s1<string opc, Intrinsic IntID>
1518   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1519                !strconcat("$dst = ", !strconcat(opc ,
1520                                                 "($src1.L, $src2.L):<<1:rnd")),
1521                [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1522
1523 class di_MInst_sisi_rnd_ll<string opc, Intrinsic IntID>
1524   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1525                !strconcat("$dst = ", !strconcat(opc ,
1526                                                 "($src1.L, $src2.L):rnd")),
1527                [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1528
1529 class di_MInst_disisi_acc<string opc, Intrinsic IntID>
1530   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1531                                            IntRegs:$src2),
1532              !strconcat("$dst += ", !strconcat(opc , "($src1, $src2)")),
1533              [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1534                                            IntRegs:$src2))],
1535              "$dst2 = $dst">;
1536
1537 class di_MInst_disisi_nac<string opc, Intrinsic IntID>
1538   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1539                                            IntRegs:$src2),
1540              !strconcat("$dst -= ", !strconcat(opc , "($src1, $src2)")),
1541              [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1542                                            IntRegs:$src2))],
1543              "$dst2 = $dst">;
1544
1545 class di_MInst_disisi_acc_sat<string opc, Intrinsic IntID>
1546   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1547                                            IntRegs:$src2),
1548              !strconcat("$dst += ", !strconcat(opc , "($src1, $src2):sat")),
1549              [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1550                                            IntRegs:$src2))],
1551              "$dst2 = $dst">;
1552
1553 class di_MInst_disisi_nac_sat<string opc, Intrinsic IntID>
1554   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1555                                            IntRegs:$src2),
1556              !strconcat("$dst -= ", !strconcat(opc , "($src1, $src2):sat")),
1557              [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1558                                            IntRegs:$src2))],
1559              "$dst2 = $dst">;
1560
1561 class di_MInst_disisi_acc_sat_conj<string opc, Intrinsic IntID>
1562   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1563                                            IntRegs:$src2),
1564              !strconcat("$dst += ", !strconcat(opc , "($src1, $src2*):sat")),
1565              [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1566                                            IntRegs:$src2))],
1567              "$dst2 = $dst">;
1568
1569 class di_MInst_disisi_nac_sat_conj<string opc, Intrinsic IntID>
1570   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1571                                            IntRegs:$src2),
1572              !strconcat("$dst -= ", !strconcat(opc , "($src1, $src2*):sat")),
1573              [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1574                                            IntRegs:$src2))],
1575              "$dst2 = $dst">;
1576
1577 class di_MInst_disisi_nac_s1_sat<string opc, Intrinsic IntID>
1578   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1579                                            IntRegs:$src2),
1580              !strconcat("$dst -= ", !strconcat(opc ,
1581                                                "($src1, $src2):<<1:sat")),
1582              [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1583                                            IntRegs:$src2))],
1584              "$dst2 = $dst">;
1585
1586 class di_MInst_disisi_acc_s1_sat_conj<string opc, Intrinsic IntID>
1587   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1588                                            IntRegs:$src2),
1589              !strconcat("$dst += ", !strconcat(opc ,
1590                                                "($src1, $src2*):<<1:sat")),
1591              [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1592                                            IntRegs:$src2))],
1593              "$dst2 = $dst">;
1594
1595 class di_MInst_disisi_nac_s1_sat_conj<string opc, Intrinsic IntID>
1596   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1597                                            IntRegs:$src2),
1598              !strconcat("$dst -= ", !strconcat(opc ,
1599                                                "($src1, $src2*):<<1:sat")),
1600              [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1601                                            IntRegs:$src2))],
1602              "$dst2 = $dst">;
1603
1604 class di_MInst_s8s8<string opc, Intrinsic IntID>
1605   : MInst<(outs DoubleRegs:$dst), (ins s8Imm:$src1, s8Imm:$src2),
1606              !strconcat("$dst = ", !strconcat(opc , "(#$src1, #$src2)")),
1607              [(set DoubleRegs:$dst, (IntID imm:$src1, imm:$src2))]>;
1608
1609 class si_MInst_sis9<string opc, Intrinsic IntID>
1610   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, s9Imm:$src2),
1611              !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
1612              [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
1613
1614 class si_MInst_sisi<string opc, Intrinsic IntID>
1615   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1616              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
1617              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1618
1619 class di_MInst_sisi_hh<string opc, Intrinsic IntID>
1620   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1621              !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.H)")),
1622              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1623
1624 class di_MInst_sisi_hh_s1<string opc, Intrinsic IntID>
1625   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1626              !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.H):<<1")),
1627              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1628
1629 class di_MInst_sisi_lh<string opc, Intrinsic IntID>
1630   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1631              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H)")),
1632              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1633
1634 class di_MInst_sisi_lh_s1<string opc, Intrinsic IntID>
1635   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1636              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H):<<1")),
1637              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1638
1639 class di_MInst_sisi_hl<string opc, Intrinsic IntID>
1640   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1641              !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.L)")),
1642              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1643
1644 class di_MInst_sisi_hl_s1<string opc, Intrinsic IntID>
1645   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1646              !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.L):<<1")),
1647              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1648
1649 class di_MInst_sisi_ll<string opc, Intrinsic IntID>
1650   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1651              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L)")),
1652              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1653
1654 class di_MInst_sisi_ll_s1<string opc, Intrinsic IntID>
1655   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1656              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L):<<1")),
1657              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1658
1659
1660 class si_MInst_sisi_hh<string opc, Intrinsic IntID>
1661   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1662              !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.H)")),
1663              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1664
1665 class si_MInst_sisi_hh_s1<string opc, Intrinsic IntID>
1666   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1667              !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.H):<<1")),
1668              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1669
1670 class si_MInst_sisi_lh<string opc, Intrinsic IntID>
1671   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1672              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H)")),
1673              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1674
1675 class si_MInst_sisi_lh_s1<string opc, Intrinsic IntID>
1676   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1677              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H):<<1")),
1678              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1679
1680 class si_MInst_sisi_hl<string opc, Intrinsic IntID>
1681   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1682              !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.L)")),
1683              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1684
1685 class si_MInst_sisi_hl_s1<string opc, Intrinsic IntID>
1686   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1687              !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.L):<<1")),
1688              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1689
1690 class si_MInst_sisi_ll<string opc, Intrinsic IntID>
1691   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1692              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L)")),
1693              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1694
1695 class si_MInst_sisi_ll_s1<string opc, Intrinsic IntID>
1696   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1697              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L):<<1")),
1698              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1699
1700 class si_MInst_sisi_up<string opc, Intrinsic IntID>
1701   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1702              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
1703              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1704
1705 class di_MInst_didi<string opc, Intrinsic IntID>
1706   : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1707              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
1708              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
1709                                            DoubleRegs:$src2))]>;
1710
1711 class di_MInst_didi_conj<string opc, Intrinsic IntID>
1712   : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1713              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2*)")),
1714              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
1715                                            DoubleRegs:$src2))]>;
1716
1717 class di_MInst_sisi_s1_sat_conj<string opc, Intrinsic IntID>
1718   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1719              !strconcat("$dst = ", !strconcat(opc ,
1720                                               "($src1, $src2*):<<1:sat")),
1721              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1722
1723 class di_MInst_didi_s1_rnd_sat<string opc, Intrinsic IntID>
1724   : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1725              !strconcat("$dst = ", !strconcat(opc ,
1726                                               "($src1, $src2):<<1:rnd:sat")),
1727              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
1728                                            DoubleRegs:$src2))]>;
1729
1730 class di_MInst_didi_sat<string opc, Intrinsic IntID>
1731   : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1732              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):sat")),
1733              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
1734                                            DoubleRegs:$src2))]>;
1735
1736 class di_MInst_didi_rnd_sat<string opc, Intrinsic IntID>
1737   : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1738              !strconcat("$dst = ", !strconcat(opc ,
1739                                               "($src1, $src2):rnd:sat")),
1740              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
1741                                            DoubleRegs:$src2))]>;
1742
1743 class si_SInst_sisi_sat<string opc, Intrinsic IntID>
1744   : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1745           !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):sat")),
1746           [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1747
1748 class si_SInst_didi_sat<string opc, Intrinsic IntID>
1749   : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1750           !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):sat")),
1751           [(set IntRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
1752
1753 class si_SInst_disi_s1_rnd_sat<string opc, Intrinsic IntID>
1754   : MInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
1755              !strconcat("$dst = ", !strconcat(opc ,
1756                                               "($src1, $src2):<<1:rnd:sat")),
1757              [(set IntRegs:$dst, (IntID DoubleRegs:$src1, IntRegs:$src2))]>;
1758
1759 class si_MInst_sisi_s1_rnd_sat<string opc, Intrinsic IntID>
1760   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1761              !strconcat("$dst = ", !strconcat(opc ,
1762                                               "($src1, $src2):<<1:rnd:sat")),
1763              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1764
1765 class si_MInst_sisi_l_s1_rnd_sat<string opc, Intrinsic IntID>
1766   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1767              !strconcat("$dst = ", !strconcat(opc ,
1768                                               "($src1, $src2.L):<<1:rnd:sat")),
1769              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1770
1771 class si_MInst_sisi_h_s1_rnd_sat<string opc, Intrinsic IntID>
1772   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1773              !strconcat("$dst = ", !strconcat(opc ,
1774                                               "($src1, $src2.H):<<1:rnd:sat")),
1775              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1776
1777 class si_MInst_sisi_rnd_sat_conj<string opc, Intrinsic IntID>
1778   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1779              !strconcat("$dst = ", !strconcat(opc ,
1780                                               "($src1, $src2*):rnd:sat")),
1781              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1782
1783 class si_MInst_sisi_s1_rnd_sat_conj<string opc, Intrinsic IntID>
1784   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1785              !strconcat("$dst = ", !strconcat(opc ,
1786                                               "($src1, $src2*):<<1:rnd:sat")),
1787              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1788
1789 class si_MInst_sisi_rnd_sat<string opc, Intrinsic IntID>
1790   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1791              !strconcat("$dst = ", !strconcat(opc ,
1792                                               "($src1, $src2):rnd:sat")),
1793              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1794
1795 class si_MInst_sisi_rnd<string opc, Intrinsic IntID>
1796   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1797              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):rnd")),
1798              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1799
1800 class si_MInst_sisisi_xacc<string opc, Intrinsic IntID>
1801   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src2,
1802                                         IntRegs:$src3),
1803              !strconcat("$dst ^= ", !strconcat(opc , "($src2, $src3)")),
1804              [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src2,
1805                                         IntRegs:$src3))],
1806              "$dst2 = $dst">;
1807
1808 class si_MInst_sisisi_acc<string opc, Intrinsic IntID>
1809   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src2,
1810                                         IntRegs:$src3),
1811              !strconcat("$dst += ", !strconcat(opc , "($src2, $src3)")),
1812              [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src2,
1813                                         IntRegs:$src3))],
1814              "$dst2 = $dst">;
1815
1816 class si_MInst_sisisi_nac<string opc, Intrinsic IntID>
1817   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src2,
1818                                         IntRegs:$src3),
1819              !strconcat("$dst -= ", !strconcat(opc , "($src2, $src3)")),
1820              [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src2,
1821                                         IntRegs:$src3))],
1822              "$dst2 = $dst">;
1823
1824 class si_MInst_sisis8_acc<string opc, Intrinsic IntID>
1825   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src2,
1826                                         s8Imm:$src3),
1827              !strconcat("$dst += ", !strconcat(opc , "($src2, #$src3)")),
1828              [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src2,
1829                                         imm:$src3))],
1830              "$dst2 = $dst">;
1831
1832 class si_MInst_sisis8_nac<string opc, Intrinsic IntID>
1833   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src2,
1834                                         s8Imm:$src3),
1835              !strconcat("$dst -= ", !strconcat(opc , "($src2, #$src3)")),
1836              [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src2,
1837                                         imm:$src3))],
1838              "$dst2 = $dst">;
1839
1840 class si_MInst_sisiu4u5<string opc, Intrinsic IntID>
1841   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1842                                         u4Imm:$src2, u5Imm:$src3),
1843                !strconcat("$dst = ", !strconcat(opc ,
1844                                                 "($src1, #$src2, #$src3)")),
1845                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1846                                           imm:$src2, imm:$src3))],
1847                "$dst2 = $dst">;
1848
1849 class si_MInst_sisiu8_acc<string opc, Intrinsic IntID>
1850   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src2,
1851                                         u8Imm:$src3),
1852                !strconcat("$dst += ", !strconcat(opc , "($src2, #$src3)")),
1853                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src2,
1854                                           imm:$src3))],
1855                "$dst2 = $dst">;
1856
1857 class si_MInst_sisiu8_nac<string opc, Intrinsic IntID>
1858   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src2,
1859                                         u8Imm:$src3),
1860                !strconcat("$dst -= ", !strconcat(opc , "($src2, #$src3)")),
1861                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src2,
1862                                           imm:$src3))],
1863                "$dst2 = $dst">;
1864
1865 class si_MInst_sisisi_acc_hh<string opc, Intrinsic IntID>
1866   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1867                                         IntRegs:$src2),
1868                !strconcat("$dst += ", !strconcat(opc , "($src1.H, $src2.H)")),
1869                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1870                                           IntRegs:$src2))],
1871                "$dst2 = $dst">;
1872
1873 class si_MInst_sisisi_acc_sat_lh<string opc, Intrinsic IntID>
1874   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1875                                         IntRegs:$src2),
1876                !strconcat("$dst += ", !strconcat(opc ,
1877                                                  "($src1.L, $src2.H):sat")),
1878                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1879                                           IntRegs:$src2))],
1880                "$dst2 = $dst">;
1881
1882 class si_MInst_sisisi_acc_sat_lh_s1<string opc, Intrinsic IntID>
1883   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1884                                         IntRegs:$src2),
1885                !strconcat("$dst += ", !strconcat(opc ,
1886                                                  "($src1.L, $src2.H):<<1:sat")),
1887                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1888                                           IntRegs:$src2))],
1889                "$dst2 = $dst">;
1890
1891 class si_MInst_sisisi_acc_sat_hh<string opc, Intrinsic IntID>
1892   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1893                                         IntRegs:$src2),
1894                !strconcat("$dst += ", !strconcat(opc ,
1895                                                  "($src1.H, $src2.H):sat")),
1896                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1897                                           IntRegs:$src2))],
1898                "$dst2 = $dst">;
1899
1900 class si_MInst_sisisi_acc_sat_hh_s1<string opc, Intrinsic IntID>
1901   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1902                                         IntRegs:$src2),
1903                !strconcat("$dst += ", !strconcat(opc ,
1904                                                  "($src1.H, $src2.H):<<1:sat")),
1905                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1906                                           IntRegs:$src2))],
1907                "$dst2 = $dst">;
1908
1909 class si_MInst_sisisi_acc_hh_s1<string opc, Intrinsic IntID>
1910   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1911                                         IntRegs:$src2),
1912                !strconcat("$dst += ", !strconcat(opc ,
1913                                                  "($src1.H, $src2.H):<<1")),
1914                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1915                                           IntRegs:$src2))],
1916                "$dst2 = $dst">;
1917
1918 class si_MInst_sisisi_nac_hh<string opc, Intrinsic IntID>
1919   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1920                                         IntRegs:$src2),
1921                !strconcat("$dst -= ", !strconcat(opc , "($src1.H, $src2.H)")),
1922                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1923                                           IntRegs:$src2))],
1924                "$dst2 = $dst">;
1925
1926 class si_MInst_sisisi_nac_sat_hh_s1<string opc, Intrinsic IntID>
1927   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1928                                         IntRegs:$src2),
1929                !strconcat("$dst -= ", !strconcat(opc ,
1930                                                  "($src1.H, $src2.H):<<1:sat")),
1931                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1932                                           IntRegs:$src2))],
1933                "$dst2 = $dst">;
1934
1935 class si_MInst_sisisi_nac_sat_hh<string opc, Intrinsic IntID>
1936   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1937                                         IntRegs:$src2),
1938                !strconcat("$dst -= ", !strconcat(opc ,
1939                                                  "($src1.H, $src2.H):sat")),
1940                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1941                                           IntRegs:$src2))],
1942                "$dst2 = $dst">;
1943
1944 class si_MInst_sisisi_nac_sat_hl_s1<string opc, Intrinsic IntID>
1945   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1946                                         IntRegs:$src2),
1947                !strconcat("$dst -= ", !strconcat(opc ,
1948                                                  "($src1.H, $src2.L):<<1:sat")),
1949                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1950                                           IntRegs:$src2))],
1951                "$dst2 = $dst">;
1952
1953 class si_MInst_sisisi_nac_sat_hl<string opc, Intrinsic IntID>
1954   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1955                                         IntRegs:$src2),
1956                !strconcat("$dst -= ", !strconcat(opc ,
1957                                                  "($src1.H, $src2.L):sat")),
1958                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1959                                           IntRegs:$src2))],
1960                "$dst2 = $dst">;
1961
1962 class si_MInst_sisisi_nac_sat_lh_s1<string opc, Intrinsic IntID>
1963   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1964                                         IntRegs:$src2),
1965                !strconcat("$dst -= ", !strconcat(opc ,
1966                                                  "($src1.L, $src2.H):<<1:sat")),
1967                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1968                                           IntRegs:$src2))],
1969                "$dst2 = $dst">;
1970
1971 class si_MInst_sisisi_nac_sat_lh<string opc, Intrinsic IntID>
1972   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1973                                         IntRegs:$src2),
1974                !strconcat("$dst -= ", !strconcat(opc ,
1975                                                  "($src1.L, $src2.H):sat")),
1976                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1977                                           IntRegs:$src2))],
1978                "$dst2 = $dst">;
1979
1980 class si_MInst_sisisi_nac_sat_ll_s1<string opc, Intrinsic IntID>
1981   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1982                                         IntRegs:$src2),
1983                !strconcat("$dst -= ", !strconcat(opc ,
1984                                                  "($src1.L, $src2.L):<<1:sat")),
1985                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1986                                           IntRegs:$src2))],
1987                "$dst2 = $dst">;
1988
1989 class si_MInst_sisisi_nac_sat_ll<string opc, Intrinsic IntID>
1990   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1991                                         IntRegs:$src2),
1992                !strconcat("$dst -= ", !strconcat(opc ,
1993                                                  "($src1.L, $src2.L):sat")),
1994                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1995                                           IntRegs:$src2))],
1996                "$dst2 = $dst">;
1997
1998 class si_MInst_sisisi_nac_hh_s1<string opc, Intrinsic IntID>
1999   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
2000                                         IntRegs:$src2),
2001                !strconcat("$dst -= ", !strconcat(opc ,
2002                                                  "($src1.H, $src2.H):<<1")),
2003                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
2004                                           IntRegs:$src2))],
2005                "$dst2 = $dst">;
2006
2007 class si_MInst_sisisi_acc_hl<string opc, Intrinsic IntID>
2008   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
2009                                         IntRegs:$src2),
2010                !strconcat("$dst += ", !strconcat(opc , "($src1.H, $src2.L)")),
2011                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
2012                                           IntRegs:$src2))],
2013                "$dst2 = $dst">;
2014
2015 class si_MInst_sisisi_acc_hl_s1<string opc, Intrinsic IntID>
2016   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
2017                                         IntRegs:$src2),
2018                !strconcat("$dst += ", !strconcat(opc ,
2019                                                  "($src1.H, $src2.L):<<1")),
2020                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
2021                                           IntRegs:$src2))],
2022                "$dst2 = $dst">;
2023
2024 class si_MInst_sisisi_nac_hl<string opc, Intrinsic IntID>
2025   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
2026                                         IntRegs:$src2),
2027                !strconcat("$dst -= ", !strconcat(opc , "($src1.H, $src2.L)")),
2028                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
2029                                           IntRegs:$src2))],
2030                "$dst2 = $dst">;
2031
2032 class si_MInst_sisisi_nac_hl_s1<string opc, Intrinsic IntID>
2033   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
2034                                         IntRegs:$src2),
2035                !strconcat("$dst -= ", !strconcat(opc ,
2036                                                  "($src1.H, $src2.L):<<1")),
2037                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
2038                                           IntRegs:$src2))],
2039                "$dst2 = $dst">;
2040
2041 class si_MInst_sisisi_acc_lh<string opc, Intrinsic IntID>
2042   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
2043                                         IntRegs:$src2),
2044                !strconcat("$dst += ", !strconcat(opc , "($src1.L, $src2.H)")),
2045                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
2046                                           IntRegs:$src2))],
2047                "$dst2 = $dst">;
2048
2049 class si_MInst_sisisi_acc_lh_s1<string opc, Intrinsic IntID>
2050   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
2051                                         IntRegs:$src2),
2052                !strconcat("$dst += ", !strconcat(opc ,
2053                                                  "($src1.L, $src2.H):<<1")),
2054                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
2055                                           IntRegs:$src2))],
2056                "$dst2 = $dst">;
2057
2058 class si_MInst_sisisi_nac_lh<string opc, Intrinsic IntID>
2059   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
2060                                         IntRegs:$src2),
2061                !strconcat("$dst -= ", !strconcat(opc , "($src1.L, $src2.H)")),
2062                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
2063                                           IntRegs:$src2))],
2064                "$dst2 = $dst">;
2065
2066 class si_MInst_sisisi_nac_lh_s1<string opc, Intrinsic IntID>
2067   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
2068                                         IntRegs:$src2),
2069                !strconcat("$dst -= ", !strconcat(opc ,
2070                                                  "($src1.L, $src2.H):<<1")),
2071                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
2072                                           IntRegs:$src2))],
2073                "$dst2 = $dst">;
2074
2075 class si_MInst_sisisi_acc_ll<string opc, Intrinsic IntID>
2076   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
2077                                         IntRegs:$src2),
2078                !strconcat("$dst += ", !strconcat(opc , "($src1.L, $src2.L)")),
2079                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
2080                                           IntRegs:$src2))],
2081                "$dst2 = $dst">;
2082
2083 class si_MInst_sisisi_acc_ll_s1<string opc, Intrinsic IntID>
2084   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
2085                                         IntRegs:$src2),
2086                !strconcat("$dst += ", !strconcat(opc ,
2087                                                  "($src1.L, $src2.L):<<1")),
2088                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
2089                                           IntRegs:$src2))],
2090                "$dst2 = $dst">;
2091
2092 class si_MInst_sisisi_acc_sat_ll_s1<string opc, Intrinsic IntID>
2093   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
2094                                         IntRegs:$src2),
2095                !strconcat("$dst += ", !strconcat(opc ,
2096                                                  "($src1.L, $src2.L):<<1:sat")),
2097                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
2098                                           IntRegs:$src2))],
2099                "$dst2 = $dst">;
2100
2101 class si_MInst_sisisi_acc_sat_hl_s1<string opc, Intrinsic IntID>
2102   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
2103                                         IntRegs:$src2),
2104                !strconcat("$dst += ", !strconcat(opc ,
2105                                                  "($src1.H, $src2.L):<<1:sat")),
2106                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
2107                                           IntRegs:$src2))],
2108                "$dst2 = $dst">;
2109
2110 class si_MInst_sisisi_acc_sat_ll<string opc, Intrinsic IntID>
2111   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
2112                                         IntRegs:$src2),
2113                !strconcat("$dst += ", !strconcat(opc ,
2114                                                  "($src1.L, $src2.L):sat")),
2115                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
2116                                           IntRegs:$src2))],
2117                "$dst2 = $dst">;
2118
2119 class si_MInst_sisisi_acc_sat_hl<string opc, Intrinsic IntID>
2120   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
2121                                         IntRegs:$src2),
2122                !strconcat("$dst += ", !strconcat(opc ,
2123                                                  "($src1.H, $src2.L):sat")),
2124                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
2125                                           IntRegs:$src2))],
2126                "$dst2 = $dst">;
2127
2128 class si_MInst_sisisi_nac_ll<string opc, Intrinsic IntID>
2129   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
2130                                         IntRegs:$src2),
2131                !strconcat("$dst -= ", !strconcat(opc , "($src1.L, $src2.L)")),
2132                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
2133                                           IntRegs:$src2))],
2134                "$dst2 = $dst">;
2135
2136 class si_MInst_sisisi_nac_ll_s1<string opc, Intrinsic IntID>
2137   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
2138                                         IntRegs:$src2),
2139                !strconcat("$dst -= ", !strconcat(opc ,
2140                                                  "($src1.L, $src2.L):<<1")),
2141                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
2142                                           IntRegs:$src2))],
2143                "$dst2 = $dst">;
2144
2145 class si_MInst_sisisi_nac_hh_sat<string opc, Intrinsic IntID>
2146   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
2147                                         IntRegs:$src2),
2148                !strconcat("$dst -= ", !strconcat(opc ,
2149                                                  "($src1.H, $src2.H):sat")),
2150                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
2151                                           IntRegs:$src2))],
2152                "$dst2 = $dst">;
2153
2154 class si_MInst_sisisi_nac_hh_s1_sat<string opc, Intrinsic IntID>
2155   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
2156                                         IntRegs:$src2),
2157                !strconcat("$dst -= ", !strconcat(opc ,
2158                                                  "($src1.H, $src2.H):<<1:sat")),
2159                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
2160                                           IntRegs:$src2))],
2161                "$dst2 = $dst">;
2162
2163 class si_MInst_sisisi_nac_hl_sat<string opc, Intrinsic IntID>
2164   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
2165                                         IntRegs:$src2),
2166                !strconcat("$dst -= ", !strconcat(opc ,
2167                                                  "($src1.H, $src2.L):sat")),
2168                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
2169                                           IntRegs:$src2))],
2170                "$dst2 = $dst">;
2171
2172 class si_MInst_sisisi_nac_hl_s1_sat<string opc, Intrinsic IntID>
2173   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
2174                                         IntRegs:$src2),
2175                !strconcat("$dst -= ", !strconcat(opc ,
2176                                                  "($src1.H, $src2.L):<<1:sat")),
2177                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
2178                                           IntRegs:$src2))],
2179                "$dst2 = $dst">;
2180
2181 class si_MInst_sisisi_nac_lh_sat<string opc, Intrinsic IntID>
2182   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
2183                                         IntRegs:$src2),
2184                !strconcat("$dst -= ", !strconcat(opc ,
2185                                                  "($src1.L, $src2.H):sat")),
2186                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
2187                                           IntRegs:$src2))],
2188                "$dst2 = $dst">;
2189
2190 class si_MInst_sisisi_nac_lh_s1_sat<string opc, Intrinsic IntID>
2191   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
2192                                         IntRegs:$src2),
2193                !strconcat("$dst -= ", !strconcat(opc ,
2194                                                  "($src1.L, $src2.H):<<1:sat")),
2195                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
2196                                           IntRegs:$src2))],
2197                "$dst2 = $dst">;
2198
2199 class si_MInst_sisisi_nac_ll_sat<string opc, Intrinsic IntID>
2200   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
2201                                         IntRegs:$src2),
2202                !strconcat("$dst -= ", !strconcat(opc ,
2203                                                  "($src1.L, $src2.L):sat")),
2204                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
2205                                           IntRegs:$src2))],
2206                "$dst2 = $dst">;
2207
2208 class si_MInst_sisisi_nac_ll_s1_sat<string opc, Intrinsic IntID>
2209   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
2210                                         IntRegs:$src2),
2211                !strconcat("$dst -= ", !strconcat(opc ,
2212                                                  "($src1.L, $src2.L):<<1:sat")),
2213                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
2214                                           IntRegs:$src2))],
2215                "$dst2 = $dst">;
2216
2217 class di_ALU32_sisi<string opc, Intrinsic IntID>
2218   : ALU32_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2219              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
2220              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
2221
2222 class di_MInst_sisi<string opc, Intrinsic IntID>
2223   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2224              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
2225              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
2226
2227 class di_MInst_sisi_sat<string opc, Intrinsic IntID>
2228   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2229              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):sat")),
2230              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
2231
2232 class di_MInst_sisi_sat_conj<string opc, Intrinsic IntID>
2233   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2234              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2*):sat")),
2235              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
2236
2237 class di_MInst_sisi_s1_sat<string opc, Intrinsic IntID>
2238   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2239              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):<<1:sat")),
2240              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
2241
2242 class di_MInst_didi_s1_sat<string opc, Intrinsic IntID>
2243   : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
2244              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):<<1:sat")),
2245              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
2246                                            DoubleRegs:$src2))]>;
2247
2248 class si_MInst_didi_s1_rnd_sat<string opc, Intrinsic IntID>
2249   : MInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
2250              !strconcat("$dst = ", !strconcat(opc ,
2251                                               "($src1, $src2):<<1:rnd:sat")),
2252              [(set IntRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
2253
2254 class si_MInst_didi_rnd_sat<string opc, Intrinsic IntID>
2255   : MInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
2256              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):rnd:sat")),
2257              [(set IntRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
2258
2259 class si_MInst_sisi_sat_hh<string opc, Intrinsic IntID>
2260   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2261              !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.H):sat")),
2262              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
2263
2264 class si_MInst_sisi_sat_hh_s1<string opc, Intrinsic IntID>
2265   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2266                !strconcat("$dst = ", !strconcat(opc ,
2267                                                 "($src1.H, $src2.H):<<1:sat")),
2268                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
2269
2270 class si_MInst_sisi_sat_hl<string opc, Intrinsic IntID>
2271   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2272              !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.L):sat")),
2273              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
2274
2275 class si_MInst_sisi_sat_hl_s1<string opc, Intrinsic IntID>
2276   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2277                !strconcat("$dst = ", !strconcat(opc ,
2278                                                 "($src1.H, $src2.L):<<1:sat")),
2279                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
2280
2281 class si_MInst_sisi_sat_lh<string opc, Intrinsic IntID>
2282   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2283              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H):sat")),
2284              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
2285
2286 class si_MInst_sisi_sat_lh_s1<string opc, Intrinsic IntID>
2287   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2288                !strconcat("$dst = ", !strconcat(opc ,
2289                                                 "($src1.L, $src2.H):<<1:sat")),
2290                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
2291
2292 class si_MInst_sisi_sat_ll<string opc, Intrinsic IntID>
2293   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2294              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L):sat")),
2295              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
2296
2297 class si_MInst_sisi_sat_ll_s1<string opc, Intrinsic IntID>
2298   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2299                !strconcat("$dst = ", !strconcat(opc ,
2300                                                 "($src1.L, $src2.L):<<1:sat")),
2301                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
2302
2303 class si_MInst_sisi_sat_rnd_hh<string opc, Intrinsic IntID>
2304   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2305                !strconcat("$dst = ", !strconcat(opc ,
2306                                                 "($src1.H, $src2.H):rnd:sat")),
2307                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
2308
2309 class si_MInst_sisi_rnd_hh<string opc, Intrinsic IntID>
2310   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2311                !strconcat("$dst = ", !strconcat(opc ,
2312                                                 "($src1.H, $src2.H):rnd")),
2313                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
2314
2315 class si_MInst_sisi_rnd_hh_s1<string opc, Intrinsic IntID>
2316   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2317                !strconcat("$dst = ", !strconcat(opc ,
2318                                                 "($src1.H, $src2.H):<<1:rnd")),
2319                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
2320
2321 class si_MInst_sisi_sat_rnd_hh_s1<string opc, Intrinsic IntID>
2322   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2323                !strconcat("$dst = ",
2324                           !strconcat(opc ,
2325                                      "($src1.H, $src2.H):<<1:rnd:sat")),
2326                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
2327
2328 class si_MInst_sisi_rnd_hl<string opc, Intrinsic IntID>
2329   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2330                !strconcat("$dst = ",
2331                           !strconcat(opc , "($src1.H, $src2.L):rnd")),
2332                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
2333
2334 class si_MInst_sisi_rnd_hl_s1<string opc, Intrinsic IntID>
2335   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2336                !strconcat("$dst = ",
2337                           !strconcat(opc , "($src1.H, $src2.L):<<1:rnd")),
2338                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
2339
2340 class si_MInst_sisi_sat_rnd_hl<string opc, Intrinsic IntID>
2341   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2342                !strconcat("$dst = ",
2343                           !strconcat(opc , "($src1.H, $src2.L):rnd:sat")),
2344                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
2345
2346 class si_MInst_sisi_sat_rnd_hl_s1<string opc, Intrinsic IntID>
2347   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2348                !strconcat("$dst = ",
2349                           !strconcat(opc , "($src1.H, $src2.L):<<1:rnd:sat")),
2350                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
2351
2352 class si_MInst_sisi_rnd_lh<string opc, Intrinsic IntID>
2353   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2354                !strconcat("$dst = ",
2355                           !strconcat(opc , "($src1.L, $src2.H):rnd")),
2356                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
2357
2358 class si_MInst_sisi_sat_rnd_lh<string opc, Intrinsic IntID>
2359   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2360                !strconcat("$dst = ",
2361                           !strconcat(opc , "($src1.L, $src2.H):rnd:sat")),
2362                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
2363
2364 class si_MInst_sisi_sat_rnd_lh_s1<string opc, Intrinsic IntID>
2365   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2366                !strconcat("$dst = ",
2367                           !strconcat(opc , "($src1.L, $src2.H):<<1:rnd:sat")),
2368                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
2369
2370 class si_MInst_sisi_rnd_lh_s1<string opc, Intrinsic IntID>
2371   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2372                !strconcat("$dst = ",
2373                           !strconcat(opc , "($src1.L, $src2.H):<<1:rnd")),
2374                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
2375
2376 class si_MInst_sisi_sat_rnd_ll<string opc, Intrinsic IntID>
2377   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2378                !strconcat("$dst = ",
2379                           !strconcat(opc , "($src1.L, $src2.L):rnd:sat")),
2380                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
2381
2382 class si_MInst_sisi_sat_rnd_ll_s1<string opc, Intrinsic IntID>
2383   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2384                !strconcat("$dst = ",
2385                           !strconcat(opc , "($src1.L, $src2.L):<<1:rnd:sat")),
2386                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
2387
2388 class si_MInst_sisi_rnd_ll<string opc, Intrinsic IntID>
2389   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2390                !strconcat("$dst = ",
2391                           !strconcat(opc , "($src1.L, $src2.L):rnd")),
2392                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
2393
2394 class si_MInst_sisi_rnd_ll_s1<string opc, Intrinsic IntID>
2395   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2396                !strconcat("$dst = ",
2397                           !strconcat(opc , "($src1.L, $src2.L):<<1:rnd")),
2398                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
2399
2400 class di_MInst_dididi_acc_sat<string opc, Intrinsic IntID>
2401   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2,
2402                                            DoubleRegs:$src1, DoubleRegs:$src2),
2403                !strconcat("$dst += ", !strconcat(opc , "($src1, $src2):sat")),
2404                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
2405                                              DoubleRegs:$src1,
2406                                              DoubleRegs:$src2))],
2407                "$dst2 = $dst">;
2408
2409 class di_MInst_dididi_acc_rnd_sat<string opc, Intrinsic IntID>
2410   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
2411                                            DoubleRegs:$src2),
2412                !strconcat("$dst += ",
2413                           !strconcat(opc , "($src1, $src2):rnd:sat")),
2414                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
2415                                              DoubleRegs:$src1,
2416                                              DoubleRegs:$src2))],
2417                "$dst2 = $dst">;
2418
2419 class di_MInst_dididi_acc_s1<string opc, Intrinsic IntID>
2420   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2,
2421                                            DoubleRegs:$src1,
2422                                            DoubleRegs:$src2),
2423                !strconcat("$dst += ",
2424                           !strconcat(opc , "($src1, $src2):<<1")),
2425                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
2426                                              DoubleRegs:$src1,
2427                                              DoubleRegs:$src2))],
2428                "$dst2 = $dst">;
2429
2430
2431 class di_MInst_dididi_acc_s1_sat<string opc, Intrinsic IntID>
2432   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2,
2433                                            DoubleRegs:$src1,
2434                                            DoubleRegs:$src2),
2435                !strconcat("$dst += ",
2436                           !strconcat(opc , "($src1, $src2):<<1:sat")),
2437                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
2438                                              DoubleRegs:$src1,
2439                                              DoubleRegs:$src2))],
2440                "$dst2 = $dst">;
2441
2442 class di_MInst_dididi_acc_s1_rnd_sat<string opc, Intrinsic IntID>
2443   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
2444                                            DoubleRegs:$src2),
2445                !strconcat("$dst += ",
2446                           !strconcat(opc , "($src1, $src2):<<1:rnd:sat")),
2447                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
2448                                              DoubleRegs:$src1,
2449                                              DoubleRegs:$src2))],
2450                "$dst2 = $dst">;
2451
2452 class di_MInst_dididi_acc<string opc, Intrinsic IntID>
2453   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
2454                                            DoubleRegs:$src2),
2455                !strconcat("$dst += ", !strconcat(opc , "($src1, $src2)")),
2456                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
2457                                              DoubleRegs:$src1,
2458                                              DoubleRegs:$src2))],
2459                "$dst2 = $dst">;
2460
2461 class di_MInst_dididi_acc_conj<string opc, Intrinsic IntID>
2462   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
2463                                            DoubleRegs:$src2),
2464                !strconcat("$dst += ", !strconcat(opc , "($src1, $src2*)")),
2465                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
2466                                              DoubleRegs:$src1,
2467                                              DoubleRegs:$src2))],
2468                "$dst2 = $dst">;
2469
2470 class di_MInst_disisi_acc_hh<string opc, Intrinsic IntID>
2471   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
2472                                            IntRegs:$src2),
2473                !strconcat("$dst += ", !strconcat(opc , "($src1.H, $src2.H)")),
2474                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
2475                                              IntRegs:$src2))],
2476                "$dst2 = $dst">;
2477
2478 class di_MInst_disisi_acc_hl<string opc, Intrinsic IntID>
2479   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
2480                                            IntRegs:$src2),
2481                !strconcat("$dst += ", !strconcat(opc , "($src1.H, $src2.L)")),
2482                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
2483                                              IntRegs:$src2))],
2484                "$dst2 = $dst">;
2485
2486 class di_MInst_disisi_acc_lh<string opc, Intrinsic IntID>
2487   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
2488                                            IntRegs:$src2),
2489                !strconcat("$dst += ", !strconcat(opc , "($src1.L, $src2.H)")),
2490                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
2491                                              IntRegs:$src2))],
2492                "$dst2 = $dst">;
2493
2494 class di_MInst_disisi_acc_ll<string opc, Intrinsic IntID>
2495   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
2496                                            IntRegs:$src2),
2497                !strconcat("$dst += ", !strconcat(opc , "($src1.L, $src2.L)")),
2498                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
2499                                              IntRegs:$src2))],
2500                "$dst2 = $dst">;
2501
2502 class di_MInst_disisi_acc_hh_s1<string opc, Intrinsic IntID>
2503   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
2504                                            IntRegs:$src2),
2505                !strconcat("$dst += ",
2506                           !strconcat(opc , "($src1.H, $src2.H):<<1")),
2507                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
2508                                              IntRegs:$src2))],
2509                "$dst2 = $dst">;
2510
2511 class di_MInst_disisi_acc_hl_s1<string opc, Intrinsic IntID>
2512   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
2513                                            IntRegs:$src2),
2514                !strconcat("$dst += ",
2515                           !strconcat(opc , "($src1.H, $src2.L):<<1")),
2516                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
2517                                              IntRegs:$src2))],
2518                "$dst2 = $dst">;
2519
2520 class di_MInst_disisi_acc_lh_s1<string opc, Intrinsic IntID>
2521   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
2522                                            IntRegs:$src2),
2523                !strconcat("$dst += ",
2524                           !strconcat(opc , "($src1.L, $src2.H):<<1")),
2525                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
2526                                              IntRegs:$src2))],
2527                "$dst2 = $dst">;
2528
2529 class di_MInst_disisi_acc_ll_s1<string opc, Intrinsic IntID>
2530   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
2531                                            IntRegs:$src2),
2532                !strconcat("$dst += ",
2533                           !strconcat(opc , "($src1.L, $src2.L):<<1")),
2534                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
2535                                              IntRegs:$src2))],
2536                "$dst2 = $dst">;
2537
2538 class di_MInst_disisi_nac_hh<string opc, Intrinsic IntID>
2539   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
2540                                            IntRegs:$src2),
2541                !strconcat("$dst -= ", !strconcat(opc , "($src1.H, $src2.H)")),
2542                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
2543                                              IntRegs:$src2))],
2544                "$dst2 = $dst">;
2545
2546 class di_MInst_disisi_nac_hl<string opc, Intrinsic IntID>
2547   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
2548                                            IntRegs:$src2),
2549                !strconcat("$dst -= ", !strconcat(opc , "($src1.H, $src2.L)")),
2550                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
2551                                              IntRegs:$src2))],
2552                "$dst2 = $dst">;
2553
2554 class di_MInst_disisi_nac_lh<string opc, Intrinsic IntID>
2555   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
2556                                            IntRegs:$src2),
2557                !strconcat("$dst -= ", !strconcat(opc , "($src1.L, $src2.H)")),
2558                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
2559                                              IntRegs:$src2))],
2560                "$dst2 = $dst">;
2561
2562 class di_MInst_disisi_nac_ll<string opc, Intrinsic IntID>
2563   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
2564                                            IntRegs:$src2),
2565                !strconcat("$dst -= ", !strconcat(opc , "($src1.L, $src2.L)")),
2566                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
2567                                              IntRegs:$src2))],
2568                "$dst2 = $dst">;
2569
2570 class di_MInst_disisi_nac_hh_s1<string opc, Intrinsic IntID>
2571   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
2572                                            IntRegs:$src2),
2573                !strconcat("$dst -= ",
2574                           !strconcat(opc , "($src1.H, $src2.H):<<1")),
2575                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
2576                                              IntRegs:$src2))],
2577                "$dst2 = $dst">;
2578
2579 class di_MInst_disisi_nac_hl_s1<string opc, Intrinsic IntID>
2580   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
2581                                            IntRegs:$src2),
2582                !strconcat("$dst -= ",
2583                           !strconcat(opc , "($src1.H, $src2.L):<<1")),
2584                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
2585                                              IntRegs:$src2))],
2586                "$dst2 = $dst">;
2587
2588 class di_MInst_disisi_nac_lh_s1<string opc, Intrinsic IntID>
2589   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
2590                                            IntRegs:$src2),
2591                !strconcat("$dst -= ",
2592                           !strconcat(opc , "($src1.L, $src2.H):<<1")),
2593                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
2594                                              IntRegs:$src2))],
2595                "$dst2 = $dst">;
2596
2597 class di_MInst_disisi_nac_ll_s1<string opc, Intrinsic IntID>
2598   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
2599                                            IntRegs:$src2),
2600                !strconcat("$dst -= ",
2601                           !strconcat(opc , "($src1.L, $src2.L):<<1")),
2602                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
2603                                              IntRegs:$src2))],
2604                "$dst2 = $dst">;
2605
2606 class di_MInst_disisi_acc_s1_sat<string opc, Intrinsic IntID>
2607   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
2608                                            IntRegs:$src2),
2609                !strconcat("$dst += ",
2610                           !strconcat(opc , "($src1, $src2):<<1:sat")),
2611                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
2612                                              IntRegs:$src2))],
2613                "$dst2 = $dst">;
2614
2615 class di_MInst_disi_s1_sat<string opc, Intrinsic IntID>
2616   : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
2617              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):<<1:sat")),
2618              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, IntRegs:$src2))]>;
2619
2620 class di_MInst_didisi_acc_s1_sat<string opc, Intrinsic IntID>
2621   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
2622                                            IntRegs:$src2),
2623                !strconcat("$dst += ",
2624                           !strconcat(opc , "($src1, $src2):<<1:sat")),
2625                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
2626                                              DoubleRegs:$src1,
2627                                              IntRegs:$src2))],
2628                "$dst2 = $dst">;
2629
2630 class si_MInst_disi_s1_rnd_sat<string opc, Intrinsic IntID>
2631   : MInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
2632              !strconcat("$dst = ",
2633                         !strconcat(opc , "($src1, $src2):<<1:rnd:sat")),
2634              [(set IntRegs:$dst, (IntID DoubleRegs:$src1, IntRegs:$src2))]>;
2635
2636 class si_MInst_didi<string opc, Intrinsic IntID>
2637   : MInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
2638              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
2639              [(set IntRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
2640
2641 //
2642 // LDInst classes.
2643 //
2644 let mayLoad = 1, hasSideEffects = 0 in
2645 class di_LDInstPI_diu4<string opc, Intrinsic IntID>
2646   : LDInstPI<(outs IntRegs:$dst, DoubleRegs:$dst2),
2647            (ins IntRegs:$src1, IntRegs:$src2, CtrRegs:$src3, s4Imm:$offset),
2648            "$dst2 = memd($src1++#$offset:circ($src3))",
2649            [],
2650            "$src1 = $dst">;
2651
2652 /********************************************************************
2653 *            ALU32/PERM                                             *
2654 *********************************************************************/
2655
2656 // ALU32 / PERM / Mux.
2657 def HEXAGON_C2_mux:
2658   si_ALU32_qisisi                 <"mux",      int_hexagon_C2_mux>;
2659
2660 /********************************************************************
2661 *            ALU32/PRED                                             *
2662 *********************************************************************/
2663
2664 // ALU32 / PRED / Compare.
2665 def HEXAGON_C2_cmpeq:
2666   qi_ALU32_sisi                   <"cmp.eq",   int_hexagon_C2_cmpeq>;
2667 def HEXAGON_C2_cmpeqi:
2668   qi_ALU32_sis10                  <"cmp.eq",   int_hexagon_C2_cmpeqi>;
2669 def HEXAGON_C2_cmpgei:
2670   qi_ALU32_sis8                   <"cmp.ge",   int_hexagon_C2_cmpgei>;
2671 def HEXAGON_C2_cmpgeui:
2672   qi_ALU32_siu8                   <"cmp.geu",  int_hexagon_C2_cmpgeui>;
2673 def HEXAGON_C2_cmpgt:
2674   qi_ALU32_sisi                   <"cmp.gt",   int_hexagon_C2_cmpgt>;
2675 def HEXAGON_C2_cmpgti:
2676   qi_ALU32_sis10                  <"cmp.gt",   int_hexagon_C2_cmpgti>;
2677 def HEXAGON_C2_cmpgtu:
2678   qi_ALU32_sisi                   <"cmp.gtu",  int_hexagon_C2_cmpgtu>;
2679 def HEXAGON_C2_cmpgtui:
2680   qi_ALU32_siu9                   <"cmp.gtu",  int_hexagon_C2_cmpgtui>;
2681 def HEXAGON_C2_cmplt:
2682   qi_ALU32_sisi                   <"cmp.lt",   int_hexagon_C2_cmplt>;
2683 def HEXAGON_C2_cmpltu:
2684   qi_ALU32_sisi                   <"cmp.ltu",  int_hexagon_C2_cmpltu>;
2685
2686 /********************************************************************
2687 *            ALU32/VH                                               *
2688 *********************************************************************/
2689
2690 // ALU32 / VH / Vector add halfwords.
2691 // Rd32=vadd[u]h(Rs32,Rt32:sat]
2692 def HEXAGON_A2_svaddh:
2693   si_ALU32_sisi                   <"vaddh",    int_hexagon_A2_svaddh>;
2694 def HEXAGON_A2_svaddhs:
2695   si_ALU32_sisi_sat               <"vaddh",    int_hexagon_A2_svaddhs>;
2696 def HEXAGON_A2_svadduhs:
2697   si_ALU32_sisi_sat               <"vadduh",   int_hexagon_A2_svadduhs>;
2698
2699 // ALU32 / VH / Vector average halfwords.
2700 def HEXAGON_A2_svavgh:
2701   si_ALU32_sisi                   <"vavgh",    int_hexagon_A2_svavgh>;
2702 def HEXAGON_A2_svavghs:
2703   si_ALU32_sisi_rnd               <"vavgh",    int_hexagon_A2_svavghs>;
2704 def HEXAGON_A2_svnavgh:
2705   si_ALU32_sisi                   <"vnavgh",   int_hexagon_A2_svnavgh>;
2706
2707 // ALU32 / VH / Vector subtract halfwords.
2708 def HEXAGON_A2_svsubh:
2709   si_ALU32_sisi                   <"vsubh",    int_hexagon_A2_svsubh>;
2710 def HEXAGON_A2_svsubhs:
2711   si_ALU32_sisi_sat               <"vsubh",    int_hexagon_A2_svsubhs>;
2712 def HEXAGON_A2_svsubuhs:
2713   si_ALU32_sisi_sat               <"vsubuh",   int_hexagon_A2_svsubuhs>;
2714
2715 /********************************************************************
2716 *            ALU64/ALU                                              *
2717 *********************************************************************/
2718
2719 // ALU64 / ALU / Compare.
2720 def HEXAGON_C2_cmpeqp:
2721   qi_ALU64_didi                   <"cmp.eq",   int_hexagon_C2_cmpeqp>;
2722 def HEXAGON_C2_cmpgtp:
2723   qi_ALU64_didi                   <"cmp.gt",   int_hexagon_C2_cmpgtp>;
2724 def HEXAGON_C2_cmpgtup:
2725   qi_ALU64_didi                   <"cmp.gtu",  int_hexagon_C2_cmpgtup>;
2726
2727 // ALU64 / ALU / Transfer register.
2728 def HEXAGON_A2_tfrp:
2729   di_ALU64_di                     <"",         int_hexagon_A2_tfrp>;
2730
2731 /********************************************************************
2732 *            ALU64/VB                                               *
2733 *********************************************************************/
2734
2735 // ALU64 / VB / Vector add unsigned bytes.
2736 def HEXAGON_A2_vaddub:
2737   di_ALU64_didi                   <"vaddub",   int_hexagon_A2_vaddub>;
2738 def HEXAGON_A2_vaddubs:
2739   di_ALU64_didi_sat               <"vaddub",   int_hexagon_A2_vaddubs>;
2740
2741 // ALU64 / VB / Vector average unsigned bytes.
2742 def HEXAGON_A2_vavgub:
2743   di_ALU64_didi                   <"vavgub",   int_hexagon_A2_vavgub>;
2744 def HEXAGON_A2_vavgubr:
2745   di_ALU64_didi_rnd               <"vavgub",   int_hexagon_A2_vavgubr>;
2746
2747 // ALU64 / VB / Vector compare unsigned bytes.
2748 def HEXAGON_A2_vcmpbeq:
2749   qi_ALU64_didi                   <"vcmpb.eq", int_hexagon_A2_vcmpbeq>;
2750 def HEXAGON_A2_vcmpbgtu:
2751   qi_ALU64_didi                   <"vcmpb.gtu",int_hexagon_A2_vcmpbgtu>;
2752
2753 // ALU64 / VB / Vector maximum/minimum unsigned bytes.
2754 def HEXAGON_A2_vmaxub:
2755   di_ALU64_didi                   <"vmaxub",   int_hexagon_A2_vmaxub>;
2756 def HEXAGON_A2_vminub:
2757   di_ALU64_didi                   <"vminub",   int_hexagon_A2_vminub>;
2758
2759 // ALU64 / VB / Vector subtract unsigned bytes.
2760 def HEXAGON_A2_vsubub:
2761   di_ALU64_didi                   <"vsubub",   int_hexagon_A2_vsubub>;
2762 def HEXAGON_A2_vsububs:
2763   di_ALU64_didi_sat               <"vsubub",   int_hexagon_A2_vsububs>;
2764
2765 // ALU64 / VB / Vector mux.
2766 def HEXAGON_C2_vmux:
2767   di_ALU64_qididi                 <"vmux",     int_hexagon_C2_vmux>;
2768
2769
2770 /********************************************************************
2771 *            ALU64/VH                                               *
2772 *********************************************************************/
2773
2774 // ALU64 / VH / Vector add halfwords.
2775 // Rdd64=vadd[u]h(Rss64,Rtt64:sat]
2776 def HEXAGON_A2_vaddh:
2777   di_ALU64_didi                   <"vaddh",    int_hexagon_A2_vaddh>;
2778 def HEXAGON_A2_vaddhs:
2779   di_ALU64_didi_sat               <"vaddh",    int_hexagon_A2_vaddhs>;
2780 def HEXAGON_A2_vadduhs:
2781   di_ALU64_didi_sat               <"vadduh",   int_hexagon_A2_vadduhs>;
2782
2783 // ALU64 / VH / Vector average halfwords.
2784 // Rdd64=v[n]avg[u]h(Rss64,Rtt64:rnd/:crnd][:sat]
2785 def HEXAGON_A2_vavgh:
2786   di_ALU64_didi                   <"vavgh",    int_hexagon_A2_vavgh>;
2787 def HEXAGON_A2_vavghcr:
2788   di_ALU64_didi_crnd              <"vavgh",    int_hexagon_A2_vavghcr>;
2789 def HEXAGON_A2_vavghr:
2790   di_ALU64_didi_rnd               <"vavgh",    int_hexagon_A2_vavghr>;
2791 def HEXAGON_A2_vavguh:
2792   di_ALU64_didi                   <"vavguh",   int_hexagon_A2_vavguh>;
2793 def HEXAGON_A2_vavguhr:
2794   di_ALU64_didi_rnd               <"vavguh",   int_hexagon_A2_vavguhr>;
2795 def HEXAGON_A2_vnavgh:
2796   di_ALU64_didi                   <"vnavgh",   int_hexagon_A2_vnavgh>;
2797 def HEXAGON_A2_vnavghcr:
2798   di_ALU64_didi_crnd_sat          <"vnavgh",   int_hexagon_A2_vnavghcr>;
2799 def HEXAGON_A2_vnavghr:
2800   di_ALU64_didi_rnd_sat           <"vnavgh",   int_hexagon_A2_vnavghr>;
2801
2802 // ALU64 / VH / Vector compare halfwords.
2803 def HEXAGON_A2_vcmpheq:
2804   qi_ALU64_didi                   <"vcmph.eq", int_hexagon_A2_vcmpheq>;
2805 def HEXAGON_A2_vcmphgt:
2806   qi_ALU64_didi                   <"vcmph.gt", int_hexagon_A2_vcmphgt>;
2807 def HEXAGON_A2_vcmphgtu:
2808   qi_ALU64_didi                   <"vcmph.gtu",int_hexagon_A2_vcmphgtu>;
2809
2810 // ALU64 / VH / Vector maximum halfwords.
2811 def HEXAGON_A2_vmaxh:
2812   di_ALU64_didi                   <"vmaxh",    int_hexagon_A2_vmaxh>;
2813 def HEXAGON_A2_vmaxuh:
2814   di_ALU64_didi                   <"vmaxuh",   int_hexagon_A2_vmaxuh>;
2815
2816 // ALU64 / VH / Vector minimum halfwords.
2817 def HEXAGON_A2_vminh:
2818   di_ALU64_didi                   <"vminh",    int_hexagon_A2_vminh>;
2819 def HEXAGON_A2_vminuh:
2820   di_ALU64_didi                   <"vminuh",   int_hexagon_A2_vminuh>;
2821
2822 // ALU64 / VH / Vector subtract halfwords.
2823 def HEXAGON_A2_vsubh:
2824   di_ALU64_didi                   <"vsubh",    int_hexagon_A2_vsubh>;
2825 def HEXAGON_A2_vsubhs:
2826   di_ALU64_didi_sat               <"vsubh",    int_hexagon_A2_vsubhs>;
2827 def HEXAGON_A2_vsubuhs:
2828   di_ALU64_didi_sat               <"vsubuh",   int_hexagon_A2_vsubuhs>;
2829
2830
2831 /********************************************************************
2832 *            ALU64/VW                                               *
2833 *********************************************************************/
2834
2835 // ALU64 / VW / Vector add words.
2836 // Rdd32=vaddw(Rss32,Rtt32)[:sat]
2837 def HEXAGON_A2_vaddw:
2838   di_ALU64_didi                   <"vaddw",    int_hexagon_A2_vaddw>;
2839 def HEXAGON_A2_vaddws:
2840   di_ALU64_didi_sat               <"vaddw",   int_hexagon_A2_vaddws>;
2841
2842 // ALU64 / VW / Vector average words.
2843 def HEXAGON_A2_vavguw:
2844   di_ALU64_didi                   <"vavguw",   int_hexagon_A2_vavguw>;
2845 def HEXAGON_A2_vavguwr:
2846   di_ALU64_didi_rnd               <"vavguw",   int_hexagon_A2_vavguwr>;
2847 def HEXAGON_A2_vavgw:
2848   di_ALU64_didi                   <"vavgw",    int_hexagon_A2_vavgw>;
2849 def HEXAGON_A2_vavgwcr:
2850   di_ALU64_didi_crnd              <"vavgw",    int_hexagon_A2_vavgwcr>;
2851 def HEXAGON_A2_vavgwr:
2852   di_ALU64_didi_rnd               <"vavgw",    int_hexagon_A2_vavgwr>;
2853 def HEXAGON_A2_vnavgw:
2854   di_ALU64_didi                   <"vnavgw",   int_hexagon_A2_vnavgw>;
2855 def HEXAGON_A2_vnavgwcr:
2856   di_ALU64_didi_crnd_sat          <"vnavgw",   int_hexagon_A2_vnavgwcr>;
2857 def HEXAGON_A2_vnavgwr:
2858   di_ALU64_didi_rnd_sat           <"vnavgw",   int_hexagon_A2_vnavgwr>;
2859
2860 // ALU64 / VW / Vector compare words.
2861 def HEXAGON_A2_vcmpweq:
2862   qi_ALU64_didi                   <"vcmpw.eq", int_hexagon_A2_vcmpweq>;
2863 def HEXAGON_A2_vcmpwgt:
2864   qi_ALU64_didi                   <"vcmpw.gt", int_hexagon_A2_vcmpwgt>;
2865 def HEXAGON_A2_vcmpwgtu:
2866   qi_ALU64_didi                   <"vcmpw.gtu",int_hexagon_A2_vcmpwgtu>;
2867
2868 // ALU64 / VW / Vector maximum words.
2869 def HEXAGON_A2_vmaxw:
2870   di_ALU64_didi                   <"vmaxw",    int_hexagon_A2_vmaxw>;
2871 def HEXAGON_A2_vmaxuw:
2872   di_ALU64_didi                   <"vmaxuw",   int_hexagon_A2_vmaxuw>;
2873
2874 // ALU64 / VW / Vector minimum words.
2875 def HEXAGON_A2_vminw:
2876   di_ALU64_didi                   <"vminw",    int_hexagon_A2_vminw>;
2877 def HEXAGON_A2_vminuw:
2878   di_ALU64_didi                   <"vminuw",   int_hexagon_A2_vminuw>;
2879
2880 // ALU64 / VW / Vector subtract words.
2881 def HEXAGON_A2_vsubw:
2882   di_ALU64_didi                   <"vsubw",    int_hexagon_A2_vsubw>;
2883 def HEXAGON_A2_vsubws:
2884   di_ALU64_didi_sat               <"vsubw",    int_hexagon_A2_vsubws>;
2885
2886
2887 /********************************************************************
2888 *            CR                                                     *
2889 *********************************************************************/
2890
2891 // CR / Logical reductions on predicates.
2892 def HEXAGON_C2_all8:
2893   qi_SInst_qi                     <"all8",     int_hexagon_C2_all8>;
2894 def HEXAGON_C2_any8:
2895   qi_SInst_qi                     <"any8",     int_hexagon_C2_any8>;
2896
2897 // CR / Logical operations on predicates.
2898 def HEXAGON_C2_pxfer_map:
2899   qi_SInst_qi_pxfer               <"",         int_hexagon_C2_pxfer_map>;
2900 def HEXAGON_C2_and:
2901   qi_SInst_qiqi                   <"and",      int_hexagon_C2_and>;
2902 def HEXAGON_C2_andn:
2903   qi_SInst_qiqi_neg               <"and",      int_hexagon_C2_andn>;
2904 def HEXAGON_C2_not:
2905   qi_SInst_qi                     <"not",      int_hexagon_C2_not>;
2906 def HEXAGON_C2_or:
2907   qi_SInst_qiqi                   <"or",       int_hexagon_C2_or>;
2908 def HEXAGON_C2_orn:
2909   qi_SInst_qiqi_neg               <"or",       int_hexagon_C2_orn>;
2910 def HEXAGON_C2_xor:
2911   qi_SInst_qiqi                   <"xor",      int_hexagon_C2_xor>;
2912
2913
2914 /********************************************************************
2915 *            MTYPE/ALU                                              *
2916 *********************************************************************/
2917
2918 // MTYPE / ALU / Vector absolute difference.
2919 def HEXAGON_M2_vabsdiffh:
2920   di_MInst_didi                   <"vabsdiffh",int_hexagon_M2_vabsdiffh>;
2921 def HEXAGON_M2_vabsdiffw:
2922   di_MInst_didi                   <"vabsdiffw",int_hexagon_M2_vabsdiffw>;
2923
2924
2925 /********************************************************************
2926 *            MTYPE/COMPLEX                                          *
2927 *********************************************************************/
2928
2929 // MTYPE / COMPLEX / Complex multiply.
2930 // Rdd[-+]=cmpy(Rs, Rt:<<1]:sat
2931 def HEXAGON_M2_cmpys_s1:
2932   di_MInst_sisi_s1_sat            <"cmpy",     int_hexagon_M2_cmpys_s1>;
2933 def HEXAGON_M2_cmpys_s0:
2934   di_MInst_sisi_sat               <"cmpy",     int_hexagon_M2_cmpys_s0>;
2935 def HEXAGON_M2_cmpysc_s1:
2936   di_MInst_sisi_s1_sat_conj       <"cmpy",     int_hexagon_M2_cmpysc_s1>;
2937 def HEXAGON_M2_cmpysc_s0:
2938   di_MInst_sisi_sat_conj          <"cmpy",     int_hexagon_M2_cmpysc_s0>;
2939
2940 def HEXAGON_M2_cmacs_s1:
2941   di_MInst_disisi_acc_s1_sat      <"cmpy",     int_hexagon_M2_cmacs_s1>;
2942 def HEXAGON_M2_cmacs_s0:
2943   di_MInst_disisi_acc_sat         <"cmpy",     int_hexagon_M2_cmacs_s0>;
2944 def HEXAGON_M2_cmacsc_s1:
2945   di_MInst_disisi_acc_s1_sat_conj <"cmpy",     int_hexagon_M2_cmacsc_s1>;
2946 def HEXAGON_M2_cmacsc_s0:
2947   di_MInst_disisi_acc_sat_conj    <"cmpy",     int_hexagon_M2_cmacsc_s0>;
2948
2949 def HEXAGON_M2_cnacs_s1:
2950   di_MInst_disisi_nac_s1_sat      <"cmpy",     int_hexagon_M2_cnacs_s1>;
2951 def HEXAGON_M2_cnacs_s0:
2952   di_MInst_disisi_nac_sat         <"cmpy",     int_hexagon_M2_cnacs_s0>;
2953 def HEXAGON_M2_cnacsc_s1:
2954   di_MInst_disisi_nac_s1_sat_conj <"cmpy",     int_hexagon_M2_cnacsc_s1>;
2955 def HEXAGON_M2_cnacsc_s0:
2956   di_MInst_disisi_nac_sat_conj    <"cmpy",     int_hexagon_M2_cnacsc_s0>;
2957
2958 // MTYPE / COMPLEX / Complex multiply real or imaginary.
2959 def HEXAGON_M2_cmpyr_s0:
2960   di_MInst_sisi                   <"cmpyr",    int_hexagon_M2_cmpyr_s0>;
2961 def HEXAGON_M2_cmacr_s0:
2962   di_MInst_disisi_acc             <"cmpyr",    int_hexagon_M2_cmacr_s0>;
2963
2964 def HEXAGON_M2_cmpyi_s0:
2965   di_MInst_sisi                   <"cmpyi",    int_hexagon_M2_cmpyi_s0>;
2966 def HEXAGON_M2_cmaci_s0:
2967   di_MInst_disisi_acc             <"cmpyi",    int_hexagon_M2_cmaci_s0>;
2968
2969 // MTYPE / COMPLEX / Complex multiply with round and pack.
2970 // Rxx32+=cmpy(Rs32,[*]Rt32:<<1]:rnd:sat
2971 def HEXAGON_M2_cmpyrs_s0:
2972   si_MInst_sisi_rnd_sat           <"cmpy",     int_hexagon_M2_cmpyrs_s0>;
2973 def HEXAGON_M2_cmpyrs_s1:
2974   si_MInst_sisi_s1_rnd_sat        <"cmpy",     int_hexagon_M2_cmpyrs_s1>;
2975
2976 def HEXAGON_M2_cmpyrsc_s0:
2977   si_MInst_sisi_rnd_sat_conj      <"cmpy",     int_hexagon_M2_cmpyrsc_s0>;
2978 def HEXAGON_M2_cmpyrsc_s1:
2979   si_MInst_sisi_s1_rnd_sat_conj   <"cmpy",     int_hexagon_M2_cmpyrsc_s1>;
2980
2981 //MTYPE / COMPLEX / Vector complex multiply real or imaginary.
2982 def HEXAGON_M2_vcmpy_s0_sat_i:
2983   di_MInst_didi_sat               <"vcmpyi",   int_hexagon_M2_vcmpy_s0_sat_i>;
2984 def HEXAGON_M2_vcmpy_s1_sat_i:
2985   di_MInst_didi_s1_sat            <"vcmpyi",   int_hexagon_M2_vcmpy_s1_sat_i>;
2986
2987 def HEXAGON_M2_vcmpy_s0_sat_r:
2988   di_MInst_didi_sat               <"vcmpyr",   int_hexagon_M2_vcmpy_s0_sat_r>;
2989 def HEXAGON_M2_vcmpy_s1_sat_r:
2990   di_MInst_didi_s1_sat            <"vcmpyr",   int_hexagon_M2_vcmpy_s1_sat_r>;
2991
2992 def HEXAGON_M2_vcmac_s0_sat_i:
2993   di_MInst_dididi_acc_sat         <"vcmpyi",   int_hexagon_M2_vcmac_s0_sat_i>;
2994 def HEXAGON_M2_vcmac_s0_sat_r:
2995   di_MInst_dididi_acc_sat         <"vcmpyr",   int_hexagon_M2_vcmac_s0_sat_r>;
2996
2997 //MTYPE / COMPLEX / Vector reduce complex multiply real or imaginary.
2998 def HEXAGON_M2_vrcmpyi_s0:
2999   di_MInst_didi                   <"vrcmpyi",  int_hexagon_M2_vrcmpyi_s0>;
3000 def HEXAGON_M2_vrcmpyr_s0:
3001   di_MInst_didi                   <"vrcmpyr",  int_hexagon_M2_vrcmpyr_s0>;
3002
3003 def HEXAGON_M2_vrcmpyi_s0c:
3004   di_MInst_didi_conj              <"vrcmpyi",  int_hexagon_M2_vrcmpyi_s0c>;
3005 def HEXAGON_M2_vrcmpyr_s0c:
3006   di_MInst_didi_conj              <"vrcmpyr",  int_hexagon_M2_vrcmpyr_s0c>;
3007
3008 def HEXAGON_M2_vrcmaci_s0:
3009   di_MInst_dididi_acc             <"vrcmpyi",  int_hexagon_M2_vrcmaci_s0>;
3010 def HEXAGON_M2_vrcmacr_s0:
3011   di_MInst_dididi_acc             <"vrcmpyr",  int_hexagon_M2_vrcmacr_s0>;
3012
3013 def HEXAGON_M2_vrcmaci_s0c:
3014   di_MInst_dididi_acc_conj        <"vrcmpyi",  int_hexagon_M2_vrcmaci_s0c>;
3015 def HEXAGON_M2_vrcmacr_s0c:
3016   di_MInst_dididi_acc_conj        <"vrcmpyr",  int_hexagon_M2_vrcmacr_s0c>;
3017
3018
3019 /********************************************************************
3020 *            MTYPE/MPYH                                             *
3021 *********************************************************************/
3022
3023 // MTYPE / MPYH / Multiply word by half (32x16).
3024 //Rdd[+]=vmpywoh(Rss,Rtt)[:<<1][:rnd][:sat]
3025 //Rdd[+]=vmpyweh(Rss,Rtt)[:<<1][:rnd][:sat]
3026 def HEXAGON_M2_mmpyl_rs1:
3027   di_MInst_didi_s1_rnd_sat        <"vmpyweh",  int_hexagon_M2_mmpyl_rs1>;
3028 def HEXAGON_M2_mmpyl_s1:
3029   di_MInst_didi_s1_sat            <"vmpyweh",  int_hexagon_M2_mmpyl_s1>;
3030 def HEXAGON_M2_mmpyl_rs0:
3031   di_MInst_didi_rnd_sat           <"vmpyweh",  int_hexagon_M2_mmpyl_rs0>;
3032 def HEXAGON_M2_mmpyl_s0:
3033   di_MInst_didi_sat               <"vmpyweh",  int_hexagon_M2_mmpyl_s0>;
3034 def HEXAGON_M2_mmpyh_rs1:
3035   di_MInst_didi_s1_rnd_sat        <"vmpywoh",  int_hexagon_M2_mmpyh_rs1>;
3036 def HEXAGON_M2_mmpyh_s1:
3037   di_MInst_didi_s1_sat            <"vmpywoh",  int_hexagon_M2_mmpyh_s1>;
3038 def HEXAGON_M2_mmpyh_rs0:
3039   di_MInst_didi_rnd_sat           <"vmpywoh",  int_hexagon_M2_mmpyh_rs0>;
3040 def HEXAGON_M2_mmpyh_s0:
3041   di_MInst_didi_sat               <"vmpywoh",  int_hexagon_M2_mmpyh_s0>;
3042 def HEXAGON_M2_mmacls_rs1:
3043   di_MInst_dididi_acc_s1_rnd_sat  <"vmpyweh",  int_hexagon_M2_mmacls_rs1>;
3044 def HEXAGON_M2_mmacls_s1:
3045   di_MInst_dididi_acc_s1_sat      <"vmpyweh",  int_hexagon_M2_mmacls_s1>;
3046 def HEXAGON_M2_mmacls_rs0:
3047   di_MInst_dididi_acc_rnd_sat     <"vmpyweh",  int_hexagon_M2_mmacls_rs0>;
3048 def HEXAGON_M2_mmacls_s0:
3049   di_MInst_dididi_acc_sat         <"vmpyweh",  int_hexagon_M2_mmacls_s0>;
3050 def HEXAGON_M2_mmachs_rs1:
3051   di_MInst_dididi_acc_s1_rnd_sat  <"vmpywoh",  int_hexagon_M2_mmachs_rs1>;
3052 def HEXAGON_M2_mmachs_s1:
3053   di_MInst_dididi_acc_s1_sat      <"vmpywoh",  int_hexagon_M2_mmachs_s1>;
3054 def HEXAGON_M2_mmachs_rs0:
3055   di_MInst_dididi_acc_rnd_sat     <"vmpywoh",  int_hexagon_M2_mmachs_rs0>;
3056 def HEXAGON_M2_mmachs_s0:
3057   di_MInst_dididi_acc_sat         <"vmpywoh",  int_hexagon_M2_mmachs_s0>;
3058
3059 // MTYPE / MPYH / Multiply word by unsigned half (32x16).
3060 //Rdd[+]=vmpywouh(Rss,Rtt)[:<<1][:rnd][:sat]
3061 //Rdd[+]=vmpyweuh(Rss,Rtt)[:<<1][:rnd][:sat]
3062 def HEXAGON_M2_mmpyul_rs1:
3063   di_MInst_didi_s1_rnd_sat        <"vmpyweuh", int_hexagon_M2_mmpyul_rs1>;
3064 def HEXAGON_M2_mmpyul_s1:
3065   di_MInst_didi_s1_sat            <"vmpyweuh", int_hexagon_M2_mmpyul_s1>;
3066 def HEXAGON_M2_mmpyul_rs0:
3067   di_MInst_didi_rnd_sat           <"vmpyweuh", int_hexagon_M2_mmpyul_rs0>;
3068 def HEXAGON_M2_mmpyul_s0:
3069   di_MInst_didi_sat               <"vmpyweuh", int_hexagon_M2_mmpyul_s0>;
3070 def HEXAGON_M2_mmpyuh_rs1:
3071   di_MInst_didi_s1_rnd_sat        <"vmpywouh", int_hexagon_M2_mmpyuh_rs1>;
3072 def HEXAGON_M2_mmpyuh_s1:
3073   di_MInst_didi_s1_sat            <"vmpywouh", int_hexagon_M2_mmpyuh_s1>;
3074 def HEXAGON_M2_mmpyuh_rs0:
3075   di_MInst_didi_rnd_sat           <"vmpywouh", int_hexagon_M2_mmpyuh_rs0>;
3076 def HEXAGON_M2_mmpyuh_s0:
3077   di_MInst_didi_sat               <"vmpywouh", int_hexagon_M2_mmpyuh_s0>;
3078 def HEXAGON_M2_mmaculs_rs1:
3079   di_MInst_dididi_acc_s1_rnd_sat  <"vmpyweuh", int_hexagon_M2_mmaculs_rs1>;
3080 def HEXAGON_M2_mmaculs_s1:
3081   di_MInst_dididi_acc_s1_sat      <"vmpyweuh", int_hexagon_M2_mmaculs_s1>;
3082 def HEXAGON_M2_mmaculs_rs0:
3083   di_MInst_dididi_acc_rnd_sat     <"vmpyweuh", int_hexagon_M2_mmaculs_rs0>;
3084 def HEXAGON_M2_mmaculs_s0:
3085   di_MInst_dididi_acc_sat         <"vmpyweuh", int_hexagon_M2_mmaculs_s0>;
3086 def HEXAGON_M2_mmacuhs_rs1:
3087   di_MInst_dididi_acc_s1_rnd_sat  <"vmpywouh", int_hexagon_M2_mmacuhs_rs1>;
3088 def HEXAGON_M2_mmacuhs_s1:
3089   di_MInst_dididi_acc_s1_sat      <"vmpywouh", int_hexagon_M2_mmacuhs_s1>;
3090 def HEXAGON_M2_mmacuhs_rs0:
3091   di_MInst_dididi_acc_rnd_sat     <"vmpywouh", int_hexagon_M2_mmacuhs_rs0>;
3092 def HEXAGON_M2_mmacuhs_s0:
3093   di_MInst_dididi_acc_sat         <"vmpywouh", int_hexagon_M2_mmacuhs_s0>;
3094
3095 /********************************************************************
3096 *            MTYPE/VB                                               *
3097 *********************************************************************/
3098
3099 // MTYPE / VB / Vector reduce add unsigned bytes.
3100 def HEXAGON_A2_vraddub:
3101   di_MInst_didi                   <"vraddub", int_hexagon_A2_vraddub>;
3102 def HEXAGON_A2_vraddub_acc:
3103   di_MInst_dididi_acc             <"vraddub", int_hexagon_A2_vraddub_acc>;
3104
3105 // MTYPE / VB / Vector sum of absolute differences unsigned bytes.
3106 def HEXAGON_A2_vrsadub:
3107   di_MInst_didi                   <"vrsadub", int_hexagon_A2_vrsadub>;
3108 def HEXAGON_A2_vrsadub_acc:
3109   di_MInst_dididi_acc             <"vrsadub", int_hexagon_A2_vrsadub_acc>;
3110
3111 /********************************************************************
3112 *            MTYPE/VH                                               *
3113 *********************************************************************/
3114
3115 // MTYPE / VH / Vector dual multiply.
3116 def HEXAGON_M2_vdmpys_s1:
3117   di_MInst_didi_s1_sat            <"vdmpy",   int_hexagon_M2_vdmpys_s1>;
3118 def HEXAGON_M2_vdmpys_s0:
3119   di_MInst_didi_sat               <"vdmpy",   int_hexagon_M2_vdmpys_s0>;
3120 def HEXAGON_M2_vdmacs_s1:
3121   di_MInst_dididi_acc_s1_sat      <"vdmpy",   int_hexagon_M2_vdmacs_s1>;
3122 def HEXAGON_M2_vdmacs_s0:
3123   di_MInst_dididi_acc_sat         <"vdmpy",   int_hexagon_M2_vdmacs_s0>;
3124
3125 // MTYPE / VH / Vector dual multiply with round and pack.
3126 def HEXAGON_M2_vdmpyrs_s0:
3127   si_MInst_didi_rnd_sat           <"vdmpy",   int_hexagon_M2_vdmpyrs_s0>;
3128 def HEXAGON_M2_vdmpyrs_s1:
3129   si_MInst_didi_s1_rnd_sat        <"vdmpy",   int_hexagon_M2_vdmpyrs_s1>;
3130
3131 // MTYPE / VH / Vector multiply even halfwords.
3132 def HEXAGON_M2_vmpy2es_s1:
3133   di_MInst_didi_s1_sat            <"vmpyeh",  int_hexagon_M2_vmpy2es_s1>;
3134 def HEXAGON_M2_vmpy2es_s0:
3135   di_MInst_didi_sat               <"vmpyeh",  int_hexagon_M2_vmpy2es_s0>;
3136 def HEXAGON_M2_vmac2es:
3137   di_MInst_dididi_acc             <"vmpyeh",  int_hexagon_M2_vmac2es>;
3138 def HEXAGON_M2_vmac2es_s1:
3139   di_MInst_dididi_acc_s1_sat      <"vmpyeh",  int_hexagon_M2_vmac2es_s1>;
3140 def HEXAGON_M2_vmac2es_s0:
3141   di_MInst_dididi_acc_sat         <"vmpyeh",  int_hexagon_M2_vmac2es_s0>;
3142
3143 // MTYPE / VH / Vector multiply halfwords.
3144 def HEXAGON_M2_vmpy2s_s0:
3145   di_MInst_sisi_sat               <"vmpyh",   int_hexagon_M2_vmpy2s_s0>;
3146 def HEXAGON_M2_vmpy2s_s1:
3147   di_MInst_sisi_s1_sat            <"vmpyh",   int_hexagon_M2_vmpy2s_s1>;
3148 def HEXAGON_M2_vmac2:
3149   di_MInst_disisi_acc             <"vmpyh",   int_hexagon_M2_vmac2>;
3150 def HEXAGON_M2_vmac2s_s0:
3151   di_MInst_disisi_acc_sat         <"vmpyh",   int_hexagon_M2_vmac2s_s0>;
3152 def HEXAGON_M2_vmac2s_s1:
3153   di_MInst_disisi_acc_s1_sat      <"vmpyh",   int_hexagon_M2_vmac2s_s1>;
3154
3155 // MTYPE / VH / Vector multiply halfwords with round and pack.
3156 def HEXAGON_M2_vmpy2s_s0pack:
3157   si_MInst_sisi_rnd_sat           <"vmpyh",   int_hexagon_M2_vmpy2s_s0pack>;
3158 def HEXAGON_M2_vmpy2s_s1pack:
3159   si_MInst_sisi_s1_rnd_sat        <"vmpyh",   int_hexagon_M2_vmpy2s_s1pack>;
3160
3161 // MTYPE / VH / Vector reduce multiply halfwords.
3162 // Rxx32+=vrmpyh(Rss32,Rtt32)
3163 def HEXAGON_M2_vrmpy_s0:
3164   di_MInst_didi                   <"vrmpyh",  int_hexagon_M2_vrmpy_s0>;
3165 def HEXAGON_M2_vrmac_s0:
3166   di_MInst_dididi_acc             <"vrmpyh",  int_hexagon_M2_vrmac_s0>;
3167
3168 /********************************************************************
3169 *            STYPE/COMPLEX                                          *
3170 *********************************************************************/
3171
3172 // STYPE / COMPLEX / Vector Complex conjugate.
3173 def HEXAGON_A2_vconj:
3174   di_SInst_di_sat                 <"vconj",   int_hexagon_A2_vconj>;
3175
3176 // STYPE / COMPLEX / Vector Complex rotate.
3177 def HEXAGON_S2_vcrotate:
3178   di_SInst_disi                   <"vcrotate",int_hexagon_S2_vcrotate>;
3179
3180
3181 /********************************************************************
3182 *            STYPE/PERM                                             *
3183 *********************************************************************/
3184
3185 // STYPE / PERM / Vector align.
3186 // Need custom lowering
3187 def HEXAGON_S2_valignib:
3188   di_SInst_didiu3                 <"valignb", int_hexagon_S2_valignib>;
3189 def HEXAGON_S2_valignrb:
3190   di_SInst_didiqi                 <"valignb", int_hexagon_S2_valignrb>;
3191
3192 // STYPE / PERM / Vector round and pack.
3193 def HEXAGON_S2_vrndpackwh:
3194   si_SInst_di                     <"vrndwh",  int_hexagon_S2_vrndpackwh>;
3195 def HEXAGON_S2_vrndpackwhs:
3196   si_SInst_di_sat                 <"vrndwh",  int_hexagon_S2_vrndpackwhs>;
3197
3198 // STYPE / PERM / Vector saturate and pack.
3199 def HEXAGON_S2_svsathb:
3200   si_SInst_si                     <"vsathb",  int_hexagon_S2_svsathb>;
3201 def HEXAGON_S2_vsathb:
3202   si_SInst_di                     <"vsathb",  int_hexagon_S2_vsathb>;
3203 def HEXAGON_S2_svsathub:
3204   si_SInst_si                     <"vsathub", int_hexagon_S2_svsathub>;
3205 def HEXAGON_S2_vsathub:
3206   si_SInst_di                     <"vsathub", int_hexagon_S2_vsathub>;
3207 def HEXAGON_S2_vsatwh:
3208   si_SInst_di                     <"vsatwh",  int_hexagon_S2_vsatwh>;
3209 def HEXAGON_S2_vsatwuh:
3210   si_SInst_di                     <"vsatwuh", int_hexagon_S2_vsatwuh>;
3211
3212 // STYPE / PERM / Vector saturate without pack.
3213 def HEXAGON_S2_vsathb_nopack:
3214   di_SInst_di                     <"vsathb",  int_hexagon_S2_vsathb_nopack>;
3215 def HEXAGON_S2_vsathub_nopack:
3216   di_SInst_di                     <"vsathub", int_hexagon_S2_vsathub_nopack>;
3217 def HEXAGON_S2_vsatwh_nopack:
3218   di_SInst_di                     <"vsatwh",  int_hexagon_S2_vsatwh_nopack>;
3219 def HEXAGON_S2_vsatwuh_nopack:
3220   di_SInst_di                     <"vsatwuh", int_hexagon_S2_vsatwuh_nopack>;
3221
3222 // STYPE / PERM / Vector shuffle.
3223 def HEXAGON_S2_shuffeb:
3224   di_SInst_didi                   <"shuffeb", int_hexagon_S2_shuffeb>;
3225 def HEXAGON_S2_shuffeh:
3226   di_SInst_didi                   <"shuffeh", int_hexagon_S2_shuffeh>;
3227 def HEXAGON_S2_shuffob:
3228   di_SInst_didi                   <"shuffob", int_hexagon_S2_shuffob>;
3229 def HEXAGON_S2_shuffoh:
3230   di_SInst_didi                   <"shuffoh", int_hexagon_S2_shuffoh>;
3231
3232 // STYPE / PERM / Vector splat bytes.
3233 def HEXAGON_S2_vsplatrb:
3234   si_SInst_si                     <"vsplatb", int_hexagon_S2_vsplatrb>;
3235
3236 // STYPE / PERM / Vector splat halfwords.
3237 def HEXAGON_S2_vsplatrh:
3238   di_SInst_si                     <"vsplath", int_hexagon_S2_vsplatrh>;
3239
3240 // STYPE / PERM / Vector splice.
3241 def Hexagon_S2_vsplicerb:
3242   di_SInst_didiqi                 <"vspliceb",int_hexagon_S2_vsplicerb>;
3243 def Hexagon_S2_vspliceib:
3244   di_SInst_didiu3                 <"vspliceb",int_hexagon_S2_vspliceib>;
3245
3246 // STYPE / PERM / Sign extend.
3247 def HEXAGON_S2_vsxtbh:
3248   di_SInst_si                     <"vsxtbh",  int_hexagon_S2_vsxtbh>;
3249 def HEXAGON_S2_vsxthw:
3250   di_SInst_si                     <"vsxthw",  int_hexagon_S2_vsxthw>;
3251
3252 // STYPE / PERM / Truncate.
3253 def HEXAGON_S2_vtrunehb:
3254   si_SInst_di                     <"vtrunehb",int_hexagon_S2_vtrunehb>;
3255 def HEXAGON_S2_vtrunohb:
3256   si_SInst_di                     <"vtrunohb",int_hexagon_S2_vtrunohb>;
3257 def HEXAGON_S2_vtrunewh:
3258   di_SInst_didi                   <"vtrunewh",int_hexagon_S2_vtrunewh>;
3259 def HEXAGON_S2_vtrunowh:
3260   di_SInst_didi                   <"vtrunowh",int_hexagon_S2_vtrunowh>;
3261
3262 // STYPE / PERM / Zero extend.
3263 def HEXAGON_S2_vzxtbh:
3264   di_SInst_si                     <"vzxtbh",  int_hexagon_S2_vzxtbh>;
3265 def HEXAGON_S2_vzxthw:
3266   di_SInst_si                     <"vzxthw",  int_hexagon_S2_vzxthw>;
3267
3268
3269 /********************************************************************
3270 *            STYPE/PRED                                             *
3271 *********************************************************************/
3272
3273 // STYPE / PRED / Mask generate from predicate.
3274 def HEXAGON_C2_mask:
3275   di_SInst_qi                     <"mask",   int_hexagon_C2_mask>;
3276
3277 // STYPE / PRED / Predicate transfer.
3278 def HEXAGON_C2_tfrpr:
3279   si_SInst_qi                     <"",       int_hexagon_C2_tfrpr>;
3280 def HEXAGON_C2_tfrrp:
3281   qi_SInst_si                     <"",       int_hexagon_C2_tfrrp>;
3282
3283 // STYPE / PRED / Viterbi pack even and odd predicate bits.
3284 def HEXAGON_C2_vitpack:
3285   si_SInst_qiqi                   <"vitpack",int_hexagon_C2_vitpack>;
3286
3287
3288 /********************************************************************
3289 *            STYPE/VH                                               *
3290 *********************************************************************/
3291
3292 // STYPE / VH / Vector absolute value halfwords.
3293 // Rdd64=vabsh(Rss64)
3294 def HEXAGON_A2_vabsh:
3295   di_SInst_di                     <"vabsh",   int_hexagon_A2_vabsh>;
3296 def HEXAGON_A2_vabshsat:
3297   di_SInst_di_sat                 <"vabsh",   int_hexagon_A2_vabshsat>;
3298
3299 // STYPE / VH / Vector shift halfwords by immediate.
3300 // Rdd64=v[asl/asr/lsr]h(Rss64,Rt32)
3301 def HEXAGON_S2_asl_i_vh:
3302   di_SInst_disi                   <"vaslh",   int_hexagon_S2_asl_i_vh>;
3303 def HEXAGON_S2_asr_i_vh:
3304   di_SInst_disi                   <"vasrh",   int_hexagon_S2_asr_i_vh>;
3305 def HEXAGON_S2_lsr_i_vh:
3306   di_SInst_disi                   <"vlsrh",   int_hexagon_S2_lsr_i_vh>;
3307
3308 // STYPE / VH / Vector shift halfwords by register.
3309 // Rdd64=v[asl/asr/lsl/lsr]w(Rss64,Rt32)
3310 def HEXAGON_S2_asl_r_vh:
3311   di_SInst_disi                   <"vaslh",   int_hexagon_S2_asl_r_vh>;
3312 def HEXAGON_S2_asr_r_vh:
3313   di_SInst_disi                   <"vasrh",   int_hexagon_S2_asr_r_vh>;
3314 def HEXAGON_S2_lsl_r_vh:
3315   di_SInst_disi                   <"vlslh",   int_hexagon_S2_lsl_r_vh>;
3316 def HEXAGON_S2_lsr_r_vh:
3317   di_SInst_disi                   <"vlsrh",   int_hexagon_S2_lsr_r_vh>;
3318
3319
3320 /********************************************************************
3321 *            STYPE/VW                                               *
3322 *********************************************************************/
3323
3324 // STYPE / VW / Vector absolute value words.
3325 def HEXAGON_A2_vabsw:
3326   di_SInst_di                     <"vabsw",   int_hexagon_A2_vabsw>;
3327 def HEXAGON_A2_vabswsat:
3328   di_SInst_di_sat                 <"vabsw",   int_hexagon_A2_vabswsat>;
3329
3330 // STYPE / VW / Vector shift words by immediate.
3331 // Rdd64=v[asl/vsl]w(Rss64,Rt32)
3332 def HEXAGON_S2_asl_i_vw:
3333   di_SInst_disi                   <"vaslw",   int_hexagon_S2_asl_i_vw>;
3334 def HEXAGON_S2_asr_i_vw:
3335   di_SInst_disi                   <"vasrw",   int_hexagon_S2_asr_i_vw>;
3336 def HEXAGON_S2_lsr_i_vw:
3337   di_SInst_disi                   <"vlsrw",   int_hexagon_S2_lsr_i_vw>;
3338
3339 // STYPE / VW / Vector shift words by register.
3340 // Rdd64=v[asl/vsl]w(Rss64,Rt32)
3341 def HEXAGON_S2_asl_r_vw:
3342   di_SInst_disi                   <"vaslw",   int_hexagon_S2_asl_r_vw>;
3343 def HEXAGON_S2_asr_r_vw:
3344   di_SInst_disi                   <"vasrw",   int_hexagon_S2_asr_r_vw>;
3345 def HEXAGON_S2_lsl_r_vw:
3346   di_SInst_disi                   <"vlslw",   int_hexagon_S2_lsl_r_vw>;
3347 def HEXAGON_S2_lsr_r_vw:
3348   di_SInst_disi                   <"vlsrw",   int_hexagon_S2_lsr_r_vw>;
3349
3350 // STYPE / VW / Vector shift words with truncate and pack.
3351 def HEXAGON_S2_asr_r_svw_trun:
3352   si_SInst_disi                   <"vasrw",   int_hexagon_S2_asr_r_svw_trun>;
3353 def HEXAGON_S2_asr_i_svw_trun:
3354   si_SInst_diu5                   <"vasrw",   int_hexagon_S2_asr_i_svw_trun>;
3355
3356 // LD / Circular loads.
3357 def HEXAGON_circ_ldd:
3358   di_LDInstPI_diu4                <"circ_ldd", int_hexagon_circ_ldd>;
3359
3360 include "HexagonIntrinsicsV3.td"
3361 include "HexagonIntrinsicsV4.td"
3362 include "HexagonIntrinsicsV5.td"