1 //===-- HexagonIntrinsics.td - Instruction intrinsics ------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
9 // This is populated based on the following specs:
10 // Hexagon V2 Architecture
11 // Application-Level Specification
14 //===----------------------------------------------------------------------===//
20 class qi_ALU32_sisi<string opc, Intrinsic IntID>
21 : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
22 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
23 [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
25 class qi_ALU32_sis10<string opc, Intrinsic IntID>
26 : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, s10Imm:$src2),
27 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
28 [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
30 class qi_ALU32_sis8<string opc, Intrinsic IntID>
31 : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, s8Imm:$src2),
32 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
33 [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
35 class qi_ALU32_siu8<string opc, Intrinsic IntID>
36 : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, u8Imm:$src2),
37 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
38 [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
40 class qi_ALU32_siu9<string opc, Intrinsic IntID>
41 : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, u9Imm:$src2),
42 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
43 [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
45 class si_ALU32_qisisi<string opc, Intrinsic IntID>
46 : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2,
48 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2, $src3)")),
49 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2,
52 class si_ALU32_qis8si<string opc, Intrinsic IntID>
53 : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, s8Imm:$src2,
55 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2, $src3)")),
56 [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2,
59 class si_ALU32_qisis8<string opc, Intrinsic IntID>
60 : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2,
62 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2, #$src3)")),
63 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2,
66 class si_ALU32_qis8s8<string opc, Intrinsic IntID>
67 : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, s8Imm:$src2, s8Imm:$src3),
68 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2, #$src3)")),
69 [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2, imm:$src3))]>;
71 class si_ALU32_sisi<string opc, Intrinsic IntID>
72 : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
73 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
74 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
76 class si_ALU32_sisi_sat<string opc, Intrinsic IntID>
77 : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
78 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):sat")),
79 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
81 class si_ALU32_sisi_rnd<string opc, Intrinsic IntID>
82 : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
83 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):rnd")),
84 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
86 class si_ALU32_sis16<string opc, Intrinsic IntID>
87 : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, s16Imm:$src2),
88 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
89 [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
91 class si_ALU32_sis10<string opc, Intrinsic IntID>
92 : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, s10Imm:$src2),
93 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
94 [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
96 class si_ALU32_s10si<string opc, Intrinsic IntID>
97 : ALU32_rr<(outs IntRegs:$dst), (ins s10Imm:$src1, IntRegs:$src2),
98 !strconcat("$dst = ", !strconcat(opc , "(#$src1, $src2)")),
99 [(set IntRegs:$dst, (IntID imm:$src1, IntRegs:$src2))]>;
101 class si_lo_ALU32_siu16<string opc, Intrinsic IntID>
102 : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u16Imm:$src2),
103 !strconcat("$dst.l = ", !strconcat(opc , "#$src2")),
104 [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
106 class si_hi_ALU32_siu16<string opc, Intrinsic IntID>
107 : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u16Imm:$src2),
108 !strconcat("$dst.h = ", !strconcat(opc , "#$src2")),
109 [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
111 class si_ALU32_s16<string opc, Intrinsic IntID>
112 : ALU32_rr<(outs IntRegs:$dst), (ins s16Imm:$src1),
113 !strconcat("$dst = ", !strconcat(opc , "#$src1")),
114 [(set IntRegs:$dst, (IntID imm:$src1))]>;
116 class di_ALU32_s8<string opc, Intrinsic IntID>
117 : ALU32_rr<(outs DoubleRegs:$dst), (ins s8Imm:$src1),
118 !strconcat("$dst = ", !strconcat(opc , "#$src1")),
119 [(set DoubleRegs:$dst, (IntID imm:$src1))]>;
121 class di_ALU64_di<string opc, Intrinsic IntID>
122 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src),
123 !strconcat("$dst = ", !strconcat(opc , "$src")),
124 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src))]>;
126 class si_ALU32_si<string opc, Intrinsic IntID>
127 : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src),
128 !strconcat("$dst = ", !strconcat(opc , "($src)")),
129 [(set IntRegs:$dst, (IntID IntRegs:$src))]>;
131 class si_ALU32_si_tfr<string opc, Intrinsic IntID>
132 : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src),
133 !strconcat("$dst = ", !strconcat(opc , "$src")),
134 [(set IntRegs:$dst, (IntID IntRegs:$src))]>;
140 class si_ALU64_si_sat<string opc, Intrinsic IntID>
141 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src),
142 !strconcat("$dst = ", !strconcat(opc , "($src):sat")),
143 [(set IntRegs:$dst, (IntID IntRegs:$src))]>;
145 class si_ALU64_didi<string opc, Intrinsic IntID>
146 : ALU64_rr<(outs IntRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
147 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
148 [(set IntRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
150 class di_ALU64_sidi<string opc, Intrinsic IntID>
151 : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src1, DoubleRegs:$src2),
152 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
153 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, DoubleRegs:$src2))]>;
155 class di_ALU64_didi<string opc, Intrinsic IntID>
156 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
157 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
158 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
159 DoubleRegs:$src2))]>;
161 class di_ALU64_qididi<string opc, Intrinsic IntID>
162 : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src1, DoubleRegs:$src2,
164 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2, $src3)")),
165 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, DoubleRegs:$src2,
166 DoubleRegs:$src3))]>;
168 class di_ALU64_sisi<string opc, Intrinsic IntID>
169 : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
170 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
171 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
173 class di_ALU64_didi_sat<string opc, Intrinsic IntID>
174 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
175 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):sat")),
176 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
177 DoubleRegs:$src2))]>;
179 class di_ALU64_didi_rnd<string opc, Intrinsic IntID>
180 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
181 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):rnd")),
182 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
183 DoubleRegs:$src2))]>;
185 class di_ALU64_didi_crnd<string opc, Intrinsic IntID>
186 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
187 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):crnd")),
188 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
189 DoubleRegs:$src2))]>;
191 class di_ALU64_didi_rnd_sat<string opc, Intrinsic IntID>
192 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
193 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):rnd:sat")),
194 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
195 DoubleRegs:$src2))]>;
197 class di_ALU64_didi_crnd_sat<string opc, Intrinsic IntID>
198 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
199 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):crnd:sat")),
200 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
201 DoubleRegs:$src2))]>;
203 class qi_ALU64_didi<string opc, Intrinsic IntID>
204 : ALU64_rr<(outs PredRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
205 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
206 [(set PredRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
208 class si_ALU64_sisi<string opc, Intrinsic IntID>
209 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
210 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
211 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
213 class si_ALU64_sisi_sat_lh<string opc, Intrinsic IntID>
214 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
215 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H):sat")),
216 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
218 class si_ALU64_sisi_l16_sat_hh<string opc, Intrinsic IntID>
219 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
220 !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.H):sat")),
221 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
223 class si_ALU64_sisi_l16_sat_lh<string opc, Intrinsic IntID>
224 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
225 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H):sat")),
226 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
228 class si_ALU64_sisi_l16_sat_hl<string opc, Intrinsic IntID>
229 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
230 !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.L):sat")),
231 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
233 class si_ALU64_sisi_l16_sat_ll<string opc, Intrinsic IntID>
234 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
235 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L):sat")),
236 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
238 class si_ALU64_sisi_l16_hh<string opc, Intrinsic IntID>
239 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
240 !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.H)")),
241 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
243 class si_ALU64_sisi_l16_hl<string opc, Intrinsic IntID>
244 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
245 !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.L)")),
246 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
248 class si_ALU64_sisi_l16_lh<string opc, Intrinsic IntID>
249 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
250 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H)")),
251 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
253 class si_ALU64_sisi_l16_ll<string opc, Intrinsic IntID>
254 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
255 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L)")),
256 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
258 class si_ALU64_sisi_h16_sat_hh<string opc, Intrinsic IntID>
259 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
260 !strconcat("$dst = ", !strconcat(opc ,
261 "($src1.H, $src2.H):sat:<<16")),
262 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
264 class si_ALU64_sisi_h16_sat_lh<string opc, Intrinsic IntID>
265 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
266 !strconcat("$dst = ", !strconcat(opc ,
267 "($src1.L, $src2.H):sat:<<16")),
268 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
270 class si_ALU64_sisi_h16_sat_hl<string opc, Intrinsic IntID>
271 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
272 !strconcat("$dst = ", !strconcat(opc ,
273 "($src1.H, $src2.L):sat:<<16")),
274 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
276 class si_ALU64_sisi_h16_sat_ll<string opc, Intrinsic IntID>
277 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
278 !strconcat("$dst = ", !strconcat(opc ,
279 "($src1.L, $src2.L):sat:<<16")),
280 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
282 class si_ALU64_sisi_h16_hh<string opc, Intrinsic IntID>
283 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
284 !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.H):<<16")),
285 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
287 class si_ALU64_sisi_h16_hl<string opc, Intrinsic IntID>
288 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
289 !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.L):<<16")),
290 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
292 class si_ALU64_sisi_h16_lh<string opc, Intrinsic IntID>
293 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
294 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H):<<16")),
295 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
297 class si_ALU64_sisi_h16_ll<string opc, Intrinsic IntID>
298 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
299 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L):<<16")),
300 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
302 class si_ALU64_sisi_lh<string opc, Intrinsic IntID>
303 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
304 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H)")),
305 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
307 class si_ALU64_sisi_ll<string opc, Intrinsic IntID>
308 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
309 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L)")),
310 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
312 class si_ALU64_sisi_sat<string opc, Intrinsic IntID>
313 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
314 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):sat")),
315 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
321 class qi_SInst_qi<string opc, Intrinsic IntID>
322 : SInst<(outs PredRegs:$dst), (ins IntRegs:$src),
323 !strconcat("$dst = ", !strconcat(opc , "($src)")),
324 [(set PredRegs:$dst, (IntID IntRegs:$src))]>;
326 class qi_SInst_qi_pxfer<string opc, Intrinsic IntID>
327 : SInst<(outs PredRegs:$dst), (ins IntRegs:$src),
328 !strconcat("$dst = ", !strconcat(opc , "$src")),
329 [(set PredRegs:$dst, (IntID IntRegs:$src))]>;
331 class qi_SInst_qiqi<string opc, Intrinsic IntID>
332 : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
333 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
334 [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
336 class qi_SInst_qiqi_neg<string opc, Intrinsic IntID>
337 : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
338 !strconcat("$dst = ", !strconcat(opc , "($src1, !$src2)")),
339 [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
341 class di_SInst_di<string opc, Intrinsic IntID>
342 : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src),
343 !strconcat("$dst = ", !strconcat(opc , "($src)")),
344 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src))]>;
346 class di_SInst_di_sat<string opc, Intrinsic IntID>
347 : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src),
348 !strconcat("$dst = ", !strconcat(opc , "($src):sat")),
349 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src))]>;
351 class si_SInst_di<string opc, Intrinsic IntID>
352 : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src),
353 !strconcat("$dst = ", !strconcat(opc , "($src)")),
354 [(set IntRegs:$dst, (IntID DoubleRegs:$src))]>;
356 class si_SInst_di_sat<string opc, Intrinsic IntID>
357 : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src),
358 !strconcat("$dst = ", !strconcat(opc , "($src):sat")),
359 [(set IntRegs:$dst, (IntID DoubleRegs:$src))]>;
361 class di_SInst_disi<string opc, Intrinsic IntID>
362 : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
363 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
364 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, IntRegs:$src2))]>;
366 class di_SInst_didi<string opc, Intrinsic IntID>
367 : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
368 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
369 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
371 class di_SInst_si<string opc, Intrinsic IntID>
372 : SInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1),
373 !strconcat("$dst = ", !strconcat(opc , "($src1)")),
374 [(set DoubleRegs:$dst, (IntID IntRegs:$src1))]>;
376 class si_SInst_sisiu3<string opc, Intrinsic IntID>
377 : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2, u3Imm:$src3),
378 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2, #$src3)")),
379 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2,
382 class si_SInst_diu5<string opc, Intrinsic IntID>
383 : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, u5Imm:$src2),
384 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
385 [(set IntRegs:$dst, (IntID DoubleRegs:$src1, imm:$src2))]>;
387 class si_SInst_disi<string opc, Intrinsic IntID>
388 : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
389 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
390 [(set IntRegs:$dst, (IntID DoubleRegs:$src1, IntRegs:$src2))]>;
392 class si_SInst_sidi<string opc, Intrinsic IntID>
393 : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, DoubleRegs:$src2),
394 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
395 [(set IntRegs:$dst, (IntID IntRegs:$src1, DoubleRegs:$src2))]>;
397 class di_SInst_disisi<string opc, Intrinsic IntID>
398 : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2,
400 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2, $src3)")),
401 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, IntRegs:$src2,
404 class di_SInst_sisi<string opc, Intrinsic IntID>
405 : SInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
406 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
407 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
409 class qi_SInst_siu5<string opc, Intrinsic IntID>
410 : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
411 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
412 [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
414 class qi_SInst_siu6<string opc, Intrinsic IntID>
415 : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, u6Imm:$src2),
416 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
417 [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
419 class qi_SInst_sisi<string opc, Intrinsic IntID>
420 : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
421 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
422 [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
424 class si_SInst_si<string opc, Intrinsic IntID>
425 : SInst<(outs IntRegs:$dst), (ins IntRegs:$src),
426 !strconcat("$dst = ", !strconcat(opc , "($src)")),
427 [(set IntRegs:$dst, (IntID IntRegs:$src))]>;
429 class si_SInst_si_sat<string opc, Intrinsic IntID>
430 : SInst<(outs IntRegs:$dst), (ins IntRegs:$src),
431 !strconcat("$dst = ", !strconcat(opc , "($src):sat")),
432 [(set IntRegs:$dst, (IntID IntRegs:$src))]>;
434 class di_SInst_qi<string opc, Intrinsic IntID>
435 : SInst<(outs DoubleRegs:$dst), (ins IntRegs:$src),
436 !strconcat("$dst = ", !strconcat(opc , "($src)")),
437 [(set DoubleRegs:$dst, (IntID IntRegs:$src))]>;
439 class si_SInst_qi<string opc, Intrinsic IntID>
440 : SInst<(outs IntRegs:$dst), (ins IntRegs:$src),
441 !strconcat("$dst = ", !strconcat(opc , "$src")),
442 [(set IntRegs:$dst, (IntID IntRegs:$src))]>;
444 class si_SInst_qiqi<string opc, Intrinsic IntID>
445 : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
446 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
447 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
449 class qi_SInst_si<string opc, Intrinsic IntID>
450 : SInst<(outs PredRegs:$dst), (ins IntRegs:$src),
451 !strconcat("$dst = ", !strconcat(opc , "$src")),
452 [(set PredRegs:$dst, (IntID IntRegs:$src))]>;
454 class si_SInst_sisi<string opc, Intrinsic IntID>
455 : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
456 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
457 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
459 class di_SInst_diu6<string opc, Intrinsic IntID>
460 : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u6Imm:$src2),
461 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
462 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, imm:$src2))]>;
464 class si_SInst_siu5<string opc, Intrinsic IntID>
465 : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
466 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
467 [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
469 class si_SInst_siu5_rnd<string opc, Intrinsic IntID>
470 : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
471 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2):rnd")),
472 [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
474 class si_SInst_siu5u5<string opc, Intrinsic IntID>
475 : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2, u5Imm:$src3),
476 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2, #$src3)")),
477 [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2, imm:$src3))]>;
479 class si_SInst_sisisi_acc<string opc, Intrinsic IntID>
480 : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
482 !strconcat("$dst += ", !strconcat(opc , "($src1, $src2)")),
483 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
487 class si_SInst_sisisi_nac<string opc, Intrinsic IntID>
488 : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
490 !strconcat("$dst -= ", !strconcat(opc , "($src1, $src2)")),
491 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
495 class di_SInst_didisi_acc<string opc, Intrinsic IntID>
496 : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
498 !strconcat("$dst += ", !strconcat(opc , "($src1, $src2)")),
499 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
504 class di_SInst_didisi_nac<string opc, Intrinsic IntID>
505 : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
507 !strconcat("$dst -= ", !strconcat(opc , "($src1, $src2)")),
508 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
509 DoubleRegs:$src1, IntRegs:$src2))],
512 class si_SInst_sisiu5u5<string opc, Intrinsic IntID>
513 : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
514 u5Imm:$src2, u5Imm:$src3),
515 !strconcat("$dst = ", !strconcat(opc ,
516 "($src1, #$src2, #$src3)")),
517 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
518 imm:$src2, imm:$src3))],
521 class si_SInst_sisidi<string opc, Intrinsic IntID>
522 : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
524 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
525 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
529 class di_SInst_didiu6u6<string opc, Intrinsic IntID>
530 : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
531 u6Imm:$src2, u6Imm:$src3),
532 !strconcat("$dst = ", !strconcat(opc ,
533 "($src1, #$src2, #$src3)")),
534 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, DoubleRegs:$src1,
535 imm:$src2, imm:$src3))],
538 class di_SInst_dididi<string opc, Intrinsic IntID>
539 : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
541 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
542 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
547 class di_SInst_diu6u6<string opc, Intrinsic IntID>
548 : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u6Imm:$src2,
550 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2, #$src3)")),
551 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, imm:$src2,
554 class di_SInst_didiqi<string opc, Intrinsic IntID>
555 : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2,
557 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2, $src3)")),
558 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2,
561 class di_SInst_didiu3<string opc, Intrinsic IntID>
562 : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2,
564 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2, #$src3)")),
565 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2,
568 class di_SInst_didisi_or<string opc, Intrinsic IntID>
569 : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
571 !strconcat("$dst |= ", !strconcat(opc , "($src1, $src2)")),
572 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, DoubleRegs:$src1,
576 class di_SInst_didisi_and<string opc, Intrinsic IntID>
577 : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
579 !strconcat("$dst &= ", !strconcat(opc , "($src1, $src2)")),
580 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, DoubleRegs:$src1,
584 class di_SInst_didiu6_and<string opc, Intrinsic IntID>
585 : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
587 !strconcat("$dst &= ", !strconcat(opc , "($src1, #$src2)")),
588 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, DoubleRegs:$src1,
592 class di_SInst_didiu6_or<string opc, Intrinsic IntID>
593 : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
595 !strconcat("$dst |= ", !strconcat(opc , "($src1, #$src2)")),
596 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, DoubleRegs:$src1,
600 class di_SInst_didiu6_xor<string opc, Intrinsic IntID>
601 : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
603 !strconcat("$dst ^= ", !strconcat(opc , "($src1, #$src2)")),
604 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, DoubleRegs:$src1,
608 class si_SInst_sisisi_and<string opc, Intrinsic IntID>
609 : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
611 !strconcat("$dst &= ", !strconcat(opc , "($src1, $src2)")),
612 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
616 class si_SInst_sisisi_or<string opc, Intrinsic IntID>
617 : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
619 !strconcat("$dst |= ", !strconcat(opc , "($src1, $src2)")),
620 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
625 class si_SInst_sisiu5_and<string opc, Intrinsic IntID>
626 : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
628 !strconcat("$dst &= ", !strconcat(opc , "($src1, #$src2)")),
629 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
633 class si_SInst_sisiu5_or<string opc, Intrinsic IntID>
634 : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
636 !strconcat("$dst |= ", !strconcat(opc , "($src1, #$src2)")),
637 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
641 class si_SInst_sisiu5_xor<string opc, Intrinsic IntID>
642 : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
644 !strconcat("$dst ^= ", !strconcat(opc , "($src1, #$src2)")),
645 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
649 class si_SInst_sisiu5_acc<string opc, Intrinsic IntID>
650 : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
652 !strconcat("$dst += ", !strconcat(opc , "($src1, #$src2)")),
653 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
657 class si_SInst_sisiu5_nac<string opc, Intrinsic IntID>
658 : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
660 !strconcat("$dst -= ", !strconcat(opc , "($src1, #$src2)")),
661 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
665 class di_SInst_didiu6_acc<string opc, Intrinsic IntID>
666 : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
668 !strconcat("$dst += ", !strconcat(opc , "($src1, #$src2)")),
669 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
670 DoubleRegs:$src1, imm:$src2))],
673 class di_SInst_didiu6_nac<string opc, Intrinsic IntID>
674 : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
676 !strconcat("$dst -= ", !strconcat(opc , "($src1, #$src2)")),
677 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, DoubleRegs:$src1,
686 class di_MInst_sisi_rnd_hh_s1<string opc, Intrinsic IntID>
687 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
688 !strconcat("$dst = ", !strconcat(opc ,
689 "($src1.H, $src2.H):<<1:rnd")),
690 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
692 class di_MInst_sisi_rnd_hh<string opc, Intrinsic IntID>
693 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
694 !strconcat("$dst = ", !strconcat(opc ,
695 "($src1.H, $src2.H):rnd")),
696 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
698 class di_MInst_sisi_rnd_hl_s1<string opc, Intrinsic IntID>
699 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
700 !strconcat("$dst = ", !strconcat(opc ,
701 "($src1.H, $src2.L):<<1:rnd")),
702 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
704 class di_MInst_sisi_rnd_hl<string opc, Intrinsic IntID>
705 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
706 !strconcat("$dst = ", !strconcat(opc ,
707 "($src1.H, $src2.L):rnd")),
708 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
710 class di_MInst_sisi_rnd_lh_s1<string opc, Intrinsic IntID>
711 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
712 !strconcat("$dst = ", !strconcat(opc ,
713 "($src1.L, $src2.H):<<1:rnd")),
714 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
716 class di_MInst_sisi_rnd_lh<string opc, Intrinsic IntID>
717 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
718 !strconcat("$dst = ", !strconcat(opc ,
719 "($src1.L, $src2.H):rnd")),
720 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
722 class di_MInst_sisi_rnd_ll_s1<string opc, Intrinsic IntID>
723 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
724 !strconcat("$dst = ", !strconcat(opc ,
725 "($src1.L, $src2.L):<<1:rnd")),
726 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
728 class di_MInst_sisi_rnd_ll<string opc, Intrinsic IntID>
729 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
730 !strconcat("$dst = ", !strconcat(opc ,
731 "($src1.L, $src2.L):rnd")),
732 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
734 class di_MInst_disisi_acc<string opc, Intrinsic IntID>
735 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
737 !strconcat("$dst += ", !strconcat(opc , "($src1, $src2)")),
738 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
742 class di_MInst_disisi_nac<string opc, Intrinsic IntID>
743 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
745 !strconcat("$dst -= ", !strconcat(opc , "($src1, $src2)")),
746 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
750 class di_MInst_disisi_acc_sat<string opc, Intrinsic IntID>
751 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
753 !strconcat("$dst += ", !strconcat(opc , "($src1, $src2):sat")),
754 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
758 class di_MInst_disisi_nac_sat<string opc, Intrinsic IntID>
759 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
761 !strconcat("$dst -= ", !strconcat(opc , "($src1, $src2):sat")),
762 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
766 class di_MInst_disisi_acc_sat_conj<string opc, Intrinsic IntID>
767 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
769 !strconcat("$dst += ", !strconcat(opc , "($src1, $src2*):sat")),
770 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
774 class di_MInst_disisi_nac_sat_conj<string opc, Intrinsic IntID>
775 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
777 !strconcat("$dst -= ", !strconcat(opc , "($src1, $src2*):sat")),
778 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
782 class di_MInst_disisi_nac_s1_sat<string opc, Intrinsic IntID>
783 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
785 !strconcat("$dst -= ", !strconcat(opc ,
786 "($src1, $src2):<<1:sat")),
787 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
791 class di_MInst_disisi_acc_s1_sat_conj<string opc, Intrinsic IntID>
792 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
794 !strconcat("$dst += ", !strconcat(opc ,
795 "($src1, $src2*):<<1:sat")),
796 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
800 class di_MInst_disisi_nac_s1_sat_conj<string opc, Intrinsic IntID>
801 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
803 !strconcat("$dst -= ", !strconcat(opc ,
804 "($src1, $src2*):<<1:sat")),
805 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
809 class di_MInst_s8s8<string opc, Intrinsic IntID>
810 : MInst<(outs DoubleRegs:$dst), (ins s8Imm:$src1, s8Imm:$src2),
811 !strconcat("$dst = ", !strconcat(opc , "(#$src1, #$src2)")),
812 [(set DoubleRegs:$dst, (IntID imm:$src1, imm:$src2))]>;
814 class si_MInst_sisi<string opc, Intrinsic IntID>
815 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
816 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
817 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
819 class di_MInst_sisi_hh<string opc, Intrinsic IntID>
820 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
821 !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.H)")),
822 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
824 class di_MInst_sisi_hh_s1<string opc, Intrinsic IntID>
825 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
826 !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.H):<<1")),
827 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
829 class di_MInst_sisi_lh<string opc, Intrinsic IntID>
830 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
831 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H)")),
832 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
834 class di_MInst_sisi_lh_s1<string opc, Intrinsic IntID>
835 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
836 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H):<<1")),
837 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
839 class di_MInst_sisi_hl<string opc, Intrinsic IntID>
840 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
841 !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.L)")),
842 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
844 class di_MInst_sisi_hl_s1<string opc, Intrinsic IntID>
845 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
846 !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.L):<<1")),
847 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
849 class di_MInst_sisi_ll<string opc, Intrinsic IntID>
850 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
851 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L)")),
852 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
854 class di_MInst_sisi_ll_s1<string opc, Intrinsic IntID>
855 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
856 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L):<<1")),
857 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
860 class si_MInst_sisi_hh<string opc, Intrinsic IntID>
861 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
862 !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.H)")),
863 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
865 class si_MInst_sisi_hh_s1<string opc, Intrinsic IntID>
866 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
867 !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.H):<<1")),
868 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
870 class si_MInst_sisi_lh<string opc, Intrinsic IntID>
871 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
872 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H)")),
873 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
875 class si_MInst_sisi_lh_s1<string opc, Intrinsic IntID>
876 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
877 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H):<<1")),
878 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
880 class si_MInst_sisi_hl<string opc, Intrinsic IntID>
881 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
882 !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.L)")),
883 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
885 class si_MInst_sisi_hl_s1<string opc, Intrinsic IntID>
886 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
887 !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.L):<<1")),
888 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
890 class si_MInst_sisi_ll<string opc, Intrinsic IntID>
891 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
892 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L)")),
893 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
895 class si_MInst_sisi_ll_s1<string opc, Intrinsic IntID>
896 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
897 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L):<<1")),
898 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
900 class si_MInst_sisi_up<string opc, Intrinsic IntID>
901 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
902 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
903 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
905 class di_MInst_didi<string opc, Intrinsic IntID>
906 : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
907 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
908 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
909 DoubleRegs:$src2))]>;
911 class di_MInst_didi_conj<string opc, Intrinsic IntID>
912 : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
913 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2*)")),
914 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
915 DoubleRegs:$src2))]>;
917 class di_MInst_sisi_s1_sat_conj<string opc, Intrinsic IntID>
918 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
919 !strconcat("$dst = ", !strconcat(opc ,
920 "($src1, $src2*):<<1:sat")),
921 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
923 class di_MInst_didi_s1_rnd_sat<string opc, Intrinsic IntID>
924 : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
925 !strconcat("$dst = ", !strconcat(opc ,
926 "($src1, $src2):<<1:rnd:sat")),
927 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
928 DoubleRegs:$src2))]>;
930 class di_MInst_didi_sat<string opc, Intrinsic IntID>
931 : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
932 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):sat")),
933 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
934 DoubleRegs:$src2))]>;
936 class di_MInst_didi_rnd_sat<string opc, Intrinsic IntID>
937 : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
938 !strconcat("$dst = ", !strconcat(opc ,
939 "($src1, $src2):rnd:sat")),
940 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
941 DoubleRegs:$src2))]>;
943 class si_SInst_sisi_sat<string opc, Intrinsic IntID>
944 : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
945 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):sat")),
946 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
948 class si_SInst_didi_sat<string opc, Intrinsic IntID>
949 : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
950 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):sat")),
951 [(set IntRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
953 class si_SInst_disi_s1_rnd_sat<string opc, Intrinsic IntID>
954 : MInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
955 !strconcat("$dst = ", !strconcat(opc ,
956 "($src1, $src2):<<1:rnd:sat")),
957 [(set IntRegs:$dst, (IntID DoubleRegs:$src1, IntRegs:$src2))]>;
959 class si_MInst_sisi_s1_rnd_sat<string opc, Intrinsic IntID>
960 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
961 !strconcat("$dst = ", !strconcat(opc ,
962 "($src1, $src2):<<1:rnd:sat")),
963 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
965 class si_MInst_sisi_l_s1_rnd_sat<string opc, Intrinsic IntID>
966 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
967 !strconcat("$dst = ", !strconcat(opc ,
968 "($src1, $src2.L):<<1:rnd:sat")),
969 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
971 class si_MInst_sisi_h_s1_rnd_sat<string opc, Intrinsic IntID>
972 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
973 !strconcat("$dst = ", !strconcat(opc ,
974 "($src1, $src2.H):<<1:rnd:sat")),
975 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
977 class si_MInst_sisi_rnd_sat_conj<string opc, Intrinsic IntID>
978 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
979 !strconcat("$dst = ", !strconcat(opc ,
980 "($src1, $src2*):rnd:sat")),
981 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
983 class si_MInst_sisi_s1_rnd_sat_conj<string opc, Intrinsic IntID>
984 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
985 !strconcat("$dst = ", !strconcat(opc ,
986 "($src1, $src2*):<<1:rnd:sat")),
987 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
989 class si_MInst_sisi_rnd_sat<string opc, Intrinsic IntID>
990 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
991 !strconcat("$dst = ", !strconcat(opc ,
992 "($src1, $src2):rnd:sat")),
993 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
995 class si_MInst_sisi_rnd<string opc, Intrinsic IntID>
996 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
997 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):rnd")),
998 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1000 class si_MInst_sisisi_xacc<string opc, Intrinsic IntID>
1001 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src2,
1003 !strconcat("$dst ^= ", !strconcat(opc , "($src2, $src3)")),
1004 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src2,
1008 class si_MInst_sisisi_acc<string opc, Intrinsic IntID>
1009 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src2,
1011 !strconcat("$dst += ", !strconcat(opc , "($src2, $src3)")),
1012 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src2,
1016 class si_MInst_sisisi_nac<string opc, Intrinsic IntID>
1017 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src2,
1019 !strconcat("$dst -= ", !strconcat(opc , "($src2, $src3)")),
1020 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src2,
1024 class si_MInst_sisis8_acc<string opc, Intrinsic IntID>
1025 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src2,
1027 !strconcat("$dst += ", !strconcat(opc , "($src2, #$src3)")),
1028 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src2,
1032 class si_MInst_sisis8_nac<string opc, Intrinsic IntID>
1033 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src2,
1035 !strconcat("$dst -= ", !strconcat(opc , "($src2, #$src3)")),
1036 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src2,
1040 class si_MInst_sisiu4u5<string opc, Intrinsic IntID>
1041 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1042 u4Imm:$src2, u5Imm:$src3),
1043 !strconcat("$dst = ", !strconcat(opc ,
1044 "($src1, #$src2, #$src3)")),
1045 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1046 imm:$src2, imm:$src3))],
1049 class si_MInst_sisiu8_acc<string opc, Intrinsic IntID>
1050 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src2,
1052 !strconcat("$dst += ", !strconcat(opc , "($src2, #$src3)")),
1053 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src2,
1057 class si_MInst_sisiu8_nac<string opc, Intrinsic IntID>
1058 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src2,
1060 !strconcat("$dst -= ", !strconcat(opc , "($src2, #$src3)")),
1061 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src2,
1065 class si_MInst_sisisi_acc_hh<string opc, Intrinsic IntID>
1066 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1068 !strconcat("$dst += ", !strconcat(opc , "($src1.H, $src2.H)")),
1069 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1073 class si_MInst_sisisi_acc_sat_lh<string opc, Intrinsic IntID>
1074 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1076 !strconcat("$dst += ", !strconcat(opc ,
1077 "($src1.L, $src2.H):sat")),
1078 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1082 class si_MInst_sisisi_acc_sat_lh_s1<string opc, Intrinsic IntID>
1083 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1085 !strconcat("$dst += ", !strconcat(opc ,
1086 "($src1.L, $src2.H):<<1:sat")),
1087 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1091 class si_MInst_sisisi_acc_sat_hh<string opc, Intrinsic IntID>
1092 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1094 !strconcat("$dst += ", !strconcat(opc ,
1095 "($src1.H, $src2.H):sat")),
1096 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1100 class si_MInst_sisisi_acc_sat_hh_s1<string opc, Intrinsic IntID>
1101 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1103 !strconcat("$dst += ", !strconcat(opc ,
1104 "($src1.H, $src2.H):<<1:sat")),
1105 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1109 class si_MInst_sisisi_acc_hh_s1<string opc, Intrinsic IntID>
1110 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1112 !strconcat("$dst += ", !strconcat(opc ,
1113 "($src1.H, $src2.H):<<1")),
1114 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1118 class si_MInst_sisisi_nac_hh<string opc, Intrinsic IntID>
1119 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1121 !strconcat("$dst -= ", !strconcat(opc , "($src1.H, $src2.H)")),
1122 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1126 class si_MInst_sisisi_nac_sat_hh_s1<string opc, Intrinsic IntID>
1127 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1129 !strconcat("$dst -= ", !strconcat(opc ,
1130 "($src1.H, $src2.H):<<1:sat")),
1131 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1135 class si_MInst_sisisi_nac_sat_hh<string opc, Intrinsic IntID>
1136 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1138 !strconcat("$dst -= ", !strconcat(opc ,
1139 "($src1.H, $src2.H):sat")),
1140 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1144 class si_MInst_sisisi_nac_sat_hl_s1<string opc, Intrinsic IntID>
1145 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1147 !strconcat("$dst -= ", !strconcat(opc ,
1148 "($src1.H, $src2.L):<<1:sat")),
1149 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1153 class si_MInst_sisisi_nac_sat_hl<string opc, Intrinsic IntID>
1154 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1156 !strconcat("$dst -= ", !strconcat(opc ,
1157 "($src1.H, $src2.L):sat")),
1158 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1162 class si_MInst_sisisi_nac_sat_lh_s1<string opc, Intrinsic IntID>
1163 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1165 !strconcat("$dst -= ", !strconcat(opc ,
1166 "($src1.L, $src2.H):<<1:sat")),
1167 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1171 class si_MInst_sisisi_nac_sat_lh<string opc, Intrinsic IntID>
1172 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1174 !strconcat("$dst -= ", !strconcat(opc ,
1175 "($src1.L, $src2.H):sat")),
1176 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1180 class si_MInst_sisisi_nac_sat_ll_s1<string opc, Intrinsic IntID>
1181 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1183 !strconcat("$dst -= ", !strconcat(opc ,
1184 "($src1.L, $src2.L):<<1:sat")),
1185 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1189 class si_MInst_sisisi_nac_sat_ll<string opc, Intrinsic IntID>
1190 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1192 !strconcat("$dst -= ", !strconcat(opc ,
1193 "($src1.L, $src2.L):sat")),
1194 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1198 class si_MInst_sisisi_nac_hh_s1<string opc, Intrinsic IntID>
1199 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1201 !strconcat("$dst -= ", !strconcat(opc ,
1202 "($src1.H, $src2.H):<<1")),
1203 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1207 class si_MInst_sisisi_acc_hl<string opc, Intrinsic IntID>
1208 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1210 !strconcat("$dst += ", !strconcat(opc , "($src1.H, $src2.L)")),
1211 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1215 class si_MInst_sisisi_acc_hl_s1<string opc, Intrinsic IntID>
1216 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1218 !strconcat("$dst += ", !strconcat(opc ,
1219 "($src1.H, $src2.L):<<1")),
1220 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1224 class si_MInst_sisisi_nac_hl<string opc, Intrinsic IntID>
1225 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1227 !strconcat("$dst -= ", !strconcat(opc , "($src1.H, $src2.L)")),
1228 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1232 class si_MInst_sisisi_nac_hl_s1<string opc, Intrinsic IntID>
1233 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1235 !strconcat("$dst -= ", !strconcat(opc ,
1236 "($src1.H, $src2.L):<<1")),
1237 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1241 class si_MInst_sisisi_acc_lh<string opc, Intrinsic IntID>
1242 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1244 !strconcat("$dst += ", !strconcat(opc , "($src1.L, $src2.H)")),
1245 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1249 class si_MInst_sisisi_acc_lh_s1<string opc, Intrinsic IntID>
1250 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1252 !strconcat("$dst += ", !strconcat(opc ,
1253 "($src1.L, $src2.H):<<1")),
1254 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1258 class si_MInst_sisisi_nac_lh<string opc, Intrinsic IntID>
1259 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1261 !strconcat("$dst -= ", !strconcat(opc , "($src1.L, $src2.H)")),
1262 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1266 class si_MInst_sisisi_nac_lh_s1<string opc, Intrinsic IntID>
1267 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1269 !strconcat("$dst -= ", !strconcat(opc ,
1270 "($src1.L, $src2.H):<<1")),
1271 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1275 class si_MInst_sisisi_acc_ll<string opc, Intrinsic IntID>
1276 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1278 !strconcat("$dst += ", !strconcat(opc , "($src1.L, $src2.L)")),
1279 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1283 class si_MInst_sisisi_acc_ll_s1<string opc, Intrinsic IntID>
1284 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1286 !strconcat("$dst += ", !strconcat(opc ,
1287 "($src1.L, $src2.L):<<1")),
1288 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1292 class si_MInst_sisisi_acc_sat_ll_s1<string opc, Intrinsic IntID>
1293 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1295 !strconcat("$dst += ", !strconcat(opc ,
1296 "($src1.L, $src2.L):<<1:sat")),
1297 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1301 class si_MInst_sisisi_acc_sat_hl_s1<string opc, Intrinsic IntID>
1302 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1304 !strconcat("$dst += ", !strconcat(opc ,
1305 "($src1.H, $src2.L):<<1:sat")),
1306 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1310 class si_MInst_sisisi_acc_sat_ll<string opc, Intrinsic IntID>
1311 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1313 !strconcat("$dst += ", !strconcat(opc ,
1314 "($src1.L, $src2.L):sat")),
1315 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1319 class si_MInst_sisisi_acc_sat_hl<string opc, Intrinsic IntID>
1320 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1322 !strconcat("$dst += ", !strconcat(opc ,
1323 "($src1.H, $src2.L):sat")),
1324 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1328 class si_MInst_sisisi_nac_ll<string opc, Intrinsic IntID>
1329 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1331 !strconcat("$dst -= ", !strconcat(opc , "($src1.L, $src2.L)")),
1332 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1336 class si_MInst_sisisi_nac_ll_s1<string opc, Intrinsic IntID>
1337 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1339 !strconcat("$dst -= ", !strconcat(opc ,
1340 "($src1.L, $src2.L):<<1")),
1341 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1345 class si_MInst_sisisi_nac_hh_sat<string opc, Intrinsic IntID>
1346 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1348 !strconcat("$dst -= ", !strconcat(opc ,
1349 "($src1.H, $src2.H):sat")),
1350 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1354 class si_MInst_sisisi_nac_hh_s1_sat<string opc, Intrinsic IntID>
1355 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1357 !strconcat("$dst -= ", !strconcat(opc ,
1358 "($src1.H, $src2.H):<<1:sat")),
1359 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1363 class si_MInst_sisisi_nac_hl_sat<string opc, Intrinsic IntID>
1364 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1366 !strconcat("$dst -= ", !strconcat(opc ,
1367 "($src1.H, $src2.L):sat")),
1368 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1372 class si_MInst_sisisi_nac_hl_s1_sat<string opc, Intrinsic IntID>
1373 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1375 !strconcat("$dst -= ", !strconcat(opc ,
1376 "($src1.H, $src2.L):<<1:sat")),
1377 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1381 class si_MInst_sisisi_nac_lh_sat<string opc, Intrinsic IntID>
1382 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1384 !strconcat("$dst -= ", !strconcat(opc ,
1385 "($src1.L, $src2.H):sat")),
1386 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1390 class si_MInst_sisisi_nac_lh_s1_sat<string opc, Intrinsic IntID>
1391 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1393 !strconcat("$dst -= ", !strconcat(opc ,
1394 "($src1.L, $src2.H):<<1:sat")),
1395 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1399 class si_MInst_sisisi_nac_ll_sat<string opc, Intrinsic IntID>
1400 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1402 !strconcat("$dst -= ", !strconcat(opc ,
1403 "($src1.L, $src2.L):sat")),
1404 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1408 class si_MInst_sisisi_nac_ll_s1_sat<string opc, Intrinsic IntID>
1409 : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1411 !strconcat("$dst -= ", !strconcat(opc ,
1412 "($src1.L, $src2.L):<<1:sat")),
1413 [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1417 class di_ALU32_sisi<string opc, Intrinsic IntID>
1418 : ALU32_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1419 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
1420 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1422 class di_MInst_sisi<string opc, Intrinsic IntID>
1423 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1424 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
1425 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1427 class di_MInst_sisi_sat<string opc, Intrinsic IntID>
1428 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1429 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):sat")),
1430 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1432 class di_MInst_sisi_sat_conj<string opc, Intrinsic IntID>
1433 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1434 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2*):sat")),
1435 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1437 class di_MInst_sisi_s1_sat<string opc, Intrinsic IntID>
1438 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1439 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):<<1:sat")),
1440 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1442 class di_MInst_didi_s1_sat<string opc, Intrinsic IntID>
1443 : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1444 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):<<1:sat")),
1445 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
1446 DoubleRegs:$src2))]>;
1448 class si_MInst_didi_s1_rnd_sat<string opc, Intrinsic IntID>
1449 : MInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1450 !strconcat("$dst = ", !strconcat(opc ,
1451 "($src1, $src2):<<1:rnd:sat")),
1452 [(set IntRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
1454 class si_MInst_didi_rnd_sat<string opc, Intrinsic IntID>
1455 : MInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1456 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):rnd:sat")),
1457 [(set IntRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
1459 class si_MInst_sisi_sat_hh<string opc, Intrinsic IntID>
1460 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1461 !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.H):sat")),
1462 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1464 class si_MInst_sisi_sat_hh_s1<string opc, Intrinsic IntID>
1465 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1466 !strconcat("$dst = ", !strconcat(opc ,
1467 "($src1.H, $src2.H):<<1:sat")),
1468 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1470 class si_MInst_sisi_sat_hl<string opc, Intrinsic IntID>
1471 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1472 !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.L):sat")),
1473 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1475 class si_MInst_sisi_sat_hl_s1<string opc, Intrinsic IntID>
1476 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1477 !strconcat("$dst = ", !strconcat(opc ,
1478 "($src1.H, $src2.L):<<1:sat")),
1479 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1481 class si_MInst_sisi_sat_lh<string opc, Intrinsic IntID>
1482 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1483 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H):sat")),
1484 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1486 class si_MInst_sisi_sat_lh_s1<string opc, Intrinsic IntID>
1487 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1488 !strconcat("$dst = ", !strconcat(opc ,
1489 "($src1.L, $src2.H):<<1:sat")),
1490 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1492 class si_MInst_sisi_sat_ll<string opc, Intrinsic IntID>
1493 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1494 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L):sat")),
1495 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1497 class si_MInst_sisi_sat_ll_s1<string opc, Intrinsic IntID>
1498 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1499 !strconcat("$dst = ", !strconcat(opc ,
1500 "($src1.L, $src2.L):<<1:sat")),
1501 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1503 class si_MInst_sisi_sat_rnd_hh<string opc, Intrinsic IntID>
1504 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1505 !strconcat("$dst = ", !strconcat(opc ,
1506 "($src1.H, $src2.H):rnd:sat")),
1507 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1509 class si_MInst_sisi_rnd_hh<string opc, Intrinsic IntID>
1510 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1511 !strconcat("$dst = ", !strconcat(opc ,
1512 "($src1.H, $src2.H):rnd")),
1513 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1515 class si_MInst_sisi_rnd_hh_s1<string opc, Intrinsic IntID>
1516 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1517 !strconcat("$dst = ", !strconcat(opc ,
1518 "($src1.H, $src2.H):<<1:rnd")),
1519 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1521 class si_MInst_sisi_sat_rnd_hh_s1<string opc, Intrinsic IntID>
1522 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1523 !strconcat("$dst = ",
1525 "($src1.H, $src2.H):<<1:rnd:sat")),
1526 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1528 class si_MInst_sisi_rnd_hl<string opc, Intrinsic IntID>
1529 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1530 !strconcat("$dst = ",
1531 !strconcat(opc , "($src1.H, $src2.L):rnd")),
1532 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1534 class si_MInst_sisi_rnd_hl_s1<string opc, Intrinsic IntID>
1535 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1536 !strconcat("$dst = ",
1537 !strconcat(opc , "($src1.H, $src2.L):<<1:rnd")),
1538 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1540 class si_MInst_sisi_sat_rnd_hl<string opc, Intrinsic IntID>
1541 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1542 !strconcat("$dst = ",
1543 !strconcat(opc , "($src1.H, $src2.L):rnd:sat")),
1544 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1546 class si_MInst_sisi_sat_rnd_hl_s1<string opc, Intrinsic IntID>
1547 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1548 !strconcat("$dst = ",
1549 !strconcat(opc , "($src1.H, $src2.L):<<1:rnd:sat")),
1550 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1552 class si_MInst_sisi_rnd_lh<string opc, Intrinsic IntID>
1553 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1554 !strconcat("$dst = ",
1555 !strconcat(opc , "($src1.L, $src2.H):rnd")),
1556 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1558 class si_MInst_sisi_sat_rnd_lh<string opc, Intrinsic IntID>
1559 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1560 !strconcat("$dst = ",
1561 !strconcat(opc , "($src1.L, $src2.H):rnd:sat")),
1562 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1564 class si_MInst_sisi_sat_rnd_lh_s1<string opc, Intrinsic IntID>
1565 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1566 !strconcat("$dst = ",
1567 !strconcat(opc , "($src1.L, $src2.H):<<1:rnd:sat")),
1568 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1570 class si_MInst_sisi_rnd_lh_s1<string opc, Intrinsic IntID>
1571 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1572 !strconcat("$dst = ",
1573 !strconcat(opc , "($src1.L, $src2.H):<<1:rnd")),
1574 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1576 class si_MInst_sisi_sat_rnd_ll<string opc, Intrinsic IntID>
1577 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1578 !strconcat("$dst = ",
1579 !strconcat(opc , "($src1.L, $src2.L):rnd:sat")),
1580 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1582 class si_MInst_sisi_sat_rnd_ll_s1<string opc, Intrinsic IntID>
1583 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1584 !strconcat("$dst = ",
1585 !strconcat(opc , "($src1.L, $src2.L):<<1:rnd:sat")),
1586 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1588 class si_MInst_sisi_rnd_ll<string opc, Intrinsic IntID>
1589 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1590 !strconcat("$dst = ",
1591 !strconcat(opc , "($src1.L, $src2.L):rnd")),
1592 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1594 class si_MInst_sisi_rnd_ll_s1<string opc, Intrinsic IntID>
1595 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1596 !strconcat("$dst = ",
1597 !strconcat(opc , "($src1.L, $src2.L):<<1:rnd")),
1598 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1600 class di_MInst_dididi_acc_sat<string opc, Intrinsic IntID>
1601 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2,
1602 DoubleRegs:$src1, DoubleRegs:$src2),
1603 !strconcat("$dst += ", !strconcat(opc , "($src1, $src2):sat")),
1604 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
1606 DoubleRegs:$src2))],
1609 class di_MInst_dididi_acc_rnd_sat<string opc, Intrinsic IntID>
1610 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
1612 !strconcat("$dst += ",
1613 !strconcat(opc , "($src1, $src2):rnd:sat")),
1614 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
1616 DoubleRegs:$src2))],
1619 class di_MInst_dididi_acc_s1<string opc, Intrinsic IntID>
1620 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2,
1623 !strconcat("$dst += ",
1624 !strconcat(opc , "($src1, $src2):<<1")),
1625 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
1627 DoubleRegs:$src2))],
1631 class di_MInst_dididi_acc_s1_sat<string opc, Intrinsic IntID>
1632 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2,
1635 !strconcat("$dst += ",
1636 !strconcat(opc , "($src1, $src2):<<1:sat")),
1637 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
1639 DoubleRegs:$src2))],
1642 class di_MInst_dididi_acc_s1_rnd_sat<string opc, Intrinsic IntID>
1643 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
1645 !strconcat("$dst += ",
1646 !strconcat(opc , "($src1, $src2):<<1:rnd:sat")),
1647 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
1649 DoubleRegs:$src2))],
1652 class di_MInst_dididi_acc<string opc, Intrinsic IntID>
1653 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
1655 !strconcat("$dst += ", !strconcat(opc , "($src1, $src2)")),
1656 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
1658 DoubleRegs:$src2))],
1661 class di_MInst_dididi_acc_conj<string opc, Intrinsic IntID>
1662 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
1664 !strconcat("$dst += ", !strconcat(opc , "($src1, $src2*)")),
1665 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
1667 DoubleRegs:$src2))],
1670 class di_MInst_disisi_acc_hh<string opc, Intrinsic IntID>
1671 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1673 !strconcat("$dst += ", !strconcat(opc , "($src1.H, $src2.H)")),
1674 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1678 class di_MInst_disisi_acc_hl<string opc, Intrinsic IntID>
1679 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1681 !strconcat("$dst += ", !strconcat(opc , "($src1.H, $src2.L)")),
1682 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1686 class di_MInst_disisi_acc_lh<string opc, Intrinsic IntID>
1687 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1689 !strconcat("$dst += ", !strconcat(opc , "($src1.L, $src2.H)")),
1690 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1694 class di_MInst_disisi_acc_ll<string opc, Intrinsic IntID>
1695 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1697 !strconcat("$dst += ", !strconcat(opc , "($src1.L, $src2.L)")),
1698 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1702 class di_MInst_disisi_acc_hh_s1<string opc, Intrinsic IntID>
1703 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1705 !strconcat("$dst += ",
1706 !strconcat(opc , "($src1.H, $src2.H):<<1")),
1707 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1711 class di_MInst_disisi_acc_hl_s1<string opc, Intrinsic IntID>
1712 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1714 !strconcat("$dst += ",
1715 !strconcat(opc , "($src1.H, $src2.L):<<1")),
1716 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1720 class di_MInst_disisi_acc_lh_s1<string opc, Intrinsic IntID>
1721 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1723 !strconcat("$dst += ",
1724 !strconcat(opc , "($src1.L, $src2.H):<<1")),
1725 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1729 class di_MInst_disisi_acc_ll_s1<string opc, Intrinsic IntID>
1730 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1732 !strconcat("$dst += ",
1733 !strconcat(opc , "($src1.L, $src2.L):<<1")),
1734 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1738 class di_MInst_disisi_nac_hh<string opc, Intrinsic IntID>
1739 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1741 !strconcat("$dst -= ", !strconcat(opc , "($src1.H, $src2.H)")),
1742 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1746 class di_MInst_disisi_nac_hl<string opc, Intrinsic IntID>
1747 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1749 !strconcat("$dst -= ", !strconcat(opc , "($src1.H, $src2.L)")),
1750 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1754 class di_MInst_disisi_nac_lh<string opc, Intrinsic IntID>
1755 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1757 !strconcat("$dst -= ", !strconcat(opc , "($src1.L, $src2.H)")),
1758 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1762 class di_MInst_disisi_nac_ll<string opc, Intrinsic IntID>
1763 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1765 !strconcat("$dst -= ", !strconcat(opc , "($src1.L, $src2.L)")),
1766 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1770 class di_MInst_disisi_nac_hh_s1<string opc, Intrinsic IntID>
1771 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1773 !strconcat("$dst -= ",
1774 !strconcat(opc , "($src1.H, $src2.H):<<1")),
1775 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1779 class di_MInst_disisi_nac_hl_s1<string opc, Intrinsic IntID>
1780 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1782 !strconcat("$dst -= ",
1783 !strconcat(opc , "($src1.H, $src2.L):<<1")),
1784 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1788 class di_MInst_disisi_nac_lh_s1<string opc, Intrinsic IntID>
1789 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1791 !strconcat("$dst -= ",
1792 !strconcat(opc , "($src1.L, $src2.H):<<1")),
1793 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1797 class di_MInst_disisi_nac_ll_s1<string opc, Intrinsic IntID>
1798 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1800 !strconcat("$dst -= ",
1801 !strconcat(opc , "($src1.L, $src2.L):<<1")),
1802 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1806 class di_MInst_disisi_acc_s1_sat<string opc, Intrinsic IntID>
1807 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1809 !strconcat("$dst += ",
1810 !strconcat(opc , "($src1, $src2):<<1:sat")),
1811 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1815 class di_MInst_disi_s1_sat<string opc, Intrinsic IntID>
1816 : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
1817 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):<<1:sat")),
1818 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, IntRegs:$src2))]>;
1820 class di_MInst_didisi_acc_s1_sat<string opc, Intrinsic IntID>
1821 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
1823 !strconcat("$dst += ",
1824 !strconcat(opc , "($src1, $src2):<<1:sat")),
1825 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
1830 class si_MInst_disi_s1_rnd_sat<string opc, Intrinsic IntID>
1831 : MInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
1832 !strconcat("$dst = ",
1833 !strconcat(opc , "($src1, $src2):<<1:rnd:sat")),
1834 [(set IntRegs:$dst, (IntID DoubleRegs:$src1, IntRegs:$src2))]>;
1836 class si_MInst_didi<string opc, Intrinsic IntID>
1837 : MInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1838 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
1839 [(set IntRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
1844 let mayLoad = 1, neverHasSideEffects = 1 in
1845 class di_LDInstPI_diu4<string opc, Intrinsic IntID>
1846 : LDInstPI<(outs IntRegs:$dst, DoubleRegs:$dst2),
1847 (ins IntRegs:$src1, IntRegs:$src2, CRRegs:$src3, s4Imm:$offset),
1848 "$dst2 = memd($src1++#$offset:circ($src3))",
1852 /********************************************************************
1854 *********************************************************************/
1856 // ALU32 / ALU / Add.
1858 si_ALU32_sisi <"add", int_hexagon_A2_add>;
1859 def HEXAGON_A2_addi:
1860 si_ALU32_sis16 <"add", int_hexagon_A2_addi>;
1862 // ALU32 / ALU / Logical operations.
1864 si_ALU32_sisi <"and", int_hexagon_A2_and>;
1865 def HEXAGON_A2_andir:
1866 si_ALU32_sis10 <"and", int_hexagon_A2_andir>;
1868 si_ALU32_si <"not", int_hexagon_A2_not>;
1870 si_ALU32_sisi <"or", int_hexagon_A2_or>;
1871 def HEXAGON_A2_orir:
1872 si_ALU32_sis10 <"or", int_hexagon_A2_orir>;
1874 si_ALU32_sisi <"xor", int_hexagon_A2_xor>;
1876 // ALU32 / ALU / Negate.
1878 si_ALU32_si <"neg", int_hexagon_A2_neg>;
1880 // ALU32 / ALU / Subtract.
1882 si_ALU32_sisi <"sub", int_hexagon_A2_sub>;
1883 def HEXAGON_A2_subri:
1884 si_ALU32_s10si <"sub", int_hexagon_A2_subri>;
1886 // ALU32 / ALU / Transfer Immediate.
1887 def HEXAGON_A2_tfril:
1888 si_lo_ALU32_siu16 <"", int_hexagon_A2_tfril>;
1889 def HEXAGON_A2_tfrih:
1890 si_hi_ALU32_siu16 <"", int_hexagon_A2_tfrih>;
1891 def HEXAGON_A2_tfrsi:
1892 si_ALU32_s16 <"", int_hexagon_A2_tfrsi>;
1893 def HEXAGON_A2_tfrpi:
1894 di_ALU32_s8 <"", int_hexagon_A2_tfrpi>;
1896 // ALU32 / ALU / Transfer Register.
1898 si_ALU32_si_tfr <"", int_hexagon_A2_tfr>;
1900 /********************************************************************
1902 *********************************************************************/
1904 // ALU32 / PERM / Combine.
1905 def HEXAGON_A2_combinew:
1906 di_ALU32_sisi <"combine", int_hexagon_A2_combinew>;
1907 def HEXAGON_A2_combine_hh:
1908 si_MInst_sisi_hh <"combine", int_hexagon_A2_combine_hh>;
1909 def HEXAGON_A2_combine_lh:
1910 si_MInst_sisi_lh <"combine", int_hexagon_A2_combine_lh>;
1911 def HEXAGON_A2_combine_hl:
1912 si_MInst_sisi_hl <"combine", int_hexagon_A2_combine_hl>;
1913 def HEXAGON_A2_combine_ll:
1914 si_MInst_sisi_ll <"combine", int_hexagon_A2_combine_ll>;
1915 def HEXAGON_A2_combineii:
1916 di_MInst_s8s8 <"combine", int_hexagon_A2_combineii>;
1918 // ALU32 / PERM / Mux.
1920 si_ALU32_qisisi <"mux", int_hexagon_C2_mux>;
1921 def HEXAGON_C2_muxri:
1922 si_ALU32_qis8si <"mux", int_hexagon_C2_muxri>;
1923 def HEXAGON_C2_muxir:
1924 si_ALU32_qisis8 <"mux", int_hexagon_C2_muxir>;
1925 def HEXAGON_C2_muxii:
1926 si_ALU32_qis8s8 <"mux", int_hexagon_C2_muxii>;
1928 // ALU32 / PERM / Shift halfword.
1929 def HEXAGON_A2_aslh:
1930 si_ALU32_si <"aslh", int_hexagon_A2_aslh>;
1931 def HEXAGON_A2_asrh:
1932 si_ALU32_si <"asrh", int_hexagon_A2_asrh>;
1933 def SI_to_SXTHI_asrh:
1934 si_ALU32_si <"asrh", int_hexagon_SI_to_SXTHI_asrh>;
1936 // ALU32 / PERM / Sign/zero extend.
1937 def HEXAGON_A2_sxth:
1938 si_ALU32_si <"sxth", int_hexagon_A2_sxth>;
1939 def HEXAGON_A2_sxtb:
1940 si_ALU32_si <"sxtb", int_hexagon_A2_sxtb>;
1941 def HEXAGON_A2_zxth:
1942 si_ALU32_si <"zxth", int_hexagon_A2_zxth>;
1943 def HEXAGON_A2_zxtb:
1944 si_ALU32_si <"zxtb", int_hexagon_A2_zxtb>;
1946 /********************************************************************
1948 *********************************************************************/
1950 // ALU32 / PRED / Compare.
1951 def HEXAGON_C2_cmpeq:
1952 qi_ALU32_sisi <"cmp.eq", int_hexagon_C2_cmpeq>;
1953 def HEXAGON_C2_cmpeqi:
1954 qi_ALU32_sis10 <"cmp.eq", int_hexagon_C2_cmpeqi>;
1955 def HEXAGON_C2_cmpgei:
1956 qi_ALU32_sis8 <"cmp.ge", int_hexagon_C2_cmpgei>;
1957 def HEXAGON_C2_cmpgeui:
1958 qi_ALU32_siu8 <"cmp.geu", int_hexagon_C2_cmpgeui>;
1959 def HEXAGON_C2_cmpgt:
1960 qi_ALU32_sisi <"cmp.gt", int_hexagon_C2_cmpgt>;
1961 def HEXAGON_C2_cmpgti:
1962 qi_ALU32_sis10 <"cmp.gt", int_hexagon_C2_cmpgti>;
1963 def HEXAGON_C2_cmpgtu:
1964 qi_ALU32_sisi <"cmp.gtu", int_hexagon_C2_cmpgtu>;
1965 def HEXAGON_C2_cmpgtui:
1966 qi_ALU32_siu9 <"cmp.gtu", int_hexagon_C2_cmpgtui>;
1967 def HEXAGON_C2_cmplt:
1968 qi_ALU32_sisi <"cmp.lt", int_hexagon_C2_cmplt>;
1969 def HEXAGON_C2_cmpltu:
1970 qi_ALU32_sisi <"cmp.ltu", int_hexagon_C2_cmpltu>;
1972 /********************************************************************
1974 *********************************************************************/
1976 // ALU32 / VH / Vector add halfwords.
1977 // Rd32=vadd[u]h(Rs32,Rt32:sat]
1978 def HEXAGON_A2_svaddh:
1979 si_ALU32_sisi <"vaddh", int_hexagon_A2_svaddh>;
1980 def HEXAGON_A2_svaddhs:
1981 si_ALU32_sisi_sat <"vaddh", int_hexagon_A2_svaddhs>;
1982 def HEXAGON_A2_svadduhs:
1983 si_ALU32_sisi_sat <"vadduh", int_hexagon_A2_svadduhs>;
1985 // ALU32 / VH / Vector average halfwords.
1986 def HEXAGON_A2_svavgh:
1987 si_ALU32_sisi <"vavgh", int_hexagon_A2_svavgh>;
1988 def HEXAGON_A2_svavghs:
1989 si_ALU32_sisi_rnd <"vavgh", int_hexagon_A2_svavghs>;
1990 def HEXAGON_A2_svnavgh:
1991 si_ALU32_sisi <"vnavgh", int_hexagon_A2_svnavgh>;
1993 // ALU32 / VH / Vector subtract halfwords.
1994 def HEXAGON_A2_svsubh:
1995 si_ALU32_sisi <"vsubh", int_hexagon_A2_svsubh>;
1996 def HEXAGON_A2_svsubhs:
1997 si_ALU32_sisi_sat <"vsubh", int_hexagon_A2_svsubhs>;
1998 def HEXAGON_A2_svsubuhs:
1999 si_ALU32_sisi_sat <"vsubuh", int_hexagon_A2_svsubuhs>;
2001 /********************************************************************
2003 *********************************************************************/
2005 // ALU64 / ALU / Add.
2006 def HEXAGON_A2_addp:
2007 di_ALU64_didi <"add", int_hexagon_A2_addp>;
2008 def HEXAGON_A2_addsat:
2009 si_ALU64_sisi_sat <"add", int_hexagon_A2_addsat>;
2011 // ALU64 / ALU / Add halfword.
2012 // Even though the definition says hl, it should be lh -
2013 //so DON'T change the class " si_ALU64_sisi_l16_lh " it inherits.
2014 def HEXAGON_A2_addh_l16_hl:
2015 si_ALU64_sisi_l16_lh <"add", int_hexagon_A2_addh_l16_hl>;
2016 def HEXAGON_A2_addh_l16_ll:
2017 si_ALU64_sisi_l16_ll <"add", int_hexagon_A2_addh_l16_ll>;
2019 def HEXAGON_A2_addh_l16_sat_hl:
2020 si_ALU64_sisi_l16_sat_lh <"add", int_hexagon_A2_addh_l16_sat_hl>;
2021 def HEXAGON_A2_addh_l16_sat_ll:
2022 si_ALU64_sisi_l16_sat_ll <"add", int_hexagon_A2_addh_l16_sat_ll>;
2024 def HEXAGON_A2_addh_h16_hh:
2025 si_ALU64_sisi_h16_hh <"add", int_hexagon_A2_addh_h16_hh>;
2026 def HEXAGON_A2_addh_h16_hl:
2027 si_ALU64_sisi_h16_hl <"add", int_hexagon_A2_addh_h16_hl>;
2028 def HEXAGON_A2_addh_h16_lh:
2029 si_ALU64_sisi_h16_lh <"add", int_hexagon_A2_addh_h16_lh>;
2030 def HEXAGON_A2_addh_h16_ll:
2031 si_ALU64_sisi_h16_ll <"add", int_hexagon_A2_addh_h16_ll>;
2033 def HEXAGON_A2_addh_h16_sat_hh:
2034 si_ALU64_sisi_h16_sat_hh <"add", int_hexagon_A2_addh_h16_sat_hh>;
2035 def HEXAGON_A2_addh_h16_sat_hl:
2036 si_ALU64_sisi_h16_sat_hl <"add", int_hexagon_A2_addh_h16_sat_hl>;
2037 def HEXAGON_A2_addh_h16_sat_lh:
2038 si_ALU64_sisi_h16_sat_lh <"add", int_hexagon_A2_addh_h16_sat_lh>;
2039 def HEXAGON_A2_addh_h16_sat_ll:
2040 si_ALU64_sisi_h16_sat_ll <"add", int_hexagon_A2_addh_h16_sat_ll>;
2042 // ALU64 / ALU / Compare.
2043 def HEXAGON_C2_cmpeqp:
2044 qi_ALU64_didi <"cmp.eq", int_hexagon_C2_cmpeqp>;
2045 def HEXAGON_C2_cmpgtp:
2046 qi_ALU64_didi <"cmp.gt", int_hexagon_C2_cmpgtp>;
2047 def HEXAGON_C2_cmpgtup:
2048 qi_ALU64_didi <"cmp.gtu", int_hexagon_C2_cmpgtup>;
2050 // ALU64 / ALU / Logical operations.
2051 def HEXAGON_A2_andp:
2052 di_ALU64_didi <"and", int_hexagon_A2_andp>;
2054 di_ALU64_didi <"or", int_hexagon_A2_orp>;
2055 def HEXAGON_A2_xorp:
2056 di_ALU64_didi <"xor", int_hexagon_A2_xorp>;
2058 // ALU64 / ALU / Maximum.
2060 si_ALU64_sisi <"max", int_hexagon_A2_max>;
2061 def HEXAGON_A2_maxu:
2062 si_ALU64_sisi <"maxu", int_hexagon_A2_maxu>;
2064 // ALU64 / ALU / Minimum.
2066 si_ALU64_sisi <"min", int_hexagon_A2_min>;
2067 def HEXAGON_A2_minu:
2068 si_ALU64_sisi <"minu", int_hexagon_A2_minu>;
2070 // ALU64 / ALU / Subtract.
2071 def HEXAGON_A2_subp:
2072 di_ALU64_didi <"sub", int_hexagon_A2_subp>;
2073 def HEXAGON_A2_subsat:
2074 si_ALU64_sisi_sat <"sub", int_hexagon_A2_subsat>;
2076 // ALU64 / ALU / Subtract halfword.
2077 // Even though the definition says hl, it should be lh -
2078 //so DON'T change the class " si_ALU64_sisi_l16_lh " it inherits.
2079 def HEXAGON_A2_subh_l16_hl:
2080 si_ALU64_sisi_l16_lh <"sub", int_hexagon_A2_subh_l16_hl>;
2081 def HEXAGON_A2_subh_l16_ll:
2082 si_ALU64_sisi_l16_ll <"sub", int_hexagon_A2_subh_l16_ll>;
2084 def HEXAGON_A2_subh_l16_sat_hl:
2085 si_ALU64_sisi_l16_sat_lh <"sub", int_hexagon_A2_subh_l16_sat_hl>;
2086 def HEXAGON_A2_subh_l16_sat_ll:
2087 si_ALU64_sisi_l16_sat_ll <"sub", int_hexagon_A2_subh_l16_sat_ll>;
2089 def HEXAGON_A2_subh_h16_hh:
2090 si_ALU64_sisi_h16_hh <"sub", int_hexagon_A2_subh_h16_hh>;
2091 def HEXAGON_A2_subh_h16_hl:
2092 si_ALU64_sisi_h16_hl <"sub", int_hexagon_A2_subh_h16_hl>;
2093 def HEXAGON_A2_subh_h16_lh:
2094 si_ALU64_sisi_h16_lh <"sub", int_hexagon_A2_subh_h16_lh>;
2095 def HEXAGON_A2_subh_h16_ll:
2096 si_ALU64_sisi_h16_ll <"sub", int_hexagon_A2_subh_h16_ll>;
2098 def HEXAGON_A2_subh_h16_sat_hh:
2099 si_ALU64_sisi_h16_sat_hh <"sub", int_hexagon_A2_subh_h16_sat_hh>;
2100 def HEXAGON_A2_subh_h16_sat_hl:
2101 si_ALU64_sisi_h16_sat_hl <"sub", int_hexagon_A2_subh_h16_sat_hl>;
2102 def HEXAGON_A2_subh_h16_sat_lh:
2103 si_ALU64_sisi_h16_sat_lh <"sub", int_hexagon_A2_subh_h16_sat_lh>;
2104 def HEXAGON_A2_subh_h16_sat_ll:
2105 si_ALU64_sisi_h16_sat_ll <"sub", int_hexagon_A2_subh_h16_sat_ll>;
2107 // ALU64 / ALU / Transfer register.
2108 def HEXAGON_A2_tfrp:
2109 di_ALU64_di <"", int_hexagon_A2_tfrp>;
2111 /********************************************************************
2113 *********************************************************************/
2115 // ALU64 / BIT / Masked parity.
2116 def HEXAGON_S2_parityp:
2117 si_ALU64_didi <"parity", int_hexagon_S2_parityp>;
2119 /********************************************************************
2121 *********************************************************************/
2123 // ALU64 / PERM / Vector pack high and low halfwords.
2124 def HEXAGON_S2_packhl:
2125 di_ALU64_sisi <"packhl", int_hexagon_S2_packhl>;
2127 /********************************************************************
2129 *********************************************************************/
2131 // ALU64 / VB / Vector add unsigned bytes.
2132 def HEXAGON_A2_vaddub:
2133 di_ALU64_didi <"vaddub", int_hexagon_A2_vaddub>;
2134 def HEXAGON_A2_vaddubs:
2135 di_ALU64_didi_sat <"vaddub", int_hexagon_A2_vaddubs>;
2137 // ALU64 / VB / Vector average unsigned bytes.
2138 def HEXAGON_A2_vavgub:
2139 di_ALU64_didi <"vavgub", int_hexagon_A2_vavgub>;
2140 def HEXAGON_A2_vavgubr:
2141 di_ALU64_didi_rnd <"vavgub", int_hexagon_A2_vavgubr>;
2143 // ALU64 / VB / Vector compare unsigned bytes.
2144 def HEXAGON_A2_vcmpbeq:
2145 qi_ALU64_didi <"vcmpb.eq", int_hexagon_A2_vcmpbeq>;
2146 def HEXAGON_A2_vcmpbgtu:
2147 qi_ALU64_didi <"vcmpb.gtu",int_hexagon_A2_vcmpbgtu>;
2149 // ALU64 / VB / Vector maximum/minimum unsigned bytes.
2150 def HEXAGON_A2_vmaxub:
2151 di_ALU64_didi <"vmaxub", int_hexagon_A2_vmaxub>;
2152 def HEXAGON_A2_vminub:
2153 di_ALU64_didi <"vminub", int_hexagon_A2_vminub>;
2155 // ALU64 / VB / Vector subtract unsigned bytes.
2156 def HEXAGON_A2_vsubub:
2157 di_ALU64_didi <"vsubub", int_hexagon_A2_vsubub>;
2158 def HEXAGON_A2_vsububs:
2159 di_ALU64_didi_sat <"vsubub", int_hexagon_A2_vsububs>;
2161 // ALU64 / VB / Vector mux.
2162 def HEXAGON_C2_vmux:
2163 di_ALU64_qididi <"vmux", int_hexagon_C2_vmux>;
2166 /********************************************************************
2168 *********************************************************************/
2170 // ALU64 / VH / Vector add halfwords.
2171 // Rdd64=vadd[u]h(Rss64,Rtt64:sat]
2172 def HEXAGON_A2_vaddh:
2173 di_ALU64_didi <"vaddh", int_hexagon_A2_vaddh>;
2174 def HEXAGON_A2_vaddhs:
2175 di_ALU64_didi_sat <"vaddh", int_hexagon_A2_vaddhs>;
2176 def HEXAGON_A2_vadduhs:
2177 di_ALU64_didi_sat <"vadduh", int_hexagon_A2_vadduhs>;
2179 // ALU64 / VH / Vector average halfwords.
2180 // Rdd64=v[n]avg[u]h(Rss64,Rtt64:rnd/:crnd][:sat]
2181 def HEXAGON_A2_vavgh:
2182 di_ALU64_didi <"vavgh", int_hexagon_A2_vavgh>;
2183 def HEXAGON_A2_vavghcr:
2184 di_ALU64_didi_crnd <"vavgh", int_hexagon_A2_vavghcr>;
2185 def HEXAGON_A2_vavghr:
2186 di_ALU64_didi_rnd <"vavgh", int_hexagon_A2_vavghr>;
2187 def HEXAGON_A2_vavguh:
2188 di_ALU64_didi <"vavguh", int_hexagon_A2_vavguh>;
2189 def HEXAGON_A2_vavguhr:
2190 di_ALU64_didi_rnd <"vavguh", int_hexagon_A2_vavguhr>;
2191 def HEXAGON_A2_vnavgh:
2192 di_ALU64_didi <"vnavgh", int_hexagon_A2_vnavgh>;
2193 def HEXAGON_A2_vnavghcr:
2194 di_ALU64_didi_crnd_sat <"vnavgh", int_hexagon_A2_vnavghcr>;
2195 def HEXAGON_A2_vnavghr:
2196 di_ALU64_didi_rnd_sat <"vnavgh", int_hexagon_A2_vnavghr>;
2198 // ALU64 / VH / Vector compare halfwords.
2199 def HEXAGON_A2_vcmpheq:
2200 qi_ALU64_didi <"vcmph.eq", int_hexagon_A2_vcmpheq>;
2201 def HEXAGON_A2_vcmphgt:
2202 qi_ALU64_didi <"vcmph.gt", int_hexagon_A2_vcmphgt>;
2203 def HEXAGON_A2_vcmphgtu:
2204 qi_ALU64_didi <"vcmph.gtu",int_hexagon_A2_vcmphgtu>;
2206 // ALU64 / VH / Vector maximum halfwords.
2207 def HEXAGON_A2_vmaxh:
2208 di_ALU64_didi <"vmaxh", int_hexagon_A2_vmaxh>;
2209 def HEXAGON_A2_vmaxuh:
2210 di_ALU64_didi <"vmaxuh", int_hexagon_A2_vmaxuh>;
2212 // ALU64 / VH / Vector minimum halfwords.
2213 def HEXAGON_A2_vminh:
2214 di_ALU64_didi <"vminh", int_hexagon_A2_vminh>;
2215 def HEXAGON_A2_vminuh:
2216 di_ALU64_didi <"vminuh", int_hexagon_A2_vminuh>;
2218 // ALU64 / VH / Vector subtract halfwords.
2219 def HEXAGON_A2_vsubh:
2220 di_ALU64_didi <"vsubh", int_hexagon_A2_vsubh>;
2221 def HEXAGON_A2_vsubhs:
2222 di_ALU64_didi_sat <"vsubh", int_hexagon_A2_vsubhs>;
2223 def HEXAGON_A2_vsubuhs:
2224 di_ALU64_didi_sat <"vsubuh", int_hexagon_A2_vsubuhs>;
2227 /********************************************************************
2229 *********************************************************************/
2231 // ALU64 / VW / Vector add words.
2232 // Rdd32=vaddw(Rss32,Rtt32)[:sat]
2233 def HEXAGON_A2_vaddw:
2234 di_ALU64_didi <"vaddw", int_hexagon_A2_vaddw>;
2235 def HEXAGON_A2_vaddws:
2236 di_ALU64_didi_sat <"vaddw", int_hexagon_A2_vaddws>;
2238 // ALU64 / VW / Vector average words.
2239 def HEXAGON_A2_vavguw:
2240 di_ALU64_didi <"vavguw", int_hexagon_A2_vavguw>;
2241 def HEXAGON_A2_vavguwr:
2242 di_ALU64_didi_rnd <"vavguw", int_hexagon_A2_vavguwr>;
2243 def HEXAGON_A2_vavgw:
2244 di_ALU64_didi <"vavgw", int_hexagon_A2_vavgw>;
2245 def HEXAGON_A2_vavgwcr:
2246 di_ALU64_didi_crnd <"vavgw", int_hexagon_A2_vavgwcr>;
2247 def HEXAGON_A2_vavgwr:
2248 di_ALU64_didi_rnd <"vavgw", int_hexagon_A2_vavgwr>;
2249 def HEXAGON_A2_vnavgw:
2250 di_ALU64_didi <"vnavgw", int_hexagon_A2_vnavgw>;
2251 def HEXAGON_A2_vnavgwcr:
2252 di_ALU64_didi_crnd_sat <"vnavgw", int_hexagon_A2_vnavgwcr>;
2253 def HEXAGON_A2_vnavgwr:
2254 di_ALU64_didi_rnd_sat <"vnavgw", int_hexagon_A2_vnavgwr>;
2256 // ALU64 / VW / Vector compare words.
2257 def HEXAGON_A2_vcmpweq:
2258 qi_ALU64_didi <"vcmpw.eq", int_hexagon_A2_vcmpweq>;
2259 def HEXAGON_A2_vcmpwgt:
2260 qi_ALU64_didi <"vcmpw.gt", int_hexagon_A2_vcmpwgt>;
2261 def HEXAGON_A2_vcmpwgtu:
2262 qi_ALU64_didi <"vcmpw.gtu",int_hexagon_A2_vcmpwgtu>;
2264 // ALU64 / VW / Vector maximum words.
2265 def HEXAGON_A2_vmaxw:
2266 di_ALU64_didi <"vmaxw", int_hexagon_A2_vmaxw>;
2267 def HEXAGON_A2_vmaxuw:
2268 di_ALU64_didi <"vmaxuw", int_hexagon_A2_vmaxuw>;
2270 // ALU64 / VW / Vector minimum words.
2271 def HEXAGON_A2_vminw:
2272 di_ALU64_didi <"vminw", int_hexagon_A2_vminw>;
2273 def HEXAGON_A2_vminuw:
2274 di_ALU64_didi <"vminuw", int_hexagon_A2_vminuw>;
2276 // ALU64 / VW / Vector subtract words.
2277 def HEXAGON_A2_vsubw:
2278 di_ALU64_didi <"vsubw", int_hexagon_A2_vsubw>;
2279 def HEXAGON_A2_vsubws:
2280 di_ALU64_didi_sat <"vsubw", int_hexagon_A2_vsubws>;
2283 /********************************************************************
2285 *********************************************************************/
2287 // CR / Logical reductions on predicates.
2288 def HEXAGON_C2_all8:
2289 qi_SInst_qi <"all8", int_hexagon_C2_all8>;
2290 def HEXAGON_C2_any8:
2291 qi_SInst_qi <"any8", int_hexagon_C2_any8>;
2293 // CR / Logical operations on predicates.
2294 def HEXAGON_C2_pxfer_map:
2295 qi_SInst_qi_pxfer <"", int_hexagon_C2_pxfer_map>;
2297 qi_SInst_qiqi <"and", int_hexagon_C2_and>;
2298 def HEXAGON_C2_andn:
2299 qi_SInst_qiqi_neg <"and", int_hexagon_C2_andn>;
2301 qi_SInst_qi <"not", int_hexagon_C2_not>;
2303 qi_SInst_qiqi <"or", int_hexagon_C2_or>;
2305 qi_SInst_qiqi_neg <"or", int_hexagon_C2_orn>;
2307 qi_SInst_qiqi <"xor", int_hexagon_C2_xor>;
2310 /********************************************************************
2312 *********************************************************************/
2314 // MTYPE / ALU / Add and accumulate.
2315 def HEXAGON_M2_acci:
2316 si_MInst_sisisi_acc <"add", int_hexagon_M2_acci>;
2317 def HEXAGON_M2_accii:
2318 si_MInst_sisis8_acc <"add", int_hexagon_M2_accii>;
2319 def HEXAGON_M2_nacci:
2320 si_MInst_sisisi_nac <"add", int_hexagon_M2_nacci>;
2321 def HEXAGON_M2_naccii:
2322 si_MInst_sisis8_nac <"add", int_hexagon_M2_naccii>;
2324 // MTYPE / ALU / Subtract and accumulate.
2325 def HEXAGON_M2_subacc:
2326 si_MInst_sisisi_acc <"sub", int_hexagon_M2_subacc>;
2328 // MTYPE / ALU / Vector absolute difference.
2329 def HEXAGON_M2_vabsdiffh:
2330 di_MInst_didi <"vabsdiffh",int_hexagon_M2_vabsdiffh>;
2331 def HEXAGON_M2_vabsdiffw:
2332 di_MInst_didi <"vabsdiffw",int_hexagon_M2_vabsdiffw>;
2334 // MTYPE / ALU / XOR and xor with destination.
2335 def HEXAGON_M2_xor_xacc:
2336 si_MInst_sisisi_xacc <"xor", int_hexagon_M2_xor_xacc>;
2339 /********************************************************************
2341 *********************************************************************/
2343 // MTYPE / COMPLEX / Complex multiply.
2344 // Rdd[-+]=cmpy(Rs, Rt:<<1]:sat
2345 def HEXAGON_M2_cmpys_s1:
2346 di_MInst_sisi_s1_sat <"cmpy", int_hexagon_M2_cmpys_s1>;
2347 def HEXAGON_M2_cmpys_s0:
2348 di_MInst_sisi_sat <"cmpy", int_hexagon_M2_cmpys_s0>;
2349 def HEXAGON_M2_cmpysc_s1:
2350 di_MInst_sisi_s1_sat_conj <"cmpy", int_hexagon_M2_cmpysc_s1>;
2351 def HEXAGON_M2_cmpysc_s0:
2352 di_MInst_sisi_sat_conj <"cmpy", int_hexagon_M2_cmpysc_s0>;
2354 def HEXAGON_M2_cmacs_s1:
2355 di_MInst_disisi_acc_s1_sat <"cmpy", int_hexagon_M2_cmacs_s1>;
2356 def HEXAGON_M2_cmacs_s0:
2357 di_MInst_disisi_acc_sat <"cmpy", int_hexagon_M2_cmacs_s0>;
2358 def HEXAGON_M2_cmacsc_s1:
2359 di_MInst_disisi_acc_s1_sat_conj <"cmpy", int_hexagon_M2_cmacsc_s1>;
2360 def HEXAGON_M2_cmacsc_s0:
2361 di_MInst_disisi_acc_sat_conj <"cmpy", int_hexagon_M2_cmacsc_s0>;
2363 def HEXAGON_M2_cnacs_s1:
2364 di_MInst_disisi_nac_s1_sat <"cmpy", int_hexagon_M2_cnacs_s1>;
2365 def HEXAGON_M2_cnacs_s0:
2366 di_MInst_disisi_nac_sat <"cmpy", int_hexagon_M2_cnacs_s0>;
2367 def HEXAGON_M2_cnacsc_s1:
2368 di_MInst_disisi_nac_s1_sat_conj <"cmpy", int_hexagon_M2_cnacsc_s1>;
2369 def HEXAGON_M2_cnacsc_s0:
2370 di_MInst_disisi_nac_sat_conj <"cmpy", int_hexagon_M2_cnacsc_s0>;
2372 // MTYPE / COMPLEX / Complex multiply real or imaginary.
2373 def HEXAGON_M2_cmpyr_s0:
2374 di_MInst_sisi <"cmpyr", int_hexagon_M2_cmpyr_s0>;
2375 def HEXAGON_M2_cmacr_s0:
2376 di_MInst_disisi_acc <"cmpyr", int_hexagon_M2_cmacr_s0>;
2378 def HEXAGON_M2_cmpyi_s0:
2379 di_MInst_sisi <"cmpyi", int_hexagon_M2_cmpyi_s0>;
2380 def HEXAGON_M2_cmaci_s0:
2381 di_MInst_disisi_acc <"cmpyi", int_hexagon_M2_cmaci_s0>;
2383 // MTYPE / COMPLEX / Complex multiply with round and pack.
2384 // Rxx32+=cmpy(Rs32,[*]Rt32:<<1]:rnd:sat
2385 def HEXAGON_M2_cmpyrs_s0:
2386 si_MInst_sisi_rnd_sat <"cmpy", int_hexagon_M2_cmpyrs_s0>;
2387 def HEXAGON_M2_cmpyrs_s1:
2388 si_MInst_sisi_s1_rnd_sat <"cmpy", int_hexagon_M2_cmpyrs_s1>;
2390 def HEXAGON_M2_cmpyrsc_s0:
2391 si_MInst_sisi_rnd_sat_conj <"cmpy", int_hexagon_M2_cmpyrsc_s0>;
2392 def HEXAGON_M2_cmpyrsc_s1:
2393 si_MInst_sisi_s1_rnd_sat_conj <"cmpy", int_hexagon_M2_cmpyrsc_s1>;
2395 //MTYPE / COMPLEX / Vector complex multiply real or imaginary.
2396 def HEXAGON_M2_vcmpy_s0_sat_i:
2397 di_MInst_didi_sat <"vcmpyi", int_hexagon_M2_vcmpy_s0_sat_i>;
2398 def HEXAGON_M2_vcmpy_s1_sat_i:
2399 di_MInst_didi_s1_sat <"vcmpyi", int_hexagon_M2_vcmpy_s1_sat_i>;
2401 def HEXAGON_M2_vcmpy_s0_sat_r:
2402 di_MInst_didi_sat <"vcmpyr", int_hexagon_M2_vcmpy_s0_sat_r>;
2403 def HEXAGON_M2_vcmpy_s1_sat_r:
2404 di_MInst_didi_s1_sat <"vcmpyr", int_hexagon_M2_vcmpy_s1_sat_r>;
2406 def HEXAGON_M2_vcmac_s0_sat_i:
2407 di_MInst_dididi_acc_sat <"vcmpyi", int_hexagon_M2_vcmac_s0_sat_i>;
2408 def HEXAGON_M2_vcmac_s0_sat_r:
2409 di_MInst_dididi_acc_sat <"vcmpyr", int_hexagon_M2_vcmac_s0_sat_r>;
2411 //MTYPE / COMPLEX / Vector reduce complex multiply real or imaginary.
2412 def HEXAGON_M2_vrcmpyi_s0:
2413 di_MInst_didi <"vrcmpyi", int_hexagon_M2_vrcmpyi_s0>;
2414 def HEXAGON_M2_vrcmpyr_s0:
2415 di_MInst_didi <"vrcmpyr", int_hexagon_M2_vrcmpyr_s0>;
2417 def HEXAGON_M2_vrcmpyi_s0c:
2418 di_MInst_didi_conj <"vrcmpyi", int_hexagon_M2_vrcmpyi_s0c>;
2419 def HEXAGON_M2_vrcmpyr_s0c:
2420 di_MInst_didi_conj <"vrcmpyr", int_hexagon_M2_vrcmpyr_s0c>;
2422 def HEXAGON_M2_vrcmaci_s0:
2423 di_MInst_dididi_acc <"vrcmpyi", int_hexagon_M2_vrcmaci_s0>;
2424 def HEXAGON_M2_vrcmacr_s0:
2425 di_MInst_dididi_acc <"vrcmpyr", int_hexagon_M2_vrcmacr_s0>;
2427 def HEXAGON_M2_vrcmaci_s0c:
2428 di_MInst_dididi_acc_conj <"vrcmpyi", int_hexagon_M2_vrcmaci_s0c>;
2429 def HEXAGON_M2_vrcmacr_s0c:
2430 di_MInst_dididi_acc_conj <"vrcmpyr", int_hexagon_M2_vrcmacr_s0c>;
2433 /********************************************************************
2435 *********************************************************************/
2437 // MTYPE / MPYH / Multiply and use lower result.
2438 //def HEXAGON_M2_mpysmi:
2439 // si_MInst_sim9 <"mpyi", int_hexagon_M2_mpysmi>;
2440 def HEXAGON_M2_mpyi:
2441 si_MInst_sisi <"mpyi", int_hexagon_M2_mpyi>;
2442 def HEXAGON_M2_mpyui:
2443 si_MInst_sisi <"mpyui", int_hexagon_M2_mpyui>;
2444 def HEXAGON_M2_macsip:
2445 si_MInst_sisiu8_acc <"mpyi", int_hexagon_M2_macsip>;
2446 def HEXAGON_M2_maci:
2447 si_MInst_sisisi_acc <"mpyi", int_hexagon_M2_maci>;
2448 def HEXAGON_M2_macsin:
2449 si_MInst_sisiu8_nac <"mpyi", int_hexagon_M2_macsin>;
2451 // MTYPE / MPYH / Multiply word by half (32x16).
2452 //Rdd[+]=vmpywoh(Rss,Rtt)[:<<1][:rnd][:sat]
2453 //Rdd[+]=vmpyweh(Rss,Rtt)[:<<1][:rnd][:sat]
2454 def HEXAGON_M2_mmpyl_rs1:
2455 di_MInst_didi_s1_rnd_sat <"vmpyweh", int_hexagon_M2_mmpyl_rs1>;
2456 def HEXAGON_M2_mmpyl_s1:
2457 di_MInst_didi_s1_sat <"vmpyweh", int_hexagon_M2_mmpyl_s1>;
2458 def HEXAGON_M2_mmpyl_rs0:
2459 di_MInst_didi_rnd_sat <"vmpyweh", int_hexagon_M2_mmpyl_rs0>;
2460 def HEXAGON_M2_mmpyl_s0:
2461 di_MInst_didi_sat <"vmpyweh", int_hexagon_M2_mmpyl_s0>;
2462 def HEXAGON_M2_mmpyh_rs1:
2463 di_MInst_didi_s1_rnd_sat <"vmpywoh", int_hexagon_M2_mmpyh_rs1>;
2464 def HEXAGON_M2_mmpyh_s1:
2465 di_MInst_didi_s1_sat <"vmpywoh", int_hexagon_M2_mmpyh_s1>;
2466 def HEXAGON_M2_mmpyh_rs0:
2467 di_MInst_didi_rnd_sat <"vmpywoh", int_hexagon_M2_mmpyh_rs0>;
2468 def HEXAGON_M2_mmpyh_s0:
2469 di_MInst_didi_sat <"vmpywoh", int_hexagon_M2_mmpyh_s0>;
2470 def HEXAGON_M2_mmacls_rs1:
2471 di_MInst_dididi_acc_s1_rnd_sat <"vmpyweh", int_hexagon_M2_mmacls_rs1>;
2472 def HEXAGON_M2_mmacls_s1:
2473 di_MInst_dididi_acc_s1_sat <"vmpyweh", int_hexagon_M2_mmacls_s1>;
2474 def HEXAGON_M2_mmacls_rs0:
2475 di_MInst_dididi_acc_rnd_sat <"vmpyweh", int_hexagon_M2_mmacls_rs0>;
2476 def HEXAGON_M2_mmacls_s0:
2477 di_MInst_dididi_acc_sat <"vmpyweh", int_hexagon_M2_mmacls_s0>;
2478 def HEXAGON_M2_mmachs_rs1:
2479 di_MInst_dididi_acc_s1_rnd_sat <"vmpywoh", int_hexagon_M2_mmachs_rs1>;
2480 def HEXAGON_M2_mmachs_s1:
2481 di_MInst_dididi_acc_s1_sat <"vmpywoh", int_hexagon_M2_mmachs_s1>;
2482 def HEXAGON_M2_mmachs_rs0:
2483 di_MInst_dididi_acc_rnd_sat <"vmpywoh", int_hexagon_M2_mmachs_rs0>;
2484 def HEXAGON_M2_mmachs_s0:
2485 di_MInst_dididi_acc_sat <"vmpywoh", int_hexagon_M2_mmachs_s0>;
2487 // MTYPE / MPYH / Multiply word by unsigned half (32x16).
2488 //Rdd[+]=vmpywouh(Rss,Rtt)[:<<1][:rnd][:sat]
2489 //Rdd[+]=vmpyweuh(Rss,Rtt)[:<<1][:rnd][:sat]
2490 def HEXAGON_M2_mmpyul_rs1:
2491 di_MInst_didi_s1_rnd_sat <"vmpyweuh", int_hexagon_M2_mmpyul_rs1>;
2492 def HEXAGON_M2_mmpyul_s1:
2493 di_MInst_didi_s1_sat <"vmpyweuh", int_hexagon_M2_mmpyul_s1>;
2494 def HEXAGON_M2_mmpyul_rs0:
2495 di_MInst_didi_rnd_sat <"vmpyweuh", int_hexagon_M2_mmpyul_rs0>;
2496 def HEXAGON_M2_mmpyul_s0:
2497 di_MInst_didi_sat <"vmpyweuh", int_hexagon_M2_mmpyul_s0>;
2498 def HEXAGON_M2_mmpyuh_rs1:
2499 di_MInst_didi_s1_rnd_sat <"vmpywouh", int_hexagon_M2_mmpyuh_rs1>;
2500 def HEXAGON_M2_mmpyuh_s1:
2501 di_MInst_didi_s1_sat <"vmpywouh", int_hexagon_M2_mmpyuh_s1>;
2502 def HEXAGON_M2_mmpyuh_rs0:
2503 di_MInst_didi_rnd_sat <"vmpywouh", int_hexagon_M2_mmpyuh_rs0>;
2504 def HEXAGON_M2_mmpyuh_s0:
2505 di_MInst_didi_sat <"vmpywouh", int_hexagon_M2_mmpyuh_s0>;
2506 def HEXAGON_M2_mmaculs_rs1:
2507 di_MInst_dididi_acc_s1_rnd_sat <"vmpyweuh", int_hexagon_M2_mmaculs_rs1>;
2508 def HEXAGON_M2_mmaculs_s1:
2509 di_MInst_dididi_acc_s1_sat <"vmpyweuh", int_hexagon_M2_mmaculs_s1>;
2510 def HEXAGON_M2_mmaculs_rs0:
2511 di_MInst_dididi_acc_rnd_sat <"vmpyweuh", int_hexagon_M2_mmaculs_rs0>;
2512 def HEXAGON_M2_mmaculs_s0:
2513 di_MInst_dididi_acc_sat <"vmpyweuh", int_hexagon_M2_mmaculs_s0>;
2514 def HEXAGON_M2_mmacuhs_rs1:
2515 di_MInst_dididi_acc_s1_rnd_sat <"vmpywouh", int_hexagon_M2_mmacuhs_rs1>;
2516 def HEXAGON_M2_mmacuhs_s1:
2517 di_MInst_dididi_acc_s1_sat <"vmpywouh", int_hexagon_M2_mmacuhs_s1>;
2518 def HEXAGON_M2_mmacuhs_rs0:
2519 di_MInst_dididi_acc_rnd_sat <"vmpywouh", int_hexagon_M2_mmacuhs_rs0>;
2520 def HEXAGON_M2_mmacuhs_s0:
2521 di_MInst_dididi_acc_sat <"vmpywouh", int_hexagon_M2_mmacuhs_s0>;
2523 // MTYPE / MPYH / Multiply and use upper result.
2524 def HEXAGON_M2_hmmpyh_rs1:
2525 si_MInst_sisi_h_s1_rnd_sat <"mpy", int_hexagon_M2_hmmpyh_rs1>;
2526 def HEXAGON_M2_hmmpyl_rs1:
2527 si_MInst_sisi_l_s1_rnd_sat <"mpy", int_hexagon_M2_hmmpyl_rs1>;
2528 def HEXAGON_M2_mpy_up:
2529 si_MInst_sisi <"mpy", int_hexagon_M2_mpy_up>;
2530 def HEXAGON_M2_dpmpyss_rnd_s0:
2531 si_MInst_sisi_rnd <"mpy", int_hexagon_M2_dpmpyss_rnd_s0>;
2532 def HEXAGON_M2_mpyu_up:
2533 si_MInst_sisi <"mpyu", int_hexagon_M2_mpyu_up>;
2535 // MTYPE / MPYH / Multiply and use full result.
2536 def HEXAGON_M2_dpmpyuu_s0:
2537 di_MInst_sisi <"mpyu", int_hexagon_M2_dpmpyuu_s0>;
2538 def HEXAGON_M2_dpmpyuu_acc_s0:
2539 di_MInst_disisi_acc <"mpyu", int_hexagon_M2_dpmpyuu_acc_s0>;
2540 def HEXAGON_M2_dpmpyuu_nac_s0:
2541 di_MInst_disisi_nac <"mpyu", int_hexagon_M2_dpmpyuu_nac_s0>;
2542 def HEXAGON_M2_dpmpyss_s0:
2543 di_MInst_sisi <"mpy", int_hexagon_M2_dpmpyss_s0>;
2544 def HEXAGON_M2_dpmpyss_acc_s0:
2545 di_MInst_disisi_acc <"mpy", int_hexagon_M2_dpmpyss_acc_s0>;
2546 def HEXAGON_M2_dpmpyss_nac_s0:
2547 di_MInst_disisi_nac <"mpy", int_hexagon_M2_dpmpyss_nac_s0>;
2550 /********************************************************************
2552 *********************************************************************/
2554 // MTYPE / MPYS / Scalar 16x16 multiply signed.
2555 //Rd=mpy(Rs.[H|L],Rt.[H|L:<<0|:<<1]|
2556 // [:<<0[:rnd|:sat|:rnd:sat]|:<<1[:rnd|:sat|:rnd:sat]]]
2557 def HEXAGON_M2_mpy_hh_s0:
2558 si_MInst_sisi_hh <"mpy", int_hexagon_M2_mpy_hh_s0>;
2559 def HEXAGON_M2_mpy_hh_s1:
2560 si_MInst_sisi_hh_s1 <"mpy", int_hexagon_M2_mpy_hh_s1>;
2561 def HEXAGON_M2_mpy_rnd_hh_s1:
2562 si_MInst_sisi_rnd_hh_s1 <"mpy", int_hexagon_M2_mpy_rnd_hh_s1>;
2563 def HEXAGON_M2_mpy_sat_rnd_hh_s1:
2564 si_MInst_sisi_sat_rnd_hh_s1 <"mpy", int_hexagon_M2_mpy_sat_rnd_hh_s1>;
2565 def HEXAGON_M2_mpy_sat_hh_s1:
2566 si_MInst_sisi_sat_hh_s1 <"mpy", int_hexagon_M2_mpy_sat_hh_s1>;
2567 def HEXAGON_M2_mpy_rnd_hh_s0:
2568 si_MInst_sisi_rnd_hh <"mpy", int_hexagon_M2_mpy_rnd_hh_s0>;
2569 def HEXAGON_M2_mpy_sat_rnd_hh_s0:
2570 si_MInst_sisi_sat_rnd_hh <"mpy", int_hexagon_M2_mpy_sat_rnd_hh_s0>;
2571 def HEXAGON_M2_mpy_sat_hh_s0:
2572 si_MInst_sisi_sat_hh <"mpy", int_hexagon_M2_mpy_sat_hh_s0>;
2574 def HEXAGON_M2_mpy_hl_s0:
2575 si_MInst_sisi_hl <"mpy", int_hexagon_M2_mpy_hl_s0>;
2576 def HEXAGON_M2_mpy_hl_s1:
2577 si_MInst_sisi_hl_s1 <"mpy", int_hexagon_M2_mpy_hl_s1>;
2578 def HEXAGON_M2_mpy_rnd_hl_s1:
2579 si_MInst_sisi_rnd_hl_s1 <"mpy", int_hexagon_M2_mpy_rnd_hl_s1>;
2580 def HEXAGON_M2_mpy_sat_rnd_hl_s1:
2581 si_MInst_sisi_sat_rnd_hl_s1 <"mpy", int_hexagon_M2_mpy_sat_rnd_hl_s1>;
2582 def HEXAGON_M2_mpy_sat_hl_s1:
2583 si_MInst_sisi_sat_hl_s1 <"mpy", int_hexagon_M2_mpy_sat_hl_s1>;
2584 def HEXAGON_M2_mpy_rnd_hl_s0:
2585 si_MInst_sisi_rnd_hl <"mpy", int_hexagon_M2_mpy_rnd_hl_s0>;
2586 def HEXAGON_M2_mpy_sat_rnd_hl_s0:
2587 si_MInst_sisi_sat_rnd_hl <"mpy", int_hexagon_M2_mpy_sat_rnd_hl_s0>;
2588 def HEXAGON_M2_mpy_sat_hl_s0:
2589 si_MInst_sisi_sat_hl <"mpy", int_hexagon_M2_mpy_sat_hl_s0>;
2591 def HEXAGON_M2_mpy_lh_s0:
2592 si_MInst_sisi_lh <"mpy", int_hexagon_M2_mpy_lh_s0>;
2593 def HEXAGON_M2_mpy_lh_s1:
2594 si_MInst_sisi_lh_s1 <"mpy", int_hexagon_M2_mpy_lh_s1>;
2595 def HEXAGON_M2_mpy_rnd_lh_s1:
2596 si_MInst_sisi_rnd_lh_s1 <"mpy", int_hexagon_M2_mpy_rnd_lh_s1>;
2597 def HEXAGON_M2_mpy_sat_rnd_lh_s1:
2598 si_MInst_sisi_sat_rnd_lh_s1 <"mpy", int_hexagon_M2_mpy_sat_rnd_lh_s1>;
2599 def HEXAGON_M2_mpy_sat_lh_s1:
2600 si_MInst_sisi_sat_lh_s1 <"mpy", int_hexagon_M2_mpy_sat_lh_s1>;
2601 def HEXAGON_M2_mpy_rnd_lh_s0:
2602 si_MInst_sisi_rnd_lh <"mpy", int_hexagon_M2_mpy_rnd_lh_s0>;
2603 def HEXAGON_M2_mpy_sat_rnd_lh_s0:
2604 si_MInst_sisi_sat_rnd_lh <"mpy", int_hexagon_M2_mpy_sat_rnd_lh_s0>;
2605 def HEXAGON_M2_mpy_sat_lh_s0:
2606 si_MInst_sisi_sat_lh <"mpy", int_hexagon_M2_mpy_sat_lh_s0>;
2608 def HEXAGON_M2_mpy_ll_s0:
2609 si_MInst_sisi_ll <"mpy", int_hexagon_M2_mpy_ll_s0>;
2610 def HEXAGON_M2_mpy_ll_s1:
2611 si_MInst_sisi_ll_s1 <"mpy", int_hexagon_M2_mpy_ll_s1>;
2612 def HEXAGON_M2_mpy_rnd_ll_s1:
2613 si_MInst_sisi_rnd_ll_s1 <"mpy", int_hexagon_M2_mpy_rnd_ll_s1>;
2614 def HEXAGON_M2_mpy_sat_rnd_ll_s1:
2615 si_MInst_sisi_sat_rnd_ll_s1 <"mpy", int_hexagon_M2_mpy_sat_rnd_ll_s1>;
2616 def HEXAGON_M2_mpy_sat_ll_s1:
2617 si_MInst_sisi_sat_ll_s1 <"mpy", int_hexagon_M2_mpy_sat_ll_s1>;
2618 def HEXAGON_M2_mpy_rnd_ll_s0:
2619 si_MInst_sisi_rnd_ll <"mpy", int_hexagon_M2_mpy_rnd_ll_s0>;
2620 def HEXAGON_M2_mpy_sat_rnd_ll_s0:
2621 si_MInst_sisi_sat_rnd_ll <"mpy", int_hexagon_M2_mpy_sat_rnd_ll_s0>;
2622 def HEXAGON_M2_mpy_sat_ll_s0:
2623 si_MInst_sisi_sat_ll <"mpy", int_hexagon_M2_mpy_sat_ll_s0>;
2625 //Rdd=mpy(Rs.[H|L],Rt.[H|L])[[:<<0|:<<1]|[:<<0:rnd|:<<1:rnd]]
2626 def HEXAGON_M2_mpyd_hh_s0:
2627 di_MInst_sisi_hh <"mpy", int_hexagon_M2_mpyd_hh_s0>;
2628 def HEXAGON_M2_mpyd_hh_s1:
2629 di_MInst_sisi_hh_s1 <"mpy", int_hexagon_M2_mpyd_hh_s1>;
2630 def HEXAGON_M2_mpyd_rnd_hh_s1:
2631 di_MInst_sisi_rnd_hh_s1 <"mpy", int_hexagon_M2_mpyd_rnd_hh_s1>;
2632 def HEXAGON_M2_mpyd_rnd_hh_s0:
2633 di_MInst_sisi_rnd_hh <"mpy", int_hexagon_M2_mpyd_rnd_hh_s0>;
2635 def HEXAGON_M2_mpyd_hl_s0:
2636 di_MInst_sisi_hl <"mpy", int_hexagon_M2_mpyd_hl_s0>;
2637 def HEXAGON_M2_mpyd_hl_s1:
2638 di_MInst_sisi_hl_s1 <"mpy", int_hexagon_M2_mpyd_hl_s1>;
2639 def HEXAGON_M2_mpyd_rnd_hl_s1:
2640 di_MInst_sisi_rnd_hl_s1 <"mpy", int_hexagon_M2_mpyd_rnd_hl_s1>;
2641 def HEXAGON_M2_mpyd_rnd_hl_s0:
2642 di_MInst_sisi_rnd_hl <"mpy", int_hexagon_M2_mpyd_rnd_hl_s0>;
2644 def HEXAGON_M2_mpyd_lh_s0:
2645 di_MInst_sisi_lh <"mpy", int_hexagon_M2_mpyd_lh_s0>;
2646 def HEXAGON_M2_mpyd_lh_s1:
2647 di_MInst_sisi_lh_s1 <"mpy", int_hexagon_M2_mpyd_lh_s1>;
2648 def HEXAGON_M2_mpyd_rnd_lh_s1:
2649 di_MInst_sisi_rnd_lh_s1 <"mpy", int_hexagon_M2_mpyd_rnd_lh_s1>;
2650 def HEXAGON_M2_mpyd_rnd_lh_s0:
2651 di_MInst_sisi_rnd_lh <"mpy", int_hexagon_M2_mpyd_rnd_lh_s0>;
2653 def HEXAGON_M2_mpyd_ll_s0:
2654 di_MInst_sisi_ll <"mpy", int_hexagon_M2_mpyd_ll_s0>;
2655 def HEXAGON_M2_mpyd_ll_s1:
2656 di_MInst_sisi_ll_s1 <"mpy", int_hexagon_M2_mpyd_ll_s1>;
2657 def HEXAGON_M2_mpyd_rnd_ll_s1:
2658 di_MInst_sisi_rnd_ll_s1 <"mpy", int_hexagon_M2_mpyd_rnd_ll_s1>;
2659 def HEXAGON_M2_mpyd_rnd_ll_s0:
2660 di_MInst_sisi_rnd_ll <"mpy", int_hexagon_M2_mpyd_rnd_ll_s0>;
2662 //Rx+=mpy(Rs.[H|L],Rt.[H|L])[[[:<<0|:<<1]|[:<<0:sat|:<<1:sat]]
2663 def HEXAGON_M2_mpy_acc_hh_s0:
2664 si_MInst_sisisi_acc_hh <"mpy", int_hexagon_M2_mpy_acc_hh_s0>;
2665 def HEXAGON_M2_mpy_acc_hh_s1:
2666 si_MInst_sisisi_acc_hh_s1 <"mpy", int_hexagon_M2_mpy_acc_hh_s1>;
2667 def HEXAGON_M2_mpy_acc_sat_hh_s1:
2668 si_MInst_sisisi_acc_sat_hh_s1 <"mpy", int_hexagon_M2_mpy_acc_sat_hh_s1>;
2669 def HEXAGON_M2_mpy_acc_sat_hh_s0:
2670 si_MInst_sisisi_acc_sat_hh <"mpy", int_hexagon_M2_mpy_acc_sat_hh_s0>;
2672 def HEXAGON_M2_mpy_acc_hl_s0:
2673 si_MInst_sisisi_acc_hl <"mpy", int_hexagon_M2_mpy_acc_hl_s0>;
2674 def HEXAGON_M2_mpy_acc_hl_s1:
2675 si_MInst_sisisi_acc_hl_s1 <"mpy", int_hexagon_M2_mpy_acc_hl_s1>;
2676 def HEXAGON_M2_mpy_acc_sat_hl_s1:
2677 si_MInst_sisisi_acc_sat_hl_s1 <"mpy", int_hexagon_M2_mpy_acc_sat_hl_s1>;
2678 def HEXAGON_M2_mpy_acc_sat_hl_s0:
2679 si_MInst_sisisi_acc_sat_hl <"mpy", int_hexagon_M2_mpy_acc_sat_hl_s0>;
2681 def HEXAGON_M2_mpy_acc_lh_s0:
2682 si_MInst_sisisi_acc_lh <"mpy", int_hexagon_M2_mpy_acc_lh_s0>;
2683 def HEXAGON_M2_mpy_acc_lh_s1:
2684 si_MInst_sisisi_acc_lh_s1 <"mpy", int_hexagon_M2_mpy_acc_lh_s1>;
2685 def HEXAGON_M2_mpy_acc_sat_lh_s1:
2686 si_MInst_sisisi_acc_sat_lh_s1 <"mpy", int_hexagon_M2_mpy_acc_sat_lh_s1>;
2687 def HEXAGON_M2_mpy_acc_sat_lh_s0:
2688 si_MInst_sisisi_acc_sat_lh <"mpy", int_hexagon_M2_mpy_acc_sat_lh_s0>;
2690 def HEXAGON_M2_mpy_acc_ll_s0:
2691 si_MInst_sisisi_acc_ll <"mpy", int_hexagon_M2_mpy_acc_ll_s0>;
2692 def HEXAGON_M2_mpy_acc_ll_s1:
2693 si_MInst_sisisi_acc_ll_s1 <"mpy", int_hexagon_M2_mpy_acc_ll_s1>;
2694 def HEXAGON_M2_mpy_acc_sat_ll_s1:
2695 si_MInst_sisisi_acc_sat_ll_s1 <"mpy", int_hexagon_M2_mpy_acc_sat_ll_s1>;
2696 def HEXAGON_M2_mpy_acc_sat_ll_s0:
2697 si_MInst_sisisi_acc_sat_ll <"mpy", int_hexagon_M2_mpy_acc_sat_ll_s0>;
2699 //Rx-=mpy(Rs.[H|L],Rt.[H|L])[[[:<<0|:<<1]|[:<<0:sat|:<<1:sat]]
2700 def HEXAGON_M2_mpy_nac_hh_s0:
2701 si_MInst_sisisi_nac_hh <"mpy", int_hexagon_M2_mpy_nac_hh_s0>;
2702 def HEXAGON_M2_mpy_nac_hh_s1:
2703 si_MInst_sisisi_nac_hh_s1 <"mpy", int_hexagon_M2_mpy_nac_hh_s1>;
2704 def HEXAGON_M2_mpy_nac_sat_hh_s1:
2705 si_MInst_sisisi_nac_sat_hh_s1 <"mpy", int_hexagon_M2_mpy_nac_sat_hh_s1>;
2706 def HEXAGON_M2_mpy_nac_sat_hh_s0:
2707 si_MInst_sisisi_nac_sat_hh <"mpy", int_hexagon_M2_mpy_nac_sat_hh_s0>;
2709 def HEXAGON_M2_mpy_nac_hl_s0:
2710 si_MInst_sisisi_nac_hl <"mpy", int_hexagon_M2_mpy_nac_hl_s0>;
2711 def HEXAGON_M2_mpy_nac_hl_s1:
2712 si_MInst_sisisi_nac_hl_s1 <"mpy", int_hexagon_M2_mpy_nac_hl_s1>;
2713 def HEXAGON_M2_mpy_nac_sat_hl_s1:
2714 si_MInst_sisisi_nac_sat_hl_s1 <"mpy", int_hexagon_M2_mpy_nac_sat_hl_s1>;
2715 def HEXAGON_M2_mpy_nac_sat_hl_s0:
2716 si_MInst_sisisi_nac_sat_hl <"mpy", int_hexagon_M2_mpy_nac_sat_hl_s0>;
2718 def HEXAGON_M2_mpy_nac_lh_s0:
2719 si_MInst_sisisi_nac_lh <"mpy", int_hexagon_M2_mpy_nac_lh_s0>;
2720 def HEXAGON_M2_mpy_nac_lh_s1:
2721 si_MInst_sisisi_nac_lh_s1 <"mpy", int_hexagon_M2_mpy_nac_lh_s1>;
2722 def HEXAGON_M2_mpy_nac_sat_lh_s1:
2723 si_MInst_sisisi_nac_sat_lh_s1 <"mpy", int_hexagon_M2_mpy_nac_sat_lh_s1>;
2724 def HEXAGON_M2_mpy_nac_sat_lh_s0:
2725 si_MInst_sisisi_nac_sat_lh <"mpy", int_hexagon_M2_mpy_nac_sat_lh_s0>;
2727 def HEXAGON_M2_mpy_nac_ll_s0:
2728 si_MInst_sisisi_nac_ll <"mpy", int_hexagon_M2_mpy_nac_ll_s0>;
2729 def HEXAGON_M2_mpy_nac_ll_s1:
2730 si_MInst_sisisi_nac_ll_s1 <"mpy", int_hexagon_M2_mpy_nac_ll_s1>;
2731 def HEXAGON_M2_mpy_nac_sat_ll_s1:
2732 si_MInst_sisisi_nac_sat_ll_s1 <"mpy", int_hexagon_M2_mpy_nac_sat_ll_s1>;
2733 def HEXAGON_M2_mpy_nac_sat_ll_s0:
2734 si_MInst_sisisi_nac_sat_ll <"mpy", int_hexagon_M2_mpy_nac_sat_ll_s0>;
2736 //Rx+=mpy(Rs.[H|L],Rt.[H|L:<<0|:<<1]
2737 def HEXAGON_M2_mpyd_acc_hh_s0:
2738 di_MInst_disisi_acc_hh <"mpy", int_hexagon_M2_mpyd_acc_hh_s0>;
2739 def HEXAGON_M2_mpyd_acc_hh_s1:
2740 di_MInst_disisi_acc_hh_s1 <"mpy", int_hexagon_M2_mpyd_acc_hh_s1>;
2742 def HEXAGON_M2_mpyd_acc_hl_s0:
2743 di_MInst_disisi_acc_hl <"mpy", int_hexagon_M2_mpyd_acc_hl_s0>;
2744 def HEXAGON_M2_mpyd_acc_hl_s1:
2745 di_MInst_disisi_acc_hl_s1 <"mpy", int_hexagon_M2_mpyd_acc_hl_s1>;
2747 def HEXAGON_M2_mpyd_acc_lh_s0:
2748 di_MInst_disisi_acc_lh <"mpy", int_hexagon_M2_mpyd_acc_lh_s0>;
2749 def HEXAGON_M2_mpyd_acc_lh_s1:
2750 di_MInst_disisi_acc_lh_s1 <"mpy", int_hexagon_M2_mpyd_acc_lh_s1>;
2752 def HEXAGON_M2_mpyd_acc_ll_s0:
2753 di_MInst_disisi_acc_ll <"mpy", int_hexagon_M2_mpyd_acc_ll_s0>;
2754 def HEXAGON_M2_mpyd_acc_ll_s1:
2755 di_MInst_disisi_acc_ll_s1 <"mpy", int_hexagon_M2_mpyd_acc_ll_s1>;
2757 //Rx-=mpy(Rs.[H|L],Rt.[H|L:<<0|:<<1]
2758 def HEXAGON_M2_mpyd_nac_hh_s0:
2759 di_MInst_disisi_nac_hh <"mpy", int_hexagon_M2_mpyd_nac_hh_s0>;
2760 def HEXAGON_M2_mpyd_nac_hh_s1:
2761 di_MInst_disisi_nac_hh_s1 <"mpy", int_hexagon_M2_mpyd_nac_hh_s1>;
2763 def HEXAGON_M2_mpyd_nac_hl_s0:
2764 di_MInst_disisi_nac_hl <"mpy", int_hexagon_M2_mpyd_nac_hl_s0>;
2765 def HEXAGON_M2_mpyd_nac_hl_s1:
2766 di_MInst_disisi_nac_hl_s1 <"mpy", int_hexagon_M2_mpyd_nac_hl_s1>;
2768 def HEXAGON_M2_mpyd_nac_lh_s0:
2769 di_MInst_disisi_nac_lh <"mpy", int_hexagon_M2_mpyd_nac_lh_s0>;
2770 def HEXAGON_M2_mpyd_nac_lh_s1:
2771 di_MInst_disisi_nac_lh_s1 <"mpy", int_hexagon_M2_mpyd_nac_lh_s1>;
2773 def HEXAGON_M2_mpyd_nac_ll_s0:
2774 di_MInst_disisi_nac_ll <"mpy", int_hexagon_M2_mpyd_nac_ll_s0>;
2775 def HEXAGON_M2_mpyd_nac_ll_s1:
2776 di_MInst_disisi_nac_ll_s1 <"mpy", int_hexagon_M2_mpyd_nac_ll_s1>;
2778 // MTYPE / MPYS / Scalar 16x16 multiply unsigned.
2779 //Rd=mpyu(Rs.[H|L],Rt.[H|L])[:<<0|:<<1]
2780 def HEXAGON_M2_mpyu_hh_s0:
2781 si_MInst_sisi_hh <"mpyu", int_hexagon_M2_mpyu_hh_s0>;
2782 def HEXAGON_M2_mpyu_hh_s1:
2783 si_MInst_sisi_hh_s1 <"mpyu", int_hexagon_M2_mpyu_hh_s1>;
2784 def HEXAGON_M2_mpyu_hl_s0:
2785 si_MInst_sisi_hl <"mpyu", int_hexagon_M2_mpyu_hl_s0>;
2786 def HEXAGON_M2_mpyu_hl_s1:
2787 si_MInst_sisi_hl_s1 <"mpyu", int_hexagon_M2_mpyu_hl_s1>;
2788 def HEXAGON_M2_mpyu_lh_s0:
2789 si_MInst_sisi_lh <"mpyu", int_hexagon_M2_mpyu_lh_s0>;
2790 def HEXAGON_M2_mpyu_lh_s1:
2791 si_MInst_sisi_lh_s1 <"mpyu", int_hexagon_M2_mpyu_lh_s1>;
2792 def HEXAGON_M2_mpyu_ll_s0:
2793 si_MInst_sisi_ll <"mpyu", int_hexagon_M2_mpyu_ll_s0>;
2794 def HEXAGON_M2_mpyu_ll_s1:
2795 si_MInst_sisi_ll_s1 <"mpyu", int_hexagon_M2_mpyu_ll_s1>;
2797 //Rdd=mpyu(Rs.[H|L],Rt.[H|L])[:<<0|:<<1]
2798 def HEXAGON_M2_mpyud_hh_s0:
2799 di_MInst_sisi_hh <"mpyu", int_hexagon_M2_mpyud_hh_s0>;
2800 def HEXAGON_M2_mpyud_hh_s1:
2801 di_MInst_sisi_hh_s1 <"mpyu", int_hexagon_M2_mpyud_hh_s1>;
2802 def HEXAGON_M2_mpyud_hl_s0:
2803 di_MInst_sisi_hl <"mpyu", int_hexagon_M2_mpyud_hl_s0>;
2804 def HEXAGON_M2_mpyud_hl_s1:
2805 di_MInst_sisi_hl_s1 <"mpyu", int_hexagon_M2_mpyud_hl_s1>;
2806 def HEXAGON_M2_mpyud_lh_s0:
2807 di_MInst_sisi_lh <"mpyu", int_hexagon_M2_mpyud_lh_s0>;
2808 def HEXAGON_M2_mpyud_lh_s1:
2809 di_MInst_sisi_lh_s1 <"mpyu", int_hexagon_M2_mpyud_lh_s1>;
2810 def HEXAGON_M2_mpyud_ll_s0:
2811 di_MInst_sisi_ll <"mpyu", int_hexagon_M2_mpyud_ll_s0>;
2812 def HEXAGON_M2_mpyud_ll_s1:
2813 di_MInst_sisi_ll_s1 <"mpyu", int_hexagon_M2_mpyud_ll_s1>;
2815 //Rd+=mpyu(Rs.[H|L],Rt.[H|L])[:<<0|:<<1]
2816 def HEXAGON_M2_mpyu_acc_hh_s0:
2817 si_MInst_sisisi_acc_hh <"mpyu", int_hexagon_M2_mpyu_acc_hh_s0>;
2818 def HEXAGON_M2_mpyu_acc_hh_s1:
2819 si_MInst_sisisi_acc_hh_s1 <"mpyu", int_hexagon_M2_mpyu_acc_hh_s1>;
2820 def HEXAGON_M2_mpyu_acc_hl_s0:
2821 si_MInst_sisisi_acc_hl <"mpyu", int_hexagon_M2_mpyu_acc_hl_s0>;
2822 def HEXAGON_M2_mpyu_acc_hl_s1:
2823 si_MInst_sisisi_acc_hl_s1 <"mpyu", int_hexagon_M2_mpyu_acc_hl_s1>;
2824 def HEXAGON_M2_mpyu_acc_lh_s0:
2825 si_MInst_sisisi_acc_lh <"mpyu", int_hexagon_M2_mpyu_acc_lh_s0>;
2826 def HEXAGON_M2_mpyu_acc_lh_s1:
2827 si_MInst_sisisi_acc_lh_s1 <"mpyu", int_hexagon_M2_mpyu_acc_lh_s1>;
2828 def HEXAGON_M2_mpyu_acc_ll_s0:
2829 si_MInst_sisisi_acc_ll <"mpyu", int_hexagon_M2_mpyu_acc_ll_s0>;
2830 def HEXAGON_M2_mpyu_acc_ll_s1:
2831 si_MInst_sisisi_acc_ll_s1 <"mpyu", int_hexagon_M2_mpyu_acc_ll_s1>;
2833 //Rd+=mpyu(Rs.[H|L],Rt.[H|L])[:<<0|:<<1]
2834 def HEXAGON_M2_mpyu_nac_hh_s0:
2835 si_MInst_sisisi_nac_hh <"mpyu", int_hexagon_M2_mpyu_nac_hh_s0>;
2836 def HEXAGON_M2_mpyu_nac_hh_s1:
2837 si_MInst_sisisi_nac_hh_s1 <"mpyu", int_hexagon_M2_mpyu_nac_hh_s1>;
2838 def HEXAGON_M2_mpyu_nac_hl_s0:
2839 si_MInst_sisisi_nac_hl <"mpyu", int_hexagon_M2_mpyu_nac_hl_s0>;
2840 def HEXAGON_M2_mpyu_nac_hl_s1:
2841 si_MInst_sisisi_nac_hl_s1 <"mpyu", int_hexagon_M2_mpyu_nac_hl_s1>;
2842 def HEXAGON_M2_mpyu_nac_lh_s0:
2843 si_MInst_sisisi_nac_lh <"mpyu", int_hexagon_M2_mpyu_nac_lh_s0>;
2844 def HEXAGON_M2_mpyu_nac_lh_s1:
2845 si_MInst_sisisi_nac_lh_s1 <"mpyu", int_hexagon_M2_mpyu_nac_lh_s1>;
2846 def HEXAGON_M2_mpyu_nac_ll_s0:
2847 si_MInst_sisisi_nac_ll <"mpyu", int_hexagon_M2_mpyu_nac_ll_s0>;
2848 def HEXAGON_M2_mpyu_nac_ll_s1:
2849 si_MInst_sisisi_nac_ll_s1 <"mpyu", int_hexagon_M2_mpyu_nac_ll_s1>;
2851 //Rdd+=mpyu(Rs.[H|L],Rt.[H|L])[:<<0|:<<1]
2852 def HEXAGON_M2_mpyud_acc_hh_s0:
2853 di_MInst_disisi_acc_hh <"mpyu", int_hexagon_M2_mpyud_acc_hh_s0>;
2854 def HEXAGON_M2_mpyud_acc_hh_s1:
2855 di_MInst_disisi_acc_hh_s1 <"mpyu", int_hexagon_M2_mpyud_acc_hh_s1>;
2856 def HEXAGON_M2_mpyud_acc_hl_s0:
2857 di_MInst_disisi_acc_hl <"mpyu", int_hexagon_M2_mpyud_acc_hl_s0>;
2858 def HEXAGON_M2_mpyud_acc_hl_s1:
2859 di_MInst_disisi_acc_hl_s1 <"mpyu", int_hexagon_M2_mpyud_acc_hl_s1>;
2860 def HEXAGON_M2_mpyud_acc_lh_s0:
2861 di_MInst_disisi_acc_lh <"mpyu", int_hexagon_M2_mpyud_acc_lh_s0>;
2862 def HEXAGON_M2_mpyud_acc_lh_s1:
2863 di_MInst_disisi_acc_lh_s1 <"mpyu", int_hexagon_M2_mpyud_acc_lh_s1>;
2864 def HEXAGON_M2_mpyud_acc_ll_s0:
2865 di_MInst_disisi_acc_ll <"mpyu", int_hexagon_M2_mpyud_acc_ll_s0>;
2866 def HEXAGON_M2_mpyud_acc_ll_s1:
2867 di_MInst_disisi_acc_ll_s1 <"mpyu", int_hexagon_M2_mpyud_acc_ll_s1>;
2869 //Rdd-=mpyu(Rs.[H|L],Rt.[H|L])[:<<0|:<<1]
2870 def HEXAGON_M2_mpyud_nac_hh_s0:
2871 di_MInst_disisi_nac_hh <"mpyu", int_hexagon_M2_mpyud_nac_hh_s0>;
2872 def HEXAGON_M2_mpyud_nac_hh_s1:
2873 di_MInst_disisi_nac_hh_s1 <"mpyu", int_hexagon_M2_mpyud_nac_hh_s1>;
2874 def HEXAGON_M2_mpyud_nac_hl_s0:
2875 di_MInst_disisi_nac_hl <"mpyu", int_hexagon_M2_mpyud_nac_hl_s0>;
2876 def HEXAGON_M2_mpyud_nac_hl_s1:
2877 di_MInst_disisi_nac_hl_s1 <"mpyu", int_hexagon_M2_mpyud_nac_hl_s1>;
2878 def HEXAGON_M2_mpyud_nac_lh_s0:
2879 di_MInst_disisi_nac_lh <"mpyu", int_hexagon_M2_mpyud_nac_lh_s0>;
2880 def HEXAGON_M2_mpyud_nac_lh_s1:
2881 di_MInst_disisi_nac_lh_s1 <"mpyu", int_hexagon_M2_mpyud_nac_lh_s1>;
2882 def HEXAGON_M2_mpyud_nac_ll_s0:
2883 di_MInst_disisi_nac_ll <"mpyu", int_hexagon_M2_mpyud_nac_ll_s0>;
2884 def HEXAGON_M2_mpyud_nac_ll_s1:
2885 di_MInst_disisi_nac_ll_s1 <"mpyu", int_hexagon_M2_mpyud_nac_ll_s1>;
2888 /********************************************************************
2890 *********************************************************************/
2892 // MTYPE / VB / Vector reduce add unsigned bytes.
2893 def HEXAGON_A2_vraddub:
2894 di_MInst_didi <"vraddub", int_hexagon_A2_vraddub>;
2895 def HEXAGON_A2_vraddub_acc:
2896 di_MInst_dididi_acc <"vraddub", int_hexagon_A2_vraddub_acc>;
2898 // MTYPE / VB / Vector sum of absolute differences unsigned bytes.
2899 def HEXAGON_A2_vrsadub:
2900 di_MInst_didi <"vrsadub", int_hexagon_A2_vrsadub>;
2901 def HEXAGON_A2_vrsadub_acc:
2902 di_MInst_dididi_acc <"vrsadub", int_hexagon_A2_vrsadub_acc>;
2904 /********************************************************************
2906 *********************************************************************/
2908 // MTYPE / VH / Vector dual multiply.
2909 def HEXAGON_M2_vdmpys_s1:
2910 di_MInst_didi_s1_sat <"vdmpy", int_hexagon_M2_vdmpys_s1>;
2911 def HEXAGON_M2_vdmpys_s0:
2912 di_MInst_didi_sat <"vdmpy", int_hexagon_M2_vdmpys_s0>;
2913 def HEXAGON_M2_vdmacs_s1:
2914 di_MInst_dididi_acc_s1_sat <"vdmpy", int_hexagon_M2_vdmacs_s1>;
2915 def HEXAGON_M2_vdmacs_s0:
2916 di_MInst_dididi_acc_sat <"vdmpy", int_hexagon_M2_vdmacs_s0>;
2918 // MTYPE / VH / Vector dual multiply with round and pack.
2919 def HEXAGON_M2_vdmpyrs_s0:
2920 si_MInst_didi_rnd_sat <"vdmpy", int_hexagon_M2_vdmpyrs_s0>;
2921 def HEXAGON_M2_vdmpyrs_s1:
2922 si_MInst_didi_s1_rnd_sat <"vdmpy", int_hexagon_M2_vdmpyrs_s1>;
2924 // MTYPE / VH / Vector multiply even halfwords.
2925 def HEXAGON_M2_vmpy2es_s1:
2926 di_MInst_didi_s1_sat <"vmpyeh", int_hexagon_M2_vmpy2es_s1>;
2927 def HEXAGON_M2_vmpy2es_s0:
2928 di_MInst_didi_sat <"vmpyeh", int_hexagon_M2_vmpy2es_s0>;
2929 def HEXAGON_M2_vmac2es:
2930 di_MInst_dididi_acc <"vmpyeh", int_hexagon_M2_vmac2es>;
2931 def HEXAGON_M2_vmac2es_s1:
2932 di_MInst_dididi_acc_s1_sat <"vmpyeh", int_hexagon_M2_vmac2es_s1>;
2933 def HEXAGON_M2_vmac2es_s0:
2934 di_MInst_dididi_acc_sat <"vmpyeh", int_hexagon_M2_vmac2es_s0>;
2936 // MTYPE / VH / Vector multiply halfwords.
2937 def HEXAGON_M2_vmpy2s_s0:
2938 di_MInst_sisi_sat <"vmpyh", int_hexagon_M2_vmpy2s_s0>;
2939 def HEXAGON_M2_vmpy2s_s1:
2940 di_MInst_sisi_s1_sat <"vmpyh", int_hexagon_M2_vmpy2s_s1>;
2941 def HEXAGON_M2_vmac2:
2942 di_MInst_disisi_acc <"vmpyh", int_hexagon_M2_vmac2>;
2943 def HEXAGON_M2_vmac2s_s0:
2944 di_MInst_disisi_acc_sat <"vmpyh", int_hexagon_M2_vmac2s_s0>;
2945 def HEXAGON_M2_vmac2s_s1:
2946 di_MInst_disisi_acc_s1_sat <"vmpyh", int_hexagon_M2_vmac2s_s1>;
2948 // MTYPE / VH / Vector multiply halfwords with round and pack.
2949 def HEXAGON_M2_vmpy2s_s0pack:
2950 si_MInst_sisi_rnd_sat <"vmpyh", int_hexagon_M2_vmpy2s_s0pack>;
2951 def HEXAGON_M2_vmpy2s_s1pack:
2952 si_MInst_sisi_s1_rnd_sat <"vmpyh", int_hexagon_M2_vmpy2s_s1pack>;
2954 // MTYPE / VH / Vector reduce multiply halfwords.
2955 // Rxx32+=vrmpyh(Rss32,Rtt32)
2956 def HEXAGON_M2_vrmpy_s0:
2957 di_MInst_didi <"vrmpyh", int_hexagon_M2_vrmpy_s0>;
2958 def HEXAGON_M2_vrmac_s0:
2959 di_MInst_dididi_acc <"vrmpyh", int_hexagon_M2_vrmac_s0>;
2962 /********************************************************************
2964 *********************************************************************/
2966 // STYPE / ALU / Absolute value.
2968 si_SInst_si <"abs", int_hexagon_A2_abs>;
2969 def HEXAGON_A2_absp:
2970 di_SInst_di <"abs", int_hexagon_A2_absp>;
2971 def HEXAGON_A2_abssat:
2972 si_SInst_si_sat <"abs", int_hexagon_A2_abssat>;
2974 // STYPE / ALU / Negate.
2975 def HEXAGON_A2_negp:
2976 di_SInst_di <"neg", int_hexagon_A2_negp>;
2977 def HEXAGON_A2_negsat:
2978 si_SInst_si_sat <"neg", int_hexagon_A2_negsat>;
2980 // STYPE / ALU / Logical Not.
2981 def HEXAGON_A2_notp:
2982 di_SInst_di <"not", int_hexagon_A2_notp>;
2984 // STYPE / ALU / Sign extend word to doubleword.
2985 def HEXAGON_A2_sxtw:
2986 di_SInst_si <"sxtw", int_hexagon_A2_sxtw>;
2989 /********************************************************************
2991 *********************************************************************/
2993 // STYPE / BIT / Count leading.
2995 si_SInst_si <"cl0", int_hexagon_S2_cl0>;
2996 def HEXAGON_S2_cl0p:
2997 si_SInst_di <"cl0", int_hexagon_S2_cl0p>;
2999 si_SInst_si <"cl1", int_hexagon_S2_cl1>;
3000 def HEXAGON_S2_cl1p:
3001 si_SInst_di <"cl1", int_hexagon_S2_cl1p>;
3003 si_SInst_si <"clb", int_hexagon_S2_clb>;
3004 def HEXAGON_S2_clbp:
3005 si_SInst_di <"clb", int_hexagon_S2_clbp>;
3006 def HEXAGON_S2_clbnorm:
3007 si_SInst_si <"normamt", int_hexagon_S2_clbnorm>;
3009 // STYPE / BIT / Count trailing.
3011 si_SInst_si <"ct0", int_hexagon_S2_ct0>;
3013 si_SInst_si <"ct1", int_hexagon_S2_ct1>;
3015 // STYPE / BIT / Compare bit mask.
3016 def Hexagon_C2_bitsclr:
3017 qi_SInst_sisi <"bitsclr", int_hexagon_C2_bitsclr>;
3018 def Hexagon_C2_bitsclri:
3019 qi_SInst_siu6 <"bitsclr", int_hexagon_C2_bitsclri>;
3020 def Hexagon_C2_bitsset:
3021 qi_SInst_sisi <"bitsset", int_hexagon_C2_bitsset>;
3023 // STYPE / BIT / Extract unsigned.
3024 // Rd[d][32/64]=extractu(Rs[s],Rt[t],[imm])
3025 def HEXAGON_S2_extractu:
3026 si_SInst_siu5u5 <"extractu",int_hexagon_S2_extractu>;
3027 def HEXAGON_S2_extractu_rp:
3028 si_SInst_sidi <"extractu",int_hexagon_S2_extractu_rp>;
3029 def HEXAGON_S2_extractup:
3030 di_SInst_diu6u6 <"extractu",int_hexagon_S2_extractup>;
3031 def HEXAGON_S2_extractup_rp:
3032 di_SInst_didi <"extractu",int_hexagon_S2_extractup_rp>;
3034 // STYPE / BIT / Insert bitfield.
3035 def Hexagon_S2_insert:
3036 si_SInst_sisiu5u5 <"insert", int_hexagon_S2_insert>;
3037 def Hexagon_S2_insert_rp:
3038 si_SInst_sisidi <"insert", int_hexagon_S2_insert_rp>;
3039 def Hexagon_S2_insertp:
3040 di_SInst_didiu6u6 <"insert", int_hexagon_S2_insertp>;
3041 def Hexagon_S2_insertp_rp:
3042 di_SInst_dididi <"insert", int_hexagon_S2_insertp_rp>;
3044 // STYPE / BIT / Innterleave/deinterleave.
3045 def Hexagon_S2_interleave:
3046 di_SInst_di <"interleave", int_hexagon_S2_interleave>;
3047 def Hexagon_S2_deinterleave:
3048 di_SInst_di <"deinterleave", int_hexagon_S2_deinterleave>;
3050 // STYPE / BIT / Linear feedback-shift Iteration.
3051 def Hexagon_S2_lfsp:
3052 di_SInst_didi <"lfs", int_hexagon_S2_lfsp>;
3054 // STYPE / BIT / Bit reverse.
3055 def Hexagon_S2_brev:
3056 si_SInst_si <"brev", int_hexagon_S2_brev>;
3058 // STYPE / BIT / Set/Clear/Toggle Bit.
3059 def HEXAGON_S2_setbit_i:
3060 si_SInst_siu5 <"setbit", int_hexagon_S2_setbit_i>;
3061 def HEXAGON_S2_togglebit_i:
3062 si_SInst_siu5 <"togglebit", int_hexagon_S2_togglebit_i>;
3063 def HEXAGON_S2_clrbit_i:
3064 si_SInst_siu5 <"clrbit", int_hexagon_S2_clrbit_i>;
3065 def HEXAGON_S2_setbit_r:
3066 si_SInst_sisi <"setbit", int_hexagon_S2_setbit_r>;
3067 def HEXAGON_S2_togglebit_r:
3068 si_SInst_sisi <"togglebit", int_hexagon_S2_togglebit_r>;
3069 def HEXAGON_S2_clrbit_r:
3070 si_SInst_sisi <"clrbit", int_hexagon_S2_clrbit_r>;
3072 // STYPE / BIT / Test Bit.
3073 def HEXAGON_S2_tstbit_i:
3074 qi_SInst_siu5 <"tstbit", int_hexagon_S2_tstbit_i>;
3075 def HEXAGON_S2_tstbit_r:
3076 qi_SInst_sisi <"tstbit", int_hexagon_S2_tstbit_r>;
3079 /********************************************************************
3081 *********************************************************************/
3083 // STYPE / COMPLEX / Vector Complex conjugate.
3084 def HEXAGON_A2_vconj:
3085 di_SInst_di_sat <"vconj", int_hexagon_A2_vconj>;
3087 // STYPE / COMPLEX / Vector Complex rotate.
3088 def HEXAGON_S2_vcrotate:
3089 di_SInst_disi <"vcrotate",int_hexagon_S2_vcrotate>;
3092 /********************************************************************
3094 *********************************************************************/
3096 // STYPE / PERM / Saturate.
3098 si_SInst_di <"sat", int_hexagon_A2_sat>;
3099 def HEXAGON_A2_satb:
3100 si_SInst_si <"satb", int_hexagon_A2_satb>;
3101 def HEXAGON_A2_sath:
3102 si_SInst_si <"sath", int_hexagon_A2_sath>;
3103 def HEXAGON_A2_satub:
3104 si_SInst_si <"satub", int_hexagon_A2_satub>;
3105 def HEXAGON_A2_satuh:
3106 si_SInst_si <"satuh", int_hexagon_A2_satuh>;
3108 // STYPE / PERM / Swizzle bytes.
3109 def HEXAGON_A2_swiz:
3110 si_SInst_si <"swiz", int_hexagon_A2_swiz>;
3112 // STYPE / PERM / Vector align.
3113 // Need custom lowering
3114 def HEXAGON_S2_valignib:
3115 di_SInst_didiu3 <"valignb", int_hexagon_S2_valignib>;
3116 def HEXAGON_S2_valignrb:
3117 di_SInst_didiqi <"valignb", int_hexagon_S2_valignrb>;
3119 // STYPE / PERM / Vector round and pack.
3120 def HEXAGON_S2_vrndpackwh:
3121 si_SInst_di <"vrndwh", int_hexagon_S2_vrndpackwh>;
3122 def HEXAGON_S2_vrndpackwhs:
3123 si_SInst_di_sat <"vrndwh", int_hexagon_S2_vrndpackwhs>;
3125 // STYPE / PERM / Vector saturate and pack.
3126 def HEXAGON_S2_svsathb:
3127 si_SInst_si <"vsathb", int_hexagon_S2_svsathb>;
3128 def HEXAGON_S2_vsathb:
3129 si_SInst_di <"vsathb", int_hexagon_S2_vsathb>;
3130 def HEXAGON_S2_svsathub:
3131 si_SInst_si <"vsathub", int_hexagon_S2_svsathub>;
3132 def HEXAGON_S2_vsathub:
3133 si_SInst_di <"vsathub", int_hexagon_S2_vsathub>;
3134 def HEXAGON_S2_vsatwh:
3135 si_SInst_di <"vsatwh", int_hexagon_S2_vsatwh>;
3136 def HEXAGON_S2_vsatwuh:
3137 si_SInst_di <"vsatwuh", int_hexagon_S2_vsatwuh>;
3139 // STYPE / PERM / Vector saturate without pack.
3140 def HEXAGON_S2_vsathb_nopack:
3141 di_SInst_di <"vsathb", int_hexagon_S2_vsathb_nopack>;
3142 def HEXAGON_S2_vsathub_nopack:
3143 di_SInst_di <"vsathub", int_hexagon_S2_vsathub_nopack>;
3144 def HEXAGON_S2_vsatwh_nopack:
3145 di_SInst_di <"vsatwh", int_hexagon_S2_vsatwh_nopack>;
3146 def HEXAGON_S2_vsatwuh_nopack:
3147 di_SInst_di <"vsatwuh", int_hexagon_S2_vsatwuh_nopack>;
3149 // STYPE / PERM / Vector shuffle.
3150 def HEXAGON_S2_shuffeb:
3151 di_SInst_didi <"shuffeb", int_hexagon_S2_shuffeb>;
3152 def HEXAGON_S2_shuffeh:
3153 di_SInst_didi <"shuffeh", int_hexagon_S2_shuffeh>;
3154 def HEXAGON_S2_shuffob:
3155 di_SInst_didi <"shuffob", int_hexagon_S2_shuffob>;
3156 def HEXAGON_S2_shuffoh:
3157 di_SInst_didi <"shuffoh", int_hexagon_S2_shuffoh>;
3159 // STYPE / PERM / Vector splat bytes.
3160 def HEXAGON_S2_vsplatrb:
3161 si_SInst_si <"vsplatb", int_hexagon_S2_vsplatrb>;
3163 // STYPE / PERM / Vector splat halfwords.
3164 def HEXAGON_S2_vsplatrh:
3165 di_SInst_si <"vsplath", int_hexagon_S2_vsplatrh>;
3167 // STYPE / PERM / Vector splice.
3168 def Hexagon_S2_vsplicerb:
3169 di_SInst_didiqi <"vspliceb",int_hexagon_S2_vsplicerb>;
3170 def Hexagon_S2_vspliceib:
3171 di_SInst_didiu3 <"vspliceb",int_hexagon_S2_vspliceib>;
3173 // STYPE / PERM / Sign extend.
3174 def HEXAGON_S2_vsxtbh:
3175 di_SInst_si <"vsxtbh", int_hexagon_S2_vsxtbh>;
3176 def HEXAGON_S2_vsxthw:
3177 di_SInst_si <"vsxthw", int_hexagon_S2_vsxthw>;
3179 // STYPE / PERM / Truncate.
3180 def HEXAGON_S2_vtrunehb:
3181 si_SInst_di <"vtrunehb",int_hexagon_S2_vtrunehb>;
3182 def HEXAGON_S2_vtrunohb:
3183 si_SInst_di <"vtrunohb",int_hexagon_S2_vtrunohb>;
3184 def HEXAGON_S2_vtrunewh:
3185 di_SInst_didi <"vtrunewh",int_hexagon_S2_vtrunewh>;
3186 def HEXAGON_S2_vtrunowh:
3187 di_SInst_didi <"vtrunowh",int_hexagon_S2_vtrunowh>;
3189 // STYPE / PERM / Zero extend.
3190 def HEXAGON_S2_vzxtbh:
3191 di_SInst_si <"vzxtbh", int_hexagon_S2_vzxtbh>;
3192 def HEXAGON_S2_vzxthw:
3193 di_SInst_si <"vzxthw", int_hexagon_S2_vzxthw>;
3196 /********************************************************************
3198 *********************************************************************/
3200 // STYPE / PRED / Mask generate from predicate.
3201 def HEXAGON_C2_mask:
3202 di_SInst_qi <"mask", int_hexagon_C2_mask>;
3204 // STYPE / PRED / Predicate transfer.
3205 def HEXAGON_C2_tfrpr:
3206 si_SInst_qi <"", int_hexagon_C2_tfrpr>;
3207 def HEXAGON_C2_tfrrp:
3208 qi_SInst_si <"", int_hexagon_C2_tfrrp>;
3210 // STYPE / PRED / Viterbi pack even and odd predicate bits.
3211 def HEXAGON_C2_vitpack:
3212 si_SInst_qiqi <"vitpack",int_hexagon_C2_vitpack>;
3215 /********************************************************************
3217 *********************************************************************/
3219 // STYPE / SHIFT / Shift by immediate.
3220 def HEXAGON_S2_asl_i_r:
3221 si_SInst_siu5 <"asl", int_hexagon_S2_asl_i_r>;
3222 def HEXAGON_S2_asr_i_r:
3223 si_SInst_siu5 <"asr", int_hexagon_S2_asr_i_r>;
3224 def HEXAGON_S2_lsr_i_r:
3225 si_SInst_siu5 <"lsr", int_hexagon_S2_lsr_i_r>;
3226 def HEXAGON_S2_asl_i_p:
3227 di_SInst_diu6 <"asl", int_hexagon_S2_asl_i_p>;
3228 def HEXAGON_S2_asr_i_p:
3229 di_SInst_diu6 <"asr", int_hexagon_S2_asr_i_p>;
3230 def HEXAGON_S2_lsr_i_p:
3231 di_SInst_diu6 <"lsr", int_hexagon_S2_lsr_i_p>;
3233 // STYPE / SHIFT / Shift by immediate and accumulate.
3234 def HEXAGON_S2_asl_i_r_acc:
3235 si_SInst_sisiu5_acc <"asl", int_hexagon_S2_asl_i_r_acc>;
3236 def HEXAGON_S2_asr_i_r_acc:
3237 si_SInst_sisiu5_acc <"asr", int_hexagon_S2_asr_i_r_acc>;
3238 def HEXAGON_S2_lsr_i_r_acc:
3239 si_SInst_sisiu5_acc <"lsr", int_hexagon_S2_lsr_i_r_acc>;
3240 def HEXAGON_S2_asl_i_r_nac:
3241 si_SInst_sisiu5_nac <"asl", int_hexagon_S2_asl_i_r_nac>;
3242 def HEXAGON_S2_asr_i_r_nac:
3243 si_SInst_sisiu5_nac <"asr", int_hexagon_S2_asr_i_r_nac>;
3244 def HEXAGON_S2_lsr_i_r_nac:
3245 si_SInst_sisiu5_nac <"lsr", int_hexagon_S2_lsr_i_r_nac>;
3246 def HEXAGON_S2_asl_i_p_acc:
3247 di_SInst_didiu6_acc <"asl", int_hexagon_S2_asl_i_p_acc>;
3248 def HEXAGON_S2_asr_i_p_acc:
3249 di_SInst_didiu6_acc <"asr", int_hexagon_S2_asr_i_p_acc>;
3250 def HEXAGON_S2_lsr_i_p_acc:
3251 di_SInst_didiu6_acc <"lsr", int_hexagon_S2_lsr_i_p_acc>;
3252 def HEXAGON_S2_asl_i_p_nac:
3253 di_SInst_didiu6_nac <"asl", int_hexagon_S2_asl_i_p_nac>;
3254 def HEXAGON_S2_asr_i_p_nac:
3255 di_SInst_didiu6_nac <"asr", int_hexagon_S2_asr_i_p_nac>;
3256 def HEXAGON_S2_lsr_i_p_nac:
3257 di_SInst_didiu6_nac <"lsr", int_hexagon_S2_lsr_i_p_nac>;
3259 // STYPE / SHIFT / Shift by immediate and add.
3260 def HEXAGON_S2_addasl_rrri:
3261 si_SInst_sisiu3 <"addasl", int_hexagon_S2_addasl_rrri>;
3263 // STYPE / SHIFT / Shift by immediate and logical.
3264 def HEXAGON_S2_asl_i_r_and:
3265 si_SInst_sisiu5_and <"asl", int_hexagon_S2_asl_i_r_and>;
3266 def HEXAGON_S2_asr_i_r_and:
3267 si_SInst_sisiu5_and <"asr", int_hexagon_S2_asr_i_r_and>;
3268 def HEXAGON_S2_lsr_i_r_and:
3269 si_SInst_sisiu5_and <"lsr", int_hexagon_S2_lsr_i_r_and>;
3271 def HEXAGON_S2_asl_i_r_xacc:
3272 si_SInst_sisiu5_xor <"asl", int_hexagon_S2_asl_i_r_xacc>;
3273 def HEXAGON_S2_lsr_i_r_xacc:
3274 si_SInst_sisiu5_xor <"lsr", int_hexagon_S2_lsr_i_r_xacc>;
3276 def HEXAGON_S2_asl_i_r_or:
3277 si_SInst_sisiu5_or <"asl", int_hexagon_S2_asl_i_r_or>;
3278 def HEXAGON_S2_asr_i_r_or:
3279 si_SInst_sisiu5_or <"asr", int_hexagon_S2_asr_i_r_or>;
3280 def HEXAGON_S2_lsr_i_r_or:
3281 si_SInst_sisiu5_or <"lsr", int_hexagon_S2_lsr_i_r_or>;
3283 def HEXAGON_S2_asl_i_p_and:
3284 di_SInst_didiu6_and <"asl", int_hexagon_S2_asl_i_p_and>;
3285 def HEXAGON_S2_asr_i_p_and:
3286 di_SInst_didiu6_and <"asr", int_hexagon_S2_asr_i_p_and>;
3287 def HEXAGON_S2_lsr_i_p_and:
3288 di_SInst_didiu6_and <"lsr", int_hexagon_S2_lsr_i_p_and>;
3290 def HEXAGON_S2_asl_i_p_xacc:
3291 di_SInst_didiu6_xor <"asl", int_hexagon_S2_asl_i_p_xacc>;
3292 def HEXAGON_S2_lsr_i_p_xacc:
3293 di_SInst_didiu6_xor <"lsr", int_hexagon_S2_lsr_i_p_xacc>;
3295 def HEXAGON_S2_asl_i_p_or:
3296 di_SInst_didiu6_or <"asl", int_hexagon_S2_asl_i_p_or>;
3297 def HEXAGON_S2_asr_i_p_or:
3298 di_SInst_didiu6_or <"asr", int_hexagon_S2_asr_i_p_or>;
3299 def HEXAGON_S2_lsr_i_p_or:
3300 di_SInst_didiu6_or <"lsr", int_hexagon_S2_lsr_i_p_or>;
3302 // STYPE / SHIFT / Shift right by immediate with rounding.
3303 def HEXAGON_S2_asr_i_r_rnd:
3304 si_SInst_siu5_rnd <"asr", int_hexagon_S2_asr_i_r_rnd>;
3305 def HEXAGON_S2_asr_i_r_rnd_goodsyntax:
3306 si_SInst_siu5 <"asrrnd", int_hexagon_S2_asr_i_r_rnd_goodsyntax>;
3308 // STYPE / SHIFT / Shift left by immediate with saturation.
3309 def HEXAGON_S2_asl_i_r_sat:
3310 si_SInst_sisi_sat <"asl", int_hexagon_S2_asl_i_r_sat>;
3312 // STYPE / SHIFT / Shift by register.
3313 def HEXAGON_S2_asl_r_r:
3314 si_SInst_sisi <"asl", int_hexagon_S2_asl_r_r>;
3315 def HEXAGON_S2_asr_r_r:
3316 si_SInst_sisi <"asr", int_hexagon_S2_asr_r_r>;
3317 def HEXAGON_S2_lsl_r_r:
3318 si_SInst_sisi <"lsl", int_hexagon_S2_lsl_r_r>;
3319 def HEXAGON_S2_lsr_r_r:
3320 si_SInst_sisi <"lsr", int_hexagon_S2_lsr_r_r>;
3321 def HEXAGON_S2_asl_r_p:
3322 di_SInst_disi <"asl", int_hexagon_S2_asl_r_p>;
3323 def HEXAGON_S2_asr_r_p:
3324 di_SInst_disi <"asr", int_hexagon_S2_asr_r_p>;
3325 def HEXAGON_S2_lsl_r_p:
3326 di_SInst_disi <"lsl", int_hexagon_S2_lsl_r_p>;
3327 def HEXAGON_S2_lsr_r_p:
3328 di_SInst_disi <"lsr", int_hexagon_S2_lsr_r_p>;
3330 // STYPE / SHIFT / Shift by register and accumulate.
3331 def HEXAGON_S2_asl_r_r_acc:
3332 si_SInst_sisisi_acc <"asl", int_hexagon_S2_asl_r_r_acc>;
3333 def HEXAGON_S2_asr_r_r_acc:
3334 si_SInst_sisisi_acc <"asr", int_hexagon_S2_asr_r_r_acc>;
3335 def HEXAGON_S2_lsl_r_r_acc:
3336 si_SInst_sisisi_acc <"lsl", int_hexagon_S2_lsl_r_r_acc>;
3337 def HEXAGON_S2_lsr_r_r_acc:
3338 si_SInst_sisisi_acc <"lsr", int_hexagon_S2_lsr_r_r_acc>;
3339 def HEXAGON_S2_asl_r_p_acc:
3340 di_SInst_didisi_acc <"asl", int_hexagon_S2_asl_r_p_acc>;
3341 def HEXAGON_S2_asr_r_p_acc:
3342 di_SInst_didisi_acc <"asr", int_hexagon_S2_asr_r_p_acc>;
3343 def HEXAGON_S2_lsl_r_p_acc:
3344 di_SInst_didisi_acc <"lsl", int_hexagon_S2_lsl_r_p_acc>;
3345 def HEXAGON_S2_lsr_r_p_acc:
3346 di_SInst_didisi_acc <"lsr", int_hexagon_S2_lsr_r_p_acc>;
3348 def HEXAGON_S2_asl_r_r_nac:
3349 si_SInst_sisisi_nac <"asl", int_hexagon_S2_asl_r_r_nac>;
3350 def HEXAGON_S2_asr_r_r_nac:
3351 si_SInst_sisisi_nac <"asr", int_hexagon_S2_asr_r_r_nac>;
3352 def HEXAGON_S2_lsl_r_r_nac:
3353 si_SInst_sisisi_nac <"lsl", int_hexagon_S2_lsl_r_r_nac>;
3354 def HEXAGON_S2_lsr_r_r_nac:
3355 si_SInst_sisisi_nac <"lsr", int_hexagon_S2_lsr_r_r_nac>;
3356 def HEXAGON_S2_asl_r_p_nac:
3357 di_SInst_didisi_nac <"asl", int_hexagon_S2_asl_r_p_nac>;
3358 def HEXAGON_S2_asr_r_p_nac:
3359 di_SInst_didisi_nac <"asr", int_hexagon_S2_asr_r_p_nac>;
3360 def HEXAGON_S2_lsl_r_p_nac:
3361 di_SInst_didisi_nac <"lsl", int_hexagon_S2_lsl_r_p_nac>;
3362 def HEXAGON_S2_lsr_r_p_nac:
3363 di_SInst_didisi_nac <"lsr", int_hexagon_S2_lsr_r_p_nac>;
3365 // STYPE / SHIFT / Shift by register and logical.
3366 def HEXAGON_S2_asl_r_r_and:
3367 si_SInst_sisisi_and <"asl", int_hexagon_S2_asl_r_r_and>;
3368 def HEXAGON_S2_asr_r_r_and:
3369 si_SInst_sisisi_and <"asr", int_hexagon_S2_asr_r_r_and>;
3370 def HEXAGON_S2_lsl_r_r_and:
3371 si_SInst_sisisi_and <"lsl", int_hexagon_S2_lsl_r_r_and>;
3372 def HEXAGON_S2_lsr_r_r_and:
3373 si_SInst_sisisi_and <"lsr", int_hexagon_S2_lsr_r_r_and>;
3375 def HEXAGON_S2_asl_r_r_or:
3376 si_SInst_sisisi_or <"asl", int_hexagon_S2_asl_r_r_or>;
3377 def HEXAGON_S2_asr_r_r_or:
3378 si_SInst_sisisi_or <"asr", int_hexagon_S2_asr_r_r_or>;
3379 def HEXAGON_S2_lsl_r_r_or:
3380 si_SInst_sisisi_or <"lsl", int_hexagon_S2_lsl_r_r_or>;
3381 def HEXAGON_S2_lsr_r_r_or:
3382 si_SInst_sisisi_or <"lsr", int_hexagon_S2_lsr_r_r_or>;
3384 def HEXAGON_S2_asl_r_p_and:
3385 di_SInst_didisi_and <"asl", int_hexagon_S2_asl_r_p_and>;
3386 def HEXAGON_S2_asr_r_p_and:
3387 di_SInst_didisi_and <"asr", int_hexagon_S2_asr_r_p_and>;
3388 def HEXAGON_S2_lsl_r_p_and:
3389 di_SInst_didisi_and <"lsl", int_hexagon_S2_lsl_r_p_and>;
3390 def HEXAGON_S2_lsr_r_p_and:
3391 di_SInst_didisi_and <"lsr", int_hexagon_S2_lsr_r_p_and>;
3393 def HEXAGON_S2_asl_r_p_or:
3394 di_SInst_didisi_or <"asl", int_hexagon_S2_asl_r_p_or>;
3395 def HEXAGON_S2_asr_r_p_or:
3396 di_SInst_didisi_or <"asr", int_hexagon_S2_asr_r_p_or>;
3397 def HEXAGON_S2_lsl_r_p_or:
3398 di_SInst_didisi_or <"lsl", int_hexagon_S2_lsl_r_p_or>;
3399 def HEXAGON_S2_lsr_r_p_or:
3400 di_SInst_didisi_or <"lsr", int_hexagon_S2_lsr_r_p_or>;
3402 // STYPE / SHIFT / Shift by register with saturation.
3403 def HEXAGON_S2_asl_r_r_sat:
3404 si_SInst_sisi_sat <"asl", int_hexagon_S2_asl_r_r_sat>;
3405 def HEXAGON_S2_asr_r_r_sat:
3406 si_SInst_sisi_sat <"asr", int_hexagon_S2_asr_r_r_sat>;
3408 // STYPE / SHIFT / Table Index.
3409 def Hexagon_S2_tableidxb_goodsyntax:
3410 si_MInst_sisiu4u5 <"tableidxb",int_hexagon_S2_tableidxb_goodsyntax>;
3411 def Hexagon_S2_tableidxd_goodsyntax:
3412 si_MInst_sisiu4u5 <"tableidxd",int_hexagon_S2_tableidxd_goodsyntax>;
3413 def Hexagon_S2_tableidxh_goodsyntax:
3414 si_MInst_sisiu4u5 <"tableidxh",int_hexagon_S2_tableidxh_goodsyntax>;
3415 def Hexagon_S2_tableidxw_goodsyntax:
3416 si_MInst_sisiu4u5 <"tableidxw",int_hexagon_S2_tableidxw_goodsyntax>;
3419 /********************************************************************
3421 *********************************************************************/
3423 // STYPE / VH / Vector absolute value halfwords.
3424 // Rdd64=vabsh(Rss64)
3425 def HEXAGON_A2_vabsh:
3426 di_SInst_di <"vabsh", int_hexagon_A2_vabsh>;
3427 def HEXAGON_A2_vabshsat:
3428 di_SInst_di_sat <"vabsh", int_hexagon_A2_vabshsat>;
3430 // STYPE / VH / Vector shift halfwords by immediate.
3431 // Rdd64=v[asl/asr/lsr]h(Rss64,Rt32)
3432 def HEXAGON_S2_asl_i_vh:
3433 di_SInst_disi <"vaslh", int_hexagon_S2_asl_i_vh>;
3434 def HEXAGON_S2_asr_i_vh:
3435 di_SInst_disi <"vasrh", int_hexagon_S2_asr_i_vh>;
3436 def HEXAGON_S2_lsr_i_vh:
3437 di_SInst_disi <"vlsrh", int_hexagon_S2_lsr_i_vh>;
3439 // STYPE / VH / Vector shift halfwords by register.
3440 // Rdd64=v[asl/asr/lsl/lsr]w(Rss64,Rt32)
3441 def HEXAGON_S2_asl_r_vh:
3442 di_SInst_disi <"vaslh", int_hexagon_S2_asl_r_vh>;
3443 def HEXAGON_S2_asr_r_vh:
3444 di_SInst_disi <"vasrh", int_hexagon_S2_asr_r_vh>;
3445 def HEXAGON_S2_lsl_r_vh:
3446 di_SInst_disi <"vlslh", int_hexagon_S2_lsl_r_vh>;
3447 def HEXAGON_S2_lsr_r_vh:
3448 di_SInst_disi <"vlsrh", int_hexagon_S2_lsr_r_vh>;
3451 /********************************************************************
3453 *********************************************************************/
3455 // STYPE / VW / Vector absolute value words.
3456 def HEXAGON_A2_vabsw:
3457 di_SInst_di <"vabsw", int_hexagon_A2_vabsw>;
3458 def HEXAGON_A2_vabswsat:
3459 di_SInst_di_sat <"vabsw", int_hexagon_A2_vabswsat>;
3461 // STYPE / VW / Vector shift words by immediate.
3462 // Rdd64=v[asl/vsl]w(Rss64,Rt32)
3463 def HEXAGON_S2_asl_i_vw:
3464 di_SInst_disi <"vaslw", int_hexagon_S2_asl_i_vw>;
3465 def HEXAGON_S2_asr_i_vw:
3466 di_SInst_disi <"vasrw", int_hexagon_S2_asr_i_vw>;
3467 def HEXAGON_S2_lsr_i_vw:
3468 di_SInst_disi <"vlsrw", int_hexagon_S2_lsr_i_vw>;
3470 // STYPE / VW / Vector shift words by register.
3471 // Rdd64=v[asl/vsl]w(Rss64,Rt32)
3472 def HEXAGON_S2_asl_r_vw:
3473 di_SInst_disi <"vaslw", int_hexagon_S2_asl_r_vw>;
3474 def HEXAGON_S2_asr_r_vw:
3475 di_SInst_disi <"vasrw", int_hexagon_S2_asr_r_vw>;
3476 def HEXAGON_S2_lsl_r_vw:
3477 di_SInst_disi <"vlslw", int_hexagon_S2_lsl_r_vw>;
3478 def HEXAGON_S2_lsr_r_vw:
3479 di_SInst_disi <"vlsrw", int_hexagon_S2_lsr_r_vw>;
3481 // STYPE / VW / Vector shift words with truncate and pack.
3482 def HEXAGON_S2_asr_r_svw_trun:
3483 si_SInst_disi <"vasrw", int_hexagon_S2_asr_r_svw_trun>;
3484 def HEXAGON_S2_asr_i_svw_trun:
3485 si_SInst_diu5 <"vasrw", int_hexagon_S2_asr_i_svw_trun>;
3487 // LD / Circular loads.
3488 def HEXAGON_circ_ldd:
3489 di_LDInstPI_diu4 <"circ_ldd", int_hexagon_circ_ldd>;
3491 include "HexagonIntrinsicsV3.td"
3492 include "HexagonIntrinsicsV4.td"
3493 include "HexagonIntrinsicsV5.td"