1 //=- HexagonInstrInfoV5.td - Target Desc. for Hexagon Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Hexagon V5 instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
18 let isCodeGenOnly = 0 in
19 def S2_asr_i_p_rnd : S_2OpInstImm<"asr", 0b110, 0b111, u6Imm,
21 (sra (i64 (add (i64 (sra I64:$src1, u6ImmPred:$src2)), 1)),
25 let Inst{13-8} = src2;
28 let isCodeGenOnly = 0 in
29 def C4_fastcorner9 : T_LOGICAL_2OP<"fastcorner9", 0b000, 0, 0>,
31 let Inst{13,7,4} = 0b111;
34 let isCodeGenOnly = 0 in
35 def C4_fastcorner9_not : T_LOGICAL_2OP<"!fastcorner9", 0b000, 0, 0>,
37 let Inst{20,13,7,4} = 0b1111;
40 def SDTHexagonFCONST32 : SDTypeProfile<1, 1, [
43 def HexagonFCONST32 : SDNode<"HexagonISD::FCONST32", SDTHexagonFCONST32>;
45 let isReMaterializable = 1, isMoveImm = 1 in
46 def FCONST32_nsdata : LDInst<(outs IntRegs:$dst), (ins globaladdress:$global),
47 "$dst = CONST32(#$global)",
48 [(set (f32 IntRegs:$dst),
49 (HexagonFCONST32 tglobaladdr:$global))]>,
52 let isReMaterializable = 1, isMoveImm = 1 in
53 def CONST64_Float_Real : LDInst<(outs DoubleRegs:$dst), (ins f64imm:$src1),
54 "$dst = CONST64(#$src1)",
55 [(set DoubleRegs:$dst, fpimm:$src1)]>,
58 let isReMaterializable = 1, isMoveImm = 1 in
59 def CONST32_Float_Real : LDInst<(outs IntRegs:$dst), (ins f32imm:$src1),
60 "$dst = CONST32(#$src1)",
61 [(set IntRegs:$dst, fpimm:$src1)]>,
64 // Transfer immediate float.
65 // Only works with single precision fp value.
66 // For double precision, use CONST64_float_real, as 64bit transfer
67 // can only hold 40-bit values - 32 from const ext + 8 bit immediate.
68 // Make sure that complexity is more than the CONST32 pattern in
69 // HexagonInstrInfo.td patterns.
70 let isExtended = 1, opExtendable = 1, isMoveImm = 1, isReMaterializable = 1,
71 isPredicable = 1, AddedComplexity = 30, validSubTargets = HasV5SubT,
73 def TFRI_f : ALU32_ri<(outs IntRegs:$dst), (ins f32Ext:$src1),
75 [(set IntRegs:$dst, fpimm:$src1)]>,
78 let isExtended = 1, opExtendable = 2, isPredicated = 1,
79 hasSideEffects = 0, validSubTargets = HasV5SubT in
80 def TFRI_cPt_f : ALU32_ri<(outs IntRegs:$dst),
81 (ins PredRegs:$src1, f32Ext:$src2),
82 "if ($src1) $dst = #$src2",
86 let isExtended = 1, opExtendable = 2, isPredicated = 1, isPredicatedFalse = 1,
87 hasSideEffects = 0, validSubTargets = HasV5SubT in
88 def TFRI_cNotPt_f : ALU32_ri<(outs IntRegs:$dst),
89 (ins PredRegs:$src1, f32Ext:$src2),
90 "if (!$src1) $dst =#$src2",
94 def SDTHexagonI32I64: SDTypeProfile<1, 1, [SDTCisVT<0, i32>,
97 def HexagonPOPCOUNT: SDNode<"HexagonISD::POPCOUNT", SDTHexagonI32I64>;
99 let hasNewValue = 1, validSubTargets = HasV5SubT, isCodeGenOnly = 0 in
100 def S5_popcountp : ALU64_rr<(outs IntRegs:$Rd), (ins DoubleRegs:$Rss),
101 "$Rd = popcount($Rss)",
102 [(set I32:$Rd, (HexagonPOPCOUNT I64:$Rss))], "", S_2op_tc_2_SLOT23>,
109 let Inst{27-21} = 0b1000011;
110 let Inst{7-5} = 0b011;
112 let Inst{20-16} = Rss;
115 let isFP = 1, hasNewValue = 1, opNewValue = 0 in
116 class T_MInstFloat <string mnemonic, bits<3> MajOp, bits<3> MinOp>
117 : MInst<(outs IntRegs:$Rd),
118 (ins IntRegs:$Rs, IntRegs:$Rt),
119 "$Rd = "#mnemonic#"($Rs, $Rt)", [],
120 "" , M_tc_3or4x_SLOT23 > ,
128 let Inst{27-24} = 0b1011;
129 let Inst{23-21} = MajOp;
130 let Inst{20-16} = Rs;
133 let Inst{7-5} = MinOp;
137 let isCommutable = 1, isCodeGenOnly = 0 in {
138 def F2_sfadd : T_MInstFloat < "sfadd", 0b000, 0b000>;
139 def F2_sfmpy : T_MInstFloat < "sfmpy", 0b010, 0b000>;
142 let isCodeGenOnly = 0 in
143 def F2_sfsub : T_MInstFloat < "sfsub", 0b000, 0b001>;
145 let Itinerary = M_tc_3x_SLOT23, isCodeGenOnly = 0 in {
146 def F2_sfmax : T_MInstFloat < "sfmax", 0b100, 0b000>;
147 def F2_sfmin : T_MInstFloat < "sfmin", 0b100, 0b001>;
150 let isCodeGenOnly = 0 in {
151 def F2_sffixupn : T_MInstFloat < "sffixupn", 0b110, 0b000>;
152 def F2_sffixupd : T_MInstFloat < "sffixupd", 0b110, 0b001>;
155 // F2_sfrecipa: Reciprocal approximation for division.
156 let isPredicateLate = 1, isFP = 1,
157 hasSideEffects = 0, hasNewValue = 1, isCodeGenOnly = 0 in
158 def F2_sfrecipa: MInst <
159 (outs IntRegs:$Rd, PredRegs:$Pe),
160 (ins IntRegs:$Rs, IntRegs:$Rt),
161 "$Rd, $Pe = sfrecipa($Rs, $Rt)">,
169 let Inst{27-21} = 0b1011111;
170 let Inst{20-16} = Rs;
178 // F2_dfcmpeq: Floating point compare for equal.
179 let isCompare = 1, isFP = 1 in
180 class T_fcmp <string mnemonic, RegisterClass RC, bits<3> MinOp,
181 list<dag> pattern = [] >
182 : ALU64Inst <(outs PredRegs:$dst), (ins RC:$src1, RC:$src2),
183 "$dst = "#mnemonic#"($src1, $src2)", pattern,
184 "" , ALU64_tc_2early_SLOT23 > ,
192 let Inst{27-21} = 0b0010111;
193 let Inst{20-16} = src1;
194 let Inst{12-8} = src2;
195 let Inst{7-5} = MinOp;
199 class T_fcmp64 <string mnemonic, PatFrag OpNode, bits<3> MinOp>
200 : T_fcmp <mnemonic, DoubleRegs, MinOp,
201 [(set I1:$dst, (OpNode F64:$src1, F64:$src2))]> {
203 let Inst{27-21} = 0b0010111;
206 class T_fcmp32 <string mnemonic, PatFrag OpNode, bits<3> MinOp>
207 : T_fcmp <mnemonic, IntRegs, MinOp,
208 [(set I1:$dst, (OpNode F32:$src1, F32:$src2))]> {
210 let Inst{27-21} = 0b0111111;
213 let isCodeGenOnly = 0 in {
214 def F2_dfcmpeq : T_fcmp64<"dfcmp.eq", setoeq, 0b000>;
215 def F2_dfcmpgt : T_fcmp64<"dfcmp.gt", setogt, 0b001>;
216 def F2_dfcmpge : T_fcmp64<"dfcmp.ge", setoge, 0b010>;
217 def F2_dfcmpuo : T_fcmp64<"dfcmp.uo", setuo, 0b011>;
219 def F2_sfcmpge : T_fcmp32<"sfcmp.ge", setoge, 0b000>;
220 def F2_sfcmpuo : T_fcmp32<"sfcmp.uo", setuo, 0b001>;
221 def F2_sfcmpeq : T_fcmp32<"sfcmp.eq", setoeq, 0b011>;
222 def F2_sfcmpgt : T_fcmp32<"sfcmp.gt", setogt, 0b100>;
225 // F2 convert template classes:
227 class F2_RDD_RSS_CONVERT<string mnemonic, bits<3> MinOp,
228 SDNode Op, PatLeaf RCOut, PatLeaf RCIn,
230 : SInst <(outs DoubleRegs:$Rdd), (ins DoubleRegs:$Rss),
231 "$Rdd = "#mnemonic#"($Rss)"#chop,
232 [(set RCOut:$Rdd, (Op RCIn:$Rss))], "",
233 S_2op_tc_3or4x_SLOT23> {
239 let Inst{27-21} = 0b0000111;
240 let Inst{20-16} = Rss;
241 let Inst{7-5} = MinOp;
246 class F2_RDD_RS_CONVERT<string mnemonic, bits<3> MinOp,
247 SDNode Op, PatLeaf RCOut, PatLeaf RCIn,
249 : SInst <(outs DoubleRegs:$Rdd), (ins IntRegs:$Rs),
250 "$Rdd = "#mnemonic#"($Rs)"#chop,
251 [(set RCOut:$Rdd, (Op RCIn:$Rs))], "",
252 S_2op_tc_3or4x_SLOT23> {
258 let Inst{27-21} = 0b0100100;
259 let Inst{20-16} = Rs;
260 let Inst{7-5} = MinOp;
264 let isFP = 1, hasNewValue = 1 in
265 class F2_RD_RSS_CONVERT<string mnemonic, bits<3> MinOp,
266 SDNode Op, PatLeaf RCOut, PatLeaf RCIn,
268 : SInst <(outs IntRegs:$Rd), (ins DoubleRegs:$Rss),
269 "$Rd = "#mnemonic#"($Rss)"#chop,
270 [(set RCOut:$Rd, (Op RCIn:$Rss))], "",
271 S_2op_tc_3or4x_SLOT23> {
277 let Inst{27-24} = 0b1000;
278 let Inst{23-21} = MinOp;
279 let Inst{20-16} = Rss;
280 let Inst{7-5} = 0b001;
284 let isFP = 1, hasNewValue = 1 in
285 class F2_RD_RS_CONVERT<string mnemonic, bits<3> MajOp, bits<3> MinOp,
286 SDNode Op, PatLeaf RCOut, PatLeaf RCIn,
288 : SInst <(outs IntRegs:$Rd), (ins IntRegs:$Rs),
289 "$Rd = "#mnemonic#"($Rs)"#chop,
290 [(set RCOut:$Rd, (Op RCIn:$Rs))], "",
291 S_2op_tc_3or4x_SLOT23> {
297 let Inst{27-24} = 0b1011;
298 let Inst{23-21} = MajOp;
299 let Inst{20-16} = Rs;
300 let Inst{7-5} = MinOp;
304 // Convert single precision to double precision and vice-versa.
305 let isCodeGenOnly = 0 in {
306 def F2_conv_sf2df : F2_RDD_RS_CONVERT <"convert_sf2df", 0b000,
309 def F2_conv_df2sf : F2_RD_RSS_CONVERT <"convert_df2sf", 0b000,
312 // Convert Integer to Floating Point.
313 def F2_conv_d2sf : F2_RD_RSS_CONVERT <"convert_d2sf", 0b010,
314 sint_to_fp, F32, I64>;
315 def F2_conv_ud2sf : F2_RD_RSS_CONVERT <"convert_ud2sf", 0b001,
316 uint_to_fp, F32, I64>;
317 def F2_conv_uw2sf : F2_RD_RS_CONVERT <"convert_uw2sf", 0b001, 0b000,
318 uint_to_fp, F32, I32>;
319 def F2_conv_w2sf : F2_RD_RS_CONVERT <"convert_w2sf", 0b010, 0b000,
320 sint_to_fp, F32, I32>;
321 def F2_conv_d2df : F2_RDD_RSS_CONVERT <"convert_d2df", 0b011,
322 sint_to_fp, F64, I64>;
323 def F2_conv_ud2df : F2_RDD_RSS_CONVERT <"convert_ud2df", 0b010,
324 uint_to_fp, F64, I64>;
325 def F2_conv_uw2df : F2_RDD_RS_CONVERT <"convert_uw2df", 0b001,
326 uint_to_fp, F64, I32>;
327 def F2_conv_w2df : F2_RDD_RS_CONVERT <"convert_w2df", 0b010,
328 sint_to_fp, F64, I32>;
330 // Convert Floating Point to Integer - default.
331 def F2_conv_df2uw_chop : F2_RD_RSS_CONVERT <"convert_df2uw", 0b101,
332 fp_to_uint, I32, F64, ":chop">;
333 def F2_conv_df2w_chop : F2_RD_RSS_CONVERT <"convert_df2w", 0b111,
334 fp_to_sint, I32, F64, ":chop">;
335 def F2_conv_sf2uw_chop : F2_RD_RS_CONVERT <"convert_sf2uw", 0b011, 0b001,
336 fp_to_uint, I32, F32, ":chop">;
337 def F2_conv_sf2w_chop : F2_RD_RS_CONVERT <"convert_sf2w", 0b100, 0b001,
338 fp_to_sint, I32, F32, ":chop">;
339 def F2_conv_df2d_chop : F2_RDD_RSS_CONVERT <"convert_df2d", 0b110,
340 fp_to_sint, I64, F64, ":chop">;
341 def F2_conv_df2ud_chop : F2_RDD_RSS_CONVERT <"convert_df2ud", 0b111,
342 fp_to_uint, I64, F64, ":chop">;
343 def F2_conv_sf2d_chop : F2_RDD_RS_CONVERT <"convert_sf2d", 0b110,
344 fp_to_sint, I64, F32, ":chop">;
345 def F2_conv_sf2ud_chop : F2_RDD_RS_CONVERT <"convert_sf2ud", 0b101,
346 fp_to_uint, I64, F32, ":chop">;
348 // Convert Floating Point to Integer: non-chopped.
349 let AddedComplexity = 20, Predicates = [HasV5T, IEEERndNearV5T] in {
350 def F2_conv_df2d : F2_RDD_RSS_CONVERT <"convert_df2d", 0b000,
351 fp_to_sint, I64, F64>;
352 def F2_conv_df2ud : F2_RDD_RSS_CONVERT <"convert_df2ud", 0b001,
353 fp_to_uint, I64, F64>;
354 def F2_conv_sf2ud : F2_RDD_RS_CONVERT <"convert_sf2ud", 0b011,
355 fp_to_uint, I64, F32>;
356 def F2_conv_sf2d : F2_RDD_RS_CONVERT <"convert_sf2d", 0b100,
357 fp_to_sint, I64, F32>;
358 def F2_conv_df2uw : F2_RD_RSS_CONVERT <"convert_df2uw", 0b011,
359 fp_to_uint, I32, F64>;
360 def F2_conv_df2w : F2_RD_RSS_CONVERT <"convert_df2w", 0b100,
361 fp_to_sint, I32, F64>;
362 def F2_conv_sf2uw : F2_RD_RS_CONVERT <"convert_sf2uw", 0b011, 0b000,
363 fp_to_uint, I32, F32>;
364 def F2_conv_sf2w : F2_RD_RS_CONVERT <"convert_sf2w", 0b100, 0b000,
365 fp_to_sint, I32, F32>;
370 let isFP = 1, hasNewValue = 1, isCodeGenOnly = 0 in
371 def F2_sffixupr: SInst<(outs IntRegs:$Rd), (ins IntRegs:$Rs),
372 "$Rd = sffixupr($Rs)",
373 [], "" , S_2op_tc_3or4x_SLOT23>, Requires<[HasV5T]> {
379 let Inst{27-21} = 0b1011101;
380 let Inst{20-16} = Rs;
381 let Inst{7-5} = 0b000;
385 // F2_sffma: Floating-point fused multiply add.
386 let isFP = 1, hasNewValue = 1 in
387 class T_sfmpy_acc <bit isSub, bit isLib>
388 : MInst<(outs IntRegs:$Rx),
389 (ins IntRegs:$dst2, IntRegs:$Rs, IntRegs:$Rt),
390 "$Rx "#!if(isSub, "-=","+=")#" sfmpy($Rs, $Rt)"#!if(isLib, ":lib",""),
391 [], "$dst2 = $Rx" , M_tc_3_SLOT23 > ,
399 let Inst{27-21} = 0b1111000;
400 let Inst{20-16} = Rs;
409 let isCodeGenOnly = 0 in {
410 def F2_sffma: T_sfmpy_acc <0, 0>;
411 def F2_sffms: T_sfmpy_acc <1, 0>;
412 def F2_sffma_lib: T_sfmpy_acc <0, 1>;
413 def F2_sffms_lib: T_sfmpy_acc <1, 1>;
416 // Floating-point fused multiply add w/ additional scaling (2**pu).
417 let isFP = 1, hasNewValue = 1, isCodeGenOnly = 0 in
418 def F2_sffma_sc: MInst <
420 (ins IntRegs:$dst2, IntRegs:$Rs, IntRegs:$Rt, PredRegs:$Pu),
421 "$Rx += sfmpy($Rs, $Rt, $Pu):scale" ,
422 [], "$dst2 = $Rx" , M_tc_3_SLOT23 > ,
431 let Inst{27-21} = 0b1111011;
432 let Inst{20-16} = Rs;
440 // Classify floating-point value
441 let isFP = 1, isCodeGenOnly = 0 in
442 def F2_sfclass : T_TEST_BIT_IMM<"sfclass", 0b111>;
444 let isFP = 1, isCodeGenOnly = 0 in
445 def F2_dfclass: ALU64Inst<(outs PredRegs:$Pd), (ins DoubleRegs:$Rss, u5Imm:$u5),
446 "$Pd = dfclass($Rss, #$u5)",
447 [], "" , ALU64_tc_2early_SLOT23 > , Requires<[HasV5T]> {
453 let Inst{27-21} = 0b1100100;
454 let Inst{20-16} = Rss;
455 let Inst{12-10} = 0b000;
457 let Inst{4-3} = 0b10;
461 // Instructions to create floating point constant
462 let hasNewValue = 1, opNewValue = 0 in
463 class T_fimm <string mnemonic, RegisterClass RC, bits<4> RegType, bit isNeg>
464 : ALU64Inst<(outs RC:$dst), (ins u10Imm:$src),
465 "$dst = "#mnemonic#"(#$src)"#!if(isNeg, ":neg", ":pos"),
466 [], "", ALU64_tc_3x_SLOT23>, Requires<[HasV5T]> {
471 let Inst{27-24} = RegType;
473 let Inst{22} = isNeg;
474 let Inst{21} = src{9};
475 let Inst{13-5} = src{8-0};
479 let isCodeGenOnly = 0 in {
480 def F2_sfimm_p : T_fimm <"sfmake", IntRegs, 0b0110, 0>;
481 def F2_sfimm_n : T_fimm <"sfmake", IntRegs, 0b0110, 1>;
482 def F2_dfimm_p : T_fimm <"dfmake", DoubleRegs, 0b1001, 0>;
483 def F2_dfimm_n : T_fimm <"dfmake", DoubleRegs, 0b1001, 1>;
486 // Convert single precision to double precision and vice-versa.
487 def CONVERT_sf2df : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src),
488 "$dst = convert_sf2df($src)",
489 [(set DoubleRegs:$dst, (fextend IntRegs:$src))]>,
492 def CONVERT_df2sf : ALU64_rr<(outs IntRegs:$dst), (ins DoubleRegs:$src),
493 "$dst = convert_df2sf($src)",
494 [(set IntRegs:$dst, (fround DoubleRegs:$src))]>,
499 def LDrid_f : LDInst<(outs DoubleRegs:$dst),
501 "$dst = memd($addr)",
502 [(set DoubleRegs:$dst, (f64 (load ADDRriS11_3:$addr)))]>,
506 let AddedComplexity = 20 in
507 def LDrid_indexed_f : LDInst<(outs DoubleRegs:$dst),
508 (ins IntRegs:$src1, s11_3Imm:$offset),
509 "$dst = memd($src1+#$offset)",
510 [(set DoubleRegs:$dst, (f64 (load (add IntRegs:$src1,
511 s11_3ImmPred:$offset))))]>,
514 def LDriw_f : LDInst<(outs IntRegs:$dst),
515 (ins MEMri:$addr), "$dst = memw($addr)",
516 [(set IntRegs:$dst, (f32 (load ADDRriS11_2:$addr)))]>,
520 let AddedComplexity = 20 in
521 def LDriw_indexed_f : LDInst<(outs IntRegs:$dst),
522 (ins IntRegs:$src1, s11_2Imm:$offset),
523 "$dst = memw($src1+#$offset)",
524 [(set IntRegs:$dst, (f32 (load (add IntRegs:$src1,
525 s11_2ImmPred:$offset))))]>,
529 def STriw_f : STInst<(outs),
530 (ins MEMri:$addr, IntRegs:$src1),
531 "memw($addr) = $src1",
532 [(store (f32 IntRegs:$src1), ADDRriS11_2:$addr)]>,
535 let AddedComplexity = 10 in
536 def STriw_indexed_f : STInst<(outs),
537 (ins IntRegs:$src1, s11_2Imm:$src2, IntRegs:$src3),
538 "memw($src1+#$src2) = $src3",
539 [(store (f32 IntRegs:$src3),
540 (add IntRegs:$src1, s11_2ImmPred:$src2))]>,
543 def STrid_f : STInst<(outs),
544 (ins MEMri:$addr, DoubleRegs:$src1),
545 "memd($addr) = $src1",
546 [(store (f64 DoubleRegs:$src1), ADDRriS11_2:$addr)]>,
549 // Indexed store double word.
550 let AddedComplexity = 10 in
551 def STrid_indexed_f : STInst<(outs),
552 (ins IntRegs:$src1, s11_3Imm:$src2, DoubleRegs:$src3),
553 "memd($src1+#$src2) = $src3",
554 [(store (f64 DoubleRegs:$src3),
555 (add IntRegs:$src1, s11_3ImmPred:$src2))]>,
560 let isCommutable = 1 in
561 def fADD_rr : ALU64_rr<(outs IntRegs:$dst),
562 (ins IntRegs:$src1, IntRegs:$src2),
563 "$dst = sfadd($src1, $src2)",
564 [(set IntRegs:$dst, (fadd IntRegs:$src1, IntRegs:$src2))]>,
567 let isCommutable = 1 in
568 def fADD64_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
570 "$dst = dfadd($src1, $src2)",
571 [(set DoubleRegs:$dst, (fadd DoubleRegs:$src1,
572 DoubleRegs:$src2))]>,
575 def fSUB_rr : ALU64_rr<(outs IntRegs:$dst),
576 (ins IntRegs:$src1, IntRegs:$src2),
577 "$dst = sfsub($src1, $src2)",
578 [(set IntRegs:$dst, (fsub IntRegs:$src1, IntRegs:$src2))]>,
581 def fSUB64_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
583 "$dst = dfsub($src1, $src2)",
584 [(set DoubleRegs:$dst, (fsub DoubleRegs:$src1,
585 DoubleRegs:$src2))]>,
588 let isCommutable = 1 in
589 def fMUL_rr : ALU64_rr<(outs IntRegs:$dst),
590 (ins IntRegs:$src1, IntRegs:$src2),
591 "$dst = sfmpy($src1, $src2)",
592 [(set IntRegs:$dst, (fmul IntRegs:$src1, IntRegs:$src2))]>,
595 let isCommutable = 1 in
596 def fMUL64_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
598 "$dst = dfmpy($src1, $src2)",
599 [(set DoubleRegs:$dst, (fmul DoubleRegs:$src1,
600 DoubleRegs:$src2))]>,
604 let isCompare = 1 in {
605 multiclass FCMP64_rr<string OpcStr, PatFrag OpNode> {
606 def _rr : ALU64_rr<(outs PredRegs:$dst), (ins DoubleRegs:$b, DoubleRegs:$c),
607 !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
609 (OpNode (f64 DoubleRegs:$b), (f64 DoubleRegs:$c)))]>,
613 multiclass FCMP32_rr<string OpcStr, PatFrag OpNode> {
614 def _rr : ALU64_rr<(outs PredRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
615 !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
617 (OpNode (f32 IntRegs:$b), (f32 IntRegs:$c)))]>,
622 defm FCMPOEQ64 : FCMP64_rr<"dfcmp.eq", setoeq>;
623 defm FCMPUEQ64 : FCMP64_rr<"dfcmp.eq", setueq>;
624 defm FCMPOGT64 : FCMP64_rr<"dfcmp.gt", setogt>;
625 defm FCMPUGT64 : FCMP64_rr<"dfcmp.gt", setugt>;
626 defm FCMPOGE64 : FCMP64_rr<"dfcmp.ge", setoge>;
627 defm FCMPUGE64 : FCMP64_rr<"dfcmp.ge", setuge>;
629 defm FCMPOEQ32 : FCMP32_rr<"sfcmp.eq", setoeq>;
630 defm FCMPUEQ32 : FCMP32_rr<"sfcmp.eq", setueq>;
631 defm FCMPOGT32 : FCMP32_rr<"sfcmp.gt", setogt>;
632 defm FCMPUGT32 : FCMP32_rr<"sfcmp.gt", setugt>;
633 defm FCMPOGE32 : FCMP32_rr<"sfcmp.ge", setoge>;
634 defm FCMPUGE32 : FCMP32_rr<"sfcmp.ge", setuge>;
637 def : Pat <(i1 (setolt (f32 IntRegs:$src1), (f32 IntRegs:$src2))),
638 (i1 (FCMPOGT32_rr IntRegs:$src2, IntRegs:$src1))>,
641 def : Pat <(i1 (setolt (f32 IntRegs:$src1), (fpimm:$src2))),
642 (i1 (FCMPOGT32_rr (f32 (TFRI_f fpimm:$src2)), (f32 IntRegs:$src1)))>,
645 def : Pat <(i1 (setolt (f64 DoubleRegs:$src1), (f64 DoubleRegs:$src2))),
646 (i1 (FCMPOGT64_rr DoubleRegs:$src2, DoubleRegs:$src1))>,
649 def : Pat <(i1 (setolt (f64 DoubleRegs:$src1), (fpimm:$src2))),
650 (i1 (FCMPOGT64_rr (f64 (CONST64_Float_Real fpimm:$src2)),
651 (f64 DoubleRegs:$src1)))>,
655 def : Pat <(i1 (setugt (f64 DoubleRegs:$src1), (fpimm:$src2))),
656 (i1 (FCMPUGT64_rr (f64 DoubleRegs:$src1),
657 (f64 (CONST64_Float_Real fpimm:$src2))))>,
660 def : Pat <(i1 (setugt (f32 IntRegs:$src1), (fpimm:$src2))),
661 (i1 (FCMPUGT32_rr (f32 IntRegs:$src1), (f32 (TFRI_f fpimm:$src2))))>,
665 def : Pat <(i1 (setult (f32 IntRegs:$src1), (f32 IntRegs:$src2))),
666 (i1 (FCMPUGT32_rr IntRegs:$src2, IntRegs:$src1))>,
669 def : Pat <(i1 (setult (f32 IntRegs:$src1), (fpimm:$src2))),
670 (i1 (FCMPUGT32_rr (f32 (TFRI_f fpimm:$src2)), (f32 IntRegs:$src1)))>,
673 def : Pat <(i1 (setult (f64 DoubleRegs:$src1), (f64 DoubleRegs:$src2))),
674 (i1 (FCMPUGT64_rr DoubleRegs:$src2, DoubleRegs:$src1))>,
677 def : Pat <(i1 (setult (f64 DoubleRegs:$src1), (fpimm:$src2))),
678 (i1 (FCMPUGT64_rr (f64 (CONST64_Float_Real fpimm:$src2)),
679 (f64 DoubleRegs:$src1)))>,
683 // rs <= rt -> rt >= rs.
684 def : Pat<(i1 (setole (f32 IntRegs:$src1), (f32 IntRegs:$src2))),
685 (i1 (FCMPOGE32_rr IntRegs:$src2, IntRegs:$src1))>,
688 def : Pat<(i1 (setole (f32 IntRegs:$src1), (fpimm:$src2))),
689 (i1 (FCMPOGE32_rr (f32 (TFRI_f fpimm:$src2)), IntRegs:$src1))>,
693 // Rss <= Rtt -> Rtt >= Rss.
694 def : Pat<(i1 (setole (f64 DoubleRegs:$src1), (f64 DoubleRegs:$src2))),
695 (i1 (FCMPOGE64_rr DoubleRegs:$src2, DoubleRegs:$src1))>,
698 def : Pat<(i1 (setole (f64 DoubleRegs:$src1), (fpimm:$src2))),
699 (i1 (FCMPOGE64_rr (f64 (CONST64_Float_Real fpimm:$src2)),
703 // rs <= rt -> rt >= rs.
704 def : Pat<(i1 (setule (f32 IntRegs:$src1), (f32 IntRegs:$src2))),
705 (i1 (FCMPUGE32_rr IntRegs:$src2, IntRegs:$src1))>,
708 def : Pat<(i1 (setule (f32 IntRegs:$src1), (fpimm:$src2))),
709 (i1 (FCMPUGE32_rr (f32 (TFRI_f fpimm:$src2)), IntRegs:$src1))>,
712 // Rss <= Rtt -> Rtt >= Rss.
713 def : Pat<(i1 (setule (f64 DoubleRegs:$src1), (f64 DoubleRegs:$src2))),
714 (i1 (FCMPUGE64_rr DoubleRegs:$src2, DoubleRegs:$src1))>,
717 def : Pat<(i1 (setule (f64 DoubleRegs:$src1), (fpimm:$src2))),
718 (i1 (FCMPUGE64_rr (f64 (CONST64_Float_Real fpimm:$src2)),
723 def : Pat<(i1 (setone (f32 IntRegs:$src1), (f32 IntRegs:$src2))),
724 (i1 (C2_not (FCMPOEQ32_rr IntRegs:$src1, IntRegs:$src2)))>,
727 def : Pat<(i1 (setone (f64 DoubleRegs:$src1), (f64 DoubleRegs:$src2))),
728 (i1 (C2_not (FCMPOEQ64_rr DoubleRegs:$src1, DoubleRegs:$src2)))>,
731 def : Pat<(i1 (setune (f32 IntRegs:$src1), (f32 IntRegs:$src2))),
732 (i1 (C2_not (FCMPUEQ32_rr IntRegs:$src1, IntRegs:$src2)))>,
735 def : Pat<(i1 (setune (f64 DoubleRegs:$src1), (f64 DoubleRegs:$src2))),
736 (i1 (C2_not (FCMPUEQ64_rr DoubleRegs:$src1, DoubleRegs:$src2)))>,
739 def : Pat<(i1 (setone (f32 IntRegs:$src1), (fpimm:$src2))),
740 (i1 (C2_not (FCMPOEQ32_rr IntRegs:$src1, (f32 (TFRI_f fpimm:$src2)))))>,
743 def : Pat<(i1 (setone (f64 DoubleRegs:$src1), (fpimm:$src2))),
744 (i1 (C2_not (FCMPOEQ64_rr DoubleRegs:$src1,
745 (f64 (CONST64_Float_Real fpimm:$src2)))))>,
748 def : Pat<(i1 (setune (f32 IntRegs:$src1), (fpimm:$src2))),
749 (i1 (C2_not (FCMPUEQ32_rr IntRegs:$src1, (f32 (TFRI_f fpimm:$src2)))))>,
752 def : Pat<(i1 (setune (f64 DoubleRegs:$src1), (fpimm:$src2))),
753 (i1 (C2_not (FCMPUEQ64_rr DoubleRegs:$src1,
754 (f64 (CONST64_Float_Real fpimm:$src2)))))>,
757 // Convert Integer to Floating Point.
758 def CONVERT_d2sf : ALU64_rr<(outs IntRegs:$dst), (ins DoubleRegs:$src),
759 "$dst = convert_d2sf($src)",
760 [(set (f32 IntRegs:$dst), (sint_to_fp (i64 DoubleRegs:$src)))]>,
763 def CONVERT_ud2sf : ALU64_rr<(outs IntRegs:$dst), (ins DoubleRegs:$src),
764 "$dst = convert_ud2sf($src)",
765 [(set (f32 IntRegs:$dst), (uint_to_fp (i64 DoubleRegs:$src)))]>,
768 def CONVERT_uw2sf : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src),
769 "$dst = convert_uw2sf($src)",
770 [(set (f32 IntRegs:$dst), (uint_to_fp (i32 IntRegs:$src)))]>,
773 def CONVERT_w2sf : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src),
774 "$dst = convert_w2sf($src)",
775 [(set (f32 IntRegs:$dst), (sint_to_fp (i32 IntRegs:$src)))]>,
778 def CONVERT_d2df : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src),
779 "$dst = convert_d2df($src)",
780 [(set (f64 DoubleRegs:$dst), (sint_to_fp (i64 DoubleRegs:$src)))]>,
783 def CONVERT_ud2df : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src),
784 "$dst = convert_ud2df($src)",
785 [(set (f64 DoubleRegs:$dst), (uint_to_fp (i64 DoubleRegs:$src)))]>,
788 def CONVERT_uw2df : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src),
789 "$dst = convert_uw2df($src)",
790 [(set (f64 DoubleRegs:$dst), (uint_to_fp (i32 IntRegs:$src)))]>,
793 def CONVERT_w2df : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src),
794 "$dst = convert_w2df($src)",
795 [(set (f64 DoubleRegs:$dst), (sint_to_fp (i32 IntRegs:$src)))]>,
798 // Convert Floating Point to Integer - default.
799 def CONVERT_df2uw : ALU64_rr<(outs IntRegs:$dst), (ins DoubleRegs:$src),
800 "$dst = convert_df2uw($src):chop",
801 [(set (i32 IntRegs:$dst), (fp_to_uint (f64 DoubleRegs:$src)))]>,
804 def CONVERT_df2w : ALU64_rr<(outs IntRegs:$dst), (ins DoubleRegs:$src),
805 "$dst = convert_df2w($src):chop",
806 [(set (i32 IntRegs:$dst), (fp_to_sint (f64 DoubleRegs:$src)))]>,
809 def CONVERT_sf2uw : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src),
810 "$dst = convert_sf2uw($src):chop",
811 [(set (i32 IntRegs:$dst), (fp_to_uint (f32 IntRegs:$src)))]>,
814 def CONVERT_sf2w : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src),
815 "$dst = convert_sf2w($src):chop",
816 [(set (i32 IntRegs:$dst), (fp_to_sint (f32 IntRegs:$src)))]>,
819 def CONVERT_df2d : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src),
820 "$dst = convert_df2d($src):chop",
821 [(set (i64 DoubleRegs:$dst), (fp_to_sint (f64 DoubleRegs:$src)))]>,
824 def CONVERT_df2ud : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src),
825 "$dst = convert_df2ud($src):chop",
826 [(set (i64 DoubleRegs:$dst), (fp_to_uint (f64 DoubleRegs:$src)))]>,
829 def CONVERT_sf2d : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src),
830 "$dst = convert_sf2d($src):chop",
831 [(set (i64 DoubleRegs:$dst), (fp_to_sint (f32 IntRegs:$src)))]>,
834 def CONVERT_sf2ud : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src),
835 "$dst = convert_sf2ud($src):chop",
836 [(set (i64 DoubleRegs:$dst), (fp_to_uint (f32 IntRegs:$src)))]>,
839 // Convert Floating Point to Integer: non-chopped.
840 let AddedComplexity = 20 in
841 def CONVERT_df2uw_nchop : ALU64_rr<(outs IntRegs:$dst), (ins DoubleRegs:$src),
842 "$dst = convert_df2uw($src)",
843 [(set (i32 IntRegs:$dst), (fp_to_uint (f64 DoubleRegs:$src)))]>,
844 Requires<[HasV5T, IEEERndNearV5T]>;
846 let AddedComplexity = 20 in
847 def CONVERT_df2w_nchop : ALU64_rr<(outs IntRegs:$dst), (ins DoubleRegs:$src),
848 "$dst = convert_df2w($src)",
849 [(set (i32 IntRegs:$dst), (fp_to_sint (f64 DoubleRegs:$src)))]>,
850 Requires<[HasV5T, IEEERndNearV5T]>;
852 let AddedComplexity = 20 in
853 def CONVERT_sf2uw_nchop : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src),
854 "$dst = convert_sf2uw($src)",
855 [(set (i32 IntRegs:$dst), (fp_to_uint (f32 IntRegs:$src)))]>,
856 Requires<[HasV5T, IEEERndNearV5T]>;
858 let AddedComplexity = 20 in
859 def CONVERT_sf2w_nchop : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src),
860 "$dst = convert_sf2w($src)",
861 [(set (i32 IntRegs:$dst), (fp_to_sint (f32 IntRegs:$src)))]>,
862 Requires<[HasV5T, IEEERndNearV5T]>;
864 let AddedComplexity = 20 in
865 def CONVERT_df2d_nchop : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src),
866 "$dst = convert_df2d($src)",
867 [(set (i64 DoubleRegs:$dst), (fp_to_sint (f64 DoubleRegs:$src)))]>,
868 Requires<[HasV5T, IEEERndNearV5T]>;
870 let AddedComplexity = 20 in
871 def CONVERT_df2ud_nchop : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src),
872 "$dst = convert_df2ud($src)",
873 [(set (i64 DoubleRegs:$dst), (fp_to_uint (f64 DoubleRegs:$src)))]>,
874 Requires<[HasV5T, IEEERndNearV5T]>;
876 let AddedComplexity = 20 in
877 def CONVERT_sf2d_nchop : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src),
878 "$dst = convert_sf2d($src)",
879 [(set (i64 DoubleRegs:$dst), (fp_to_sint (f32 IntRegs:$src)))]>,
880 Requires<[HasV5T, IEEERndNearV5T]>;
882 let AddedComplexity = 20 in
883 def CONVERT_sf2ud_nchop : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src),
884 "$dst = convert_sf2ud($src)",
885 [(set (i64 DoubleRegs:$dst), (fp_to_uint (f32 IntRegs:$src)))]>,
886 Requires<[HasV5T, IEEERndNearV5T]>;
890 // Bitcast is different than [fp|sint|uint]_to_[sint|uint|fp].
891 def : Pat <(i32 (bitconvert (f32 IntRegs:$src))),
892 (i32 (A2_tfr IntRegs:$src))>,
895 def : Pat <(f32 (bitconvert (i32 IntRegs:$src))),
896 (f32 (A2_tfr IntRegs:$src))>,
899 def : Pat <(i64 (bitconvert (f64 DoubleRegs:$src))),
900 (i64 (A2_tfrp DoubleRegs:$src))>,
903 def : Pat <(f64 (bitconvert (i64 DoubleRegs:$src))),
904 (f64 (A2_tfrp DoubleRegs:$src))>,
907 def FMADD_sp : ALU64_acc<(outs IntRegs:$dst),
908 (ins IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
909 "$dst += sfmpy($src2, $src3)",
910 [(set (f32 IntRegs:$dst),
911 (fma IntRegs:$src2, IntRegs:$src3, IntRegs:$src1))],
916 // Floating point max/min.
918 let AddedComplexity = 100 in
919 def FMAX_sp : ALU64_rr<(outs IntRegs:$dst),
920 (ins IntRegs:$src1, IntRegs:$src2),
921 "$dst = sfmax($src1, $src2)",
922 [(set IntRegs:$dst, (f32 (select (i1 (setolt IntRegs:$src2,
928 let AddedComplexity = 100 in
929 def FMIN_sp : ALU64_rr<(outs IntRegs:$dst),
930 (ins IntRegs:$src1, IntRegs:$src2),
931 "$dst = sfmin($src1, $src2)",
932 [(set IntRegs:$dst, (f32 (select (i1 (setogt IntRegs:$src2,
938 // Pseudo instruction to encode a set of conditional transfers.
939 // This instruction is used instead of a mux and trades-off codesize
940 // for performance. We conduct this transformation optimistically in
941 // the hope that these instructions get promoted to dot-new transfers.
942 let AddedComplexity = 100, isPredicated = 1 in
943 def TFR_condset_rr_f : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1,
946 "Error; should not emit",
947 [(set IntRegs:$dst, (f32 (select PredRegs:$src1,
952 let AddedComplexity = 100, isPredicated = 1 in
953 def TFR_condset_rr64_f : ALU32_rr<(outs DoubleRegs:$dst), (ins PredRegs:$src1,
956 "Error; should not emit",
957 [(set DoubleRegs:$dst, (f64 (select PredRegs:$src1,
959 DoubleRegs:$src3)))]>,
964 let AddedComplexity = 100, isPredicated = 1 in
965 def TFR_condset_ri_f : ALU32_rr<(outs IntRegs:$dst),
966 (ins PredRegs:$src1, IntRegs:$src2, f32imm:$src3),
967 "Error; should not emit",
969 (f32 (select PredRegs:$src1, IntRegs:$src2, fpimm:$src3)))]>,
972 let AddedComplexity = 100, isPredicated = 1 in
973 def TFR_condset_ir_f : ALU32_rr<(outs IntRegs:$dst),
974 (ins PredRegs:$src1, f32imm:$src2, IntRegs:$src3),
975 "Error; should not emit",
977 (f32 (select PredRegs:$src1, fpimm:$src2, IntRegs:$src3)))]>,
980 let AddedComplexity = 100, isPredicated = 1 in
981 def TFR_condset_ii_f : ALU32_rr<(outs IntRegs:$dst),
982 (ins PredRegs:$src1, f32imm:$src2, f32imm:$src3),
983 "Error; should not emit",
984 [(set IntRegs:$dst, (f32 (select PredRegs:$src1,
990 def : Pat <(select (i1 (setult (f32 IntRegs:$src1), (f32 IntRegs:$src2))),
992 (f32 IntRegs:$src4)),
993 (TFR_condset_rr_f (FCMPUGT32_rr IntRegs:$src2, IntRegs:$src1), IntRegs:$src4,
994 IntRegs:$src3)>, Requires<[HasV5T]>;
996 def : Pat <(select (i1 (setult (f64 DoubleRegs:$src1), (f64 DoubleRegs:$src2))),
997 (f64 DoubleRegs:$src3),
998 (f64 DoubleRegs:$src4)),
999 (TFR_condset_rr64_f (FCMPUGT64_rr DoubleRegs:$src2, DoubleRegs:$src1),
1000 DoubleRegs:$src4, DoubleRegs:$src3)>, Requires<[HasV5T]>;
1002 // Map from p0 = pnot(p0); r0 = mux(p0, #i, #j) => r0 = mux(p0, #j, #i).
1003 def : Pat <(select (not PredRegs:$src1), fpimm:$src2, fpimm:$src3),
1004 (TFR_condset_ii_f PredRegs:$src1, fpimm:$src3, fpimm:$src2)>;
1006 // Map from p0 = pnot(p0); r0 = select(p0, #i, r1)
1007 // => r0 = TFR_condset_ri(p0, r1, #i)
1008 def : Pat <(select (not PredRegs:$src1), fpimm:$src2, IntRegs:$src3),
1009 (TFR_condset_ri_f PredRegs:$src1, IntRegs:$src3, fpimm:$src2)>;
1011 // Map from p0 = pnot(p0); r0 = mux(p0, r1, #i)
1012 // => r0 = TFR_condset_ir(p0, #i, r1)
1013 def : Pat <(select (not PredRegs:$src1), IntRegs:$src2, fpimm:$src3),
1014 (TFR_condset_ir_f PredRegs:$src1, fpimm:$src3, IntRegs:$src2)>;
1016 def : Pat <(i32 (fp_to_sint (f64 DoubleRegs:$src1))),
1017 (i32 (EXTRACT_SUBREG (i64 (CONVERT_df2d (f64 DoubleRegs:$src1))), subreg_loreg))>,
1020 def : Pat <(fabs (f32 IntRegs:$src1)),
1021 (S2_clrbit_i (f32 IntRegs:$src1), 31)>,
1024 def : Pat <(fneg (f32 IntRegs:$src1)),
1025 (S2_togglebit_i (f32 IntRegs:$src1), 31)>,
1029 def : Pat <(fabs (f64 DoubleRegs:$src1)),
1030 (S2_clrbit_i (f32 (EXTRACT_SUBREG DoubleRegs:$src1, subreg_hireg)), 31)>,
1033 def : Pat <(fabs (f64 DoubleRegs:$src1)),
1034 (S2_clrbit_i (f32 (EXTRACT_SUBREG DoubleRegs:$src1, subreg_hireg)), 31)>,