1 //=- HexagonInstrInfoV5.td - Target Desc. for Hexagon Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Hexagon V5 instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
18 let isCodeGenOnly = 0 in
19 def S2_asr_i_p_rnd : S_2OpInstImm<"asr", 0b110, 0b111, u6Imm,
21 (sra (i64 (add (i64 (sra I64:$src1, u6ImmPred:$src2)), 1)),
25 let Inst{13-8} = src2;
28 let isCodeGenOnly = 0 in
29 def C4_fastcorner9 : T_LOGICAL_2OP<"fastcorner9", 0b000, 0, 0>,
31 let Inst{13,7,4} = 0b111;
34 let isCodeGenOnly = 0 in
35 def C4_fastcorner9_not : T_LOGICAL_2OP<"!fastcorner9", 0b000, 0, 0>,
37 let Inst{20,13,7,4} = 0b1111;
40 def SDTHexagonFCONST32 : SDTypeProfile<1, 1, [
43 def HexagonFCONST32 : SDNode<"HexagonISD::FCONST32", SDTHexagonFCONST32>;
45 let isReMaterializable = 1, isMoveImm = 1 in
46 def FCONST32_nsdata : LDInst<(outs IntRegs:$dst), (ins globaladdress:$global),
47 "$dst = CONST32(#$global)",
48 [(set (f32 IntRegs:$dst),
49 (HexagonFCONST32 tglobaladdr:$global))]>,
52 let isReMaterializable = 1, isMoveImm = 1 in
53 def CONST64_Float_Real : LDInst<(outs DoubleRegs:$dst), (ins f64imm:$src1),
54 "$dst = CONST64(#$src1)",
55 [(set DoubleRegs:$dst, fpimm:$src1)]>,
58 let isReMaterializable = 1, isMoveImm = 1 in
59 def CONST32_Float_Real : LDInst<(outs IntRegs:$dst), (ins f32imm:$src1),
60 "$dst = CONST32(#$src1)",
61 [(set IntRegs:$dst, fpimm:$src1)]>,
64 // Transfer immediate float.
65 // Only works with single precision fp value.
66 // For double precision, use CONST64_float_real, as 64bit transfer
67 // can only hold 40-bit values - 32 from const ext + 8 bit immediate.
68 // Make sure that complexity is more than the CONST32 pattern in
69 // HexagonInstrInfo.td patterns.
70 let isExtended = 1, opExtendable = 1, isMoveImm = 1, isReMaterializable = 1,
71 isPredicable = 1, AddedComplexity = 30, validSubTargets = HasV5SubT,
73 def TFRI_f : ALU32_ri<(outs IntRegs:$dst), (ins f32Ext:$src1),
75 [(set IntRegs:$dst, fpimm:$src1)]>,
78 let isExtended = 1, opExtendable = 2, isPredicated = 1,
79 hasSideEffects = 0, validSubTargets = HasV5SubT in
80 def TFRI_cPt_f : ALU32_ri<(outs IntRegs:$dst),
81 (ins PredRegs:$src1, f32Ext:$src2),
82 "if ($src1) $dst = #$src2",
86 let isExtended = 1, opExtendable = 2, isPredicated = 1, isPredicatedFalse = 1,
87 hasSideEffects = 0, validSubTargets = HasV5SubT in
88 def TFRI_cNotPt_f : ALU32_ri<(outs IntRegs:$dst),
89 (ins PredRegs:$src1, f32Ext:$src2),
90 "if (!$src1) $dst =#$src2",
94 def SDTHexagonI32I64: SDTypeProfile<1, 1, [SDTCisVT<0, i32>,
97 def HexagonPOPCOUNT: SDNode<"HexagonISD::POPCOUNT", SDTHexagonI32I64>;
99 let hasNewValue = 1, validSubTargets = HasV5SubT, isCodeGenOnly = 0 in
100 def S5_popcountp : ALU64_rr<(outs IntRegs:$Rd), (ins DoubleRegs:$Rss),
101 "$Rd = popcount($Rss)",
102 [(set I32:$Rd, (HexagonPOPCOUNT I64:$Rss))], "", S_2op_tc_2_SLOT23>,
109 let Inst{27-21} = 0b1000011;
110 let Inst{7-5} = 0b011;
112 let Inst{20-16} = Rss;
115 defm: Loadx_pat<load, f32, s11_2ExtPred, L2_loadri_io>;
116 defm: Loadx_pat<load, f64, s11_3ExtPred, L2_loadrd_io>;
118 defm: Storex_pat<store, F32, s11_2ExtPred, S2_storeri_io>;
119 defm: Storex_pat<store, F64, s11_3ExtPred, S2_storerd_io>;
121 let isFP = 1, hasNewValue = 1, opNewValue = 0 in
122 class T_MInstFloat <string mnemonic, bits<3> MajOp, bits<3> MinOp>
123 : MInst<(outs IntRegs:$Rd),
124 (ins IntRegs:$Rs, IntRegs:$Rt),
125 "$Rd = "#mnemonic#"($Rs, $Rt)", [],
126 "" , M_tc_3or4x_SLOT23 > ,
134 let Inst{27-24} = 0b1011;
135 let Inst{23-21} = MajOp;
136 let Inst{20-16} = Rs;
139 let Inst{7-5} = MinOp;
143 let isCommutable = 1, isCodeGenOnly = 0 in {
144 def F2_sfadd : T_MInstFloat < "sfadd", 0b000, 0b000>;
145 def F2_sfmpy : T_MInstFloat < "sfmpy", 0b010, 0b000>;
148 let isCodeGenOnly = 0 in
149 def F2_sfsub : T_MInstFloat < "sfsub", 0b000, 0b001>;
151 let Itinerary = M_tc_3x_SLOT23, isCodeGenOnly = 0 in {
152 def F2_sfmax : T_MInstFloat < "sfmax", 0b100, 0b000>;
153 def F2_sfmin : T_MInstFloat < "sfmin", 0b100, 0b001>;
156 let isCodeGenOnly = 0 in {
157 def F2_sffixupn : T_MInstFloat < "sffixupn", 0b110, 0b000>;
158 def F2_sffixupd : T_MInstFloat < "sffixupd", 0b110, 0b001>;
161 // F2_sfrecipa: Reciprocal approximation for division.
162 let isPredicateLate = 1, isFP = 1,
163 hasSideEffects = 0, hasNewValue = 1, isCodeGenOnly = 0 in
164 def F2_sfrecipa: MInst <
165 (outs IntRegs:$Rd, PredRegs:$Pe),
166 (ins IntRegs:$Rs, IntRegs:$Rt),
167 "$Rd, $Pe = sfrecipa($Rs, $Rt)">,
175 let Inst{27-21} = 0b1011111;
176 let Inst{20-16} = Rs;
184 // F2_dfcmpeq: Floating point compare for equal.
185 let isCompare = 1, isFP = 1 in
186 class T_fcmp <string mnemonic, RegisterClass RC, bits<3> MinOp,
187 list<dag> pattern = [] >
188 : ALU64Inst <(outs PredRegs:$dst), (ins RC:$src1, RC:$src2),
189 "$dst = "#mnemonic#"($src1, $src2)", pattern,
190 "" , ALU64_tc_2early_SLOT23 > ,
198 let Inst{27-21} = 0b0010111;
199 let Inst{20-16} = src1;
200 let Inst{12-8} = src2;
201 let Inst{7-5} = MinOp;
205 class T_fcmp64 <string mnemonic, PatFrag OpNode, bits<3> MinOp>
206 : T_fcmp <mnemonic, DoubleRegs, MinOp,
207 [(set I1:$dst, (OpNode F64:$src1, F64:$src2))]> {
209 let Inst{27-21} = 0b0010111;
212 class T_fcmp32 <string mnemonic, PatFrag OpNode, bits<3> MinOp>
213 : T_fcmp <mnemonic, IntRegs, MinOp,
214 [(set I1:$dst, (OpNode F32:$src1, F32:$src2))]> {
216 let Inst{27-21} = 0b0111111;
219 let isCodeGenOnly = 0 in {
220 def F2_dfcmpeq : T_fcmp64<"dfcmp.eq", setoeq, 0b000>;
221 def F2_dfcmpgt : T_fcmp64<"dfcmp.gt", setogt, 0b001>;
222 def F2_dfcmpge : T_fcmp64<"dfcmp.ge", setoge, 0b010>;
223 def F2_dfcmpuo : T_fcmp64<"dfcmp.uo", setuo, 0b011>;
225 def F2_sfcmpge : T_fcmp32<"sfcmp.ge", setoge, 0b000>;
226 def F2_sfcmpuo : T_fcmp32<"sfcmp.uo", setuo, 0b001>;
227 def F2_sfcmpeq : T_fcmp32<"sfcmp.eq", setoeq, 0b011>;
228 def F2_sfcmpgt : T_fcmp32<"sfcmp.gt", setogt, 0b100>;
231 // F2 convert template classes:
233 class F2_RDD_RSS_CONVERT<string mnemonic, bits<3> MinOp,
234 SDNode Op, PatLeaf RCOut, PatLeaf RCIn,
236 : SInst <(outs DoubleRegs:$Rdd), (ins DoubleRegs:$Rss),
237 "$Rdd = "#mnemonic#"($Rss)"#chop,
238 [(set RCOut:$Rdd, (Op RCIn:$Rss))], "",
239 S_2op_tc_3or4x_SLOT23> {
245 let Inst{27-21} = 0b0000111;
246 let Inst{20-16} = Rss;
247 let Inst{7-5} = MinOp;
252 class F2_RDD_RS_CONVERT<string mnemonic, bits<3> MinOp,
253 SDNode Op, PatLeaf RCOut, PatLeaf RCIn,
255 : SInst <(outs DoubleRegs:$Rdd), (ins IntRegs:$Rs),
256 "$Rdd = "#mnemonic#"($Rs)"#chop,
257 [(set RCOut:$Rdd, (Op RCIn:$Rs))], "",
258 S_2op_tc_3or4x_SLOT23> {
264 let Inst{27-21} = 0b0100100;
265 let Inst{20-16} = Rs;
266 let Inst{7-5} = MinOp;
270 let isFP = 1, hasNewValue = 1 in
271 class F2_RD_RSS_CONVERT<string mnemonic, bits<3> MinOp,
272 SDNode Op, PatLeaf RCOut, PatLeaf RCIn,
274 : SInst <(outs IntRegs:$Rd), (ins DoubleRegs:$Rss),
275 "$Rd = "#mnemonic#"($Rss)"#chop,
276 [(set RCOut:$Rd, (Op RCIn:$Rss))], "",
277 S_2op_tc_3or4x_SLOT23> {
283 let Inst{27-24} = 0b1000;
284 let Inst{23-21} = MinOp;
285 let Inst{20-16} = Rss;
286 let Inst{7-5} = 0b001;
290 let isFP = 1, hasNewValue = 1 in
291 class F2_RD_RS_CONVERT<string mnemonic, bits<3> MajOp, bits<3> MinOp,
292 SDNode Op, PatLeaf RCOut, PatLeaf RCIn,
294 : SInst <(outs IntRegs:$Rd), (ins IntRegs:$Rs),
295 "$Rd = "#mnemonic#"($Rs)"#chop,
296 [(set RCOut:$Rd, (Op RCIn:$Rs))], "",
297 S_2op_tc_3or4x_SLOT23> {
303 let Inst{27-24} = 0b1011;
304 let Inst{23-21} = MajOp;
305 let Inst{20-16} = Rs;
306 let Inst{7-5} = MinOp;
310 // Convert single precision to double precision and vice-versa.
311 let isCodeGenOnly = 0 in {
312 def F2_conv_sf2df : F2_RDD_RS_CONVERT <"convert_sf2df", 0b000,
315 def F2_conv_df2sf : F2_RD_RSS_CONVERT <"convert_df2sf", 0b000,
318 // Convert Integer to Floating Point.
319 def F2_conv_d2sf : F2_RD_RSS_CONVERT <"convert_d2sf", 0b010,
320 sint_to_fp, F32, I64>;
321 def F2_conv_ud2sf : F2_RD_RSS_CONVERT <"convert_ud2sf", 0b001,
322 uint_to_fp, F32, I64>;
323 def F2_conv_uw2sf : F2_RD_RS_CONVERT <"convert_uw2sf", 0b001, 0b000,
324 uint_to_fp, F32, I32>;
325 def F2_conv_w2sf : F2_RD_RS_CONVERT <"convert_w2sf", 0b010, 0b000,
326 sint_to_fp, F32, I32>;
327 def F2_conv_d2df : F2_RDD_RSS_CONVERT <"convert_d2df", 0b011,
328 sint_to_fp, F64, I64>;
329 def F2_conv_ud2df : F2_RDD_RSS_CONVERT <"convert_ud2df", 0b010,
330 uint_to_fp, F64, I64>;
331 def F2_conv_uw2df : F2_RDD_RS_CONVERT <"convert_uw2df", 0b001,
332 uint_to_fp, F64, I32>;
333 def F2_conv_w2df : F2_RDD_RS_CONVERT <"convert_w2df", 0b010,
334 sint_to_fp, F64, I32>;
336 // Convert Floating Point to Integer - default.
337 def F2_conv_df2uw_chop : F2_RD_RSS_CONVERT <"convert_df2uw", 0b101,
338 fp_to_uint, I32, F64, ":chop">;
339 def F2_conv_df2w_chop : F2_RD_RSS_CONVERT <"convert_df2w", 0b111,
340 fp_to_sint, I32, F64, ":chop">;
341 def F2_conv_sf2uw_chop : F2_RD_RS_CONVERT <"convert_sf2uw", 0b011, 0b001,
342 fp_to_uint, I32, F32, ":chop">;
343 def F2_conv_sf2w_chop : F2_RD_RS_CONVERT <"convert_sf2w", 0b100, 0b001,
344 fp_to_sint, I32, F32, ":chop">;
345 def F2_conv_df2d_chop : F2_RDD_RSS_CONVERT <"convert_df2d", 0b110,
346 fp_to_sint, I64, F64, ":chop">;
347 def F2_conv_df2ud_chop : F2_RDD_RSS_CONVERT <"convert_df2ud", 0b111,
348 fp_to_uint, I64, F64, ":chop">;
349 def F2_conv_sf2d_chop : F2_RDD_RS_CONVERT <"convert_sf2d", 0b110,
350 fp_to_sint, I64, F32, ":chop">;
351 def F2_conv_sf2ud_chop : F2_RDD_RS_CONVERT <"convert_sf2ud", 0b101,
352 fp_to_uint, I64, F32, ":chop">;
354 // Convert Floating Point to Integer: non-chopped.
355 let AddedComplexity = 20, Predicates = [HasV5T, IEEERndNearV5T] in {
356 def F2_conv_df2d : F2_RDD_RSS_CONVERT <"convert_df2d", 0b000,
357 fp_to_sint, I64, F64>;
358 def F2_conv_df2ud : F2_RDD_RSS_CONVERT <"convert_df2ud", 0b001,
359 fp_to_uint, I64, F64>;
360 def F2_conv_sf2ud : F2_RDD_RS_CONVERT <"convert_sf2ud", 0b011,
361 fp_to_uint, I64, F32>;
362 def F2_conv_sf2d : F2_RDD_RS_CONVERT <"convert_sf2d", 0b100,
363 fp_to_sint, I64, F32>;
364 def F2_conv_df2uw : F2_RD_RSS_CONVERT <"convert_df2uw", 0b011,
365 fp_to_uint, I32, F64>;
366 def F2_conv_df2w : F2_RD_RSS_CONVERT <"convert_df2w", 0b100,
367 fp_to_sint, I32, F64>;
368 def F2_conv_sf2uw : F2_RD_RS_CONVERT <"convert_sf2uw", 0b011, 0b000,
369 fp_to_uint, I32, F32>;
370 def F2_conv_sf2w : F2_RD_RS_CONVERT <"convert_sf2w", 0b100, 0b000,
371 fp_to_sint, I32, F32>;
376 let isFP = 1, hasNewValue = 1, isCodeGenOnly = 0 in
377 def F2_sffixupr: SInst<(outs IntRegs:$Rd), (ins IntRegs:$Rs),
378 "$Rd = sffixupr($Rs)",
379 [], "" , S_2op_tc_3or4x_SLOT23>, Requires<[HasV5T]> {
385 let Inst{27-21} = 0b1011101;
386 let Inst{20-16} = Rs;
387 let Inst{7-5} = 0b000;
391 // F2_sffma: Floating-point fused multiply add.
392 let isFP = 1, hasNewValue = 1 in
393 class T_sfmpy_acc <bit isSub, bit isLib>
394 : MInst<(outs IntRegs:$Rx),
395 (ins IntRegs:$dst2, IntRegs:$Rs, IntRegs:$Rt),
396 "$Rx "#!if(isSub, "-=","+=")#" sfmpy($Rs, $Rt)"#!if(isLib, ":lib",""),
397 [], "$dst2 = $Rx" , M_tc_3_SLOT23 > ,
405 let Inst{27-21} = 0b1111000;
406 let Inst{20-16} = Rs;
415 let isCodeGenOnly = 0 in {
416 def F2_sffma: T_sfmpy_acc <0, 0>;
417 def F2_sffms: T_sfmpy_acc <1, 0>;
418 def F2_sffma_lib: T_sfmpy_acc <0, 1>;
419 def F2_sffms_lib: T_sfmpy_acc <1, 1>;
422 // Floating-point fused multiply add w/ additional scaling (2**pu).
423 let isFP = 1, hasNewValue = 1, isCodeGenOnly = 0 in
424 def F2_sffma_sc: MInst <
426 (ins IntRegs:$dst2, IntRegs:$Rs, IntRegs:$Rt, PredRegs:$Pu),
427 "$Rx += sfmpy($Rs, $Rt, $Pu):scale" ,
428 [], "$dst2 = $Rx" , M_tc_3_SLOT23 > ,
437 let Inst{27-21} = 0b1111011;
438 let Inst{20-16} = Rs;
446 // Classify floating-point value
447 let isFP = 1, isCodeGenOnly = 0 in
448 def F2_sfclass : T_TEST_BIT_IMM<"sfclass", 0b111>;
450 let isFP = 1, isCodeGenOnly = 0 in
451 def F2_dfclass: ALU64Inst<(outs PredRegs:$Pd), (ins DoubleRegs:$Rss, u5Imm:$u5),
452 "$Pd = dfclass($Rss, #$u5)",
453 [], "" , ALU64_tc_2early_SLOT23 > , Requires<[HasV5T]> {
459 let Inst{27-21} = 0b1100100;
460 let Inst{20-16} = Rss;
461 let Inst{12-10} = 0b000;
463 let Inst{4-3} = 0b10;
467 // Instructions to create floating point constant
468 let hasNewValue = 1, opNewValue = 0 in
469 class T_fimm <string mnemonic, RegisterClass RC, bits<4> RegType, bit isNeg>
470 : ALU64Inst<(outs RC:$dst), (ins u10Imm:$src),
471 "$dst = "#mnemonic#"(#$src)"#!if(isNeg, ":neg", ":pos"),
472 [], "", ALU64_tc_3x_SLOT23>, Requires<[HasV5T]> {
477 let Inst{27-24} = RegType;
479 let Inst{22} = isNeg;
480 let Inst{21} = src{9};
481 let Inst{13-5} = src{8-0};
485 let isCodeGenOnly = 0 in {
486 def F2_sfimm_p : T_fimm <"sfmake", IntRegs, 0b0110, 0>;
487 def F2_sfimm_n : T_fimm <"sfmake", IntRegs, 0b0110, 1>;
488 def F2_dfimm_p : T_fimm <"dfmake", DoubleRegs, 0b1001, 0>;
489 def F2_dfimm_n : T_fimm <"dfmake", DoubleRegs, 0b1001, 1>;
493 let isCommutable = 1 in
494 def fADD_rr : ALU64_rr<(outs IntRegs:$dst),
495 (ins IntRegs:$src1, IntRegs:$src2),
496 "$dst = sfadd($src1, $src2)",
497 [(set IntRegs:$dst, (fadd IntRegs:$src1, IntRegs:$src2))]>,
500 let isCommutable = 1 in
501 def fADD64_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
503 "$dst = dfadd($src1, $src2)",
504 [(set DoubleRegs:$dst, (fadd DoubleRegs:$src1,
505 DoubleRegs:$src2))]>,
508 def fSUB_rr : ALU64_rr<(outs IntRegs:$dst),
509 (ins IntRegs:$src1, IntRegs:$src2),
510 "$dst = sfsub($src1, $src2)",
511 [(set IntRegs:$dst, (fsub IntRegs:$src1, IntRegs:$src2))]>,
514 def fSUB64_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
516 "$dst = dfsub($src1, $src2)",
517 [(set DoubleRegs:$dst, (fsub DoubleRegs:$src1,
518 DoubleRegs:$src2))]>,
521 let isCommutable = 1 in
522 def fMUL_rr : ALU64_rr<(outs IntRegs:$dst),
523 (ins IntRegs:$src1, IntRegs:$src2),
524 "$dst = sfmpy($src1, $src2)",
525 [(set IntRegs:$dst, (fmul IntRegs:$src1, IntRegs:$src2))]>,
528 let isCommutable = 1 in
529 def fMUL64_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
531 "$dst = dfmpy($src1, $src2)",
532 [(set DoubleRegs:$dst, (fmul DoubleRegs:$src1,
533 DoubleRegs:$src2))]>,
537 let isCompare = 1 in {
538 multiclass FCMP64_rr<string OpcStr, PatFrag OpNode> {
539 def _rr : ALU64_rr<(outs PredRegs:$dst), (ins DoubleRegs:$b, DoubleRegs:$c),
540 !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
542 (OpNode (f64 DoubleRegs:$b), (f64 DoubleRegs:$c)))]>,
546 multiclass FCMP32_rr<string OpcStr, PatFrag OpNode> {
547 def _rr : ALU64_rr<(outs PredRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
548 !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
550 (OpNode (f32 IntRegs:$b), (f32 IntRegs:$c)))]>,
555 defm FCMPOEQ64 : FCMP64_rr<"dfcmp.eq", setoeq>;
556 defm FCMPUEQ64 : FCMP64_rr<"dfcmp.eq", setueq>;
557 defm FCMPOGT64 : FCMP64_rr<"dfcmp.gt", setogt>;
558 defm FCMPUGT64 : FCMP64_rr<"dfcmp.gt", setugt>;
559 defm FCMPOGE64 : FCMP64_rr<"dfcmp.ge", setoge>;
560 defm FCMPUGE64 : FCMP64_rr<"dfcmp.ge", setuge>;
562 defm FCMPOEQ32 : FCMP32_rr<"sfcmp.eq", setoeq>;
563 defm FCMPUEQ32 : FCMP32_rr<"sfcmp.eq", setueq>;
564 defm FCMPOGT32 : FCMP32_rr<"sfcmp.gt", setogt>;
565 defm FCMPUGT32 : FCMP32_rr<"sfcmp.gt", setugt>;
566 defm FCMPOGE32 : FCMP32_rr<"sfcmp.ge", setoge>;
567 defm FCMPUGE32 : FCMP32_rr<"sfcmp.ge", setuge>;
570 def : Pat <(i1 (setolt (f32 IntRegs:$src1), (f32 IntRegs:$src2))),
571 (i1 (FCMPOGT32_rr IntRegs:$src2, IntRegs:$src1))>,
574 def : Pat <(i1 (setolt (f32 IntRegs:$src1), (fpimm:$src2))),
575 (i1 (FCMPOGT32_rr (f32 (TFRI_f fpimm:$src2)), (f32 IntRegs:$src1)))>,
578 def : Pat <(i1 (setolt (f64 DoubleRegs:$src1), (f64 DoubleRegs:$src2))),
579 (i1 (FCMPOGT64_rr DoubleRegs:$src2, DoubleRegs:$src1))>,
582 def : Pat <(i1 (setolt (f64 DoubleRegs:$src1), (fpimm:$src2))),
583 (i1 (FCMPOGT64_rr (f64 (CONST64_Float_Real fpimm:$src2)),
584 (f64 DoubleRegs:$src1)))>,
588 def : Pat <(i1 (setugt (f64 DoubleRegs:$src1), (fpimm:$src2))),
589 (i1 (FCMPUGT64_rr (f64 DoubleRegs:$src1),
590 (f64 (CONST64_Float_Real fpimm:$src2))))>,
593 def : Pat <(i1 (setugt (f32 IntRegs:$src1), (fpimm:$src2))),
594 (i1 (FCMPUGT32_rr (f32 IntRegs:$src1), (f32 (TFRI_f fpimm:$src2))))>,
598 def : Pat <(i1 (setult (f32 IntRegs:$src1), (f32 IntRegs:$src2))),
599 (i1 (FCMPUGT32_rr IntRegs:$src2, IntRegs:$src1))>,
602 def : Pat <(i1 (setult (f32 IntRegs:$src1), (fpimm:$src2))),
603 (i1 (FCMPUGT32_rr (f32 (TFRI_f fpimm:$src2)), (f32 IntRegs:$src1)))>,
606 def : Pat <(i1 (setult (f64 DoubleRegs:$src1), (f64 DoubleRegs:$src2))),
607 (i1 (FCMPUGT64_rr DoubleRegs:$src2, DoubleRegs:$src1))>,
610 def : Pat <(i1 (setult (f64 DoubleRegs:$src1), (fpimm:$src2))),
611 (i1 (FCMPUGT64_rr (f64 (CONST64_Float_Real fpimm:$src2)),
612 (f64 DoubleRegs:$src1)))>,
616 // rs <= rt -> rt >= rs.
617 def : Pat<(i1 (setole (f32 IntRegs:$src1), (f32 IntRegs:$src2))),
618 (i1 (FCMPOGE32_rr IntRegs:$src2, IntRegs:$src1))>,
621 def : Pat<(i1 (setole (f32 IntRegs:$src1), (fpimm:$src2))),
622 (i1 (FCMPOGE32_rr (f32 (TFRI_f fpimm:$src2)), IntRegs:$src1))>,
626 // Rss <= Rtt -> Rtt >= Rss.
627 def : Pat<(i1 (setole (f64 DoubleRegs:$src1), (f64 DoubleRegs:$src2))),
628 (i1 (FCMPOGE64_rr DoubleRegs:$src2, DoubleRegs:$src1))>,
631 def : Pat<(i1 (setole (f64 DoubleRegs:$src1), (fpimm:$src2))),
632 (i1 (FCMPOGE64_rr (f64 (CONST64_Float_Real fpimm:$src2)),
636 // rs <= rt -> rt >= rs.
637 def : Pat<(i1 (setule (f32 IntRegs:$src1), (f32 IntRegs:$src2))),
638 (i1 (FCMPUGE32_rr IntRegs:$src2, IntRegs:$src1))>,
641 def : Pat<(i1 (setule (f32 IntRegs:$src1), (fpimm:$src2))),
642 (i1 (FCMPUGE32_rr (f32 (TFRI_f fpimm:$src2)), IntRegs:$src1))>,
645 // Rss <= Rtt -> Rtt >= Rss.
646 def : Pat<(i1 (setule (f64 DoubleRegs:$src1), (f64 DoubleRegs:$src2))),
647 (i1 (FCMPUGE64_rr DoubleRegs:$src2, DoubleRegs:$src1))>,
650 def : Pat<(i1 (setule (f64 DoubleRegs:$src1), (fpimm:$src2))),
651 (i1 (FCMPUGE64_rr (f64 (CONST64_Float_Real fpimm:$src2)),
656 def : Pat<(i1 (setone (f32 IntRegs:$src1), (f32 IntRegs:$src2))),
657 (i1 (C2_not (FCMPOEQ32_rr IntRegs:$src1, IntRegs:$src2)))>,
660 def : Pat<(i1 (setone (f64 DoubleRegs:$src1), (f64 DoubleRegs:$src2))),
661 (i1 (C2_not (FCMPOEQ64_rr DoubleRegs:$src1, DoubleRegs:$src2)))>,
664 def : Pat<(i1 (setune (f32 IntRegs:$src1), (f32 IntRegs:$src2))),
665 (i1 (C2_not (FCMPUEQ32_rr IntRegs:$src1, IntRegs:$src2)))>,
668 def : Pat<(i1 (setune (f64 DoubleRegs:$src1), (f64 DoubleRegs:$src2))),
669 (i1 (C2_not (FCMPUEQ64_rr DoubleRegs:$src1, DoubleRegs:$src2)))>,
672 def : Pat<(i1 (setone (f32 IntRegs:$src1), (fpimm:$src2))),
673 (i1 (C2_not (FCMPOEQ32_rr IntRegs:$src1, (f32 (TFRI_f fpimm:$src2)))))>,
676 def : Pat<(i1 (setone (f64 DoubleRegs:$src1), (fpimm:$src2))),
677 (i1 (C2_not (FCMPOEQ64_rr DoubleRegs:$src1,
678 (f64 (CONST64_Float_Real fpimm:$src2)))))>,
681 def : Pat<(i1 (setune (f32 IntRegs:$src1), (fpimm:$src2))),
682 (i1 (C2_not (FCMPUEQ32_rr IntRegs:$src1, (f32 (TFRI_f fpimm:$src2)))))>,
685 def : Pat<(i1 (setune (f64 DoubleRegs:$src1), (fpimm:$src2))),
686 (i1 (C2_not (FCMPUEQ64_rr DoubleRegs:$src1,
687 (f64 (CONST64_Float_Real fpimm:$src2)))))>,
690 // Convert Integer to Floating Point.
691 def CONVERT_d2sf : ALU64_rr<(outs IntRegs:$dst), (ins DoubleRegs:$src),
692 "$dst = convert_d2sf($src)",
693 [(set (f32 IntRegs:$dst), (sint_to_fp (i64 DoubleRegs:$src)))]>,
696 def CONVERT_ud2sf : ALU64_rr<(outs IntRegs:$dst), (ins DoubleRegs:$src),
697 "$dst = convert_ud2sf($src)",
698 [(set (f32 IntRegs:$dst), (uint_to_fp (i64 DoubleRegs:$src)))]>,
701 def CONVERT_uw2sf : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src),
702 "$dst = convert_uw2sf($src)",
703 [(set (f32 IntRegs:$dst), (uint_to_fp (i32 IntRegs:$src)))]>,
706 def CONVERT_w2sf : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src),
707 "$dst = convert_w2sf($src)",
708 [(set (f32 IntRegs:$dst), (sint_to_fp (i32 IntRegs:$src)))]>,
711 def CONVERT_d2df : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src),
712 "$dst = convert_d2df($src)",
713 [(set (f64 DoubleRegs:$dst), (sint_to_fp (i64 DoubleRegs:$src)))]>,
716 def CONVERT_ud2df : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src),
717 "$dst = convert_ud2df($src)",
718 [(set (f64 DoubleRegs:$dst), (uint_to_fp (i64 DoubleRegs:$src)))]>,
721 def CONVERT_uw2df : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src),
722 "$dst = convert_uw2df($src)",
723 [(set (f64 DoubleRegs:$dst), (uint_to_fp (i32 IntRegs:$src)))]>,
726 def CONVERT_w2df : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src),
727 "$dst = convert_w2df($src)",
728 [(set (f64 DoubleRegs:$dst), (sint_to_fp (i32 IntRegs:$src)))]>,
731 // Convert Floating Point to Integer - default.
732 def CONVERT_df2uw : ALU64_rr<(outs IntRegs:$dst), (ins DoubleRegs:$src),
733 "$dst = convert_df2uw($src):chop",
734 [(set (i32 IntRegs:$dst), (fp_to_uint (f64 DoubleRegs:$src)))]>,
737 def CONVERT_df2w : ALU64_rr<(outs IntRegs:$dst), (ins DoubleRegs:$src),
738 "$dst = convert_df2w($src):chop",
739 [(set (i32 IntRegs:$dst), (fp_to_sint (f64 DoubleRegs:$src)))]>,
742 def CONVERT_sf2uw : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src),
743 "$dst = convert_sf2uw($src):chop",
744 [(set (i32 IntRegs:$dst), (fp_to_uint (f32 IntRegs:$src)))]>,
747 def CONVERT_sf2w : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src),
748 "$dst = convert_sf2w($src):chop",
749 [(set (i32 IntRegs:$dst), (fp_to_sint (f32 IntRegs:$src)))]>,
752 def CONVERT_df2d : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src),
753 "$dst = convert_df2d($src):chop",
754 [(set (i64 DoubleRegs:$dst), (fp_to_sint (f64 DoubleRegs:$src)))]>,
757 def CONVERT_df2ud : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src),
758 "$dst = convert_df2ud($src):chop",
759 [(set (i64 DoubleRegs:$dst), (fp_to_uint (f64 DoubleRegs:$src)))]>,
762 def CONVERT_sf2d : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src),
763 "$dst = convert_sf2d($src):chop",
764 [(set (i64 DoubleRegs:$dst), (fp_to_sint (f32 IntRegs:$src)))]>,
767 def CONVERT_sf2ud : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src),
768 "$dst = convert_sf2ud($src):chop",
769 [(set (i64 DoubleRegs:$dst), (fp_to_uint (f32 IntRegs:$src)))]>,
772 // Convert Floating Point to Integer: non-chopped.
773 let AddedComplexity = 20 in
774 def CONVERT_df2uw_nchop : ALU64_rr<(outs IntRegs:$dst), (ins DoubleRegs:$src),
775 "$dst = convert_df2uw($src)",
776 [(set (i32 IntRegs:$dst), (fp_to_uint (f64 DoubleRegs:$src)))]>,
777 Requires<[HasV5T, IEEERndNearV5T]>;
779 let AddedComplexity = 20 in
780 def CONVERT_df2w_nchop : ALU64_rr<(outs IntRegs:$dst), (ins DoubleRegs:$src),
781 "$dst = convert_df2w($src)",
782 [(set (i32 IntRegs:$dst), (fp_to_sint (f64 DoubleRegs:$src)))]>,
783 Requires<[HasV5T, IEEERndNearV5T]>;
785 let AddedComplexity = 20 in
786 def CONVERT_sf2uw_nchop : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src),
787 "$dst = convert_sf2uw($src)",
788 [(set (i32 IntRegs:$dst), (fp_to_uint (f32 IntRegs:$src)))]>,
789 Requires<[HasV5T, IEEERndNearV5T]>;
791 let AddedComplexity = 20 in
792 def CONVERT_sf2w_nchop : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src),
793 "$dst = convert_sf2w($src)",
794 [(set (i32 IntRegs:$dst), (fp_to_sint (f32 IntRegs:$src)))]>,
795 Requires<[HasV5T, IEEERndNearV5T]>;
797 let AddedComplexity = 20 in
798 def CONVERT_df2d_nchop : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src),
799 "$dst = convert_df2d($src)",
800 [(set (i64 DoubleRegs:$dst), (fp_to_sint (f64 DoubleRegs:$src)))]>,
801 Requires<[HasV5T, IEEERndNearV5T]>;
803 let AddedComplexity = 20 in
804 def CONVERT_df2ud_nchop : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src),
805 "$dst = convert_df2ud($src)",
806 [(set (i64 DoubleRegs:$dst), (fp_to_uint (f64 DoubleRegs:$src)))]>,
807 Requires<[HasV5T, IEEERndNearV5T]>;
809 let AddedComplexity = 20 in
810 def CONVERT_sf2d_nchop : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src),
811 "$dst = convert_sf2d($src)",
812 [(set (i64 DoubleRegs:$dst), (fp_to_sint (f32 IntRegs:$src)))]>,
813 Requires<[HasV5T, IEEERndNearV5T]>;
815 let AddedComplexity = 20 in
816 def CONVERT_sf2ud_nchop : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src),
817 "$dst = convert_sf2ud($src)",
818 [(set (i64 DoubleRegs:$dst), (fp_to_uint (f32 IntRegs:$src)))]>,
819 Requires<[HasV5T, IEEERndNearV5T]>;
823 // Bitcast is different than [fp|sint|uint]_to_[sint|uint|fp].
824 def : Pat <(i32 (bitconvert (f32 IntRegs:$src))),
825 (i32 (A2_tfr IntRegs:$src))>,
828 def : Pat <(f32 (bitconvert (i32 IntRegs:$src))),
829 (f32 (A2_tfr IntRegs:$src))>,
832 def : Pat <(i64 (bitconvert (f64 DoubleRegs:$src))),
833 (i64 (A2_tfrp DoubleRegs:$src))>,
836 def : Pat <(f64 (bitconvert (i64 DoubleRegs:$src))),
837 (f64 (A2_tfrp DoubleRegs:$src))>,
840 def FMADD_sp : ALU64_acc<(outs IntRegs:$dst),
841 (ins IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
842 "$dst += sfmpy($src2, $src3)",
843 [(set (f32 IntRegs:$dst),
844 (fma IntRegs:$src2, IntRegs:$src3, IntRegs:$src1))],
849 // Floating point max/min.
851 let AddedComplexity = 100 in
852 def FMAX_sp : ALU64_rr<(outs IntRegs:$dst),
853 (ins IntRegs:$src1, IntRegs:$src2),
854 "$dst = sfmax($src1, $src2)",
855 [(set IntRegs:$dst, (f32 (select (i1 (setolt IntRegs:$src2,
861 let AddedComplexity = 100 in
862 def FMIN_sp : ALU64_rr<(outs IntRegs:$dst),
863 (ins IntRegs:$src1, IntRegs:$src2),
864 "$dst = sfmin($src1, $src2)",
865 [(set IntRegs:$dst, (f32 (select (i1 (setogt IntRegs:$src2,
871 // Pseudo instruction to encode a set of conditional transfers.
872 // This instruction is used instead of a mux and trades-off codesize
873 // for performance. We conduct this transformation optimistically in
874 // the hope that these instructions get promoted to dot-new transfers.
875 let AddedComplexity = 100, isPredicated = 1 in
876 def TFR_condset_rr_f : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1,
879 "Error; should not emit",
880 [(set IntRegs:$dst, (f32 (select PredRegs:$src1,
885 let AddedComplexity = 100, isPredicated = 1 in
886 def TFR_condset_rr64_f : ALU32_rr<(outs DoubleRegs:$dst), (ins PredRegs:$src1,
889 "Error; should not emit",
890 [(set DoubleRegs:$dst, (f64 (select PredRegs:$src1,
892 DoubleRegs:$src3)))]>,
897 let AddedComplexity = 100, isPredicated = 1 in
898 def TFR_condset_ri_f : ALU32_rr<(outs IntRegs:$dst),
899 (ins PredRegs:$src1, IntRegs:$src2, f32imm:$src3),
900 "Error; should not emit",
902 (f32 (select PredRegs:$src1, IntRegs:$src2, fpimm:$src3)))]>,
905 let AddedComplexity = 100, isPredicated = 1 in
906 def TFR_condset_ir_f : ALU32_rr<(outs IntRegs:$dst),
907 (ins PredRegs:$src1, f32imm:$src2, IntRegs:$src3),
908 "Error; should not emit",
910 (f32 (select PredRegs:$src1, fpimm:$src2, IntRegs:$src3)))]>,
913 let AddedComplexity = 100, isPredicated = 1 in
914 def TFR_condset_ii_f : ALU32_rr<(outs IntRegs:$dst),
915 (ins PredRegs:$src1, f32imm:$src2, f32imm:$src3),
916 "Error; should not emit",
917 [(set IntRegs:$dst, (f32 (select PredRegs:$src1,
923 def : Pat <(select (i1 (setult (f32 IntRegs:$src1), (f32 IntRegs:$src2))),
925 (f32 IntRegs:$src4)),
926 (TFR_condset_rr_f (FCMPUGT32_rr IntRegs:$src2, IntRegs:$src1), IntRegs:$src4,
927 IntRegs:$src3)>, Requires<[HasV5T]>;
929 def : Pat <(select (i1 (setult (f64 DoubleRegs:$src1), (f64 DoubleRegs:$src2))),
930 (f64 DoubleRegs:$src3),
931 (f64 DoubleRegs:$src4)),
932 (TFR_condset_rr64_f (FCMPUGT64_rr DoubleRegs:$src2, DoubleRegs:$src1),
933 DoubleRegs:$src4, DoubleRegs:$src3)>, Requires<[HasV5T]>;
935 // Map from p0 = pnot(p0); r0 = mux(p0, #i, #j) => r0 = mux(p0, #j, #i).
936 def : Pat <(select (not PredRegs:$src1), fpimm:$src2, fpimm:$src3),
937 (TFR_condset_ii_f PredRegs:$src1, fpimm:$src3, fpimm:$src2)>;
939 // Map from p0 = pnot(p0); r0 = select(p0, #i, r1)
940 // => r0 = TFR_condset_ri(p0, r1, #i)
941 def : Pat <(select (not PredRegs:$src1), fpimm:$src2, IntRegs:$src3),
942 (TFR_condset_ri_f PredRegs:$src1, IntRegs:$src3, fpimm:$src2)>;
944 // Map from p0 = pnot(p0); r0 = mux(p0, r1, #i)
945 // => r0 = TFR_condset_ir(p0, #i, r1)
946 def : Pat <(select (not PredRegs:$src1), IntRegs:$src2, fpimm:$src3),
947 (TFR_condset_ir_f PredRegs:$src1, fpimm:$src3, IntRegs:$src2)>;
949 def : Pat <(i32 (fp_to_sint (f64 DoubleRegs:$src1))),
950 (i32 (EXTRACT_SUBREG (i64 (CONVERT_df2d (f64 DoubleRegs:$src1))), subreg_loreg))>,
953 def : Pat <(fabs (f32 IntRegs:$src1)),
954 (S2_clrbit_i (f32 IntRegs:$src1), 31)>,
957 def : Pat <(fneg (f32 IntRegs:$src1)),
958 (S2_togglebit_i (f32 IntRegs:$src1), 31)>,
962 def : Pat <(fabs (f64 DoubleRegs:$src1)),
963 (S2_clrbit_i (f32 (EXTRACT_SUBREG DoubleRegs:$src1, subreg_hireg)), 31)>,
966 def : Pat <(fabs (f64 DoubleRegs:$src1)),
967 (S2_clrbit_i (f32 (EXTRACT_SUBREG DoubleRegs:$src1, subreg_hireg)), 31)>,