1 //=- HexagonInstrInfoV5.td - Target Desc. for Hexagon Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Hexagon V5 instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
18 //Rdd[+]=vrmpybsu(Rss,Rtt)
19 let Predicates = [HasV5T], isCodeGenOnly = 0 in {
20 def M5_vrmpybsu: T_XTYPE_Vect<"vrmpybsu", 0b110, 0b001, 0>;
21 def M5_vrmacbsu: T_XTYPE_Vect_acc<"vrmpybsu", 0b110, 0b001, 0>;
23 //Rdd[+]=vrmpybu(Rss,Rtt)
24 def M5_vrmpybuu: T_XTYPE_Vect<"vrmpybu", 0b100, 0b001, 0>;
25 def M5_vrmacbuu: T_XTYPE_Vect_acc<"vrmpybu", 0b100, 0b001, 0>;
27 def M5_vdmpybsu: T_M2_vmpy<"vdmpybsu", 0b101, 0b001, 0, 0, 1>;
28 def M5_vdmacbsu: T_M2_vmpy_acc_sat <"vdmpybsu", 0b001, 0b001, 0, 0>;
31 // Vector multiply bytes
32 // Rdd=vmpyb[s]u(Rs,Rt)
33 let Predicates = [HasV5T], isCodeGenOnly = 0 in {
34 def M5_vmpybsu: T_XTYPE_mpy64 <"vmpybsu", 0b010, 0b001, 0, 0, 0>;
35 def M5_vmpybuu: T_XTYPE_mpy64 <"vmpybu", 0b100, 0b001, 0, 0, 0>;
37 // Rxx+=vmpyb[s]u(Rs,Rt)
38 def M5_vmacbsu: T_XTYPE_mpy64_acc <"vmpybsu", "+", 0b110, 0b001, 0, 0, 0>;
39 def M5_vmacbuu: T_XTYPE_mpy64_acc <"vmpybu", "+", 0b100, 0b001, 0, 0, 0>;
41 // Rd=vaddhub(Rss,Rtt):sat
42 let hasNewValue = 1, opNewValue = 0 in
43 def A5_vaddhubs: T_S3op_1 <"vaddhub", IntRegs, 0b01, 0b001, 0, 1>;
46 let isCodeGenOnly = 0 in
47 def S2_asr_i_p_rnd : S_2OpInstImm<"asr", 0b110, 0b111, u6Imm,
49 (sra (i64 (add (i64 (sra I64:$src1, u6ImmPred:$src2)), 1)),
53 let Inst{13-8} = src2;
56 def S2_asr_i_p_rnd_goodsyntax
57 : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u6Imm:$src2),
58 "$dst = asrrnd($src1, #$src2)">;
60 let isCodeGenOnly = 0 in
61 def C4_fastcorner9 : T_LOGICAL_2OP<"fastcorner9", 0b000, 0, 0>,
63 let Inst{13,7,4} = 0b111;
66 let isCodeGenOnly = 0 in
67 def C4_fastcorner9_not : T_LOGICAL_2OP<"!fastcorner9", 0b000, 0, 0>,
69 let Inst{20,13,7,4} = 0b1111;
72 def SDTHexagonFCONST32 : SDTypeProfile<1, 1, [
75 def HexagonFCONST32 : SDNode<"HexagonISD::FCONST32", SDTHexagonFCONST32>;
77 let isReMaterializable = 1, isMoveImm = 1 in
78 def FCONST32_nsdata : LDInst<(outs IntRegs:$dst), (ins globaladdress:$global),
79 "$dst = CONST32(#$global)",
80 [(set (f32 IntRegs:$dst),
81 (HexagonFCONST32 tglobaladdr:$global))]>,
84 let isReMaterializable = 1, isMoveImm = 1 in
85 def CONST64_Float_Real : LDInst<(outs DoubleRegs:$dst), (ins f64imm:$src1),
86 "$dst = CONST64(#$src1)",
87 [(set DoubleRegs:$dst, fpimm:$src1)]>,
90 let isReMaterializable = 1, isMoveImm = 1 in
91 def CONST32_Float_Real : LDInst<(outs IntRegs:$dst), (ins f32imm:$src1),
92 "$dst = CONST32(#$src1)",
93 [(set IntRegs:$dst, fpimm:$src1)]>,
96 // Transfer immediate float.
97 // Only works with single precision fp value.
98 // For double precision, use CONST64_float_real, as 64bit transfer
99 // can only hold 40-bit values - 32 from const ext + 8 bit immediate.
100 // Make sure that complexity is more than the CONST32 pattern in
101 // HexagonInstrInfo.td patterns.
102 let isExtended = 1, opExtendable = 1, isMoveImm = 1, isReMaterializable = 1,
103 isPredicable = 1, AddedComplexity = 30, validSubTargets = HasV5SubT,
105 def TFRI_f : ALU32_ri<(outs IntRegs:$dst), (ins f32Ext:$src1),
107 [(set IntRegs:$dst, fpimm:$src1)]>,
110 let isExtended = 1, opExtendable = 2, isPredicated = 1,
111 hasSideEffects = 0, validSubTargets = HasV5SubT in
112 def TFRI_cPt_f : ALU32_ri<(outs IntRegs:$dst),
113 (ins PredRegs:$src1, f32Ext:$src2),
114 "if ($src1) $dst = #$src2",
118 let isExtended = 1, opExtendable = 2, isPredicated = 1, isPredicatedFalse = 1,
119 hasSideEffects = 0, validSubTargets = HasV5SubT in
120 def TFRI_cNotPt_f : ALU32_ri<(outs IntRegs:$dst),
121 (ins PredRegs:$src1, f32Ext:$src2),
122 "if (!$src1) $dst =#$src2",
126 def SDTHexagonI32I64: SDTypeProfile<1, 1, [SDTCisVT<0, i32>,
129 def HexagonPOPCOUNT: SDNode<"HexagonISD::POPCOUNT", SDTHexagonI32I64>;
131 let hasNewValue = 1, validSubTargets = HasV5SubT, isCodeGenOnly = 0 in
132 def S5_popcountp : ALU64_rr<(outs IntRegs:$Rd), (ins DoubleRegs:$Rss),
133 "$Rd = popcount($Rss)",
134 [(set I32:$Rd, (HexagonPOPCOUNT I64:$Rss))], "", S_2op_tc_2_SLOT23>,
141 let Inst{27-21} = 0b1000011;
142 let Inst{7-5} = 0b011;
144 let Inst{20-16} = Rss;
147 defm: Loadx_pat<load, f32, s11_2ExtPred, L2_loadri_io>;
148 defm: Loadx_pat<load, f64, s11_3ExtPred, L2_loadrd_io>;
150 defm: Storex_pat<store, F32, s11_2ExtPred, S2_storeri_io>;
151 defm: Storex_pat<store, F64, s11_3ExtPred, S2_storerd_io>;
153 let isFP = 1, hasNewValue = 1, opNewValue = 0 in
154 class T_MInstFloat <string mnemonic, bits<3> MajOp, bits<3> MinOp>
155 : MInst<(outs IntRegs:$Rd),
156 (ins IntRegs:$Rs, IntRegs:$Rt),
157 "$Rd = "#mnemonic#"($Rs, $Rt)", [],
158 "" , M_tc_3or4x_SLOT23 > ,
166 let Inst{27-24} = 0b1011;
167 let Inst{23-21} = MajOp;
168 let Inst{20-16} = Rs;
171 let Inst{7-5} = MinOp;
175 let isCommutable = 1, isCodeGenOnly = 0 in {
176 def F2_sfadd : T_MInstFloat < "sfadd", 0b000, 0b000>;
177 def F2_sfmpy : T_MInstFloat < "sfmpy", 0b010, 0b000>;
180 let isCodeGenOnly = 0 in
181 def F2_sfsub : T_MInstFloat < "sfsub", 0b000, 0b001>;
183 def: Pat<(f32 (fadd F32:$src1, F32:$src2)),
184 (F2_sfadd F32:$src1, F32:$src2)>;
186 def: Pat<(f32 (fsub F32:$src1, F32:$src2)),
187 (F2_sfsub F32:$src1, F32:$src2)>;
189 def: Pat<(f32 (fmul F32:$src1, F32:$src2)),
190 (F2_sfmpy F32:$src1, F32:$src2)>;
192 let Itinerary = M_tc_3x_SLOT23, isCodeGenOnly = 0 in {
193 def F2_sfmax : T_MInstFloat < "sfmax", 0b100, 0b000>;
194 def F2_sfmin : T_MInstFloat < "sfmin", 0b100, 0b001>;
197 let isCodeGenOnly = 0 in {
198 def F2_sffixupn : T_MInstFloat < "sffixupn", 0b110, 0b000>;
199 def F2_sffixupd : T_MInstFloat < "sffixupd", 0b110, 0b001>;
202 // F2_sfrecipa: Reciprocal approximation for division.
203 let isPredicateLate = 1, isFP = 1,
204 hasSideEffects = 0, hasNewValue = 1, isCodeGenOnly = 0 in
205 def F2_sfrecipa: MInst <
206 (outs IntRegs:$Rd, PredRegs:$Pe),
207 (ins IntRegs:$Rs, IntRegs:$Rt),
208 "$Rd, $Pe = sfrecipa($Rs, $Rt)">,
216 let Inst{27-21} = 0b1011111;
217 let Inst{20-16} = Rs;
225 // F2_dfcmpeq: Floating point compare for equal.
226 let isCompare = 1, isFP = 1 in
227 class T_fcmp <string mnemonic, RegisterClass RC, bits<3> MinOp,
228 list<dag> pattern = [] >
229 : ALU64Inst <(outs PredRegs:$dst), (ins RC:$src1, RC:$src2),
230 "$dst = "#mnemonic#"($src1, $src2)", pattern,
231 "" , ALU64_tc_2early_SLOT23 > ,
239 let Inst{27-21} = 0b0010111;
240 let Inst{20-16} = src1;
241 let Inst{12-8} = src2;
242 let Inst{7-5} = MinOp;
246 class T_fcmp64 <string mnemonic, PatFrag OpNode, bits<3> MinOp>
247 : T_fcmp <mnemonic, DoubleRegs, MinOp,
248 [(set I1:$dst, (OpNode F64:$src1, F64:$src2))]> {
250 let Inst{27-21} = 0b0010111;
253 class T_fcmp32 <string mnemonic, PatFrag OpNode, bits<3> MinOp>
254 : T_fcmp <mnemonic, IntRegs, MinOp,
255 [(set I1:$dst, (OpNode F32:$src1, F32:$src2))]> {
257 let Inst{27-21} = 0b0111111;
260 let isCodeGenOnly = 0 in {
261 def F2_dfcmpeq : T_fcmp64<"dfcmp.eq", setoeq, 0b000>;
262 def F2_dfcmpgt : T_fcmp64<"dfcmp.gt", setogt, 0b001>;
263 def F2_dfcmpge : T_fcmp64<"dfcmp.ge", setoge, 0b010>;
264 def F2_dfcmpuo : T_fcmp64<"dfcmp.uo", setuo, 0b011>;
266 def F2_sfcmpge : T_fcmp32<"sfcmp.ge", setoge, 0b000>;
267 def F2_sfcmpuo : T_fcmp32<"sfcmp.uo", setuo, 0b001>;
268 def F2_sfcmpeq : T_fcmp32<"sfcmp.eq", setoeq, 0b011>;
269 def F2_sfcmpgt : T_fcmp32<"sfcmp.gt", setogt, 0b100>;
272 //===----------------------------------------------------------------------===//
273 // Multiclass to define 'Def Pats' for ordered gt, ge, eq operations.
274 //===----------------------------------------------------------------------===//
276 let Predicates = [HasV5T] in
277 multiclass T_fcmp_pats<PatFrag cmpOp, InstHexagon IntMI, InstHexagon DoubleMI> {
279 def: Pat<(i1 (cmpOp F32:$src1, F32:$src2)),
280 (IntMI F32:$src1, F32:$src2)>;
282 def: Pat<(i1 (cmpOp F64:$src1, F64:$src2)),
283 (DoubleMI F64:$src1, F64:$src2)>;
286 defm : T_fcmp_pats <seteq, F2_sfcmpeq, F2_dfcmpeq>;
287 defm : T_fcmp_pats <setgt, F2_sfcmpgt, F2_dfcmpgt>;
288 defm : T_fcmp_pats <setge, F2_sfcmpge, F2_dfcmpge>;
290 //===----------------------------------------------------------------------===//
291 // Multiclass to define 'Def Pats' for unordered gt, ge, eq operations.
292 //===----------------------------------------------------------------------===//
293 let Predicates = [HasV5T] in
294 multiclass unord_Pats <PatFrag cmpOp, InstHexagon IntMI, InstHexagon DoubleMI> {
296 def: Pat<(i1 (cmpOp F32:$src1, F32:$src2)),
297 (C2_or (F2_sfcmpuo F32:$src1, F32:$src2),
298 (IntMI F32:$src1, F32:$src2))>;
301 def: Pat<(i1 (cmpOp F64:$src1, F64:$src2)),
302 (C2_or (F2_dfcmpuo F64:$src1, F64:$src2),
303 (DoubleMI F64:$src1, F64:$src2))>;
306 defm : unord_Pats <setuge, F2_sfcmpge, F2_dfcmpge>;
307 defm : unord_Pats <setugt, F2_sfcmpgt, F2_dfcmpgt>;
308 defm : unord_Pats <setueq, F2_sfcmpeq, F2_dfcmpeq>;
310 //===----------------------------------------------------------------------===//
311 // Multiclass to define 'Def Pats' for the following dags:
312 // seteq(setoeq(op1, op2), 0) -> not(setoeq(op1, op2))
313 // seteq(setoeq(op1, op2), 1) -> setoeq(op1, op2)
314 // setne(setoeq(op1, op2), 0) -> setoeq(op1, op2)
315 // setne(setoeq(op1, op2), 1) -> not(setoeq(op1, op2))
316 //===----------------------------------------------------------------------===//
317 let Predicates = [HasV5T] in
318 multiclass eq_ordgePats <PatFrag cmpOp, InstHexagon IntMI,
319 InstHexagon DoubleMI> {
321 def: Pat<(i1 (seteq (i1 (cmpOp F32:$src1, F32:$src2)), 0)),
322 (C2_not (IntMI F32:$src1, F32:$src2))>;
323 def: Pat<(i1 (seteq (i1 (cmpOp F32:$src1, F32:$src2)), 1)),
324 (IntMI F32:$src1, F32:$src2)>;
325 def: Pat<(i1 (setne (i1 (cmpOp F32:$src1, F32:$src2)), 0)),
326 (IntMI F32:$src1, F32:$src2)>;
327 def: Pat<(i1 (setne (i1 (cmpOp F32:$src1, F32:$src2)), 1)),
328 (C2_not (IntMI F32:$src1, F32:$src2))>;
331 def : Pat<(i1 (seteq (i1 (cmpOp F64:$src1, F64:$src2)), 0)),
332 (C2_not (DoubleMI F64:$src1, F64:$src2))>;
333 def : Pat<(i1 (seteq (i1 (cmpOp F64:$src1, F64:$src2)), 1)),
334 (DoubleMI F64:$src1, F64:$src2)>;
335 def : Pat<(i1 (setne (i1 (cmpOp F64:$src1, F64:$src2)), 0)),
336 (DoubleMI F64:$src1, F64:$src2)>;
337 def : Pat<(i1 (setne (i1 (cmpOp F64:$src1, F64:$src2)), 1)),
338 (C2_not (DoubleMI F64:$src1, F64:$src2))>;
341 defm : eq_ordgePats<setoeq, F2_sfcmpeq, F2_dfcmpeq>;
342 defm : eq_ordgePats<setoge, F2_sfcmpge, F2_dfcmpge>;
343 defm : eq_ordgePats<setogt, F2_sfcmpgt, F2_dfcmpgt>;
345 //===----------------------------------------------------------------------===//
346 // Multiclass to define 'Def Pats' for the following dags:
347 // seteq(setolt(op1, op2), 0) -> not(setogt(op2, op1))
348 // seteq(setolt(op1, op2), 1) -> setogt(op2, op1)
349 // setne(setolt(op1, op2), 0) -> setogt(op2, op1)
350 // setne(setolt(op1, op2), 1) -> not(setogt(op2, op1))
351 //===----------------------------------------------------------------------===//
352 let Predicates = [HasV5T] in
353 multiclass eq_ordltPats <PatFrag cmpOp, InstHexagon IntMI,
354 InstHexagon DoubleMI> {
356 def: Pat<(i1 (seteq (i1 (cmpOp F32:$src1, F32:$src2)), 0)),
357 (C2_not (IntMI F32:$src2, F32:$src1))>;
358 def: Pat<(i1 (seteq (i1 (cmpOp F32:$src1, F32:$src2)), 1)),
359 (IntMI F32:$src2, F32:$src1)>;
360 def: Pat<(i1 (setne (i1 (cmpOp F32:$src1, F32:$src2)), 0)),
361 (IntMI F32:$src2, F32:$src1)>;
362 def: Pat<(i1 (setne (i1 (cmpOp F32:$src1, F32:$src2)), 1)),
363 (C2_not (IntMI F32:$src2, F32:$src1))>;
366 def: Pat<(i1 (seteq (i1 (cmpOp F64:$src1, F64:$src2)), 0)),
367 (C2_not (DoubleMI F64:$src2, F64:$src1))>;
368 def: Pat<(i1 (seteq (i1 (cmpOp F64:$src1, F64:$src2)), 1)),
369 (DoubleMI F64:$src2, F64:$src1)>;
370 def: Pat<(i1 (setne (i1 (cmpOp F64:$src1, F64:$src2)), 0)),
371 (DoubleMI F64:$src2, F64:$src1)>;
372 def: Pat<(i1 (setne (i1 (cmpOp F64:$src1, F64:$src2)), 0)),
373 (C2_not (DoubleMI F64:$src2, F64:$src1))>;
376 defm : eq_ordltPats<setole, F2_sfcmpge, F2_dfcmpge>;
377 defm : eq_ordltPats<setolt, F2_sfcmpgt, F2_dfcmpgt>;
380 // o. seto inverse of setuo. http://llvm.org/docs/LangRef.html#i_fcmp
381 let Predicates = [HasV5T] in {
382 def: Pat<(i1 (seto F32:$src1, F32:$src2)),
383 (C2_not (F2_sfcmpuo F32:$src2, F32:$src1))>;
384 def: Pat<(i1 (seto F32:$src1, fpimm:$src2)),
385 (C2_not (F2_sfcmpuo (TFRI_f fpimm:$src2), F32:$src1))>;
386 def: Pat<(i1 (seto F64:$src1, F64:$src2)),
387 (C2_not (F2_dfcmpuo F64:$src2, F64:$src1))>;
388 def: Pat<(i1 (seto F64:$src1, fpimm:$src2)),
389 (C2_not (F2_dfcmpuo (CONST64_Float_Real fpimm:$src2), F64:$src1))>;
393 let Predicates = [HasV5T] in {
394 def: Pat<(i1 (setolt F32:$src1, F32:$src2)),
395 (F2_sfcmpgt F32:$src2, F32:$src1)>;
396 def: Pat<(i1 (setolt F32:$src1, fpimm:$src2)),
397 (F2_sfcmpgt (f32 (TFRI_f fpimm:$src2)), F32:$src1)>;
398 def: Pat<(i1 (setolt F64:$src1, F64:$src2)),
399 (F2_dfcmpgt F64:$src2, F64:$src1)>;
400 def: Pat<(i1 (setolt F64:$src1, fpimm:$src2)),
401 (F2_dfcmpgt (CONST64_Float_Real fpimm:$src2), F64:$src1)>;
405 let Predicates = [HasV5T] in {
406 def: Pat<(i1 (setult F32:$src1, F32:$src2)),
407 (C2_or (F2_sfcmpuo F32:$src1, F32:$src2),
408 (F2_sfcmpgt F32:$src2, F32:$src1))>;
409 def: Pat<(i1 (setult F32:$src1, fpimm:$src2)),
410 (C2_or (F2_sfcmpuo F32:$src1, (TFRI_f fpimm:$src2)),
411 (F2_sfcmpgt (TFRI_f fpimm:$src2), F32:$src1))>;
412 def: Pat<(i1 (setult F64:$src1, F64:$src2)),
413 (C2_or (F2_dfcmpuo F64:$src1, F64:$src2),
414 (F2_dfcmpgt F64:$src2, F64:$src1))>;
415 def: Pat<(i1 (setult F64:$src1, fpimm:$src2)),
416 (C2_or (F2_dfcmpuo F64:$src1, (CONST64_Float_Real fpimm:$src2)),
417 (F2_dfcmpgt (CONST64_Float_Real fpimm:$src2), F64:$src1))>;
421 let Predicates = [HasV5T] in {
422 // rs <= rt -> rt >= rs.
423 def: Pat<(i1 (setole F32:$src1, F32:$src2)),
424 (F2_sfcmpge F32:$src2, F32:$src1)>;
425 def: Pat<(i1 (setole F32:$src1, fpimm:$src2)),
426 (F2_sfcmpge (TFRI_f fpimm:$src2), F32:$src1)>;
428 // Rss <= Rtt -> Rtt >= Rss.
429 def: Pat<(i1 (setole F64:$src1, F64:$src2)),
430 (F2_dfcmpge F64:$src2, F64:$src1)>;
431 def: Pat<(i1 (setole F64:$src1, fpimm:$src2)),
432 (F2_dfcmpge (CONST64_Float_Real fpimm:$src2), F64:$src1)>;
436 let Predicates = [HasV5T] in {
437 // rs <= rt -> rt >= rs.
438 def: Pat<(i1 (setule F32:$src1, F32:$src2)),
439 (C2_or (F2_sfcmpuo F32:$src1, F32:$src2),
440 (F2_sfcmpge F32:$src2, F32:$src1))>;
441 def: Pat<(i1 (setule F32:$src1, fpimm:$src2)),
442 (C2_or (F2_sfcmpuo F32:$src1, (TFRI_f fpimm:$src2)),
443 (F2_sfcmpge (TFRI_f fpimm:$src2), F32:$src1))>;
444 def: Pat<(i1 (setule F64:$src1, F64:$src2)),
445 (C2_or (F2_dfcmpuo F64:$src1, F64:$src2),
446 (F2_dfcmpge F64:$src2, F64:$src1))>;
447 def: Pat<(i1 (setule F64:$src1, fpimm:$src2)),
448 (C2_or (F2_dfcmpuo F64:$src1, (CONST64_Float_Real fpimm:$src2)),
449 (F2_dfcmpge (CONST64_Float_Real fpimm:$src2), F64:$src1))>;
453 let Predicates = [HasV5T] in {
454 def: Pat<(i1 (setone F32:$src1, F32:$src2)),
455 (C2_not (F2_sfcmpeq F32:$src1, F32:$src2))>;
456 def: Pat<(i1 (setone F64:$src1, F64:$src2)),
457 (C2_not (F2_dfcmpeq F64:$src1, F64:$src2))>;
458 def: Pat<(i1 (setone F32:$src1, fpimm:$src2)),
459 (C2_not (F2_sfcmpeq F32:$src1, (TFRI_f fpimm:$src2)))>;
460 def: Pat<(i1 (setone F64:$src1, fpimm:$src2)),
461 (C2_not (F2_dfcmpeq F64:$src1, (CONST64_Float_Real fpimm:$src2)))>;
465 let Predicates = [HasV5T] in {
466 def: Pat<(i1 (setune F32:$src1, F32:$src2)),
467 (C2_or (F2_sfcmpuo F32:$src1, F32:$src2),
468 (C2_not (F2_sfcmpeq F32:$src1, F32:$src2)))>;
469 def: Pat<(i1 (setune F64:$src1, F64:$src2)),
470 (C2_or (F2_dfcmpuo F64:$src1, F64:$src2),
471 (C2_not (F2_dfcmpeq F64:$src1, F64:$src2)))>;
472 def: Pat<(i1 (setune F32:$src1, fpimm:$src2)),
473 (C2_or (F2_sfcmpuo F32:$src1, (TFRI_f fpimm:$src2)),
474 (C2_not (F2_sfcmpeq F32:$src1, (TFRI_f fpimm:$src2))))>;
475 def: Pat<(i1 (setune F64:$src1, fpimm:$src2)),
476 (C2_or (F2_dfcmpuo F64:$src1, (CONST64_Float_Real fpimm:$src2)),
477 (C2_not (F2_dfcmpeq F64:$src1,
478 (CONST64_Float_Real fpimm:$src2))))>;
481 // Besides set[o|u][comparions], we also need set[comparisons].
482 let Predicates = [HasV5T] in {
484 def: Pat<(i1 (setlt F32:$src1, F32:$src2)),
485 (F2_sfcmpgt F32:$src2, F32:$src1)>;
486 def: Pat<(i1 (setlt F32:$src1, fpimm:$src2)),
487 (F2_sfcmpgt (TFRI_f fpimm:$src2), F32:$src1)>;
488 def: Pat<(i1 (setlt F64:$src1, F64:$src2)),
489 (F2_dfcmpgt F64:$src2, F64:$src1)>;
490 def: Pat<(i1 (setlt F64:$src1, fpimm:$src2)),
491 (F2_dfcmpgt (CONST64_Float_Real fpimm:$src2), F64:$src1)>;
494 // rs <= rt -> rt >= rs.
495 def: Pat<(i1 (setle F32:$src1, F32:$src2)),
496 (F2_sfcmpge F32:$src2, F32:$src1)>;
497 def: Pat<(i1 (setle F32:$src1, fpimm:$src2)),
498 (F2_sfcmpge (TFRI_f fpimm:$src2), F32:$src1)>;
500 // Rss <= Rtt -> Rtt >= Rss.
501 def: Pat<(i1 (setle F64:$src1, F64:$src2)),
502 (F2_dfcmpge F64:$src2, F64:$src1)>;
503 def: Pat<(i1 (setle F64:$src1, fpimm:$src2)),
504 (F2_dfcmpge (CONST64_Float_Real fpimm:$src2), F64:$src1)>;
507 def: Pat<(i1 (setne F32:$src1, F32:$src2)),
508 (C2_not (F2_sfcmpeq F32:$src1, F32:$src2))>;
509 def: Pat<(i1 (setne F64:$src1, F64:$src2)),
510 (C2_not (F2_dfcmpeq F64:$src1, F64:$src2))>;
511 def: Pat<(i1 (setne F32:$src1, fpimm:$src2)),
512 (C2_not (F2_sfcmpeq F32:$src1, (TFRI_f fpimm:$src2)))>;
513 def: Pat<(i1 (setne F64:$src1, fpimm:$src2)),
514 (C2_not (F2_dfcmpeq F64:$src1, (CONST64_Float_Real fpimm:$src2)))>;
517 // F2 convert template classes:
519 class F2_RDD_RSS_CONVERT<string mnemonic, bits<3> MinOp,
520 SDNode Op, PatLeaf RCOut, PatLeaf RCIn,
522 : SInst <(outs DoubleRegs:$Rdd), (ins DoubleRegs:$Rss),
523 "$Rdd = "#mnemonic#"($Rss)"#chop,
524 [(set RCOut:$Rdd, (Op RCIn:$Rss))], "",
525 S_2op_tc_3or4x_SLOT23> {
531 let Inst{27-21} = 0b0000111;
532 let Inst{20-16} = Rss;
533 let Inst{7-5} = MinOp;
538 class F2_RDD_RS_CONVERT<string mnemonic, bits<3> MinOp,
539 SDNode Op, PatLeaf RCOut, PatLeaf RCIn,
541 : SInst <(outs DoubleRegs:$Rdd), (ins IntRegs:$Rs),
542 "$Rdd = "#mnemonic#"($Rs)"#chop,
543 [(set RCOut:$Rdd, (Op RCIn:$Rs))], "",
544 S_2op_tc_3or4x_SLOT23> {
550 let Inst{27-21} = 0b0100100;
551 let Inst{20-16} = Rs;
552 let Inst{7-5} = MinOp;
556 let isFP = 1, hasNewValue = 1 in
557 class F2_RD_RSS_CONVERT<string mnemonic, bits<3> MinOp,
558 SDNode Op, PatLeaf RCOut, PatLeaf RCIn,
560 : SInst <(outs IntRegs:$Rd), (ins DoubleRegs:$Rss),
561 "$Rd = "#mnemonic#"($Rss)"#chop,
562 [(set RCOut:$Rd, (Op RCIn:$Rss))], "",
563 S_2op_tc_3or4x_SLOT23> {
569 let Inst{27-24} = 0b1000;
570 let Inst{23-21} = MinOp;
571 let Inst{20-16} = Rss;
572 let Inst{7-5} = 0b001;
576 let isFP = 1, hasNewValue = 1 in
577 class F2_RD_RS_CONVERT<string mnemonic, bits<3> MajOp, bits<3> MinOp,
578 SDNode Op, PatLeaf RCOut, PatLeaf RCIn,
580 : SInst <(outs IntRegs:$Rd), (ins IntRegs:$Rs),
581 "$Rd = "#mnemonic#"($Rs)"#chop,
582 [(set RCOut:$Rd, (Op RCIn:$Rs))], "",
583 S_2op_tc_3or4x_SLOT23> {
589 let Inst{27-24} = 0b1011;
590 let Inst{23-21} = MajOp;
591 let Inst{20-16} = Rs;
592 let Inst{7-5} = MinOp;
596 // Convert single precision to double precision and vice-versa.
597 let isCodeGenOnly = 0 in {
598 def F2_conv_sf2df : F2_RDD_RS_CONVERT <"convert_sf2df", 0b000,
601 def F2_conv_df2sf : F2_RD_RSS_CONVERT <"convert_df2sf", 0b000,
604 // Convert Integer to Floating Point.
605 def F2_conv_d2sf : F2_RD_RSS_CONVERT <"convert_d2sf", 0b010,
606 sint_to_fp, F32, I64>;
607 def F2_conv_ud2sf : F2_RD_RSS_CONVERT <"convert_ud2sf", 0b001,
608 uint_to_fp, F32, I64>;
609 def F2_conv_uw2sf : F2_RD_RS_CONVERT <"convert_uw2sf", 0b001, 0b000,
610 uint_to_fp, F32, I32>;
611 def F2_conv_w2sf : F2_RD_RS_CONVERT <"convert_w2sf", 0b010, 0b000,
612 sint_to_fp, F32, I32>;
613 def F2_conv_d2df : F2_RDD_RSS_CONVERT <"convert_d2df", 0b011,
614 sint_to_fp, F64, I64>;
615 def F2_conv_ud2df : F2_RDD_RSS_CONVERT <"convert_ud2df", 0b010,
616 uint_to_fp, F64, I64>;
617 def F2_conv_uw2df : F2_RDD_RS_CONVERT <"convert_uw2df", 0b001,
618 uint_to_fp, F64, I32>;
619 def F2_conv_w2df : F2_RDD_RS_CONVERT <"convert_w2df", 0b010,
620 sint_to_fp, F64, I32>;
622 // Convert Floating Point to Integer - default.
623 def F2_conv_df2uw_chop : F2_RD_RSS_CONVERT <"convert_df2uw", 0b101,
624 fp_to_uint, I32, F64, ":chop">;
625 def F2_conv_df2w_chop : F2_RD_RSS_CONVERT <"convert_df2w", 0b111,
626 fp_to_sint, I32, F64, ":chop">;
627 def F2_conv_sf2uw_chop : F2_RD_RS_CONVERT <"convert_sf2uw", 0b011, 0b001,
628 fp_to_uint, I32, F32, ":chop">;
629 def F2_conv_sf2w_chop : F2_RD_RS_CONVERT <"convert_sf2w", 0b100, 0b001,
630 fp_to_sint, I32, F32, ":chop">;
631 def F2_conv_df2d_chop : F2_RDD_RSS_CONVERT <"convert_df2d", 0b110,
632 fp_to_sint, I64, F64, ":chop">;
633 def F2_conv_df2ud_chop : F2_RDD_RSS_CONVERT <"convert_df2ud", 0b111,
634 fp_to_uint, I64, F64, ":chop">;
635 def F2_conv_sf2d_chop : F2_RDD_RS_CONVERT <"convert_sf2d", 0b110,
636 fp_to_sint, I64, F32, ":chop">;
637 def F2_conv_sf2ud_chop : F2_RDD_RS_CONVERT <"convert_sf2ud", 0b101,
638 fp_to_uint, I64, F32, ":chop">;
640 // Convert Floating Point to Integer: non-chopped.
641 let AddedComplexity = 20, Predicates = [HasV5T, IEEERndNearV5T] in {
642 def F2_conv_df2d : F2_RDD_RSS_CONVERT <"convert_df2d", 0b000,
643 fp_to_sint, I64, F64>;
644 def F2_conv_df2ud : F2_RDD_RSS_CONVERT <"convert_df2ud", 0b001,
645 fp_to_uint, I64, F64>;
646 def F2_conv_sf2ud : F2_RDD_RS_CONVERT <"convert_sf2ud", 0b011,
647 fp_to_uint, I64, F32>;
648 def F2_conv_sf2d : F2_RDD_RS_CONVERT <"convert_sf2d", 0b100,
649 fp_to_sint, I64, F32>;
650 def F2_conv_df2uw : F2_RD_RSS_CONVERT <"convert_df2uw", 0b011,
651 fp_to_uint, I32, F64>;
652 def F2_conv_df2w : F2_RD_RSS_CONVERT <"convert_df2w", 0b100,
653 fp_to_sint, I32, F64>;
654 def F2_conv_sf2uw : F2_RD_RS_CONVERT <"convert_sf2uw", 0b011, 0b000,
655 fp_to_uint, I32, F32>;
656 def F2_conv_sf2w : F2_RD_RS_CONVERT <"convert_sf2w", 0b100, 0b000,
657 fp_to_sint, I32, F32>;
662 let isFP = 1, hasNewValue = 1, isCodeGenOnly = 0 in
663 def F2_sffixupr: SInst<(outs IntRegs:$Rd), (ins IntRegs:$Rs),
664 "$Rd = sffixupr($Rs)",
665 [], "" , S_2op_tc_3or4x_SLOT23>, Requires<[HasV5T]> {
671 let Inst{27-21} = 0b1011101;
672 let Inst{20-16} = Rs;
673 let Inst{7-5} = 0b000;
677 // Bitcast is different than [fp|sint|uint]_to_[sint|uint|fp].
678 let Predicates = [HasV5T] in {
679 def: Pat <(i32 (bitconvert F32:$src)), (I32:$src)>;
680 def: Pat <(f32 (bitconvert I32:$src)), (F32:$src)>;
681 def: Pat <(i64 (bitconvert F64:$src)), (I64:$src)>;
682 def: Pat <(f64 (bitconvert I64:$src)), (F64:$src)>;
685 // F2_sffma: Floating-point fused multiply add.
686 let isFP = 1, hasNewValue = 1 in
687 class T_sfmpy_acc <bit isSub, bit isLib>
688 : MInst<(outs IntRegs:$Rx),
689 (ins IntRegs:$dst2, IntRegs:$Rs, IntRegs:$Rt),
690 "$Rx "#!if(isSub, "-=","+=")#" sfmpy($Rs, $Rt)"#!if(isLib, ":lib",""),
691 [], "$dst2 = $Rx" , M_tc_3_SLOT23 > ,
699 let Inst{27-21} = 0b1111000;
700 let Inst{20-16} = Rs;
709 let isCodeGenOnly = 0 in {
710 def F2_sffma: T_sfmpy_acc <0, 0>;
711 def F2_sffms: T_sfmpy_acc <1, 0>;
712 def F2_sffma_lib: T_sfmpy_acc <0, 1>;
713 def F2_sffms_lib: T_sfmpy_acc <1, 1>;
716 // Floating-point fused multiply add w/ additional scaling (2**pu).
717 let isFP = 1, hasNewValue = 1, isCodeGenOnly = 0 in
718 def F2_sffma_sc: MInst <
720 (ins IntRegs:$dst2, IntRegs:$Rs, IntRegs:$Rt, PredRegs:$Pu),
721 "$Rx += sfmpy($Rs, $Rt, $Pu):scale" ,
722 [], "$dst2 = $Rx" , M_tc_3_SLOT23 > ,
731 let Inst{27-21} = 0b1111011;
732 let Inst{20-16} = Rs;
740 let isExtended = 1, isExtentSigned = 1, opExtentBits = 8, opExtendable = 3,
741 isPseudo = 1, InputType = "imm" in
742 def MUX_ir_f : ALU32_rr<(outs IntRegs:$dst),
743 (ins PredRegs:$src1, IntRegs:$src2, f32Ext:$src3),
744 "$dst = mux($src1, $src2, #$src3)",
745 [(set F32:$dst, (f32 (select I1:$src1, F32:$src2, fpimm:$src3)))]>,
748 let isExtended = 1, isExtentSigned = 1, opExtentBits = 8, opExtendable = 2,
749 isPseudo = 1, InputType = "imm" in
750 def MUX_ri_f : ALU32_rr<(outs IntRegs:$dst),
751 (ins PredRegs:$src1, f32Ext:$src2, IntRegs:$src3),
752 "$dst = mux($src1, #$src2, $src3)",
753 [(set F32:$dst, (f32 (select I1:$src1, fpimm:$src2, F32:$src3)))]>,
756 //===----------------------------------------------------------------------===//
757 // :natural forms of vasrh and vasrhub insns
758 //===----------------------------------------------------------------------===//
759 // S5_asrhub_rnd_sat: Vector arithmetic shift right by immediate with round,
760 // saturate, and pack.
761 let Defs = [USR_OVF], hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in
762 class T_ASRHUB<bit isSat>
763 : SInst <(outs IntRegs:$Rd),
764 (ins DoubleRegs:$Rss, u4Imm:$u4),
765 "$Rd = vasrhub($Rss, #$u4):"#!if(isSat, "sat", "raw"),
766 [], "", S_2op_tc_2_SLOT23>,
774 let Inst{27-21} = 0b1000011;
775 let Inst{20-16} = Rss;
776 let Inst{13-12} = 0b00;
778 let Inst{7-6} = 0b10;
782 let isCodeGenOnly = 0 in {
783 def S5_asrhub_rnd_sat : T_ASRHUB <0>;
784 def S5_asrhub_sat : T_ASRHUB <1>;
787 def S5_asrhub_rnd_sat_goodsyntax
788 : SInst <(outs IntRegs:$Rd), (ins DoubleRegs:$Rss, u4Imm:$u4),
789 "$Rd = vasrhub($Rss, #$u4):rnd:sat">, Requires<[HasV5T]>;
791 // S5_vasrhrnd: Vector arithmetic shift right by immediate with round.
792 let hasSideEffects = 0, isCodeGenOnly = 0 in
793 def S5_vasrhrnd : SInst <(outs DoubleRegs:$Rdd),
794 (ins DoubleRegs:$Rss, u4Imm:$u4),
795 "$Rdd = vasrh($Rss, #$u4):raw">,
803 let Inst{27-21} = 0b0000001;
804 let Inst{20-16} = Rss;
805 let Inst{13-12} = 0b00;
807 let Inst{7-5} = 0b000;
811 // Floating point reciprocal square root approximation
812 let Uses = [USR], isPredicateLate = 1, isFP = 1,
813 hasSideEffects = 0, hasNewValue = 1, opNewValue = 0,
814 validSubTargets = HasV5SubT, isCodeGenOnly = 0 in
815 def F2_sfinvsqrta: SInst <
816 (outs IntRegs:$Rd, PredRegs:$Pe),
818 "$Rd, $Pe = sfinvsqrta($Rs)" > ,
826 let Inst{27-21} = 0b1011111;
827 let Inst{20-16} = Rs;
833 // Complex multiply 32x16
834 let Defs = [USR_OVF], Itinerary = S_3op_tc_3x_SLOT23, isCodeGenOnly = 0 in {
835 def M4_cmpyi_whc : T_S3op_8<"cmpyiwh", 0b101, 1, 1, 1, 1>;
836 def M4_cmpyr_whc : T_S3op_8<"cmpyrwh", 0b111, 1, 1, 1, 1>;
839 // Classify floating-point value
840 let isFP = 1, isCodeGenOnly = 0 in
841 def F2_sfclass : T_TEST_BIT_IMM<"sfclass", 0b111>;
843 let isFP = 1, isCodeGenOnly = 0 in
844 def F2_dfclass: ALU64Inst<(outs PredRegs:$Pd), (ins DoubleRegs:$Rss, u5Imm:$u5),
845 "$Pd = dfclass($Rss, #$u5)",
846 [], "" , ALU64_tc_2early_SLOT23 > , Requires<[HasV5T]> {
852 let Inst{27-21} = 0b1100100;
853 let Inst{20-16} = Rss;
854 let Inst{12-10} = 0b000;
856 let Inst{4-3} = 0b10;
860 // Instructions to create floating point constant
861 let hasNewValue = 1, opNewValue = 0 in
862 class T_fimm <string mnemonic, RegisterClass RC, bits<4> RegType, bit isNeg>
863 : ALU64Inst<(outs RC:$dst), (ins u10Imm:$src),
864 "$dst = "#mnemonic#"(#$src)"#!if(isNeg, ":neg", ":pos"),
865 [], "", ALU64_tc_3x_SLOT23>, Requires<[HasV5T]> {
870 let Inst{27-24} = RegType;
872 let Inst{22} = isNeg;
873 let Inst{21} = src{9};
874 let Inst{13-5} = src{8-0};
878 let isCodeGenOnly = 0 in {
879 def F2_sfimm_p : T_fimm <"sfmake", IntRegs, 0b0110, 0>;
880 def F2_sfimm_n : T_fimm <"sfmake", IntRegs, 0b0110, 1>;
881 def F2_dfimm_p : T_fimm <"dfmake", DoubleRegs, 0b1001, 0>;
882 def F2_dfimm_n : T_fimm <"dfmake", DoubleRegs, 0b1001, 1>;
885 def : Pat <(fabs (f32 IntRegs:$src1)),
886 (S2_clrbit_i (f32 IntRegs:$src1), 31)>,
889 def : Pat <(fneg (f32 IntRegs:$src1)),
890 (S2_togglebit_i (f32 IntRegs:$src1), 31)>,
894 def : Pat <(fabs (f64 DoubleRegs:$src1)),
895 (S2_clrbit_i (f32 (EXTRACT_SUBREG DoubleRegs:$src1, subreg_hireg)), 31)>,
898 def : Pat <(fabs (f64 DoubleRegs:$src1)),
899 (S2_clrbit_i (f32 (EXTRACT_SUBREG DoubleRegs:$src1, subreg_hireg)), 31)>,