1 //=- HexagonInstrInfoV5.td - Target Desc. for Hexagon Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Hexagon V5 instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
18 //Rdd[+]=vrmpybsu(Rss,Rtt)
19 let Predicates = [HasV5T], isCodeGenOnly = 0 in {
20 def M5_vrmpybsu: T_XTYPE_Vect<"vrmpybsu", 0b110, 0b001, 0>;
21 def M5_vrmacbsu: T_XTYPE_Vect_acc<"vrmpybsu", 0b110, 0b001, 0>;
23 //Rdd[+]=vrmpybu(Rss,Rtt)
24 def M5_vrmpybuu: T_XTYPE_Vect<"vrmpybu", 0b100, 0b001, 0>;
25 def M5_vrmacbuu: T_XTYPE_Vect_acc<"vrmpybu", 0b100, 0b001, 0>;
27 def M5_vdmpybsu: T_M2_vmpy<"vdmpybsu", 0b101, 0b001, 0, 0, 1>;
28 def M5_vdmacbsu: T_M2_vmpy_acc_sat <"vdmpybsu", 0b001, 0b001, 0, 0>;
31 // Vector multiply bytes
32 // Rdd=vmpyb[s]u(Rs,Rt)
33 let Predicates = [HasV5T], isCodeGenOnly = 0 in {
34 def M5_vmpybsu: T_XTYPE_mpy64 <"vmpybsu", 0b010, 0b001, 0, 0, 0>;
35 def M5_vmpybuu: T_XTYPE_mpy64 <"vmpybu", 0b100, 0b001, 0, 0, 0>;
37 // Rxx+=vmpyb[s]u(Rs,Rt)
38 def M5_vmacbsu: T_XTYPE_mpy64_acc <"vmpybsu", "+", 0b110, 0b001, 0, 0, 0>;
39 def M5_vmacbuu: T_XTYPE_mpy64_acc <"vmpybu", "+", 0b100, 0b001, 0, 0, 0>;
41 // Rd=vaddhub(Rss,Rtt):sat
42 let hasNewValue = 1, opNewValue = 0 in
43 def A5_vaddhubs: T_S3op_1 <"vaddhub", IntRegs, 0b01, 0b001, 0, 1>;
46 let isCodeGenOnly = 0 in
47 def S2_asr_i_p_rnd : S_2OpInstImm<"asr", 0b110, 0b111, u6Imm,
49 (sra (i64 (add (i64 (sra I64:$src1, u6ImmPred:$src2)), 1)),
53 let Inst{13-8} = src2;
56 let isCodeGenOnly = 1 in
57 def S2_asr_i_p_rnd_goodsyntax
58 : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u6Imm:$src2),
59 "$dst = asrrnd($src1, #$src2)">;
61 let isCodeGenOnly = 0 in
62 def C4_fastcorner9 : T_LOGICAL_2OP<"fastcorner9", 0b000, 0, 0>,
64 let Inst{13,7,4} = 0b111;
67 let isCodeGenOnly = 0 in
68 def C4_fastcorner9_not : T_LOGICAL_2OP<"!fastcorner9", 0b000, 0, 0>,
70 let Inst{20,13,7,4} = 0b1111;
73 def SDTHexagonFCONST32 : SDTypeProfile<1, 1, [
76 def HexagonFCONST32 : SDNode<"HexagonISD::FCONST32", SDTHexagonFCONST32>;
78 let isReMaterializable = 1, isMoveImm = 1, isCodeGenOnly = 1 in
79 def FCONST32_nsdata : LDInst<(outs IntRegs:$dst), (ins globaladdress:$global),
80 "$dst = CONST32(#$global)",
81 [(set (f32 IntRegs:$dst),
82 (HexagonFCONST32 tglobaladdr:$global))]>,
85 let isReMaterializable = 1, isMoveImm = 1, isCodeGenOnly = 1 in
86 def CONST64_Float_Real : LDInst<(outs DoubleRegs:$dst), (ins f64imm:$src1),
87 "$dst = CONST64(#$src1)",
88 [(set DoubleRegs:$dst, fpimm:$src1)]>,
91 let isReMaterializable = 1, isMoveImm = 1, isCodeGenOnly = 1 in
92 def CONST32_Float_Real : LDInst<(outs IntRegs:$dst), (ins f32imm:$src1),
93 "$dst = CONST32(#$src1)",
94 [(set IntRegs:$dst, fpimm:$src1)]>,
97 // Transfer immediate float.
98 // Only works with single precision fp value.
99 // For double precision, use CONST64_float_real, as 64bit transfer
100 // can only hold 40-bit values - 32 from const ext + 8 bit immediate.
101 // Make sure that complexity is more than the CONST32 pattern in
102 // HexagonInstrInfo.td patterns.
103 let isExtended = 1, opExtendable = 1, isMoveImm = 1, isReMaterializable = 1,
104 isPredicable = 1, AddedComplexity = 30, validSubTargets = HasV5SubT,
106 def TFRI_f : ALU32_ri<(outs IntRegs:$dst), (ins f32Ext:$src1),
108 [(set IntRegs:$dst, fpimm:$src1)]>,
111 let isExtended = 1, opExtendable = 2, isPredicated = 1,
112 hasSideEffects = 0, validSubTargets = HasV5SubT in
113 def TFRI_cPt_f : ALU32_ri<(outs IntRegs:$dst),
114 (ins PredRegs:$src1, f32Ext:$src2),
115 "if ($src1) $dst = #$src2",
119 let isExtended = 1, opExtendable = 2, isPredicated = 1, isPredicatedFalse = 1,
120 hasSideEffects = 0, validSubTargets = HasV5SubT in
121 def TFRI_cNotPt_f : ALU32_ri<(outs IntRegs:$dst),
122 (ins PredRegs:$src1, f32Ext:$src2),
123 "if (!$src1) $dst =#$src2",
127 def SDTHexagonI32I64: SDTypeProfile<1, 1, [SDTCisVT<0, i32>,
130 def HexagonPOPCOUNT: SDNode<"HexagonISD::POPCOUNT", SDTHexagonI32I64>;
132 let hasNewValue = 1, validSubTargets = HasV5SubT, isCodeGenOnly = 0 in
133 def S5_popcountp : ALU64_rr<(outs IntRegs:$Rd), (ins DoubleRegs:$Rss),
134 "$Rd = popcount($Rss)",
135 [(set I32:$Rd, (HexagonPOPCOUNT I64:$Rss))], "", S_2op_tc_2_SLOT23>,
142 let Inst{27-21} = 0b1000011;
143 let Inst{7-5} = 0b011;
145 let Inst{20-16} = Rss;
148 defm: Loadx_pat<load, f32, s11_2ExtPred, L2_loadri_io>;
149 defm: Loadx_pat<load, f64, s11_3ExtPred, L2_loadrd_io>;
151 defm: Storex_pat<store, F32, s11_2ExtPred, S2_storeri_io>;
152 defm: Storex_pat<store, F64, s11_3ExtPred, S2_storerd_io>;
154 let isFP = 1, hasNewValue = 1, opNewValue = 0 in
155 class T_MInstFloat <string mnemonic, bits<3> MajOp, bits<3> MinOp>
156 : MInst<(outs IntRegs:$Rd),
157 (ins IntRegs:$Rs, IntRegs:$Rt),
158 "$Rd = "#mnemonic#"($Rs, $Rt)", [],
159 "" , M_tc_3or4x_SLOT23 > ,
167 let Inst{27-24} = 0b1011;
168 let Inst{23-21} = MajOp;
169 let Inst{20-16} = Rs;
172 let Inst{7-5} = MinOp;
176 let isCommutable = 1, isCodeGenOnly = 0 in {
177 def F2_sfadd : T_MInstFloat < "sfadd", 0b000, 0b000>;
178 def F2_sfmpy : T_MInstFloat < "sfmpy", 0b010, 0b000>;
181 let isCodeGenOnly = 0 in
182 def F2_sfsub : T_MInstFloat < "sfsub", 0b000, 0b001>;
184 def: Pat<(f32 (fadd F32:$src1, F32:$src2)),
185 (F2_sfadd F32:$src1, F32:$src2)>;
187 def: Pat<(f32 (fsub F32:$src1, F32:$src2)),
188 (F2_sfsub F32:$src1, F32:$src2)>;
190 def: Pat<(f32 (fmul F32:$src1, F32:$src2)),
191 (F2_sfmpy F32:$src1, F32:$src2)>;
193 let Itinerary = M_tc_3x_SLOT23, isCodeGenOnly = 0 in {
194 def F2_sfmax : T_MInstFloat < "sfmax", 0b100, 0b000>;
195 def F2_sfmin : T_MInstFloat < "sfmin", 0b100, 0b001>;
198 let isCodeGenOnly = 0 in {
199 def F2_sffixupn : T_MInstFloat < "sffixupn", 0b110, 0b000>;
200 def F2_sffixupd : T_MInstFloat < "sffixupd", 0b110, 0b001>;
203 // F2_sfrecipa: Reciprocal approximation for division.
204 let isPredicateLate = 1, isFP = 1,
205 hasSideEffects = 0, hasNewValue = 1, isCodeGenOnly = 0 in
206 def F2_sfrecipa: MInst <
207 (outs IntRegs:$Rd, PredRegs:$Pe),
208 (ins IntRegs:$Rs, IntRegs:$Rt),
209 "$Rd, $Pe = sfrecipa($Rs, $Rt)">,
217 let Inst{27-21} = 0b1011111;
218 let Inst{20-16} = Rs;
226 // F2_dfcmpeq: Floating point compare for equal.
227 let isCompare = 1, isFP = 1 in
228 class T_fcmp <string mnemonic, RegisterClass RC, bits<3> MinOp,
229 list<dag> pattern = [] >
230 : ALU64Inst <(outs PredRegs:$dst), (ins RC:$src1, RC:$src2),
231 "$dst = "#mnemonic#"($src1, $src2)", pattern,
232 "" , ALU64_tc_2early_SLOT23 > ,
240 let Inst{27-21} = 0b0010111;
241 let Inst{20-16} = src1;
242 let Inst{12-8} = src2;
243 let Inst{7-5} = MinOp;
247 class T_fcmp64 <string mnemonic, PatFrag OpNode, bits<3> MinOp>
248 : T_fcmp <mnemonic, DoubleRegs, MinOp,
249 [(set I1:$dst, (OpNode F64:$src1, F64:$src2))]> {
251 let Inst{27-21} = 0b0010111;
254 class T_fcmp32 <string mnemonic, PatFrag OpNode, bits<3> MinOp>
255 : T_fcmp <mnemonic, IntRegs, MinOp,
256 [(set I1:$dst, (OpNode F32:$src1, F32:$src2))]> {
258 let Inst{27-21} = 0b0111111;
261 let isCodeGenOnly = 0 in {
262 def F2_dfcmpeq : T_fcmp64<"dfcmp.eq", setoeq, 0b000>;
263 def F2_dfcmpgt : T_fcmp64<"dfcmp.gt", setogt, 0b001>;
264 def F2_dfcmpge : T_fcmp64<"dfcmp.ge", setoge, 0b010>;
265 def F2_dfcmpuo : T_fcmp64<"dfcmp.uo", setuo, 0b011>;
267 def F2_sfcmpge : T_fcmp32<"sfcmp.ge", setoge, 0b000>;
268 def F2_sfcmpuo : T_fcmp32<"sfcmp.uo", setuo, 0b001>;
269 def F2_sfcmpeq : T_fcmp32<"sfcmp.eq", setoeq, 0b011>;
270 def F2_sfcmpgt : T_fcmp32<"sfcmp.gt", setogt, 0b100>;
273 //===----------------------------------------------------------------------===//
274 // Multiclass to define 'Def Pats' for ordered gt, ge, eq operations.
275 //===----------------------------------------------------------------------===//
277 let Predicates = [HasV5T] in
278 multiclass T_fcmp_pats<PatFrag cmpOp, InstHexagon IntMI, InstHexagon DoubleMI> {
280 def: Pat<(i1 (cmpOp F32:$src1, F32:$src2)),
281 (IntMI F32:$src1, F32:$src2)>;
283 def: Pat<(i1 (cmpOp F64:$src1, F64:$src2)),
284 (DoubleMI F64:$src1, F64:$src2)>;
287 defm : T_fcmp_pats <seteq, F2_sfcmpeq, F2_dfcmpeq>;
288 defm : T_fcmp_pats <setgt, F2_sfcmpgt, F2_dfcmpgt>;
289 defm : T_fcmp_pats <setge, F2_sfcmpge, F2_dfcmpge>;
291 //===----------------------------------------------------------------------===//
292 // Multiclass to define 'Def Pats' for unordered gt, ge, eq operations.
293 //===----------------------------------------------------------------------===//
294 let Predicates = [HasV5T] in
295 multiclass unord_Pats <PatFrag cmpOp, InstHexagon IntMI, InstHexagon DoubleMI> {
297 def: Pat<(i1 (cmpOp F32:$src1, F32:$src2)),
298 (C2_or (F2_sfcmpuo F32:$src1, F32:$src2),
299 (IntMI F32:$src1, F32:$src2))>;
302 def: Pat<(i1 (cmpOp F64:$src1, F64:$src2)),
303 (C2_or (F2_dfcmpuo F64:$src1, F64:$src2),
304 (DoubleMI F64:$src1, F64:$src2))>;
307 defm : unord_Pats <setuge, F2_sfcmpge, F2_dfcmpge>;
308 defm : unord_Pats <setugt, F2_sfcmpgt, F2_dfcmpgt>;
309 defm : unord_Pats <setueq, F2_sfcmpeq, F2_dfcmpeq>;
311 //===----------------------------------------------------------------------===//
312 // Multiclass to define 'Def Pats' for the following dags:
313 // seteq(setoeq(op1, op2), 0) -> not(setoeq(op1, op2))
314 // seteq(setoeq(op1, op2), 1) -> setoeq(op1, op2)
315 // setne(setoeq(op1, op2), 0) -> setoeq(op1, op2)
316 // setne(setoeq(op1, op2), 1) -> not(setoeq(op1, op2))
317 //===----------------------------------------------------------------------===//
318 let Predicates = [HasV5T] in
319 multiclass eq_ordgePats <PatFrag cmpOp, InstHexagon IntMI,
320 InstHexagon DoubleMI> {
322 def: Pat<(i1 (seteq (i1 (cmpOp F32:$src1, F32:$src2)), 0)),
323 (C2_not (IntMI F32:$src1, F32:$src2))>;
324 def: Pat<(i1 (seteq (i1 (cmpOp F32:$src1, F32:$src2)), 1)),
325 (IntMI F32:$src1, F32:$src2)>;
326 def: Pat<(i1 (setne (i1 (cmpOp F32:$src1, F32:$src2)), 0)),
327 (IntMI F32:$src1, F32:$src2)>;
328 def: Pat<(i1 (setne (i1 (cmpOp F32:$src1, F32:$src2)), 1)),
329 (C2_not (IntMI F32:$src1, F32:$src2))>;
332 def : Pat<(i1 (seteq (i1 (cmpOp F64:$src1, F64:$src2)), 0)),
333 (C2_not (DoubleMI F64:$src1, F64:$src2))>;
334 def : Pat<(i1 (seteq (i1 (cmpOp F64:$src1, F64:$src2)), 1)),
335 (DoubleMI F64:$src1, F64:$src2)>;
336 def : Pat<(i1 (setne (i1 (cmpOp F64:$src1, F64:$src2)), 0)),
337 (DoubleMI F64:$src1, F64:$src2)>;
338 def : Pat<(i1 (setne (i1 (cmpOp F64:$src1, F64:$src2)), 1)),
339 (C2_not (DoubleMI F64:$src1, F64:$src2))>;
342 defm : eq_ordgePats<setoeq, F2_sfcmpeq, F2_dfcmpeq>;
343 defm : eq_ordgePats<setoge, F2_sfcmpge, F2_dfcmpge>;
344 defm : eq_ordgePats<setogt, F2_sfcmpgt, F2_dfcmpgt>;
346 //===----------------------------------------------------------------------===//
347 // Multiclass to define 'Def Pats' for the following dags:
348 // seteq(setolt(op1, op2), 0) -> not(setogt(op2, op1))
349 // seteq(setolt(op1, op2), 1) -> setogt(op2, op1)
350 // setne(setolt(op1, op2), 0) -> setogt(op2, op1)
351 // setne(setolt(op1, op2), 1) -> not(setogt(op2, op1))
352 //===----------------------------------------------------------------------===//
353 let Predicates = [HasV5T] in
354 multiclass eq_ordltPats <PatFrag cmpOp, InstHexagon IntMI,
355 InstHexagon DoubleMI> {
357 def: Pat<(i1 (seteq (i1 (cmpOp F32:$src1, F32:$src2)), 0)),
358 (C2_not (IntMI F32:$src2, F32:$src1))>;
359 def: Pat<(i1 (seteq (i1 (cmpOp F32:$src1, F32:$src2)), 1)),
360 (IntMI F32:$src2, F32:$src1)>;
361 def: Pat<(i1 (setne (i1 (cmpOp F32:$src1, F32:$src2)), 0)),
362 (IntMI F32:$src2, F32:$src1)>;
363 def: Pat<(i1 (setne (i1 (cmpOp F32:$src1, F32:$src2)), 1)),
364 (C2_not (IntMI F32:$src2, F32:$src1))>;
367 def: Pat<(i1 (seteq (i1 (cmpOp F64:$src1, F64:$src2)), 0)),
368 (C2_not (DoubleMI F64:$src2, F64:$src1))>;
369 def: Pat<(i1 (seteq (i1 (cmpOp F64:$src1, F64:$src2)), 1)),
370 (DoubleMI F64:$src2, F64:$src1)>;
371 def: Pat<(i1 (setne (i1 (cmpOp F64:$src1, F64:$src2)), 0)),
372 (DoubleMI F64:$src2, F64:$src1)>;
373 def: Pat<(i1 (setne (i1 (cmpOp F64:$src1, F64:$src2)), 0)),
374 (C2_not (DoubleMI F64:$src2, F64:$src1))>;
377 defm : eq_ordltPats<setole, F2_sfcmpge, F2_dfcmpge>;
378 defm : eq_ordltPats<setolt, F2_sfcmpgt, F2_dfcmpgt>;
381 // o. seto inverse of setuo. http://llvm.org/docs/LangRef.html#i_fcmp
382 let Predicates = [HasV5T] in {
383 def: Pat<(i1 (seto F32:$src1, F32:$src2)),
384 (C2_not (F2_sfcmpuo F32:$src2, F32:$src1))>;
385 def: Pat<(i1 (seto F32:$src1, fpimm:$src2)),
386 (C2_not (F2_sfcmpuo (TFRI_f fpimm:$src2), F32:$src1))>;
387 def: Pat<(i1 (seto F64:$src1, F64:$src2)),
388 (C2_not (F2_dfcmpuo F64:$src2, F64:$src1))>;
389 def: Pat<(i1 (seto F64:$src1, fpimm:$src2)),
390 (C2_not (F2_dfcmpuo (CONST64_Float_Real fpimm:$src2), F64:$src1))>;
394 let Predicates = [HasV5T] in {
395 def: Pat<(i1 (setolt F32:$src1, F32:$src2)),
396 (F2_sfcmpgt F32:$src2, F32:$src1)>;
397 def: Pat<(i1 (setolt F32:$src1, fpimm:$src2)),
398 (F2_sfcmpgt (f32 (TFRI_f fpimm:$src2)), F32:$src1)>;
399 def: Pat<(i1 (setolt F64:$src1, F64:$src2)),
400 (F2_dfcmpgt F64:$src2, F64:$src1)>;
401 def: Pat<(i1 (setolt F64:$src1, fpimm:$src2)),
402 (F2_dfcmpgt (CONST64_Float_Real fpimm:$src2), F64:$src1)>;
406 let Predicates = [HasV5T] in {
407 def: Pat<(i1 (setult F32:$src1, F32:$src2)),
408 (C2_or (F2_sfcmpuo F32:$src1, F32:$src2),
409 (F2_sfcmpgt F32:$src2, F32:$src1))>;
410 def: Pat<(i1 (setult F32:$src1, fpimm:$src2)),
411 (C2_or (F2_sfcmpuo F32:$src1, (TFRI_f fpimm:$src2)),
412 (F2_sfcmpgt (TFRI_f fpimm:$src2), F32:$src1))>;
413 def: Pat<(i1 (setult F64:$src1, F64:$src2)),
414 (C2_or (F2_dfcmpuo F64:$src1, F64:$src2),
415 (F2_dfcmpgt F64:$src2, F64:$src1))>;
416 def: Pat<(i1 (setult F64:$src1, fpimm:$src2)),
417 (C2_or (F2_dfcmpuo F64:$src1, (CONST64_Float_Real fpimm:$src2)),
418 (F2_dfcmpgt (CONST64_Float_Real fpimm:$src2), F64:$src1))>;
422 let Predicates = [HasV5T] in {
423 // rs <= rt -> rt >= rs.
424 def: Pat<(i1 (setole F32:$src1, F32:$src2)),
425 (F2_sfcmpge F32:$src2, F32:$src1)>;
426 def: Pat<(i1 (setole F32:$src1, fpimm:$src2)),
427 (F2_sfcmpge (TFRI_f fpimm:$src2), F32:$src1)>;
429 // Rss <= Rtt -> Rtt >= Rss.
430 def: Pat<(i1 (setole F64:$src1, F64:$src2)),
431 (F2_dfcmpge F64:$src2, F64:$src1)>;
432 def: Pat<(i1 (setole F64:$src1, fpimm:$src2)),
433 (F2_dfcmpge (CONST64_Float_Real fpimm:$src2), F64:$src1)>;
437 let Predicates = [HasV5T] in {
438 // rs <= rt -> rt >= rs.
439 def: Pat<(i1 (setule F32:$src1, F32:$src2)),
440 (C2_or (F2_sfcmpuo F32:$src1, F32:$src2),
441 (F2_sfcmpge F32:$src2, F32:$src1))>;
442 def: Pat<(i1 (setule F32:$src1, fpimm:$src2)),
443 (C2_or (F2_sfcmpuo F32:$src1, (TFRI_f fpimm:$src2)),
444 (F2_sfcmpge (TFRI_f fpimm:$src2), F32:$src1))>;
445 def: Pat<(i1 (setule F64:$src1, F64:$src2)),
446 (C2_or (F2_dfcmpuo F64:$src1, F64:$src2),
447 (F2_dfcmpge F64:$src2, F64:$src1))>;
448 def: Pat<(i1 (setule F64:$src1, fpimm:$src2)),
449 (C2_or (F2_dfcmpuo F64:$src1, (CONST64_Float_Real fpimm:$src2)),
450 (F2_dfcmpge (CONST64_Float_Real fpimm:$src2), F64:$src1))>;
454 let Predicates = [HasV5T] in {
455 def: Pat<(i1 (setone F32:$src1, F32:$src2)),
456 (C2_not (F2_sfcmpeq F32:$src1, F32:$src2))>;
457 def: Pat<(i1 (setone F64:$src1, F64:$src2)),
458 (C2_not (F2_dfcmpeq F64:$src1, F64:$src2))>;
459 def: Pat<(i1 (setone F32:$src1, fpimm:$src2)),
460 (C2_not (F2_sfcmpeq F32:$src1, (TFRI_f fpimm:$src2)))>;
461 def: Pat<(i1 (setone F64:$src1, fpimm:$src2)),
462 (C2_not (F2_dfcmpeq F64:$src1, (CONST64_Float_Real fpimm:$src2)))>;
466 let Predicates = [HasV5T] in {
467 def: Pat<(i1 (setune F32:$src1, F32:$src2)),
468 (C2_or (F2_sfcmpuo F32:$src1, F32:$src2),
469 (C2_not (F2_sfcmpeq F32:$src1, F32:$src2)))>;
470 def: Pat<(i1 (setune F64:$src1, F64:$src2)),
471 (C2_or (F2_dfcmpuo F64:$src1, F64:$src2),
472 (C2_not (F2_dfcmpeq F64:$src1, F64:$src2)))>;
473 def: Pat<(i1 (setune F32:$src1, fpimm:$src2)),
474 (C2_or (F2_sfcmpuo F32:$src1, (TFRI_f fpimm:$src2)),
475 (C2_not (F2_sfcmpeq F32:$src1, (TFRI_f fpimm:$src2))))>;
476 def: Pat<(i1 (setune F64:$src1, fpimm:$src2)),
477 (C2_or (F2_dfcmpuo F64:$src1, (CONST64_Float_Real fpimm:$src2)),
478 (C2_not (F2_dfcmpeq F64:$src1,
479 (CONST64_Float_Real fpimm:$src2))))>;
482 // Besides set[o|u][comparions], we also need set[comparisons].
483 let Predicates = [HasV5T] in {
485 def: Pat<(i1 (setlt F32:$src1, F32:$src2)),
486 (F2_sfcmpgt F32:$src2, F32:$src1)>;
487 def: Pat<(i1 (setlt F32:$src1, fpimm:$src2)),
488 (F2_sfcmpgt (TFRI_f fpimm:$src2), F32:$src1)>;
489 def: Pat<(i1 (setlt F64:$src1, F64:$src2)),
490 (F2_dfcmpgt F64:$src2, F64:$src1)>;
491 def: Pat<(i1 (setlt F64:$src1, fpimm:$src2)),
492 (F2_dfcmpgt (CONST64_Float_Real fpimm:$src2), F64:$src1)>;
495 // rs <= rt -> rt >= rs.
496 def: Pat<(i1 (setle F32:$src1, F32:$src2)),
497 (F2_sfcmpge F32:$src2, F32:$src1)>;
498 def: Pat<(i1 (setle F32:$src1, fpimm:$src2)),
499 (F2_sfcmpge (TFRI_f fpimm:$src2), F32:$src1)>;
501 // Rss <= Rtt -> Rtt >= Rss.
502 def: Pat<(i1 (setle F64:$src1, F64:$src2)),
503 (F2_dfcmpge F64:$src2, F64:$src1)>;
504 def: Pat<(i1 (setle F64:$src1, fpimm:$src2)),
505 (F2_dfcmpge (CONST64_Float_Real fpimm:$src2), F64:$src1)>;
508 def: Pat<(i1 (setne F32:$src1, F32:$src2)),
509 (C2_not (F2_sfcmpeq F32:$src1, F32:$src2))>;
510 def: Pat<(i1 (setne F64:$src1, F64:$src2)),
511 (C2_not (F2_dfcmpeq F64:$src1, F64:$src2))>;
512 def: Pat<(i1 (setne F32:$src1, fpimm:$src2)),
513 (C2_not (F2_sfcmpeq F32:$src1, (TFRI_f fpimm:$src2)))>;
514 def: Pat<(i1 (setne F64:$src1, fpimm:$src2)),
515 (C2_not (F2_dfcmpeq F64:$src1, (CONST64_Float_Real fpimm:$src2)))>;
518 // F2 convert template classes:
520 class F2_RDD_RSS_CONVERT<string mnemonic, bits<3> MinOp,
521 SDNode Op, PatLeaf RCOut, PatLeaf RCIn,
523 : SInst <(outs DoubleRegs:$Rdd), (ins DoubleRegs:$Rss),
524 "$Rdd = "#mnemonic#"($Rss)"#chop,
525 [(set RCOut:$Rdd, (Op RCIn:$Rss))], "",
526 S_2op_tc_3or4x_SLOT23> {
532 let Inst{27-21} = 0b0000111;
533 let Inst{20-16} = Rss;
534 let Inst{7-5} = MinOp;
539 class F2_RDD_RS_CONVERT<string mnemonic, bits<3> MinOp,
540 SDNode Op, PatLeaf RCOut, PatLeaf RCIn,
542 : SInst <(outs DoubleRegs:$Rdd), (ins IntRegs:$Rs),
543 "$Rdd = "#mnemonic#"($Rs)"#chop,
544 [(set RCOut:$Rdd, (Op RCIn:$Rs))], "",
545 S_2op_tc_3or4x_SLOT23> {
551 let Inst{27-21} = 0b0100100;
552 let Inst{20-16} = Rs;
553 let Inst{7-5} = MinOp;
557 let isFP = 1, hasNewValue = 1 in
558 class F2_RD_RSS_CONVERT<string mnemonic, bits<3> MinOp,
559 SDNode Op, PatLeaf RCOut, PatLeaf RCIn,
561 : SInst <(outs IntRegs:$Rd), (ins DoubleRegs:$Rss),
562 "$Rd = "#mnemonic#"($Rss)"#chop,
563 [(set RCOut:$Rd, (Op RCIn:$Rss))], "",
564 S_2op_tc_3or4x_SLOT23> {
570 let Inst{27-24} = 0b1000;
571 let Inst{23-21} = MinOp;
572 let Inst{20-16} = Rss;
573 let Inst{7-5} = 0b001;
577 let isFP = 1, hasNewValue = 1 in
578 class F2_RD_RS_CONVERT<string mnemonic, bits<3> MajOp, bits<3> MinOp,
579 SDNode Op, PatLeaf RCOut, PatLeaf RCIn,
581 : SInst <(outs IntRegs:$Rd), (ins IntRegs:$Rs),
582 "$Rd = "#mnemonic#"($Rs)"#chop,
583 [(set RCOut:$Rd, (Op RCIn:$Rs))], "",
584 S_2op_tc_3or4x_SLOT23> {
590 let Inst{27-24} = 0b1011;
591 let Inst{23-21} = MajOp;
592 let Inst{20-16} = Rs;
593 let Inst{7-5} = MinOp;
597 // Convert single precision to double precision and vice-versa.
598 let isCodeGenOnly = 0 in {
599 def F2_conv_sf2df : F2_RDD_RS_CONVERT <"convert_sf2df", 0b000,
602 def F2_conv_df2sf : F2_RD_RSS_CONVERT <"convert_df2sf", 0b000,
605 // Convert Integer to Floating Point.
606 def F2_conv_d2sf : F2_RD_RSS_CONVERT <"convert_d2sf", 0b010,
607 sint_to_fp, F32, I64>;
608 def F2_conv_ud2sf : F2_RD_RSS_CONVERT <"convert_ud2sf", 0b001,
609 uint_to_fp, F32, I64>;
610 def F2_conv_uw2sf : F2_RD_RS_CONVERT <"convert_uw2sf", 0b001, 0b000,
611 uint_to_fp, F32, I32>;
612 def F2_conv_w2sf : F2_RD_RS_CONVERT <"convert_w2sf", 0b010, 0b000,
613 sint_to_fp, F32, I32>;
614 def F2_conv_d2df : F2_RDD_RSS_CONVERT <"convert_d2df", 0b011,
615 sint_to_fp, F64, I64>;
616 def F2_conv_ud2df : F2_RDD_RSS_CONVERT <"convert_ud2df", 0b010,
617 uint_to_fp, F64, I64>;
618 def F2_conv_uw2df : F2_RDD_RS_CONVERT <"convert_uw2df", 0b001,
619 uint_to_fp, F64, I32>;
620 def F2_conv_w2df : F2_RDD_RS_CONVERT <"convert_w2df", 0b010,
621 sint_to_fp, F64, I32>;
623 // Convert Floating Point to Integer - default.
624 def F2_conv_df2uw_chop : F2_RD_RSS_CONVERT <"convert_df2uw", 0b101,
625 fp_to_uint, I32, F64, ":chop">;
626 def F2_conv_df2w_chop : F2_RD_RSS_CONVERT <"convert_df2w", 0b111,
627 fp_to_sint, I32, F64, ":chop">;
628 def F2_conv_sf2uw_chop : F2_RD_RS_CONVERT <"convert_sf2uw", 0b011, 0b001,
629 fp_to_uint, I32, F32, ":chop">;
630 def F2_conv_sf2w_chop : F2_RD_RS_CONVERT <"convert_sf2w", 0b100, 0b001,
631 fp_to_sint, I32, F32, ":chop">;
632 def F2_conv_df2d_chop : F2_RDD_RSS_CONVERT <"convert_df2d", 0b110,
633 fp_to_sint, I64, F64, ":chop">;
634 def F2_conv_df2ud_chop : F2_RDD_RSS_CONVERT <"convert_df2ud", 0b111,
635 fp_to_uint, I64, F64, ":chop">;
636 def F2_conv_sf2d_chop : F2_RDD_RS_CONVERT <"convert_sf2d", 0b110,
637 fp_to_sint, I64, F32, ":chop">;
638 def F2_conv_sf2ud_chop : F2_RDD_RS_CONVERT <"convert_sf2ud", 0b101,
639 fp_to_uint, I64, F32, ":chop">;
641 // Convert Floating Point to Integer: non-chopped.
642 let AddedComplexity = 20, Predicates = [HasV5T, IEEERndNearV5T] in {
643 def F2_conv_df2d : F2_RDD_RSS_CONVERT <"convert_df2d", 0b000,
644 fp_to_sint, I64, F64>;
645 def F2_conv_df2ud : F2_RDD_RSS_CONVERT <"convert_df2ud", 0b001,
646 fp_to_uint, I64, F64>;
647 def F2_conv_sf2ud : F2_RDD_RS_CONVERT <"convert_sf2ud", 0b011,
648 fp_to_uint, I64, F32>;
649 def F2_conv_sf2d : F2_RDD_RS_CONVERT <"convert_sf2d", 0b100,
650 fp_to_sint, I64, F32>;
651 def F2_conv_df2uw : F2_RD_RSS_CONVERT <"convert_df2uw", 0b011,
652 fp_to_uint, I32, F64>;
653 def F2_conv_df2w : F2_RD_RSS_CONVERT <"convert_df2w", 0b100,
654 fp_to_sint, I32, F64>;
655 def F2_conv_sf2uw : F2_RD_RS_CONVERT <"convert_sf2uw", 0b011, 0b000,
656 fp_to_uint, I32, F32>;
657 def F2_conv_sf2w : F2_RD_RS_CONVERT <"convert_sf2w", 0b100, 0b000,
658 fp_to_sint, I32, F32>;
663 let isFP = 1, hasNewValue = 1, isCodeGenOnly = 0 in
664 def F2_sffixupr: SInst<(outs IntRegs:$Rd), (ins IntRegs:$Rs),
665 "$Rd = sffixupr($Rs)",
666 [], "" , S_2op_tc_3or4x_SLOT23>, Requires<[HasV5T]> {
672 let Inst{27-21} = 0b1011101;
673 let Inst{20-16} = Rs;
674 let Inst{7-5} = 0b000;
678 // Bitcast is different than [fp|sint|uint]_to_[sint|uint|fp].
679 let Predicates = [HasV5T] in {
680 def: Pat <(i32 (bitconvert F32:$src)), (I32:$src)>;
681 def: Pat <(f32 (bitconvert I32:$src)), (F32:$src)>;
682 def: Pat <(i64 (bitconvert F64:$src)), (I64:$src)>;
683 def: Pat <(f64 (bitconvert I64:$src)), (F64:$src)>;
686 // F2_sffma: Floating-point fused multiply add.
687 let isFP = 1, hasNewValue = 1 in
688 class T_sfmpy_acc <bit isSub, bit isLib>
689 : MInst<(outs IntRegs:$Rx),
690 (ins IntRegs:$dst2, IntRegs:$Rs, IntRegs:$Rt),
691 "$Rx "#!if(isSub, "-=","+=")#" sfmpy($Rs, $Rt)"#!if(isLib, ":lib",""),
692 [], "$dst2 = $Rx" , M_tc_3_SLOT23 > ,
700 let Inst{27-21} = 0b1111000;
701 let Inst{20-16} = Rs;
710 let isCodeGenOnly = 0 in {
711 def F2_sffma: T_sfmpy_acc <0, 0>;
712 def F2_sffms: T_sfmpy_acc <1, 0>;
713 def F2_sffma_lib: T_sfmpy_acc <0, 1>;
714 def F2_sffms_lib: T_sfmpy_acc <1, 1>;
717 // Floating-point fused multiply add w/ additional scaling (2**pu).
718 let isFP = 1, hasNewValue = 1, isCodeGenOnly = 0 in
719 def F2_sffma_sc: MInst <
721 (ins IntRegs:$dst2, IntRegs:$Rs, IntRegs:$Rt, PredRegs:$Pu),
722 "$Rx += sfmpy($Rs, $Rt, $Pu):scale" ,
723 [], "$dst2 = $Rx" , M_tc_3_SLOT23 > ,
732 let Inst{27-21} = 0b1111011;
733 let Inst{20-16} = Rs;
741 let isExtended = 1, isExtentSigned = 1, opExtentBits = 8, opExtendable = 3,
742 isPseudo = 1, InputType = "imm" in
743 def MUX_ir_f : ALU32_rr<(outs IntRegs:$dst),
744 (ins PredRegs:$src1, IntRegs:$src2, f32Ext:$src3),
745 "$dst = mux($src1, $src2, #$src3)",
746 [(set F32:$dst, (f32 (select I1:$src1, F32:$src2, fpimm:$src3)))]>,
749 let isExtended = 1, isExtentSigned = 1, opExtentBits = 8, opExtendable = 2,
750 isPseudo = 1, InputType = "imm" in
751 def MUX_ri_f : ALU32_rr<(outs IntRegs:$dst),
752 (ins PredRegs:$src1, f32Ext:$src2, IntRegs:$src3),
753 "$dst = mux($src1, #$src2, $src3)",
754 [(set F32:$dst, (f32 (select I1:$src1, fpimm:$src2, F32:$src3)))]>,
757 //===----------------------------------------------------------------------===//
758 // :natural forms of vasrh and vasrhub insns
759 //===----------------------------------------------------------------------===//
760 // S5_asrhub_rnd_sat: Vector arithmetic shift right by immediate with round,
761 // saturate, and pack.
762 let Defs = [USR_OVF], hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in
763 class T_ASRHUB<bit isSat>
764 : SInst <(outs IntRegs:$Rd),
765 (ins DoubleRegs:$Rss, u4Imm:$u4),
766 "$Rd = vasrhub($Rss, #$u4):"#!if(isSat, "sat", "raw"),
767 [], "", S_2op_tc_2_SLOT23>,
775 let Inst{27-21} = 0b1000011;
776 let Inst{20-16} = Rss;
777 let Inst{13-12} = 0b00;
779 let Inst{7-6} = 0b10;
783 let isCodeGenOnly = 0 in {
784 def S5_asrhub_rnd_sat : T_ASRHUB <0>;
785 def S5_asrhub_sat : T_ASRHUB <1>;
788 let isCodeGenOnly = 1 in
789 def S5_asrhub_rnd_sat_goodsyntax
790 : SInst <(outs IntRegs:$Rd), (ins DoubleRegs:$Rss, u4Imm:$u4),
791 "$Rd = vasrhub($Rss, #$u4):rnd:sat">, Requires<[HasV5T]>;
793 // S5_vasrhrnd: Vector arithmetic shift right by immediate with round.
794 let hasSideEffects = 0, isCodeGenOnly = 0 in
795 def S5_vasrhrnd : SInst <(outs DoubleRegs:$Rdd),
796 (ins DoubleRegs:$Rss, u4Imm:$u4),
797 "$Rdd = vasrh($Rss, #$u4):raw">,
805 let Inst{27-21} = 0b0000001;
806 let Inst{20-16} = Rss;
807 let Inst{13-12} = 0b00;
809 let Inst{7-5} = 0b000;
813 let isCodeGenOnly = 1 in
814 def S5_vasrhrnd_goodsyntax
815 : SInst <(outs DoubleRegs:$Rdd), (ins DoubleRegs:$Rss, u4Imm:$u4),
816 "$Rdd = vasrh($Rss,#$u4):rnd">, Requires<[HasV5T]>;
818 // Floating point reciprocal square root approximation
819 let Uses = [USR], isPredicateLate = 1, isFP = 1,
820 hasSideEffects = 0, hasNewValue = 1, opNewValue = 0,
821 validSubTargets = HasV5SubT, isCodeGenOnly = 0 in
822 def F2_sfinvsqrta: SInst <
823 (outs IntRegs:$Rd, PredRegs:$Pe),
825 "$Rd, $Pe = sfinvsqrta($Rs)" > ,
833 let Inst{27-21} = 0b1011111;
834 let Inst{20-16} = Rs;
840 // Complex multiply 32x16
841 let Defs = [USR_OVF], Itinerary = S_3op_tc_3x_SLOT23, isCodeGenOnly = 0 in {
842 def M4_cmpyi_whc : T_S3op_8<"cmpyiwh", 0b101, 1, 1, 1, 1>;
843 def M4_cmpyr_whc : T_S3op_8<"cmpyrwh", 0b111, 1, 1, 1, 1>;
846 // Classify floating-point value
847 let isFP = 1, isCodeGenOnly = 0 in
848 def F2_sfclass : T_TEST_BIT_IMM<"sfclass", 0b111>;
850 let isFP = 1, isCodeGenOnly = 0 in
851 def F2_dfclass: ALU64Inst<(outs PredRegs:$Pd), (ins DoubleRegs:$Rss, u5Imm:$u5),
852 "$Pd = dfclass($Rss, #$u5)",
853 [], "" , ALU64_tc_2early_SLOT23 > , Requires<[HasV5T]> {
859 let Inst{27-21} = 0b1100100;
860 let Inst{20-16} = Rss;
861 let Inst{12-10} = 0b000;
863 let Inst{4-3} = 0b10;
867 // Instructions to create floating point constant
868 let hasNewValue = 1, opNewValue = 0 in
869 class T_fimm <string mnemonic, RegisterClass RC, bits<4> RegType, bit isNeg>
870 : ALU64Inst<(outs RC:$dst), (ins u10Imm:$src),
871 "$dst = "#mnemonic#"(#$src)"#!if(isNeg, ":neg", ":pos"),
872 [], "", ALU64_tc_3x_SLOT23>, Requires<[HasV5T]> {
877 let Inst{27-24} = RegType;
879 let Inst{22} = isNeg;
880 let Inst{21} = src{9};
881 let Inst{13-5} = src{8-0};
885 let isCodeGenOnly = 0 in {
886 def F2_sfimm_p : T_fimm <"sfmake", IntRegs, 0b0110, 0>;
887 def F2_sfimm_n : T_fimm <"sfmake", IntRegs, 0b0110, 1>;
888 def F2_dfimm_p : T_fimm <"dfmake", DoubleRegs, 0b1001, 0>;
889 def F2_dfimm_n : T_fimm <"dfmake", DoubleRegs, 0b1001, 1>;
892 def : Pat <(fabs (f32 IntRegs:$src1)),
893 (S2_clrbit_i (f32 IntRegs:$src1), 31)>,
896 def : Pat <(fneg (f32 IntRegs:$src1)),
897 (S2_togglebit_i (f32 IntRegs:$src1), 31)>,
901 def : Pat <(fabs (f64 DoubleRegs:$src1)),
902 (S2_clrbit_i (f32 (EXTRACT_SUBREG DoubleRegs:$src1, subreg_hireg)), 31)>,
905 def : Pat <(fabs (f64 DoubleRegs:$src1)),
906 (S2_clrbit_i (f32 (EXTRACT_SUBREG DoubleRegs:$src1, subreg_hireg)), 31)>,