lib/Target/Hexagon/HexagonInstrInfoV4.td

   1 //=- HexagonInstrInfoV4.td - Target Desc. for Hexagon Target -*- tablegen -*-=//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file describes the Hexagon V4 instructions in TableGen format.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 let neverHasSideEffects = 1 in
  15 class T_Immext<dag ins> :
  16   EXTENDERInst<(outs), ins, "immext(#$imm)", []>,
  17   Requires<[HasV4T]>;
  18
  19 def IMMEXT_b : T_Immext<(ins brtarget:$imm)>;
  20 def IMMEXT_c : T_Immext<(ins calltarget:$imm)>;
  21 def IMMEXT_g : T_Immext<(ins globaladdress:$imm)>;
  22 def IMMEXT_i : T_Immext<(ins u26_6Imm:$imm)>;
  23
  24 // Hexagon V4 Architecture spec defines 8 instruction classes:
  25 // LD ST ALU32 XTYPE J JR MEMOP NV CR SYSTEM(system is not implemented in the
  26 // compiler)
  27
  28 // LD Instructions:
  29 // ========================================
  30 // Loads (8/16/32/64 bit)
  31 // Deallocframe
  32
  33 // ST Instructions:
  34 // ========================================
  35 // Stores (8/16/32/64 bit)
  36 // Allocframe
  37
  38 // ALU32 Instructions:
  39 // ========================================
  40 // Arithmetic / Logical (32 bit)
  41 // Vector Halfword
  42
  43 // XTYPE Instructions (32/64 bit):
  44 // ========================================
  45 // Arithmetic, Logical, Bit Manipulation
  46 // Multiply (Integer, Fractional, Complex)
  47 // Permute / Vector Permute Operations
  48 // Predicate Operations
  49 // Shift / Shift with Add/Sub/Logical
  50 // Vector Byte ALU
  51 // Vector Halfword (ALU, Shift, Multiply)
  52 // Vector Word (ALU, Shift)
  53
  54 // J Instructions:
  55 // ========================================
  56 // Jump/Call PC-relative
  57
  58 // JR Instructions:
  59 // ========================================
  60 // Jump/Call Register
  61
  62 // MEMOP Instructions:
  63 // ========================================
  64 // Operation on memory (8/16/32 bit)
  65
  66 // NV Instructions:
  67 // ========================================
  68 // New-value Jumps
  69 // New-value Stores
  70
  71 // CR Instructions:
  72 // ========================================
  73 // Control-Register Transfers
  74 // Hardware Loop Setup
  75 // Predicate Logicals & Reductions
  76
  77 // SYSTEM Instructions (not implemented in the compiler):
  78 // ========================================
  79 // Prefetch
  80 // Cache Maintenance
  81 // Bus Operations
  82
  83
  84 //===----------------------------------------------------------------------===//
  85 // ALU32 +
  86 //===----------------------------------------------------------------------===//
  87
  88 // Shift halfword.
  89
  90 let isPredicated = 1, neverHasSideEffects = 1, validSubTargets = HasV4SubT in {
  91 def ASLH_cPt_V4 : ALU32_rr<(outs IntRegs:$dst),
  92             (ins PredRegs:$src1, IntRegs:$src2),
  93             "if ($src1) $dst = aslh($src2)",
  94             []>,
  95             Requires<[HasV4T]>;
  96
  97 def ASLH_cNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
  98             (ins PredRegs:$src1, IntRegs:$src2),
  99             "if (!$src1) $dst = aslh($src2)",
 100             []>,
 101             Requires<[HasV4T]>;
 102
 103 def ASLH_cdnPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 104             (ins PredRegs:$src1, IntRegs:$src2),
 105             "if ($src1.new) $dst = aslh($src2)",
 106             []>,
 107             Requires<[HasV4T]>;
 108
 109 def ASLH_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 110             (ins PredRegs:$src1, IntRegs:$src2),
 111             "if (!$src1.new) $dst = aslh($src2)",
 112             []>,
 113             Requires<[HasV4T]>;
 114
 115 def ASRH_cPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 116             (ins PredRegs:$src1, IntRegs:$src2),
 117             "if ($src1) $dst = asrh($src2)",
 118             []>,
 119             Requires<[HasV4T]>;
 120
 121 def ASRH_cNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 122             (ins PredRegs:$src1, IntRegs:$src2),
 123             "if (!$src1) $dst = asrh($src2)",
 124             []>,
 125             Requires<[HasV4T]>;
 126
 127 def ASRH_cdnPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 128             (ins PredRegs:$src1, IntRegs:$src2),
 129             "if ($src1.new) $dst = asrh($src2)",
 130             []>,
 131             Requires<[HasV4T]>;
 132
 133 def ASRH_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 134             (ins PredRegs:$src1, IntRegs:$src2),
 135             "if (!$src1.new) $dst = asrh($src2)",
 136             []>,
 137             Requires<[HasV4T]>;
 138 }
 139
 140 // Sign extend.
 141
 142 let isPredicated = 1, neverHasSideEffects = 1, validSubTargets = HasV4SubT in {
 143 def SXTB_cPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 144             (ins PredRegs:$src1, IntRegs:$src2),
 145             "if ($src1) $dst = sxtb($src2)",
 146             []>,
 147             Requires<[HasV4T]>;
 148
 149 def SXTB_cNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 150             (ins PredRegs:$src1, IntRegs:$src2),
 151             "if (!$src1) $dst = sxtb($src2)",
 152             []>,
 153             Requires<[HasV4T]>;
 154
 155 def SXTB_cdnPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 156             (ins PredRegs:$src1, IntRegs:$src2),
 157             "if ($src1.new) $dst = sxtb($src2)",
 158             []>,
 159             Requires<[HasV4T]>;
 160
 161 def SXTB_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 162             (ins PredRegs:$src1, IntRegs:$src2),
 163             "if (!$src1.new) $dst = sxtb($src2)",
 164             []>,
 165             Requires<[HasV4T]>;
 166
 167
 168 def SXTH_cPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 169             (ins PredRegs:$src1, IntRegs:$src2),
 170             "if ($src1) $dst = sxth($src2)",
 171             []>,
 172             Requires<[HasV4T]>;
 173
 174 def SXTH_cNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 175             (ins PredRegs:$src1, IntRegs:$src2),
 176             "if (!$src1) $dst = sxth($src2)",
 177             []>,
 178             Requires<[HasV4T]>;
 179
 180 def SXTH_cdnPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 181             (ins PredRegs:$src1, IntRegs:$src2),
 182             "if ($src1.new) $dst = sxth($src2)",
 183             []>,
 184             Requires<[HasV4T]>;
 185
 186 def SXTH_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 187             (ins PredRegs:$src1, IntRegs:$src2),
 188             "if (!$src1.new) $dst = sxth($src2)",
 189             []>,
 190             Requires<[HasV4T]>;
 191 }
 192
 193 // Zero exten.
 194
 195 let neverHasSideEffects = 1, isPredicated = 1, validSubTargets = HasV4SubT in {
 196 def ZXTB_cPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 197             (ins PredRegs:$src1, IntRegs:$src2),
 198             "if ($src1) $dst = zxtb($src2)",
 199             []>,
 200             Requires<[HasV4T]>;
 201
 202 def ZXTB_cNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 203             (ins PredRegs:$src1, IntRegs:$src2),
 204             "if (!$src1) $dst = zxtb($src2)",
 205             []>,
 206             Requires<[HasV4T]>;
 207
 208 def ZXTB_cdnPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 209             (ins PredRegs:$src1, IntRegs:$src2),
 210             "if ($src1.new) $dst = zxtb($src2)",
 211             []>,
 212             Requires<[HasV4T]>;
 213
 214 def ZXTB_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 215             (ins PredRegs:$src1, IntRegs:$src2),
 216             "if (!$src1.new) $dst = zxtb($src2)",
 217             []>,
 218             Requires<[HasV4T]>;
 219
 220 def ZXTH_cPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 221             (ins PredRegs:$src1, IntRegs:$src2),
 222             "if ($src1) $dst = zxth($src2)",
 223             []>,
 224             Requires<[HasV4T]>;
 225
 226 def ZXTH_cNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 227             (ins PredRegs:$src1, IntRegs:$src2),
 228             "if (!$src1) $dst = zxth($src2)",
 229             []>,
 230             Requires<[HasV4T]>;
 231
 232 def ZXTH_cdnPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 233             (ins PredRegs:$src1, IntRegs:$src2),
 234             "if ($src1.new) $dst = zxth($src2)",
 235             []>,
 236             Requires<[HasV4T]>;
 237
 238 def ZXTH_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 239             (ins PredRegs:$src1, IntRegs:$src2),
 240             "if (!$src1.new) $dst = zxth($src2)",
 241             []>,
 242             Requires<[HasV4T]>;
 243 }
 244
 245 // Generate frame index addresses.
 246 let neverHasSideEffects = 1, isReMaterializable = 1,
 247 isExtended = 1, opExtendable = 2, validSubTargets = HasV4SubT in
 248 def TFR_FI_immext_V4 : ALU32_ri<(outs IntRegs:$dst),
 249             (ins IntRegs:$src1, s32Imm:$offset),
 250             "$dst = add($src1, ##$offset)",
 251             []>,
 252             Requires<[HasV4T]>;
 253
 254
 255 //===----------------------------------------------------------------------===//
 256 // ALU32 -
 257 //===----------------------------------------------------------------------===//
 258
 259
 260 //===----------------------------------------------------------------------===//
 261 // ALU32/PERM +
 262 //===----------------------------------------------------------------------===//
 263
 264 // Combine
 265 // Rdd=combine(Rs, #s8)
 266 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 8,
 267     neverHasSideEffects = 1, validSubTargets = HasV4SubT in
 268 def COMBINE_rI_V4 : ALU32_ri<(outs DoubleRegs:$dst),
 269             (ins IntRegs:$src1, s8Ext:$src2),
 270             "$dst = combine($src1, #$src2)",
 271             []>,
 272             Requires<[HasV4T]>;
 273
 274 // Rdd=combine(#s8, Rs)
 275 let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 8,
 276     neverHasSideEffects = 1, validSubTargets = HasV4SubT in
 277 def COMBINE_Ir_V4 : ALU32_ir<(outs DoubleRegs:$dst),
 278             (ins s8Ext:$src1, IntRegs:$src2),
 279             "$dst = combine(#$src1, $src2)",
 280             []>,
 281             Requires<[HasV4T]>;
 282
 283 let isExtendable = 1, opExtendable = 2, isExtentSigned = 0, opExtentBits = 6,
 284     neverHasSideEffects = 1, validSubTargets = HasV4SubT in
 285 def COMBINE_iI_V4 : ALU32_ii<(outs DoubleRegs:$dst),
 286             (ins s8Imm:$src1, u6Ext:$src2),
 287             "$dst = combine(#$src1, #$src2)",
 288             []>,
 289             Requires<[HasV4T]>;
 290
 291 //===----------------------------------------------------------------------===//
 292 // ALU32/PERM +
 293 //===----------------------------------------------------------------------===//
 294
 295 //===----------------------------------------------------------------------===//
 296 // LD +
 297 //===----------------------------------------------------------------------===//
 298 //
 299 // These absolute set addressing mode instructions accept immediate as
 300 // an operand. We have duplicated these patterns to take global address.
 301
 302 let neverHasSideEffects = 1 in
 303 def LDrid_abs_setimm_V4 : LDInst2<(outs DoubleRegs:$dst1, IntRegs:$dst2),
 304             (ins u6Imm:$addr),
 305             "$dst1 = memd($dst2=#$addr)",
 306             []>,
 307             Requires<[HasV4T]>;
 308
 309 // Rd=memb(Re=#U6)
 310 let neverHasSideEffects = 1 in
 311 def LDrib_abs_setimm_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
 312             (ins u6Imm:$addr),
 313             "$dst1 = memb($dst2=#$addr)",
 314             []>,
 315             Requires<[HasV4T]>;
 316
 317 // Rd=memh(Re=#U6)
 318 let neverHasSideEffects = 1 in
 319 def LDrih_abs_setimm_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
 320             (ins u6Imm:$addr),
 321             "$dst1 = memh($dst2=#$addr)",
 322             []>,
 323             Requires<[HasV4T]>;
 324
 325 // Rd=memub(Re=#U6)
 326 let neverHasSideEffects = 1 in
 327 def LDriub_abs_setimm_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
 328             (ins u6Imm:$addr),
 329             "$dst1 = memub($dst2=#$addr)",
 330             []>,
 331             Requires<[HasV4T]>;
 332
 333 // Rd=memuh(Re=#U6)
 334 let neverHasSideEffects = 1 in
 335 def LDriuh_abs_setimm_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
 336             (ins u6Imm:$addr),
 337             "$dst1 = memuh($dst2=#$addr)",
 338             []>,
 339             Requires<[HasV4T]>;
 340
 341 // Rd=memw(Re=#U6)
 342 let neverHasSideEffects = 1 in
 343 def LDriw_abs_setimm_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
 344             (ins u6Imm:$addr),
 345             "$dst1 = memw($dst2=#$addr)",
 346             []>,
 347             Requires<[HasV4T]>;
 348
 349 // Following patterns are defined for absolute set addressing mode
 350 // instruction which take global address as operand.
 351 let neverHasSideEffects = 1 in
 352 def LDrid_abs_set_V4 : LDInst2<(outs DoubleRegs:$dst1, IntRegs:$dst2),
 353             (ins globaladdress:$addr),
 354             "$dst1 = memd($dst2=##$addr)",
 355             []>,
 356             Requires<[HasV4T]>;
 357
 358 // Rd=memb(Re=#U6)
 359 let neverHasSideEffects = 1 in
 360 def LDrib_abs_set_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
 361             (ins globaladdress:$addr),
 362             "$dst1 = memb($dst2=##$addr)",
 363             []>,
 364             Requires<[HasV4T]>;
 365
 366 // Rd=memh(Re=#U6)
 367 let neverHasSideEffects = 1 in
 368 def LDrih_abs_set_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
 369             (ins globaladdress:$addr),
 370             "$dst1 = memh($dst2=##$addr)",
 371             []>,
 372             Requires<[HasV4T]>;
 373
 374 // Rd=memub(Re=#U6)
 375 let neverHasSideEffects = 1 in
 376 def LDriub_abs_set_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
 377             (ins globaladdress:$addr),
 378             "$dst1 = memub($dst2=##$addr)",
 379             []>,
 380             Requires<[HasV4T]>;
 381
 382 // Rd=memuh(Re=#U6)
 383 let neverHasSideEffects = 1 in
 384 def LDriuh_abs_set_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
 385             (ins globaladdress:$addr),
 386             "$dst1 = memuh($dst2=##$addr)",
 387             []>,
 388             Requires<[HasV4T]>;
 389
 390 // Rd=memw(Re=#U6)
 391 let neverHasSideEffects = 1 in
 392 def LDriw_abs_set_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
 393             (ins globaladdress:$addr),
 394             "$dst1 = memw($dst2=##$addr)",
 395             []>,
 396             Requires<[HasV4T]>;
 397
 398 // Load doubleword.
 399 //
 400 // Make sure that in post increment load, the first operand is always the post
 401 // increment operand.
 402 //
 403 // Rdd=memd(Rs+Rt<<#u2)
 404 // Special case pattern for indexed load without offset which is easier to
 405 // match. AddedComplexity of this pattern should be lower than base+offset load
 406 // and lower yet than the more generic version with offset/shift below
 407 // Similar approach is taken for all other base+index loads.
 408 let AddedComplexity = 10, isPredicable = 1 in
 409 def LDrid_indexed_V4 : LDInst<(outs DoubleRegs:$dst),
 410                     (ins IntRegs:$src1, IntRegs:$src2),
 411                     "$dst=memd($src1+$src2<<#0)",
 412                     [(set (i64 DoubleRegs:$dst),
 413                           (i64 (load (add (i32 IntRegs:$src1),
 414                                           (i32 IntRegs:$src2)))))]>,
 415                     Requires<[HasV4T]>;
 416
 417 // multiclass for load instructions with base + register offset
 418 // addressing mode
 419 multiclass ld_idxd_shl_pbase<string mnemonic, RegisterClass RC, bit isNot,
 420                              bit isPredNew> {
 421   let PNewValue = #!if(isPredNew, "new", "") in
 422   def #NAME# : LDInst2<(outs RC:$dst),
 423             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$offset),
 424             !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
 425             ") ")#"$dst = "#mnemonic#"($src2+$src3<<#$offset)",
 426             []>, Requires<[HasV4T]>;
 427 }
 428
 429 multiclass ld_idxd_shl_pred<string mnemonic, RegisterClass RC, bit PredNot> {
 430   let PredSense = #!if(PredNot, "false", "true") in {
 431     defm _c#NAME# : ld_idxd_shl_pbase<mnemonic, RC, PredNot, 0>;
 432     // Predicate new
 433     defm _cdn#NAME# : ld_idxd_shl_pbase<mnemonic, RC, PredNot, 1>;
 434   }
 435 }
 436
 437 let neverHasSideEffects  = 1 in
 438 multiclass ld_idxd_shl<string mnemonic, string CextOp, RegisterClass RC> {
 439   let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed_shl in {
 440     let isPredicable = 1 in
 441     def #NAME#_V4 : LDInst2<(outs RC:$dst),
 442             (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$offset),
 443             "$dst = "#mnemonic#"($src1+$src2<<#$offset)",
 444             []>, Requires<[HasV4T]>;
 445
 446     let isPredicated = 1 in {
 447       defm Pt_V4 : ld_idxd_shl_pred<mnemonic, RC, 0 >;
 448       defm NotPt_V4 : ld_idxd_shl_pred<mnemonic, RC, 1>;
 449     }
 450   }
 451 }
 452
 453 let addrMode = BaseRegOffset in {
 454   defm LDrib_indexed_shl: ld_idxd_shl<"memb", "LDrib", IntRegs>, AddrModeRel;
 455   defm LDriub_indexed_shl: ld_idxd_shl<"memub", "LDriub", IntRegs>, AddrModeRel;
 456   defm LDrih_indexed_shl: ld_idxd_shl<"memh", "LDrih", IntRegs>, AddrModeRel;
 457   defm LDriuh_indexed_shl: ld_idxd_shl<"memuh", "LDriuh", IntRegs>, AddrModeRel;
 458   defm LDriw_indexed_shl: ld_idxd_shl<"memw", "LDriw", IntRegs>, AddrModeRel;
 459   defm LDrid_indexed_shl: ld_idxd_shl<"memd", "LDrid", DoubleRegs>, AddrModeRel;
 460 }
 461
 462 // 'def pats' for load instructions with base + register offset and non-zero
 463 // immediate value. Immediate value is used to left-shift the second
 464 // register operand.
 465 let AddedComplexity = 40 in {
 466 def : Pat <(i32 (sextloadi8 (add IntRegs:$src1,
 467                                  (shl IntRegs:$src2, u2ImmPred:$offset)))),
 468            (LDrib_indexed_shl_V4 IntRegs:$src1,
 469             IntRegs:$src2, u2ImmPred:$offset)>,
 470             Requires<[HasV4T]>;
 471
 472 def : Pat <(i32 (zextloadi8 (add IntRegs:$src1,
 473                                  (shl IntRegs:$src2, u2ImmPred:$offset)))),
 474            (LDriub_indexed_shl_V4 IntRegs:$src1,
 475             IntRegs:$src2, u2ImmPred:$offset)>,
 476             Requires<[HasV4T]>;
 477
 478 def : Pat <(i32 (extloadi8 (add IntRegs:$src1,
 479                                 (shl IntRegs:$src2, u2ImmPred:$offset)))),
 480            (LDriub_indexed_shl_V4 IntRegs:$src1,
 481             IntRegs:$src2, u2ImmPred:$offset)>,
 482             Requires<[HasV4T]>;
 483
 484 def : Pat <(i32 (sextloadi16 (add IntRegs:$src1,
 485                                   (shl IntRegs:$src2, u2ImmPred:$offset)))),
 486            (LDrih_indexed_shl_V4 IntRegs:$src1,
 487             IntRegs:$src2, u2ImmPred:$offset)>,
 488             Requires<[HasV4T]>;
 489
 490 def : Pat <(i32 (zextloadi16 (add IntRegs:$src1,
 491                                   (shl IntRegs:$src2, u2ImmPred:$offset)))),
 492            (LDriuh_indexed_shl_V4 IntRegs:$src1,
 493             IntRegs:$src2, u2ImmPred:$offset)>,
 494             Requires<[HasV4T]>;
 495
 496 def : Pat <(i32 (extloadi16 (add IntRegs:$src1,
 497                                  (shl IntRegs:$src2, u2ImmPred:$offset)))),
 498            (LDriuh_indexed_shl_V4 IntRegs:$src1,
 499             IntRegs:$src2, u2ImmPred:$offset)>,
 500             Requires<[HasV4T]>;
 501
 502 def : Pat <(i32 (load (add IntRegs:$src1,
 503                            (shl IntRegs:$src2, u2ImmPred:$offset)))),
 504            (LDriw_indexed_shl_V4 IntRegs:$src1,
 505             IntRegs:$src2, u2ImmPred:$offset)>,
 506             Requires<[HasV4T]>;
 507
 508 def : Pat <(i64 (load (add IntRegs:$src1,
 509                            (shl IntRegs:$src2, u2ImmPred:$offset)))),
 510            (LDrid_indexed_shl_V4 IntRegs:$src1,
 511             IntRegs:$src2, u2ImmPred:$offset)>,
 512             Requires<[HasV4T]>;
 513 }
 514
 515 //// Load doubleword conditionally.
 516 // if ([!]Pv[.new]) Rd=memd(Rs+Rt<<#u2)
 517 // if (Pv) Rd=memd(Rs+Rt<<#u2)
 518 let AddedComplexity = 15, isPredicated = 1 in
 519 def LDrid_indexed_cPt_V4 : LDInst2<(outs DoubleRegs:$dst),
 520                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 521                     "if ($src1) $dst=memd($src2+$src3<<#0)",
 522                     []>,
 523                     Requires<[HasV4T]>;
 524
 525 // if (Pv.new) Rd=memd(Rs+Rt<<#u2)
 526 let AddedComplexity = 15, isPredicated = 1 in
 527 def LDrid_indexed_cdnPt_V4 : LDInst2<(outs DoubleRegs:$dst),
 528                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 529                     "if ($src1.new) $dst=memd($src2+$src3<<#0)",
 530                     []>,
 531                     Requires<[HasV4T]>;
 532
 533 // if (!Pv) Rd=memd(Rs+Rt<<#u2)
 534 let AddedComplexity = 15, isPredicated = 1 in
 535 def LDrid_indexed_cNotPt_V4 : LDInst2<(outs DoubleRegs:$dst),
 536                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 537                     "if (!$src1) $dst=memd($src2+$src3<<#0)",
 538                     []>,
 539                     Requires<[HasV4T]>;
 540
 541 // if (!Pv.new) Rd=memd(Rs+Rt<<#u2)
 542 let AddedComplexity = 15, isPredicated = 1 in
 543 def LDrid_indexed_cdnNotPt_V4 : LDInst2<(outs DoubleRegs:$dst),
 544                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 545                     "if (!$src1.new) $dst=memd($src2+$src3<<#0)",
 546                     []>,
 547                     Requires<[HasV4T]>;
 548
 549 // Rdd=memd(Rt<<#u2+#U6)
 550
 551 //// Load byte.
 552 // Rd=memb(Rs+Rt<<#u2)
 553 let AddedComplexity = 10, isPredicable = 1 in
 554 def LDrib_indexed_V4 : LDInst<(outs IntRegs:$dst),
 555                     (ins IntRegs:$src1, IntRegs:$src2),
 556                     "$dst=memb($src1+$src2<<#0)",
 557                     [(set (i32 IntRegs:$dst),
 558                           (i32 (sextloadi8 (add (i32 IntRegs:$src1),
 559                                                 (i32 IntRegs:$src2)))))]>,
 560                     Requires<[HasV4T]>;
 561
 562 let AddedComplexity = 10, isPredicable = 1 in
 563 def LDriub_indexed_V4 : LDInst<(outs IntRegs:$dst),
 564                     (ins IntRegs:$src1, IntRegs:$src2),
 565                     "$dst=memub($src1+$src2<<#0)",
 566                     [(set (i32 IntRegs:$dst),
 567                           (i32 (zextloadi8 (add (i32 IntRegs:$src1),
 568                                                 (i32 IntRegs:$src2)))))]>,
 569                     Requires<[HasV4T]>;
 570
 571 let AddedComplexity = 10, isPredicable = 1 in
 572 def LDriub_ae_indexed_V4 : LDInst<(outs IntRegs:$dst),
 573                     (ins IntRegs:$src1, IntRegs:$src2),
 574                     "$dst=memub($src1+$src2<<#0)",
 575                     [(set (i32 IntRegs:$dst),
 576                           (i32 (extloadi8 (add (i32 IntRegs:$src1),
 577                                                (i32 IntRegs:$src2)))))]>,
 578                     Requires<[HasV4T]>;
 579
 580 let AddedComplexity = 40, isPredicable = 1 in
 581 def LDriub_ae_indexed_shl_V4 : LDInst<(outs IntRegs:$dst),
 582                     (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$offset),
 583                     "$dst=memub($src1+$src2<<#$offset)",
 584                     [(set (i32 IntRegs:$dst),
 585                           (i32 (extloadi8 (add (i32 IntRegs:$src1),
 586                                                (shl (i32 IntRegs:$src2),
 587                                                     u2ImmPred:$offset)))))]>,
 588                     Requires<[HasV4T]>;
 589
 590 //// Load byte conditionally.
 591 // if ([!]Pv[.new]) Rd=memb(Rs+Rt<<#u2)
 592 // if (Pv) Rd=memb(Rs+Rt<<#u2)
 593 let AddedComplexity = 15, isPredicated = 1 in
 594 def LDrib_indexed_cPt_V4 : LDInst2<(outs IntRegs:$dst),
 595                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 596                     "if ($src1) $dst=memb($src2+$src3<<#0)",
 597                     []>,
 598                     Requires<[HasV4T]>;
 599
 600 // if (Pv.new) Rd=memb(Rs+Rt<<#u2)
 601 let AddedComplexity = 15, isPredicated = 1 in
 602 def LDrib_indexed_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
 603                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 604                     "if ($src1.new) $dst=memb($src2+$src3<<#0)",
 605                     []>,
 606                     Requires<[HasV4T]>;
 607
 608 // if (!Pv) Rd=memb(Rs+Rt<<#u2)
 609 let AddedComplexity = 15, isPredicated = 1 in
 610 def LDrib_indexed_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 611                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 612                     "if (!$src1) $dst=memb($src2+$src3<<#0)",
 613                     []>,
 614                     Requires<[HasV4T]>;
 615
 616 // if (!Pv.new) Rd=memb(Rs+Rt<<#u2)
 617 let AddedComplexity = 15, isPredicated = 1 in
 618 def LDrib_indexed_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 619                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 620                     "if (!$src1.new) $dst=memb($src2+$src3<<#0)",
 621                     []>,
 622                     Requires<[HasV4T]>;
 623
 624 //// Load unsigned byte conditionally.
 625 // if ([!]Pv[.new]) Rd=memub(Rs+Rt<<#u2)
 626 // if (Pv) Rd=memub(Rs+Rt<<#u2)
 627 let AddedComplexity = 15, isPredicated = 1 in
 628 def LDriub_indexed_cPt_V4 : LDInst2<(outs IntRegs:$dst),
 629                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 630                     "if ($src1) $dst=memub($src2+$src3<<#0)",
 631                     []>,
 632                     Requires<[HasV4T]>;
 633
 634 // if (Pv.new) Rd=memub(Rs+Rt<<#u2)
 635 let AddedComplexity = 15, isPredicated = 1 in
 636 def LDriub_indexed_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
 637                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 638                     "if ($src1.new) $dst=memub($src2+$src3<<#0)",
 639                     []>,
 640                     Requires<[HasV4T]>;
 641
 642 // if (!Pv) Rd=memub(Rs+Rt<<#u2)
 643 let AddedComplexity = 15, isPredicated = 1 in
 644 def LDriub_indexed_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 645                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 646                     "if (!$src1) $dst=memub($src2+$src3<<#0)",
 647                     []>,
 648                     Requires<[HasV4T]>;
 649
 650 // if (!Pv.new) Rd=memub(Rs+Rt<<#u2)
 651 let AddedComplexity = 15, isPredicated = 1 in
 652 def LDriub_indexed_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 653                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 654                     "if (!$src1.new) $dst=memub($src2+$src3<<#0)",
 655                     []>,
 656                     Requires<[HasV4T]>;
 657
 658 // Rd=memb(Rt<<#u2+#U6)
 659
 660 //// Load halfword
 661 // Rd=memh(Rs+Rt<<#u2)
 662 let AddedComplexity = 10, isPredicable = 1 in
 663 def LDrih_indexed_V4 : LDInst<(outs IntRegs:$dst),
 664                     (ins IntRegs:$src1, IntRegs:$src2),
 665                     "$dst=memh($src1+$src2<<#0)",
 666                     [(set (i32 IntRegs:$dst),
 667                           (i32 (sextloadi16 (add (i32 IntRegs:$src1),
 668                                                  (i32 IntRegs:$src2)))))]>,
 669                     Requires<[HasV4T]>;
 670
 671 let AddedComplexity = 10, isPredicable = 1 in
 672 def LDriuh_indexed_V4 : LDInst<(outs IntRegs:$dst),
 673                     (ins IntRegs:$src1, IntRegs:$src2),
 674                     "$dst=memuh($src1+$src2<<#0)",
 675                     [(set (i32 IntRegs:$dst),
 676                           (i32 (zextloadi16 (add (i32 IntRegs:$src1),
 677                                                  (i32 IntRegs:$src2)))))]>,
 678                     Requires<[HasV4T]>;
 679
 680 let AddedComplexity = 10, isPredicable = 1 in
 681 def LDriuh_ae_indexed_V4 : LDInst<(outs IntRegs:$dst),
 682                     (ins IntRegs:$src1, IntRegs:$src2),
 683                     "$dst=memuh($src1+$src2<<#0)",
 684                     [(set (i32 IntRegs:$dst),
 685                           (i32 (extloadi16 (add (i32 IntRegs:$src1),
 686                                                 (i32 IntRegs:$src2)))))]>,
 687                     Requires<[HasV4T]>;
 688
 689 let AddedComplexity = 40, isPredicable = 1 in
 690 def LDriuh_ae_indexed_shl_V4 : LDInst<(outs IntRegs:$dst),
 691                     (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$offset),
 692                     "$dst=memuh($src1+$src2<<#$offset)",
 693                     [(set (i32 IntRegs:$dst),
 694                           (i32 (extloadi16 (add (i32 IntRegs:$src1),
 695                                                 (shl (i32 IntRegs:$src2),
 696                                                      u2ImmPred:$offset)))))]>,
 697                     Requires<[HasV4T]>;
 698
 699 //// Load halfword conditionally.
 700 // if ([!]Pv[.new]) Rd=memh(Rs+Rt<<#u2)
 701 // if (Pv) Rd=memh(Rs+Rt<<#u2)
 702 let AddedComplexity = 15, isPredicated = 1 in
 703 def LDrih_indexed_cPt_V4 : LDInst2<(outs IntRegs:$dst),
 704                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 705                     "if ($src1) $dst=memh($src2+$src3<<#0)",
 706                     []>,
 707                     Requires<[HasV4T]>;
 708
 709 // if (Pv.new) Rd=memh(Rs+Rt<<#u2)
 710 let AddedComplexity = 15, isPredicated = 1 in
 711 def LDrih_indexed_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
 712                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 713                     "if ($src1.new) $dst=memh($src2+$src3<<#0)",
 714                     []>,
 715                     Requires<[HasV4T]>;
 716
 717 // if (!Pv) Rd=memh(Rs+Rt<<#u2)
 718 let AddedComplexity = 15, isPredicated = 1 in
 719 def LDrih_indexed_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 720                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 721                     "if (!$src1) $dst=memh($src2+$src3<<#0)",
 722                     []>,
 723                     Requires<[HasV4T]>;
 724
 725 // if (!Pv.new) Rd=memh(Rs+Rt<<#u2)
 726 let AddedComplexity = 15, isPredicated = 1 in
 727 def LDrih_indexed_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 728                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 729                     "if (!$src1.new) $dst=memh($src2+$src3<<#0)",
 730                     []>,
 731                     Requires<[HasV4T]>;
 732
 733 //// Load unsigned halfword conditionally.
 734 // if ([!]Pv[.new]) Rd=memuh(Rs+Rt<<#u2)
 735 // if (Pv) Rd=memuh(Rs+Rt<<#u2)
 736 let AddedComplexity = 15, isPredicated = 1 in
 737 def LDriuh_indexed_cPt_V4 : LDInst2<(outs IntRegs:$dst),
 738                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 739                     "if ($src1) $dst=memuh($src2+$src3<<#0)",
 740                     []>,
 741                     Requires<[HasV4T]>;
 742
 743 // if (Pv.new) Rd=memuh(Rs+Rt<<#u2)
 744 let AddedComplexity = 15, isPredicated = 1 in
 745 def LDriuh_indexed_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
 746                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 747                     "if ($src1.new) $dst=memuh($src2+$src3<<#0)",
 748                     []>,
 749                     Requires<[HasV4T]>;
 750
 751 // if (!Pv) Rd=memuh(Rs+Rt<<#u2)
 752 let AddedComplexity = 15, isPredicated = 1 in
 753 def LDriuh_indexed_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 754                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 755                     "if (!$src1) $dst=memuh($src2+$src3<<#0)",
 756                     []>,
 757                     Requires<[HasV4T]>;
 758
 759 // if (!Pv.new) Rd=memuh(Rs+Rt<<#u2)
 760 let AddedComplexity = 15, isPredicated = 1 in
 761 def LDriuh_indexed_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 762                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 763                     "if (!$src1.new) $dst=memuh($src2+$src3<<#0)",
 764                     []>,
 765                     Requires<[HasV4T]>;
 766
 767 // Rd=memh(Rt<<#u2+#U6)
 768
 769 //// Load word.
 770 // Load predicate: Fix for bug 5279.
 771 let neverHasSideEffects = 1 in
 772 def LDriw_pred_V4 : LDInst2<(outs PredRegs:$dst),
 773             (ins MEMri:$addr),
 774             "Error; should not emit",
 775             []>,
 776             Requires<[HasV4T]>;
 777
 778 // Rd=memw(Re=#U6)
 779
 780 // Rd=memw(Rs+Rt<<#u2)
 781 let AddedComplexity = 10, isPredicable = 1 in
 782 def LDriw_indexed_V4 : LDInst<(outs IntRegs:$dst),
 783                     (ins IntRegs:$src1, IntRegs:$src2),
 784                     "$dst=memw($src1+$src2<<#0)",
 785                     [(set (i32 IntRegs:$dst),
 786                           (i32 (load (add (i32 IntRegs:$src1),
 787                                           (i32 IntRegs:$src2)))))]>,
 788                     Requires<[HasV4T]>;
 789
 790 //// Load word conditionally.
 791 // if ([!]Pv[.new]) Rd=memw(Rs+Rt<<#u2)
 792 // if (Pv) Rd=memw(Rs+Rt<<#u2)
 793 let AddedComplexity = 15, isPredicated = 1 in
 794 def LDriw_indexed_cPt_V4 : LDInst2<(outs IntRegs:$dst),
 795                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 796                     "if ($src1) $dst=memw($src2+$src3<<#0)",
 797                     []>,
 798                     Requires<[HasV4T]>;
 799
 800 // if (Pv.new) Rd=memh(Rs+Rt<<#u2)
 801 let AddedComplexity = 15, isPredicated = 1 in
 802 def LDriw_indexed_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
 803                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 804                     "if ($src1.new) $dst=memw($src2+$src3<<#0)",
 805                     []>,
 806                     Requires<[HasV4T]>;
 807
 808 // if (!Pv) Rd=memh(Rs+Rt<<#u2)
 809 let AddedComplexity = 15, isPredicated = 1 in
 810 def LDriw_indexed_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 811                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 812                     "if (!$src1) $dst=memw($src2+$src3<<#0)",
 813                     []>,
 814                     Requires<[HasV4T]>;
 815
 816 // if (!Pv.new) Rd=memh(Rs+Rt<<#u2)
 817 let AddedComplexity = 15, isPredicated = 1 in
 818 def LDriw_indexed_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 819                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 820                     "if (!$src1.new) $dst=memw($src2+$src3<<#0)",
 821                     []>,
 822                     Requires<[HasV4T]>;
 823
 824 /// Load from global offset
 825
 826 let isPredicable = 1, neverHasSideEffects = 1 in
 827 def LDrid_GP_V4 : LDInst2<(outs DoubleRegs:$dst),
 828             (ins globaladdress:$global, u16Imm:$offset),
 829             "$dst=memd(#$global+$offset)",
 830             []>,
 831             Requires<[HasV4T]>;
 832
 833 let neverHasSideEffects = 1, isPredicated = 1 in
 834 def LDrid_GP_cPt_V4 : LDInst2<(outs DoubleRegs:$dst),
 835             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 836             "if ($src1) $dst=memd(##$global+$offset)",
 837             []>,
 838             Requires<[HasV4T]>;
 839
 840 let neverHasSideEffects = 1, isPredicated = 1 in
 841 def LDrid_GP_cNotPt_V4 : LDInst2<(outs DoubleRegs:$dst),
 842             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 843             "if (!$src1) $dst=memd(##$global+$offset)",
 844             []>,
 845             Requires<[HasV4T]>;
 846
 847 let neverHasSideEffects = 1, isPredicated = 1 in
 848 def LDrid_GP_cdnPt_V4 : LDInst2<(outs DoubleRegs:$dst),
 849             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 850             "if ($src1.new) $dst=memd(##$global+$offset)",
 851             []>,
 852             Requires<[HasV4T]>;
 853
 854 let neverHasSideEffects = 1, isPredicated = 1 in
 855 def LDrid_GP_cdnNotPt_V4 : LDInst2<(outs DoubleRegs:$dst),
 856             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 857             "if (!$src1.new) $dst=memd(##$global+$offset)",
 858             []>,
 859             Requires<[HasV4T]>;
 860
 861 let isPredicable = 1, neverHasSideEffects = 1 in
 862 def LDrib_GP_V4 : LDInst2<(outs IntRegs:$dst),
 863             (ins globaladdress:$global, u16Imm:$offset),
 864             "$dst=memb(#$global+$offset)",
 865             []>,
 866             Requires<[HasV4T]>;
 867
 868 let neverHasSideEffects = 1, isPredicated = 1 in
 869 def LDrib_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst),
 870             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 871             "if ($src1) $dst=memb(##$global+$offset)",
 872             []>,
 873             Requires<[HasV4T]>;
 874
 875 let neverHasSideEffects = 1, isPredicated = 1 in
 876 def LDrib_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 877             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 878             "if (!$src1) $dst=memb(##$global+$offset)",
 879             []>,
 880             Requires<[HasV4T]>;
 881
 882 let neverHasSideEffects = 1, isPredicated = 1 in
 883 def LDrib_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
 884             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 885             "if ($src1.new) $dst=memb(##$global+$offset)",
 886             []>,
 887             Requires<[HasV4T]>;
 888
 889 let neverHasSideEffects = 1, isPredicated = 1 in
 890 def LDrib_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 891             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 892             "if (!$src1.new) $dst=memb(##$global+$offset)",
 893             []>,
 894             Requires<[HasV4T]>;
 895
 896
 897 let isPredicable = 1, neverHasSideEffects = 1 in
 898 def LDriub_GP_V4 : LDInst2<(outs IntRegs:$dst),
 899             (ins globaladdress:$global, u16Imm:$offset),
 900             "$dst=memub(#$global+$offset)",
 901             []>,
 902             Requires<[HasV4T]>;
 903
 904
 905 let neverHasSideEffects = 1, isPredicated = 1 in
 906 def LDriub_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst),
 907             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 908             "if ($src1) $dst=memub(##$global+$offset)",
 909             []>,
 910             Requires<[HasV4T]>;
 911
 912 let neverHasSideEffects = 1, isPredicated = 1 in
 913 def LDriub_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 914             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 915             "if (!$src1) $dst=memub(##$global+$offset)",
 916             []>,
 917             Requires<[HasV4T]>;
 918
 919 let neverHasSideEffects = 1, isPredicated = 1 in
 920 def LDriub_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
 921             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 922             "if ($src1.new) $dst=memub(##$global+$offset)",
 923             []>,
 924             Requires<[HasV4T]>;
 925
 926 let neverHasSideEffects = 1, isPredicated = 1 in
 927 def LDriub_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 928             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 929             "if (!$src1.new) $dst=memub(##$global+$offset)",
 930             []>,
 931             Requires<[HasV4T]>;
 932
 933
 934 let isPredicable = 1, neverHasSideEffects = 1 in
 935 def LDrih_GP_V4 : LDInst2<(outs IntRegs:$dst),
 936             (ins globaladdress:$global, u16Imm:$offset),
 937             "$dst=memh(#$global+$offset)",
 938             []>,
 939             Requires<[HasV4T]>;
 940
 941
 942 let neverHasSideEffects = 1, isPredicated = 1 in
 943 def LDrih_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst),
 944             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 945             "if ($src1) $dst=memh(##$global+$offset)",
 946             []>,
 947             Requires<[HasV4T]>;
 948
 949 let neverHasSideEffects = 1, isPredicated = 1 in
 950 def LDrih_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 951             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 952             "if (!$src1) $dst=memh(##$global+$offset)",
 953             []>,
 954             Requires<[HasV4T]>;
 955
 956 let neverHasSideEffects = 1, isPredicated = 1 in
 957 def LDrih_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
 958             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 959             "if ($src1.new) $dst=memh(##$global+$offset)",
 960             []>,
 961             Requires<[HasV4T]>;
 962
 963 let neverHasSideEffects = 1, isPredicated = 1 in
 964 def LDrih_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 965             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 966             "if (!$src1.new) $dst=memh(##$global+$offset)",
 967             []>,
 968             Requires<[HasV4T]>;
 969
 970
 971 let isPredicable = 1, neverHasSideEffects = 1 in
 972 def LDriuh_GP_V4 : LDInst2<(outs IntRegs:$dst),
 973             (ins globaladdress:$global, u16Imm:$offset),
 974             "$dst=memuh(#$global+$offset)",
 975             []>,
 976             Requires<[HasV4T]>;
 977
 978 let neverHasSideEffects = 1, isPredicated = 1 in
 979 def LDriuh_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst),
 980             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 981             "if ($src1) $dst=memuh(##$global+$offset)",
 982             []>,
 983             Requires<[HasV4T]>;
 984
 985 let neverHasSideEffects = 1, isPredicated = 1 in
 986 def LDriuh_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 987             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 988             "if (!$src1) $dst=memuh(##$global+$offset)",
 989             []>,
 990             Requires<[HasV4T]>;
 991
 992 let neverHasSideEffects = 1, isPredicated = 1 in
 993 def LDriuh_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
 994             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 995             "if ($src1.new) $dst=memuh(##$global+$offset)",
 996             []>,
 997             Requires<[HasV4T]>;
 998
 999 let neverHasSideEffects = 1, isPredicated = 1 in
1000 def LDriuh_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1001             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
1002             "if (!$src1.new) $dst=memuh(##$global+$offset)",
1003             []>,
1004             Requires<[HasV4T]>;
1005
1006 let isPredicable = 1, neverHasSideEffects = 1 in
1007 def LDriw_GP_V4 : LDInst2<(outs IntRegs:$dst),
1008             (ins globaladdress:$global, u16Imm:$offset),
1009             "$dst=memw(#$global+$offset)",
1010             []>,
1011             Requires<[HasV4T]>;
1012
1013
1014 let neverHasSideEffects = 1, isPredicated = 1 in
1015 def LDriw_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst),
1016             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
1017             "if ($src1) $dst=memw(##$global+$offset)",
1018             []>,
1019             Requires<[HasV4T]>;
1020
1021 let neverHasSideEffects = 1, isPredicated = 1 in
1022 def LDriw_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1023             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
1024             "if (!$src1) $dst=memw(##$global+$offset)",
1025             []>,
1026             Requires<[HasV4T]>;
1027
1028
1029 let neverHasSideEffects = 1, isPredicated = 1 in
1030 def LDriw_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
1031             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
1032             "if ($src1.new) $dst=memw(##$global+$offset)",
1033             []>,
1034             Requires<[HasV4T]>;
1035
1036 let neverHasSideEffects = 1, isPredicated = 1 in
1037 def LDriw_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1038             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
1039             "if (!$src1.new) $dst=memw(##$global+$offset)",
1040             []>,
1041             Requires<[HasV4T]>;
1042
1043
1044 let isPredicable = 1, neverHasSideEffects = 1, validSubTargets = HasV4SubT in
1045 def LDd_GP_V4 : LDInst2<(outs DoubleRegs:$dst),
1046             (ins globaladdress:$global),
1047             "$dst=memd(#$global)",
1048             []>,
1049             Requires<[HasV4T]>;
1050
1051 // if (Pv) Rtt=memd(##global)
1052 let neverHasSideEffects = 1, isPredicated = 1, isExtended = 1, opExtendable = 2,
1053 validSubTargets = HasV4SubT in {
1054 def LDd_GP_cPt_V4 : LDInst2<(outs DoubleRegs:$dst),
1055             (ins PredRegs:$src1, globaladdress:$global),
1056             "if ($src1) $dst=memd(##$global)",
1057             []>,
1058             Requires<[HasV4T]>;
1059
1060
1061 // if (!Pv) Rtt=memd(##global)
1062 def LDd_GP_cNotPt_V4 : LDInst2<(outs DoubleRegs:$dst),
1063             (ins PredRegs:$src1, globaladdress:$global),
1064             "if (!$src1) $dst=memd(##$global)",
1065             []>,
1066             Requires<[HasV4T]>;
1067
1068 // if (Pv) Rtt=memd(##global)
1069 def LDd_GP_cdnPt_V4 : LDInst2<(outs DoubleRegs:$dst),
1070             (ins PredRegs:$src1, globaladdress:$global),
1071             "if ($src1.new) $dst=memd(##$global)",
1072             []>,
1073             Requires<[HasV4T]>;
1074
1075
1076 // if (!Pv) Rtt=memd(##global)
1077 def LDd_GP_cdnNotPt_V4 : LDInst2<(outs DoubleRegs:$dst),
1078             (ins PredRegs:$src1, globaladdress:$global),
1079             "if (!$src1.new) $dst=memd(##$global)",
1080             []>,
1081             Requires<[HasV4T]>;
1082 }
1083
1084 let isPredicable = 1, neverHasSideEffects = 1, validSubTargets = HasV4SubT in
1085 def LDb_GP_V4 : LDInst2<(outs IntRegs:$dst),
1086             (ins globaladdress:$global),
1087             "$dst=memb(#$global)",
1088             []>,
1089             Requires<[HasV4T]>;
1090
1091 // if (Pv) Rt=memb(##global)
1092 let neverHasSideEffects = 1, isPredicated = 1, isExtended = 1, opExtendable = 2,
1093 validSubTargets = HasV4SubT in {
1094 def LDb_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst),
1095             (ins PredRegs:$src1, globaladdress:$global),
1096             "if ($src1) $dst=memb(##$global)",
1097             []>,
1098             Requires<[HasV4T]>;
1099
1100 // if (!Pv) Rt=memb(##global)
1101 def LDb_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1102             (ins PredRegs:$src1, globaladdress:$global),
1103             "if (!$src1) $dst=memb(##$global)",
1104             []>,
1105             Requires<[HasV4T]>;
1106
1107 // if (Pv) Rt=memb(##global)
1108 def LDb_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
1109             (ins PredRegs:$src1, globaladdress:$global),
1110             "if ($src1.new) $dst=memb(##$global)",
1111             []>,
1112             Requires<[HasV4T]>;
1113
1114 // if (!Pv) Rt=memb(##global)
1115 def LDb_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1116             (ins PredRegs:$src1, globaladdress:$global),
1117             "if (!$src1.new) $dst=memb(##$global)",
1118             []>,
1119             Requires<[HasV4T]>;
1120 }
1121
1122 let isPredicable = 1, neverHasSideEffects = 1, validSubTargets = HasV4SubT in
1123 def LDub_GP_V4 : LDInst2<(outs IntRegs:$dst),
1124             (ins globaladdress:$global),
1125             "$dst=memub(#$global)",
1126             []>,
1127             Requires<[HasV4T]>;
1128
1129 // if (Pv) Rt=memub(##global)
1130 let neverHasSideEffects = 1, isPredicated = 1, isExtended = 1, opExtendable = 2,
1131 validSubTargets = HasV4SubT in {
1132 def LDub_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst),
1133             (ins PredRegs:$src1, globaladdress:$global),
1134             "if ($src1) $dst=memub(##$global)",
1135             []>,
1136             Requires<[HasV4T]>;
1137
1138
1139 // if (!Pv) Rt=memub(##global)
1140 def LDub_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1141             (ins PredRegs:$src1, globaladdress:$global),
1142             "if (!$src1) $dst=memub(##$global)",
1143             []>,
1144             Requires<[HasV4T]>;
1145
1146 // if (Pv) Rt=memub(##global)
1147 def LDub_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
1148             (ins PredRegs:$src1, globaladdress:$global),
1149             "if ($src1.new) $dst=memub(##$global)",
1150             []>,
1151             Requires<[HasV4T]>;
1152
1153
1154 // if (!Pv) Rt=memub(##global)
1155 def LDub_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1156             (ins PredRegs:$src1, globaladdress:$global),
1157             "if (!$src1.new) $dst=memub(##$global)",
1158             []>,
1159             Requires<[HasV4T]>;
1160 }
1161
1162 let isPredicable = 1, neverHasSideEffects = 1, validSubTargets = HasV4SubT in
1163 def LDh_GP_V4 : LDInst2<(outs IntRegs:$dst),
1164             (ins globaladdress:$global),
1165             "$dst=memh(#$global)",
1166             []>,
1167             Requires<[HasV4T]>;
1168
1169 // if (Pv) Rt=memh(##global)
1170 let neverHasSideEffects = 1, isPredicated = 1, isExtended = 1, opExtendable = 2,
1171 validSubTargets = HasV4SubT in {
1172 def LDh_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst),
1173             (ins PredRegs:$src1, globaladdress:$global),
1174             "if ($src1) $dst=memh(##$global)",
1175             []>,
1176             Requires<[HasV4T]>;
1177
1178 // if (!Pv) Rt=memh(##global)
1179 def LDh_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1180             (ins PredRegs:$src1, globaladdress:$global),
1181             "if (!$src1) $dst=memh(##$global)",
1182             []>,
1183             Requires<[HasV4T]>;
1184
1185 // if (Pv) Rt=memh(##global)
1186 def LDh_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
1187             (ins PredRegs:$src1, globaladdress:$global),
1188             "if ($src1.new) $dst=memh(##$global)",
1189             []>,
1190             Requires<[HasV4T]>;
1191
1192 // if (!Pv) Rt=memh(##global)
1193 def LDh_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1194             (ins PredRegs:$src1, globaladdress:$global),
1195             "if (!$src1.new) $dst=memh(##$global)",
1196             []>,
1197             Requires<[HasV4T]>;
1198 }
1199
1200 let isPredicable = 1, neverHasSideEffects = 1, validSubTargets = HasV4SubT in
1201 def LDuh_GP_V4 : LDInst2<(outs IntRegs:$dst),
1202             (ins globaladdress:$global),
1203             "$dst=memuh(#$global)",
1204             []>,
1205             Requires<[HasV4T]>;
1206
1207 // if (Pv) Rt=memuh(##global)
1208 let neverHasSideEffects = 1, isPredicated = 1, isExtended = 1, opExtendable = 2,
1209 validSubTargets = HasV4SubT in {
1210 def LDuh_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst),
1211             (ins PredRegs:$src1, globaladdress:$global),
1212             "if ($src1) $dst=memuh(##$global)",
1213             []>,
1214             Requires<[HasV4T]>;
1215
1216 // if (!Pv) Rt=memuh(##global)
1217 def LDuh_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1218             (ins PredRegs:$src1, globaladdress:$global),
1219             "if (!$src1) $dst=memuh(##$global)",
1220             []>,
1221             Requires<[HasV4T]>;
1222
1223 // if (Pv) Rt=memuh(##global)
1224 def LDuh_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
1225             (ins PredRegs:$src1, globaladdress:$global),
1226             "if ($src1.new) $dst=memuh(##$global)",
1227             []>,
1228             Requires<[HasV4T]>;
1229
1230 // if (!Pv) Rt=memuh(##global)
1231 def LDuh_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1232             (ins PredRegs:$src1, globaladdress:$global),
1233             "if (!$src1.new) $dst=memuh(##$global)",
1234             []>,
1235             Requires<[HasV4T]>;
1236 }
1237
1238 let isPredicable = 1, neverHasSideEffects = 1, validSubTargets = HasV4SubT in
1239 def LDw_GP_V4 : LDInst2<(outs IntRegs:$dst),
1240             (ins globaladdress:$global),
1241             "$dst=memw(#$global)",
1242             []>,
1243             Requires<[HasV4T]>;
1244
1245 // if (Pv) Rt=memw(##global)
1246 let neverHasSideEffects = 1, isPredicated = 1, isExtended = 1, opExtendable = 2,
1247 validSubTargets = HasV4SubT in {
1248 def LDw_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst),
1249             (ins PredRegs:$src1, globaladdress:$global),
1250             "if ($src1) $dst=memw(##$global)",
1251             []>,
1252             Requires<[HasV4T]>;
1253
1254
1255 // if (!Pv) Rt=memw(##global)
1256 def LDw_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1257             (ins PredRegs:$src1, globaladdress:$global),
1258             "if (!$src1) $dst=memw(##$global)",
1259             []>,
1260             Requires<[HasV4T]>;
1261
1262 // if (Pv) Rt=memw(##global)
1263 def LDw_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
1264             (ins PredRegs:$src1, globaladdress:$global),
1265             "if ($src1.new) $dst=memw(##$global)",
1266             []>,
1267             Requires<[HasV4T]>;
1268
1269
1270 // if (!Pv) Rt=memw(##global)
1271 def LDw_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1272             (ins PredRegs:$src1, globaladdress:$global),
1273             "if (!$src1.new) $dst=memw(##$global)",
1274             []>,
1275             Requires<[HasV4T]>;
1276 }
1277
1278
1279 def : Pat <(atomic_load_64 (HexagonCONST32_GP tglobaladdr:$global)),
1280            (i64 (LDd_GP_V4 tglobaladdr:$global))>,
1281             Requires<[HasV4T]>;
1282
1283 def : Pat <(atomic_load_32 (HexagonCONST32_GP tglobaladdr:$global)),
1284            (i32 (LDw_GP_V4 tglobaladdr:$global))>,
1285             Requires<[HasV4T]>;
1286
1287 def : Pat <(atomic_load_16 (HexagonCONST32_GP tglobaladdr:$global)),
1288            (i32 (LDuh_GP_V4 tglobaladdr:$global))>,
1289             Requires<[HasV4T]>;
1290
1291 def : Pat <(atomic_load_8 (HexagonCONST32_GP tglobaladdr:$global)),
1292            (i32 (LDub_GP_V4 tglobaladdr:$global))>,
1293             Requires<[HasV4T]>;
1294
1295 // Map from load(globaladdress) -> memw(#foo + 0)
1296 let AddedComplexity = 100 in
1297 def : Pat <(i64 (load (HexagonCONST32_GP tglobaladdr:$global))),
1298            (i64 (LDd_GP_V4 tglobaladdr:$global))>,
1299             Requires<[HasV4T]>;
1300
1301 // Map from Pd = load(globaladdress) -> Rd = memb(globaladdress), Pd = Rd
1302 let AddedComplexity = 100 in
1303 def : Pat <(i1 (load (HexagonCONST32_GP tglobaladdr:$global))),
1304            (i1 (TFR_PdRs (i32 (LDb_GP_V4 tglobaladdr:$global))))>,
1305            Requires<[HasV4T]>;
1306
1307 // When the Interprocedural Global Variable optimizer realizes that a certain
1308 // global variable takes only two constant values, it shrinks the global to
1309 // a boolean. Catch those loads here in the following 3 patterns.
1310 let AddedComplexity = 100 in
1311 def : Pat <(i32 (extloadi1 (HexagonCONST32_GP tglobaladdr:$global))),
1312            (i32 (LDb_GP_V4 tglobaladdr:$global))>,
1313             Requires<[HasV4T]>;
1314
1315 let AddedComplexity = 100 in
1316 def : Pat <(i32 (sextloadi1 (HexagonCONST32_GP tglobaladdr:$global))),
1317            (i32 (LDb_GP_V4 tglobaladdr:$global))>,
1318             Requires<[HasV4T]>;
1319
1320 // Map from load(globaladdress) -> memb(#foo)
1321 let AddedComplexity = 100 in
1322 def : Pat <(i32 (extloadi8 (HexagonCONST32_GP tglobaladdr:$global))),
1323            (i32 (LDb_GP_V4 tglobaladdr:$global))>,
1324             Requires<[HasV4T]>;
1325
1326 // Map from load(globaladdress) -> memb(#foo)
1327 let AddedComplexity = 100 in
1328 def : Pat <(i32 (sextloadi8 (HexagonCONST32_GP tglobaladdr:$global))),
1329            (i32 (LDb_GP_V4 tglobaladdr:$global))>,
1330             Requires<[HasV4T]>;
1331
1332 let AddedComplexity = 100 in
1333 def : Pat <(i32 (zextloadi1 (HexagonCONST32_GP tglobaladdr:$global))),
1334            (i32 (LDub_GP_V4 tglobaladdr:$global))>,
1335             Requires<[HasV4T]>;
1336
1337 // Map from load(globaladdress) -> memub(#foo)
1338 let AddedComplexity = 100 in
1339 def : Pat <(i32 (zextloadi8 (HexagonCONST32_GP tglobaladdr:$global))),
1340            (i32 (LDub_GP_V4 tglobaladdr:$global))>,
1341             Requires<[HasV4T]>;
1342
1343 // Map from load(globaladdress) -> memh(#foo)
1344 let AddedComplexity = 100 in
1345 def : Pat <(i32 (extloadi16 (HexagonCONST32_GP tglobaladdr:$global))),
1346            (i32 (LDh_GP_V4 tglobaladdr:$global))>,
1347             Requires<[HasV4T]>;
1348
1349 // Map from load(globaladdress) -> memh(#foo)
1350 let AddedComplexity = 100 in
1351 def : Pat <(i32 (sextloadi16 (HexagonCONST32_GP tglobaladdr:$global))),
1352            (i32 (LDh_GP_V4 tglobaladdr:$global))>,
1353             Requires<[HasV4T]>;
1354
1355 // Map from load(globaladdress) -> memuh(#foo)
1356 let AddedComplexity = 100 in
1357 def : Pat <(i32 (zextloadi16 (HexagonCONST32_GP tglobaladdr:$global))),
1358            (i32 (LDuh_GP_V4 tglobaladdr:$global))>,
1359             Requires<[HasV4T]>;
1360
1361 // Map from load(globaladdress) -> memw(#foo)
1362 let AddedComplexity = 100 in
1363 def : Pat <(i32 (load (HexagonCONST32_GP tglobaladdr:$global))),
1364            (i32 (LDw_GP_V4 tglobaladdr:$global))>,
1365             Requires<[HasV4T]>;
1366
1367 def : Pat <(atomic_load_64 (add (HexagonCONST32_GP tglobaladdr:$global),
1368                                 u16ImmPred:$offset)),
1369            (i64 (LDrid_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
1370            Requires<[HasV4T]>;
1371
1372 def : Pat <(atomic_load_32 (add (HexagonCONST32_GP tglobaladdr:$global),
1373                                 u16ImmPred:$offset)),
1374            (i32 (LDriw_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
1375             Requires<[HasV4T]>;
1376
1377 def : Pat <(atomic_load_16 (add (HexagonCONST32_GP tglobaladdr:$global),
1378                                 u16ImmPred:$offset)),
1379            (i32 (LDriuh_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
1380             Requires<[HasV4T]>;
1381
1382 def : Pat <(atomic_load_8 (add (HexagonCONST32_GP tglobaladdr:$global),
1383                                u16ImmPred:$offset)),
1384            (i32 (LDriub_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
1385            Requires<[HasV4T]>;
1386
1387 // Map from load(globaladdress + x) -> memd(#foo + x)
1388 let AddedComplexity = 100 in
1389 def : Pat <(i64 (load (add (HexagonCONST32_GP tglobaladdr:$global),
1390                            u16ImmPred:$offset))),
1391            (i64 (LDrid_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
1392            Requires<[HasV4T]>;
1393
1394 // Map from load(globaladdress + x) -> memb(#foo + x)
1395 let AddedComplexity = 100 in
1396 def : Pat <(i32 (extloadi8 (add (HexagonCONST32_GP tglobaladdr:$global),
1397                            u16ImmPred:$offset))),
1398            (i32 (LDrib_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
1399            Requires<[HasV4T]>;
1400
1401 // Map from load(globaladdress + x) -> memb(#foo + x)
1402 let AddedComplexity = 100 in
1403 def : Pat <(i32 (sextloadi8 (add (HexagonCONST32_GP tglobaladdr:$global),
1404                             u16ImmPred:$offset))),
1405            (i32 (LDrib_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
1406            Requires<[HasV4T]>;
1407
1408 // Map from load(globaladdress + x) -> memub(#foo + x)
1409 let AddedComplexity = 100 in
1410 def : Pat <(i32 (zextloadi8 (add (HexagonCONST32_GP tglobaladdr:$global),
1411                             u16ImmPred:$offset))),
1412            (i32 (LDriub_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
1413            Requires<[HasV4T]>;
1414
1415 // Map from load(globaladdress + x) -> memuh(#foo + x)
1416 let AddedComplexity = 100 in
1417 def : Pat <(i32 (extloadi16 (add (HexagonCONST32_GP tglobaladdr:$global),
1418                             u16ImmPred:$offset))),
1419            (i32 (LDrih_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
1420             Requires<[HasV4T]>;
1421
1422 // Map from load(globaladdress + x) -> memh(#foo + x)
1423 let AddedComplexity = 100 in
1424 def : Pat <(i32 (sextloadi16 (add (HexagonCONST32_GP tglobaladdr:$global),
1425                              u16ImmPred:$offset))),
1426            (i32 (LDrih_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
1427            Requires<[HasV4T]>;
1428
1429
1430 // Map from load(globaladdress + x) -> memuh(#foo + x)
1431 let AddedComplexity = 100 in
1432 def : Pat <(i32 (zextloadi16 (add (HexagonCONST32_GP tglobaladdr:$global),
1433                              u16ImmPred:$offset))),
1434            (i32 (LDriuh_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
1435             Requires<[HasV4T]>;
1436
1437 // Map from load(globaladdress + x) -> memw(#foo + x)
1438 let AddedComplexity = 100 in
1439 def : Pat <(i32 (load (add (HexagonCONST32_GP tglobaladdr:$global),
1440                       u16ImmPred:$offset))),
1441            (i32 (LDriw_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
1442             Requires<[HasV4T]>;
1443
1444
1445 //===----------------------------------------------------------------------===//
1446 // LD -
1447 //===----------------------------------------------------------------------===//
1448
1449 //===----------------------------------------------------------------------===//
1450 // ST +
1451 //===----------------------------------------------------------------------===//
1452 ///
1453 /// Assumptions::: ****** DO NOT IGNORE ********
1454 /// 1. Make sure that in post increment store, the zero'th operand is always the
1455 ///    post increment operand.
1456 /// 2. Make sure that the store value operand(Rt/Rtt) in a store is always the
1457 ///    last operand.
1458 ///
1459
1460 // memd(Re=#U6)=Rtt
1461 def STrid_abs_setimm_V4 : STInst2<(outs IntRegs:$dst1),
1462             (ins DoubleRegs:$src1, u6Imm:$src2),
1463             "memd($dst1=#$src2) = $src1",
1464             []>,
1465             Requires<[HasV4T]>;
1466
1467 // memb(Re=#U6)=Rs
1468 def STrib_abs_setimm_V4 : STInst2<(outs IntRegs:$dst1),
1469             (ins IntRegs:$src1, u6Imm:$src2),
1470             "memb($dst1=#$src2) = $src1",
1471             []>,
1472             Requires<[HasV4T]>;
1473
1474 // memh(Re=#U6)=Rs
1475 def STrih_abs_setimm_V4 : STInst2<(outs IntRegs:$dst1),
1476             (ins IntRegs:$src1, u6Imm:$src2),
1477             "memh($dst1=#$src2) = $src1",
1478             []>,
1479             Requires<[HasV4T]>;
1480
1481 // memw(Re=#U6)=Rs
1482 def STriw_abs_setimm_V4 : STInst2<(outs IntRegs:$dst1),
1483             (ins IntRegs:$src1, u6Imm:$src2),
1484             "memw($dst1=#$src2) = $src1",
1485             []>,
1486             Requires<[HasV4T]>;
1487
1488 // memd(Re=#U6)=Rtt
1489 def STrid_abs_set_V4 : STInst2<(outs IntRegs:$dst1),
1490             (ins DoubleRegs:$src1, globaladdress:$src2),
1491             "memd($dst1=##$src2) = $src1",
1492             []>,
1493             Requires<[HasV4T]>;
1494
1495 // memb(Re=#U6)=Rs
1496 def STrib_abs_set_V4 : STInst2<(outs IntRegs:$dst1),
1497             (ins IntRegs:$src1, globaladdress:$src2),
1498             "memb($dst1=##$src2) = $src1",
1499             []>,
1500             Requires<[HasV4T]>;
1501
1502 // memh(Re=#U6)=Rs
1503 def STrih_abs_set_V4 : STInst2<(outs IntRegs:$dst1),
1504             (ins IntRegs:$src1, globaladdress:$src2),
1505             "memh($dst1=##$src2) = $src1",
1506             []>,
1507             Requires<[HasV4T]>;
1508
1509 // memw(Re=#U6)=Rs
1510 def STriw_abs_set_V4 : STInst2<(outs IntRegs:$dst1),
1511             (ins IntRegs:$src1, globaladdress:$src2),
1512             "memw($dst1=##$src2) = $src1",
1513             []>,
1514             Requires<[HasV4T]>;
1515
1516
1517 // multiclass for store instructions with base + register offset addressing
1518 // mode
1519 multiclass ST_Idxd_shl_Pbase<string mnemonic, RegisterClass RC, bit isNot,
1520                              bit isPredNew> {
1521   let PNewValue = #!if(isPredNew, "new", "") in
1522   def #NAME# : STInst2<(outs),
1523             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
1524                  RC:$src5),
1525             !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1526             ") ")#mnemonic#"($src2+$src3<<#$src4) = $src5",
1527             []>,
1528             Requires<[HasV4T]>;
1529 }
1530
1531 multiclass ST_Idxd_shl_Pred<string mnemonic, RegisterClass RC, bit PredNot> {
1532   let PredSense = #!if(PredNot, "false", "true") in {
1533     defm _c#NAME# : ST_Idxd_shl_Pbase<mnemonic, RC, PredNot, 0>;
1534     // Predicate new
1535     defm _cdn#NAME# : ST_Idxd_shl_Pbase<mnemonic, RC, PredNot, 1>;
1536   }
1537 }
1538
1539 let isNVStorable = 1 in
1540 multiclass ST_Idxd_shl<string mnemonic, string CextOp, RegisterClass RC> {
1541   let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed_shl in {
1542     let isPredicable = 1 in
1543     def #NAME#_V4 : STInst2<(outs),
1544             (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$src3, RC:$src4),
1545             #mnemonic#"($src1+$src2<<#$src3) = $src4",
1546             []>,
1547             Requires<[HasV4T]>;
1548
1549     let isPredicated = 1 in {
1550       defm Pt_V4 : ST_Idxd_shl_Pred<mnemonic, RC, 0 >;
1551       defm NotPt_V4 : ST_Idxd_shl_Pred<mnemonic, RC, 1>;
1552     }
1553   }
1554 }
1555
1556 // multiclass for new-value store instructions with base + register offset
1557 // addressing mode.
1558 multiclass ST_Idxd_shl_Pbase_nv<string mnemonic, RegisterClass RC, bit isNot,
1559                              bit isPredNew> {
1560   let PNewValue = #!if(isPredNew, "new", "") in
1561   def #NAME#_nv_V4 : NVInst_V4<(outs),
1562             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
1563                  RC:$src5),
1564             !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1565             ") ")#mnemonic#"($src2+$src3<<#$src4) = $src5.new",
1566             []>,
1567             Requires<[HasV4T]>;
1568 }
1569
1570 multiclass ST_Idxd_shl_Pred_nv<string mnemonic, RegisterClass RC, bit PredNot> {
1571   let PredSense = #!if(PredNot, "false", "true") in {
1572     defm _c#NAME# : ST_Idxd_shl_Pbase_nv<mnemonic, RC, PredNot, 0>;
1573     // Predicate new
1574     defm _cdn#NAME# : ST_Idxd_shl_Pbase_nv<mnemonic, RC, PredNot, 1>;
1575   }
1576 }
1577
1578 let mayStore = 1, isNVStore = 1 in
1579 multiclass ST_Idxd_shl_nv<string mnemonic, string CextOp, RegisterClass RC> {
1580   let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed_shl in {
1581     let isPredicable = 1 in
1582     def #NAME#_nv_V4 : NVInst_V4<(outs),
1583             (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$src3, RC:$src4),
1584             #mnemonic#"($src1+$src2<<#$src3) = $src4.new",
1585             []>,
1586             Requires<[HasV4T]>;
1587
1588     let isPredicated = 1 in {
1589       defm Pt : ST_Idxd_shl_Pred_nv<mnemonic, RC, 0 >;
1590       defm NotPt : ST_Idxd_shl_Pred_nv<mnemonic, RC, 1>;
1591     }
1592   }
1593 }
1594
1595 let addrMode = BaseRegOffset, neverHasSideEffects = 1,
1596 validSubTargets = HasV4SubT in {
1597   defm STrib_indexed_shl: ST_Idxd_shl<"memb", "STrib", IntRegs>,
1598                           ST_Idxd_shl_nv<"memb", "STrib", IntRegs>, AddrModeRel;
1599
1600   defm STrih_indexed_shl: ST_Idxd_shl<"memh", "STrih", IntRegs>,
1601                           ST_Idxd_shl_nv<"memh", "STrih", IntRegs>, AddrModeRel;
1602
1603   defm STriw_indexed_shl: ST_Idxd_shl<"memw", "STriw", IntRegs>,
1604                           ST_Idxd_shl_nv<"memw", "STriw", IntRegs>, AddrModeRel;
1605
1606   let isNVStorable = 0 in
1607   defm STrid_indexed_shl: ST_Idxd_shl<"memd", "STrid", DoubleRegs>, AddrModeRel;
1608 }
1609
1610 let Predicates = [HasV4T], AddedComplexity = 10 in {
1611 def : Pat<(truncstorei8 (i32 IntRegs:$src4),
1612                        (add IntRegs:$src1, (shl IntRegs:$src2,
1613                                                 u2ImmPred:$src3))),
1614           (STrib_indexed_shl_V4 IntRegs:$src1, IntRegs:$src2,
1615                                 u2ImmPred:$src3, IntRegs:$src4)>;
1616
1617 def : Pat<(truncstorei16 (i32 IntRegs:$src4),
1618                         (add IntRegs:$src1, (shl IntRegs:$src2,
1619                                                  u2ImmPred:$src3))),
1620           (STrih_indexed_shl_V4 IntRegs:$src1, IntRegs:$src2,
1621                                 u2ImmPred:$src3, IntRegs:$src4)>;
1622
1623 def : Pat<(store (i32 IntRegs:$src4),
1624                  (add IntRegs:$src1, (shl IntRegs:$src2, u2ImmPred:$src3))),
1625           (STriw_indexed_shl_V4 IntRegs:$src1, IntRegs:$src2,
1626                                 u2ImmPred:$src3, IntRegs:$src4)>;
1627
1628 def : Pat<(store (i64 DoubleRegs:$src4),
1629                 (add IntRegs:$src1, (shl IntRegs:$src2, u2ImmPred:$src3))),
1630           (STrid_indexed_shl_V4 IntRegs:$src1, IntRegs:$src2,
1631                                 u2ImmPred:$src3, DoubleRegs:$src4)>;
1632 }
1633
1634 // memd(Ru<<#u2+#U6)=Rtt
1635 let AddedComplexity = 10 in
1636 def STrid_shl_V4 : STInst<(outs),
1637             (ins IntRegs:$src1, u2Imm:$src2, u6Imm:$src3, DoubleRegs:$src4),
1638             "memd($src1<<#$src2+#$src3) = $src4",
1639             [(store (i64 DoubleRegs:$src4),
1640                     (add (shl (i32 IntRegs:$src1), u2ImmPred:$src2),
1641                          u6ImmPred:$src3))]>,
1642             Requires<[HasV4T]>;
1643
1644 // memd(Rx++#s4:3)=Rtt
1645 // memd(Rx++#s4:3:circ(Mu))=Rtt
1646 // memd(Rx++I:circ(Mu))=Rtt
1647 // memd(Rx++Mu)=Rtt
1648 // memd(Rx++Mu:brev)=Rtt
1649 // memd(gp+#u16:3)=Rtt
1650
1651 // Store doubleword conditionally.
1652 // if ([!]Pv[.new]) memd(#u6)=Rtt
1653 // TODO: needs to be implemented.
1654
1655 // if ([!]Pv[.new]) memd(Rx++#s4:3)=Rtt
1656 // if (Pv) memd(Rx++#s4:3)=Rtt
1657 // if (Pv.new) memd(Rx++#s4:3)=Rtt
1658 let AddedComplexity = 10, neverHasSideEffects = 1,
1659     isPredicated = 1 in
1660 def POST_STdri_cdnPt_V4 : STInst2PI<(outs IntRegs:$dst),
1661             (ins PredRegs:$src1, DoubleRegs:$src2, IntRegs:$src3,
1662                  s4_3Imm:$offset),
1663             "if ($src1.new) memd($src3++#$offset) = $src2",
1664             [],
1665             "$src3 = $dst">,
1666             Requires<[HasV4T]>;
1667
1668 // if (!Pv) memd(Rx++#s4:3)=Rtt
1669 // if (!Pv.new) memd(Rx++#s4:3)=Rtt
1670 let AddedComplexity = 10, neverHasSideEffects = 1,
1671     isPredicated = 1 in
1672 def POST_STdri_cdnNotPt_V4 : STInst2PI<(outs IntRegs:$dst),
1673             (ins PredRegs:$src1, DoubleRegs:$src2, IntRegs:$src3,
1674                  s4_3Imm:$offset),
1675             "if (!$src1.new) memd($src3++#$offset) = $src2",
1676             [],
1677             "$src3 = $dst">,
1678             Requires<[HasV4T]>;
1679
1680
1681 // multiclass for store instructions with base + immediate offset
1682 // addressing mode and immediate stored value.
1683 multiclass ST_Imm_Pbase<string mnemonic, Operand OffsetOp, bit isNot,
1684                         bit isPredNew> {
1685   let PNewValue = #!if(isPredNew, "new", "") in
1686   def #NAME# : STInst2<(outs),
1687             (ins PredRegs:$src1, IntRegs:$src2, OffsetOp:$src3, s6Ext:$src4),
1688             #!if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1689             ") ")#mnemonic#"($src2+#$src3) = #$src4",
1690             []>,
1691             Requires<[HasV4T]>;
1692 }
1693
1694 multiclass ST_Imm_Pred<string mnemonic, Operand OffsetOp, bit PredNot> {
1695   let PredSense = #!if(PredNot, "false", "true") in {
1696     defm _c#NAME# : ST_Imm_Pbase<mnemonic, OffsetOp, PredNot, 0>;
1697     // Predicate new
1698     defm _cdn#NAME# : ST_Imm_Pbase<mnemonic, OffsetOp, PredNot, 1>;
1699   }
1700 }
1701
1702 let isExtendable = 1, isExtentSigned = 1, neverHasSideEffects = 1 in
1703 multiclass ST_Imm<string mnemonic, string CextOp, Operand OffsetOp> {
1704   let CextOpcode = CextOp, BaseOpcode = CextOp#_imm in {
1705     let opExtendable = 2, opExtentBits = 8, isPredicable = 1 in
1706     def #NAME#_V4 : STInst2<(outs),
1707             (ins IntRegs:$src1, OffsetOp:$src2, s8Ext:$src3),
1708             #mnemonic#"($src1+#$src2) = #$src3",
1709             []>,
1710             Requires<[HasV4T]>;
1711
1712     let opExtendable = 3, opExtentBits = 6, isPredicated = 1 in {
1713       defm Pt_V4 : ST_Imm_Pred<mnemonic, OffsetOp, 0>;
1714       defm NotPt_V4 : ST_Imm_Pred<mnemonic, OffsetOp, 1 >;
1715     }
1716   }
1717 }
1718
1719 let addrMode = BaseImmOffset, InputType = "imm",
1720     validSubTargets = HasV4SubT in {
1721   defm STrib_imm : ST_Imm<"memb", "STrib", u6_0Imm>, ImmRegRel;
1722   defm STrih_imm : ST_Imm<"memh", "STrih", u6_1Imm>, ImmRegRel;
1723   defm STriw_imm : ST_Imm<"memw", "STriw", u6_2Imm>, ImmRegRel;
1724 }
1725
1726 let Predicates = [HasV4T], AddedComplexity = 10 in {
1727 def: Pat<(truncstorei8 s8ExtPred:$src3, (add IntRegs:$src1, u6_0ImmPred:$src2)),
1728             (STrib_imm_V4 IntRegs:$src1, u6_0ImmPred:$src2, s8ExtPred:$src3)>;
1729
1730 def: Pat<(truncstorei16 s8ExtPred:$src3, (add IntRegs:$src1,
1731                                               u6_1ImmPred:$src2)),
1732             (STrih_imm_V4 IntRegs:$src1, u6_1ImmPred:$src2, s8ExtPred:$src3)>;
1733
1734 def: Pat<(store s8ExtPred:$src3, (add IntRegs:$src1, u6_2ImmPred:$src2)),
1735             (STriw_imm_V4 IntRegs:$src1, u6_2ImmPred:$src2, s8ExtPred:$src3)>;
1736 }
1737
1738 let AddedComplexity = 6 in
1739 def : Pat <(truncstorei8 s8ExtPred:$src2, (i32 IntRegs:$src1)),
1740            (STrib_imm_V4 IntRegs:$src1, 0, s8ExtPred:$src2)>,
1741            Requires<[HasV4T]>;
1742
1743 // memb(Ru<<#u2+#U6)=Rt
1744 let AddedComplexity = 10 in
1745 def STrib_shl_V4 : STInst<(outs),
1746             (ins IntRegs:$src1, u2Imm:$src2, u6Imm:$src3, IntRegs:$src4),
1747             "memb($src1<<#$src2+#$src3) = $src4",
1748             [(truncstorei8 (i32 IntRegs:$src4),
1749                            (add (shl (i32 IntRegs:$src1), u2ImmPred:$src2),
1750                                 u6ImmPred:$src3))]>,
1751             Requires<[HasV4T]>;
1752
1753 // memb(Rx++#s4:0:circ(Mu))=Rt
1754 // memb(Rx++I:circ(Mu))=Rt
1755 // memb(Rx++Mu)=Rt
1756 // memb(Rx++Mu:brev)=Rt
1757 // memb(gp+#u16:0)=Rt
1758
1759
1760 // Store byte conditionally.
1761 // if ([!]Pv[.new]) memb(#u6)=Rt
1762 // if ([!]Pv[.new]) memb(Rx++#s4:0)=Rt
1763 // if (Pv) memb(Rx++#s4:0)=Rt
1764 // if (Pv.new) memb(Rx++#s4:0)=Rt
1765 let hasCtrlDep = 1,
1766     isPredicated = 1 in
1767 def POST_STbri_cdnPt_V4 : STInst2PI<(outs IntRegs:$dst),
1768             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_0Imm:$offset),
1769             "if ($src1.new) memb($src3++#$offset) = $src2",
1770             [],"$src3 = $dst">,
1771             Requires<[HasV4T]>;
1772
1773 // if (!Pv) memb(Rx++#s4:0)=Rt
1774 // if (!Pv.new) memb(Rx++#s4:0)=Rt
1775 let hasCtrlDep = 1,
1776     isPredicated = 1 in
1777 def POST_STbri_cdnNotPt_V4 : STInst2PI<(outs IntRegs:$dst),
1778             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_0Imm:$offset),
1779             "if (!$src1.new) memb($src3++#$offset) = $src2",
1780             [],"$src3 = $dst">,
1781             Requires<[HasV4T]>;
1782
1783
1784 // Store halfword.
1785 // TODO: needs to be implemented
1786 // memh(Re=#U6)=Rt.H
1787 // memh(Rs+#s11:1)=Rt.H
1788 let AddedComplexity = 6 in
1789 def : Pat <(truncstorei16 s8ExtPred:$src2, (i32 IntRegs:$src1)),
1790            (STrih_imm_V4 IntRegs:$src1, 0, s8ExtPred:$src2)>,
1791            Requires<[HasV4T]>;
1792
1793 // memh(Rs+Ru<<#u2)=Rt.H
1794 // TODO: needs to be implemented.
1795
1796 // memh(Ru<<#u2+#U6)=Rt.H
1797 // memh(Ru<<#u2+#U6)=Rt
1798 let AddedComplexity = 10 in
1799 def STrih_shl_V4 : STInst<(outs),
1800             (ins IntRegs:$src1, u2Imm:$src2, u6Imm:$src3, IntRegs:$src4),
1801             "memh($src1<<#$src2+#$src3) = $src4",
1802             [(truncstorei16 (i32 IntRegs:$src4),
1803                             (add (shl (i32 IntRegs:$src1), u2ImmPred:$src2),
1804                                  u6ImmPred:$src3))]>,
1805             Requires<[HasV4T]>;
1806
1807 // memh(Rx++#s4:1:circ(Mu))=Rt.H
1808 // memh(Rx++#s4:1:circ(Mu))=Rt
1809 // memh(Rx++I:circ(Mu))=Rt.H
1810 // memh(Rx++I:circ(Mu))=Rt
1811 // memh(Rx++Mu)=Rt.H
1812 // memh(Rx++Mu)=Rt
1813 // memh(Rx++Mu:brev)=Rt.H
1814 // memh(Rx++Mu:brev)=Rt
1815 // memh(gp+#u16:1)=Rt
1816 // if ([!]Pv[.new]) memh(#u6)=Rt.H
1817 // if ([!]Pv[.new]) memh(#u6)=Rt
1818
1819
1820 // if ([!]Pv[.new]) memh(Rs+#u6:1)=Rt.H
1821 // TODO: needs to be implemented.
1822
1823 // if ([!]Pv[.new]) memh(Rx++#s4:1)=Rt.H
1824 // TODO: Needs to be implemented.
1825
1826 // if ([!]Pv[.new]) memh(Rx++#s4:1)=Rt
1827 // if (Pv) memh(Rx++#s4:1)=Rt
1828 // if (Pv.new) memh(Rx++#s4:1)=Rt
1829 let hasCtrlDep = 1,
1830     isPredicated = 1 in
1831 def POST_SThri_cdnPt_V4 : STInst2PI<(outs IntRegs:$dst),
1832             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_1Imm:$offset),
1833             "if ($src1.new) memh($src3++#$offset) = $src2",
1834             [],"$src3 = $dst">,
1835             Requires<[HasV4T]>;
1836
1837 // if (!Pv) memh(Rx++#s4:1)=Rt
1838 // if (!Pv.new) memh(Rx++#s4:1)=Rt
1839 let hasCtrlDep = 1,
1840     isPredicated = 1 in
1841 def POST_SThri_cdnNotPt_V4 : STInst2PI<(outs IntRegs:$dst),
1842             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_1Imm:$offset),
1843             "if (!$src1.new) memh($src3++#$offset) = $src2",
1844             [],"$src3 = $dst">,
1845             Requires<[HasV4T]>;
1846
1847
1848 // Store word.
1849 // memw(Re=#U6)=Rt
1850 // TODO: Needs to be implemented.
1851
1852 // Store predicate:
1853 let neverHasSideEffects = 1 in
1854 def STriw_pred_V4 : STInst2<(outs),
1855             (ins MEMri:$addr, PredRegs:$src1),
1856             "Error; should not emit",
1857             []>,
1858             Requires<[HasV4T]>;
1859
1860 let AddedComplexity = 6 in
1861 def : Pat <(store s8ExtPred:$src2, (i32 IntRegs:$src1)),
1862            (STriw_imm_V4 IntRegs:$src1, 0, s8ExtPred:$src2)>,
1863            Requires<[HasV4T]>;
1864
1865 // memw(Ru<<#u2+#U6)=Rt
1866 let AddedComplexity = 10 in
1867 def STriw_shl_V4 : STInst<(outs),
1868             (ins IntRegs:$src1, u2Imm:$src2, u6Imm:$src3, IntRegs:$src4),
1869             "memw($src1<<#$src2+#$src3) = $src4",
1870             [(store (i32 IntRegs:$src4),
1871                     (add (shl (i32 IntRegs:$src1), u2ImmPred:$src2),
1872                               u6ImmPred:$src3))]>,
1873             Requires<[HasV4T]>;
1874
1875 // memw(Rx++#s4:2)=Rt
1876 // memw(Rx++#s4:2:circ(Mu))=Rt
1877 // memw(Rx++I:circ(Mu))=Rt
1878 // memw(Rx++Mu)=Rt
1879 // memw(Rx++Mu:brev)=Rt
1880 // memw(gp+#u16:2)=Rt
1881
1882
1883 // if ([!]Pv[.new]) memw(Rx++#s4:2)=Rt
1884 // if (Pv) memw(Rx++#s4:2)=Rt
1885 // if (Pv.new) memw(Rx++#s4:2)=Rt
1886 let hasCtrlDep = 1,
1887     isPredicated = 1 in
1888 def POST_STwri_cdnPt_V4 : STInst2PI<(outs IntRegs:$dst),
1889             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset),
1890             "if ($src1.new) memw($src3++#$offset) = $src2",
1891             [],"$src3 = $dst">,
1892             Requires<[HasV4T]>;
1893
1894 // if (!Pv) memw(Rx++#s4:2)=Rt
1895 // if (!Pv.new) memw(Rx++#s4:2)=Rt
1896 let hasCtrlDep = 1,
1897     isPredicated = 1 in
1898 def POST_STwri_cdnNotPt_V4 : STInst2PI<(outs IntRegs:$dst),
1899             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset),
1900             "if (!$src1.new) memw($src3++#$offset) = $src2",
1901             [],"$src3 = $dst">,
1902             Requires<[HasV4T]>;
1903
1904
1905 /// store to global address
1906
1907 let isPredicable = 1, neverHasSideEffects = 1 in
1908 def STrid_GP_V4 : STInst2<(outs),
1909             (ins globaladdress:$global, u16Imm:$offset, DoubleRegs:$src),
1910             "memd(#$global+$offset) = $src",
1911             []>,
1912             Requires<[HasV4T]>;
1913
1914 let neverHasSideEffects = 1, isPredicated = 1 in
1915 def STrid_GP_cPt_V4 : STInst2<(outs),
1916             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
1917                                                         DoubleRegs:$src2),
1918             "if ($src1) memd(##$global+$offset) = $src2",
1919             []>,
1920             Requires<[HasV4T]>;
1921
1922 let neverHasSideEffects = 1, isPredicated = 1 in
1923 def STrid_GP_cNotPt_V4 : STInst2<(outs),
1924             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
1925                                                         DoubleRegs:$src2),
1926             "if (!$src1) memd(##$global+$offset) = $src2",
1927             []>,
1928             Requires<[HasV4T]>;
1929
1930 let neverHasSideEffects = 1, isPredicated = 1 in
1931 def STrid_GP_cdnPt_V4 : STInst2<(outs),
1932             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
1933                                                         DoubleRegs:$src2),
1934             "if ($src1.new) memd(##$global+$offset) = $src2",
1935             []>,
1936             Requires<[HasV4T]>;
1937
1938 let neverHasSideEffects = 1, isPredicated = 1 in
1939 def STrid_GP_cdnNotPt_V4 : STInst2<(outs),
1940             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
1941                                                         DoubleRegs:$src2),
1942             "if (!$src1.new) memd(##$global+$offset) = $src2",
1943             []>,
1944             Requires<[HasV4T]>;
1945
1946 let isPredicable = 1, neverHasSideEffects = 1 in
1947 def STrib_GP_V4 : STInst2<(outs),
1948             (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),
1949             "memb(#$global+$offset) = $src",
1950             []>,
1951             Requires<[HasV4T]>;
1952
1953 let neverHasSideEffects = 1, isPredicated = 1 in
1954 def STrib_GP_cPt_V4 : STInst2<(outs),
1955             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
1956                                                         IntRegs:$src2),
1957             "if ($src1) memb(##$global+$offset) = $src2",
1958             []>,
1959             Requires<[HasV4T]>;
1960
1961 let neverHasSideEffects = 1, isPredicated = 1 in
1962 def STrib_GP_cNotPt_V4 : STInst2<(outs),
1963             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
1964                                                         IntRegs:$src2),
1965             "if (!$src1) memb(##$global+$offset) = $src2",
1966             []>,
1967             Requires<[HasV4T]>;
1968
1969 let neverHasSideEffects = 1, isPredicated = 1 in
1970 def STrib_GP_cdnPt_V4 : STInst2<(outs),
1971             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
1972                                                         IntRegs:$src2),
1973             "if ($src1.new) memb(##$global+$offset) = $src2",
1974             []>,
1975             Requires<[HasV4T]>;
1976
1977 let neverHasSideEffects = 1, isPredicated = 1 in
1978 def STrib_GP_cdnNotPt_V4 : STInst2<(outs),
1979             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
1980                                                         IntRegs:$src2),
1981             "if (!$src1.new) memb(##$global+$offset) = $src2",
1982             []>,
1983             Requires<[HasV4T]>;
1984
1985 let isPredicable = 1, neverHasSideEffects = 1 in
1986 def STrih_GP_V4 : STInst2<(outs),
1987             (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),
1988             "memh(#$global+$offset) = $src",
1989             []>,
1990             Requires<[HasV4T]>;
1991
1992 let neverHasSideEffects = 1, isPredicated = 1 in
1993 def STrih_GP_cPt_V4 : STInst2<(outs),
1994             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
1995                                                         IntRegs:$src2),
1996             "if ($src1) memh(##$global+$offset) = $src2",
1997             []>,
1998             Requires<[HasV4T]>;
1999
2000 let neverHasSideEffects = 1, isPredicated = 1 in
2001 def STrih_GP_cNotPt_V4 : STInst2<(outs),
2002             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2003                                                         IntRegs:$src2),
2004             "if (!$src1) memh(##$global+$offset) = $src2",
2005             []>,
2006             Requires<[HasV4T]>;
2007
2008 let neverHasSideEffects = 1, isPredicated = 1 in
2009 def STrih_GP_cdnPt_V4 : STInst2<(outs),
2010             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2011                                                         IntRegs:$src2),
2012             "if ($src1.new) memh(##$global+$offset) = $src2",
2013             []>,
2014             Requires<[HasV4T]>;
2015
2016 let neverHasSideEffects = 1, isPredicated = 1 in
2017 def STrih_GP_cdnNotPt_V4 : STInst2<(outs),
2018             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2019                                                         IntRegs:$src2),
2020             "if (!$src1.new) memh(##$global+$offset) = $src2",
2021             []>,
2022             Requires<[HasV4T]>;
2023
2024 let isPredicable = 1, neverHasSideEffects = 1 in
2025 def STriw_GP_V4 : STInst2<(outs),
2026             (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),
2027             "memw(#$global+$offset) = $src",
2028             []>,
2029             Requires<[HasV4T]>;
2030
2031 let neverHasSideEffects = 1, isPredicated = 1 in
2032 def STriw_GP_cPt_V4 : STInst2<(outs),
2033             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2034                                                         IntRegs:$src2),
2035             "if ($src1) memw(##$global+$offset) = $src2",
2036             []>,
2037             Requires<[HasV4T]>;
2038
2039 let neverHasSideEffects = 1, isPredicated = 1 in
2040 def STriw_GP_cNotPt_V4 : STInst2<(outs),
2041             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2042                                                         IntRegs:$src2),
2043             "if (!$src1) memw(##$global+$offset) = $src2",
2044             []>,
2045             Requires<[HasV4T]>;
2046
2047 let neverHasSideEffects = 1, isPredicated = 1 in
2048 def STriw_GP_cdnPt_V4 : STInst2<(outs),
2049             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2050                                                         IntRegs:$src2),
2051             "if ($src1.new) memw(##$global+$offset) = $src2",
2052             []>,
2053             Requires<[HasV4T]>;
2054
2055 let neverHasSideEffects = 1, isPredicated = 1 in
2056 def STriw_GP_cdnNotPt_V4 : STInst2<(outs),
2057             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2058                                                         IntRegs:$src2),
2059             "if (!$src1.new) memw(##$global+$offset) = $src2",
2060             []>,
2061             Requires<[HasV4T]>;
2062
2063 // memd(#global)=Rtt
2064 let isPredicable = 1, neverHasSideEffects = 1 in
2065 def STd_GP_V4 : STInst2<(outs),
2066             (ins globaladdress:$global, DoubleRegs:$src),
2067             "memd(#$global) = $src",
2068             []>,
2069             Requires<[HasV4T]>;
2070
2071 // if (Pv) memd(##global) = Rtt
2072 let neverHasSideEffects = 1, isPredicated = 1 in
2073 def STd_GP_cPt_V4 : STInst2<(outs),
2074             (ins PredRegs:$src1, globaladdress:$global, DoubleRegs:$src2),
2075             "if ($src1) memd(##$global) = $src2",
2076             []>,
2077             Requires<[HasV4T]>;
2078
2079 // if (!Pv) memd(##global) = Rtt
2080 let neverHasSideEffects = 1, isPredicated = 1 in
2081 def STd_GP_cNotPt_V4 : STInst2<(outs),
2082             (ins PredRegs:$src1, globaladdress:$global, DoubleRegs:$src2),
2083             "if (!$src1) memd(##$global) = $src2",
2084             []>,
2085               Requires<[HasV4T]>;
2086
2087 // if (Pv) memd(##global) = Rtt
2088 let neverHasSideEffects = 1, isPredicated = 1 in
2089 def STd_GP_cdnPt_V4 : STInst2<(outs),
2090             (ins PredRegs:$src1, globaladdress:$global, DoubleRegs:$src2),
2091             "if ($src1.new) memd(##$global) = $src2",
2092             []>,
2093               Requires<[HasV4T]>;
2094
2095 // if (!Pv) memd(##global) = Rtt
2096 let neverHasSideEffects = 1, isPredicated = 1 in
2097 def STd_GP_cdnNotPt_V4 : STInst2<(outs),
2098             (ins PredRegs:$src1, globaladdress:$global, DoubleRegs:$src2),
2099             "if (!$src1.new) memd(##$global) = $src2",
2100             []>,
2101             Requires<[HasV4T]>;
2102
2103 // memb(#global)=Rt
2104 let isPredicable = 1, neverHasSideEffects = 1 in
2105 def STb_GP_V4 : STInst2<(outs),
2106             (ins globaladdress:$global, IntRegs:$src),
2107             "memb(#$global) = $src",
2108             []>,
2109             Requires<[HasV4T]>;
2110
2111 // if (Pv) memb(##global) = Rt
2112 let neverHasSideEffects = 1, isPredicated = 1 in
2113 def STb_GP_cPt_V4 : STInst2<(outs),
2114             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2115             "if ($src1) memb(##$global) = $src2",
2116               []>,
2117               Requires<[HasV4T]>;
2118
2119 // if (!Pv) memb(##global) = Rt
2120 let neverHasSideEffects = 1, isPredicated = 1 in
2121 def STb_GP_cNotPt_V4 : STInst2<(outs),
2122             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2123             "if (!$src1) memb(##$global) = $src2",
2124               []>,
2125               Requires<[HasV4T]>;
2126
2127 // if (Pv) memb(##global) = Rt
2128 let neverHasSideEffects = 1, isPredicated = 1 in
2129 def STb_GP_cdnPt_V4 : STInst2<(outs),
2130             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2131             "if ($src1.new) memb(##$global) = $src2",
2132               []>,
2133               Requires<[HasV4T]>;
2134
2135 // if (!Pv) memb(##global) = Rt
2136 let neverHasSideEffects = 1, isPredicated = 1 in
2137 def STb_GP_cdnNotPt_V4 : STInst2<(outs),
2138             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2139             "if (!$src1.new) memb(##$global) = $src2",
2140               []>,
2141               Requires<[HasV4T]>;
2142
2143 // memh(#global)=Rt
2144 let isPredicable = 1, neverHasSideEffects = 1 in
2145 def STh_GP_V4 : STInst2<(outs),
2146             (ins globaladdress:$global, IntRegs:$src),
2147             "memh(#$global) = $src",
2148             []>,
2149             Requires<[HasV4T]>;
2150
2151 // if (Pv) memh(##global) = Rt
2152 let neverHasSideEffects = 1, isPredicated = 1 in
2153 def STh_GP_cPt_V4 : STInst2<(outs),
2154             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2155             "if ($src1) memh(##$global) = $src2",
2156               []>,
2157               Requires<[HasV4T]>;
2158
2159 // if (!Pv) memh(##global) = Rt
2160 let neverHasSideEffects = 1, isPredicated = 1 in
2161 def STh_GP_cNotPt_V4 : STInst2<(outs),
2162             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2163             "if (!$src1) memh(##$global) = $src2",
2164               []>,
2165               Requires<[HasV4T]>;
2166
2167 // if (Pv) memh(##global) = Rt
2168 let neverHasSideEffects = 1, isPredicated = 1 in
2169 def STh_GP_cdnPt_V4 : STInst2<(outs),
2170             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2171             "if ($src1.new) memh(##$global) = $src2",
2172               []>,
2173               Requires<[HasV4T]>;
2174
2175 // if (!Pv) memh(##global) = Rt
2176 let neverHasSideEffects = 1, isPredicated = 1 in
2177 def STh_GP_cdnNotPt_V4 : STInst2<(outs),
2178             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2179             "if (!$src1.new) memh(##$global) = $src2",
2180               []>,
2181               Requires<[HasV4T]>;
2182
2183 // memw(#global)=Rt
2184 let isPredicable = 1, neverHasSideEffects = 1 in
2185 def STw_GP_V4 : STInst2<(outs),
2186             (ins globaladdress:$global, IntRegs:$src),
2187             "memw(#$global) = $src",
2188               []>,
2189               Requires<[HasV4T]>;
2190
2191 // if (Pv) memw(##global) = Rt
2192 let neverHasSideEffects = 1, isPredicated = 1 in
2193 def STw_GP_cPt_V4 : STInst2<(outs),
2194             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2195             "if ($src1) memw(##$global) = $src2",
2196               []>,
2197               Requires<[HasV4T]>;
2198
2199 // if (!Pv) memw(##global) = Rt
2200 let neverHasSideEffects = 1, isPredicated = 1 in
2201 def STw_GP_cNotPt_V4 : STInst2<(outs),
2202             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2203             "if (!$src1) memw(##$global) = $src2",
2204               []>,
2205               Requires<[HasV4T]>;
2206
2207 // if (Pv) memw(##global) = Rt
2208 let neverHasSideEffects = 1, isPredicated = 1 in
2209 def STw_GP_cdnPt_V4 : STInst2<(outs),
2210             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2211             "if ($src1.new) memw(##$global) = $src2",
2212               []>,
2213               Requires<[HasV4T]>;
2214
2215 // if (!Pv) memw(##global) = Rt
2216 let neverHasSideEffects = 1, isPredicated = 1 in
2217 def STw_GP_cdnNotPt_V4 : STInst2<(outs),
2218             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2219             "if (!$src1.new) memw(##$global) = $src2",
2220             []>,
2221               Requires<[HasV4T]>;
2222
2223 // 64 bit atomic store
2224 def : Pat <(atomic_store_64 (HexagonCONST32_GP tglobaladdr:$global),
2225                             (i64 DoubleRegs:$src1)),
2226            (STd_GP_V4 tglobaladdr:$global, (i64 DoubleRegs:$src1))>,
2227            Requires<[HasV4T]>;
2228
2229 // Map from store(globaladdress) -> memd(#foo)
2230 let AddedComplexity = 100 in
2231 def : Pat <(store (i64 DoubleRegs:$src1),
2232                   (HexagonCONST32_GP tglobaladdr:$global)),
2233            (STd_GP_V4 tglobaladdr:$global, (i64 DoubleRegs:$src1))>,
2234            Requires<[HasV4T]>;
2235
2236 // 8 bit atomic store
2237 def : Pat < (atomic_store_8 (HexagonCONST32_GP tglobaladdr:$global),
2238                             (i32 IntRegs:$src1)),
2239             (STb_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>,
2240               Requires<[HasV4T]>;
2241
2242 // Map from store(globaladdress) -> memb(#foo)
2243 let AddedComplexity = 100 in
2244 def : Pat<(truncstorei8 (i32 IntRegs:$src1),
2245           (HexagonCONST32_GP tglobaladdr:$global)),
2246           (STb_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>,
2247           Requires<[HasV4T]>;
2248
2249 // Map from "i1 = constant<-1>; memw(CONST32(#foo)) = i1"
2250 //       to "r0 = 1; memw(#foo) = r0"
2251 let AddedComplexity = 100 in
2252 def : Pat<(store (i1 -1), (HexagonCONST32_GP tglobaladdr:$global)),
2253           (STb_GP_V4 tglobaladdr:$global, (TFRI 1))>,
2254           Requires<[HasV4T]>;
2255
2256 def : Pat<(atomic_store_16 (HexagonCONST32_GP tglobaladdr:$global),
2257                            (i32 IntRegs:$src1)),
2258           (STh_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>,
2259           Requires<[HasV4T]>;
2260
2261 // Map from store(globaladdress) -> memh(#foo)
2262 let AddedComplexity = 100 in
2263 def : Pat<(truncstorei16 (i32 IntRegs:$src1),
2264                          (HexagonCONST32_GP tglobaladdr:$global)),
2265           (STh_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>,
2266           Requires<[HasV4T]>;
2267
2268 // 32 bit atomic store
2269 def : Pat<(atomic_store_32 (HexagonCONST32_GP tglobaladdr:$global),
2270                            (i32 IntRegs:$src1)),
2271           (STw_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>,
2272           Requires<[HasV4T]>;
2273
2274 // Map from store(globaladdress) -> memw(#foo)
2275 let AddedComplexity = 100 in
2276 def : Pat<(store (i32 IntRegs:$src1), (HexagonCONST32_GP tglobaladdr:$global)),
2277           (STw_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>,
2278           Requires<[HasV4T]>;
2279
2280 def : Pat<(atomic_store_64 (add (HexagonCONST32_GP tglobaladdr:$global),
2281                                 u16ImmPred:$offset),
2282                            (i64 DoubleRegs:$src1)),
2283           (STrid_GP_V4 tglobaladdr:$global, u16ImmPred:$offset,
2284                                             (i64 DoubleRegs:$src1))>,
2285           Requires<[HasV4T]>;
2286
2287 def : Pat<(atomic_store_32 (add (HexagonCONST32_GP tglobaladdr:$global),
2288                                 u16ImmPred:$offset),
2289                            (i32 IntRegs:$src1)),
2290           (STriw_GP_V4 tglobaladdr:$global, u16ImmPred:$offset,
2291                                             (i32 IntRegs:$src1))>,
2292           Requires<[HasV4T]>;
2293
2294 def : Pat<(atomic_store_16 (add (HexagonCONST32_GP tglobaladdr:$global),
2295                                 u16ImmPred:$offset),
2296                            (i32 IntRegs:$src1)),
2297           (STrih_GP_V4 tglobaladdr:$global, u16ImmPred:$offset,
2298                                             (i32 IntRegs:$src1))>,
2299           Requires<[HasV4T]>;
2300
2301 def : Pat<(atomic_store_8 (add (HexagonCONST32_GP tglobaladdr:$global),
2302                                u16ImmPred:$offset),
2303                           (i32 IntRegs:$src1)),
2304           (STrib_GP_V4 tglobaladdr:$global, u16ImmPred:$offset,
2305                                             (i32 IntRegs:$src1))>,
2306           Requires<[HasV4T]>;
2307
2308 // Map from store(globaladdress + x) -> memd(#foo + x)
2309 let AddedComplexity = 100 in
2310 def : Pat<(store (i64 DoubleRegs:$src1),
2311                     (add (HexagonCONST32_GP tglobaladdr:$global),
2312                                         u16ImmPred:$offset)),
2313           (STrid_GP_V4 tglobaladdr:$global, u16ImmPred:$offset,
2314                                             (i64 DoubleRegs:$src1))>,
2315           Requires<[HasV4T]>;
2316
2317 // Map from store(globaladdress + x) -> memb(#foo + x)
2318 let AddedComplexity = 100 in
2319 def : Pat<(truncstorei8 (i32 IntRegs:$src1),
2320                         (add (HexagonCONST32_GP tglobaladdr:$global),
2321                              u16ImmPred:$offset)),
2322           (STrib_GP_V4 tglobaladdr:$global, u16ImmPred:$offset,
2323                                             (i32 IntRegs:$src1))>,
2324           Requires<[HasV4T]>;
2325
2326 // Map from store(globaladdress + x) -> memh(#foo + x)
2327 let AddedComplexity = 100 in
2328 def : Pat<(truncstorei16 (i32 IntRegs:$src1),
2329                          (add (HexagonCONST32_GP tglobaladdr:$global),
2330                               u16ImmPred:$offset)),
2331           (STrih_GP_V4 tglobaladdr:$global, u16ImmPred:$offset,
2332                                             (i32 IntRegs:$src1))>,
2333           Requires<[HasV4T]>;
2334
2335 // Map from store(globaladdress + x) -> memw(#foo + x)
2336 let AddedComplexity = 100 in
2337 def : Pat<(store (i32 IntRegs:$src1),
2338                  (add (HexagonCONST32_GP tglobaladdr:$global),
2339                                 u16ImmPred:$offset)),
2340           (STriw_GP_V4 tglobaladdr:$global, u16ImmPred:$offset,
2341                                             (i32 IntRegs:$src1))>,
2342           Requires<[HasV4T]>;
2343
2344
2345
2346 //===----------------------------------------------------------------------===
2347 // ST -
2348 //===----------------------------------------------------------------------===
2349
2350
2351 //===----------------------------------------------------------------------===//
2352 // NV/ST +
2353 //===----------------------------------------------------------------------===//
2354
2355 // multiclass for new-value store instructions with base + immediate offset.
2356 //
2357 multiclass ST_Idxd_Pbase_nv<string mnemonic, RegisterClass RC,
2358                             Operand predImmOp, bit isNot, bit isPredNew> {
2359   let PNewValue = #!if(isPredNew, "new", "") in
2360   def #NAME#_nv_V4 : NVInst_V4<(outs),
2361             (ins PredRegs:$src1, IntRegs:$src2, predImmOp:$src3, RC: $src4),
2362             !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
2363             ") ")#mnemonic#"($src2+#$src3) = $src4.new",
2364             []>,
2365             Requires<[HasV4T]>;
2366 }
2367
2368 multiclass ST_Idxd_Pred_nv<string mnemonic, RegisterClass RC, Operand predImmOp,
2369                            bit PredNot> {
2370   let PredSense = #!if(PredNot, "false", "true") in {
2371     defm _c#NAME# : ST_Idxd_Pbase_nv<mnemonic, RC, predImmOp, PredNot, 0>;
2372     // Predicate new
2373     defm _cdn#NAME# : ST_Idxd_Pbase_nv<mnemonic, RC, predImmOp, PredNot, 1>;
2374   }
2375 }
2376
2377 let mayStore = 1, isNVStore = 1, neverHasSideEffects = 1, isExtendable = 1 in
2378 multiclass ST_Idxd_nv<string mnemonic, string CextOp, RegisterClass RC,
2379                    Operand ImmOp, Operand predImmOp, bits<5> ImmBits,
2380                    bits<5> PredImmBits> {
2381
2382   let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed in {
2383     let opExtendable = 1, isExtentSigned = 1, opExtentBits = ImmBits,
2384     isPredicable = 1 in
2385     def #NAME#_nv_V4 : NVInst_V4<(outs),
2386             (ins IntRegs:$src1, ImmOp:$src2, RC:$src3),
2387             #mnemonic#"($src1+#$src2) = $src3.new",
2388             []>,
2389             Requires<[HasV4T]>;
2390
2391     let opExtendable = 2, isExtentSigned = 0, opExtentBits = PredImmBits,
2392     isPredicated = 1 in {
2393       defm Pt : ST_Idxd_Pred_nv<mnemonic, RC, predImmOp, 0>;
2394       defm NotPt : ST_Idxd_Pred_nv<mnemonic, RC, predImmOp, 1>;
2395     }
2396   }
2397 }
2398
2399 let addrMode = BaseImmOffset, validSubTargets = HasV4SubT in {
2400   defm STrib_indexed: ST_Idxd_nv<"memb", "STrib", IntRegs, s11_0Ext,
2401                                  u6_0Ext, 11, 6>, AddrModeRel;
2402   defm STrih_indexed: ST_Idxd_nv<"memh", "STrih", IntRegs, s11_1Ext,
2403                                  u6_1Ext, 12, 7>, AddrModeRel;
2404   defm STriw_indexed: ST_Idxd_nv<"memw", "STriw", IntRegs, s11_2Ext,
2405                                  u6_2Ext, 13, 8>, AddrModeRel;
2406 }
2407
2408 // multiclass for new-value store instructions with base + immediate offset.
2409 // and MEMri operand.
2410 multiclass ST_MEMri_Pbase_nv<string mnemonic, RegisterClass RC, bit isNot,
2411                           bit isPredNew> {
2412   let PNewValue = #!if(isPredNew, "new", "") in
2413   def #NAME#_nv_V4 : NVInst_V4<(outs),
2414             (ins PredRegs:$src1, MEMri:$addr, RC: $src2),
2415             !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
2416             ") ")#mnemonic#"($addr) = $src2.new",
2417             []>,
2418             Requires<[HasV4T]>;
2419 }
2420
2421 multiclass ST_MEMri_Pred_nv<string mnemonic, RegisterClass RC, bit PredNot> {
2422   let PredSense = #!if(PredNot, "false", "true") in {
2423     defm _c#NAME# : ST_MEMri_Pbase_nv<mnemonic, RC, PredNot, 0>;
2424
2425     // Predicate new
2426     defm _cdn#NAME# : ST_MEMri_Pbase_nv<mnemonic, RC, PredNot, 1>;
2427   }
2428 }
2429
2430 let mayStore = 1, isNVStore = 1, isExtendable = 1, neverHasSideEffects = 1 in
2431 multiclass ST_MEMri_nv<string mnemonic, string CextOp, RegisterClass RC,
2432                     bits<5> ImmBits, bits<5> PredImmBits> {
2433
2434   let CextOpcode = CextOp, BaseOpcode = CextOp in {
2435     let opExtendable = 1, isExtentSigned = 1, opExtentBits = ImmBits,
2436          isPredicable = 1 in
2437     def #NAME#_nv_V4 : NVInst_V4<(outs),
2438             (ins MEMri:$addr, RC:$src),
2439             #mnemonic#"($addr) = $src.new",
2440             []>,
2441             Requires<[HasV4T]>;
2442
2443     let opExtendable = 2, isExtentSigned = 0, opExtentBits = PredImmBits,
2444         neverHasSideEffects = 1, isPredicated = 1 in {
2445       defm Pt : ST_MEMri_Pred_nv<mnemonic, RC, 0>;
2446       defm NotPt : ST_MEMri_Pred_nv<mnemonic, RC, 1>;
2447     }
2448   }
2449 }
2450
2451 let addrMode = BaseImmOffset, isMEMri = "true", validSubTargets = HasV4SubT,
2452 mayStore = 1 in {
2453   defm STrib: ST_MEMri_nv<"memb", "STrib", IntRegs, 11, 6>, AddrModeRel;
2454   defm STrih: ST_MEMri_nv<"memh", "STrih", IntRegs, 12, 7>, AddrModeRel;
2455   defm STriw: ST_MEMri_nv<"memw", "STriw", IntRegs, 13, 8>, AddrModeRel;
2456 }
2457
2458 // memb(Ru<<#u2+#U6)=Nt.new
2459 let mayStore = 1, AddedComplexity = 10 in
2460 def STrib_shl_nv_V4 : NVInst_V4<(outs),
2461             (ins IntRegs:$src1, u2Imm:$src2, u6Imm:$src3, IntRegs:$src4),
2462             "memb($src1<<#$src2+#$src3) = $src4.new",
2463             []>,
2464             Requires<[HasV4T]>;
2465
2466 // memb(Rx++#s4:0)=Nt.new
2467 let mayStore = 1, hasCtrlDep = 1, isPredicable = 1  in
2468 def POST_STbri_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
2469             (ins IntRegs:$src1, IntRegs:$src2, s4_0Imm:$offset),
2470             "memb($src2++#$offset) = $src1.new",
2471             [],
2472             "$src2 = $dst">,
2473             Requires<[HasV4T]>;
2474
2475 // memb(Rx++#s4:0:circ(Mu))=Nt.new
2476 // memb(Rx++I:circ(Mu))=Nt.new
2477 // memb(Rx++Mu)=Nt.new
2478 // memb(Rx++Mu:brev)=Nt.new
2479
2480 // memb(gp+#u16:0)=Nt.new
2481 let mayStore = 1, neverHasSideEffects = 1 in
2482 def STrib_GP_nv_V4 : NVInst_V4<(outs),
2483             (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),
2484             "memb(#$global+$offset) = $src.new",
2485             []>,
2486             Requires<[HasV4T]>;
2487
2488 // memb(#global)=Nt.new
2489 let mayStore = 1, neverHasSideEffects = 1 in
2490 def STb_GP_nv_V4 : NVInst_V4<(outs),
2491             (ins globaladdress:$global, IntRegs:$src),
2492             "memb(#$global) = $src.new",
2493             []>,
2494             Requires<[HasV4T]>;
2495
2496 // if ([!]Pv[.new]) memb(Rx++#s4:0)=Nt.new
2497 // if (Pv) memb(Rx++#s4:0)=Nt.new
2498 let mayStore = 1, hasCtrlDep = 1,
2499     isPredicated = 1 in
2500 def POST_STbri_cPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
2501             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_0Imm:$offset),
2502             "if ($src1) memb($src3++#$offset) = $src2.new",
2503             [],"$src3 = $dst">,
2504             Requires<[HasV4T]>;
2505
2506 // if (Pv.new) memb(Rx++#s4:0)=Nt.new
2507 let mayStore = 1, hasCtrlDep = 1,
2508     isPredicated = 1 in
2509 def POST_STbri_cdnPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
2510             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_0Imm:$offset),
2511             "if ($src1.new) memb($src3++#$offset) = $src2.new",
2512             [],"$src3 = $dst">,
2513             Requires<[HasV4T]>;
2514
2515 // if (!Pv) memb(Rx++#s4:0)=Nt.new
2516 let mayStore = 1, hasCtrlDep = 1,
2517     isPredicated = 1 in
2518 def POST_STbri_cNotPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
2519             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_0Imm:$offset),
2520             "if (!$src1) memb($src3++#$offset) = $src2.new",
2521             [],"$src3 = $dst">,
2522             Requires<[HasV4T]>;
2523
2524 // if (!Pv.new) memb(Rx++#s4:0)=Nt.new
2525 let mayStore = 1, hasCtrlDep = 1,
2526     isPredicated = 1 in
2527 def POST_STbri_cdnNotPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
2528             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_0Imm:$offset),
2529             "if (!$src1.new) memb($src3++#$offset) = $src2.new",
2530             [],"$src3 = $dst">,
2531             Requires<[HasV4T]>;
2532
2533 // memh(Ru<<#u2+#U6)=Nt.new
2534 let mayStore = 1, AddedComplexity = 10 in
2535 def STrih_shl_nv_V4 : NVInst_V4<(outs),
2536             (ins IntRegs:$src1, u2Imm:$src2, u6Imm:$src3, IntRegs:$src4),
2537             "memh($src1<<#$src2+#$src3) = $src4.new",
2538             []>,
2539             Requires<[HasV4T]>;
2540
2541 // memh(Rx++#s4:1)=Nt.new
2542 let mayStore = 1, hasCtrlDep = 1, isPredicable = 1  in
2543 def POST_SThri_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
2544             (ins IntRegs:$src1, IntRegs:$src2, s4_1Imm:$offset),
2545             "memh($src2++#$offset) = $src1.new",
2546             [],
2547             "$src2 = $dst">,
2548             Requires<[HasV4T]>;
2549
2550 // memh(Rx++#s4:1:circ(Mu))=Nt.new
2551 // memh(Rx++I:circ(Mu))=Nt.new
2552 // memh(Rx++Mu)=Nt.new
2553 // memh(Rx++Mu:brev)=Nt.new
2554
2555 // memh(gp+#u16:1)=Nt.new
2556 let mayStore = 1, neverHasSideEffects = 1 in
2557 def STrih_GP_nv_V4 : NVInst_V4<(outs),
2558             (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),
2559             "memh(#$global+$offset) = $src.new",
2560             []>,
2561             Requires<[HasV4T]>;
2562
2563 // memh(#global)=Nt.new
2564 let mayStore = 1, neverHasSideEffects = 1 in
2565 def STh_GP_nv_V4 : NVInst_V4<(outs),
2566             (ins globaladdress:$global, IntRegs:$src),
2567             "memh(#$global) = $src.new",
2568             []>,
2569             Requires<[HasV4T]>;
2570
2571
2572 // if ([!]Pv[]) memh(Rx++#s4:1)=Nt.new
2573 // if (Pv) memh(Rx++#s4:1)=Nt.new
2574 let mayStore = 1, hasCtrlDep = 1,
2575     isPredicated = 1 in
2576 def POST_SThri_cPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
2577             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_1Imm:$offset),
2578             "if ($src1) memh($src3++#$offset) = $src2.new",
2579             [],"$src3 = $dst">,
2580             Requires<[HasV4T]>;
2581
2582 // if (Pv.new) memh(Rx++#s4:1)=Nt.new
2583 let mayStore = 1, hasCtrlDep = 1,
2584     isPredicated = 1 in
2585 def POST_SThri_cdnPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
2586             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_1Imm:$offset),
2587             "if ($src1.new) memh($src3++#$offset) = $src2.new",
2588             [],"$src3 = $dst">,
2589             Requires<[HasV4T]>;
2590
2591 // if (!Pv) memh(Rx++#s4:1)=Nt.new
2592 let mayStore = 1, hasCtrlDep = 1,
2593     isPredicated = 1 in
2594 def POST_SThri_cNotPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
2595             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_1Imm:$offset),
2596             "if (!$src1) memh($src3++#$offset) = $src2.new",
2597             [],"$src3 = $dst">,
2598             Requires<[HasV4T]>;
2599
2600 // if (!Pv.new) memh(Rx++#s4:1)=Nt.new
2601 let mayStore = 1, hasCtrlDep = 1,
2602     isPredicated = 1 in
2603 def POST_SThri_cdnNotPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
2604             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_1Imm:$offset),
2605             "if (!$src1.new) memh($src3++#$offset) = $src2.new",
2606             [],"$src3 = $dst">,
2607             Requires<[HasV4T]>;
2608
2609 // memw(Ru<<#u2+#U6)=Nt.new
2610 let mayStore = 1, AddedComplexity = 10 in
2611 def STriw_shl_nv_V4 : NVInst_V4<(outs),
2612             (ins IntRegs:$src1, u2Imm:$src2, u6Imm:$src3, IntRegs:$src4),
2613             "memw($src1<<#$src2+#$src3) = $src4.new",
2614             []>,
2615             Requires<[HasV4T]>;
2616
2617 // memw(Rx++#s4:2)=Nt.new
2618 let mayStore = 1, hasCtrlDep = 1, isPredicable = 1  in
2619 def POST_STwri_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
2620             (ins IntRegs:$src1, IntRegs:$src2, s4_2Imm:$offset),
2621             "memw($src2++#$offset) = $src1.new",
2622             [],
2623             "$src2 = $dst">,
2624             Requires<[HasV4T]>;
2625
2626 // memw(Rx++#s4:2:circ(Mu))=Nt.new
2627 // memw(Rx++I:circ(Mu))=Nt.new
2628 // memw(Rx++Mu)=Nt.new
2629 // memw(Rx++Mu:brev)=Nt.new
2630 // memw(gp+#u16:2)=Nt.new
2631 let mayStore = 1, neverHasSideEffects = 1 in
2632 def STriw_GP_nv_V4 : NVInst_V4<(outs),
2633             (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),
2634             "memw(#$global+$offset) = $src.new",
2635             []>,
2636             Requires<[HasV4T]>;
2637
2638 let mayStore = 1, neverHasSideEffects = 1 in
2639 def STw_GP_nv_V4 : NVInst_V4<(outs),
2640             (ins globaladdress:$global, IntRegs:$src),
2641             "memw(#$global) = $src.new",
2642             []>,
2643             Requires<[HasV4T]>;
2644
2645 // if ([!]Pv[.new]) memw(Rx++#s4:2)=Nt.new
2646 // if (Pv) memw(Rx++#s4:2)=Nt.new
2647 let mayStore = 1, hasCtrlDep = 1,
2648     isPredicated = 1 in
2649 def POST_STwri_cPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
2650             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset),
2651             "if ($src1) memw($src3++#$offset) = $src2.new",
2652             [],"$src3 = $dst">,
2653             Requires<[HasV4T]>;
2654
2655 // if (Pv.new) memw(Rx++#s4:2)=Nt.new
2656 let mayStore = 1, hasCtrlDep = 1,
2657     isPredicated = 1 in
2658 def POST_STwri_cdnPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
2659             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset),
2660             "if ($src1.new) memw($src3++#$offset) = $src2.new",
2661             [],"$src3 = $dst">,
2662             Requires<[HasV4T]>;
2663
2664 // if (!Pv) memw(Rx++#s4:2)=Nt.new
2665 let mayStore = 1, hasCtrlDep = 1,
2666     isPredicated = 1 in
2667 def POST_STwri_cNotPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
2668             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset),
2669             "if (!$src1) memw($src3++#$offset) = $src2.new",
2670             [],"$src3 = $dst">,
2671             Requires<[HasV4T]>;
2672
2673 // if (!Pv.new) memw(Rx++#s4:2)=Nt.new
2674 let mayStore = 1, hasCtrlDep = 1,
2675     isPredicated = 1 in
2676 def POST_STwri_cdnNotPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
2677             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset),
2678             "if (!$src1.new) memw($src3++#$offset) = $src2.new",
2679             [],"$src3 = $dst">,
2680             Requires<[HasV4T]>;
2681
2682
2683
2684 // if (Pv) memb(##global) = Rt
2685 let mayStore = 1, neverHasSideEffects = 1 in
2686 def STb_GP_cPt_nv_V4 : NVInst_V4<(outs),
2687             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2688             "if ($src1) memb(##$global) = $src2.new",
2689             []>,
2690             Requires<[HasV4T]>;
2691
2692 // if (!Pv) memb(##global) = Rt
2693 let mayStore = 1, neverHasSideEffects = 1 in
2694 def STb_GP_cNotPt_nv_V4 : NVInst_V4<(outs),
2695             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2696             "if (!$src1) memb(##$global) = $src2.new",
2697             []>,
2698             Requires<[HasV4T]>;
2699
2700 // if (Pv) memb(##global) = Rt
2701 let mayStore = 1, neverHasSideEffects = 1 in
2702 def STb_GP_cdnPt_nv_V4 : NVInst_V4<(outs),
2703             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2704             "if ($src1.new) memb(##$global) = $src2.new",
2705             []>,
2706             Requires<[HasV4T]>;
2707
2708 // if (!Pv) memb(##global) = Rt
2709 let mayStore = 1, neverHasSideEffects = 1 in
2710 def STb_GP_cdnNotPt_nv_V4 : NVInst_V4<(outs),
2711             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2712             "if (!$src1.new) memb(##$global) = $src2.new",
2713             []>,
2714             Requires<[HasV4T]>;
2715
2716 // if (Pv) memh(##global) = Rt
2717 let mayStore = 1, neverHasSideEffects = 1 in
2718 def STh_GP_cPt_nv_V4 : NVInst_V4<(outs),
2719             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2720             "if ($src1) memh(##$global) = $src2.new",
2721             []>,
2722             Requires<[HasV4T]>;
2723
2724 // if (!Pv) memh(##global) = Rt
2725 let mayStore = 1, neverHasSideEffects = 1 in
2726 def STh_GP_cNotPt_nv_V4 : NVInst_V4<(outs),
2727             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2728             "if (!$src1) memh(##$global) = $src2.new",
2729             []>,
2730             Requires<[HasV4T]>;
2731
2732 // if (Pv) memh(##global) = Rt
2733 let mayStore = 1, neverHasSideEffects = 1 in
2734 def STh_GP_cdnPt_nv_V4 : NVInst_V4<(outs),
2735             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2736             "if ($src1.new) memh(##$global) = $src2.new",
2737             []>,
2738             Requires<[HasV4T]>;
2739
2740 // if (!Pv) memh(##global) = Rt
2741 let mayStore = 1, neverHasSideEffects = 1 in
2742 def STh_GP_cdnNotPt_nv_V4 : NVInst_V4<(outs),
2743             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2744             "if (!$src1.new) memh(##$global) = $src2.new",
2745             []>,
2746             Requires<[HasV4T]>;
2747
2748 // if (Pv) memw(##global) = Rt
2749 let mayStore = 1, neverHasSideEffects = 1 in
2750 def STw_GP_cPt_nv_V4 : NVInst_V4<(outs),
2751             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2752             "if ($src1) memw(##$global) = $src2.new",
2753             []>,
2754             Requires<[HasV4T]>;
2755
2756 // if (!Pv) memw(##global) = Rt
2757 let mayStore = 1, neverHasSideEffects = 1 in
2758 def STw_GP_cNotPt_nv_V4 : NVInst_V4<(outs),
2759             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2760             "if (!$src1) memw(##$global) = $src2.new",
2761             []>,
2762             Requires<[HasV4T]>;
2763
2764 // if (Pv) memw(##global) = Rt
2765 let mayStore = 1, neverHasSideEffects = 1 in
2766 def STw_GP_cdnPt_nv_V4 : NVInst_V4<(outs),
2767             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2768             "if ($src1.new) memw(##$global) = $src2.new",
2769             []>,
2770             Requires<[HasV4T]>;
2771
2772 // if (!Pv) memw(##global) = Rt
2773 let mayStore = 1, neverHasSideEffects = 1 in
2774 def STw_GP_cdnNotPt_nv_V4 : NVInst_V4<(outs),
2775             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2776             "if (!$src1.new) memw(##$global) = $src2.new",
2777             []>,
2778             Requires<[HasV4T]>;
2779
2780 let mayStore = 1, neverHasSideEffects = 1 in
2781 def STrib_GP_cPt_nv_V4 : NVInst_V4<(outs),
2782             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2783                                                         IntRegs:$src2),
2784             "if ($src1) memb(##$global+$offset) = $src2.new",
2785             []>,
2786             Requires<[HasV4T]>;
2787
2788 let mayStore = 1, neverHasSideEffects = 1 in
2789 def STrib_GP_cNotPt_nv_V4 : NVInst_V4<(outs),
2790             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2791                                                         IntRegs:$src2),
2792             "if (!$src1) memb(##$global+$offset) = $src2.new",
2793             []>,
2794             Requires<[HasV4T]>;
2795
2796 let mayStore = 1, neverHasSideEffects = 1 in
2797 def STrib_GP_cdnPt_nv_V4 : NVInst_V4<(outs),
2798             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2799                                                         IntRegs:$src2),
2800             "if ($src1.new) memb(##$global+$offset) = $src2.new",
2801             []>,
2802             Requires<[HasV4T]>;
2803
2804 let mayStore = 1, neverHasSideEffects = 1 in
2805 def STrib_GP_cdnNotPt_nv_V4 : NVInst_V4<(outs),
2806             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2807                                                         IntRegs:$src2),
2808             "if (!$src1.new) memb(##$global+$offset) = $src2.new",
2809             []>,
2810             Requires<[HasV4T]>;
2811
2812 let mayStore = 1, neverHasSideEffects = 1 in
2813 def STrih_GP_cPt_nv_V4 : NVInst_V4<(outs),
2814             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2815                                                         IntRegs:$src2),
2816             "if ($src1) memh(##$global+$offset) = $src2.new",
2817             []>,
2818             Requires<[HasV4T]>;
2819
2820 let mayStore = 1, neverHasSideEffects = 1 in
2821 def STrih_GP_cNotPt_nv_V4 : NVInst_V4<(outs),
2822             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2823                                                         IntRegs:$src2),
2824             "if (!$src1) memh(##$global+$offset) = $src2.new",
2825             []>,
2826             Requires<[HasV4T]>;
2827
2828 let mayStore = 1, neverHasSideEffects = 1 in
2829 def STrih_GP_cdnPt_nv_V4 : NVInst_V4<(outs),
2830             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2831                                                         IntRegs:$src2),
2832             "if ($src1.new) memh(##$global+$offset) = $src2.new",
2833             []>,
2834             Requires<[HasV4T]>;
2835
2836 let mayStore = 1, neverHasSideEffects = 1 in
2837 def STrih_GP_cdnNotPt_nv_V4 : NVInst_V4<(outs),
2838             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2839                                                         IntRegs:$src2),
2840             "if (!$src1.new) memh(##$global+$offset) = $src2.new",
2841             []>,
2842             Requires<[HasV4T]>;
2843
2844 let mayStore = 1, neverHasSideEffects = 1 in
2845 def STriw_GP_cPt_nv_V4 : NVInst_V4<(outs),
2846             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2847                                                         IntRegs:$src2),
2848             "if ($src1) memw(##$global+$offset) = $src2.new",
2849             []>,
2850             Requires<[HasV4T]>;
2851
2852 let mayStore = 1, neverHasSideEffects = 1 in
2853 def STriw_GP_cNotPt_nv_V4 : NVInst_V4<(outs),
2854             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2855                                                         IntRegs:$src2),
2856             "if (!$src1) memw(##$global+$offset) = $src2.new",
2857             []>,
2858             Requires<[HasV4T]>;
2859
2860 let mayStore = 1, neverHasSideEffects = 1 in
2861 def STriw_GP_cdnPt_nv_V4 : NVInst_V4<(outs),
2862             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2863                                                         IntRegs:$src2),
2864             "if ($src1.new) memw(##$global+$offset) = $src2.new",
2865             []>,
2866             Requires<[HasV4T]>;
2867
2868 let mayStore = 1, neverHasSideEffects = 1 in
2869 def STriw_GP_cdnNotPt_nv_V4 : NVInst_V4<(outs),
2870             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2871                                                         IntRegs:$src2),
2872             "if (!$src1.new) memw(##$global+$offset) = $src2.new",
2873             []>,
2874             Requires<[HasV4T]>;
2875
2876 //===----------------------------------------------------------------------===//
2877 // NV/ST -
2878 //===----------------------------------------------------------------------===//
2879
2880 //===----------------------------------------------------------------------===//
2881 // NV/J +
2882 //===----------------------------------------------------------------------===//
2883
2884 multiclass NVJ_type_basic_reg<string NotStr, string OpcStr, string TakenStr> {
2885   def _ie_nv_V4 : NVInst_V4<(outs),
2886             (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset),
2887             !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
2888             !strconcat("($src1.new, $src2)) jump:",
2889             !strconcat(TakenStr, " $offset"))))),
2890             []>,
2891             Requires<[HasV4T]>;
2892
2893   def _nv_V4 : NVInst_V4<(outs),
2894             (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset),
2895             !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
2896             !strconcat("($src1.new, $src2)) jump:",
2897             !strconcat(TakenStr, " $offset"))))),
2898             []>,
2899             Requires<[HasV4T]>;
2900 }
2901
2902 multiclass NVJ_type_basic_2ndDotNew<string NotStr, string OpcStr,
2903                                                    string TakenStr> {
2904   def _ie_nv_V4 : NVInst_V4<(outs),
2905             (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset),
2906             !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
2907             !strconcat("($src1, $src2.new)) jump:",
2908             !strconcat(TakenStr, " $offset"))))),
2909             []>,
2910             Requires<[HasV4T]>;
2911
2912   def _nv_V4 : NVInst_V4<(outs),
2913             (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset),
2914             !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
2915             !strconcat("($src1, $src2.new)) jump:",
2916             !strconcat(TakenStr, " $offset"))))),
2917             []>,
2918             Requires<[HasV4T]>;
2919 }
2920
2921 multiclass NVJ_type_basic_imm<string NotStr, string OpcStr, string TakenStr> {
2922   def _ie_nv_V4 : NVInst_V4<(outs),
2923             (ins IntRegs:$src1, u5Imm:$src2, brtarget:$offset),
2924             !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
2925             !strconcat("($src1.new, #$src2)) jump:",
2926             !strconcat(TakenStr, " $offset"))))),
2927             []>,
2928             Requires<[HasV4T]>;
2929
2930   def _nv_V4 : NVInst_V4<(outs),
2931             (ins IntRegs:$src1, u5Imm:$src2, brtarget:$offset),
2932             !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
2933             !strconcat("($src1.new, #$src2)) jump:",
2934             !strconcat(TakenStr, " $offset"))))),
2935             []>,
2936             Requires<[HasV4T]>;
2937 }
2938
2939 multiclass NVJ_type_basic_neg<string NotStr, string OpcStr, string TakenStr> {
2940   def _ie_nv_V4 : NVInst_V4<(outs),
2941             (ins IntRegs:$src1, nOneImm:$src2, brtarget:$offset),
2942             !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
2943             !strconcat("($src1.new, #$src2)) jump:",
2944             !strconcat(TakenStr, " $offset"))))),
2945             []>,
2946             Requires<[HasV4T]>;
2947
2948   def _nv_V4 : NVInst_V4<(outs),
2949             (ins IntRegs:$src1, nOneImm:$src2, brtarget:$offset),
2950             !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
2951             !strconcat("($src1.new, #$src2)) jump:",
2952             !strconcat(TakenStr, " $offset"))))),
2953             []>,
2954             Requires<[HasV4T]>;
2955 }
2956
2957 multiclass NVJ_type_basic_tstbit<string NotStr, string OpcStr,
2958                                                 string TakenStr> {
2959   def _ie_nv_V4 : NVInst_V4<(outs),
2960             (ins IntRegs:$src1, u1Imm:$src2, brtarget:$offset),
2961             !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
2962             !strconcat("($src1.new, #$src2)) jump:",
2963             !strconcat(TakenStr, " $offset"))))),
2964             []>,
2965             Requires<[HasV4T]>;
2966
2967   def _nv_V4 : NVInst_V4<(outs),
2968             (ins IntRegs:$src1, u1Imm:$src2, brtarget:$offset),
2969             !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
2970             !strconcat("($src1.new, #$src2)) jump:",
2971             !strconcat(TakenStr, " $offset"))))),
2972             []>,
2973             Requires<[HasV4T]>;
2974 }
2975
2976 // Multiclass for regular dot new of Ist operand register.
2977 multiclass NVJ_type_br_pred_reg<string NotStr, string OpcStr> {
2978   defm Pt  : NVJ_type_basic_reg<NotStr, OpcStr, "t">;
2979   defm Pnt : NVJ_type_basic_reg<NotStr, OpcStr, "nt">;
2980 }
2981
2982 // Multiclass for dot new of 2nd operand register.
2983 multiclass NVJ_type_br_pred_2ndDotNew<string NotStr, string OpcStr> {
2984   defm Pt  : NVJ_type_basic_2ndDotNew<NotStr, OpcStr, "t">;
2985   defm Pnt : NVJ_type_basic_2ndDotNew<NotStr, OpcStr, "nt">;
2986 }
2987
2988 // Multiclass for 2nd operand immediate, including -1.
2989 multiclass NVJ_type_br_pred_imm<string NotStr, string OpcStr> {
2990   defm Pt     : NVJ_type_basic_imm<NotStr, OpcStr, "t">;
2991   defm Pnt    : NVJ_type_basic_imm<NotStr, OpcStr, "nt">;
2992   defm Ptneg  : NVJ_type_basic_neg<NotStr, OpcStr, "t">;
2993   defm Pntneg : NVJ_type_basic_neg<NotStr, OpcStr, "nt">;
2994 }
2995
2996 // Multiclass for 2nd operand immediate, excluding -1.
2997 multiclass NVJ_type_br_pred_imm_only<string NotStr, string OpcStr> {
2998   defm Pt     : NVJ_type_basic_imm<NotStr, OpcStr, "t">;
2999   defm Pnt    : NVJ_type_basic_imm<NotStr, OpcStr, "nt">;
3000 }
3001
3002 // Multiclass for tstbit, where 2nd operand is always #0.
3003 multiclass NVJ_type_br_pred_tstbit<string NotStr, string OpcStr> {
3004   defm Pt     : NVJ_type_basic_tstbit<NotStr, OpcStr, "t">;
3005   defm Pnt    : NVJ_type_basic_tstbit<NotStr, OpcStr, "nt">;
3006 }
3007
3008 // Multiclass for GT.
3009 multiclass NVJ_type_rr_ri<string OpcStr> {
3010   defm rrNot   : NVJ_type_br_pred_reg<"!", OpcStr>;
3011   defm rr      : NVJ_type_br_pred_reg<"",  OpcStr>;
3012   defm rrdnNot : NVJ_type_br_pred_2ndDotNew<"!", OpcStr>;
3013   defm rrdn    : NVJ_type_br_pred_2ndDotNew<"",  OpcStr>;
3014   defm riNot   : NVJ_type_br_pred_imm<"!", OpcStr>;
3015   defm ri      : NVJ_type_br_pred_imm<"",  OpcStr>;
3016 }
3017
3018 // Multiclass for EQ.
3019 multiclass NVJ_type_rr_ri_no_2ndDotNew<string OpcStr> {
3020   defm rrNot   : NVJ_type_br_pred_reg<"!", OpcStr>;
3021   defm rr      : NVJ_type_br_pred_reg<"",  OpcStr>;
3022   defm riNot   : NVJ_type_br_pred_imm<"!", OpcStr>;
3023   defm ri      : NVJ_type_br_pred_imm<"",  OpcStr>;
3024 }
3025
3026 // Multiclass for GTU.
3027 multiclass NVJ_type_rr_ri_no_nOne<string OpcStr> {
3028   defm rrNot   : NVJ_type_br_pred_reg<"!", OpcStr>;
3029   defm rr      : NVJ_type_br_pred_reg<"",  OpcStr>;
3030   defm rrdnNot : NVJ_type_br_pred_2ndDotNew<"!", OpcStr>;
3031   defm rrdn    : NVJ_type_br_pred_2ndDotNew<"",  OpcStr>;
3032   defm riNot   : NVJ_type_br_pred_imm_only<"!", OpcStr>;
3033   defm ri      : NVJ_type_br_pred_imm_only<"",  OpcStr>;
3034 }
3035
3036 // Multiclass for tstbit.
3037 multiclass NVJ_type_r0<string OpcStr> {
3038   defm r0Not : NVJ_type_br_pred_tstbit<"!", OpcStr>;
3039   defm r0    : NVJ_type_br_pred_tstbit<"",  OpcStr>;
3040  }
3041
3042 // Base Multiclass for New Value Jump.
3043 multiclass NVJ_type {
3044   defm GT     : NVJ_type_rr_ri<"cmp.gt">;
3045   defm EQ     : NVJ_type_rr_ri_no_2ndDotNew<"cmp.eq">;
3046   defm GTU    : NVJ_type_rr_ri_no_nOne<"cmp.gtu">;
3047   defm TSTBIT : NVJ_type_r0<"tstbit">;
3048 }
3049
3050 let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC] in {
3051   defm JMP_ : NVJ_type;
3052 }
3053
3054 //===----------------------------------------------------------------------===//
3055 // NV/J -
3056 //===----------------------------------------------------------------------===//
3057
3058 //===----------------------------------------------------------------------===//
3059 // XTYPE/ALU +
3060 //===----------------------------------------------------------------------===//
3061
3062 //  Add and accumulate.
3063 //  Rd=add(Rs,add(Ru,#s6))
3064 def ADDr_ADDri_V4 : MInst<(outs IntRegs:$dst),
3065           (ins IntRegs:$src1, IntRegs:$src2, s6Imm:$src3),
3066           "$dst = add($src1, add($src2, #$src3))",
3067           [(set (i32 IntRegs:$dst),
3068            (add (i32 IntRegs:$src1), (add (i32 IntRegs:$src2),
3069                                           s6ImmPred:$src3)))]>,
3070           Requires<[HasV4T]>;
3071
3072 //  Rd=add(Rs,sub(#s6,Ru))
3073 def ADDr_SUBri_V4 : MInst<(outs IntRegs:$dst),
3074           (ins IntRegs:$src1, s6Imm:$src2, IntRegs:$src3),
3075           "$dst = add($src1, sub(#$src2, $src3))",
3076           [(set (i32 IntRegs:$dst),
3077            (add (i32 IntRegs:$src1), (sub s6ImmPred:$src2,
3078                                           (i32 IntRegs:$src3))))]>,
3079           Requires<[HasV4T]>;
3080
3081 // Generates the same instruction as ADDr_SUBri_V4 but matches different
3082 // pattern.
3083 //  Rd=add(Rs,sub(#s6,Ru))
3084 def ADDri_SUBr_V4 : MInst<(outs IntRegs:$dst),
3085           (ins IntRegs:$src1, s6Imm:$src2, IntRegs:$src3),
3086           "$dst = add($src1, sub(#$src2, $src3))",
3087           [(set (i32 IntRegs:$dst),
3088                 (sub (add (i32 IntRegs:$src1), s6ImmPred:$src2),
3089                      (i32 IntRegs:$src3)))]>,
3090           Requires<[HasV4T]>;
3091
3092
3093 //  Add or subtract doublewords with carry.
3094 //TODO:
3095 //  Rdd=add(Rss,Rtt,Px):carry
3096 //TODO:
3097 //  Rdd=sub(Rss,Rtt,Px):carry
3098
3099
3100 //  Logical doublewords.
3101 //  Rdd=and(Rtt,~Rss)
3102 def ANDd_NOTd_V4 : MInst<(outs DoubleRegs:$dst),
3103           (ins DoubleRegs:$src1, DoubleRegs:$src2),
3104           "$dst = and($src1, ~$src2)",
3105           [(set (i64 DoubleRegs:$dst), (and (i64 DoubleRegs:$src1),
3106                                       (not (i64 DoubleRegs:$src2))))]>,
3107           Requires<[HasV4T]>;
3108
3109 //  Rdd=or(Rtt,~Rss)
3110 def ORd_NOTd_V4 : MInst<(outs DoubleRegs:$dst),
3111           (ins DoubleRegs:$src1, DoubleRegs:$src2),
3112           "$dst = or($src1, ~$src2)",
3113           [(set (i64 DoubleRegs:$dst),
3114            (or (i64 DoubleRegs:$src1), (not (i64 DoubleRegs:$src2))))]>,
3115           Requires<[HasV4T]>;
3116
3117
3118 //  Logical-logical doublewords.
3119 //  Rxx^=xor(Rss,Rtt)
3120 def XORd_XORdd: MInst_acc<(outs DoubleRegs:$dst),
3121           (ins DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),
3122           "$dst ^= xor($src2, $src3)",
3123           [(set (i64 DoubleRegs:$dst),
3124            (xor (i64 DoubleRegs:$src1), (xor (i64 DoubleRegs:$src2),
3125                                              (i64 DoubleRegs:$src3))))],
3126           "$src1 = $dst">,
3127           Requires<[HasV4T]>;
3128
3129
3130 // Logical-logical words.
3131 // Rx=or(Ru,and(Rx,#s10))
3132 def ORr_ANDri_V4 : MInst_acc<(outs IntRegs:$dst),
3133             (ins IntRegs:$src1, IntRegs: $src2, s10Imm:$src3),
3134             "$dst = or($src1, and($src2, #$src3))",
3135             [(set (i32 IntRegs:$dst),
3136                   (or (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
3137                                                 s10ImmPred:$src3)))],
3138             "$src2 = $dst">,
3139             Requires<[HasV4T]>;
3140
3141 // Rx[&|^]=and(Rs,Rt)
3142 // Rx&=and(Rs,Rt)
3143 def ANDr_ANDrr_V4 : MInst_acc<(outs IntRegs:$dst),
3144             (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
3145             "$dst &= and($src2, $src3)",
3146             [(set (i32 IntRegs:$dst),
3147                   (and (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
3148                                                  (i32 IntRegs:$src3))))],
3149             "$src1 = $dst">,
3150             Requires<[HasV4T]>;
3151
3152 // Rx|=and(Rs,Rt)
3153 def ORr_ANDrr_V4 : MInst_acc<(outs IntRegs:$dst),
3154             (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
3155             "$dst |= and($src2, $src3)",
3156             [(set (i32 IntRegs:$dst),
3157                   (or (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
3158                                                 (i32 IntRegs:$src3))))],
3159             "$src1 = $dst">,
3160             Requires<[HasV4T]>;
3161
3162 // Rx^=and(Rs,Rt)
3163 def XORr_ANDrr_V4 : MInst_acc<(outs IntRegs:$dst),
3164             (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
3165             "$dst ^= and($src2, $src3)",
3166             [(set (i32 IntRegs:$dst),
3167              (xor (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
3168                                             (i32 IntRegs:$src3))))],
3169             "$src1 = $dst">,
3170             Requires<[HasV4T]>;
3171
3172 // Rx[&|^]=and(Rs,~Rt)
3173 // Rx&=and(Rs,~Rt)
3174 def ANDr_ANDr_NOTr_V4 : MInst_acc<(outs IntRegs:$dst),
3175             (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
3176             "$dst &= and($src2, ~$src3)",
3177             [(set (i32 IntRegs:$dst),
3178                   (and (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
3179                                                  (not (i32 IntRegs:$src3)))))],
3180             "$src1 = $dst">,
3181             Requires<[HasV4T]>;
3182
3183 // Rx|=and(Rs,~Rt)
3184 def ORr_ANDr_NOTr_V4 : MInst_acc<(outs IntRegs:$dst),
3185             (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
3186             "$dst |= and($src2, ~$src3)",
3187             [(set (i32 IntRegs:$dst),
3188              (or (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
3189                                            (not (i32 IntRegs:$src3)))))],
3190             "$src1 = $dst">,
3191             Requires<[HasV4T]>;
3192
3193 // Rx^=and(Rs,~Rt)
3194 def XORr_ANDr_NOTr_V4 : MInst_acc<(outs IntRegs:$dst),
3195             (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
3196             "$dst ^= and($src2, ~$src3)",
3197             [(set (i32 IntRegs:$dst),
3198              (xor (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
3199                                             (not (i32 IntRegs:$src3)))))],
3200             "$src1 = $dst">,
3201             Requires<[HasV4T]>;
3202
3203 // Rx[&|^]=or(Rs,Rt)
3204 // Rx&=or(Rs,Rt)
3205 def ANDr_ORrr_V4 : MInst_acc<(outs IntRegs:$dst),
3206             (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
3207             "$dst &= or($src2, $src3)",
3208             [(set (i32 IntRegs:$dst),
3209                   (and (i32 IntRegs:$src1), (or (i32 IntRegs:$src2),
3210                                                 (i32 IntRegs:$src3))))],
3211             "$src1 = $dst">,
3212             Requires<[HasV4T]>;
3213
3214 // Rx|=or(Rs,Rt)
3215 def ORr_ORrr_V4 : MInst_acc<(outs IntRegs:$dst),
3216             (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
3217             "$dst |= or($src2, $src3)",
3218             [(set (i32 IntRegs:$dst),
3219                   (or (i32 IntRegs:$src1), (or (i32 IntRegs:$src2),
3220                                                (i32 IntRegs:$src3))))],
3221             "$src1 = $dst">,
3222             Requires<[HasV4T]>;
3223
3224 // Rx^=or(Rs,Rt)
3225 def XORr_ORrr_V4 : MInst_acc<(outs IntRegs:$dst),
3226             (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
3227             "$dst ^= or($src2, $src3)",
3228             [(set (i32 IntRegs:$dst),
3229              (xor (i32 IntRegs:$src1), (or (i32 IntRegs:$src2),
3230                                            (i32 IntRegs:$src3))))],
3231             "$src1 = $dst">,
3232             Requires<[HasV4T]>;
3233
3234 // Rx[&|^]=xor(Rs,Rt)
3235 // Rx&=xor(Rs,Rt)
3236 def ANDr_XORrr_V4 : MInst_acc<(outs IntRegs:$dst),
3237             (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
3238             "$dst &= xor($src2, $src3)",
3239             [(set (i32 IntRegs:$dst),
3240                   (and (i32 IntRegs:$src1), (xor (i32 IntRegs:$src2),
3241                                                  (i32 IntRegs:$src3))))],
3242             "$src1 = $dst">,
3243             Requires<[HasV4T]>;
3244
3245 // Rx|=xor(Rs,Rt)
3246 def ORr_XORrr_V4 : MInst_acc<(outs IntRegs:$dst),
3247             (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
3248             "$dst |= xor($src2, $src3)",
3249             [(set (i32 IntRegs:$dst),
3250                   (and (i32 IntRegs:$src1), (xor (i32 IntRegs:$src2),
3251                                                  (i32 IntRegs:$src3))))],
3252             "$src1 = $dst">,
3253             Requires<[HasV4T]>;
3254
3255 // Rx^=xor(Rs,Rt)
3256 def XORr_XORrr_V4 : MInst_acc<(outs IntRegs:$dst),
3257             (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
3258             "$dst ^= xor($src2, $src3)",
3259             [(set (i32 IntRegs:$dst),
3260              (and (i32 IntRegs:$src1), (xor (i32 IntRegs:$src2),
3261                                             (i32 IntRegs:$src3))))],
3262             "$src1 = $dst">,
3263             Requires<[HasV4T]>;
3264
3265 // Rx|=and(Rs,#s10)
3266 def ORr_ANDri2_V4 : MInst_acc<(outs IntRegs:$dst),
3267             (ins IntRegs:$src1, IntRegs: $src2, s10Imm:$src3),
3268             "$dst |= and($src2, #$src3)",
3269             [(set (i32 IntRegs:$dst),
3270                   (or (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
3271                                                 s10ImmPred:$src3)))],
3272             "$src1 = $dst">,
3273             Requires<[HasV4T]>;
3274
3275 // Rx|=or(Rs,#s10)
3276 def ORr_ORri_V4 : MInst_acc<(outs IntRegs:$dst),
3277             (ins IntRegs:$src1, IntRegs: $src2, s10Imm:$src3),
3278             "$dst |= or($src2, #$src3)",
3279             [(set (i32 IntRegs:$dst),
3280                   (or (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
3281                                                 s10ImmPred:$src3)))],
3282             "$src1 = $dst">,
3283             Requires<[HasV4T]>;
3284
3285
3286 //    Modulo wrap
3287 //        Rd=modwrap(Rs,Rt)
3288 //    Round
3289 //        Rd=cround(Rs,#u5)
3290 //        Rd=cround(Rs,Rt)
3291 //        Rd=round(Rs,#u5)[:sat]
3292 //        Rd=round(Rs,Rt)[:sat]
3293 //    Vector reduce add unsigned halfwords
3294 //        Rd=vraddh(Rss,Rtt)
3295 //    Vector add bytes
3296 //        Rdd=vaddb(Rss,Rtt)
3297 //    Vector conditional negate
3298 //        Rdd=vcnegh(Rss,Rt)
3299 //        Rxx+=vrcnegh(Rss,Rt)
3300 //    Vector maximum bytes
3301 //        Rdd=vmaxb(Rtt,Rss)
3302 //    Vector reduce maximum halfwords
3303 //        Rxx=vrmaxh(Rss,Ru)
3304 //        Rxx=vrmaxuh(Rss,Ru)
3305 //    Vector reduce maximum words
3306 //        Rxx=vrmaxuw(Rss,Ru)
3307 //        Rxx=vrmaxw(Rss,Ru)
3308 //    Vector minimum bytes
3309 //        Rdd=vminb(Rtt,Rss)
3310 //    Vector reduce minimum halfwords
3311 //        Rxx=vrminh(Rss,Ru)
3312 //        Rxx=vrminuh(Rss,Ru)
3313 //    Vector reduce minimum words
3314 //        Rxx=vrminuw(Rss,Ru)
3315 //        Rxx=vrminw(Rss,Ru)
3316 //    Vector subtract bytes
3317 //        Rdd=vsubb(Rss,Rtt)
3318
3319 //===----------------------------------------------------------------------===//
3320 // XTYPE/ALU -
3321 //===----------------------------------------------------------------------===//
3322
3323
3324 //===----------------------------------------------------------------------===//
3325 // XTYPE/MPY +
3326 //===----------------------------------------------------------------------===//
3327
3328 // Multiply and user lower result.
3329 // Rd=add(#u6,mpyi(Rs,#U6))
3330 def ADDi_MPYri_V4 : MInst<(outs IntRegs:$dst),
3331             (ins u6Imm:$src1, IntRegs:$src2, u6Imm:$src3),
3332             "$dst = add(#$src1, mpyi($src2, #$src3))",
3333             [(set (i32 IntRegs:$dst),
3334                   (add (mul (i32 IntRegs:$src2), u6ImmPred:$src3),
3335                        u6ImmPred:$src1))]>,
3336             Requires<[HasV4T]>;
3337
3338 // Rd=add(#u6,mpyi(Rs,Rt))
3339
3340 def ADDi_MPYrr_V4 : MInst<(outs IntRegs:$dst),
3341             (ins u6Imm:$src1, IntRegs:$src2, IntRegs:$src3),
3342             "$dst = add(#$src1, mpyi($src2, $src3))",
3343             [(set (i32 IntRegs:$dst),
3344                   (add (mul (i32 IntRegs:$src2), (i32 IntRegs:$src3)),
3345                        u6ImmPred:$src1))]>,
3346             Requires<[HasV4T]>;
3347
3348 // Rd=add(Ru,mpyi(#u6:2,Rs))
3349 def ADDr_MPYir_V4 : MInst<(outs IntRegs:$dst),
3350             (ins IntRegs:$src1, u6Imm:$src2, IntRegs:$src3),
3351             "$dst = add($src1, mpyi(#$src2, $src3))",
3352             [(set (i32 IntRegs:$dst),
3353              (add (i32 IntRegs:$src1), (mul (i32 IntRegs:$src3),
3354                                             u6_2ImmPred:$src2)))]>,
3355             Requires<[HasV4T]>;
3356
3357 // Rd=add(Ru,mpyi(Rs,#u6))
3358 def ADDr_MPYri_V4 : MInst<(outs IntRegs:$dst),
3359             (ins IntRegs:$src1, IntRegs:$src2, u6Imm:$src3),
3360             "$dst = add($src1, mpyi($src2, #$src3))",
3361             [(set (i32 IntRegs:$dst),
3362                   (add (i32 IntRegs:$src1), (mul (i32 IntRegs:$src2),
3363                                                  u6ImmPred:$src3)))]>,
3364             Requires<[HasV4T]>;
3365
3366 // Rx=add(Ru,mpyi(Rx,Rs))
3367 def ADDr_MPYrr_V4 : MInst_acc<(outs IntRegs:$dst),
3368             (ins IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
3369             "$dst = add($src1, mpyi($src2, $src3))",
3370             [(set (i32 IntRegs:$dst),
3371              (add (i32 IntRegs:$src1), (mul (i32 IntRegs:$src2),
3372                                             (i32 IntRegs:$src3))))],
3373             "$src2 = $dst">,
3374             Requires<[HasV4T]>;
3375
3376
3377 // Polynomial multiply words
3378 // Rdd=pmpyw(Rs,Rt)
3379 // Rxx^=pmpyw(Rs,Rt)
3380
3381 // Vector reduce multiply word by signed half (32x16)
3382 // Rdd=vrmpyweh(Rss,Rtt)[:<<1]
3383 // Rdd=vrmpywoh(Rss,Rtt)[:<<1]
3384 // Rxx+=vrmpyweh(Rss,Rtt)[:<<1]
3385 // Rxx+=vrmpywoh(Rss,Rtt)[:<<1]
3386
3387 // Multiply and use upper result
3388 // Rd=mpy(Rs,Rt.H):<<1:sat
3389 // Rd=mpy(Rs,Rt.L):<<1:sat
3390 // Rd=mpy(Rs,Rt):<<1
3391 // Rd=mpy(Rs,Rt):<<1:sat
3392 // Rd=mpysu(Rs,Rt)
3393 // Rx+=mpy(Rs,Rt):<<1:sat
3394 // Rx-=mpy(Rs,Rt):<<1:sat
3395
3396 // Vector multiply bytes
3397 // Rdd=vmpybsu(Rs,Rt)
3398 // Rdd=vmpybu(Rs,Rt)
3399 // Rxx+=vmpybsu(Rs,Rt)
3400 // Rxx+=vmpybu(Rs,Rt)
3401
3402 // Vector polynomial multiply halfwords
3403 // Rdd=vpmpyh(Rs,Rt)
3404 // Rxx^=vpmpyh(Rs,Rt)
3405
3406 //===----------------------------------------------------------------------===//
3407 // XTYPE/MPY -
3408 //===----------------------------------------------------------------------===//
3409
3410
3411 //===----------------------------------------------------------------------===//
3412 // XTYPE/SHIFT +
3413 //===----------------------------------------------------------------------===//
3414
3415 // Shift by immediate and accumulate.
3416 // Rx=add(#u8,asl(Rx,#U5))
3417 def ADDi_ASLri_V4 : MInst_acc<(outs IntRegs:$dst),
3418             (ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3),
3419             "$dst = add(#$src1, asl($src2, #$src3))",
3420             [(set (i32 IntRegs:$dst),
3421                   (add (shl (i32 IntRegs:$src2), u5ImmPred:$src3),
3422                        u8ImmPred:$src1))],
3423             "$src2 = $dst">,
3424             Requires<[HasV4T]>;
3425
3426 // Rx=add(#u8,lsr(Rx,#U5))
3427 def ADDi_LSRri_V4 : MInst_acc<(outs IntRegs:$dst),
3428             (ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3),
3429             "$dst = add(#$src1, lsr($src2, #$src3))",
3430             [(set (i32 IntRegs:$dst),
3431                   (add (srl (i32 IntRegs:$src2), u5ImmPred:$src3),
3432                        u8ImmPred:$src1))],
3433             "$src2 = $dst">,
3434             Requires<[HasV4T]>;
3435
3436 // Rx=sub(#u8,asl(Rx,#U5))
3437 def SUBi_ASLri_V4 : MInst_acc<(outs IntRegs:$dst),
3438             (ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3),
3439             "$dst = sub(#$src1, asl($src2, #$src3))",
3440             [(set (i32 IntRegs:$dst),
3441                   (sub (shl (i32 IntRegs:$src2), u5ImmPred:$src3),
3442                        u8ImmPred:$src1))],
3443             "$src2 = $dst">,
3444             Requires<[HasV4T]>;
3445
3446 // Rx=sub(#u8,lsr(Rx,#U5))
3447 def SUBi_LSRri_V4 : MInst_acc<(outs IntRegs:$dst),
3448             (ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3),
3449             "$dst = sub(#$src1, lsr($src2, #$src3))",
3450             [(set (i32 IntRegs:$dst),
3451                   (sub (srl (i32 IntRegs:$src2), u5ImmPred:$src3),
3452                        u8ImmPred:$src1))],
3453             "$src2 = $dst">,
3454             Requires<[HasV4T]>;
3455
3456
3457 //Shift by immediate and logical.
3458 //Rx=and(#u8,asl(Rx,#U5))
3459 def ANDi_ASLri_V4 : MInst_acc<(outs IntRegs:$dst),
3460             (ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3),
3461             "$dst = and(#$src1, asl($src2, #$src3))",
3462             [(set (i32 IntRegs:$dst),
3463                   (and (shl (i32 IntRegs:$src2), u5ImmPred:$src3),
3464                        u8ImmPred:$src1))],
3465             "$src2 = $dst">,
3466             Requires<[HasV4T]>;
3467
3468 //Rx=and(#u8,lsr(Rx,#U5))
3469 def ANDi_LSRri_V4 : MInst_acc<(outs IntRegs:$dst),
3470             (ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3),
3471             "$dst = and(#$src1, lsr($src2, #$src3))",
3472             [(set (i32 IntRegs:$dst),
3473                   (and (srl (i32 IntRegs:$src2), u5ImmPred:$src3),
3474                        u8ImmPred:$src1))],
3475             "$src2 = $dst">,
3476             Requires<[HasV4T]>;
3477
3478 //Rx=or(#u8,asl(Rx,#U5))
3479 let AddedComplexity = 30 in
3480 def ORi_ASLri_V4 : MInst_acc<(outs IntRegs:$dst),
3481             (ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3),
3482             "$dst = or(#$src1, asl($src2, #$src3))",
3483             [(set (i32 IntRegs:$dst),
3484                   (or (shl (i32 IntRegs:$src2), u5ImmPred:$src3),
3485                       u8ImmPred:$src1))],
3486             "$src2 = $dst">,
3487             Requires<[HasV4T]>;
3488
3489 //Rx=or(#u8,lsr(Rx,#U5))
3490 let AddedComplexity = 30 in
3491 def ORi_LSRri_V4 : MInst_acc<(outs IntRegs:$dst),
3492             (ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3),
3493             "$dst = or(#$src1, lsr($src2, #$src3))",
3494             [(set (i32 IntRegs:$dst),
3495                   (or (srl (i32 IntRegs:$src2), u5ImmPred:$src3),
3496                       u8ImmPred:$src1))],
3497             "$src2 = $dst">,
3498             Requires<[HasV4T]>;
3499
3500
3501 //Shift by register.
3502 //Rd=lsl(#s6,Rt)
3503 def LSLi_V4 : MInst<(outs IntRegs:$dst), (ins s6Imm:$src1, IntRegs:$src2),
3504             "$dst = lsl(#$src1, $src2)",
3505             [(set (i32 IntRegs:$dst), (shl s6ImmPred:$src1,
3506                                            (i32 IntRegs:$src2)))]>,
3507             Requires<[HasV4T]>;
3508
3509
3510 //Shift by register and logical.
3511 //Rxx^=asl(Rss,Rt)
3512 def ASLd_rr_xor_V4 : MInst_acc<(outs DoubleRegs:$dst),
3513             (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
3514             "$dst ^= asl($src2, $src3)",
3515             [(set (i64 DoubleRegs:$dst),
3516                   (xor (i64 DoubleRegs:$src1), (shl (i64 DoubleRegs:$src2),
3517                                                     (i32 IntRegs:$src3))))],
3518             "$src1 = $dst">,
3519             Requires<[HasV4T]>;
3520
3521 //Rxx^=asr(Rss,Rt)
3522 def ASRd_rr_xor_V4 : MInst_acc<(outs DoubleRegs:$dst),
3523             (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
3524             "$dst ^= asr($src2, $src3)",
3525             [(set (i64 DoubleRegs:$dst),
3526                   (xor (i64 DoubleRegs:$src1), (sra (i64 DoubleRegs:$src2),
3527                                                     (i32 IntRegs:$src3))))],
3528             "$src1 = $dst">,
3529             Requires<[HasV4T]>;
3530
3531 //Rxx^=lsl(Rss,Rt)
3532 def LSLd_rr_xor_V4 : MInst_acc<(outs DoubleRegs:$dst),
3533             (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
3534             "$dst ^= lsl($src2, $src3)",
3535             [(set (i64 DoubleRegs:$dst), (xor (i64 DoubleRegs:$src1),
3536                                               (shl (i64 DoubleRegs:$src2),
3537                                                    (i32 IntRegs:$src3))))],
3538             "$src1 = $dst">,
3539             Requires<[HasV4T]>;
3540
3541 //Rxx^=lsr(Rss,Rt)
3542 def LSRd_rr_xor_V4 : MInst_acc<(outs DoubleRegs:$dst),
3543             (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
3544             "$dst ^= lsr($src2, $src3)",
3545             [(set (i64 DoubleRegs:$dst),
3546                   (xor (i64 DoubleRegs:$src1), (srl (i64 DoubleRegs:$src2),
3547                                                     (i32 IntRegs:$src3))))],
3548             "$src1 = $dst">,
3549             Requires<[HasV4T]>;
3550
3551
3552 //===----------------------------------------------------------------------===//
3553 // XTYPE/SHIFT -
3554 //===----------------------------------------------------------------------===//
3555
3556 //===----------------------------------------------------------------------===//
3557 // MEMOP: Word, Half, Byte
3558 //===----------------------------------------------------------------------===//
3559
3560 //===----------------------------------------------------------------------===//
3561 // MEMOP: Word
3562 //
3563 //  Implemented:
3564 //     MEMw_ADDi_indexed_V4  : memw(Rs+#u6:2)+=#U5
3565 //     MEMw_SUBi_indexed_V4  : memw(Rs+#u6:2)-=#U5
3566 //     MEMw_ADDr_indexed_V4  : memw(Rs+#u6:2)+=Rt
3567 //     MEMw_SUBr_indexed_V4  : memw(Rs+#u6:2)-=Rt
3568 //     MEMw_CLRr_indexed_V4  : memw(Rs+#u6:2)&=Rt
3569 //     MEMw_SETr_indexed_V4  : memw(Rs+#u6:2)|=Rt
3570 //     MEMw_ADDi_V4          : memw(Rs+#u6:2)+=#U5
3571 //     MEMw_SUBi_V4          : memw(Rs+#u6:2)-=#U5
3572 //     MEMw_ADDr_V4          : memw(Rs+#u6:2)+=Rt
3573 //     MEMw_SUBr_V4          : memw(Rs+#u6:2)-=Rt
3574 //     MEMw_CLRr_V4          : memw(Rs+#u6:2)&=Rt
3575 //     MEMw_SETr_V4          : memw(Rs+#u6:2)|=Rt
3576 //
3577 //   Not implemented:
3578 //     MEMw_CLRi_indexed_V4  : memw(Rs+#u6:2)=clrbit(#U5)
3579 //     MEMw_SETi_indexed_V4  : memw(Rs+#u6:2)=setbit(#U5)
3580 //     MEMw_CLRi_V4          : memw(Rs+#u6:2)=clrbit(#U5)
3581 //     MEMw_SETi_V4          : memw(Rs+#u6:2)=setbit(#U5)
3582 //===----------------------------------------------------------------------===//
3583
3584
3585
3586 // memw(Rs+#u6:2) += #U5
3587 let AddedComplexity = 30 in
3588 def MEMw_ADDi_indexed_MEM_V4 : MEMInst_V4<(outs),
3589             (ins IntRegs:$base, u6_2Imm:$offset, u5Imm:$addend),
3590             "memw($base+#$offset) += #$addend",
3591             []>,
3592             Requires<[HasV4T, UseMEMOP]>;
3593
3594 // memw(Rs+#u6:2) -= #U5
3595 let AddedComplexity = 30 in
3596 def MEMw_SUBi_indexed_MEM_V4 : MEMInst_V4<(outs),
3597             (ins IntRegs:$base, u6_2Imm:$offset, u5Imm:$subend),
3598             "memw($base+#$offset) -= #$subend",
3599             []>,
3600             Requires<[HasV4T, UseMEMOP]>;
3601
3602 // memw(Rs+#u6:2) += Rt
3603 let AddedComplexity = 30 in
3604 def MEMw_ADDr_indexed_MEM_V4 : MEMInst_V4<(outs),
3605             (ins IntRegs:$base, u6_2Imm:$offset, IntRegs:$addend),
3606             "memw($base+#$offset) += $addend",
3607             [(store (add (load (add (i32 IntRegs:$base), u6_2ImmPred:$offset)),
3608                          (i32 IntRegs:$addend)),
3609                     (add (i32 IntRegs:$base), u6_2ImmPred:$offset))]>,
3610             Requires<[HasV4T, UseMEMOP]>;
3611
3612 // memw(Rs+#u6:2) -= Rt
3613 let AddedComplexity = 30 in
3614 def MEMw_SUBr_indexed_MEM_V4 : MEMInst_V4<(outs),
3615             (ins IntRegs:$base, u6_2Imm:$offset, IntRegs:$subend),
3616             "memw($base+#$offset) -= $subend",
3617             [(store (sub (load (add (i32 IntRegs:$base), u6_2ImmPred:$offset)),
3618                          (i32 IntRegs:$subend)),
3619                     (add (i32 IntRegs:$base), u6_2ImmPred:$offset))]>,
3620             Requires<[HasV4T, UseMEMOP]>;
3621
3622 // memw(Rs+#u6:2) &= Rt
3623 let AddedComplexity = 30 in
3624 def MEMw_ANDr_indexed_MEM_V4 : MEMInst_V4<(outs),
3625             (ins IntRegs:$base, u6_2Imm:$offset, IntRegs:$andend),
3626             "memw($base+#$offset) &= $andend",
3627             [(store (and (load (add (i32 IntRegs:$base), u6_2ImmPred:$offset)),
3628                          (i32 IntRegs:$andend)),
3629                     (add (i32 IntRegs:$base), u6_2ImmPred:$offset))]>,
3630             Requires<[HasV4T, UseMEMOP]>;
3631
3632 // memw(Rs+#u6:2) |= Rt
3633 let AddedComplexity = 30 in
3634 def MEMw_ORr_indexed_MEM_V4 : MEMInst_V4<(outs),
3635             (ins IntRegs:$base, u6_2Imm:$offset, IntRegs:$orend),
3636             "memw($base+#$offset) |= $orend",
3637             [(store (or (load (add (i32 IntRegs:$base), u6_2ImmPred:$offset)),
3638                         (i32 IntRegs:$orend)),
3639                     (add (i32 IntRegs:$base), u6_2ImmPred:$offset))]>,
3640             Requires<[HasV4T, UseMEMOP]>;
3641
3642 // memw(Rs+#u6:2) += #U5
3643 let AddedComplexity = 30 in
3644 def MEMw_ADDi_MEM_V4 : MEMInst_V4<(outs),
3645             (ins MEMri:$addr, u5Imm:$addend),
3646             "memw($addr) += $addend",
3647             []>,
3648             Requires<[HasV4T, UseMEMOP]>;
3649
3650 // memw(Rs+#u6:2) -= #U5
3651 let AddedComplexity = 30 in
3652 def MEMw_SUBi_MEM_V4 : MEMInst_V4<(outs),
3653             (ins MEMri:$addr, u5Imm:$subend),
3654             "memw($addr) -= $subend",
3655             []>,
3656             Requires<[HasV4T, UseMEMOP]>;
3657
3658 // memw(Rs+#u6:2) += Rt
3659 let AddedComplexity = 30 in
3660 def MEMw_ADDr_MEM_V4 : MEMInst_V4<(outs),
3661             (ins MEMri:$addr, IntRegs:$addend),
3662             "memw($addr) += $addend",
3663             [(store (add (load ADDRriU6_2:$addr), (i32 IntRegs:$addend)),
3664                     ADDRriU6_2:$addr)]>,
3665             Requires<[HasV4T, UseMEMOP]>;
3666
3667 // memw(Rs+#u6:2) -= Rt
3668 let AddedComplexity = 30 in
3669 def MEMw_SUBr_MEM_V4 : MEMInst_V4<(outs),
3670             (ins MEMri:$addr, IntRegs:$subend),
3671             "memw($addr) -= $subend",
3672             [(store (sub (load ADDRriU6_2:$addr), (i32 IntRegs:$subend)),
3673                     ADDRriU6_2:$addr)]>,
3674             Requires<[HasV4T, UseMEMOP]>;
3675
3676 // memw(Rs+#u6:2) &= Rt
3677 let AddedComplexity = 30 in
3678 def MEMw_ANDr_MEM_V4 : MEMInst_V4<(outs),
3679             (ins MEMri:$addr, IntRegs:$andend),
3680             "memw($addr) &= $andend",
3681             [(store (and (load ADDRriU6_2:$addr), (i32 IntRegs:$andend)),
3682                     ADDRriU6_2:$addr)]>,
3683             Requires<[HasV4T, UseMEMOP]>;
3684
3685 // memw(Rs+#u6:2) |= Rt
3686 let AddedComplexity = 30 in
3687 def MEMw_ORr_MEM_V4 : MEMInst_V4<(outs),
3688             (ins MEMri:$addr, IntRegs:$orend),
3689             "memw($addr) |= $orend",
3690             [(store (or (load ADDRriU6_2:$addr), (i32 IntRegs:$orend)),
3691                     ADDRriU6_2:$addr)]>,
3692             Requires<[HasV4T, UseMEMOP]>;
3693
3694 //===----------------------------------------------------------------------===//
3695 // MEMOP: Halfword
3696 //
3697 //  Implemented:
3698 //     MEMh_ADDi_indexed_V4  : memw(Rs+#u6:2)+=#U5
3699 //     MEMh_SUBi_indexed_V4  : memw(Rs+#u6:2)-=#U5
3700 //     MEMh_ADDr_indexed_V4  : memw(Rs+#u6:2)+=Rt
3701 //     MEMh_SUBr_indexed_V4  : memw(Rs+#u6:2)-=Rt
3702 //     MEMh_CLRr_indexed_V4  : memw(Rs+#u6:2)&=Rt
3703 //     MEMh_SETr_indexed_V4  : memw(Rs+#u6:2)|=Rt
3704 //     MEMh_ADDi_V4          : memw(Rs+#u6:2)+=#U5
3705 //     MEMh_SUBi_V4          : memw(Rs+#u6:2)-=#U5
3706 //     MEMh_ADDr_V4          : memw(Rs+#u6:2)+=Rt
3707 //     MEMh_SUBr_V4          : memw(Rs+#u6:2)-=Rt
3708 //     MEMh_CLRr_V4          : memw(Rs+#u6:2)&=Rt
3709 //     MEMh_SETr_V4          : memw(Rs+#u6:2)|=Rt
3710 //
3711 //   Not implemented:
3712 //     MEMh_CLRi_indexed_V4  : memw(Rs+#u6:2)=clrbit(#U5)
3713 //     MEMh_SETi_indexed_V4  : memw(Rs+#u6:2)=setbit(#U5)
3714 //     MEMh_CLRi_V4          : memw(Rs+#u6:2)=clrbit(#U5)
3715 //     MEMh_SETi_V4          : memw(Rs+#u6:2)=setbit(#U5)
3716 //===----------------------------------------------------------------------===//
3717
3718
3719 // memh(Rs+#u6:1) += #U5
3720 let AddedComplexity = 30 in
3721 def MEMh_ADDi_indexed_MEM_V4 : MEMInst_V4<(outs),
3722             (ins IntRegs:$base, u6_1Imm:$offset, u5Imm:$addend),
3723             "memh($base+#$offset) += $addend",
3724             []>,
3725             Requires<[HasV4T, UseMEMOP]>;
3726
3727 // memh(Rs+#u6:1) -= #U5
3728 let AddedComplexity = 30 in
3729 def MEMh_SUBi_indexed_MEM_V4 : MEMInst_V4<(outs),
3730             (ins IntRegs:$base, u6_1Imm:$offset, u5Imm:$subend),
3731             "memh($base+#$offset) -= $subend",
3732             []>,
3733             Requires<[HasV4T, UseMEMOP]>;
3734
3735 // memh(Rs+#u6:1) += Rt
3736 let AddedComplexity = 30 in
3737 def MEMh_ADDr_indexed_MEM_V4 : MEMInst_V4<(outs),
3738             (ins IntRegs:$base, u6_1Imm:$offset, IntRegs:$addend),
3739             "memh($base+#$offset) += $addend",
3740             [(truncstorei16 (add (sextloadi16 (add (i32 IntRegs:$base),
3741                                                    u6_1ImmPred:$offset)),
3742                                  (i32 IntRegs:$addend)),
3743                             (add (i32 IntRegs:$base), u6_1ImmPred:$offset))]>,
3744             Requires<[HasV4T, UseMEMOP]>;
3745
3746 // memh(Rs+#u6:1) -= Rt
3747 let AddedComplexity = 30 in
3748 def MEMh_SUBr_indexed_MEM_V4 : MEMInst_V4<(outs),
3749             (ins IntRegs:$base, u6_1Imm:$offset, IntRegs:$subend),
3750             "memh($base+#$offset) -= $subend",
3751             [(truncstorei16 (sub (sextloadi16 (add (i32 IntRegs:$base),
3752                                                    u6_1ImmPred:$offset)),
3753                                  (i32 IntRegs:$subend)),
3754                             (add (i32 IntRegs:$base), u6_1ImmPred:$offset))]>,
3755             Requires<[HasV4T, UseMEMOP]>;
3756
3757 // memh(Rs+#u6:1) &= Rt
3758 let AddedComplexity = 30 in
3759 def MEMh_ANDr_indexed_MEM_V4 : MEMInst_V4<(outs),
3760             (ins IntRegs:$base, u6_1Imm:$offset, IntRegs:$andend),
3761             "memh($base+#$offset) += $andend",
3762             [(truncstorei16 (and (sextloadi16 (add (i32 IntRegs:$base),
3763                                                    u6_1ImmPred:$offset)),
3764                                  (i32 IntRegs:$andend)),
3765                             (add (i32 IntRegs:$base), u6_1ImmPred:$offset))]>,
3766             Requires<[HasV4T, UseMEMOP]>;
3767
3768 // memh(Rs+#u6:1) |= Rt
3769 let AddedComplexity = 30 in
3770 def MEMh_ORr_indexed_MEM_V4 : MEMInst_V4<(outs),
3771             (ins IntRegs:$base, u6_1Imm:$offset, IntRegs:$orend),
3772             "memh($base+#$offset) |= $orend",
3773             [(truncstorei16 (or (sextloadi16 (add (i32 IntRegs:$base),
3774                                               u6_1ImmPred:$offset)),
3775                              (i32 IntRegs:$orend)),
3776                             (add (i32 IntRegs:$base), u6_1ImmPred:$offset))]>,
3777             Requires<[HasV4T, UseMEMOP]>;
3778
3779 // memh(Rs+#u6:1) += #U5
3780 let AddedComplexity = 30 in
3781 def MEMh_ADDi_MEM_V4 : MEMInst_V4<(outs),
3782             (ins MEMri:$addr, u5Imm:$addend),
3783             "memh($addr) += $addend",
3784             []>,
3785             Requires<[HasV4T, UseMEMOP]>;
3786
3787 // memh(Rs+#u6:1) -= #U5
3788 let AddedComplexity = 30 in
3789 def MEMh_SUBi_MEM_V4 : MEMInst_V4<(outs),
3790             (ins MEMri:$addr, u5Imm:$subend),
3791             "memh($addr) -= $subend",
3792             []>,
3793             Requires<[HasV4T, UseMEMOP]>;
3794
3795 // memh(Rs+#u6:1) += Rt
3796 let AddedComplexity = 30 in
3797 def MEMh_ADDr_MEM_V4 : MEMInst_V4<(outs),
3798             (ins MEMri:$addr, IntRegs:$addend),
3799             "memh($addr) += $addend",
3800             [(truncstorei16 (add (sextloadi16 ADDRriU6_1:$addr),
3801                                  (i32 IntRegs:$addend)), ADDRriU6_1:$addr)]>,
3802             Requires<[HasV4T, UseMEMOP]>;
3803
3804 // memh(Rs+#u6:1) -= Rt
3805 let AddedComplexity = 30 in
3806 def MEMh_SUBr_MEM_V4 : MEMInst_V4<(outs),
3807             (ins MEMri:$addr, IntRegs:$subend),
3808             "memh($addr) -= $subend",
3809             [(truncstorei16 (sub (sextloadi16 ADDRriU6_1:$addr),
3810                                  (i32 IntRegs:$subend)), ADDRriU6_1:$addr)]>,
3811             Requires<[HasV4T, UseMEMOP]>;
3812
3813 // memh(Rs+#u6:1) &= Rt
3814 let AddedComplexity = 30 in
3815 def MEMh_ANDr_MEM_V4 : MEMInst_V4<(outs),
3816             (ins MEMri:$addr, IntRegs:$andend),
3817             "memh($addr) &= $andend",
3818             [(truncstorei16 (and (sextloadi16 ADDRriU6_1:$addr),
3819                                  (i32 IntRegs:$andend)), ADDRriU6_1:$addr)]>,
3820             Requires<[HasV4T, UseMEMOP]>;
3821
3822 // memh(Rs+#u6:1) |= Rt
3823 let AddedComplexity = 30 in
3824 def MEMh_ORr_MEM_V4 : MEMInst_V4<(outs),
3825             (ins MEMri:$addr, IntRegs:$orend),
3826             "memh($addr) |= $orend",
3827             [(truncstorei16 (or (sextloadi16 ADDRriU6_1:$addr),
3828                                 (i32 IntRegs:$orend)), ADDRriU6_1:$addr)]>,
3829             Requires<[HasV4T, UseMEMOP]>;
3830
3831
3832 //===----------------------------------------------------------------------===//
3833 // MEMOP: Byte
3834 //
3835 //  Implemented:
3836 //     MEMb_ADDi_indexed_V4  : memb(Rs+#u6:0)+=#U5
3837 //     MEMb_SUBi_indexed_V4  : memb(Rs+#u6:0)-=#U5
3838 //     MEMb_ADDr_indexed_V4  : memb(Rs+#u6:0)+=Rt
3839 //     MEMb_SUBr_indexed_V4  : memb(Rs+#u6:0)-=Rt
3840 //     MEMb_CLRr_indexed_V4  : memb(Rs+#u6:0)&=Rt
3841 //     MEMb_SETr_indexed_V4  : memb(Rs+#u6:0)|=Rt
3842 //     MEMb_ADDi_V4          : memb(Rs+#u6:0)+=#U5
3843 //     MEMb_SUBi_V4          : memb(Rs+#u6:0)-=#U5
3844 //     MEMb_ADDr_V4          : memb(Rs+#u6:0)+=Rt
3845 //     MEMb_SUBr_V4          : memb(Rs+#u6:0)-=Rt
3846 //     MEMb_CLRr_V4          : memb(Rs+#u6:0)&=Rt
3847 //     MEMb_SETr_V4          : memb(Rs+#u6:0)|=Rt
3848 //
3849 //   Not implemented:
3850 //     MEMb_CLRi_indexed_V4  : memb(Rs+#u6:0)=clrbit(#U5)
3851 //     MEMb_SETi_indexed_V4  : memb(Rs+#u6:0)=setbit(#U5)
3852 //     MEMb_CLRi_V4          : memb(Rs+#u6:0)=clrbit(#U5)
3853 //     MEMb_SETi_V4          : memb(Rs+#u6:0)=setbit(#U5)
3854 //===----------------------------------------------------------------------===//
3855
3856 // memb(Rs+#u6:0) += #U5
3857 let AddedComplexity = 30 in
3858 def MEMb_ADDi_indexed_MEM_V4 : MEMInst_V4<(outs),
3859             (ins IntRegs:$base, u6_0Imm:$offset, u5Imm:$addend),
3860             "memb($base+#$offset) += $addend",
3861             []>,
3862             Requires<[HasV4T, UseMEMOP]>;
3863
3864 // memb(Rs+#u6:0) -= #U5
3865 let AddedComplexity = 30 in
3866 def MEMb_SUBi_indexed_MEM_V4 : MEMInst_V4<(outs),
3867             (ins IntRegs:$base, u6_0Imm:$offset, u5Imm:$subend),
3868             "memb($base+#$offset) -= $subend",
3869             []>,
3870             Requires<[HasV4T, UseMEMOP]>;
3871
3872 // memb(Rs+#u6:0) += Rt
3873 let AddedComplexity = 30 in
3874 def MEMb_ADDr_indexed_MEM_V4 : MEMInst_V4<(outs),
3875             (ins IntRegs:$base, u6_0Imm:$offset, IntRegs:$addend),
3876             "memb($base+#$offset) += $addend",
3877             [(truncstorei8 (add (sextloadi8 (add (i32 IntRegs:$base),
3878                                                  u6_0ImmPred:$offset)),
3879                                 (i32 IntRegs:$addend)),
3880                            (add (i32 IntRegs:$base), u6_0ImmPred:$offset))]>,
3881             Requires<[HasV4T, UseMEMOP]>;
3882
3883 // memb(Rs+#u6:0) -= Rt
3884 let AddedComplexity = 30 in
3885 def MEMb_SUBr_indexed_MEM_V4 : MEMInst_V4<(outs),
3886             (ins IntRegs:$base, u6_0Imm:$offset, IntRegs:$subend),
3887             "memb($base+#$offset) -= $subend",
3888             [(truncstorei8 (sub (sextloadi8 (add (i32 IntRegs:$base),
3889                                                  u6_0ImmPred:$offset)),
3890                                 (i32 IntRegs:$subend)),
3891                            (add (i32 IntRegs:$base), u6_0ImmPred:$offset))]>,
3892             Requires<[HasV4T, UseMEMOP]>;
3893
3894 // memb(Rs+#u6:0) &= Rt
3895 let AddedComplexity = 30 in
3896 def MEMb_ANDr_indexed_MEM_V4 : MEMInst_V4<(outs),
3897             (ins IntRegs:$base, u6_0Imm:$offset, IntRegs:$andend),
3898             "memb($base+#$offset) += $andend",
3899             [(truncstorei8 (and (sextloadi8 (add (i32 IntRegs:$base),
3900                                                  u6_0ImmPred:$offset)),
3901                                 (i32 IntRegs:$andend)),
3902                            (add (i32 IntRegs:$base), u6_0ImmPred:$offset))]>,
3903             Requires<[HasV4T, UseMEMOP]>;
3904
3905 // memb(Rs+#u6:0) |= Rt
3906 let AddedComplexity = 30 in
3907 def MEMb_ORr_indexed_MEM_V4 : MEMInst_V4<(outs),
3908             (ins IntRegs:$base, u6_0Imm:$offset, IntRegs:$orend),
3909             "memb($base+#$offset) |= $orend",
3910             [(truncstorei8 (or (sextloadi8 (add (i32 IntRegs:$base),
3911                                                 u6_0ImmPred:$offset)),
3912                                (i32 IntRegs:$orend)),
3913                            (add (i32 IntRegs:$base), u6_0ImmPred:$offset))]>,
3914             Requires<[HasV4T, UseMEMOP]>;
3915
3916 // memb(Rs+#u6:0) += #U5
3917 let AddedComplexity = 30 in
3918 def MEMb_ADDi_MEM_V4 : MEMInst_V4<(outs),
3919             (ins MEMri:$addr, u5Imm:$addend),
3920             "memb($addr) += $addend",
3921             []>,
3922             Requires<[HasV4T, UseMEMOP]>;
3923
3924 // memb(Rs+#u6:0) -= #U5
3925 let AddedComplexity = 30 in
3926 def MEMb_SUBi_MEM_V4 : MEMInst_V4<(outs),
3927             (ins MEMri:$addr, u5Imm:$subend),
3928             "memb($addr) -= $subend",
3929             []>,
3930             Requires<[HasV4T, UseMEMOP]>;
3931
3932 // memb(Rs+#u6:0) += Rt
3933 let AddedComplexity = 30 in
3934 def MEMb_ADDr_MEM_V4 : MEMInst_V4<(outs),
3935             (ins MEMri:$addr, IntRegs:$addend),
3936             "memb($addr) += $addend",
3937             [(truncstorei8 (add (sextloadi8 ADDRriU6_0:$addr),
3938                                 (i32 IntRegs:$addend)), ADDRriU6_0:$addr)]>,
3939             Requires<[HasV4T, UseMEMOP]>;
3940
3941 // memb(Rs+#u6:0) -= Rt
3942 let AddedComplexity = 30 in
3943 def MEMb_SUBr_MEM_V4 : MEMInst_V4<(outs),
3944             (ins MEMri:$addr, IntRegs:$subend),
3945             "memb($addr) -= $subend",
3946             [(truncstorei8 (sub (sextloadi8 ADDRriU6_0:$addr),
3947                                 (i32 IntRegs:$subend)), ADDRriU6_0:$addr)]>,
3948             Requires<[HasV4T, UseMEMOP]>;
3949
3950 // memb(Rs+#u6:0) &= Rt
3951 let AddedComplexity = 30 in
3952 def MEMb_ANDr_MEM_V4 : MEMInst_V4<(outs),
3953             (ins MEMri:$addr, IntRegs:$andend),
3954             "memb($addr) &= $andend",
3955             [(truncstorei8 (and (sextloadi8 ADDRriU6_0:$addr),
3956                                 (i32 IntRegs:$andend)), ADDRriU6_0:$addr)]>,
3957             Requires<[HasV4T, UseMEMOP]>;
3958
3959 // memb(Rs+#u6:0) |= Rt
3960 let AddedComplexity = 30 in
3961 def MEMb_ORr_MEM_V4 : MEMInst_V4<(outs),
3962             (ins MEMri:$addr, IntRegs:$orend),
3963             "memb($addr) |= $orend",
3964             [(truncstorei8 (or (sextloadi8 ADDRriU6_0:$addr),
3965                                (i32 IntRegs:$orend)), ADDRriU6_0:$addr)]>,
3966             Requires<[HasV4T, UseMEMOP]>;
3967
3968
3969 //===----------------------------------------------------------------------===//
3970 // XTYPE/PRED +
3971 //===----------------------------------------------------------------------===//
3972
3973 // Hexagon V4 only supports these flavors of byte/half compare instructions:
3974 // EQ/GT/GTU. Other flavors like GE/GEU/LT/LTU/LE/LEU are not supported by
3975 // hardware. However, compiler can still implement these patterns through
3976 // appropriate patterns combinations based on current implemented patterns.
3977 // The implemented patterns are: EQ/GT/GTU.
3978 // Missing patterns are: GE/GEU/LT/LTU/LE/LEU.
3979
3980 // Following instruction is not being extended as it results into the
3981 // incorrect code for negative numbers.
3982 // Pd=cmpb.eq(Rs,#u8)
3983
3984 let isCompare = 1 in
3985 def CMPbEQri_V4 : MInst<(outs PredRegs:$dst),
3986             (ins IntRegs:$src1, u8Imm:$src2),
3987             "$dst = cmpb.eq($src1, #$src2)",
3988             [(set (i1 PredRegs:$dst),
3989                   (seteq (and (i32 IntRegs:$src1), 255), u8ImmPred:$src2))]>,
3990             Requires<[HasV4T]>;
3991
3992 // Pd=cmpb.eq(Rs,Rt)
3993 let isCompare = 1 in
3994 def CMPbEQrr_ubub_V4 : MInst<(outs PredRegs:$dst),
3995             (ins IntRegs:$src1, IntRegs:$src2),
3996             "$dst = cmpb.eq($src1, $src2)",
3997             [(set (i1 PredRegs:$dst),
3998                   (seteq (and (xor (i32 IntRegs:$src1),
3999                                    (i32 IntRegs:$src2)), 255), 0))]>,
4000             Requires<[HasV4T]>;
4001
4002 // Pd=cmpb.eq(Rs,Rt)
4003 let isCompare = 1 in
4004 def CMPbEQrr_sbsb_V4 : MInst<(outs PredRegs:$dst),
4005             (ins IntRegs:$src1, IntRegs:$src2),
4006             "$dst = cmpb.eq($src1, $src2)",
4007             [(set (i1 PredRegs:$dst),
4008                   (seteq (shl (i32 IntRegs:$src1), (i32 24)),
4009                          (shl (i32 IntRegs:$src2), (i32 24))))]>,
4010             Requires<[HasV4T]>;
4011
4012 // Pd=cmpb.gt(Rs,Rt)
4013 let isCompare = 1 in
4014 def CMPbGTrr_V4 : MInst<(outs PredRegs:$dst),
4015             (ins IntRegs:$src1, IntRegs:$src2),
4016             "$dst = cmpb.gt($src1, $src2)",
4017             [(set (i1 PredRegs:$dst),
4018                   (setgt (shl (i32 IntRegs:$src1), (i32 24)),
4019                          (shl (i32 IntRegs:$src2), (i32 24))))]>,
4020             Requires<[HasV4T]>;
4021
4022 // Pd=cmpb.gtu(Rs,#u7)
4023 let isCompare = 1 in
4024 def CMPbGTUri_V4 : MInst<(outs PredRegs:$dst),
4025             (ins IntRegs:$src1, u7Imm:$src2),
4026             "$dst = cmpb.gtu($src1, #$src2)",
4027             [(set (i1 PredRegs:$dst), (setugt (and (i32 IntRegs:$src1), 255),
4028                                               u7ImmPred:$src2))]>,
4029             Requires<[HasV4T]>;
4030
4031 // Pd=cmpb.gtu(Rs,Rt)
4032 let isCompare = 1 in
4033 def CMPbGTUrr_V4 : MInst<(outs PredRegs:$dst),
4034             (ins IntRegs:$src1, IntRegs:$src2),
4035             "$dst = cmpb.gtu($src1, $src2)",
4036             [(set (i1 PredRegs:$dst), (setugt (and (i32 IntRegs:$src1), 255),
4037                                              (and (i32 IntRegs:$src2), 255)))]>,
4038             Requires<[HasV4T]>;
4039
4040 // Following instruction is not being extended as it results into the incorrect
4041 // code for negative numbers.
4042
4043 // Signed half compare(.eq) ri.
4044 // Pd=cmph.eq(Rs,#s8)
4045 let isCompare = 1 in
4046 def CMPhEQri_V4 : MInst<(outs PredRegs:$dst),
4047             (ins IntRegs:$src1, s8Imm:$src2),
4048             "$dst = cmph.eq($src1, #$src2)",
4049             [(set (i1 PredRegs:$dst), (seteq (and (i32 IntRegs:$src1), 65535),
4050                                              s8ImmPred:$src2))]>,
4051             Requires<[HasV4T]>;
4052
4053 // Signed half compare(.eq) rr.
4054 // Case 1: xor + and, then compare:
4055 //   r0=xor(r0,r1)
4056 //   r0=and(r0,#0xffff)
4057 //   p0=cmp.eq(r0,#0)
4058 // Pd=cmph.eq(Rs,Rt)
4059 let isCompare = 1 in
4060 def CMPhEQrr_xor_V4 : MInst<(outs PredRegs:$dst),
4061             (ins IntRegs:$src1, IntRegs:$src2),
4062             "$dst = cmph.eq($src1, $src2)",
4063             [(set (i1 PredRegs:$dst), (seteq (and (xor (i32 IntRegs:$src1),
4064                                                        (i32 IntRegs:$src2)),
4065                                                   65535), 0))]>,
4066             Requires<[HasV4T]>;
4067
4068 // Signed half compare(.eq) rr.
4069 // Case 2: shift left 16 bits then compare:
4070 //   r0=asl(r0,16)
4071 //   r1=asl(r1,16)
4072 //   p0=cmp.eq(r0,r1)
4073 // Pd=cmph.eq(Rs,Rt)
4074 let isCompare = 1 in
4075 def CMPhEQrr_shl_V4 : MInst<(outs PredRegs:$dst),
4076             (ins IntRegs:$src1, IntRegs:$src2),
4077             "$dst = cmph.eq($src1, $src2)",
4078             [(set (i1 PredRegs:$dst),
4079                   (seteq (shl (i32 IntRegs:$src1), (i32 16)),
4080                          (shl (i32 IntRegs:$src2), (i32 16))))]>,
4081             Requires<[HasV4T]>;
4082
4083 /* Incorrect Pattern -- immediate should be right shifted before being
4084 used in the cmph.gt instruction.
4085 // Signed half compare(.gt) ri.
4086 // Pd=cmph.gt(Rs,#s8)
4087
4088 let isCompare = 1 in
4089 def CMPhGTri_V4 : MInst<(outs PredRegs:$dst),
4090             (ins IntRegs:$src1, s8Imm:$src2),
4091             "$dst = cmph.gt($src1, #$src2)",
4092             [(set (i1 PredRegs:$dst),
4093                   (setgt (shl (i32 IntRegs:$src1), (i32 16)),
4094                          s8ImmPred:$src2))]>,
4095             Requires<[HasV4T]>;
4096 */
4097
4098 // Signed half compare(.gt) rr.
4099 // Pd=cmph.gt(Rs,Rt)
4100 let isCompare = 1 in
4101 def CMPhGTrr_shl_V4 : MInst<(outs PredRegs:$dst),
4102             (ins IntRegs:$src1, IntRegs:$src2),
4103             "$dst = cmph.gt($src1, $src2)",
4104             [(set (i1 PredRegs:$dst),
4105                   (setgt (shl (i32 IntRegs:$src1), (i32 16)),
4106                          (shl (i32 IntRegs:$src2), (i32 16))))]>,
4107             Requires<[HasV4T]>;
4108
4109 // Unsigned half compare rr (.gtu).
4110 // Pd=cmph.gtu(Rs,Rt)
4111 let isCompare = 1 in
4112 def CMPhGTUrr_V4 : MInst<(outs PredRegs:$dst),
4113             (ins IntRegs:$src1, IntRegs:$src2),
4114             "$dst = cmph.gtu($src1, $src2)",
4115             [(set (i1 PredRegs:$dst),
4116                   (setugt (and (i32 IntRegs:$src1), 65535),
4117                           (and (i32 IntRegs:$src2), 65535)))]>,
4118             Requires<[HasV4T]>;
4119
4120 // Unsigned half compare ri (.gtu).
4121 // Pd=cmph.gtu(Rs,#u7)
4122 let isCompare = 1 in
4123 def CMPhGTUri_V4 : MInst<(outs PredRegs:$dst),
4124             (ins IntRegs:$src1, u7Imm:$src2),
4125             "$dst = cmph.gtu($src1, #$src2)",
4126             [(set (i1 PredRegs:$dst), (setugt (and (i32 IntRegs:$src1), 65535),
4127                                               u7ImmPred:$src2))]>,
4128             Requires<[HasV4T]>;
4129
4130 //===----------------------------------------------------------------------===//
4131 // XTYPE/PRED -
4132 //===----------------------------------------------------------------------===//
4133
4134 //Deallocate frame and return.
4135 //    dealloc_return
4136 let isReturn = 1, isTerminator = 1, isBarrier = 1, isPredicable = 1,
4137   Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1 in {
4138   def DEALLOC_RET_V4 : NVInst_V4<(outs), (ins i32imm:$amt1),
4139             "dealloc_return",
4140             []>,
4141             Requires<[HasV4T]>;
4142 }
4143
4144 // Restore registers and dealloc return function call.
4145 let isCall = 1, isBarrier = 1, isReturn = 1, isTerminator = 1,
4146   Defs = [R29, R30, R31, PC] in {
4147   def RESTORE_DEALLOC_RET_JMP_V4 : JInst<(outs),
4148                                    (ins calltarget:$dst),
4149              "jump $dst // Restore_and_dealloc_return",
4150              []>,
4151              Requires<[HasV4T]>;
4152 }
4153
4154 // Restore registers and dealloc frame before a tail call.
4155 let isCall = 1, isBarrier = 1,
4156   Defs = [R29, R30, R31, PC] in {
4157   def RESTORE_DEALLOC_BEFORE_TAILCALL_V4 : JInst<(outs),
4158                                            (ins calltarget:$dst),
4159              "call $dst // Restore_and_dealloc_before_tailcall",
4160              []>,
4161              Requires<[HasV4T]>;
4162 }
4163
4164 // Save registers function call.
4165 let isCall = 1, isBarrier = 1,
4166   Uses = [R29, R31] in {
4167   def SAVE_REGISTERS_CALL_V4 : JInst<(outs),
4168                                (ins calltarget:$dst),
4169              "call $dst // Save_calle_saved_registers",
4170              []>,
4171              Requires<[HasV4T]>;
4172 }
4173
4174 //    if (Ps) dealloc_return
4175 let isReturn = 1, isTerminator = 1,
4176     Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1,
4177     isPredicated = 1 in {
4178   def DEALLOC_RET_cPt_V4 : NVInst_V4<(outs),
4179                            (ins PredRegs:$src1, i32imm:$amt1),
4180             "if ($src1) dealloc_return",
4181             []>,
4182             Requires<[HasV4T]>;
4183 }
4184
4185 //    if (!Ps) dealloc_return
4186 let isReturn = 1, isTerminator = 1,
4187     Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1,
4188     isPredicated = 1 in {
4189   def DEALLOC_RET_cNotPt_V4 : NVInst_V4<(outs), (ins PredRegs:$src1,
4190                                                      i32imm:$amt1),
4191             "if (!$src1) dealloc_return",
4192             []>,
4193             Requires<[HasV4T]>;
4194 }
4195
4196 //    if (Ps.new) dealloc_return:nt
4197 let isReturn = 1, isTerminator = 1,
4198     Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1,
4199     isPredicated = 1 in {
4200   def DEALLOC_RET_cdnPnt_V4 : NVInst_V4<(outs), (ins PredRegs:$src1,
4201                                                      i32imm:$amt1),
4202             "if ($src1.new) dealloc_return:nt",
4203             []>,
4204             Requires<[HasV4T]>;
4205 }
4206
4207 //    if (!Ps.new) dealloc_return:nt
4208 let isReturn = 1, isTerminator = 1,
4209     Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1,
4210     isPredicated = 1 in {
4211   def DEALLOC_RET_cNotdnPnt_V4 : NVInst_V4<(outs), (ins PredRegs:$src1,
4212                                                         i32imm:$amt1),
4213             "if (!$src1.new) dealloc_return:nt",
4214             []>,
4215             Requires<[HasV4T]>;
4216 }
4217
4218 //    if (Ps.new) dealloc_return:t
4219 let isReturn = 1, isTerminator = 1,
4220     Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1,
4221     isPredicated = 1 in {
4222   def DEALLOC_RET_cdnPt_V4 : NVInst_V4<(outs), (ins PredRegs:$src1,
4223                                                     i32imm:$amt1),
4224             "if ($src1.new) dealloc_return:t",
4225             []>,
4226             Requires<[HasV4T]>;
4227 }
4228
4229 //    if (!Ps.new) dealloc_return:nt
4230 let isReturn = 1, isTerminator = 1,
4231     Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1,
4232     isPredicated = 1 in {
4233   def DEALLOC_RET_cNotdnPt_V4 : NVInst_V4<(outs), (ins PredRegs:$src1,
4234                                                        i32imm:$amt1),
4235             "if (!$src1.new) dealloc_return:t",
4236             []>,
4237             Requires<[HasV4T]>;
4238 }
4239
4240
4241 // Load/Store with absolute addressing mode
4242 // memw(#u6)=Rt
4243
4244 multiclass ST_abs<string OpcStr> {
4245   let isPredicable = 1 in
4246   def _abs_V4 : STInst2<(outs),
4247             (ins globaladdress:$absaddr, IntRegs:$src),
4248             !strconcat(OpcStr, "(##$absaddr) = $src"),
4249             []>,
4250             Requires<[HasV4T]>;
4251
4252   let isPredicated = 1 in
4253   def _abs_cPt_V4 : STInst2<(outs),
4254             (ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2),
4255             !strconcat("if ($src1)",
4256             !strconcat(OpcStr, "(##$absaddr) = $src2")),
4257             []>,
4258             Requires<[HasV4T]>;
4259
4260   let isPredicated = 1 in
4261   def _abs_cNotPt_V4 : STInst2<(outs),
4262             (ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2),
4263             !strconcat("if (!$src1)",
4264             !strconcat(OpcStr, "(##$absaddr) = $src2")),
4265             []>,
4266             Requires<[HasV4T]>;
4267
4268   let isPredicated = 1 in
4269   def _abs_cdnPt_V4 : STInst2<(outs),
4270             (ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2),
4271             !strconcat("if ($src1.new)",
4272             !strconcat(OpcStr, "(##$absaddr) = $src2")),
4273             []>,
4274             Requires<[HasV4T]>;
4275
4276   let isPredicated = 1 in
4277   def _abs_cdnNotPt_V4 : STInst2<(outs),
4278             (ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2),
4279             !strconcat("if (!$src1.new)",
4280             !strconcat(OpcStr, "(##$absaddr) = $src2")),
4281             []>,
4282             Requires<[HasV4T]>;
4283
4284   def _abs_nv_V4 : STInst2<(outs),
4285             (ins globaladdress:$absaddr, IntRegs:$src),
4286             !strconcat(OpcStr, "(##$absaddr) = $src.new"),
4287             []>,
4288             Requires<[HasV4T]>;
4289
4290   let isPredicated = 1 in
4291   def _abs_cPt_nv_V4 : STInst2<(outs),
4292             (ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2),
4293             !strconcat("if ($src1)",
4294             !strconcat(OpcStr, "(##$absaddr) = $src2.new")),
4295             []>,
4296             Requires<[HasV4T]>;
4297
4298   let isPredicated = 1 in
4299   def _abs_cNotPt_nv_V4 : STInst2<(outs),
4300             (ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2),
4301             !strconcat("if (!$src1)",
4302             !strconcat(OpcStr, "(##$absaddr) = $src2.new")),
4303             []>,
4304             Requires<[HasV4T]>;
4305
4306   let isPredicated = 1 in
4307   def _abs_cdnPt_nv_V4 : STInst2<(outs),
4308             (ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2),
4309             !strconcat("if ($src1.new)",
4310             !strconcat(OpcStr, "(##$absaddr) = $src2.new")),
4311             []>,
4312             Requires<[HasV4T]>;
4313
4314   let isPredicated = 1 in
4315   def _abs_cdnNotPt_nv_V4 : STInst2<(outs),
4316             (ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2),
4317             !strconcat("if (!$src1.new)",
4318             !strconcat(OpcStr, "(##$absaddr) = $src2.new")),
4319             []>,
4320             Requires<[HasV4T]>;
4321 }
4322
4323 let AddedComplexity = 30, isPredicable = 1 in
4324 def STrid_abs_V4 : STInst<(outs),
4325           (ins globaladdress:$absaddr, DoubleRegs:$src),
4326            "memd(##$absaddr) = $src",
4327           [(store (i64 DoubleRegs:$src),
4328                   (HexagonCONST32 tglobaladdr:$absaddr))]>,
4329           Requires<[HasV4T]>;
4330
4331 let AddedComplexity = 30, isPredicated = 1 in
4332 def STrid_abs_cPt_V4 : STInst2<(outs),
4333           (ins PredRegs:$src1, globaladdress:$absaddr, DoubleRegs:$src2),
4334           "if ($src1) memd(##$absaddr) = $src2",
4335           []>,
4336           Requires<[HasV4T]>;
4337
4338 let AddedComplexity = 30, isPredicated = 1 in
4339 def STrid_abs_cNotPt_V4 : STInst2<(outs),
4340           (ins PredRegs:$src1, globaladdress:$absaddr, DoubleRegs:$src2),
4341           "if (!$src1) memd(##$absaddr) = $src2",
4342           []>,
4343           Requires<[HasV4T]>;
4344
4345 let AddedComplexity = 30, isPredicated = 1 in
4346 def STrid_abs_cdnPt_V4 : STInst2<(outs),
4347           (ins PredRegs:$src1, globaladdress:$absaddr, DoubleRegs:$src2),
4348           "if ($src1.new) memd(##$absaddr) = $src2",
4349           []>,
4350           Requires<[HasV4T]>;
4351
4352 let AddedComplexity = 30, isPredicated = 1 in
4353 def STrid_abs_cdnNotPt_V4 : STInst2<(outs),
4354           (ins PredRegs:$src1, globaladdress:$absaddr, DoubleRegs:$src2),
4355           "if (!$src1.new) memd(##$absaddr) = $src2",
4356           []>,
4357           Requires<[HasV4T]>;
4358
4359 defm STrib : ST_abs<"memb">;
4360 defm STrih : ST_abs<"memh">;
4361 defm STriw : ST_abs<"memw">;
4362
4363 let Predicates = [HasV4T], AddedComplexity  = 30 in
4364 def : Pat<(truncstorei8 (i32 IntRegs:$src1),
4365                         (HexagonCONST32 tglobaladdr:$absaddr)),
4366           (STrib_abs_V4 tglobaladdr: $absaddr, IntRegs: $src1)>;
4367
4368 let Predicates = [HasV4T], AddedComplexity  = 30 in
4369 def : Pat<(truncstorei16 (i32 IntRegs:$src1),
4370                           (HexagonCONST32 tglobaladdr:$absaddr)),
4371           (STrih_abs_V4 tglobaladdr: $absaddr, IntRegs: $src1)>;
4372
4373 let Predicates = [HasV4T], AddedComplexity  = 30 in
4374 def : Pat<(store (i32 IntRegs:$src1), (HexagonCONST32 tglobaladdr:$absaddr)),
4375           (STriw_abs_V4 tglobaladdr: $absaddr, IntRegs: $src1)>;
4376
4377
4378 multiclass LD_abs<string OpcStr> {
4379   let isPredicable = 1 in
4380   def _abs_V4 : LDInst2<(outs IntRegs:$dst),
4381             (ins globaladdress:$absaddr),
4382             !strconcat("$dst = ", !strconcat(OpcStr, "(##$absaddr)")),
4383             []>,
4384             Requires<[HasV4T]>;
4385
4386   let isPredicated = 1 in
4387   def _abs_cPt_V4 : LDInst2<(outs IntRegs:$dst),
4388             (ins PredRegs:$src1, globaladdress:$absaddr),
4389             !strconcat("if ($src1) $dst = ",
4390             !strconcat(OpcStr, "(##$absaddr)")),
4391             []>,
4392             Requires<[HasV4T]>;
4393
4394   let isPredicated = 1 in
4395   def _abs_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
4396             (ins PredRegs:$src1, globaladdress:$absaddr),
4397             !strconcat("if (!$src1) $dst = ",
4398             !strconcat(OpcStr, "(##$absaddr)")),
4399             []>,
4400             Requires<[HasV4T]>;
4401
4402   let isPredicated = 1 in
4403   def _abs_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
4404             (ins PredRegs:$src1, globaladdress:$absaddr),
4405             !strconcat("if ($src1.new) $dst = ",
4406             !strconcat(OpcStr, "(##$absaddr)")),
4407             []>,
4408             Requires<[HasV4T]>;
4409
4410   let isPredicated = 1 in
4411   def _abs_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
4412             (ins PredRegs:$src1, globaladdress:$absaddr),
4413             !strconcat("if (!$src1.new) $dst = ",
4414             !strconcat(OpcStr, "(##$absaddr)")),
4415             []>,
4416             Requires<[HasV4T]>;
4417 }
4418
4419 let AddedComplexity = 30 in
4420 def LDrid_abs_V4 : LDInst<(outs DoubleRegs:$dst),
4421           (ins globaladdress:$absaddr),
4422           "$dst = memd(##$absaddr)",
4423           [(set (i64 DoubleRegs:$dst),
4424                 (load (HexagonCONST32 tglobaladdr:$absaddr)))]>,
4425           Requires<[HasV4T]>;
4426
4427 let AddedComplexity = 30, isPredicated = 1 in
4428 def LDrid_abs_cPt_V4 : LDInst2<(outs DoubleRegs:$dst),
4429           (ins PredRegs:$src1, globaladdress:$absaddr),
4430           "if ($src1) $dst = memd(##$absaddr)",
4431           []>,
4432           Requires<[HasV4T]>;
4433
4434 let AddedComplexity = 30, isPredicated = 1 in
4435 def LDrid_abs_cNotPt_V4 : LDInst2<(outs DoubleRegs:$dst),
4436           (ins PredRegs:$src1, globaladdress:$absaddr),
4437           "if (!$src1) $dst = memd(##$absaddr)",
4438           []>,
4439           Requires<[HasV4T]>;
4440
4441 let AddedComplexity = 30, isPredicated = 1 in
4442 def LDrid_abs_cdnPt_V4 : LDInst2<(outs DoubleRegs:$dst),
4443           (ins PredRegs:$src1, globaladdress:$absaddr),
4444           "if ($src1.new) $dst = memd(##$absaddr)",
4445           []>,
4446           Requires<[HasV4T]>;
4447
4448 let AddedComplexity = 30, isPredicated = 1 in
4449 def LDrid_abs_cdnNotPt_V4 : LDInst2<(outs DoubleRegs:$dst),
4450           (ins PredRegs:$src1, globaladdress:$absaddr),
4451           "if (!$src1.new) $dst = memd(##$absaddr)",
4452           []>,
4453           Requires<[HasV4T]>;
4454
4455 defm LDrib : LD_abs<"memb">;
4456 defm LDriub : LD_abs<"memub">;
4457 defm LDrih : LD_abs<"memh">;
4458 defm LDriuh : LD_abs<"memuh">;
4459 defm LDriw : LD_abs<"memw">;
4460
4461
4462 let Predicates = [HasV4T], AddedComplexity  = 30 in
4463 def : Pat<(i32 (load (HexagonCONST32 tglobaladdr:$absaddr))),
4464           (LDriw_abs_V4 tglobaladdr: $absaddr)>;
4465
4466 let Predicates = [HasV4T], AddedComplexity=30 in
4467 def : Pat<(i32 (sextloadi8 (HexagonCONST32 tglobaladdr:$absaddr))),
4468           (LDrib_abs_V4 tglobaladdr:$absaddr)>;
4469
4470 let Predicates = [HasV4T], AddedComplexity=30 in
4471 def : Pat<(i32 (zextloadi8 (HexagonCONST32 tglobaladdr:$absaddr))),
4472           (LDriub_abs_V4 tglobaladdr:$absaddr)>;
4473
4474 let Predicates = [HasV4T], AddedComplexity=30 in
4475 def : Pat<(i32 (sextloadi16 (HexagonCONST32 tglobaladdr:$absaddr))),
4476           (LDrih_abs_V4 tglobaladdr:$absaddr)>;
4477
4478 let Predicates = [HasV4T], AddedComplexity=30 in
4479 def : Pat<(i32 (zextloadi16 (HexagonCONST32 tglobaladdr:$absaddr))),
4480           (LDriuh_abs_V4 tglobaladdr:$absaddr)>;
4481
4482 // Transfer global address into a register
4483 let AddedComplexity=50, isMoveImm = 1, isReMaterializable = 1 in
4484 def TFRI_V4 : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$src1),
4485            "$dst = ##$src1",
4486            [(set IntRegs:$dst, (HexagonCONST32 tglobaladdr:$src1))]>,
4487            Requires<[HasV4T]>;
4488
4489 let AddedComplexity=50, neverHasSideEffects = 1, isPredicated = 1 in
4490 def TFRI_cPt_V4 : ALU32_ri<(outs IntRegs:$dst),
4491                            (ins PredRegs:$src1, globaladdress:$src2),
4492            "if($src1) $dst = ##$src2",
4493            []>,
4494            Requires<[HasV4T]>;
4495
4496 let AddedComplexity=50, neverHasSideEffects = 1, isPredicated = 1 in
4497 def TFRI_cNotPt_V4 : ALU32_ri<(outs IntRegs:$dst),
4498                               (ins PredRegs:$src1, globaladdress:$src2),
4499            "if(!$src1) $dst = ##$src2",
4500            []>,
4501            Requires<[HasV4T]>;
4502
4503 let AddedComplexity=50, neverHasSideEffects = 1, isPredicated = 1 in
4504 def TFRI_cdnPt_V4 : ALU32_ri<(outs IntRegs:$dst),
4505                              (ins PredRegs:$src1, globaladdress:$src2),
4506            "if($src1.new) $dst = ##$src2",
4507            []>,
4508            Requires<[HasV4T]>;
4509
4510 let AddedComplexity=50, neverHasSideEffects = 1, isPredicated = 1 in
4511 def TFRI_cdnNotPt_V4 : ALU32_ri<(outs IntRegs:$dst),
4512                                 (ins PredRegs:$src1, globaladdress:$src2),
4513            "if(!$src1.new) $dst = ##$src2",
4514            []>,
4515            Requires<[HasV4T]>;
4516
4517 let AddedComplexity = 50, Predicates = [HasV4T] in
4518 def : Pat<(HexagonCONST32_GP tglobaladdr:$src1),
4519            (TFRI_V4 tglobaladdr:$src1)>;
4520
4521
4522 // Load - Indirect with long offset: These instructions take global address
4523 // as an operand
4524 let AddedComplexity = 10 in
4525 def LDrid_ind_lo_V4 : LDInst<(outs DoubleRegs:$dst),
4526             (ins IntRegs:$src1, u2Imm:$src2, globaladdress:$offset),
4527             "$dst=memd($src1<<#$src2+##$offset)",
4528             [(set (i64 DoubleRegs:$dst),
4529                   (load (add (shl IntRegs:$src1, u2ImmPred:$src2),
4530                         (HexagonCONST32 tglobaladdr:$offset))))]>,
4531             Requires<[HasV4T]>;
4532
4533 let AddedComplexity = 10 in
4534 multiclass LD_indirect_lo<string OpcStr, PatFrag OpNode> {
4535   def _lo_V4 : LDInst<(outs IntRegs:$dst),
4536             (ins IntRegs:$src1, u2Imm:$src2, globaladdress:$offset),
4537             !strconcat("$dst = ",
4538             !strconcat(OpcStr, "($src1<<#$src2+##$offset)")),
4539             [(set IntRegs:$dst,
4540                   (i32 (OpNode (add (shl IntRegs:$src1, u2ImmPred:$src2),
4541                           (HexagonCONST32 tglobaladdr:$offset)))))]>,
4542             Requires<[HasV4T]>;
4543 }
4544
4545 defm LDrib_ind : LD_indirect_lo<"memb", sextloadi8>;
4546 defm LDriub_ind : LD_indirect_lo<"memub", zextloadi8>;
4547 defm LDrih_ind : LD_indirect_lo<"memh", sextloadi16>;
4548 defm LDriuh_ind : LD_indirect_lo<"memuh", zextloadi16>;
4549 defm LDriw_ind : LD_indirect_lo<"memw", load>;
4550
4551 // Store - Indirect with long offset: These instructions take global address
4552 // as an operand
4553 let AddedComplexity = 10 in
4554 def STrid_ind_lo_V4 : STInst<(outs),
4555             (ins IntRegs:$src1, u2Imm:$src2, globaladdress:$src3,
4556                  DoubleRegs:$src4),
4557             "memd($src1<<#$src2+#$src3) = $src4",
4558             [(store (i64 DoubleRegs:$src4),
4559                  (add (shl IntRegs:$src1, u2ImmPred:$src2),
4560                       (HexagonCONST32 tglobaladdr:$src3)))]>,
4561              Requires<[HasV4T]>;
4562
4563 let AddedComplexity = 10 in
4564 multiclass ST_indirect_lo<string OpcStr, PatFrag OpNode> {
4565   def _lo_V4 : STInst<(outs),
4566             (ins IntRegs:$src1, u2Imm:$src2, globaladdress:$src3,
4567                  IntRegs:$src4),
4568             !strconcat(OpcStr, "($src1<<#$src2+##$src3) = $src4"),
4569             [(OpNode (i32 IntRegs:$src4),
4570                  (add (shl IntRegs:$src1, u2ImmPred:$src2),
4571                       (HexagonCONST32 tglobaladdr:$src3)))]>,
4572              Requires<[HasV4T]>;
4573 }
4574
4575 defm STrib_ind : ST_indirect_lo<"memb", truncstorei8>;
4576 defm STrih_ind : ST_indirect_lo<"memh", truncstorei16>;
4577 defm STriw_ind : ST_indirect_lo<"memw", store>;
4578
4579 // Store - absolute addressing mode: These instruction take constant
4580 // value as the extended operand
4581 multiclass ST_absimm<string OpcStr> {
4582   let isPredicable = 1 in
4583   def _abs_V4 : STInst2<(outs),
4584             (ins u6Imm:$src1, IntRegs:$src2),
4585             !strconcat(OpcStr, "(#$src1) = $src2"),
4586             []>,
4587             Requires<[HasV4T]>;
4588
4589   let isPredicated = 1 in
4590   def _abs_cPt_V4 : STInst2<(outs),
4591             (ins PredRegs:$src1, u6Imm:$src2, IntRegs:$src3),
4592             !strconcat("if ($src1)", !strconcat(OpcStr, "(#$src2) = $src3")),
4593             []>,
4594             Requires<[HasV4T]>;
4595
4596   let isPredicated = 1 in
4597   def _abs_cNotPt_V4 : STInst2<(outs),
4598             (ins PredRegs:$src1, u6Imm:$src2, IntRegs:$src3),
4599             !strconcat("if (!$src1)", !strconcat(OpcStr, "(#$src2) = $src3")),
4600             []>,
4601             Requires<[HasV4T]>;
4602
4603   let isPredicated = 1 in
4604   def _abs_cdnPt_V4 : STInst2<(outs),
4605             (ins PredRegs:$src1, u6Imm:$src2, IntRegs:$src3),
4606             !strconcat("if ($src1.new)",
4607             !strconcat(OpcStr, "(#$src2) = $src3")),
4608             []>,
4609             Requires<[HasV4T]>;
4610
4611   let isPredicated = 1 in
4612   def _abs_cdnNotPt_V4 : STInst2<(outs),
4613             (ins PredRegs:$src1, u6Imm:$src2, IntRegs:$src3),
4614             !strconcat("if (!$src1.new)",
4615             !strconcat(OpcStr, "(#$src2) = $src3")),
4616             []>,
4617             Requires<[HasV4T]>;
4618
4619   def _abs_nv_V4 : STInst2<(outs),
4620             (ins u6Imm:$src1, IntRegs:$src2),
4621             !strconcat(OpcStr, "(#$src1) = $src2.new"),
4622             []>,
4623             Requires<[HasV4T]>;
4624
4625   let isPredicated = 1 in
4626   def _abs_cPt_nv_V4 : STInst2<(outs),
4627             (ins PredRegs:$src1, u6Imm:$src2, IntRegs:$src3),
4628             !strconcat("if ($src1)",
4629             !strconcat(OpcStr, "(#$src2) = $src3.new")),
4630             []>,
4631             Requires<[HasV4T]>;
4632
4633   let isPredicated = 1 in
4634   def _abs_cNotPt_nv_V4 : STInst2<(outs),
4635             (ins PredRegs:$src1, u6Imm:$src2, IntRegs:$src3),
4636             !strconcat("if (!$src1)",
4637             !strconcat(OpcStr, "(#$src2) = $src3.new")),
4638             []>,
4639             Requires<[HasV4T]>;
4640
4641   let isPredicated = 1 in
4642   def _abs_cdnPt_nv_V4 : STInst2<(outs),
4643             (ins PredRegs:$src1, u6Imm:$src2, IntRegs:$src3),
4644             !strconcat("if ($src1.new)",
4645             !strconcat(OpcStr, "(#$src2) = $src3.new")),
4646             []>,
4647             Requires<[HasV4T]>;
4648
4649   let isPredicated = 1 in
4650   def _abs_cdnNotPt_nv_V4 : STInst2<(outs),
4651             (ins PredRegs:$src1, u6Imm:$src2, IntRegs:$src3),
4652             !strconcat("if (!$src1.new)",
4653             !strconcat(OpcStr, "(#$src2) = $src3.new")),
4654             []>,
4655             Requires<[HasV4T]>;
4656 }
4657
4658 defm STrib_imm : ST_absimm<"memb">;
4659 defm STrih_imm : ST_absimm<"memh">;
4660 defm STriw_imm : ST_absimm<"memw">;
4661
4662 let Predicates = [HasV4T], AddedComplexity  = 30 in
4663 def : Pat<(truncstorei8 (i32 IntRegs:$src1), u6ImmPred:$src2),
4664           (STrib_imm_abs_V4 u6ImmPred:$src2, IntRegs: $src1)>;
4665
4666 let Predicates = [HasV4T], AddedComplexity  = 30 in
4667 def : Pat<(truncstorei16 (i32 IntRegs:$src1), u6ImmPred:$src2),
4668           (STrih_imm_abs_V4 u6ImmPred:$src2, IntRegs: $src1)>;
4669
4670 let Predicates = [HasV4T], AddedComplexity  = 30 in
4671 def : Pat<(store (i32 IntRegs:$src1), u6ImmPred:$src2),
4672           (STriw_imm_abs_V4 u6ImmPred:$src2, IntRegs: $src1)>;
4673
4674
4675 // Load - absolute addressing mode: These instruction take constant
4676 // value as the extended operand
4677
4678 multiclass LD_absimm<string OpcStr> {
4679   let isPredicable = 1 in
4680   def _abs_V4 : LDInst2<(outs IntRegs:$dst),
4681             (ins u6Imm:$src),
4682             !strconcat("$dst = ",
4683             !strconcat(OpcStr, "(#$src)")),
4684             []>,
4685             Requires<[HasV4T]>;
4686
4687   let isPredicated = 1 in
4688   def _abs_cPt_V4 : LDInst2<(outs IntRegs:$dst),
4689             (ins PredRegs:$src1, u6Imm:$src2),
4690             !strconcat("if ($src1) $dst = ",
4691             !strconcat(OpcStr, "(#$src2)")),
4692             []>,
4693             Requires<[HasV4T]>;
4694
4695   let isPredicated = 1 in
4696   def _abs_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
4697             (ins PredRegs:$src1, u6Imm:$src2),
4698             !strconcat("if (!$src1) $dst = ",
4699             !strconcat(OpcStr, "(#$src2)")),
4700             []>,
4701             Requires<[HasV4T]>;
4702
4703   let isPredicated = 1 in
4704   def _abs_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
4705             (ins PredRegs:$src1, u6Imm:$src2),
4706             !strconcat("if ($src1.new) $dst = ",
4707             !strconcat(OpcStr, "(#$src2)")),
4708             []>,
4709             Requires<[HasV4T]>;
4710
4711   let isPredicated = 1 in
4712   def _abs_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
4713             (ins PredRegs:$src1, u6Imm:$src2),
4714             !strconcat("if (!$src1.new) $dst = ",
4715             !strconcat(OpcStr, "(#$src2)")),
4716             []>,
4717             Requires<[HasV4T]>;
4718 }
4719
4720 defm LDrib_imm : LD_absimm<"memb">;
4721 defm LDriub_imm : LD_absimm<"memub">;
4722 defm LDrih_imm : LD_absimm<"memh">;
4723 defm LDriuh_imm : LD_absimm<"memuh">;
4724 defm LDriw_imm : LD_absimm<"memw">;
4725
4726 let Predicates = [HasV4T], AddedComplexity  = 30 in
4727 def : Pat<(i32 (load u6ImmPred:$src)),
4728           (LDriw_imm_abs_V4 u6ImmPred:$src)>;
4729
4730 let Predicates = [HasV4T], AddedComplexity=30 in
4731 def : Pat<(i32 (sextloadi8 u6ImmPred:$src)),
4732           (LDrib_imm_abs_V4 u6ImmPred:$src)>;
4733
4734 let Predicates = [HasV4T], AddedComplexity=30 in
4735 def : Pat<(i32 (zextloadi8 u6ImmPred:$src)),
4736           (LDriub_imm_abs_V4 u6ImmPred:$src)>;
4737
4738 let Predicates = [HasV4T], AddedComplexity=30 in
4739 def : Pat<(i32 (sextloadi16 u6ImmPred:$src)),
4740           (LDrih_imm_abs_V4 u6ImmPred:$src)>;
4741
4742 let Predicates = [HasV4T], AddedComplexity=30 in
4743 def : Pat<(i32 (zextloadi16 u6ImmPred:$src)),
4744           (LDriuh_imm_abs_V4 u6ImmPred:$src)>;
4745
4746
4747 // Indexed store double word - global address.
4748 // memw(Rs+#u6:2)=#S8
4749 let AddedComplexity = 10 in
4750 def STriw_offset_ext_V4 : STInst<(outs),
4751             (ins IntRegs:$src1, u6_2Imm:$src2, globaladdress:$src3),
4752             "memw($src1+#$src2) = ##$src3",
4753             [(store (HexagonCONST32 tglobaladdr:$src3),
4754                     (add IntRegs:$src1, u6_2ImmPred:$src2))]>,
4755             Requires<[HasV4T]>;
4756
4757
4758 // Indexed store double word - global address.
4759 // memw(Rs+#u6:2)=#S8
4760 let AddedComplexity = 10 in
4761 def STrih_offset_ext_V4 : STInst<(outs),
4762             (ins IntRegs:$src1, u6_1Imm:$src2, globaladdress:$src3),
4763             "memh($src1+#$src2) = ##$src3",
4764             [(truncstorei16 (HexagonCONST32 tglobaladdr:$src3),
4765                     (add IntRegs:$src1, u6_1ImmPred:$src2))]>,
4766             Requires<[HasV4T]>;