lib/Target/Hexagon/HexagonInstrInfoV4.td

   1 //=- HexagonInstrInfoV4.td - Target Desc. for Hexagon Target -*- tablegen -*-=//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file describes the Hexagon V4 instructions in TableGen format.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 let neverHasSideEffects = 1 in
  15 def IMMEXT : Immext<(outs), (ins),
  16                     "/* immext #... */",
  17                     []>,
  18              Requires<[HasV4T]>;
  19
  20 // Hexagon V4 Architecture spec defines 8 instruction classes:
  21 // LD ST ALU32 XTYPE J JR MEMOP NV CR SYSTEM(system is not implemented in the
  22 // compiler)
  23
  24 // LD Instructions:
  25 // ========================================
  26 // Loads (8/16/32/64 bit)
  27 // Deallocframe
  28
  29 // ST Instructions:
  30 // ========================================
  31 // Stores (8/16/32/64 bit)
  32 // Allocframe
  33
  34 // ALU32 Instructions:
  35 // ========================================
  36 // Arithmetic / Logical (32 bit)
  37 // Vector Halfword
  38
  39 // XTYPE Instructions (32/64 bit):
  40 // ========================================
  41 // Arithmetic, Logical, Bit Manipulation
  42 // Multiply (Integer, Fractional, Complex)
  43 // Permute / Vector Permute Operations
  44 // Predicate Operations
  45 // Shift / Shift with Add/Sub/Logical
  46 // Vector Byte ALU
  47 // Vector Halfword (ALU, Shift, Multiply)
  48 // Vector Word (ALU, Shift)
  49
  50 // J Instructions:
  51 // ========================================
  52 // Jump/Call PC-relative
  53
  54 // JR Instructions:
  55 // ========================================
  56 // Jump/Call Register
  57
  58 // MEMOP Instructions:
  59 // ========================================
  60 // Operation on memory (8/16/32 bit)
  61
  62 // NV Instructions:
  63 // ========================================
  64 // New-value Jumps
  65 // New-value Stores
  66
  67 // CR Instructions:
  68 // ========================================
  69 // Control-Register Transfers
  70 // Hardware Loop Setup
  71 // Predicate Logicals & Reductions
  72
  73 // SYSTEM Instructions (not implemented in the compiler):
  74 // ========================================
  75 // Prefetch
  76 // Cache Maintenance
  77 // Bus Operations
  78
  79
  80 //===----------------------------------------------------------------------===//
  81 // ALU32 +
  82 //===----------------------------------------------------------------------===//
  83
  84 // Shift halfword.
  85
  86 let isPredicated = 1 in
  87 def ASLH_cPt_V4 : ALU32_rr<(outs IntRegs:$dst),
  88             (ins PredRegs:$src1, IntRegs:$src2),
  89             "if ($src1) $dst = aslh($src2)",
  90             []>,
  91             Requires<[HasV4T]>;
  92
  93 let isPredicated = 1 in
  94 def ASLH_cNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
  95             (ins PredRegs:$src1, IntRegs:$src2),
  96             "if (!$src1) $dst = aslh($src2)",
  97             []>,
  98             Requires<[HasV4T]>;
  99
 100 let isPredicated = 1 in
 101 def ASLH_cdnPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 102             (ins PredRegs:$src1, IntRegs:$src2),
 103             "if ($src1.new) $dst = aslh($src2)",
 104             []>,
 105             Requires<[HasV4T]>;
 106
 107 let isPredicated = 1 in
 108 def ASLH_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 109             (ins PredRegs:$src1, IntRegs:$src2),
 110             "if (!$src1.new) $dst = aslh($src2)",
 111             []>,
 112             Requires<[HasV4T]>;
 113
 114 let isPredicated = 1 in
 115 def ASRH_cPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 116             (ins PredRegs:$src1, IntRegs:$src2),
 117             "if ($src1) $dst = asrh($src2)",
 118             []>,
 119             Requires<[HasV4T]>;
 120
 121 let isPredicated = 1 in
 122 def ASRH_cNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 123             (ins PredRegs:$src1, IntRegs:$src2),
 124             "if (!$src1) $dst = asrh($src2)",
 125             []>,
 126             Requires<[HasV4T]>;
 127
 128 let isPredicated = 1 in
 129 def ASRH_cdnPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 130             (ins PredRegs:$src1, IntRegs:$src2),
 131             "if ($src1.new) $dst = asrh($src2)",
 132             []>,
 133             Requires<[HasV4T]>;
 134
 135 let isPredicated = 1 in
 136 def ASRH_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 137             (ins PredRegs:$src1, IntRegs:$src2),
 138             "if (!$src1.new) $dst = asrh($src2)",
 139             []>,
 140             Requires<[HasV4T]>;
 141
 142 // Sign extend.
 143
 144 let isPredicated = 1 in
 145 def SXTB_cPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 146             (ins PredRegs:$src1, IntRegs:$src2),
 147             "if ($src1) $dst = sxtb($src2)",
 148             []>,
 149             Requires<[HasV4T]>;
 150
 151 let isPredicated = 1 in
 152 def SXTB_cNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 153             (ins PredRegs:$src1, IntRegs:$src2),
 154             "if (!$src1) $dst = sxtb($src2)",
 155             []>,
 156             Requires<[HasV4T]>;
 157
 158 let isPredicated = 1 in
 159 def SXTB_cdnPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 160             (ins PredRegs:$src1, IntRegs:$src2),
 161             "if ($src1.new) $dst = sxtb($src2)",
 162             []>,
 163             Requires<[HasV4T]>;
 164
 165 let isPredicated = 1 in
 166 def SXTB_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 167             (ins PredRegs:$src1, IntRegs:$src2),
 168             "if (!$src1.new) $dst = sxtb($src2)",
 169             []>,
 170             Requires<[HasV4T]>;
 171
 172
 173 let isPredicated = 1 in
 174 def SXTH_cPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 175             (ins PredRegs:$src1, IntRegs:$src2),
 176             "if ($src1) $dst = sxth($src2)",
 177             []>,
 178             Requires<[HasV4T]>;
 179
 180 let isPredicated = 1 in
 181 def SXTH_cNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 182             (ins PredRegs:$src1, IntRegs:$src2),
 183             "if (!$src1) $dst = sxth($src2)",
 184             []>,
 185             Requires<[HasV4T]>;
 186
 187 let isPredicated = 1 in
 188 def SXTH_cdnPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 189             (ins PredRegs:$src1, IntRegs:$src2),
 190             "if ($src1.new) $dst = sxth($src2)",
 191             []>,
 192             Requires<[HasV4T]>;
 193
 194 let isPredicated = 1 in
 195 def SXTH_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 196             (ins PredRegs:$src1, IntRegs:$src2),
 197             "if (!$src1.new) $dst = sxth($src2)",
 198             []>,
 199             Requires<[HasV4T]>;
 200
 201 // Zero exten.
 202
 203 let neverHasSideEffects = 1, isPredicated = 1 in
 204 def ZXTB_cPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 205             (ins PredRegs:$src1, IntRegs:$src2),
 206             "if ($src1) $dst = zxtb($src2)",
 207             []>,
 208             Requires<[HasV4T]>;
 209
 210 let neverHasSideEffects = 1, isPredicated = 1 in
 211 def ZXTB_cNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 212             (ins PredRegs:$src1, IntRegs:$src2),
 213             "if (!$src1) $dst = zxtb($src2)",
 214             []>,
 215             Requires<[HasV4T]>;
 216
 217 let neverHasSideEffects = 1, isPredicated = 1 in
 218 def ZXTB_cdnPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 219             (ins PredRegs:$src1, IntRegs:$src2),
 220             "if ($src1.new) $dst = zxtb($src2)",
 221             []>,
 222             Requires<[HasV4T]>;
 223
 224 let neverHasSideEffects = 1, isPredicated = 1 in
 225 def ZXTB_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 226             (ins PredRegs:$src1, IntRegs:$src2),
 227             "if (!$src1.new) $dst = zxtb($src2)",
 228             []>,
 229             Requires<[HasV4T]>;
 230
 231 let neverHasSideEffects = 1, isPredicated = 1 in
 232 def ZXTH_cPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 233             (ins PredRegs:$src1, IntRegs:$src2),
 234             "if ($src1) $dst = zxth($src2)",
 235             []>,
 236             Requires<[HasV4T]>;
 237
 238 let neverHasSideEffects = 1, isPredicated = 1 in
 239 def ZXTH_cNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 240             (ins PredRegs:$src1, IntRegs:$src2),
 241             "if (!$src1) $dst = zxth($src2)",
 242             []>,
 243             Requires<[HasV4T]>;
 244
 245 let neverHasSideEffects = 1, isPredicated = 1 in
 246 def ZXTH_cdnPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 247             (ins PredRegs:$src1, IntRegs:$src2),
 248             "if ($src1.new) $dst = zxth($src2)",
 249             []>,
 250             Requires<[HasV4T]>;
 251
 252 let neverHasSideEffects = 1, isPredicated = 1 in
 253 def ZXTH_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 254             (ins PredRegs:$src1, IntRegs:$src2),
 255             "if (!$src1.new) $dst = zxth($src2)",
 256             []>,
 257             Requires<[HasV4T]>;
 258
 259 // Generate frame index addresses.
 260 let neverHasSideEffects = 1, isReMaterializable = 1 in
 261 def TFR_FI_immext_V4 : ALU32_ri<(outs IntRegs:$dst),
 262             (ins IntRegs:$src1, s32Imm:$offset),
 263             "$dst = add($src1, ##$offset)",
 264             []>,
 265             Requires<[HasV4T]>;
 266
 267
 268 //===----------------------------------------------------------------------===//
 269 // ALU32 -
 270 //===----------------------------------------------------------------------===//
 271
 272
 273 //===----------------------------------------------------------------------===//
 274 // ALU32/PERM +
 275 //===----------------------------------------------------------------------===//
 276
 277 // Combine
 278 // Rdd=combine(Rs, #s8)
 279 let neverHasSideEffects = 1 in
 280 def COMBINE_ri_V4 : ALU32_ri<(outs DoubleRegs:$dst),
 281             (ins IntRegs:$src1, s8Imm:$src2),
 282             "$dst = combine($src1, #$src2)",
 283             []>,
 284             Requires<[HasV4T]>;
 285 // Rdd=combine(#s8, Rs)
 286 let neverHasSideEffects = 1 in
 287 def COMBINE_ir_V4 : ALU32_ir<(outs DoubleRegs:$dst),
 288             (ins s8Imm:$src1, IntRegs:$src2),
 289             "$dst = combine(#$src1, $src2)",
 290             []>,
 291             Requires<[HasV4T]>;
 292 //===----------------------------------------------------------------------===//
 293 // ALU32/PERM +
 294 //===----------------------------------------------------------------------===//
 295
 296 //===----------------------------------------------------------------------===//
 297 // LD +
 298 //===----------------------------------------------------------------------===//
 299 //
 300 // These absolute set addressing mode instructions accept immediate as
 301 // an operand. We have duplicated these patterns to take global address.
 302
 303 let neverHasSideEffects = 1 in
 304 def LDrid_abs_setimm_V4 : LDInst2<(outs DoubleRegs:$dst1, IntRegs:$dst2),
 305             (ins u6Imm:$addr),
 306             "$dst1 = memd($dst2=#$addr)",
 307             []>,
 308             Requires<[HasV4T]>;
 309
 310 // Rd=memb(Re=#U6)
 311 let neverHasSideEffects = 1 in
 312 def LDrib_abs_setimm_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
 313             (ins u6Imm:$addr),
 314             "$dst1 = memb($dst2=#$addr)",
 315             []>,
 316             Requires<[HasV4T]>;
 317
 318 // Rd=memh(Re=#U6)
 319 let neverHasSideEffects = 1 in
 320 def LDrih_abs_setimm_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
 321             (ins u6Imm:$addr),
 322             "$dst1 = memh($dst2=#$addr)",
 323             []>,
 324             Requires<[HasV4T]>;
 325
 326 // Rd=memub(Re=#U6)
 327 let neverHasSideEffects = 1 in
 328 def LDriub_abs_setimm_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
 329             (ins u6Imm:$addr),
 330             "$dst1 = memub($dst2=#$addr)",
 331             []>,
 332             Requires<[HasV4T]>;
 333
 334 // Rd=memuh(Re=#U6)
 335 let neverHasSideEffects = 1 in
 336 def LDriuh_abs_setimm_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
 337             (ins u6Imm:$addr),
 338             "$dst1 = memuh($dst2=#$addr)",
 339             []>,
 340             Requires<[HasV4T]>;
 341
 342 // Rd=memw(Re=#U6)
 343 let neverHasSideEffects = 1 in
 344 def LDriw_abs_setimm_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
 345             (ins u6Imm:$addr),
 346             "$dst1 = memw($dst2=#$addr)",
 347             []>,
 348             Requires<[HasV4T]>;
 349
 350 // Following patterns are defined for absolute set addressing mode
 351 // instruction which take global address as operand.
 352 let neverHasSideEffects = 1 in
 353 def LDrid_abs_set_V4 : LDInst2<(outs DoubleRegs:$dst1, IntRegs:$dst2),
 354             (ins globaladdress:$addr),
 355             "$dst1 = memd($dst2=##$addr)",
 356             []>,
 357             Requires<[HasV4T]>;
 358
 359 // Rd=memb(Re=#U6)
 360 let neverHasSideEffects = 1 in
 361 def LDrib_abs_set_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
 362             (ins globaladdress:$addr),
 363             "$dst1 = memb($dst2=##$addr)",
 364             []>,
 365             Requires<[HasV4T]>;
 366
 367 // Rd=memh(Re=#U6)
 368 let neverHasSideEffects = 1 in
 369 def LDrih_abs_set_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
 370             (ins globaladdress:$addr),
 371             "$dst1 = memh($dst2=##$addr)",
 372             []>,
 373             Requires<[HasV4T]>;
 374
 375 // Rd=memub(Re=#U6)
 376 let neverHasSideEffects = 1 in
 377 def LDriub_abs_set_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
 378             (ins globaladdress:$addr),
 379             "$dst1 = memub($dst2=##$addr)",
 380             []>,
 381             Requires<[HasV4T]>;
 382
 383 // Rd=memuh(Re=#U6)
 384 let neverHasSideEffects = 1 in
 385 def LDriuh_abs_set_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
 386             (ins globaladdress:$addr),
 387             "$dst1 = memuh($dst2=##$addr)",
 388             []>,
 389             Requires<[HasV4T]>;
 390
 391 // Rd=memw(Re=#U6)
 392 let neverHasSideEffects = 1 in
 393 def LDriw_abs_set_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
 394             (ins globaladdress:$addr),
 395             "$dst1 = memw($dst2=##$addr)",
 396             []>,
 397             Requires<[HasV4T]>;
 398
 399 // Load doubleword.
 400 //
 401 // Make sure that in post increment load, the first operand is always the post
 402 // increment operand.
 403 //
 404 // Rdd=memd(Rs+Rt<<#u2)
 405 // Special case pattern for indexed load without offset which is easier to
 406 // match. AddedComplexity of this pattern should be lower than base+offset load
 407 // and lower yet than the more generic version with offset/shift below
 408 // Similar approach is taken for all other base+index loads.
 409 let AddedComplexity = 10, isPredicable = 1 in
 410 def LDrid_indexed_V4 : LDInst<(outs DoubleRegs:$dst),
 411                     (ins IntRegs:$src1, IntRegs:$src2),
 412                     "$dst=memd($src1+$src2<<#0)",
 413                     [(set (i64 DoubleRegs:$dst),
 414                           (i64 (load (add (i32 IntRegs:$src1),
 415                                           (i32 IntRegs:$src2)))))]>,
 416                     Requires<[HasV4T]>;
 417
 418 let AddedComplexity = 40, isPredicable = 1 in
 419 def LDrid_indexed_shl_V4 : LDInst<(outs DoubleRegs:$dst),
 420                     (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$offset),
 421                     "$dst=memd($src1+$src2<<#$offset)",
 422                     [(set (i64 DoubleRegs:$dst),
 423                           (i64 (load (add (i32 IntRegs:$src1),
 424                                           (shl (i32 IntRegs:$src2),
 425                                                u2ImmPred:$offset)))))]>,
 426                     Requires<[HasV4T]>;
 427
 428 //// Load doubleword conditionally.
 429 // if ([!]Pv[.new]) Rd=memd(Rs+Rt<<#u2)
 430 // if (Pv) Rd=memd(Rs+Rt<<#u2)
 431 let AddedComplexity = 15, isPredicated = 1 in
 432 def LDrid_indexed_cPt_V4 : LDInst2<(outs DoubleRegs:$dst),
 433                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 434                     "if ($src1) $dst=memd($src2+$src3<<#0)",
 435                     []>,
 436                     Requires<[HasV4T]>;
 437
 438 // if (Pv.new) Rd=memd(Rs+Rt<<#u2)
 439 let AddedComplexity = 15, isPredicated = 1 in
 440 def LDrid_indexed_cdnPt_V4 : LDInst2<(outs DoubleRegs:$dst),
 441                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 442                     "if ($src1.new) $dst=memd($src2+$src3<<#0)",
 443                     []>,
 444                     Requires<[HasV4T]>;
 445
 446 // if (!Pv) Rd=memd(Rs+Rt<<#u2)
 447 let AddedComplexity = 15, isPredicated = 1 in
 448 def LDrid_indexed_cNotPt_V4 : LDInst2<(outs DoubleRegs:$dst),
 449                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 450                     "if (!$src1) $dst=memd($src2+$src3<<#0)",
 451                     []>,
 452                     Requires<[HasV4T]>;
 453
 454 // if (!Pv.new) Rd=memd(Rs+Rt<<#u2)
 455 let AddedComplexity = 15, isPredicated = 1 in
 456 def LDrid_indexed_cdnNotPt_V4 : LDInst2<(outs DoubleRegs:$dst),
 457                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 458                     "if (!$src1.new) $dst=memd($src2+$src3<<#0)",
 459                     []>,
 460                     Requires<[HasV4T]>;
 461
 462 // if (Pv) Rd=memd(Rs+Rt<<#u2)
 463 let AddedComplexity = 45, isPredicated = 1 in
 464 def LDrid_indexed_shl_cPt_V4 : LDInst2<(outs DoubleRegs:$dst),
 465                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
 466                          u2Imm:$offset),
 467                     "if ($src1) $dst=memd($src2+$src3<<#$offset)",
 468                     []>,
 469                     Requires<[HasV4T]>;
 470
 471 // if (Pv.new) Rd=memd(Rs+Rt<<#u2)
 472 let AddedComplexity = 45, isPredicated = 1 in
 473 def LDrid_indexed_shl_cdnPt_V4 : LDInst2<(outs DoubleRegs:$dst),
 474                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
 475                          u2Imm:$offset),
 476                     "if ($src1.new) $dst=memd($src2+$src3<<#$offset)",
 477                     []>,
 478                     Requires<[HasV4T]>;
 479
 480 // if (!Pv) Rd=memd(Rs+Rt<<#u2)
 481 let AddedComplexity = 45, isPredicated = 1 in
 482 def LDrid_indexed_shl_cNotPt_V4 : LDInst2<(outs DoubleRegs:$dst),
 483                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
 484                          u2Imm:$offset),
 485                     "if (!$src1) $dst=memd($src2+$src3<<#$offset)",
 486                     []>,
 487                     Requires<[HasV4T]>;
 488
 489 // if (!Pv.new) Rd=memd(Rs+Rt<<#u2)
 490 let AddedComplexity = 45, isPredicated = 1 in
 491 def LDrid_indexed_shl_cdnNotPt_V4 : LDInst2<(outs DoubleRegs:$dst),
 492                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
 493                          u2Imm:$offset),
 494                     "if (!$src1.new) $dst=memd($src2+$src3<<#$offset)",
 495                     []>,
 496                     Requires<[HasV4T]>;
 497
 498 // Rdd=memd(Rt<<#u2+#U6)
 499
 500 //// Load byte.
 501 // Rd=memb(Rs+Rt<<#u2)
 502 let AddedComplexity = 10, isPredicable = 1 in
 503 def LDrib_indexed_V4 : LDInst<(outs IntRegs:$dst),
 504                     (ins IntRegs:$src1, IntRegs:$src2),
 505                     "$dst=memb($src1+$src2<<#0)",
 506                     [(set (i32 IntRegs:$dst),
 507                           (i32 (sextloadi8 (add (i32 IntRegs:$src1),
 508                                                 (i32 IntRegs:$src2)))))]>,
 509                     Requires<[HasV4T]>;
 510
 511 let AddedComplexity = 10, isPredicable = 1 in
 512 def LDriub_indexed_V4 : LDInst<(outs IntRegs:$dst),
 513                     (ins IntRegs:$src1, IntRegs:$src2),
 514                     "$dst=memub($src1+$src2<<#0)",
 515                     [(set (i32 IntRegs:$dst),
 516                           (i32 (zextloadi8 (add (i32 IntRegs:$src1),
 517                                                 (i32 IntRegs:$src2)))))]>,
 518                     Requires<[HasV4T]>;
 519
 520 let AddedComplexity = 10, isPredicable = 1 in
 521 def LDriub_ae_indexed_V4 : LDInst<(outs IntRegs:$dst),
 522                     (ins IntRegs:$src1, IntRegs:$src2),
 523                     "$dst=memub($src1+$src2<<#0)",
 524                     [(set (i32 IntRegs:$dst),
 525                           (i32 (extloadi8 (add (i32 IntRegs:$src1),
 526                                                (i32 IntRegs:$src2)))))]>,
 527                     Requires<[HasV4T]>;
 528
 529 let AddedComplexity = 40, isPredicable = 1 in
 530 def LDrib_indexed_shl_V4 : LDInst<(outs IntRegs:$dst),
 531                     (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$offset),
 532                     "$dst=memb($src1+$src2<<#$offset)",
 533                     [(set (i32 IntRegs:$dst),
 534                           (i32 (sextloadi8 (add (i32 IntRegs:$src1),
 535                                                 (shl (i32 IntRegs:$src2),
 536                                                      u2ImmPred:$offset)))))]>,
 537                     Requires<[HasV4T]>;
 538
 539 let AddedComplexity = 40, isPredicable = 1 in
 540 def LDriub_indexed_shl_V4 : LDInst<(outs IntRegs:$dst),
 541                     (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$offset),
 542                     "$dst=memub($src1+$src2<<#$offset)",
 543                     [(set (i32 IntRegs:$dst),
 544                           (i32 (zextloadi8 (add (i32 IntRegs:$src1),
 545                                                 (shl (i32 IntRegs:$src2),
 546                                                      u2ImmPred:$offset)))))]>,
 547                     Requires<[HasV4T]>;
 548
 549 let AddedComplexity = 40, isPredicable = 1 in
 550 def LDriub_ae_indexed_shl_V4 : LDInst<(outs IntRegs:$dst),
 551                     (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$offset),
 552                     "$dst=memub($src1+$src2<<#$offset)",
 553                     [(set (i32 IntRegs:$dst),
 554                           (i32 (extloadi8 (add (i32 IntRegs:$src1),
 555                                                (shl (i32 IntRegs:$src2),
 556                                                     u2ImmPred:$offset)))))]>,
 557                     Requires<[HasV4T]>;
 558
 559 //// Load byte conditionally.
 560 // if ([!]Pv[.new]) Rd=memb(Rs+Rt<<#u2)
 561 // if (Pv) Rd=memb(Rs+Rt<<#u2)
 562 let AddedComplexity = 15, isPredicated = 1 in
 563 def LDrib_indexed_cPt_V4 : LDInst2<(outs IntRegs:$dst),
 564                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 565                     "if ($src1) $dst=memb($src2+$src3<<#0)",
 566                     []>,
 567                     Requires<[HasV4T]>;
 568
 569 // if (Pv.new) Rd=memb(Rs+Rt<<#u2)
 570 let AddedComplexity = 15, isPredicated = 1 in
 571 def LDrib_indexed_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
 572                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 573                     "if ($src1.new) $dst=memb($src2+$src3<<#0)",
 574                     []>,
 575                     Requires<[HasV4T]>;
 576
 577 // if (!Pv) Rd=memb(Rs+Rt<<#u2)
 578 let AddedComplexity = 15, isPredicated = 1 in
 579 def LDrib_indexed_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 580                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 581                     "if (!$src1) $dst=memb($src2+$src3<<#0)",
 582                     []>,
 583                     Requires<[HasV4T]>;
 584
 585 // if (!Pv.new) Rd=memb(Rs+Rt<<#u2)
 586 let AddedComplexity = 15, isPredicated = 1 in
 587 def LDrib_indexed_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 588                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 589                     "if (!$src1.new) $dst=memb($src2+$src3<<#0)",
 590                     []>,
 591                     Requires<[HasV4T]>;
 592
 593 // if (Pv) Rd=memb(Rs+Rt<<#u2)
 594 let AddedComplexity = 45, isPredicated = 1 in
 595 def LDrib_indexed_shl_cPt_V4 : LDInst2<(outs IntRegs:$dst),
 596                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
 597                          u2Imm:$offset),
 598                     "if ($src1) $dst=memb($src2+$src3<<#$offset)",
 599                     []>,
 600                     Requires<[HasV4T]>;
 601
 602 // if (Pv.new) Rd=memb(Rs+Rt<<#u2)
 603 let AddedComplexity = 45, isPredicated = 1 in
 604 def LDrib_indexed_shl_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
 605                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
 606                          u2Imm:$offset),
 607                     "if ($src1.new) $dst=memb($src2+$src3<<#$offset)",
 608                     []>,
 609                     Requires<[HasV4T]>;
 610
 611 // if (!Pv) Rd=memb(Rs+Rt<<#u2)
 612 let AddedComplexity = 45, isPredicated = 1 in
 613 def LDrib_indexed_shl_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 614                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
 615                          u2Imm:$offset),
 616                     "if (!$src1) $dst=memb($src2+$src3<<#$offset)",
 617                     []>,
 618                     Requires<[HasV4T]>;
 619
 620 // if (!Pv.new) Rd=memb(Rs+Rt<<#u2)
 621 let AddedComplexity = 45, isPredicated = 1 in
 622 def LDrib_indexed_shl_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 623                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
 624                          u2Imm:$offset),
 625                     "if (!$src1.new) $dst=memb($src2+$src3<<#$offset)",
 626                     []>,
 627                     Requires<[HasV4T]>;
 628
 629 //// Load unsigned byte conditionally.
 630 // if ([!]Pv[.new]) Rd=memub(Rs+Rt<<#u2)
 631 // if (Pv) Rd=memub(Rs+Rt<<#u2)
 632 let AddedComplexity = 15, isPredicated = 1 in
 633 def LDriub_indexed_cPt_V4 : LDInst2<(outs IntRegs:$dst),
 634                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 635                     "if ($src1) $dst=memub($src2+$src3<<#0)",
 636                     []>,
 637                     Requires<[HasV4T]>;
 638
 639 // if (Pv.new) Rd=memub(Rs+Rt<<#u2)
 640 let AddedComplexity = 15, isPredicated = 1 in
 641 def LDriub_indexed_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
 642                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 643                     "if ($src1.new) $dst=memub($src2+$src3<<#0)",
 644                     []>,
 645                     Requires<[HasV4T]>;
 646
 647 // if (!Pv) Rd=memub(Rs+Rt<<#u2)
 648 let AddedComplexity = 15, isPredicated = 1 in
 649 def LDriub_indexed_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 650                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 651                     "if (!$src1) $dst=memub($src2+$src3<<#0)",
 652                     []>,
 653                     Requires<[HasV4T]>;
 654
 655 // if (!Pv.new) Rd=memub(Rs+Rt<<#u2)
 656 let AddedComplexity = 15, isPredicated = 1 in
 657 def LDriub_indexed_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 658                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 659                     "if (!$src1.new) $dst=memub($src2+$src3<<#0)",
 660                     []>,
 661                     Requires<[HasV4T]>;
 662
 663 // if (Pv) Rd=memub(Rs+Rt<<#u2)
 664 let AddedComplexity = 45, isPredicated = 1 in
 665 def LDriub_indexed_shl_cPt_V4 : LDInst2<(outs IntRegs:$dst),
 666                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
 667                          u2Imm:$offset),
 668                     "if ($src1) $dst=memub($src2+$src3<<#$offset)",
 669                     []>,
 670                     Requires<[HasV4T]>;
 671
 672 // if (Pv.new) Rd=memub(Rs+Rt<<#u2)
 673 let AddedComplexity = 45, isPredicated = 1 in
 674 def LDriub_indexed_shl_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
 675                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
 676                          u2Imm:$offset),
 677                     "if ($src1.new) $dst=memub($src2+$src3<<#$offset)",
 678                     []>,
 679                     Requires<[HasV4T]>;
 680
 681 // if (!Pv) Rd=memub(Rs+Rt<<#u2)
 682 let AddedComplexity = 45, isPredicated = 1 in
 683 def LDriub_indexed_shl_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 684                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
 685                          u2Imm:$offset),
 686                     "if (!$src1) $dst=memub($src2+$src3<<#$offset)",
 687                     []>,
 688                     Requires<[HasV4T]>;
 689
 690 // if (!Pv.new) Rd=memub(Rs+Rt<<#u2)
 691 let AddedComplexity = 45, isPredicated = 1 in
 692 def LDriub_indexed_shl_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 693                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
 694                          u2Imm:$offset),
 695                     "if (!$src1.new) $dst=memub($src2+$src3<<#$offset)",
 696                     []>,
 697                     Requires<[HasV4T]>;
 698
 699 // Rd=memb(Rt<<#u2+#U6)
 700
 701 //// Load halfword
 702 // Rd=memh(Rs+Rt<<#u2)
 703 let AddedComplexity = 10, isPredicable = 1 in
 704 def LDrih_indexed_V4 : LDInst<(outs IntRegs:$dst),
 705                     (ins IntRegs:$src1, IntRegs:$src2),
 706                     "$dst=memh($src1+$src2<<#0)",
 707                     [(set (i32 IntRegs:$dst),
 708                           (i32 (sextloadi16 (add (i32 IntRegs:$src1),
 709                                                  (i32 IntRegs:$src2)))))]>,
 710                     Requires<[HasV4T]>;
 711
 712 let AddedComplexity = 10, isPredicable = 1 in
 713 def LDriuh_indexed_V4 : LDInst<(outs IntRegs:$dst),
 714                     (ins IntRegs:$src1, IntRegs:$src2),
 715                     "$dst=memuh($src1+$src2<<#0)",
 716                     [(set (i32 IntRegs:$dst),
 717                           (i32 (zextloadi16 (add (i32 IntRegs:$src1),
 718                                                  (i32 IntRegs:$src2)))))]>,
 719                     Requires<[HasV4T]>;
 720
 721 let AddedComplexity = 10, isPredicable = 1 in
 722 def LDriuh_ae_indexed_V4 : LDInst<(outs IntRegs:$dst),
 723                     (ins IntRegs:$src1, IntRegs:$src2),
 724                     "$dst=memuh($src1+$src2<<#0)",
 725                     [(set (i32 IntRegs:$dst),
 726                           (i32 (extloadi16 (add (i32 IntRegs:$src1),
 727                                                 (i32 IntRegs:$src2)))))]>,
 728                     Requires<[HasV4T]>;
 729
 730 // Rd=memh(Rs+Rt<<#u2)
 731 let AddedComplexity = 40, isPredicable = 1 in
 732 def LDrih_indexed_shl_V4 : LDInst<(outs IntRegs:$dst),
 733                     (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$offset),
 734                     "$dst=memh($src1+$src2<<#$offset)",
 735                     [(set (i32 IntRegs:$dst),
 736                           (i32 (sextloadi16 (add (i32 IntRegs:$src1),
 737                                                  (shl (i32 IntRegs:$src2),
 738                                                       u2ImmPred:$offset)))))]>,
 739                     Requires<[HasV4T]>;
 740
 741 let AddedComplexity = 40, isPredicable = 1 in
 742 def LDriuh_indexed_shl_V4 : LDInst<(outs IntRegs:$dst),
 743                     (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$offset),
 744                     "$dst=memuh($src1+$src2<<#$offset)",
 745                     [(set (i32 IntRegs:$dst),
 746                           (i32 (zextloadi16 (add (i32 IntRegs:$src1),
 747                                                  (shl (i32 IntRegs:$src2),
 748                                                       u2ImmPred:$offset)))))]>,
 749                     Requires<[HasV4T]>;
 750
 751 let AddedComplexity = 40, isPredicable = 1 in
 752 def LDriuh_ae_indexed_shl_V4 : LDInst<(outs IntRegs:$dst),
 753                     (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$offset),
 754                     "$dst=memuh($src1+$src2<<#$offset)",
 755                     [(set (i32 IntRegs:$dst),
 756                           (i32 (extloadi16 (add (i32 IntRegs:$src1),
 757                                                 (shl (i32 IntRegs:$src2),
 758                                                      u2ImmPred:$offset)))))]>,
 759                     Requires<[HasV4T]>;
 760
 761 //// Load halfword conditionally.
 762 // if ([!]Pv[.new]) Rd=memh(Rs+Rt<<#u2)
 763 // if (Pv) Rd=memh(Rs+Rt<<#u2)
 764 let AddedComplexity = 15, isPredicated = 1 in
 765 def LDrih_indexed_cPt_V4 : LDInst2<(outs IntRegs:$dst),
 766                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 767                     "if ($src1) $dst=memh($src2+$src3<<#0)",
 768                     []>,
 769                     Requires<[HasV4T]>;
 770
 771 // if (Pv.new) Rd=memh(Rs+Rt<<#u2)
 772 let AddedComplexity = 15, isPredicated = 1 in
 773 def LDrih_indexed_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
 774                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 775                     "if ($src1.new) $dst=memh($src2+$src3<<#0)",
 776                     []>,
 777                     Requires<[HasV4T]>;
 778
 779 // if (!Pv) Rd=memh(Rs+Rt<<#u2)
 780 let AddedComplexity = 15, isPredicated = 1 in
 781 def LDrih_indexed_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 782                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 783                     "if (!$src1) $dst=memh($src2+$src3<<#0)",
 784                     []>,
 785                     Requires<[HasV4T]>;
 786
 787 // if (!Pv.new) Rd=memh(Rs+Rt<<#u2)
 788 let AddedComplexity = 15, isPredicated = 1 in
 789 def LDrih_indexed_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 790                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 791                     "if (!$src1.new) $dst=memh($src2+$src3<<#0)",
 792                     []>,
 793                     Requires<[HasV4T]>;
 794
 795 // if (Pv) Rd=memh(Rs+Rt<<#u2)
 796 let AddedComplexity = 45, isPredicated = 1 in
 797 def LDrih_indexed_shl_cPt_V4 : LDInst2<(outs IntRegs:$dst),
 798                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
 799                          u2Imm:$offset),
 800                     "if ($src1) $dst=memh($src2+$src3<<#$offset)",
 801                     []>,
 802                     Requires<[HasV4T]>;
 803
 804 // if (Pv.new) Rd=memh(Rs+Rt<<#u2)
 805 let AddedComplexity = 45, isPredicated = 1 in
 806 def LDrih_indexed_shl_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
 807                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
 808                          u2Imm:$offset),
 809                     "if ($src1.new) $dst=memh($src2+$src3<<#$offset)",
 810                     []>,
 811                     Requires<[HasV4T]>;
 812
 813 // if (!Pv) Rd=memh(Rs+Rt<<#u2)
 814 let AddedComplexity = 45, isPredicated = 1 in
 815 def LDrih_indexed_shl_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 816                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
 817                          u2Imm:$offset),
 818                     "if (!$src1) $dst=memh($src2+$src3<<#$offset)",
 819                     []>,
 820                     Requires<[HasV4T]>;
 821
 822 // if (!Pv.new) Rd=memh(Rs+Rt<<#u2)
 823 let AddedComplexity = 45, isPredicated = 1 in
 824 def LDrih_indexed_shl_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 825                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
 826                          u2Imm:$offset),
 827                     "if (!$src1.new) $dst=memh($src2+$src3<<#$offset)",
 828                     []>,
 829                     Requires<[HasV4T]>;
 830
 831 //// Load unsigned halfword conditionally.
 832 // if ([!]Pv[.new]) Rd=memuh(Rs+Rt<<#u2)
 833 // if (Pv) Rd=memuh(Rs+Rt<<#u2)
 834 let AddedComplexity = 15, isPredicated = 1 in
 835 def LDriuh_indexed_cPt_V4 : LDInst2<(outs IntRegs:$dst),
 836                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 837                     "if ($src1) $dst=memuh($src2+$src3<<#0)",
 838                     []>,
 839                     Requires<[HasV4T]>;
 840
 841 // if (Pv.new) Rd=memuh(Rs+Rt<<#u2)
 842 let AddedComplexity = 15, isPredicated = 1 in
 843 def LDriuh_indexed_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
 844                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 845                     "if ($src1.new) $dst=memuh($src2+$src3<<#0)",
 846                     []>,
 847                     Requires<[HasV4T]>;
 848
 849 // if (!Pv) Rd=memuh(Rs+Rt<<#u2)
 850 let AddedComplexity = 15, isPredicated = 1 in
 851 def LDriuh_indexed_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 852                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 853                     "if (!$src1) $dst=memuh($src2+$src3<<#0)",
 854                     []>,
 855                     Requires<[HasV4T]>;
 856
 857 // if (!Pv.new) Rd=memuh(Rs+Rt<<#u2)
 858 let AddedComplexity = 15, isPredicated = 1 in
 859 def LDriuh_indexed_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 860                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 861                     "if (!$src1.new) $dst=memuh($src2+$src3<<#0)",
 862                     []>,
 863                     Requires<[HasV4T]>;
 864
 865 // if (Pv) Rd=memuh(Rs+Rt<<#u2)
 866 let AddedComplexity = 45, isPredicated = 1 in
 867 def LDriuh_indexed_shl_cPt_V4 : LDInst2<(outs IntRegs:$dst),
 868                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
 869                          u2Imm:$offset),
 870                     "if ($src1) $dst=memuh($src2+$src3<<#$offset)",
 871                     []>,
 872                     Requires<[HasV4T]>;
 873
 874 // if (Pv.new) Rd=memuh(Rs+Rt<<#u2)
 875 let AddedComplexity = 45, isPredicated = 1 in
 876 def LDriuh_indexed_shl_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
 877                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
 878                          u2Imm:$offset),
 879                     "if ($src1.new) $dst=memuh($src2+$src3<<#$offset)",
 880                     []>,
 881                     Requires<[HasV4T]>;
 882
 883 // if (!Pv) Rd=memuh(Rs+Rt<<#u2)
 884 let AddedComplexity = 45, isPredicated = 1 in
 885 def LDriuh_indexed_shl_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 886                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
 887                          u2Imm:$offset),
 888                     "if (!$src1) $dst=memuh($src2+$src3<<#$offset)",
 889                     []>,
 890                     Requires<[HasV4T]>;
 891
 892 // if (!Pv.new) Rd=memuh(Rs+Rt<<#u2)
 893 let AddedComplexity = 45, isPredicated = 1 in
 894 def LDriuh_indexed_shl_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 895                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
 896                          u2Imm:$offset),
 897                     "if (!$src1.new) $dst=memuh($src2+$src3<<#$offset)",
 898                     []>,
 899                     Requires<[HasV4T]>;
 900
 901 // Rd=memh(Rt<<#u2+#U6)
 902
 903 //// Load word.
 904 // Load predicate: Fix for bug 5279.
 905 let neverHasSideEffects = 1 in
 906 def LDriw_pred_V4 : LDInst2<(outs PredRegs:$dst),
 907             (ins MEMri:$addr),
 908             "Error; should not emit",
 909             []>,
 910             Requires<[HasV4T]>;
 911
 912 // Rd=memw(Re=#U6)
 913
 914 // Rd=memw(Rs+Rt<<#u2)
 915 let AddedComplexity = 10, isPredicable = 1 in
 916 def LDriw_indexed_V4 : LDInst<(outs IntRegs:$dst),
 917                     (ins IntRegs:$src1, IntRegs:$src2),
 918                     "$dst=memw($src1+$src2<<#0)",
 919                     [(set (i32 IntRegs:$dst),
 920                           (i32 (load (add (i32 IntRegs:$src1),
 921                                           (i32 IntRegs:$src2)))))]>,
 922                     Requires<[HasV4T]>;
 923
 924 // Rd=memw(Rs+Rt<<#u2)
 925 let AddedComplexity = 40, isPredicable = 1 in
 926 def LDriw_indexed_shl_V4 : LDInst<(outs IntRegs:$dst),
 927                     (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$offset),
 928                     "$dst=memw($src1+$src2<<#$offset)",
 929                     [(set (i32 IntRegs:$dst),
 930                           (i32 (load (add (i32 IntRegs:$src1),
 931                                           (shl (i32 IntRegs:$src2),
 932                                                u2ImmPred:$offset)))))]>,
 933                     Requires<[HasV4T]>;
 934
 935 //// Load word conditionally.
 936 // if ([!]Pv[.new]) Rd=memw(Rs+Rt<<#u2)
 937 // if (Pv) Rd=memw(Rs+Rt<<#u2)
 938 let AddedComplexity = 15, isPredicated = 1 in
 939 def LDriw_indexed_cPt_V4 : LDInst2<(outs IntRegs:$dst),
 940                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 941                     "if ($src1) $dst=memw($src2+$src3<<#0)",
 942                     []>,
 943                     Requires<[HasV4T]>;
 944
 945 // if (Pv.new) Rd=memh(Rs+Rt<<#u2)
 946 let AddedComplexity = 15, isPredicated = 1 in
 947 def LDriw_indexed_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
 948                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 949                     "if ($src1.new) $dst=memw($src2+$src3<<#0)",
 950                     []>,
 951                     Requires<[HasV4T]>;
 952
 953 // if (!Pv) Rd=memh(Rs+Rt<<#u2)
 954 let AddedComplexity = 15, isPredicated = 1 in
 955 def LDriw_indexed_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 956                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 957                     "if (!$src1) $dst=memw($src2+$src3<<#0)",
 958                     []>,
 959                     Requires<[HasV4T]>;
 960
 961 // if (!Pv.new) Rd=memh(Rs+Rt<<#u2)
 962 let AddedComplexity = 15, isPredicated = 1 in
 963 def LDriw_indexed_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 964                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 965                     "if (!$src1.new) $dst=memw($src2+$src3<<#0)",
 966                     []>,
 967                     Requires<[HasV4T]>;
 968
 969 // if (Pv) Rd=memh(Rs+Rt<<#u2)
 970 let AddedComplexity = 45, isPredicated = 1 in
 971 def LDriw_indexed_shl_cPt_V4 : LDInst2<(outs IntRegs:$dst),
 972                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
 973                          u2Imm:$offset),
 974                     "if ($src1) $dst=memw($src2+$src3<<#$offset)",
 975                     []>,
 976                     Requires<[HasV4T]>;
 977
 978 // if (Pv.new) Rd=memh(Rs+Rt<<#u2)
 979 let AddedComplexity = 45, isPredicated = 1 in
 980 def LDriw_indexed_shl_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
 981                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
 982                          u2Imm:$offset),
 983                     "if ($src1.new) $dst=memw($src2+$src3<<#$offset)",
 984                     []>,
 985                     Requires<[HasV4T]>;
 986
 987 // if (!Pv) Rd=memh(Rs+Rt<<#u2)
 988 let AddedComplexity = 45, isPredicated = 1 in
 989 def LDriw_indexed_shl_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 990                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
 991                          u2Imm:$offset),
 992                     "if (!$src1) $dst=memw($src2+$src3<<#$offset)",
 993                     []>,
 994                     Requires<[HasV4T]>;
 995
 996 // if (!Pv.new) Rd=memh(Rs+Rt<<#u2)
 997 let AddedComplexity = 45, isPredicated = 1 in
 998 def LDriw_indexed_shl_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 999                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3,
1000                          u2Imm:$offset),
1001                     "if (!$src1.new) $dst=memw($src2+$src3<<#$offset)",
1002                     []>,
1003                     Requires<[HasV4T]>;
1004
1005 /// Load from global offset
1006
1007 let isPredicable = 1, neverHasSideEffects = 1 in
1008 def LDrid_GP_V4 : LDInst2<(outs DoubleRegs:$dst),
1009             (ins globaladdress:$global, u16Imm:$offset),
1010             "$dst=memd(#$global+$offset)",
1011             []>,
1012             Requires<[HasV4T]>;
1013
1014 let neverHasSideEffects = 1, isPredicated = 1 in
1015 def LDrid_GP_cPt_V4 : LDInst2<(outs DoubleRegs:$dst),
1016             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
1017             "if ($src1) $dst=memd(##$global+$offset)",
1018             []>,
1019             Requires<[HasV4T]>;
1020
1021 let neverHasSideEffects = 1, isPredicated = 1 in
1022 def LDrid_GP_cNotPt_V4 : LDInst2<(outs DoubleRegs:$dst),
1023             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
1024             "if (!$src1) $dst=memd(##$global+$offset)",
1025             []>,
1026             Requires<[HasV4T]>;
1027
1028 let neverHasSideEffects = 1, isPredicated = 1 in
1029 def LDrid_GP_cdnPt_V4 : LDInst2<(outs DoubleRegs:$dst),
1030             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
1031             "if ($src1.new) $dst=memd(##$global+$offset)",
1032             []>,
1033             Requires<[HasV4T]>;
1034
1035 let neverHasSideEffects = 1, isPredicated = 1 in
1036 def LDrid_GP_cdnNotPt_V4 : LDInst2<(outs DoubleRegs:$dst),
1037             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
1038             "if (!$src1.new) $dst=memd(##$global+$offset)",
1039             []>,
1040             Requires<[HasV4T]>;
1041
1042 let isPredicable = 1, neverHasSideEffects = 1 in
1043 def LDrib_GP_V4 : LDInst2<(outs IntRegs:$dst),
1044             (ins globaladdress:$global, u16Imm:$offset),
1045             "$dst=memb(#$global+$offset)",
1046             []>,
1047             Requires<[HasV4T]>;
1048
1049 let neverHasSideEffects = 1, isPredicated = 1 in
1050 def LDrib_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst),
1051             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
1052             "if ($src1) $dst=memb(##$global+$offset)",
1053             []>,
1054             Requires<[HasV4T]>;
1055
1056 let neverHasSideEffects = 1, isPredicated = 1 in
1057 def LDrib_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1058             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
1059             "if (!$src1) $dst=memb(##$global+$offset)",
1060             []>,
1061             Requires<[HasV4T]>;
1062
1063 let neverHasSideEffects = 1, isPredicated = 1 in
1064 def LDrib_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
1065             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
1066             "if ($src1.new) $dst=memb(##$global+$offset)",
1067             []>,
1068             Requires<[HasV4T]>;
1069
1070 let neverHasSideEffects = 1, isPredicated = 1 in
1071 def LDrib_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1072             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
1073             "if (!$src1.new) $dst=memb(##$global+$offset)",
1074             []>,
1075             Requires<[HasV4T]>;
1076
1077
1078 let isPredicable = 1, neverHasSideEffects = 1 in
1079 def LDriub_GP_V4 : LDInst2<(outs IntRegs:$dst),
1080             (ins globaladdress:$global, u16Imm:$offset),
1081             "$dst=memub(#$global+$offset)",
1082             []>,
1083             Requires<[HasV4T]>;
1084
1085
1086 let neverHasSideEffects = 1, isPredicated = 1 in
1087 def LDriub_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst),
1088             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
1089             "if ($src1) $dst=memub(##$global+$offset)",
1090             []>,
1091             Requires<[HasV4T]>;
1092
1093 let neverHasSideEffects = 1, isPredicated = 1 in
1094 def LDriub_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1095             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
1096             "if (!$src1) $dst=memub(##$global+$offset)",
1097             []>,
1098             Requires<[HasV4T]>;
1099
1100 let neverHasSideEffects = 1, isPredicated = 1 in
1101 def LDriub_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
1102             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
1103             "if ($src1.new) $dst=memub(##$global+$offset)",
1104             []>,
1105             Requires<[HasV4T]>;
1106
1107 let neverHasSideEffects = 1, isPredicated = 1 in
1108 def LDriub_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1109             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
1110             "if (!$src1.new) $dst=memub(##$global+$offset)",
1111             []>,
1112             Requires<[HasV4T]>;
1113
1114
1115 let isPredicable = 1, neverHasSideEffects = 1 in
1116 def LDrih_GP_V4 : LDInst2<(outs IntRegs:$dst),
1117             (ins globaladdress:$global, u16Imm:$offset),
1118             "$dst=memh(#$global+$offset)",
1119             []>,
1120             Requires<[HasV4T]>;
1121
1122
1123 let neverHasSideEffects = 1, isPredicated = 1 in
1124 def LDrih_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst),
1125             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
1126             "if ($src1) $dst=memh(##$global+$offset)",
1127             []>,
1128             Requires<[HasV4T]>;
1129
1130 let neverHasSideEffects = 1, isPredicated = 1 in
1131 def LDrih_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1132             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
1133             "if (!$src1) $dst=memh(##$global+$offset)",
1134             []>,
1135             Requires<[HasV4T]>;
1136
1137 let neverHasSideEffects = 1, isPredicated = 1 in
1138 def LDrih_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
1139             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
1140             "if ($src1.new) $dst=memh(##$global+$offset)",
1141             []>,
1142             Requires<[HasV4T]>;
1143
1144 let neverHasSideEffects = 1, isPredicated = 1 in
1145 def LDrih_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1146             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
1147             "if (!$src1.new) $dst=memh(##$global+$offset)",
1148             []>,
1149             Requires<[HasV4T]>;
1150
1151
1152 let isPredicable = 1, neverHasSideEffects = 1 in
1153 def LDriuh_GP_V4 : LDInst2<(outs IntRegs:$dst),
1154             (ins globaladdress:$global, u16Imm:$offset),
1155             "$dst=memuh(#$global+$offset)",
1156             []>,
1157             Requires<[HasV4T]>;
1158
1159 let neverHasSideEffects = 1, isPredicated = 1 in
1160 def LDriuh_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst),
1161             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
1162             "if ($src1) $dst=memuh(##$global+$offset)",
1163             []>,
1164             Requires<[HasV4T]>;
1165
1166 let neverHasSideEffects = 1, isPredicated = 1 in
1167 def LDriuh_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1168             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
1169             "if (!$src1) $dst=memuh(##$global+$offset)",
1170             []>,
1171             Requires<[HasV4T]>;
1172
1173 let neverHasSideEffects = 1, isPredicated = 1 in
1174 def LDriuh_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
1175             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
1176             "if ($src1.new) $dst=memuh(##$global+$offset)",
1177             []>,
1178             Requires<[HasV4T]>;
1179
1180 let neverHasSideEffects = 1, isPredicated = 1 in
1181 def LDriuh_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1182             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
1183             "if (!$src1.new) $dst=memuh(##$global+$offset)",
1184             []>,
1185             Requires<[HasV4T]>;
1186
1187 let isPredicable = 1, neverHasSideEffects = 1 in
1188 def LDriw_GP_V4 : LDInst2<(outs IntRegs:$dst),
1189             (ins globaladdress:$global, u16Imm:$offset),
1190             "$dst=memw(#$global+$offset)",
1191             []>,
1192             Requires<[HasV4T]>;
1193
1194
1195 let neverHasSideEffects = 1, isPredicated = 1 in
1196 def LDriw_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst),
1197             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
1198             "if ($src1) $dst=memw(##$global+$offset)",
1199             []>,
1200             Requires<[HasV4T]>;
1201
1202 let neverHasSideEffects = 1, isPredicated = 1 in
1203 def LDriw_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1204             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
1205             "if (!$src1) $dst=memw(##$global+$offset)",
1206             []>,
1207             Requires<[HasV4T]>;
1208
1209
1210 let neverHasSideEffects = 1, isPredicated = 1 in
1211 def LDriw_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
1212             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
1213             "if ($src1.new) $dst=memw(##$global+$offset)",
1214             []>,
1215             Requires<[HasV4T]>;
1216
1217 let neverHasSideEffects = 1, isPredicated = 1 in
1218 def LDriw_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1219             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
1220             "if (!$src1.new) $dst=memw(##$global+$offset)",
1221             []>,
1222             Requires<[HasV4T]>;
1223
1224
1225 let isPredicable = 1, neverHasSideEffects = 1 in
1226 def LDd_GP_V4 : LDInst2<(outs DoubleRegs:$dst),
1227             (ins globaladdress:$global),
1228             "$dst=memd(#$global)",
1229             []>,
1230             Requires<[HasV4T]>;
1231
1232 // if (Pv) Rtt=memd(##global)
1233 let neverHasSideEffects = 1, isPredicated = 1 in
1234 def LDd_GP_cPt_V4 : LDInst2<(outs DoubleRegs:$dst),
1235             (ins PredRegs:$src1, globaladdress:$global),
1236             "if ($src1) $dst=memd(##$global)",
1237             []>,
1238             Requires<[HasV4T]>;
1239
1240
1241 // if (!Pv) Rtt=memd(##global)
1242 let neverHasSideEffects = 1, isPredicated = 1 in
1243 def LDd_GP_cNotPt_V4 : LDInst2<(outs DoubleRegs:$dst),
1244             (ins PredRegs:$src1, globaladdress:$global),
1245             "if (!$src1) $dst=memd(##$global)",
1246             []>,
1247             Requires<[HasV4T]>;
1248
1249 // if (Pv) Rtt=memd(##global)
1250 let neverHasSideEffects = 1, isPredicated = 1 in
1251 def LDd_GP_cdnPt_V4 : LDInst2<(outs DoubleRegs:$dst),
1252             (ins PredRegs:$src1, globaladdress:$global),
1253             "if ($src1.new) $dst=memd(##$global)",
1254             []>,
1255             Requires<[HasV4T]>;
1256
1257
1258 // if (!Pv) Rtt=memd(##global)
1259 let neverHasSideEffects = 1, isPredicated = 1 in
1260 def LDd_GP_cdnNotPt_V4 : LDInst2<(outs DoubleRegs:$dst),
1261             (ins PredRegs:$src1, globaladdress:$global),
1262             "if (!$src1.new) $dst=memd(##$global)",
1263             []>,
1264             Requires<[HasV4T]>;
1265
1266 let isPredicable = 1, neverHasSideEffects = 1 in
1267 def LDb_GP_V4 : LDInst2<(outs IntRegs:$dst),
1268             (ins globaladdress:$global),
1269             "$dst=memb(#$global)",
1270             []>,
1271             Requires<[HasV4T]>;
1272
1273 // if (Pv) Rt=memb(##global)
1274 let neverHasSideEffects = 1, isPredicated = 1 in
1275 def LDb_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst),
1276             (ins PredRegs:$src1, globaladdress:$global),
1277             "if ($src1) $dst=memb(##$global)",
1278             []>,
1279             Requires<[HasV4T]>;
1280
1281 // if (!Pv) Rt=memb(##global)
1282 let neverHasSideEffects = 1, isPredicated = 1 in
1283 def LDb_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1284             (ins PredRegs:$src1, globaladdress:$global),
1285             "if (!$src1) $dst=memb(##$global)",
1286             []>,
1287             Requires<[HasV4T]>;
1288
1289 // if (Pv) Rt=memb(##global)
1290 let neverHasSideEffects = 1, isPredicated = 1 in
1291 def LDb_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
1292             (ins PredRegs:$src1, globaladdress:$global),
1293             "if ($src1.new) $dst=memb(##$global)",
1294             []>,
1295             Requires<[HasV4T]>;
1296
1297 // if (!Pv) Rt=memb(##global)
1298 let neverHasSideEffects = 1, isPredicated = 1 in
1299 def LDb_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1300             (ins PredRegs:$src1, globaladdress:$global),
1301             "if (!$src1.new) $dst=memb(##$global)",
1302             []>,
1303             Requires<[HasV4T]>;
1304
1305 let isPredicable = 1, neverHasSideEffects = 1 in
1306 def LDub_GP_V4 : LDInst2<(outs IntRegs:$dst),
1307             (ins globaladdress:$global),
1308             "$dst=memub(#$global)",
1309             []>,
1310             Requires<[HasV4T]>;
1311
1312 // if (Pv) Rt=memub(##global)
1313 let neverHasSideEffects = 1, isPredicated = 1 in
1314 def LDub_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst),
1315             (ins PredRegs:$src1, globaladdress:$global),
1316             "if ($src1) $dst=memub(##$global)",
1317             []>,
1318             Requires<[HasV4T]>;
1319
1320
1321 // if (!Pv) Rt=memub(##global)
1322 let neverHasSideEffects = 1, isPredicated = 1 in
1323 def LDub_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1324             (ins PredRegs:$src1, globaladdress:$global),
1325             "if (!$src1) $dst=memub(##$global)",
1326             []>,
1327             Requires<[HasV4T]>;
1328
1329 // if (Pv) Rt=memub(##global)
1330 let neverHasSideEffects = 1, isPredicated = 1 in
1331 def LDub_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
1332             (ins PredRegs:$src1, globaladdress:$global),
1333             "if ($src1.new) $dst=memub(##$global)",
1334             []>,
1335             Requires<[HasV4T]>;
1336
1337
1338 // if (!Pv) Rt=memub(##global)
1339 let neverHasSideEffects = 1, isPredicated = 1 in
1340 def LDub_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1341             (ins PredRegs:$src1, globaladdress:$global),
1342             "if (!$src1.new) $dst=memub(##$global)",
1343             []>,
1344             Requires<[HasV4T]>;
1345
1346 let isPredicable = 1, neverHasSideEffects = 1 in
1347 def LDh_GP_V4 : LDInst2<(outs IntRegs:$dst),
1348             (ins globaladdress:$global),
1349             "$dst=memh(#$global)",
1350             []>,
1351             Requires<[HasV4T]>;
1352
1353 // if (Pv) Rt=memh(##global)
1354 let neverHasSideEffects = 1, isPredicated = 1 in
1355 def LDh_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst),
1356             (ins PredRegs:$src1, globaladdress:$global),
1357             "if ($src1) $dst=memh(##$global)",
1358             []>,
1359             Requires<[HasV4T]>;
1360
1361 // if (!Pv) Rt=memh(##global)
1362 let neverHasSideEffects = 1, isPredicated = 1 in
1363 def LDh_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1364             (ins PredRegs:$src1, globaladdress:$global),
1365             "if (!$src1) $dst=memh(##$global)",
1366             []>,
1367             Requires<[HasV4T]>;
1368
1369 // if (Pv) Rt=memh(##global)
1370 let neverHasSideEffects = 1, isPredicated = 1 in
1371 def LDh_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
1372             (ins PredRegs:$src1, globaladdress:$global),
1373             "if ($src1.new) $dst=memh(##$global)",
1374             []>,
1375             Requires<[HasV4T]>;
1376
1377 // if (!Pv) Rt=memh(##global)
1378 let neverHasSideEffects = 1, isPredicated = 1 in
1379 def LDh_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1380             (ins PredRegs:$src1, globaladdress:$global),
1381             "if (!$src1.new) $dst=memh(##$global)",
1382             []>,
1383             Requires<[HasV4T]>;
1384
1385 let isPredicable = 1, neverHasSideEffects = 1 in
1386 def LDuh_GP_V4 : LDInst2<(outs IntRegs:$dst),
1387             (ins globaladdress:$global),
1388             "$dst=memuh(#$global)",
1389             []>,
1390             Requires<[HasV4T]>;
1391
1392 // if (Pv) Rt=memuh(##global)
1393 let neverHasSideEffects = 1, isPredicated = 1 in
1394 def LDuh_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst),
1395             (ins PredRegs:$src1, globaladdress:$global),
1396             "if ($src1) $dst=memuh(##$global)",
1397             []>,
1398             Requires<[HasV4T]>;
1399
1400 // if (!Pv) Rt=memuh(##global)
1401 let neverHasSideEffects = 1, isPredicated = 1 in
1402 def LDuh_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1403             (ins PredRegs:$src1, globaladdress:$global),
1404             "if (!$src1) $dst=memuh(##$global)",
1405             []>,
1406             Requires<[HasV4T]>;
1407
1408 // if (Pv) Rt=memuh(##global)
1409 let neverHasSideEffects = 1, isPredicated = 1 in
1410 def LDuh_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
1411             (ins PredRegs:$src1, globaladdress:$global),
1412             "if ($src1.new) $dst=memuh(##$global)",
1413             []>,
1414             Requires<[HasV4T]>;
1415
1416 // if (!Pv) Rt=memuh(##global)
1417 let neverHasSideEffects = 1, isPredicated = 1 in
1418 def LDuh_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1419             (ins PredRegs:$src1, globaladdress:$global),
1420             "if (!$src1.new) $dst=memuh(##$global)",
1421             []>,
1422             Requires<[HasV4T]>;
1423
1424 let isPredicable = 1, neverHasSideEffects = 1 in
1425 def LDw_GP_V4 : LDInst2<(outs IntRegs:$dst),
1426             (ins globaladdress:$global),
1427             "$dst=memw(#$global)",
1428             []>,
1429             Requires<[HasV4T]>;
1430
1431 // if (Pv) Rt=memw(##global)
1432 let neverHasSideEffects = 1, isPredicated = 1 in
1433 def LDw_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst),
1434             (ins PredRegs:$src1, globaladdress:$global),
1435             "if ($src1) $dst=memw(##$global)",
1436             []>,
1437             Requires<[HasV4T]>;
1438
1439
1440 // if (!Pv) Rt=memw(##global)
1441 let neverHasSideEffects = 1, isPredicated = 1 in
1442 def LDw_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1443             (ins PredRegs:$src1, globaladdress:$global),
1444             "if (!$src1) $dst=memw(##$global)",
1445             []>,
1446             Requires<[HasV4T]>;
1447
1448 // if (Pv) Rt=memw(##global)
1449 let neverHasSideEffects = 1, isPredicated = 1 in
1450 def LDw_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
1451             (ins PredRegs:$src1, globaladdress:$global),
1452             "if ($src1.new) $dst=memw(##$global)",
1453             []>,
1454             Requires<[HasV4T]>;
1455
1456
1457 // if (!Pv) Rt=memw(##global)
1458 let neverHasSideEffects = 1, isPredicated = 1 in
1459 def LDw_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1460             (ins PredRegs:$src1, globaladdress:$global),
1461             "if (!$src1.new) $dst=memw(##$global)",
1462             []>,
1463             Requires<[HasV4T]>;
1464
1465
1466
1467 def : Pat <(atomic_load_64 (HexagonCONST32_GP tglobaladdr:$global)),
1468            (i64 (LDd_GP_V4 tglobaladdr:$global))>,
1469             Requires<[HasV4T]>;
1470
1471 def : Pat <(atomic_load_32 (HexagonCONST32_GP tglobaladdr:$global)),
1472            (i32 (LDw_GP_V4 tglobaladdr:$global))>,
1473             Requires<[HasV4T]>;
1474
1475 def : Pat <(atomic_load_16 (HexagonCONST32_GP tglobaladdr:$global)),
1476            (i32 (LDuh_GP_V4 tglobaladdr:$global))>,
1477             Requires<[HasV4T]>;
1478
1479 def : Pat <(atomic_load_8 (HexagonCONST32_GP tglobaladdr:$global)),
1480            (i32 (LDub_GP_V4 tglobaladdr:$global))>,
1481             Requires<[HasV4T]>;
1482
1483 // Map from load(globaladdress) -> memw(#foo + 0)
1484 let AddedComplexity = 100 in
1485 def : Pat <(i64 (load (HexagonCONST32_GP tglobaladdr:$global))),
1486            (i64 (LDd_GP_V4 tglobaladdr:$global))>,
1487             Requires<[HasV4T]>;
1488
1489 // Map from Pd = load(globaladdress) -> Rd = memb(globaladdress), Pd = Rd
1490 let AddedComplexity = 100 in
1491 def : Pat <(i1 (load (HexagonCONST32_GP tglobaladdr:$global))),
1492            (i1 (TFR_PdRs (i32 (LDb_GP_V4 tglobaladdr:$global))))>,
1493            Requires<[HasV4T]>;
1494
1495 // When the Interprocedural Global Variable optimizer realizes that a certain
1496 // global variable takes only two constant values, it shrinks the global to
1497 // a boolean. Catch those loads here in the following 3 patterns.
1498 let AddedComplexity = 100 in
1499 def : Pat <(i32 (extloadi1 (HexagonCONST32_GP tglobaladdr:$global))),
1500            (i32 (LDb_GP_V4 tglobaladdr:$global))>,
1501             Requires<[HasV4T]>;
1502
1503 let AddedComplexity = 100 in
1504 def : Pat <(i32 (sextloadi1 (HexagonCONST32_GP tglobaladdr:$global))),
1505            (i32 (LDb_GP_V4 tglobaladdr:$global))>,
1506             Requires<[HasV4T]>;
1507
1508 // Map from load(globaladdress) -> memb(#foo)
1509 let AddedComplexity = 100 in
1510 def : Pat <(i32 (extloadi8 (HexagonCONST32_GP tglobaladdr:$global))),
1511            (i32 (LDb_GP_V4 tglobaladdr:$global))>,
1512             Requires<[HasV4T]>;
1513
1514 // Map from load(globaladdress) -> memb(#foo)
1515 let AddedComplexity = 100 in
1516 def : Pat <(i32 (sextloadi8 (HexagonCONST32_GP tglobaladdr:$global))),
1517            (i32 (LDb_GP_V4 tglobaladdr:$global))>,
1518             Requires<[HasV4T]>;
1519
1520 let AddedComplexity = 100 in
1521 def : Pat <(i32 (zextloadi1 (HexagonCONST32_GP tglobaladdr:$global))),
1522            (i32 (LDub_GP_V4 tglobaladdr:$global))>,
1523             Requires<[HasV4T]>;
1524
1525 // Map from load(globaladdress) -> memub(#foo)
1526 let AddedComplexity = 100 in
1527 def : Pat <(i32 (zextloadi8 (HexagonCONST32_GP tglobaladdr:$global))),
1528            (i32 (LDub_GP_V4 tglobaladdr:$global))>,
1529             Requires<[HasV4T]>;
1530
1531 // Map from load(globaladdress) -> memh(#foo)
1532 let AddedComplexity = 100 in
1533 def : Pat <(i32 (extloadi16 (HexagonCONST32_GP tglobaladdr:$global))),
1534            (i32 (LDh_GP_V4 tglobaladdr:$global))>,
1535             Requires<[HasV4T]>;
1536
1537 // Map from load(globaladdress) -> memh(#foo)
1538 let AddedComplexity = 100 in
1539 def : Pat <(i32 (sextloadi16 (HexagonCONST32_GP tglobaladdr:$global))),
1540            (i32 (LDh_GP_V4 tglobaladdr:$global))>,
1541             Requires<[HasV4T]>;
1542
1543 // Map from load(globaladdress) -> memuh(#foo)
1544 let AddedComplexity = 100 in
1545 def : Pat <(i32 (zextloadi16 (HexagonCONST32_GP tglobaladdr:$global))),
1546            (i32 (LDuh_GP_V4 tglobaladdr:$global))>,
1547             Requires<[HasV4T]>;
1548
1549 // Map from load(globaladdress) -> memw(#foo)
1550 let AddedComplexity = 100 in
1551 def : Pat <(i32 (load (HexagonCONST32_GP tglobaladdr:$global))),
1552            (i32 (LDw_GP_V4 tglobaladdr:$global))>,
1553             Requires<[HasV4T]>;
1554
1555 def : Pat <(atomic_load_64 (add (HexagonCONST32_GP tglobaladdr:$global),
1556                                 u16ImmPred:$offset)),
1557            (i64 (LDrid_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
1558            Requires<[HasV4T]>;
1559
1560 def : Pat <(atomic_load_32 (add (HexagonCONST32_GP tglobaladdr:$global),
1561                                 u16ImmPred:$offset)),
1562            (i32 (LDriw_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
1563             Requires<[HasV4T]>;
1564
1565 def : Pat <(atomic_load_16 (add (HexagonCONST32_GP tglobaladdr:$global),
1566                                 u16ImmPred:$offset)),
1567            (i32 (LDriuh_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
1568             Requires<[HasV4T]>;
1569
1570 def : Pat <(atomic_load_8 (add (HexagonCONST32_GP tglobaladdr:$global),
1571                                u16ImmPred:$offset)),
1572            (i32 (LDriub_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
1573            Requires<[HasV4T]>;
1574
1575 // Map from load(globaladdress + x) -> memd(#foo + x)
1576 let AddedComplexity = 100 in
1577 def : Pat <(i64 (load (add (HexagonCONST32_GP tglobaladdr:$global),
1578                            u16ImmPred:$offset))),
1579            (i64 (LDrid_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
1580            Requires<[HasV4T]>;
1581
1582 // Map from load(globaladdress + x) -> memb(#foo + x)
1583 let AddedComplexity = 100 in
1584 def : Pat <(i32 (extloadi8 (add (HexagonCONST32_GP tglobaladdr:$global),
1585                            u16ImmPred:$offset))),
1586            (i32 (LDrib_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
1587            Requires<[HasV4T]>;
1588
1589 // Map from load(globaladdress + x) -> memb(#foo + x)
1590 let AddedComplexity = 100 in
1591 def : Pat <(i32 (sextloadi8 (add (HexagonCONST32_GP tglobaladdr:$global),
1592                             u16ImmPred:$offset))),
1593            (i32 (LDrib_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
1594            Requires<[HasV4T]>;
1595
1596 // Map from load(globaladdress + x) -> memub(#foo + x)
1597 let AddedComplexity = 100 in
1598 def : Pat <(i32 (zextloadi8 (add (HexagonCONST32_GP tglobaladdr:$global),
1599                             u16ImmPred:$offset))),
1600            (i32 (LDriub_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
1601            Requires<[HasV4T]>;
1602
1603 // Map from load(globaladdress + x) -> memuh(#foo + x)
1604 let AddedComplexity = 100 in
1605 def : Pat <(i32 (extloadi16 (add (HexagonCONST32_GP tglobaladdr:$global),
1606                             u16ImmPred:$offset))),
1607            (i32 (LDrih_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
1608             Requires<[HasV4T]>;
1609
1610 // Map from load(globaladdress + x) -> memh(#foo + x)
1611 let AddedComplexity = 100 in
1612 def : Pat <(i32 (sextloadi16 (add (HexagonCONST32_GP tglobaladdr:$global),
1613                              u16ImmPred:$offset))),
1614            (i32 (LDrih_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
1615            Requires<[HasV4T]>;
1616
1617
1618 // Map from load(globaladdress + x) -> memuh(#foo + x)
1619 let AddedComplexity = 100 in
1620 def : Pat <(i32 (zextloadi16 (add (HexagonCONST32_GP tglobaladdr:$global),
1621                              u16ImmPred:$offset))),
1622            (i32 (LDriuh_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
1623             Requires<[HasV4T]>;
1624
1625 // Map from load(globaladdress + x) -> memw(#foo + x)
1626 let AddedComplexity = 100 in
1627 def : Pat <(i32 (load (add (HexagonCONST32_GP tglobaladdr:$global),
1628                       u16ImmPred:$offset))),
1629            (i32 (LDriw_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
1630             Requires<[HasV4T]>;
1631
1632
1633 //===----------------------------------------------------------------------===//
1634 // LD -
1635 //===----------------------------------------------------------------------===//
1636
1637 //===----------------------------------------------------------------------===//
1638 // ST +
1639 //===----------------------------------------------------------------------===//
1640 ///
1641 /// Assumptions::: ****** DO NOT IGNORE ********
1642 /// 1. Make sure that in post increment store, the zero'th operand is always the
1643 ///    post increment operand.
1644 /// 2. Make sure that the store value operand(Rt/Rtt) in a store is always the
1645 ///    last operand.
1646 ///
1647
1648 // memd(Re=#U6)=Rtt
1649 def STrid_abs_setimm_V4 : STInst2<(outs IntRegs:$dst1),
1650             (ins DoubleRegs:$src1, u6Imm:$src2),
1651             "memd($dst1=#$src2) = $src1",
1652             []>,
1653             Requires<[HasV4T]>;
1654
1655 // memb(Re=#U6)=Rs
1656 def STrib_abs_setimm_V4 : STInst2<(outs IntRegs:$dst1),
1657             (ins IntRegs:$src1, u6Imm:$src2),
1658             "memb($dst1=#$src2) = $src1",
1659             []>,
1660             Requires<[HasV4T]>;
1661
1662 // memh(Re=#U6)=Rs
1663 def STrih_abs_setimm_V4 : STInst2<(outs IntRegs:$dst1),
1664             (ins IntRegs:$src1, u6Imm:$src2),
1665             "memh($dst1=#$src2) = $src1",
1666             []>,
1667             Requires<[HasV4T]>;
1668
1669 // memw(Re=#U6)=Rs
1670 def STriw_abs_setimm_V4 : STInst2<(outs IntRegs:$dst1),
1671             (ins IntRegs:$src1, u6Imm:$src2),
1672             "memw($dst1=#$src2) = $src1",
1673             []>,
1674             Requires<[HasV4T]>;
1675
1676 // memd(Re=#U6)=Rtt
1677 def STrid_abs_set_V4 : STInst2<(outs IntRegs:$dst1),
1678             (ins DoubleRegs:$src1, globaladdress:$src2),
1679             "memd($dst1=##$src2) = $src1",
1680             []>,
1681             Requires<[HasV4T]>;
1682
1683 // memb(Re=#U6)=Rs
1684 def STrib_abs_set_V4 : STInst2<(outs IntRegs:$dst1),
1685             (ins IntRegs:$src1, globaladdress:$src2),
1686             "memb($dst1=##$src2) = $src1",
1687             []>,
1688             Requires<[HasV4T]>;
1689
1690 // memh(Re=#U6)=Rs
1691 def STrih_abs_set_V4 : STInst2<(outs IntRegs:$dst1),
1692             (ins IntRegs:$src1, globaladdress:$src2),
1693             "memh($dst1=##$src2) = $src1",
1694             []>,
1695             Requires<[HasV4T]>;
1696
1697 // memw(Re=#U6)=Rs
1698 def STriw_abs_set_V4 : STInst2<(outs IntRegs:$dst1),
1699             (ins IntRegs:$src1, globaladdress:$src2),
1700             "memw($dst1=##$src2) = $src1",
1701             []>,
1702             Requires<[HasV4T]>;
1703
1704 // memd(Rs+Ru<<#u2)=Rtt
1705 let AddedComplexity = 10, isPredicable = 1 in
1706 def STrid_indexed_shl_V4 : STInst<(outs),
1707             (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$src3, DoubleRegs:$src4),
1708             "memd($src1+$src2<<#$src3) = $src4",
1709             [(store (i64 DoubleRegs:$src4),
1710                     (add (i32 IntRegs:$src1),
1711                          (shl (i32 IntRegs:$src2), u2ImmPred:$src3)))]>,
1712             Requires<[HasV4T]>;
1713
1714 // memd(Ru<<#u2+#U6)=Rtt
1715 let AddedComplexity = 10 in
1716 def STrid_shl_V4 : STInst<(outs),
1717             (ins IntRegs:$src1, u2Imm:$src2, u6Imm:$src3, DoubleRegs:$src4),
1718             "memd($src1<<#$src2+#$src3) = $src4",
1719             [(store (i64 DoubleRegs:$src4),
1720                     (add (shl (i32 IntRegs:$src1), u2ImmPred:$src2),
1721                          u6ImmPred:$src3))]>,
1722             Requires<[HasV4T]>;
1723
1724 // memd(Rx++#s4:3)=Rtt
1725 // memd(Rx++#s4:3:circ(Mu))=Rtt
1726 // memd(Rx++I:circ(Mu))=Rtt
1727 // memd(Rx++Mu)=Rtt
1728 // memd(Rx++Mu:brev)=Rtt
1729 // memd(gp+#u16:3)=Rtt
1730
1731 // Store doubleword conditionally.
1732 // if ([!]Pv[.new]) memd(#u6)=Rtt
1733 // TODO: needs to be implemented.
1734
1735 // if ([!]Pv[.new]) memd(Rs+#u6:3)=Rtt
1736 // if (Pv) memd(Rs+#u6:3)=Rtt
1737 // if (Pv.new) memd(Rs+#u6:3)=Rtt
1738 let AddedComplexity = 10, neverHasSideEffects = 1,
1739     isPredicated = 1 in
1740 def STrid_cdnPt_V4 : STInst2<(outs),
1741             (ins PredRegs:$src1, MEMri:$addr, DoubleRegs:$src2),
1742             "if ($src1.new) memd($addr) = $src2",
1743             []>,
1744             Requires<[HasV4T]>;
1745
1746 // if (!Pv) memd(Rs+#u6:3)=Rtt
1747 // if (!Pv.new) memd(Rs+#u6:3)=Rtt
1748 let AddedComplexity = 10, neverHasSideEffects = 1,
1749     isPredicated = 1 in
1750 def STrid_cdnNotPt_V4 : STInst2<(outs),
1751             (ins PredRegs:$src1, MEMri:$addr, DoubleRegs:$src2),
1752             "if (!$src1.new) memd($addr) = $src2",
1753             []>,
1754             Requires<[HasV4T]>;
1755
1756 // if (Pv) memd(Rs+#u6:3)=Rtt
1757 // if (Pv.new) memd(Rs+#u6:3)=Rtt
1758 let AddedComplexity = 10, neverHasSideEffects = 1,
1759     isPredicated = 1 in
1760 def STrid_indexed_cdnPt_V4 : STInst2<(outs),
1761             (ins PredRegs:$src1, IntRegs:$src2, u6_3Imm:$src3,
1762                  DoubleRegs:$src4),
1763             "if ($src1.new) memd($src2+#$src3) = $src4",
1764             []>,
1765             Requires<[HasV4T]>;
1766
1767 // if (!Pv) memd(Rs+#u6:3)=Rtt
1768 // if (!Pv.new) memd(Rs+#u6:3)=Rtt
1769 let AddedComplexity = 10, neverHasSideEffects = 1,
1770     isPredicated = 1 in
1771 def STrid_indexed_cdnNotPt_V4 : STInst2<(outs),
1772             (ins PredRegs:$src1, IntRegs:$src2, u6_3Imm:$src3,
1773                  DoubleRegs:$src4),
1774             "if (!$src1.new) memd($src2+#$src3) = $src4",
1775             []>,
1776             Requires<[HasV4T]>;
1777
1778 // if ([!]Pv[.new]) memd(Rs+Ru<<#u2)=Rtt
1779 // if (Pv) memd(Rs+Ru<<#u2)=Rtt
1780 let AddedComplexity = 10, neverHasSideEffects = 1,
1781     isPredicated = 1 in
1782 def STrid_indexed_shl_cPt_V4 : STInst2<(outs),
1783             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
1784                  DoubleRegs:$src5),
1785             "if ($src1) memd($src2+$src3<<#$src4) = $src5",
1786             []>,
1787             Requires<[HasV4T]>;
1788
1789 // if (Pv.new) memd(Rs+Ru<<#u2)=Rtt
1790 let AddedComplexity = 10, neverHasSideEffects = 1,
1791     isPredicated = 1 in
1792 def STrid_indexed_shl_cdnPt_V4 : STInst2<(outs),
1793             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
1794                  DoubleRegs:$src5),
1795             "if ($src1.new) memd($src2+$src3<<#$src4) = $src5",
1796             []>,
1797             Requires<[HasV4T]>;
1798 // if (!Pv) memd(Rs+Ru<<#u2)=Rtt
1799 let AddedComplexity = 10, neverHasSideEffects = 1,
1800     isPredicated = 1 in
1801 def STrid_indexed_shl_cNotPt_V4 : STInst2<(outs),
1802             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
1803                  DoubleRegs:$src5),
1804             "if (!$src1) memd($src2+$src3<<#$src4) = $src5",
1805             []>,
1806             Requires<[HasV4T]>;
1807 // if (!Pv.new) memd(Rs+Ru<<#u2)=Rtt
1808 let AddedComplexity = 10, neverHasSideEffects = 1,
1809     isPredicated = 1 in
1810 def STrid_indexed_shl_cdnNotPt_V4 : STInst2<(outs),
1811             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
1812                  DoubleRegs:$src5),
1813             "if (!$src1.new) memd($src2+$src3<<#$src4) = $src5",
1814             []>,
1815             Requires<[HasV4T]>;
1816
1817 // if ([!]Pv[.new]) memd(Rx++#s4:3)=Rtt
1818 // if (Pv) memd(Rx++#s4:3)=Rtt
1819 // if (Pv.new) memd(Rx++#s4:3)=Rtt
1820 let AddedComplexity = 10, neverHasSideEffects = 1,
1821     isPredicated = 1 in
1822 def POST_STdri_cdnPt_V4 : STInst2PI<(outs IntRegs:$dst),
1823             (ins PredRegs:$src1, DoubleRegs:$src2, IntRegs:$src3,
1824                  s4_3Imm:$offset),
1825             "if ($src1.new) memd($src3++#$offset) = $src2",
1826             [],
1827             "$src3 = $dst">,
1828             Requires<[HasV4T]>;
1829
1830 // if (!Pv) memd(Rx++#s4:3)=Rtt
1831 // if (!Pv.new) memd(Rx++#s4:3)=Rtt
1832 let AddedComplexity = 10, neverHasSideEffects = 1,
1833     isPredicated = 1 in
1834 def POST_STdri_cdnNotPt_V4 : STInst2PI<(outs IntRegs:$dst),
1835             (ins PredRegs:$src1, DoubleRegs:$src2, IntRegs:$src3,
1836                  s4_3Imm:$offset),
1837             "if (!$src1.new) memd($src3++#$offset) = $src2",
1838             [],
1839             "$src3 = $dst">,
1840             Requires<[HasV4T]>;
1841
1842
1843 // Store byte.
1844 // memb(Rs+#u6:0)=#S8
1845 let AddedComplexity = 10, isPredicable = 1 in
1846 def STrib_imm_V4 : STInst<(outs),
1847             (ins IntRegs:$src1, u6_0Imm:$src2, s8Imm:$src3),
1848             "memb($src1+#$src2) = #$src3",
1849             [(truncstorei8 s8ImmPred:$src3, (add (i32 IntRegs:$src1),
1850                                                  u6_0ImmPred:$src2))]>,
1851             Requires<[HasV4T]>;
1852
1853 // memb(Rs+Ru<<#u2)=Rt
1854 let AddedComplexity = 10, isPredicable = 1 in
1855 def STrib_indexed_shl_V4 : STInst<(outs),
1856             (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$src3, IntRegs:$src4),
1857             "memb($src1+$src2<<#$src3) = $src4",
1858             [(truncstorei8 (i32 IntRegs:$src4),
1859                            (add (i32 IntRegs:$src1),
1860                                 (shl (i32 IntRegs:$src2),
1861                                           u2ImmPred:$src3)))]>,
1862             Requires<[HasV4T]>;
1863
1864 // memb(Ru<<#u2+#U6)=Rt
1865 let AddedComplexity = 10 in
1866 def STrib_shl_V4 : STInst<(outs),
1867             (ins IntRegs:$src1, u2Imm:$src2, u6Imm:$src3, IntRegs:$src4),
1868             "memb($src1<<#$src2+#$src3) = $src4",
1869             [(truncstorei8 (i32 IntRegs:$src4),
1870                            (add (shl (i32 IntRegs:$src1), u2ImmPred:$src2),
1871                                 u6ImmPred:$src3))]>,
1872             Requires<[HasV4T]>;
1873
1874 // memb(Rx++#s4:0:circ(Mu))=Rt
1875 // memb(Rx++I:circ(Mu))=Rt
1876 // memb(Rx++Mu)=Rt
1877 // memb(Rx++Mu:brev)=Rt
1878 // memb(gp+#u16:0)=Rt
1879
1880
1881 // Store byte conditionally.
1882 // if ([!]Pv[.new]) memb(#u6)=Rt
1883 // if ([!]Pv[.new]) memb(Rs+#u6:0)=#S6
1884 // if (Pv) memb(Rs+#u6:0)=#S6
1885 let neverHasSideEffects = 1,
1886     isPredicated = 1 in
1887 def STrib_imm_cPt_V4 : STInst2<(outs),
1888             (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, s6Imm:$src4),
1889             "if ($src1) memb($src2+#$src3) = #$src4",
1890             []>,
1891             Requires<[HasV4T]>;
1892
1893 // if (Pv.new) memb(Rs+#u6:0)=#S6
1894 let neverHasSideEffects = 1,
1895     isPredicated = 1 in
1896 def STrib_imm_cdnPt_V4 : STInst2<(outs),
1897             (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, s6Imm:$src4),
1898             "if ($src1.new) memb($src2+#$src3) = #$src4",
1899             []>,
1900             Requires<[HasV4T]>;
1901
1902 // if (!Pv) memb(Rs+#u6:0)=#S6
1903 let neverHasSideEffects = 1,
1904     isPredicated = 1 in
1905 def STrib_imm_cNotPt_V4 : STInst2<(outs),
1906             (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, s6Imm:$src4),
1907             "if (!$src1) memb($src2+#$src3) = #$src4",
1908             []>,
1909             Requires<[HasV4T]>;
1910
1911 // if (!Pv.new) memb(Rs+#u6:0)=#S6
1912 let neverHasSideEffects = 1,
1913     isPredicated = 1 in
1914 def STrib_imm_cdnNotPt_V4 : STInst2<(outs),
1915             (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, s6Imm:$src4),
1916             "if (!$src1.new) memb($src2+#$src3) = #$src4",
1917             []>,
1918             Requires<[HasV4T]>;
1919
1920 // if ([!]Pv[.new]) memb(Rs+#u6:0)=Rt
1921 // if (Pv) memb(Rs+#u6:0)=Rt
1922 // if (Pv.new) memb(Rs+#u6:0)=Rt
1923 let neverHasSideEffects = 1,
1924     isPredicated = 1 in
1925 def STrib_cdnPt_V4 : STInst2<(outs),
1926             (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
1927             "if ($src1.new) memb($addr) = $src2",
1928             []>,
1929             Requires<[HasV4T]>;
1930
1931 // if (!Pv) memb(Rs+#u6:0)=Rt
1932 // if (!Pv.new) memb(Rs+#u6:0)=Rt
1933 let neverHasSideEffects = 1,
1934     isPredicated = 1 in
1935 def STrib_cdnNotPt_V4 : STInst2<(outs),
1936             (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
1937             "if (!$src1.new) memb($addr) = $src2",
1938             []>,
1939             Requires<[HasV4T]>;
1940
1941 // if (Pv) memb(Rs+#u6:0)=Rt
1942 // if (!Pv) memb(Rs+#u6:0)=Rt
1943 // if (Pv.new) memb(Rs+#u6:0)=Rt
1944 let neverHasSideEffects = 1,
1945     isPredicated = 1 in
1946 def STrib_indexed_cdnPt_V4 : STInst2<(outs),
1947             (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, IntRegs:$src4),
1948             "if ($src1.new) memb($src2+#$src3) = $src4",
1949             []>,
1950             Requires<[HasV4T]>;
1951
1952 // if (!Pv.new) memb(Rs+#u6:0)=Rt
1953 let neverHasSideEffects = 1,
1954     isPredicated = 1 in
1955 def STrib_indexed_cdnNotPt_V4 : STInst2<(outs),
1956             (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, IntRegs:$src4),
1957             "if (!$src1.new) memb($src2+#$src3) = $src4",
1958             []>,
1959             Requires<[HasV4T]>;
1960
1961 // if ([!]Pv[.new]) memb(Rs+Ru<<#u2)=Rt
1962 // if (Pv) memb(Rs+Ru<<#u2)=Rt
1963 let AddedComplexity = 10,
1964     isPredicated = 1 in
1965 def STrib_indexed_shl_cPt_V4 : STInst2<(outs),
1966             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
1967                  IntRegs:$src5),
1968             "if ($src1) memb($src2+$src3<<#$src4) = $src5",
1969             []>,
1970             Requires<[HasV4T]>;
1971
1972 // if (Pv.new) memb(Rs+Ru<<#u2)=Rt
1973 let AddedComplexity = 10,
1974     isPredicated = 1 in
1975 def STrib_indexed_shl_cdnPt_V4 : STInst2<(outs),
1976             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
1977                  IntRegs:$src5),
1978             "if ($src1.new) memb($src2+$src3<<#$src4) = $src5",
1979             []>,
1980             Requires<[HasV4T]>;
1981
1982 // if (!Pv) memb(Rs+Ru<<#u2)=Rt
1983 let AddedComplexity = 10,
1984     isPredicated = 1 in
1985 def STrib_indexed_shl_cNotPt_V4 : STInst2<(outs),
1986             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
1987                  IntRegs:$src5),
1988             "if (!$src1) memb($src2+$src3<<#$src4) = $src5",
1989             []>,
1990             Requires<[HasV4T]>;
1991
1992 // if (!Pv.new) memb(Rs+Ru<<#u2)=Rt
1993 let AddedComplexity = 10,
1994     isPredicated = 1 in
1995 def STrib_indexed_shl_cdnNotPt_V4 : STInst2<(outs),
1996             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
1997                  IntRegs:$src5),
1998             "if (!$src1.new) memb($src2+$src3<<#$src4) = $src5",
1999             []>,
2000             Requires<[HasV4T]>;
2001
2002 // if ([!]Pv[.new]) memb(Rx++#s4:0)=Rt
2003 // if (Pv) memb(Rx++#s4:0)=Rt
2004 // if (Pv.new) memb(Rx++#s4:0)=Rt
2005 let hasCtrlDep = 1,
2006     isPredicated = 1 in
2007 def POST_STbri_cdnPt_V4 : STInst2PI<(outs IntRegs:$dst),
2008             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_0Imm:$offset),
2009             "if ($src1.new) memb($src3++#$offset) = $src2",
2010             [],"$src3 = $dst">,
2011             Requires<[HasV4T]>;
2012
2013 // if (!Pv) memb(Rx++#s4:0)=Rt
2014 // if (!Pv.new) memb(Rx++#s4:0)=Rt
2015 let hasCtrlDep = 1,
2016     isPredicated = 1 in
2017 def POST_STbri_cdnNotPt_V4 : STInst2PI<(outs IntRegs:$dst),
2018             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_0Imm:$offset),
2019             "if (!$src1.new) memb($src3++#$offset) = $src2",
2020             [],"$src3 = $dst">,
2021             Requires<[HasV4T]>;
2022
2023
2024 // Store halfword.
2025 // TODO: needs to be implemented
2026 // memh(Re=#U6)=Rt.H
2027 // memh(Rs+#s11:1)=Rt.H
2028 // memh(Rs+#u6:1)=#S8
2029 let AddedComplexity = 10, isPredicable = 1 in
2030 def STrih_imm_V4 : STInst<(outs),
2031             (ins IntRegs:$src1, u6_1Imm:$src2, s8Imm:$src3),
2032             "memh($src1+#$src2) = #$src3",
2033             [(truncstorei16 s8ImmPred:$src3, (add (i32 IntRegs:$src1),
2034                                                   u6_1ImmPred:$src2))]>,
2035             Requires<[HasV4T]>;
2036
2037 // memh(Rs+Ru<<#u2)=Rt.H
2038 // TODO: needs to be implemented.
2039
2040 // memh(Rs+Ru<<#u2)=Rt
2041 let AddedComplexity = 10, isPredicable = 1 in
2042 def STrih_indexed_shl_V4 : STInst<(outs),
2043             (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$src3, IntRegs:$src4),
2044             "memh($src1+$src2<<#$src3) = $src4",
2045             [(truncstorei16 (i32 IntRegs:$src4),
2046                             (add (i32 IntRegs:$src1),
2047                                  (shl (i32 IntRegs:$src2),
2048                                       u2ImmPred:$src3)))]>,
2049             Requires<[HasV4T]>;
2050
2051 // memh(Ru<<#u2+#U6)=Rt.H
2052 // memh(Ru<<#u2+#U6)=Rt
2053 let AddedComplexity = 10 in
2054 def STrih_shl_V4 : STInst<(outs),
2055             (ins IntRegs:$src1, u2Imm:$src2, u6Imm:$src3, IntRegs:$src4),
2056             "memh($src1<<#$src2+#$src3) = $src4",
2057             [(truncstorei16 (i32 IntRegs:$src4),
2058                             (add (shl (i32 IntRegs:$src1), u2ImmPred:$src2),
2059                                  u6ImmPred:$src3))]>,
2060             Requires<[HasV4T]>;
2061
2062 // memh(Rx++#s4:1:circ(Mu))=Rt.H
2063 // memh(Rx++#s4:1:circ(Mu))=Rt
2064 // memh(Rx++I:circ(Mu))=Rt.H
2065 // memh(Rx++I:circ(Mu))=Rt
2066 // memh(Rx++Mu)=Rt.H
2067 // memh(Rx++Mu)=Rt
2068 // memh(Rx++Mu:brev)=Rt.H
2069 // memh(Rx++Mu:brev)=Rt
2070 // memh(gp+#u16:1)=Rt
2071 // if ([!]Pv[.new]) memh(#u6)=Rt.H
2072 // if ([!]Pv[.new]) memh(#u6)=Rt
2073
2074 // if ([!]Pv[.new]) memh(Rs+#u6:1)=#S6
2075 // if (Pv) memh(Rs+#u6:1)=#S6
2076 let neverHasSideEffects = 1,
2077     isPredicated = 1 in
2078 def STrih_imm_cPt_V4 : STInst2<(outs),
2079             (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, s6Imm:$src4),
2080             "if ($src1) memh($src2+#$src3) = #$src4",
2081             []>,
2082             Requires<[HasV4T]>;
2083
2084 // if (Pv.new) memh(Rs+#u6:1)=#S6
2085 let neverHasSideEffects = 1,
2086     isPredicated = 1 in
2087 def STrih_imm_cdnPt_V4 : STInst2<(outs),
2088             (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, s6Imm:$src4),
2089             "if ($src1.new) memh($src2+#$src3) = #$src4",
2090             []>,
2091             Requires<[HasV4T]>;
2092
2093 // if (!Pv) memh(Rs+#u6:1)=#S6
2094 let neverHasSideEffects = 1,
2095     isPredicated = 1 in
2096 def STrih_imm_cNotPt_V4 : STInst2<(outs),
2097             (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, s6Imm:$src4),
2098             "if (!$src1) memh($src2+#$src3) = #$src4",
2099             []>,
2100             Requires<[HasV4T]>;
2101
2102 // if (!Pv.new) memh(Rs+#u6:1)=#S6
2103 let neverHasSideEffects = 1,
2104     isPredicated = 1 in
2105 def STrih_imm_cdnNotPt_V4 : STInst2<(outs),
2106             (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, s6Imm:$src4),
2107             "if (!$src1.new) memh($src2+#$src3) = #$src4",
2108             []>,
2109             Requires<[HasV4T]>;
2110
2111 // if ([!]Pv[.new]) memh(Rs+#u6:1)=Rt.H
2112 // TODO: needs to be implemented.
2113
2114 // if ([!]Pv[.new]) memh(Rs+#u6:1)=Rt
2115 // if (Pv) memh(Rs+#u6:1)=Rt
2116 // if (Pv.new) memh(Rs+#u6:1)=Rt
2117 let neverHasSideEffects = 1,
2118     isPredicated = 1 in
2119 def STrih_cdnPt_V4 : STInst2<(outs),
2120             (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
2121             "if ($src1.new) memh($addr) = $src2",
2122             []>,
2123             Requires<[HasV4T]>;
2124
2125 // if (!Pv) memh(Rs+#u6:1)=Rt
2126 // if (!Pv.new) memh(Rs+#u6:1)=Rt
2127 let neverHasSideEffects = 1,
2128     isPredicated = 1 in
2129 def STrih_cdnNotPt_V4 : STInst2<(outs),
2130             (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
2131             "if (!$src1.new) memh($addr) = $src2",
2132             []>,
2133             Requires<[HasV4T]>;
2134
2135 // if (Pv.new) memh(Rs+#u6:1)=Rt
2136 let neverHasSideEffects = 1,
2137     isPredicated = 1 in
2138 def STrih_indexed_cdnPt_V4 : STInst2<(outs),
2139             (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, IntRegs:$src4),
2140             "if ($src1.new) memh($src2+#$src3) = $src4",
2141             []>,
2142             Requires<[HasV4T]>;
2143
2144 // if (!Pv.new) memh(Rs+#u6:1)=Rt
2145 let neverHasSideEffects = 1,
2146     isPredicated = 1 in
2147 def STrih_indexed_cdnNotPt_V4 : STInst2<(outs),
2148             (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, IntRegs:$src4),
2149             "if (!$src1.new) memh($src2+#$src3) = $src4",
2150             []>,
2151             Requires<[HasV4T]>;
2152
2153 // if ([!]Pv[.new]) memh(Rs+Ru<<#u2)=Rt.H
2154 // if ([!]Pv[.new]) memh(Rs+Ru<<#u2)=Rt
2155 // if (Pv) memh(Rs+Ru<<#u2)=Rt
2156 let AddedComplexity = 10,
2157     isPredicated = 1 in
2158 def STrih_indexed_shl_cPt_V4 : STInst2<(outs),
2159             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
2160                  IntRegs:$src5),
2161             "if ($src1) memh($src2+$src3<<#$src4) = $src5",
2162             []>,
2163             Requires<[HasV4T]>;
2164
2165 // if (Pv.new) memh(Rs+Ru<<#u2)=Rt
2166 let AddedComplexity = 10,
2167     isPredicated = 1 in
2168 def STrih_indexed_shl_cdnPt_V4 : STInst2<(outs),
2169             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
2170                  IntRegs:$src5),
2171             "if ($src1.new) memh($src2+$src3<<#$src4) = $src5",
2172             []>,
2173             Requires<[HasV4T]>;
2174
2175 // if (!Pv) memh(Rs+Ru<<#u2)=Rt
2176 let AddedComplexity = 10,
2177     isPredicated = 1 in
2178 def STrih_indexed_shl_cNotPt_V4 : STInst2<(outs),
2179             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
2180                  IntRegs:$src5),
2181             "if (!$src1) memh($src2+$src3<<#$src4) = $src5",
2182             []>,
2183             Requires<[HasV4T]>;
2184
2185 // if (!Pv.new) memh(Rs+Ru<<#u2)=Rt
2186 let AddedComplexity = 10,
2187     isPredicated = 1 in
2188 def STrih_indexed_shl_cdnNotPt_V4 : STInst2<(outs),
2189             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
2190                  IntRegs:$src5),
2191             "if (!$src1.new) memh($src2+$src3<<#$src4) = $src5",
2192             []>,
2193             Requires<[HasV4T]>;
2194
2195 // if ([!]Pv[.new]) memh(Rx++#s4:1)=Rt.H
2196 // TODO: Needs to be implemented.
2197
2198 // if ([!]Pv[.new]) memh(Rx++#s4:1)=Rt
2199 // if (Pv) memh(Rx++#s4:1)=Rt
2200 // if (Pv.new) memh(Rx++#s4:1)=Rt
2201 let hasCtrlDep = 1,
2202     isPredicated = 1 in
2203 def POST_SThri_cdnPt_V4 : STInst2PI<(outs IntRegs:$dst),
2204             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_1Imm:$offset),
2205             "if ($src1.new) memh($src3++#$offset) = $src2",
2206             [],"$src3 = $dst">,
2207             Requires<[HasV4T]>;
2208
2209 // if (!Pv) memh(Rx++#s4:1)=Rt
2210 // if (!Pv.new) memh(Rx++#s4:1)=Rt
2211 let hasCtrlDep = 1,
2212     isPredicated = 1 in
2213 def POST_SThri_cdnNotPt_V4 : STInst2PI<(outs IntRegs:$dst),
2214             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_1Imm:$offset),
2215             "if (!$src1.new) memh($src3++#$offset) = $src2",
2216             [],"$src3 = $dst">,
2217             Requires<[HasV4T]>;
2218
2219
2220 // Store word.
2221 // memw(Re=#U6)=Rt
2222 // TODO: Needs to be implemented.
2223
2224 // Store predicate:
2225 let neverHasSideEffects = 1 in
2226 def STriw_pred_V4 : STInst2<(outs),
2227             (ins MEMri:$addr, PredRegs:$src1),
2228             "Error; should not emit",
2229             []>,
2230             Requires<[HasV4T]>;
2231
2232
2233 // memw(Rs+#u6:2)=#S8
2234 let AddedComplexity = 10, isPredicable = 1 in
2235 def STriw_imm_V4 : STInst<(outs),
2236             (ins IntRegs:$src1, u6_2Imm:$src2, s8Imm:$src3),
2237             "memw($src1+#$src2) = #$src3",
2238             [(store s8ImmPred:$src3, (add (i32 IntRegs:$src1),
2239                                           u6_2ImmPred:$src2))]>,
2240             Requires<[HasV4T]>;
2241
2242 // memw(Rs+Ru<<#u2)=Rt
2243 let AddedComplexity = 10, isPredicable = 1 in
2244 def STriw_indexed_shl_V4 : STInst<(outs),
2245             (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$src3, IntRegs:$src4),
2246             "memw($src1+$src2<<#$src3) = $src4",
2247             [(store (i32 IntRegs:$src4), (add (i32 IntRegs:$src1),
2248                                     (shl (i32 IntRegs:$src2),
2249                                          u2ImmPred:$src3)))]>,
2250             Requires<[HasV4T]>;
2251
2252 // memw(Ru<<#u2+#U6)=Rt
2253 let AddedComplexity = 10 in
2254 def STriw_shl_V4 : STInst<(outs),
2255             (ins IntRegs:$src1, u2Imm:$src2, u6Imm:$src3, IntRegs:$src4),
2256             "memw($src1<<#$src2+#$src3) = $src4",
2257             [(store (i32 IntRegs:$src4),
2258                     (add (shl (i32 IntRegs:$src1), u2ImmPred:$src2),
2259                               u6ImmPred:$src3))]>,
2260             Requires<[HasV4T]>;
2261
2262 // memw(Rx++#s4:2)=Rt
2263 // memw(Rx++#s4:2:circ(Mu))=Rt
2264 // memw(Rx++I:circ(Mu))=Rt
2265 // memw(Rx++Mu)=Rt
2266 // memw(Rx++Mu:brev)=Rt
2267 // memw(gp+#u16:2)=Rt
2268
2269
2270 // Store word conditionally.
2271
2272 // if ([!]Pv[.new]) memw(Rs+#u6:2)=#S6
2273 // if (Pv) memw(Rs+#u6:2)=#S6
2274 let neverHasSideEffects = 1,
2275     isPredicated = 1 in
2276 def STriw_imm_cPt_V4 : STInst2<(outs),
2277             (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, s6Imm:$src4),
2278             "if ($src1) memw($src2+#$src3) = #$src4",
2279             []>,
2280             Requires<[HasV4T]>;
2281
2282 // if (Pv.new) memw(Rs+#u6:2)=#S6
2283 let neverHasSideEffects = 1,
2284     isPredicated = 1 in
2285 def STriw_imm_cdnPt_V4 : STInst2<(outs),
2286             (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, s6Imm:$src4),
2287             "if ($src1.new) memw($src2+#$src3) = #$src4",
2288             []>,
2289             Requires<[HasV4T]>;
2290
2291 // if (!Pv) memw(Rs+#u6:2)=#S6
2292 let neverHasSideEffects = 1,
2293     isPredicated = 1 in
2294 def STriw_imm_cNotPt_V4 : STInst2<(outs),
2295             (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, s6Imm:$src4),
2296             "if (!$src1) memw($src2+#$src3) = #$src4",
2297             []>,
2298             Requires<[HasV4T]>;
2299
2300 // if (!Pv.new) memw(Rs+#u6:2)=#S6
2301 let neverHasSideEffects = 1,
2302     isPredicated = 1 in
2303 def STriw_imm_cdnNotPt_V4 : STInst2<(outs),
2304             (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, s6Imm:$src4),
2305             "if (!$src1.new) memw($src2+#$src3) = #$src4",
2306             []>,
2307             Requires<[HasV4T]>;
2308
2309 // if ([!]Pv[.new]) memw(Rs+#u6:2)=Rt
2310 // if (Pv) memw(Rs+#u6:2)=Rt
2311 // if (Pv.new) memw(Rs+#u6:2)=Rt
2312 let neverHasSideEffects = 1,
2313     isPredicated = 1 in
2314 def STriw_cdnPt_V4 : STInst2<(outs),
2315             (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
2316             "if ($src1.new) memw($addr) = $src2",
2317             []>,
2318             Requires<[HasV4T]>;
2319
2320 // if (!Pv) memw(Rs+#u6:2)=Rt
2321 // if (!Pv.new) memw(Rs+#u6:2)=Rt
2322 let neverHasSideEffects = 1,
2323     isPredicated = 1 in
2324 def STriw_cdnNotPt_V4 : STInst2<(outs),
2325             (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
2326             "if (!$src1.new) memw($addr) = $src2",
2327             []>,
2328             Requires<[HasV4T]>;
2329
2330 // if (Pv) memw(Rs+#u6:2)=Rt
2331 // if (!Pv) memw(Rs+#u6:2)=Rt
2332 // if (Pv.new) memw(Rs+#u6:2)=Rt
2333 let neverHasSideEffects = 1,
2334     isPredicated = 1 in
2335 def STriw_indexed_cdnPt_V4 : STInst2<(outs),
2336             (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, IntRegs:$src4),
2337             "if ($src1.new) memw($src2+#$src3) = $src4",
2338             []>,
2339             Requires<[HasV4T]>;
2340
2341 // if (!Pv.new) memw(Rs+#u6:2)=Rt
2342 let neverHasSideEffects = 1,
2343     isPredicated = 1 in
2344 def STriw_indexed_cdnNotPt_V4 : STInst2<(outs),
2345             (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, IntRegs:$src4),
2346             "if (!$src1.new) memw($src2+#$src3) = $src4",
2347             []>,
2348             Requires<[HasV4T]>;
2349
2350 // if ([!]Pv[.new]) memw(Rs+Ru<<#u2)=Rt
2351 // if (Pv) memw(Rs+Ru<<#u2)=Rt
2352 let AddedComplexity = 10,
2353     isPredicated = 1 in
2354 def STriw_indexed_shl_cPt_V4 : STInst2<(outs),
2355             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
2356                  IntRegs:$src5),
2357             "if ($src1) memw($src2+$src3<<#$src4) = $src5",
2358             []>,
2359             Requires<[HasV4T]>;
2360
2361 // if (Pv.new) memw(Rs+Ru<<#u2)=Rt
2362 let AddedComplexity = 10,
2363     isPredicated = 1 in
2364 def STriw_indexed_shl_cdnPt_V4 : STInst2<(outs),
2365             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
2366                  IntRegs:$src5),
2367             "if ($src1.new) memw($src2+$src3<<#$src4) = $src5",
2368             []>,
2369             Requires<[HasV4T]>;
2370
2371 // if (!Pv) memw(Rs+Ru<<#u2)=Rt
2372 let AddedComplexity = 10,
2373     isPredicated = 1 in
2374 def STriw_indexed_shl_cNotPt_V4 : STInst2<(outs),
2375             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
2376                  IntRegs:$src5),
2377             "if (!$src1) memw($src2+$src3<<#$src4) = $src5",
2378             []>,
2379             Requires<[HasV4T]>;
2380
2381 // if (!Pv.new) memw(Rs+Ru<<#u2)=Rt
2382 let AddedComplexity = 10,
2383     isPredicated = 1 in
2384 def STriw_indexed_shl_cdnNotPt_V4 : STInst2<(outs),
2385             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
2386                  IntRegs:$src5),
2387             "if (!$src1.new) memw($src2+$src3<<#$src4) = $src5",
2388             []>,
2389             Requires<[HasV4T]>;
2390
2391 // if ([!]Pv[.new]) memw(Rx++#s4:2)=Rt
2392 // if (Pv) memw(Rx++#s4:2)=Rt
2393 // if (Pv.new) memw(Rx++#s4:2)=Rt
2394 let hasCtrlDep = 1,
2395     isPredicated = 1 in
2396 def POST_STwri_cdnPt_V4 : STInst2PI<(outs IntRegs:$dst),
2397             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset),
2398             "if ($src1.new) memw($src3++#$offset) = $src2",
2399             [],"$src3 = $dst">,
2400             Requires<[HasV4T]>;
2401
2402 // if (!Pv) memw(Rx++#s4:2)=Rt
2403 // if (!Pv.new) memw(Rx++#s4:2)=Rt
2404 let hasCtrlDep = 1,
2405     isPredicated = 1 in
2406 def POST_STwri_cdnNotPt_V4 : STInst2PI<(outs IntRegs:$dst),
2407             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset),
2408             "if (!$src1.new) memw($src3++#$offset) = $src2",
2409             [],"$src3 = $dst">,
2410             Requires<[HasV4T]>;
2411
2412
2413 /// store to global address
2414
2415 let isPredicable = 1, neverHasSideEffects = 1 in
2416 def STrid_GP_V4 : STInst2<(outs),
2417             (ins globaladdress:$global, u16Imm:$offset, DoubleRegs:$src),
2418             "memd(#$global+$offset) = $src",
2419             []>,
2420             Requires<[HasV4T]>;
2421
2422 let neverHasSideEffects = 1, isPredicated = 1 in
2423 def STrid_GP_cPt_V4 : STInst2<(outs),
2424             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2425                                                         DoubleRegs:$src2),
2426             "if ($src1) memd(##$global+$offset) = $src2",
2427             []>,
2428             Requires<[HasV4T]>;
2429
2430 let neverHasSideEffects = 1, isPredicated = 1 in
2431 def STrid_GP_cNotPt_V4 : STInst2<(outs),
2432             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2433                                                         DoubleRegs:$src2),
2434             "if (!$src1) memd(##$global+$offset) = $src2",
2435             []>,
2436             Requires<[HasV4T]>;
2437
2438 let neverHasSideEffects = 1, isPredicated = 1 in
2439 def STrid_GP_cdnPt_V4 : STInst2<(outs),
2440             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2441                                                         DoubleRegs:$src2),
2442             "if ($src1.new) memd(##$global+$offset) = $src2",
2443             []>,
2444             Requires<[HasV4T]>;
2445
2446 let neverHasSideEffects = 1, isPredicated = 1 in
2447 def STrid_GP_cdnNotPt_V4 : STInst2<(outs),
2448             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2449                                                         DoubleRegs:$src2),
2450             "if (!$src1.new) memd(##$global+$offset) = $src2",
2451             []>,
2452             Requires<[HasV4T]>;
2453
2454 let isPredicable = 1, neverHasSideEffects = 1 in
2455 def STrib_GP_V4 : STInst2<(outs),
2456             (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),
2457             "memb(#$global+$offset) = $src",
2458             []>,
2459             Requires<[HasV4T]>;
2460
2461 let neverHasSideEffects = 1, isPredicated = 1 in
2462 def STrib_GP_cPt_V4 : STInst2<(outs),
2463             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2464                                                         IntRegs:$src2),
2465             "if ($src1) memb(##$global+$offset) = $src2",
2466             []>,
2467             Requires<[HasV4T]>;
2468
2469 let neverHasSideEffects = 1, isPredicated = 1 in
2470 def STrib_GP_cNotPt_V4 : STInst2<(outs),
2471             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2472                                                         IntRegs:$src2),
2473             "if (!$src1) memb(##$global+$offset) = $src2",
2474             []>,
2475             Requires<[HasV4T]>;
2476
2477 let neverHasSideEffects = 1, isPredicated = 1 in
2478 def STrib_GP_cdnPt_V4 : STInst2<(outs),
2479             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2480                                                         IntRegs:$src2),
2481             "if ($src1.new) memb(##$global+$offset) = $src2",
2482             []>,
2483             Requires<[HasV4T]>;
2484
2485 let neverHasSideEffects = 1, isPredicated = 1 in
2486 def STrib_GP_cdnNotPt_V4 : STInst2<(outs),
2487             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2488                                                         IntRegs:$src2),
2489             "if (!$src1.new) memb(##$global+$offset) = $src2",
2490             []>,
2491             Requires<[HasV4T]>;
2492
2493 let isPredicable = 1, neverHasSideEffects = 1 in
2494 def STrih_GP_V4 : STInst2<(outs),
2495             (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),
2496             "memh(#$global+$offset) = $src",
2497             []>,
2498             Requires<[HasV4T]>;
2499
2500 let neverHasSideEffects = 1, isPredicated = 1 in
2501 def STrih_GP_cPt_V4 : STInst2<(outs),
2502             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2503                                                         IntRegs:$src2),
2504             "if ($src1) memh(##$global+$offset) = $src2",
2505             []>,
2506             Requires<[HasV4T]>;
2507
2508 let neverHasSideEffects = 1, isPredicated = 1 in
2509 def STrih_GP_cNotPt_V4 : STInst2<(outs),
2510             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2511                                                         IntRegs:$src2),
2512             "if (!$src1) memh(##$global+$offset) = $src2",
2513             []>,
2514             Requires<[HasV4T]>;
2515
2516 let neverHasSideEffects = 1, isPredicated = 1 in
2517 def STrih_GP_cdnPt_V4 : STInst2<(outs),
2518             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2519                                                         IntRegs:$src2),
2520             "if ($src1.new) memh(##$global+$offset) = $src2",
2521             []>,
2522             Requires<[HasV4T]>;
2523
2524 let neverHasSideEffects = 1, isPredicated = 1 in
2525 def STrih_GP_cdnNotPt_V4 : STInst2<(outs),
2526             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2527                                                         IntRegs:$src2),
2528             "if (!$src1.new) memh(##$global+$offset) = $src2",
2529             []>,
2530             Requires<[HasV4T]>;
2531
2532 let isPredicable = 1, neverHasSideEffects = 1 in
2533 def STriw_GP_V4 : STInst2<(outs),
2534             (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),
2535             "memw(#$global+$offset) = $src",
2536             []>,
2537             Requires<[HasV4T]>;
2538
2539 let neverHasSideEffects = 1, isPredicated = 1 in
2540 def STriw_GP_cPt_V4 : STInst2<(outs),
2541             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2542                                                         IntRegs:$src2),
2543             "if ($src1) memw(##$global+$offset) = $src2",
2544             []>,
2545             Requires<[HasV4T]>;
2546
2547 let neverHasSideEffects = 1, isPredicated = 1 in
2548 def STriw_GP_cNotPt_V4 : STInst2<(outs),
2549             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2550                                                         IntRegs:$src2),
2551             "if (!$src1) memw(##$global+$offset) = $src2",
2552             []>,
2553             Requires<[HasV4T]>;
2554
2555 let neverHasSideEffects = 1, isPredicated = 1 in
2556 def STriw_GP_cdnPt_V4 : STInst2<(outs),
2557             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2558                                                         IntRegs:$src2),
2559             "if ($src1.new) memw(##$global+$offset) = $src2",
2560             []>,
2561             Requires<[HasV4T]>;
2562
2563 let neverHasSideEffects = 1, isPredicated = 1 in
2564 def STriw_GP_cdnNotPt_V4 : STInst2<(outs),
2565             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2566                                                         IntRegs:$src2),
2567             "if (!$src1.new) memw(##$global+$offset) = $src2",
2568             []>,
2569             Requires<[HasV4T]>;
2570
2571 // memd(#global)=Rtt
2572 let isPredicable = 1, neverHasSideEffects = 1 in
2573 def STd_GP_V4 : STInst2<(outs),
2574             (ins globaladdress:$global, DoubleRegs:$src),
2575             "memd(#$global) = $src",
2576             []>,
2577             Requires<[HasV4T]>;
2578
2579 // if (Pv) memd(##global) = Rtt
2580 let neverHasSideEffects = 1, isPredicated = 1 in
2581 def STd_GP_cPt_V4 : STInst2<(outs),
2582             (ins PredRegs:$src1, globaladdress:$global, DoubleRegs:$src2),
2583             "if ($src1) memd(##$global) = $src2",
2584             []>,
2585             Requires<[HasV4T]>;
2586
2587 // if (!Pv) memd(##global) = Rtt
2588 let neverHasSideEffects = 1, isPredicated = 1 in
2589 def STd_GP_cNotPt_V4 : STInst2<(outs),
2590             (ins PredRegs:$src1, globaladdress:$global, DoubleRegs:$src2),
2591             "if (!$src1) memd(##$global) = $src2",
2592             []>,
2593               Requires<[HasV4T]>;
2594
2595 // if (Pv) memd(##global) = Rtt
2596 let neverHasSideEffects = 1, isPredicated = 1 in
2597 def STd_GP_cdnPt_V4 : STInst2<(outs),
2598             (ins PredRegs:$src1, globaladdress:$global, DoubleRegs:$src2),
2599             "if ($src1.new) memd(##$global) = $src2",
2600             []>,
2601               Requires<[HasV4T]>;
2602
2603 // if (!Pv) memd(##global) = Rtt
2604 let neverHasSideEffects = 1, isPredicated = 1 in
2605 def STd_GP_cdnNotPt_V4 : STInst2<(outs),
2606             (ins PredRegs:$src1, globaladdress:$global, DoubleRegs:$src2),
2607             "if (!$src1.new) memd(##$global) = $src2",
2608             []>,
2609             Requires<[HasV4T]>;
2610
2611 // memb(#global)=Rt
2612 let isPredicable = 1, neverHasSideEffects = 1 in
2613 def STb_GP_V4 : STInst2<(outs),
2614             (ins globaladdress:$global, IntRegs:$src),
2615             "memb(#$global) = $src",
2616             []>,
2617             Requires<[HasV4T]>;
2618
2619 // if (Pv) memb(##global) = Rt
2620 let neverHasSideEffects = 1, isPredicated = 1 in
2621 def STb_GP_cPt_V4 : STInst2<(outs),
2622             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2623             "if ($src1) memb(##$global) = $src2",
2624               []>,
2625               Requires<[HasV4T]>;
2626
2627 // if (!Pv) memb(##global) = Rt
2628 let neverHasSideEffects = 1, isPredicated = 1 in
2629 def STb_GP_cNotPt_V4 : STInst2<(outs),
2630             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2631             "if (!$src1) memb(##$global) = $src2",
2632               []>,
2633               Requires<[HasV4T]>;
2634
2635 // if (Pv) memb(##global) = Rt
2636 let neverHasSideEffects = 1, isPredicated = 1 in
2637 def STb_GP_cdnPt_V4 : STInst2<(outs),
2638             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2639             "if ($src1.new) memb(##$global) = $src2",
2640               []>,
2641               Requires<[HasV4T]>;
2642
2643 // if (!Pv) memb(##global) = Rt
2644 let neverHasSideEffects = 1, isPredicated = 1 in
2645 def STb_GP_cdnNotPt_V4 : STInst2<(outs),
2646             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2647             "if (!$src1.new) memb(##$global) = $src2",
2648               []>,
2649               Requires<[HasV4T]>;
2650
2651 // memh(#global)=Rt
2652 let isPredicable = 1, neverHasSideEffects = 1 in
2653 def STh_GP_V4 : STInst2<(outs),
2654             (ins globaladdress:$global, IntRegs:$src),
2655             "memh(#$global) = $src",
2656             []>,
2657             Requires<[HasV4T]>;
2658
2659 // if (Pv) memh(##global) = Rt
2660 let neverHasSideEffects = 1, isPredicated = 1 in
2661 def STh_GP_cPt_V4 : STInst2<(outs),
2662             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2663             "if ($src1) memh(##$global) = $src2",
2664               []>,
2665               Requires<[HasV4T]>;
2666
2667 // if (!Pv) memh(##global) = Rt
2668 let neverHasSideEffects = 1, isPredicated = 1 in
2669 def STh_GP_cNotPt_V4 : STInst2<(outs),
2670             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2671             "if (!$src1) memh(##$global) = $src2",
2672               []>,
2673               Requires<[HasV4T]>;
2674
2675 // if (Pv) memh(##global) = Rt
2676 let neverHasSideEffects = 1, isPredicated = 1 in
2677 def STh_GP_cdnPt_V4 : STInst2<(outs),
2678             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2679             "if ($src1.new) memh(##$global) = $src2",
2680               []>,
2681               Requires<[HasV4T]>;
2682
2683 // if (!Pv) memh(##global) = Rt
2684 let neverHasSideEffects = 1, isPredicated = 1 in
2685 def STh_GP_cdnNotPt_V4 : STInst2<(outs),
2686             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2687             "if (!$src1.new) memh(##$global) = $src2",
2688               []>,
2689               Requires<[HasV4T]>;
2690
2691 // memw(#global)=Rt
2692 let isPredicable = 1, neverHasSideEffects = 1 in
2693 def STw_GP_V4 : STInst2<(outs),
2694             (ins globaladdress:$global, IntRegs:$src),
2695             "memw(#$global) = $src",
2696               []>,
2697               Requires<[HasV4T]>;
2698
2699 // if (Pv) memw(##global) = Rt
2700 let neverHasSideEffects = 1, isPredicated = 1 in
2701 def STw_GP_cPt_V4 : STInst2<(outs),
2702             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2703             "if ($src1) memw(##$global) = $src2",
2704               []>,
2705               Requires<[HasV4T]>;
2706
2707 // if (!Pv) memw(##global) = Rt
2708 let neverHasSideEffects = 1, isPredicated = 1 in
2709 def STw_GP_cNotPt_V4 : STInst2<(outs),
2710             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2711             "if (!$src1) memw(##$global) = $src2",
2712               []>,
2713               Requires<[HasV4T]>;
2714
2715 // if (Pv) memw(##global) = Rt
2716 let neverHasSideEffects = 1, isPredicated = 1 in
2717 def STw_GP_cdnPt_V4 : STInst2<(outs),
2718             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2719             "if ($src1.new) memw(##$global) = $src2",
2720               []>,
2721               Requires<[HasV4T]>;
2722
2723 // if (!Pv) memw(##global) = Rt
2724 let neverHasSideEffects = 1, isPredicated = 1 in
2725 def STw_GP_cdnNotPt_V4 : STInst2<(outs),
2726             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2727             "if (!$src1.new) memw(##$global) = $src2",
2728             []>,
2729               Requires<[HasV4T]>;
2730
2731 // 64 bit atomic store
2732 def : Pat <(atomic_store_64 (HexagonCONST32_GP tglobaladdr:$global),
2733                             (i64 DoubleRegs:$src1)),
2734            (STd_GP_V4 tglobaladdr:$global, (i64 DoubleRegs:$src1))>,
2735            Requires<[HasV4T]>;
2736
2737 // Map from store(globaladdress) -> memd(#foo)
2738 let AddedComplexity = 100 in
2739 def : Pat <(store (i64 DoubleRegs:$src1),
2740                   (HexagonCONST32_GP tglobaladdr:$global)),
2741            (STd_GP_V4 tglobaladdr:$global, (i64 DoubleRegs:$src1))>,
2742            Requires<[HasV4T]>;
2743
2744 // 8 bit atomic store
2745 def : Pat < (atomic_store_8 (HexagonCONST32_GP tglobaladdr:$global),
2746                             (i32 IntRegs:$src1)),
2747             (STb_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>,
2748               Requires<[HasV4T]>;
2749
2750 // Map from store(globaladdress) -> memb(#foo)
2751 let AddedComplexity = 100 in
2752 def : Pat<(truncstorei8 (i32 IntRegs:$src1),
2753           (HexagonCONST32_GP tglobaladdr:$global)),
2754           (STb_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>,
2755           Requires<[HasV4T]>;
2756
2757 // Map from "i1 = constant<-1>; memw(CONST32(#foo)) = i1"
2758 //       to "r0 = 1; memw(#foo) = r0"
2759 let AddedComplexity = 100 in
2760 def : Pat<(store (i1 -1), (HexagonCONST32_GP tglobaladdr:$global)),
2761           (STb_GP_V4 tglobaladdr:$global, (TFRI 1))>,
2762           Requires<[HasV4T]>;
2763
2764 def : Pat<(atomic_store_16 (HexagonCONST32_GP tglobaladdr:$global),
2765                            (i32 IntRegs:$src1)),
2766           (STh_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>,
2767           Requires<[HasV4T]>;
2768
2769 // Map from store(globaladdress) -> memh(#foo)
2770 let AddedComplexity = 100 in
2771 def : Pat<(truncstorei16 (i32 IntRegs:$src1),
2772                          (HexagonCONST32_GP tglobaladdr:$global)),
2773           (STh_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>,
2774           Requires<[HasV4T]>;
2775
2776 // 32 bit atomic store
2777 def : Pat<(atomic_store_32 (HexagonCONST32_GP tglobaladdr:$global),
2778                            (i32 IntRegs:$src1)),
2779           (STw_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>,
2780           Requires<[HasV4T]>;
2781
2782 // Map from store(globaladdress) -> memw(#foo)
2783 let AddedComplexity = 100 in
2784 def : Pat<(store (i32 IntRegs:$src1), (HexagonCONST32_GP tglobaladdr:$global)),
2785           (STw_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>,
2786           Requires<[HasV4T]>;
2787
2788 def : Pat<(atomic_store_64 (add (HexagonCONST32_GP tglobaladdr:$global),
2789                                 u16ImmPred:$offset),
2790                            (i64 DoubleRegs:$src1)),
2791           (STrid_GP_V4 tglobaladdr:$global, u16ImmPred:$offset,
2792                                             (i64 DoubleRegs:$src1))>,
2793           Requires<[HasV4T]>;
2794
2795 def : Pat<(atomic_store_32 (add (HexagonCONST32_GP tglobaladdr:$global),
2796                                 u16ImmPred:$offset),
2797                            (i32 IntRegs:$src1)),
2798           (STriw_GP_V4 tglobaladdr:$global, u16ImmPred:$offset,
2799                                             (i32 IntRegs:$src1))>,
2800           Requires<[HasV4T]>;
2801
2802 def : Pat<(atomic_store_16 (add (HexagonCONST32_GP tglobaladdr:$global),
2803                                 u16ImmPred:$offset),
2804                            (i32 IntRegs:$src1)),
2805           (STrih_GP_V4 tglobaladdr:$global, u16ImmPred:$offset,
2806                                             (i32 IntRegs:$src1))>,
2807           Requires<[HasV4T]>;
2808
2809 def : Pat<(atomic_store_8 (add (HexagonCONST32_GP tglobaladdr:$global),
2810                                u16ImmPred:$offset),
2811                           (i32 IntRegs:$src1)),
2812           (STrib_GP_V4 tglobaladdr:$global, u16ImmPred:$offset,
2813                                             (i32 IntRegs:$src1))>,
2814           Requires<[HasV4T]>;
2815
2816 // Map from store(globaladdress + x) -> memd(#foo + x)
2817 let AddedComplexity = 100 in
2818 def : Pat<(store (i64 DoubleRegs:$src1),
2819                     (add (HexagonCONST32_GP tglobaladdr:$global),
2820                                         u16ImmPred:$offset)),
2821           (STrid_GP_V4 tglobaladdr:$global, u16ImmPred:$offset,
2822                                             (i64 DoubleRegs:$src1))>,
2823           Requires<[HasV4T]>;
2824
2825 // Map from store(globaladdress + x) -> memb(#foo + x)
2826 let AddedComplexity = 100 in
2827 def : Pat<(truncstorei8 (i32 IntRegs:$src1),
2828                         (add (HexagonCONST32_GP tglobaladdr:$global),
2829                              u16ImmPred:$offset)),
2830           (STrib_GP_V4 tglobaladdr:$global, u16ImmPred:$offset,
2831                                             (i32 IntRegs:$src1))>,
2832           Requires<[HasV4T]>;
2833
2834 // Map from store(globaladdress + x) -> memh(#foo + x)
2835 let AddedComplexity = 100 in
2836 def : Pat<(truncstorei16 (i32 IntRegs:$src1),
2837                          (add (HexagonCONST32_GP tglobaladdr:$global),
2838                               u16ImmPred:$offset)),
2839           (STrih_GP_V4 tglobaladdr:$global, u16ImmPred:$offset,
2840                                             (i32 IntRegs:$src1))>,
2841           Requires<[HasV4T]>;
2842
2843 // Map from store(globaladdress + x) -> memw(#foo + x)
2844 let AddedComplexity = 100 in
2845 def : Pat<(store (i32 IntRegs:$src1),
2846                  (add (HexagonCONST32_GP tglobaladdr:$global),
2847                                 u16ImmPred:$offset)),
2848           (STriw_GP_V4 tglobaladdr:$global, u16ImmPred:$offset,
2849                                             (i32 IntRegs:$src1))>,
2850           Requires<[HasV4T]>;
2851
2852
2853
2854 //===----------------------------------------------------------------------===
2855 // ST -
2856 //===----------------------------------------------------------------------===
2857
2858
2859 //===----------------------------------------------------------------------===//
2860 // NV/ST +
2861 //===----------------------------------------------------------------------===//
2862
2863 // Store new-value byte.
2864
2865 // memb(Re=#U6)=Nt.new
2866 // memb(Rs+#s11:0)=Nt.new
2867 let mayStore = 1, isPredicable = 1 in
2868 def STrib_nv_V4 : NVInst_V4<(outs), (ins MEMri:$addr, IntRegs:$src1),
2869             "memb($addr) = $src1.new",
2870             []>,
2871             Requires<[HasV4T]>;
2872
2873 let mayStore = 1, isPredicable = 1 in
2874 def STrib_indexed_nv_V4 : NVInst_V4<(outs),
2875             (ins IntRegs:$src1, s11_0Imm:$src2, IntRegs:$src3),
2876             "memb($src1+#$src2) = $src3.new",
2877             []>,
2878             Requires<[HasV4T]>;
2879
2880 // memb(Rs+Ru<<#u2)=Nt.new
2881 let mayStore = 1, AddedComplexity = 10, isPredicable = 1 in
2882 def STrib_indexed_shl_nv_V4 : NVInst_V4<(outs),
2883             (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$src3, IntRegs:$src4),
2884             "memb($src1+$src2<<#$src3) = $src4.new",
2885             []>,
2886             Requires<[HasV4T]>;
2887
2888 // memb(Ru<<#u2+#U6)=Nt.new
2889 let mayStore = 1, AddedComplexity = 10 in
2890 def STrib_shl_nv_V4 : NVInst_V4<(outs),
2891             (ins IntRegs:$src1, u2Imm:$src2, u6Imm:$src3, IntRegs:$src4),
2892             "memb($src1<<#$src2+#$src3) = $src4.new",
2893             []>,
2894             Requires<[HasV4T]>;
2895
2896 // memb(Rx++#s4:0)=Nt.new
2897 let mayStore = 1, hasCtrlDep = 1, isPredicable = 1  in
2898 def POST_STbri_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
2899             (ins IntRegs:$src1, IntRegs:$src2, s4_0Imm:$offset),
2900             "memb($src2++#$offset) = $src1.new",
2901             [],
2902             "$src2 = $dst">,
2903             Requires<[HasV4T]>;
2904
2905 // memb(Rx++#s4:0:circ(Mu))=Nt.new
2906 // memb(Rx++I:circ(Mu))=Nt.new
2907 // memb(Rx++Mu)=Nt.new
2908 // memb(Rx++Mu:brev)=Nt.new
2909
2910 // memb(gp+#u16:0)=Nt.new
2911 let mayStore = 1, neverHasSideEffects = 1 in
2912 def STrib_GP_nv_V4 : NVInst_V4<(outs),
2913             (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),
2914             "memb(#$global+$offset) = $src.new",
2915             []>,
2916             Requires<[HasV4T]>;
2917
2918 // memb(#global)=Nt.new
2919 let mayStore = 1, neverHasSideEffects = 1 in
2920 def STb_GP_nv_V4 : NVInst_V4<(outs),
2921             (ins globaladdress:$global, IntRegs:$src),
2922             "memb(#$global) = $src.new",
2923             []>,
2924             Requires<[HasV4T]>;
2925
2926 // Store new-value byte conditionally.
2927 // if ([!]Pv[.new]) memb(#u6)=Nt.new
2928 // if (Pv) memb(Rs+#u6:0)=Nt.new
2929 let mayStore = 1, neverHasSideEffects = 1,
2930     isPredicated = 1 in
2931 def STrib_cPt_nv_V4 : NVInst_V4<(outs),
2932             (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
2933             "if ($src1) memb($addr) = $src2.new",
2934             []>,
2935             Requires<[HasV4T]>;
2936
2937 // if (Pv.new) memb(Rs+#u6:0)=Nt.new
2938 let mayStore = 1, neverHasSideEffects = 1,
2939     isPredicated = 1 in
2940 def STrib_cdnPt_nv_V4 : NVInst_V4<(outs),
2941             (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
2942             "if ($src1.new) memb($addr) = $src2.new",
2943             []>,
2944             Requires<[HasV4T]>;
2945
2946 // if (!Pv) memb(Rs+#u6:0)=Nt.new
2947 let mayStore = 1, neverHasSideEffects = 1,
2948     isPredicated = 1 in
2949 def STrib_cNotPt_nv_V4 : NVInst_V4<(outs),
2950             (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
2951             "if (!$src1) memb($addr) = $src2.new",
2952             []>,
2953             Requires<[HasV4T]>;
2954
2955 // if (!Pv.new) memb(Rs+#u6:0)=Nt.new
2956 let mayStore = 1, neverHasSideEffects = 1,
2957     isPredicated = 1 in
2958 def STrib_cdnNotPt_nv_V4 : NVInst_V4<(outs),
2959             (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
2960             "if (!$src1.new) memb($addr) = $src2.new",
2961             []>,
2962             Requires<[HasV4T]>;
2963
2964 // if (Pv) memb(Rs+#u6:0)=Nt.new
2965 let mayStore = 1, neverHasSideEffects = 1,
2966     isPredicated = 1 in
2967 def STrib_indexed_cPt_nv_V4 : NVInst_V4<(outs),
2968             (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, IntRegs:$src4),
2969             "if ($src1) memb($src2+#$src3) = $src4.new",
2970             []>,
2971             Requires<[HasV4T]>;
2972
2973 // if (Pv.new) memb(Rs+#u6:0)=Nt.new
2974 let mayStore = 1, neverHasSideEffects = 1,
2975     isPredicated = 1 in
2976 def STrib_indexed_cdnPt_nv_V4 : NVInst_V4<(outs),
2977             (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, IntRegs:$src4),
2978             "if ($src1.new) memb($src2+#$src3) = $src4.new",
2979             []>,
2980             Requires<[HasV4T]>;
2981
2982 // if (!Pv) memb(Rs+#u6:0)=Nt.new
2983 let mayStore = 1, neverHasSideEffects = 1,
2984     isPredicated = 1 in
2985 def STrib_indexed_cNotPt_nv_V4 : NVInst_V4<(outs),
2986             (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, IntRegs:$src4),
2987             "if (!$src1) memb($src2+#$src3) = $src4.new",
2988             []>,
2989             Requires<[HasV4T]>;
2990
2991 // if (!Pv.new) memb(Rs+#u6:0)=Nt.new
2992 let mayStore = 1, neverHasSideEffects = 1,
2993     isPredicated = 1 in
2994 def STrib_indexed_cdnNotPt_nv_V4 : NVInst_V4<(outs),
2995             (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, IntRegs:$src4),
2996             "if (!$src1.new) memb($src2+#$src3) = $src4.new",
2997             []>,
2998             Requires<[HasV4T]>;
2999
3000
3001 // if ([!]Pv[.new]) memb(Rs+Ru<<#u2)=Nt.new
3002 // if (Pv) memb(Rs+Ru<<#u2)=Nt.new
3003 let mayStore = 1, AddedComplexity = 10,
3004     isPredicated = 1 in
3005 def STrib_indexed_shl_cPt_nv_V4 : NVInst_V4<(outs),
3006             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
3007                  IntRegs:$src5),
3008             "if ($src1) memb($src2+$src3<<#$src4) = $src5.new",
3009             []>,
3010             Requires<[HasV4T]>;
3011
3012 // if (Pv.new) memb(Rs+Ru<<#u2)=Nt.new
3013 let mayStore = 1, AddedComplexity = 10,
3014     isPredicated = 1 in
3015 def STrib_indexed_shl_cdnPt_nv_V4 : NVInst_V4<(outs),
3016             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
3017                  IntRegs:$src5),
3018             "if ($src1.new) memb($src2+$src3<<#$src4) = $src5.new",
3019             []>,
3020             Requires<[HasV4T]>;
3021
3022 // if (!Pv) memb(Rs+Ru<<#u2)=Nt.new
3023 let mayStore = 1, AddedComplexity = 10,
3024     isPredicated = 1 in
3025 def STrib_indexed_shl_cNotPt_nv_V4 : NVInst_V4<(outs),
3026             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
3027                  IntRegs:$src5),
3028             "if (!$src1) memb($src2+$src3<<#$src4) = $src5.new",
3029             []>,
3030             Requires<[HasV4T]>;
3031
3032 // if (!Pv.new) memb(Rs+Ru<<#u2)=Nt.new
3033 let mayStore = 1, AddedComplexity = 10,
3034     isPredicated = 1 in
3035 def STrib_indexed_shl_cdnNotPt_nv_V4 : NVInst_V4<(outs),
3036             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
3037                  IntRegs:$src5),
3038             "if (!$src1.new) memb($src2+$src3<<#$src4) = $src5.new",
3039             []>,
3040             Requires<[HasV4T]>;
3041
3042 // if ([!]Pv[.new]) memb(Rx++#s4:0)=Nt.new
3043 // if (Pv) memb(Rx++#s4:0)=Nt.new
3044 let mayStore = 1, hasCtrlDep = 1,
3045     isPredicated = 1 in
3046 def POST_STbri_cPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
3047             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_0Imm:$offset),
3048             "if ($src1) memb($src3++#$offset) = $src2.new",
3049             [],"$src3 = $dst">,
3050             Requires<[HasV4T]>;
3051
3052 // if (Pv.new) memb(Rx++#s4:0)=Nt.new
3053 let mayStore = 1, hasCtrlDep = 1,
3054     isPredicated = 1 in
3055 def POST_STbri_cdnPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
3056             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_0Imm:$offset),
3057             "if ($src1.new) memb($src3++#$offset) = $src2.new",
3058             [],"$src3 = $dst">,
3059             Requires<[HasV4T]>;
3060
3061 // if (!Pv) memb(Rx++#s4:0)=Nt.new
3062 let mayStore = 1, hasCtrlDep = 1,
3063     isPredicated = 1 in
3064 def POST_STbri_cNotPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
3065             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_0Imm:$offset),
3066             "if (!$src1) memb($src3++#$offset) = $src2.new",
3067             [],"$src3 = $dst">,
3068             Requires<[HasV4T]>;
3069
3070 // if (!Pv.new) memb(Rx++#s4:0)=Nt.new
3071 let mayStore = 1, hasCtrlDep = 1,
3072     isPredicated = 1 in
3073 def POST_STbri_cdnNotPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
3074             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_0Imm:$offset),
3075             "if (!$src1.new) memb($src3++#$offset) = $src2.new",
3076             [],"$src3 = $dst">,
3077             Requires<[HasV4T]>;
3078
3079
3080 // Store new-value halfword.
3081 // memh(Re=#U6)=Nt.new
3082 // memh(Rs+#s11:1)=Nt.new
3083 let mayStore = 1, isPredicable = 1 in
3084 def STrih_nv_V4 : NVInst_V4<(outs), (ins MEMri:$addr, IntRegs:$src1),
3085             "memh($addr) = $src1.new",
3086             []>,
3087             Requires<[HasV4T]>;
3088
3089 let mayStore = 1, isPredicable = 1 in
3090 def STrih_indexed_nv_V4 : NVInst_V4<(outs),
3091             (ins IntRegs:$src1, s11_1Imm:$src2, IntRegs:$src3),
3092             "memh($src1+#$src2) = $src3.new",
3093             []>,
3094             Requires<[HasV4T]>;
3095
3096 // memh(Rs+Ru<<#u2)=Nt.new
3097 let mayStore = 1, AddedComplexity = 10, isPredicable = 1 in
3098 def STrih_indexed_shl_nv_V4 : NVInst_V4<(outs),
3099             (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$src3, IntRegs:$src4),
3100             "memh($src1+$src2<<#$src3) = $src4.new",
3101             []>,
3102             Requires<[HasV4T]>;
3103
3104 // memh(Ru<<#u2+#U6)=Nt.new
3105 let mayStore = 1, AddedComplexity = 10 in
3106 def STrih_shl_nv_V4 : NVInst_V4<(outs),
3107             (ins IntRegs:$src1, u2Imm:$src2, u6Imm:$src3, IntRegs:$src4),
3108             "memh($src1<<#$src2+#$src3) = $src4.new",
3109             []>,
3110             Requires<[HasV4T]>;
3111
3112 // memh(Rx++#s4:1)=Nt.new
3113 let mayStore = 1, hasCtrlDep = 1, isPredicable = 1  in
3114 def POST_SThri_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
3115             (ins IntRegs:$src1, IntRegs:$src2, s4_1Imm:$offset),
3116             "memh($src2++#$offset) = $src1.new",
3117             [],
3118             "$src2 = $dst">,
3119             Requires<[HasV4T]>;
3120
3121 // memh(Rx++#s4:1:circ(Mu))=Nt.new
3122 // memh(Rx++I:circ(Mu))=Nt.new
3123 // memh(Rx++Mu)=Nt.new
3124 // memh(Rx++Mu:brev)=Nt.new
3125
3126 // memh(gp+#u16:1)=Nt.new
3127 let mayStore = 1, neverHasSideEffects = 1 in
3128 def STrih_GP_nv_V4 : NVInst_V4<(outs),
3129             (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),
3130             "memh(#$global+$offset) = $src.new",
3131             []>,
3132             Requires<[HasV4T]>;
3133
3134 // memh(#global)=Nt.new
3135 let mayStore = 1, neverHasSideEffects = 1 in
3136 def STh_GP_nv_V4 : NVInst_V4<(outs),
3137             (ins globaladdress:$global, IntRegs:$src),
3138             "memh(#$global) = $src.new",
3139             []>,
3140             Requires<[HasV4T]>;
3141
3142
3143 // Store new-value halfword conditionally.
3144
3145 // if ([!]Pv[.new]) memh(#u6)=Nt.new
3146
3147 // if ([!]Pv[.new]) memh(Rs+#u6:1)=Nt.new
3148 // if (Pv) memh(Rs+#u6:1)=Nt.new
3149 let mayStore = 1, neverHasSideEffects = 1,
3150     isPredicated = 1 in
3151 def STrih_cPt_nv_V4 : NVInst_V4<(outs),
3152             (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
3153             "if ($src1) memh($addr) = $src2.new",
3154             []>,
3155             Requires<[HasV4T]>;
3156
3157 // if (Pv.new) memh(Rs+#u6:1)=Nt.new
3158 let mayStore = 1, neverHasSideEffects = 1,
3159     isPredicated = 1 in
3160 def STrih_cdnPt_nv_V4 : NVInst_V4<(outs),
3161             (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
3162             "if ($src1.new) memh($addr) = $src2.new",
3163             []>,
3164             Requires<[HasV4T]>;
3165
3166 // if (!Pv) memh(Rs+#u6:1)=Nt.new
3167 let mayStore = 1, neverHasSideEffects = 1,
3168     isPredicated = 1 in
3169 def STrih_cNotPt_nv_V4 : NVInst_V4<(outs),
3170             (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
3171             "if (!$src1) memh($addr) = $src2.new",
3172             []>,
3173             Requires<[HasV4T]>;
3174
3175 // if (!Pv.new) memh(Rs+#u6:1)=Nt.new
3176 let mayStore = 1, neverHasSideEffects = 1,
3177     isPredicated = 1 in
3178 def STrih_cdnNotPt_nv_V4 : NVInst_V4<(outs),
3179             (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
3180             "if (!$src1.new) memh($addr) = $src2.new",
3181             []>,
3182             Requires<[HasV4T]>;
3183
3184 // if (Pv) memh(Rs+#u6:1)=Nt.new
3185 let mayStore = 1, neverHasSideEffects = 1,
3186     isPredicated = 1 in
3187 def STrih_indexed_cPt_nv_V4 : NVInst_V4<(outs),
3188             (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, IntRegs:$src4),
3189             "if ($src1) memh($src2+#$src3) = $src4.new",
3190             []>,
3191             Requires<[HasV4T]>;
3192
3193 // if (Pv.new) memh(Rs+#u6:1)=Nt.new
3194 let mayStore = 1, neverHasSideEffects = 1,
3195     isPredicated = 1 in
3196 def STrih_indexed_cdnPt_nv_V4 : NVInst_V4<(outs),
3197             (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, IntRegs:$src4),
3198             "if ($src1.new) memh($src2+#$src3) = $src4.new",
3199             []>,
3200             Requires<[HasV4T]>;
3201
3202 // if (!Pv) memh(Rs+#u6:1)=Nt.new
3203 let mayStore = 1, neverHasSideEffects = 1,
3204     isPredicated = 1 in
3205 def STrih_indexed_cNotPt_nv_V4 : NVInst_V4<(outs),
3206             (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, IntRegs:$src4),
3207             "if (!$src1) memh($src2+#$src3) = $src4.new",
3208             []>,
3209             Requires<[HasV4T]>;
3210
3211 // if (!Pv.new) memh(Rs+#u6:1)=Nt.new
3212 let mayStore = 1, neverHasSideEffects = 1,
3213     isPredicated = 1 in
3214 def STrih_indexed_cdnNotPt_nv_V4 : NVInst_V4<(outs),
3215             (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, IntRegs:$src4),
3216             "if (!$src1.new) memh($src2+#$src3) = $src4.new",
3217             []>,
3218             Requires<[HasV4T]>;
3219
3220 // if ([!]Pv[.new]) memh(Rs+Ru<<#u2)=Nt.new
3221 // if (Pv) memh(Rs+Ru<<#u2)=Nt.new
3222 let mayStore = 1, AddedComplexity = 10,
3223     isPredicated = 1 in
3224 def STrih_indexed_shl_cPt_nv_V4 : NVInst_V4<(outs),
3225             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
3226                  IntRegs:$src5),
3227             "if ($src1) memh($src2+$src3<<#$src4) = $src5.new",
3228             []>,
3229             Requires<[HasV4T]>;
3230
3231 // if (Pv.new) memh(Rs+Ru<<#u2)=Nt.new
3232 let mayStore = 1, AddedComplexity = 10,
3233     isPredicated = 1 in
3234 def STrih_indexed_shl_cdnPt_nv_V4 : NVInst_V4<(outs),
3235             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
3236                  IntRegs:$src5),
3237             "if ($src1.new) memh($src2+$src3<<#$src4) = $src5.new",
3238             []>,
3239             Requires<[HasV4T]>;
3240
3241 // if (!Pv) memh(Rs+Ru<<#u2)=Nt.new
3242 let mayStore = 1, AddedComplexity = 10,
3243     isPredicated = 1 in
3244 def STrih_indexed_shl_cNotPt_nv_V4 : NVInst_V4<(outs),
3245             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
3246                  IntRegs:$src5),
3247             "if (!$src1) memh($src2+$src3<<#$src4) = $src5.new",
3248             []>,
3249             Requires<[HasV4T]>;
3250
3251 // if (!Pv.new) memh(Rs+Ru<<#u2)=Nt.new
3252 let mayStore = 1, AddedComplexity = 10,
3253     isPredicated = 1 in
3254 def STrih_indexed_shl_cdnNotPt_nv_V4 : NVInst_V4<(outs),
3255             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
3256                  IntRegs:$src5),
3257             "if (!$src1.new) memh($src2+$src3<<#$src4) = $src5.new",
3258             []>,
3259             Requires<[HasV4T]>;
3260
3261 // if ([!]Pv[]) memh(Rx++#s4:1)=Nt.new
3262 // if (Pv) memh(Rx++#s4:1)=Nt.new
3263 let mayStore = 1, hasCtrlDep = 1,
3264     isPredicated = 1 in
3265 def POST_SThri_cPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
3266             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_1Imm:$offset),
3267             "if ($src1) memh($src3++#$offset) = $src2.new",
3268             [],"$src3 = $dst">,
3269             Requires<[HasV4T]>;
3270
3271 // if (Pv.new) memh(Rx++#s4:1)=Nt.new
3272 let mayStore = 1, hasCtrlDep = 1,
3273     isPredicated = 1 in
3274 def POST_SThri_cdnPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
3275             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_1Imm:$offset),
3276             "if ($src1.new) memh($src3++#$offset) = $src2.new",
3277             [],"$src3 = $dst">,
3278             Requires<[HasV4T]>;
3279
3280 // if (!Pv) memh(Rx++#s4:1)=Nt.new
3281 let mayStore = 1, hasCtrlDep = 1,
3282     isPredicated = 1 in
3283 def POST_SThri_cNotPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
3284             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_1Imm:$offset),
3285             "if (!$src1) memh($src3++#$offset) = $src2.new",
3286             [],"$src3 = $dst">,
3287             Requires<[HasV4T]>;
3288
3289 // if (!Pv.new) memh(Rx++#s4:1)=Nt.new
3290 let mayStore = 1, hasCtrlDep = 1,
3291     isPredicated = 1 in
3292 def POST_SThri_cdnNotPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
3293             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_1Imm:$offset),
3294             "if (!$src1.new) memh($src3++#$offset) = $src2.new",
3295             [],"$src3 = $dst">,
3296             Requires<[HasV4T]>;
3297
3298
3299 // Store new-value word.
3300
3301 // memw(Re=#U6)=Nt.new
3302 // memw(Rs+#s11:2)=Nt.new
3303 let mayStore = 1, isPredicable = 1 in
3304 def STriw_nv_V4 : NVInst_V4<(outs),
3305             (ins MEMri:$addr, IntRegs:$src1),
3306             "memw($addr) = $src1.new",
3307             []>,
3308             Requires<[HasV4T]>;
3309
3310 let mayStore = 1, isPredicable = 1 in
3311 def STriw_indexed_nv_V4 : NVInst_V4<(outs),
3312             (ins IntRegs:$src1, s11_2Imm:$src2, IntRegs:$src3),
3313             "memw($src1+#$src2) = $src3.new",
3314             []>,
3315             Requires<[HasV4T]>;
3316
3317 // memw(Rs+Ru<<#u2)=Nt.new
3318 let mayStore = 1, AddedComplexity = 10, isPredicable = 1 in
3319 def STriw_indexed_shl_nv_V4 : NVInst_V4<(outs),
3320             (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$src3, IntRegs:$src4),
3321             "memw($src1+$src2<<#$src3) = $src4.new",
3322             []>,
3323             Requires<[HasV4T]>;
3324
3325 // memw(Ru<<#u2+#U6)=Nt.new
3326 let mayStore = 1, AddedComplexity = 10 in
3327 def STriw_shl_nv_V4 : NVInst_V4<(outs),
3328             (ins IntRegs:$src1, u2Imm:$src2, u6Imm:$src3, IntRegs:$src4),
3329             "memw($src1<<#$src2+#$src3) = $src4.new",
3330             []>,
3331             Requires<[HasV4T]>;
3332
3333 // memw(Rx++#s4:2)=Nt.new
3334 let mayStore = 1, hasCtrlDep = 1, isPredicable = 1  in
3335 def POST_STwri_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
3336             (ins IntRegs:$src1, IntRegs:$src2, s4_2Imm:$offset),
3337             "memw($src2++#$offset) = $src1.new",
3338             [],
3339             "$src2 = $dst">,
3340             Requires<[HasV4T]>;
3341
3342 // memw(Rx++#s4:2:circ(Mu))=Nt.new
3343 // memw(Rx++I:circ(Mu))=Nt.new
3344 // memw(Rx++Mu)=Nt.new
3345 // memw(Rx++Mu:brev)=Nt.new
3346 // memw(gp+#u16:2)=Nt.new
3347 let mayStore = 1, neverHasSideEffects = 1 in
3348 def STriw_GP_nv_V4 : NVInst_V4<(outs),
3349             (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),
3350             "memw(#$global+$offset) = $src.new",
3351             []>,
3352             Requires<[HasV4T]>;
3353
3354 let mayStore = 1, neverHasSideEffects = 1 in
3355 def STw_GP_nv_V4 : NVInst_V4<(outs),
3356             (ins globaladdress:$global, IntRegs:$src),
3357             "memw(#$global) = $src.new",
3358             []>,
3359             Requires<[HasV4T]>;
3360
3361 // Store new-value word conditionally.
3362
3363 // if ([!]Pv[.new]) memw(#u6)=Nt.new
3364
3365 // if ([!]Pv[.new]) memw(Rs+#u6:2)=Nt.new
3366 // if (Pv) memw(Rs+#u6:2)=Nt.new
3367 let mayStore = 1, neverHasSideEffects = 1,
3368     isPredicated = 1 in
3369 def STriw_cPt_nv_V4 : NVInst_V4<(outs),
3370             (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
3371             "if ($src1) memw($addr) = $src2.new",
3372             []>,
3373             Requires<[HasV4T]>;
3374
3375 // if (Pv.new) memw(Rs+#u6:2)=Nt.new
3376 let mayStore = 1, neverHasSideEffects = 1,
3377     isPredicated = 1 in
3378 def STriw_cdnPt_nv_V4 : NVInst_V4<(outs),
3379             (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
3380             "if ($src1.new) memw($addr) = $src2.new",
3381             []>,
3382             Requires<[HasV4T]>;
3383
3384 // if (!Pv) memw(Rs+#u6:2)=Nt.new
3385 let mayStore = 1, neverHasSideEffects = 1,
3386     isPredicated = 1 in
3387 def STriw_cNotPt_nv_V4 : NVInst_V4<(outs),
3388             (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
3389             "if (!$src1) memw($addr) = $src2.new",
3390             []>,
3391             Requires<[HasV4T]>;
3392
3393 // if (!Pv.new) memw(Rs+#u6:2)=Nt.new
3394 let mayStore = 1, neverHasSideEffects = 1,
3395     isPredicated = 1 in
3396 def STriw_cdnNotPt_nv_V4 : NVInst_V4<(outs),
3397             (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
3398             "if (!$src1.new) memw($addr) = $src2.new",
3399             []>,
3400             Requires<[HasV4T]>;
3401
3402 // if (Pv) memw(Rs+#u6:2)=Nt.new
3403 let mayStore = 1, neverHasSideEffects = 1,
3404     isPredicated = 1 in
3405 def STriw_indexed_cPt_nv_V4 : NVInst_V4<(outs),
3406             (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, IntRegs:$src4),
3407             "if ($src1) memw($src2+#$src3) = $src4.new",
3408             []>,
3409             Requires<[HasV4T]>;
3410
3411 // if (Pv.new) memw(Rs+#u6:2)=Nt.new
3412 let mayStore = 1, neverHasSideEffects = 1,
3413     isPredicated = 1 in
3414 def STriw_indexed_cdnPt_nv_V4 : NVInst_V4<(outs),
3415             (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, IntRegs:$src4),
3416             "if ($src1.new) memw($src2+#$src3) = $src4.new",
3417             []>,
3418             Requires<[HasV4T]>;
3419
3420 // if (!Pv) memw(Rs+#u6:2)=Nt.new
3421 let mayStore = 1, neverHasSideEffects = 1,
3422     isPredicated = 1 in
3423 def STriw_indexed_cNotPt_nv_V4 : NVInst_V4<(outs),
3424             (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, IntRegs:$src4),
3425             "if (!$src1) memw($src2+#$src3) = $src4.new",
3426             []>,
3427             Requires<[HasV4T]>;
3428
3429 // if (!Pv.new) memw(Rs+#u6:2)=Nt.new
3430 let mayStore = 1, neverHasSideEffects = 1,
3431     isPredicated = 1 in
3432 def STriw_indexed_cdnNotPt_nv_V4 : NVInst_V4<(outs),
3433             (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, IntRegs:$src4),
3434             "if (!$src1.new) memw($src2+#$src3) = $src4.new",
3435             []>,
3436             Requires<[HasV4T]>;
3437
3438
3439 // if ([!]Pv[.new]) memw(Rs+Ru<<#u2)=Nt.new
3440 // if (Pv) memw(Rs+Ru<<#u2)=Nt.new
3441 let mayStore = 1, AddedComplexity = 10,
3442     isPredicated = 1 in
3443 def STriw_indexed_shl_cPt_nv_V4 : NVInst_V4<(outs),
3444             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
3445                  IntRegs:$src5),
3446             "if ($src1) memw($src2+$src3<<#$src4) = $src5.new",
3447             []>,
3448             Requires<[HasV4T]>;
3449
3450 // if (Pv.new) memw(Rs+Ru<<#u2)=Nt.new
3451 let mayStore = 1, AddedComplexity = 10,
3452     isPredicated = 1 in
3453 def STriw_indexed_shl_cdnPt_nv_V4 : NVInst_V4<(outs),
3454             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
3455                  IntRegs:$src5),
3456             "if ($src1.new) memw($src2+$src3<<#$src4) = $src5.new",
3457             []>,
3458             Requires<[HasV4T]>;
3459
3460 // if (!Pv) memw(Rs+Ru<<#u2)=Nt.new
3461 let mayStore = 1, AddedComplexity = 10,
3462     isPredicated = 1 in
3463 def STriw_indexed_shl_cNotPt_nv_V4 : NVInst_V4<(outs),
3464             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
3465                  IntRegs:$src5),
3466             "if (!$src1) memw($src2+$src3<<#$src4) = $src5.new",
3467             []>,
3468             Requires<[HasV4T]>;
3469
3470 // if (!Pv.new) memw(Rs+Ru<<#u2)=Nt.new
3471 let mayStore = 1, AddedComplexity = 10,
3472     isPredicated = 1 in
3473 def STriw_indexed_shl_cdnNotPt_nv_V4 : NVInst_V4<(outs),
3474             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
3475                  IntRegs:$src5),
3476             "if (!$src1.new) memw($src2+$src3<<#$src4) = $src5.new",
3477             []>,
3478             Requires<[HasV4T]>;
3479
3480 // if ([!]Pv[.new]) memw(Rx++#s4:2)=Nt.new
3481 // if (Pv) memw(Rx++#s4:2)=Nt.new
3482 let mayStore = 1, hasCtrlDep = 1,
3483     isPredicated = 1 in
3484 def POST_STwri_cPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
3485             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset),
3486             "if ($src1) memw($src3++#$offset) = $src2.new",
3487             [],"$src3 = $dst">,
3488             Requires<[HasV4T]>;
3489
3490 // if (Pv.new) memw(Rx++#s4:2)=Nt.new
3491 let mayStore = 1, hasCtrlDep = 1,
3492     isPredicated = 1 in
3493 def POST_STwri_cdnPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
3494             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset),
3495             "if ($src1.new) memw($src3++#$offset) = $src2.new",
3496             [],"$src3 = $dst">,
3497             Requires<[HasV4T]>;
3498
3499 // if (!Pv) memw(Rx++#s4:2)=Nt.new
3500 let mayStore = 1, hasCtrlDep = 1,
3501     isPredicated = 1 in
3502 def POST_STwri_cNotPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
3503             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset),
3504             "if (!$src1) memw($src3++#$offset) = $src2.new",
3505             [],"$src3 = $dst">,
3506             Requires<[HasV4T]>;
3507
3508 // if (!Pv.new) memw(Rx++#s4:2)=Nt.new
3509 let mayStore = 1, hasCtrlDep = 1,
3510     isPredicated = 1 in
3511 def POST_STwri_cdnNotPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
3512             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset),
3513             "if (!$src1.new) memw($src3++#$offset) = $src2.new",
3514             [],"$src3 = $dst">,
3515             Requires<[HasV4T]>;
3516
3517
3518
3519 // if (Pv) memb(##global) = Rt
3520 let mayStore = 1, neverHasSideEffects = 1 in
3521 def STb_GP_cPt_nv_V4 : NVInst_V4<(outs),
3522             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
3523             "if ($src1) memb(##$global) = $src2.new",
3524             []>,
3525             Requires<[HasV4T]>;
3526
3527 // if (!Pv) memb(##global) = Rt
3528 let mayStore = 1, neverHasSideEffects = 1 in
3529 def STb_GP_cNotPt_nv_V4 : NVInst_V4<(outs),
3530             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
3531             "if (!$src1) memb(##$global) = $src2.new",
3532             []>,
3533             Requires<[HasV4T]>;
3534
3535 // if (Pv) memb(##global) = Rt
3536 let mayStore = 1, neverHasSideEffects = 1 in
3537 def STb_GP_cdnPt_nv_V4 : NVInst_V4<(outs),
3538             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
3539             "if ($src1.new) memb(##$global) = $src2.new",
3540             []>,
3541             Requires<[HasV4T]>;
3542
3543 // if (!Pv) memb(##global) = Rt
3544 let mayStore = 1, neverHasSideEffects = 1 in
3545 def STb_GP_cdnNotPt_nv_V4 : NVInst_V4<(outs),
3546             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
3547             "if (!$src1.new) memb(##$global) = $src2.new",
3548             []>,
3549             Requires<[HasV4T]>;
3550
3551 // if (Pv) memh(##global) = Rt
3552 let mayStore = 1, neverHasSideEffects = 1 in
3553 def STh_GP_cPt_nv_V4 : NVInst_V4<(outs),
3554             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
3555             "if ($src1) memh(##$global) = $src2.new",
3556             []>,
3557             Requires<[HasV4T]>;
3558
3559 // if (!Pv) memh(##global) = Rt
3560 let mayStore = 1, neverHasSideEffects = 1 in
3561 def STh_GP_cNotPt_nv_V4 : NVInst_V4<(outs),
3562             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
3563             "if (!$src1) memh(##$global) = $src2.new",
3564             []>,
3565             Requires<[HasV4T]>;
3566
3567 // if (Pv) memh(##global) = Rt
3568 let mayStore = 1, neverHasSideEffects = 1 in
3569 def STh_GP_cdnPt_nv_V4 : NVInst_V4<(outs),
3570             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
3571             "if ($src1.new) memh(##$global) = $src2.new",
3572             []>,
3573             Requires<[HasV4T]>;
3574
3575 // if (!Pv) memh(##global) = Rt
3576 let mayStore = 1, neverHasSideEffects = 1 in
3577 def STh_GP_cdnNotPt_nv_V4 : NVInst_V4<(outs),
3578             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
3579             "if (!$src1.new) memh(##$global) = $src2.new",
3580             []>,
3581             Requires<[HasV4T]>;
3582
3583 // if (Pv) memw(##global) = Rt
3584 let mayStore = 1, neverHasSideEffects = 1 in
3585 def STw_GP_cPt_nv_V4 : NVInst_V4<(outs),
3586             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
3587             "if ($src1) memw(##$global) = $src2.new",
3588             []>,
3589             Requires<[HasV4T]>;
3590
3591 // if (!Pv) memw(##global) = Rt
3592 let mayStore = 1, neverHasSideEffects = 1 in
3593 def STw_GP_cNotPt_nv_V4 : NVInst_V4<(outs),
3594             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
3595             "if (!$src1) memw(##$global) = $src2.new",
3596             []>,
3597             Requires<[HasV4T]>;
3598
3599 // if (Pv) memw(##global) = Rt
3600 let mayStore = 1, neverHasSideEffects = 1 in
3601 def STw_GP_cdnPt_nv_V4 : NVInst_V4<(outs),
3602             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
3603             "if ($src1.new) memw(##$global) = $src2.new",
3604             []>,
3605             Requires<[HasV4T]>;
3606
3607 // if (!Pv) memw(##global) = Rt
3608 let mayStore = 1, neverHasSideEffects = 1 in
3609 def STw_GP_cdnNotPt_nv_V4 : NVInst_V4<(outs),
3610             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
3611             "if (!$src1.new) memw(##$global) = $src2.new",
3612             []>,
3613             Requires<[HasV4T]>;
3614
3615 let mayStore = 1, neverHasSideEffects = 1 in
3616 def STrib_GP_cPt_nv_V4 : NVInst_V4<(outs),
3617             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
3618                                                         IntRegs:$src2),
3619             "if ($src1) memb(##$global+$offset) = $src2.new",
3620             []>,
3621             Requires<[HasV4T]>;
3622
3623 let mayStore = 1, neverHasSideEffects = 1 in
3624 def STrib_GP_cNotPt_nv_V4 : NVInst_V4<(outs),
3625             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
3626                                                         IntRegs:$src2),
3627             "if (!$src1) memb(##$global+$offset) = $src2.new",
3628             []>,
3629             Requires<[HasV4T]>;
3630
3631 let mayStore = 1, neverHasSideEffects = 1 in
3632 def STrib_GP_cdnPt_nv_V4 : NVInst_V4<(outs),
3633             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
3634                                                         IntRegs:$src2),
3635             "if ($src1.new) memb(##$global+$offset) = $src2.new",
3636             []>,
3637             Requires<[HasV4T]>;
3638
3639 let mayStore = 1, neverHasSideEffects = 1 in
3640 def STrib_GP_cdnNotPt_nv_V4 : NVInst_V4<(outs),
3641             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
3642                                                         IntRegs:$src2),
3643             "if (!$src1.new) memb(##$global+$offset) = $src2.new",
3644             []>,
3645             Requires<[HasV4T]>;
3646
3647 let mayStore = 1, neverHasSideEffects = 1 in
3648 def STrih_GP_cPt_nv_V4 : NVInst_V4<(outs),
3649             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
3650                                                         IntRegs:$src2),
3651             "if ($src1) memh(##$global+$offset) = $src2.new",
3652             []>,
3653             Requires<[HasV4T]>;
3654
3655 let mayStore = 1, neverHasSideEffects = 1 in
3656 def STrih_GP_cNotPt_nv_V4 : NVInst_V4<(outs),
3657             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
3658                                                         IntRegs:$src2),
3659             "if (!$src1) memh(##$global+$offset) = $src2.new",
3660             []>,
3661             Requires<[HasV4T]>;
3662
3663 let mayStore = 1, neverHasSideEffects = 1 in
3664 def STrih_GP_cdnPt_nv_V4 : NVInst_V4<(outs),
3665             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
3666                                                         IntRegs:$src2),
3667             "if ($src1.new) memh(##$global+$offset) = $src2.new",
3668             []>,
3669             Requires<[HasV4T]>;
3670
3671 let mayStore = 1, neverHasSideEffects = 1 in
3672 def STrih_GP_cdnNotPt_nv_V4 : NVInst_V4<(outs),
3673             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
3674                                                         IntRegs:$src2),
3675             "if (!$src1.new) memh(##$global+$offset) = $src2.new",
3676             []>,
3677             Requires<[HasV4T]>;
3678
3679 let mayStore = 1, neverHasSideEffects = 1 in
3680 def STriw_GP_cPt_nv_V4 : NVInst_V4<(outs),
3681             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
3682                                                         IntRegs:$src2),
3683             "if ($src1) memw(##$global+$offset) = $src2.new",
3684             []>,
3685             Requires<[HasV4T]>;
3686
3687 let mayStore = 1, neverHasSideEffects = 1 in
3688 def STriw_GP_cNotPt_nv_V4 : NVInst_V4<(outs),
3689             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
3690                                                         IntRegs:$src2),
3691             "if (!$src1) memw(##$global+$offset) = $src2.new",
3692             []>,
3693             Requires<[HasV4T]>;
3694
3695 let mayStore = 1, neverHasSideEffects = 1 in
3696 def STriw_GP_cdnPt_nv_V4 : NVInst_V4<(outs),
3697             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
3698                                                         IntRegs:$src2),
3699             "if ($src1.new) memw(##$global+$offset) = $src2.new",
3700             []>,
3701             Requires<[HasV4T]>;
3702
3703 let mayStore = 1, neverHasSideEffects = 1 in
3704 def STriw_GP_cdnNotPt_nv_V4 : NVInst_V4<(outs),
3705             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
3706                                                         IntRegs:$src2),
3707             "if (!$src1.new) memw(##$global+$offset) = $src2.new",
3708             []>,
3709             Requires<[HasV4T]>;
3710
3711 //===----------------------------------------------------------------------===//
3712 // NV/ST -
3713 //===----------------------------------------------------------------------===//
3714
3715 //===----------------------------------------------------------------------===//
3716 // NV/J +
3717 //===----------------------------------------------------------------------===//
3718
3719 multiclass NVJ_type_basic_reg<string NotStr, string OpcStr, string TakenStr> {
3720   def _ie_nv_V4 : NVInst_V4<(outs),
3721             (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset),
3722             !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
3723             !strconcat("($src1.new, $src2)) jump:",
3724             !strconcat(TakenStr, " $offset"))))),
3725             []>,
3726             Requires<[HasV4T]>;
3727
3728   def _nv_V4 : NVInst_V4<(outs),
3729             (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset),
3730             !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
3731             !strconcat("($src1.new, $src2)) jump:",
3732             !strconcat(TakenStr, " $offset"))))),
3733             []>,
3734             Requires<[HasV4T]>;
3735 }
3736
3737 multiclass NVJ_type_basic_2ndDotNew<string NotStr, string OpcStr,
3738                                                    string TakenStr> {
3739   def _ie_nv_V4 : NVInst_V4<(outs),
3740             (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset),
3741             !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
3742             !strconcat("($src1, $src2.new)) jump:",
3743             !strconcat(TakenStr, " $offset"))))),
3744             []>,
3745             Requires<[HasV4T]>;
3746
3747   def _nv_V4 : NVInst_V4<(outs),
3748             (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset),
3749             !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
3750             !strconcat("($src1, $src2.new)) jump:",
3751             !strconcat(TakenStr, " $offset"))))),
3752             []>,
3753             Requires<[HasV4T]>;
3754 }
3755
3756 multiclass NVJ_type_basic_imm<string NotStr, string OpcStr, string TakenStr> {
3757   def _ie_nv_V4 : NVInst_V4<(outs),
3758             (ins IntRegs:$src1, u5Imm:$src2, brtarget:$offset),
3759             !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
3760             !strconcat("($src1.new, #$src2)) jump:",
3761             !strconcat(TakenStr, " $offset"))))),
3762             []>,
3763             Requires<[HasV4T]>;
3764
3765   def _nv_V4 : NVInst_V4<(outs),
3766             (ins IntRegs:$src1, u5Imm:$src2, brtarget:$offset),
3767             !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
3768             !strconcat("($src1.new, #$src2)) jump:",
3769             !strconcat(TakenStr, " $offset"))))),
3770             []>,
3771             Requires<[HasV4T]>;
3772 }
3773
3774 multiclass NVJ_type_basic_neg<string NotStr, string OpcStr, string TakenStr> {
3775   def _ie_nv_V4 : NVInst_V4<(outs),
3776             (ins IntRegs:$src1, nOneImm:$src2, brtarget:$offset),
3777             !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
3778             !strconcat("($src1.new, #$src2)) jump:",
3779             !strconcat(TakenStr, " $offset"))))),
3780             []>,
3781             Requires<[HasV4T]>;
3782
3783   def _nv_V4 : NVInst_V4<(outs),
3784             (ins IntRegs:$src1, nOneImm:$src2, brtarget:$offset),
3785             !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
3786             !strconcat("($src1.new, #$src2)) jump:",
3787             !strconcat(TakenStr, " $offset"))))),
3788             []>,
3789             Requires<[HasV4T]>;
3790 }
3791
3792 multiclass NVJ_type_basic_tstbit<string NotStr, string OpcStr,
3793                                                 string TakenStr> {
3794   def _ie_nv_V4 : NVInst_V4<(outs),
3795             (ins IntRegs:$src1, u1Imm:$src2, brtarget:$offset),
3796             !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
3797             !strconcat("($src1.new, #$src2)) jump:",
3798             !strconcat(TakenStr, " $offset"))))),
3799             []>,
3800             Requires<[HasV4T]>;
3801
3802   def _nv_V4 : NVInst_V4<(outs),
3803             (ins IntRegs:$src1, u1Imm:$src2, brtarget:$offset),
3804             !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
3805             !strconcat("($src1.new, #$src2)) jump:",
3806             !strconcat(TakenStr, " $offset"))))),
3807             []>,
3808             Requires<[HasV4T]>;
3809 }
3810
3811 // Multiclass for regular dot new of Ist operand register.
3812 multiclass NVJ_type_br_pred_reg<string NotStr, string OpcStr> {
3813   defm Pt  : NVJ_type_basic_reg<NotStr, OpcStr, "t">;
3814   defm Pnt : NVJ_type_basic_reg<NotStr, OpcStr, "nt">;
3815 }
3816
3817 // Multiclass for dot new of 2nd operand register.
3818 multiclass NVJ_type_br_pred_2ndDotNew<string NotStr, string OpcStr> {
3819   defm Pt  : NVJ_type_basic_2ndDotNew<NotStr, OpcStr, "t">;
3820   defm Pnt : NVJ_type_basic_2ndDotNew<NotStr, OpcStr, "nt">;
3821 }
3822
3823 // Multiclass for 2nd operand immediate, including -1.
3824 multiclass NVJ_type_br_pred_imm<string NotStr, string OpcStr> {
3825   defm Pt     : NVJ_type_basic_imm<NotStr, OpcStr, "t">;
3826   defm Pnt    : NVJ_type_basic_imm<NotStr, OpcStr, "nt">;
3827   defm Ptneg  : NVJ_type_basic_neg<NotStr, OpcStr, "t">;
3828   defm Pntneg : NVJ_type_basic_neg<NotStr, OpcStr, "nt">;
3829 }
3830
3831 // Multiclass for 2nd operand immediate, excluding -1.
3832 multiclass NVJ_type_br_pred_imm_only<string NotStr, string OpcStr> {
3833   defm Pt     : NVJ_type_basic_imm<NotStr, OpcStr, "t">;
3834   defm Pnt    : NVJ_type_basic_imm<NotStr, OpcStr, "nt">;
3835 }
3836
3837 // Multiclass for tstbit, where 2nd operand is always #0.
3838 multiclass NVJ_type_br_pred_tstbit<string NotStr, string OpcStr> {
3839   defm Pt     : NVJ_type_basic_tstbit<NotStr, OpcStr, "t">;
3840   defm Pnt    : NVJ_type_basic_tstbit<NotStr, OpcStr, "nt">;
3841 }
3842
3843 // Multiclass for GT.
3844 multiclass NVJ_type_rr_ri<string OpcStr> {
3845   defm rrNot   : NVJ_type_br_pred_reg<"!", OpcStr>;
3846   defm rr      : NVJ_type_br_pred_reg<"",  OpcStr>;
3847   defm rrdnNot : NVJ_type_br_pred_2ndDotNew<"!", OpcStr>;
3848   defm rrdn    : NVJ_type_br_pred_2ndDotNew<"",  OpcStr>;
3849   defm riNot   : NVJ_type_br_pred_imm<"!", OpcStr>;
3850   defm ri      : NVJ_type_br_pred_imm<"",  OpcStr>;
3851 }
3852
3853 // Multiclass for EQ.
3854 multiclass NVJ_type_rr_ri_no_2ndDotNew<string OpcStr> {
3855   defm rrNot   : NVJ_type_br_pred_reg<"!", OpcStr>;
3856   defm rr      : NVJ_type_br_pred_reg<"",  OpcStr>;
3857   defm riNot   : NVJ_type_br_pred_imm<"!", OpcStr>;
3858   defm ri      : NVJ_type_br_pred_imm<"",  OpcStr>;
3859 }
3860
3861 // Multiclass for GTU.
3862 multiclass NVJ_type_rr_ri_no_nOne<string OpcStr> {
3863   defm rrNot   : NVJ_type_br_pred_reg<"!", OpcStr>;
3864   defm rr      : NVJ_type_br_pred_reg<"",  OpcStr>;
3865   defm rrdnNot : NVJ_type_br_pred_2ndDotNew<"!", OpcStr>;
3866   defm rrdn    : NVJ_type_br_pred_2ndDotNew<"",  OpcStr>;
3867   defm riNot   : NVJ_type_br_pred_imm_only<"!", OpcStr>;
3868   defm ri      : NVJ_type_br_pred_imm_only<"",  OpcStr>;
3869 }
3870
3871 // Multiclass for tstbit.
3872 multiclass NVJ_type_r0<string OpcStr> {
3873   defm r0Not : NVJ_type_br_pred_tstbit<"!", OpcStr>;
3874   defm r0    : NVJ_type_br_pred_tstbit<"",  OpcStr>;
3875  }
3876
3877 // Base Multiclass for New Value Jump.
3878 multiclass NVJ_type {
3879   defm GT     : NVJ_type_rr_ri<"cmp.gt">;
3880   defm EQ     : NVJ_type_rr_ri_no_2ndDotNew<"cmp.eq">;
3881   defm GTU    : NVJ_type_rr_ri_no_nOne<"cmp.gtu">;
3882   defm TSTBIT : NVJ_type_r0<"tstbit">;
3883 }
3884
3885 let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC] in {
3886   defm JMP_ : NVJ_type;
3887 }
3888
3889 //===----------------------------------------------------------------------===//
3890 // NV/J -
3891 //===----------------------------------------------------------------------===//
3892
3893 //===----------------------------------------------------------------------===//
3894 // XTYPE/ALU +
3895 //===----------------------------------------------------------------------===//
3896
3897 //  Add and accumulate.
3898 //  Rd=add(Rs,add(Ru,#s6))
3899 def ADDr_ADDri_V4 : MInst<(outs IntRegs:$dst),
3900           (ins IntRegs:$src1, IntRegs:$src2, s6Imm:$src3),
3901           "$dst = add($src1, add($src2, #$src3))",
3902           [(set (i32 IntRegs:$dst),
3903            (add (i32 IntRegs:$src1), (add (i32 IntRegs:$src2),
3904                                           s6ImmPred:$src3)))]>,
3905           Requires<[HasV4T]>;
3906
3907 //  Rd=add(Rs,sub(#s6,Ru))
3908 def ADDr_SUBri_V4 : MInst<(outs IntRegs:$dst),
3909           (ins IntRegs:$src1, s6Imm:$src2, IntRegs:$src3),
3910           "$dst = add($src1, sub(#$src2, $src3))",
3911           [(set (i32 IntRegs:$dst),
3912            (add (i32 IntRegs:$src1), (sub s6ImmPred:$src2,
3913                                           (i32 IntRegs:$src3))))]>,
3914           Requires<[HasV4T]>;
3915
3916 // Generates the same instruction as ADDr_SUBri_V4 but matches different
3917 // pattern.
3918 //  Rd=add(Rs,sub(#s6,Ru))
3919 def ADDri_SUBr_V4 : MInst<(outs IntRegs:$dst),
3920           (ins IntRegs:$src1, s6Imm:$src2, IntRegs:$src3),
3921           "$dst = add($src1, sub(#$src2, $src3))",
3922           [(set (i32 IntRegs:$dst),
3923                 (sub (add (i32 IntRegs:$src1), s6ImmPred:$src2),
3924                      (i32 IntRegs:$src3)))]>,
3925           Requires<[HasV4T]>;
3926
3927
3928 //  Add or subtract doublewords with carry.
3929 //TODO:
3930 //  Rdd=add(Rss,Rtt,Px):carry
3931 //TODO:
3932 //  Rdd=sub(Rss,Rtt,Px):carry
3933
3934
3935 //  Logical doublewords.
3936 //  Rdd=and(Rtt,~Rss)
3937 def ANDd_NOTd_V4 : MInst<(outs DoubleRegs:$dst),
3938           (ins DoubleRegs:$src1, DoubleRegs:$src2),
3939           "$dst = and($src1, ~$src2)",
3940           [(set (i64 DoubleRegs:$dst), (and (i64 DoubleRegs:$src1),
3941                                       (not (i64 DoubleRegs:$src2))))]>,
3942           Requires<[HasV4T]>;
3943
3944 //  Rdd=or(Rtt,~Rss)
3945 def ORd_NOTd_V4 : MInst<(outs DoubleRegs:$dst),
3946           (ins DoubleRegs:$src1, DoubleRegs:$src2),
3947           "$dst = or($src1, ~$src2)",
3948           [(set (i64 DoubleRegs:$dst),
3949            (or (i64 DoubleRegs:$src1), (not (i64 DoubleRegs:$src2))))]>,
3950           Requires<[HasV4T]>;
3951
3952
3953 //  Logical-logical doublewords.
3954 //  Rxx^=xor(Rss,Rtt)
3955 def XORd_XORdd: MInst_acc<(outs DoubleRegs:$dst),
3956           (ins DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),
3957           "$dst ^= xor($src2, $src3)",
3958           [(set (i64 DoubleRegs:$dst),
3959            (xor (i64 DoubleRegs:$src1), (xor (i64 DoubleRegs:$src2),
3960                                              (i64 DoubleRegs:$src3))))],
3961           "$src1 = $dst">,
3962           Requires<[HasV4T]>;
3963
3964
3965 // Logical-logical words.
3966 // Rx=or(Ru,and(Rx,#s10))
3967 def ORr_ANDri_V4 : MInst_acc<(outs IntRegs:$dst),
3968             (ins IntRegs:$src1, IntRegs: $src2, s10Imm:$src3),
3969             "$dst = or($src1, and($src2, #$src3))",
3970             [(set (i32 IntRegs:$dst),
3971                   (or (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
3972                                                 s10ImmPred:$src3)))],
3973             "$src2 = $dst">,
3974             Requires<[HasV4T]>;
3975
3976 // Rx[&|^]=and(Rs,Rt)
3977 // Rx&=and(Rs,Rt)
3978 def ANDr_ANDrr_V4 : MInst_acc<(outs IntRegs:$dst),
3979             (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
3980             "$dst &= and($src2, $src3)",
3981             [(set (i32 IntRegs:$dst),
3982                   (and (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
3983                                                  (i32 IntRegs:$src3))))],
3984             "$src1 = $dst">,
3985             Requires<[HasV4T]>;
3986
3987 // Rx|=and(Rs,Rt)
3988 def ORr_ANDrr_V4 : MInst_acc<(outs IntRegs:$dst),
3989             (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
3990             "$dst |= and($src2, $src3)",
3991             [(set (i32 IntRegs:$dst),
3992                   (or (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
3993                                                 (i32 IntRegs:$src3))))],
3994             "$src1 = $dst">,
3995             Requires<[HasV4T]>;
3996
3997 // Rx^=and(Rs,Rt)
3998 def XORr_ANDrr_V4 : MInst_acc<(outs IntRegs:$dst),
3999             (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
4000             "$dst ^= and($src2, $src3)",
4001             [(set (i32 IntRegs:$dst),
4002              (xor (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
4003                                             (i32 IntRegs:$src3))))],
4004             "$src1 = $dst">,
4005             Requires<[HasV4T]>;
4006
4007 // Rx[&|^]=and(Rs,~Rt)
4008 // Rx&=and(Rs,~Rt)
4009 def ANDr_ANDr_NOTr_V4 : MInst_acc<(outs IntRegs:$dst),
4010             (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
4011             "$dst &= and($src2, ~$src3)",
4012             [(set (i32 IntRegs:$dst),
4013                   (and (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
4014                                                  (not (i32 IntRegs:$src3)))))],
4015             "$src1 = $dst">,
4016             Requires<[HasV4T]>;
4017
4018 // Rx|=and(Rs,~Rt)
4019 def ORr_ANDr_NOTr_V4 : MInst_acc<(outs IntRegs:$dst),
4020             (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
4021             "$dst |= and($src2, ~$src3)",
4022             [(set (i32 IntRegs:$dst),
4023              (or (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
4024                                            (not (i32 IntRegs:$src3)))))],
4025             "$src1 = $dst">,
4026             Requires<[HasV4T]>;
4027
4028 // Rx^=and(Rs,~Rt)
4029 def XORr_ANDr_NOTr_V4 : MInst_acc<(outs IntRegs:$dst),
4030             (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
4031             "$dst ^= and($src2, ~$src3)",
4032             [(set (i32 IntRegs:$dst),
4033              (xor (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
4034                                             (not (i32 IntRegs:$src3)))))],
4035             "$src1 = $dst">,
4036             Requires<[HasV4T]>;
4037
4038 // Rx[&|^]=or(Rs,Rt)
4039 // Rx&=or(Rs,Rt)
4040 def ANDr_ORrr_V4 : MInst_acc<(outs IntRegs:$dst),
4041             (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
4042             "$dst &= or($src2, $src3)",
4043             [(set (i32 IntRegs:$dst),
4044                   (and (i32 IntRegs:$src1), (or (i32 IntRegs:$src2),
4045                                                 (i32 IntRegs:$src3))))],
4046             "$src1 = $dst">,
4047             Requires<[HasV4T]>;
4048
4049 // Rx|=or(Rs,Rt)
4050 def ORr_ORrr_V4 : MInst_acc<(outs IntRegs:$dst),
4051             (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
4052             "$dst |= or($src2, $src3)",
4053             [(set (i32 IntRegs:$dst),
4054                   (or (i32 IntRegs:$src1), (or (i32 IntRegs:$src2),
4055                                                (i32 IntRegs:$src3))))],
4056             "$src1 = $dst">,
4057             Requires<[HasV4T]>;
4058
4059 // Rx^=or(Rs,Rt)
4060 def XORr_ORrr_V4 : MInst_acc<(outs IntRegs:$dst),
4061             (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
4062             "$dst ^= or($src2, $src3)",
4063             [(set (i32 IntRegs:$dst),
4064              (xor (i32 IntRegs:$src1), (or (i32 IntRegs:$src2),
4065                                            (i32 IntRegs:$src3))))],
4066             "$src1 = $dst">,
4067             Requires<[HasV4T]>;
4068
4069 // Rx[&|^]=xor(Rs,Rt)
4070 // Rx&=xor(Rs,Rt)
4071 def ANDr_XORrr_V4 : MInst_acc<(outs IntRegs:$dst),
4072             (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
4073             "$dst &= xor($src2, $src3)",
4074             [(set (i32 IntRegs:$dst),
4075                   (and (i32 IntRegs:$src1), (xor (i32 IntRegs:$src2),
4076                                                  (i32 IntRegs:$src3))))],
4077             "$src1 = $dst">,
4078             Requires<[HasV4T]>;
4079
4080 // Rx|=xor(Rs,Rt)
4081 def ORr_XORrr_V4 : MInst_acc<(outs IntRegs:$dst),
4082             (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
4083             "$dst |= xor($src2, $src3)",
4084             [(set (i32 IntRegs:$dst),
4085                   (and (i32 IntRegs:$src1), (xor (i32 IntRegs:$src2),
4086                                                  (i32 IntRegs:$src3))))],
4087             "$src1 = $dst">,
4088             Requires<[HasV4T]>;
4089
4090 // Rx^=xor(Rs,Rt)
4091 def XORr_XORrr_V4 : MInst_acc<(outs IntRegs:$dst),
4092             (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
4093             "$dst ^= xor($src2, $src3)",
4094             [(set (i32 IntRegs:$dst),
4095              (and (i32 IntRegs:$src1), (xor (i32 IntRegs:$src2),
4096                                             (i32 IntRegs:$src3))))],
4097             "$src1 = $dst">,
4098             Requires<[HasV4T]>;
4099
4100 // Rx|=and(Rs,#s10)
4101 def ORr_ANDri2_V4 : MInst_acc<(outs IntRegs:$dst),
4102             (ins IntRegs:$src1, IntRegs: $src2, s10Imm:$src3),
4103             "$dst |= and($src2, #$src3)",
4104             [(set (i32 IntRegs:$dst),
4105                   (or (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
4106                                                 s10ImmPred:$src3)))],
4107             "$src1 = $dst">,
4108             Requires<[HasV4T]>;
4109
4110 // Rx|=or(Rs,#s10)
4111 def ORr_ORri_V4 : MInst_acc<(outs IntRegs:$dst),
4112             (ins IntRegs:$src1, IntRegs: $src2, s10Imm:$src3),
4113             "$dst |= or($src2, #$src3)",
4114             [(set (i32 IntRegs:$dst),
4115                   (or (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
4116                                                 s10ImmPred:$src3)))],
4117             "$src1 = $dst">,
4118             Requires<[HasV4T]>;
4119
4120
4121 //    Modulo wrap
4122 //        Rd=modwrap(Rs,Rt)
4123 //    Round
4124 //        Rd=cround(Rs,#u5)
4125 //        Rd=cround(Rs,Rt)
4126 //        Rd=round(Rs,#u5)[:sat]
4127 //        Rd=round(Rs,Rt)[:sat]
4128 //    Vector reduce add unsigned halfwords
4129 //        Rd=vraddh(Rss,Rtt)
4130 //    Vector add bytes
4131 //        Rdd=vaddb(Rss,Rtt)
4132 //    Vector conditional negate
4133 //        Rdd=vcnegh(Rss,Rt)
4134 //        Rxx+=vrcnegh(Rss,Rt)
4135 //    Vector maximum bytes
4136 //        Rdd=vmaxb(Rtt,Rss)
4137 //    Vector reduce maximum halfwords
4138 //        Rxx=vrmaxh(Rss,Ru)
4139 //        Rxx=vrmaxuh(Rss,Ru)
4140 //    Vector reduce maximum words
4141 //        Rxx=vrmaxuw(Rss,Ru)
4142 //        Rxx=vrmaxw(Rss,Ru)
4143 //    Vector minimum bytes
4144 //        Rdd=vminb(Rtt,Rss)
4145 //    Vector reduce minimum halfwords
4146 //        Rxx=vrminh(Rss,Ru)
4147 //        Rxx=vrminuh(Rss,Ru)
4148 //    Vector reduce minimum words
4149 //        Rxx=vrminuw(Rss,Ru)
4150 //        Rxx=vrminw(Rss,Ru)
4151 //    Vector subtract bytes
4152 //        Rdd=vsubb(Rss,Rtt)
4153
4154 //===----------------------------------------------------------------------===//
4155 // XTYPE/ALU -
4156 //===----------------------------------------------------------------------===//
4157
4158
4159 //===----------------------------------------------------------------------===//
4160 // XTYPE/MPY +
4161 //===----------------------------------------------------------------------===//
4162
4163 // Multiply and user lower result.
4164 // Rd=add(#u6,mpyi(Rs,#U6))
4165 def ADDi_MPYri_V4 : MInst<(outs IntRegs:$dst),
4166             (ins u6Imm:$src1, IntRegs:$src2, u6Imm:$src3),
4167             "$dst = add(#$src1, mpyi($src2, #$src3))",
4168             [(set (i32 IntRegs:$dst),
4169                   (add (mul (i32 IntRegs:$src2), u6ImmPred:$src3),
4170                        u6ImmPred:$src1))]>,
4171             Requires<[HasV4T]>;
4172
4173 // Rd=add(#u6,mpyi(Rs,Rt))
4174
4175 def ADDi_MPYrr_V4 : MInst<(outs IntRegs:$dst),
4176             (ins u6Imm:$src1, IntRegs:$src2, IntRegs:$src3),
4177             "$dst = add(#$src1, mpyi($src2, $src3))",
4178             [(set (i32 IntRegs:$dst),
4179                   (add (mul (i32 IntRegs:$src2), (i32 IntRegs:$src3)),
4180                        u6ImmPred:$src1))]>,
4181             Requires<[HasV4T]>;
4182
4183 // Rd=add(Ru,mpyi(#u6:2,Rs))
4184 def ADDr_MPYir_V4 : MInst<(outs IntRegs:$dst),
4185             (ins IntRegs:$src1, u6Imm:$src2, IntRegs:$src3),
4186             "$dst = add($src1, mpyi(#$src2, $src3))",
4187             [(set (i32 IntRegs:$dst),
4188              (add (i32 IntRegs:$src1), (mul (i32 IntRegs:$src3),
4189                                             u6_2ImmPred:$src2)))]>,
4190             Requires<[HasV4T]>;
4191
4192 // Rd=add(Ru,mpyi(Rs,#u6))
4193 def ADDr_MPYri_V4 : MInst<(outs IntRegs:$dst),
4194             (ins IntRegs:$src1, IntRegs:$src2, u6Imm:$src3),
4195             "$dst = add($src1, mpyi($src2, #$src3))",
4196             [(set (i32 IntRegs:$dst),
4197                   (add (i32 IntRegs:$src1), (mul (i32 IntRegs:$src2),
4198                                                  u6ImmPred:$src3)))]>,
4199             Requires<[HasV4T]>;
4200
4201 // Rx=add(Ru,mpyi(Rx,Rs))
4202 def ADDr_MPYrr_V4 : MInst_acc<(outs IntRegs:$dst),
4203             (ins IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
4204             "$dst = add($src1, mpyi($src2, $src3))",
4205             [(set (i32 IntRegs:$dst),
4206              (add (i32 IntRegs:$src1), (mul (i32 IntRegs:$src2),
4207                                             (i32 IntRegs:$src3))))],
4208             "$src2 = $dst">,
4209             Requires<[HasV4T]>;
4210
4211
4212 // Polynomial multiply words
4213 // Rdd=pmpyw(Rs,Rt)
4214 // Rxx^=pmpyw(Rs,Rt)
4215
4216 // Vector reduce multiply word by signed half (32x16)
4217 // Rdd=vrmpyweh(Rss,Rtt)[:<<1]
4218 // Rdd=vrmpywoh(Rss,Rtt)[:<<1]
4219 // Rxx+=vrmpyweh(Rss,Rtt)[:<<1]
4220 // Rxx+=vrmpywoh(Rss,Rtt)[:<<1]
4221
4222 // Multiply and use upper result
4223 // Rd=mpy(Rs,Rt.H):<<1:sat
4224 // Rd=mpy(Rs,Rt.L):<<1:sat
4225 // Rd=mpy(Rs,Rt):<<1
4226 // Rd=mpy(Rs,Rt):<<1:sat
4227 // Rd=mpysu(Rs,Rt)
4228 // Rx+=mpy(Rs,Rt):<<1:sat
4229 // Rx-=mpy(Rs,Rt):<<1:sat
4230
4231 // Vector multiply bytes
4232 // Rdd=vmpybsu(Rs,Rt)
4233 // Rdd=vmpybu(Rs,Rt)
4234 // Rxx+=vmpybsu(Rs,Rt)
4235 // Rxx+=vmpybu(Rs,Rt)
4236
4237 // Vector polynomial multiply halfwords
4238 // Rdd=vpmpyh(Rs,Rt)
4239 // Rxx^=vpmpyh(Rs,Rt)
4240
4241 //===----------------------------------------------------------------------===//
4242 // XTYPE/MPY -
4243 //===----------------------------------------------------------------------===//
4244
4245
4246 //===----------------------------------------------------------------------===//
4247 // XTYPE/SHIFT +
4248 //===----------------------------------------------------------------------===//
4249
4250 // Shift by immediate and accumulate.
4251 // Rx=add(#u8,asl(Rx,#U5))
4252 def ADDi_ASLri_V4 : MInst_acc<(outs IntRegs:$dst),
4253             (ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3),
4254             "$dst = add(#$src1, asl($src2, #$src3))",
4255             [(set (i32 IntRegs:$dst),
4256                   (add (shl (i32 IntRegs:$src2), u5ImmPred:$src3),
4257                        u8ImmPred:$src1))],
4258             "$src2 = $dst">,
4259             Requires<[HasV4T]>;
4260
4261 // Rx=add(#u8,lsr(Rx,#U5))
4262 def ADDi_LSRri_V4 : MInst_acc<(outs IntRegs:$dst),
4263             (ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3),
4264             "$dst = add(#$src1, lsr($src2, #$src3))",
4265             [(set (i32 IntRegs:$dst),
4266                   (add (srl (i32 IntRegs:$src2), u5ImmPred:$src3),
4267                        u8ImmPred:$src1))],
4268             "$src2 = $dst">,
4269             Requires<[HasV4T]>;
4270
4271 // Rx=sub(#u8,asl(Rx,#U5))
4272 def SUBi_ASLri_V4 : MInst_acc<(outs IntRegs:$dst),
4273             (ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3),
4274             "$dst = sub(#$src1, asl($src2, #$src3))",
4275             [(set (i32 IntRegs:$dst),
4276                   (sub (shl (i32 IntRegs:$src2), u5ImmPred:$src3),
4277                        u8ImmPred:$src1))],
4278             "$src2 = $dst">,
4279             Requires<[HasV4T]>;
4280
4281 // Rx=sub(#u8,lsr(Rx,#U5))
4282 def SUBi_LSRri_V4 : MInst_acc<(outs IntRegs:$dst),
4283             (ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3),
4284             "$dst = sub(#$src1, lsr($src2, #$src3))",
4285             [(set (i32 IntRegs:$dst),
4286                   (sub (srl (i32 IntRegs:$src2), u5ImmPred:$src3),
4287                        u8ImmPred:$src1))],
4288             "$src2 = $dst">,
4289             Requires<[HasV4T]>;
4290
4291
4292 //Shift by immediate and logical.
4293 //Rx=and(#u8,asl(Rx,#U5))
4294 def ANDi_ASLri_V4 : MInst_acc<(outs IntRegs:$dst),
4295             (ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3),
4296             "$dst = and(#$src1, asl($src2, #$src3))",
4297             [(set (i32 IntRegs:$dst),
4298                   (and (shl (i32 IntRegs:$src2), u5ImmPred:$src3),
4299                        u8ImmPred:$src1))],
4300             "$src2 = $dst">,
4301             Requires<[HasV4T]>;
4302
4303 //Rx=and(#u8,lsr(Rx,#U5))
4304 def ANDi_LSRri_V4 : MInst_acc<(outs IntRegs:$dst),
4305             (ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3),
4306             "$dst = and(#$src1, lsr($src2, #$src3))",
4307             [(set (i32 IntRegs:$dst),
4308                   (and (srl (i32 IntRegs:$src2), u5ImmPred:$src3),
4309                        u8ImmPred:$src1))],
4310             "$src2 = $dst">,
4311             Requires<[HasV4T]>;
4312
4313 //Rx=or(#u8,asl(Rx,#U5))
4314 let AddedComplexity = 30 in
4315 def ORi_ASLri_V4 : MInst_acc<(outs IntRegs:$dst),
4316             (ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3),
4317             "$dst = or(#$src1, asl($src2, #$src3))",
4318             [(set (i32 IntRegs:$dst),
4319                   (or (shl (i32 IntRegs:$src2), u5ImmPred:$src3),
4320                       u8ImmPred:$src1))],
4321             "$src2 = $dst">,
4322             Requires<[HasV4T]>;
4323
4324 //Rx=or(#u8,lsr(Rx,#U5))
4325 let AddedComplexity = 30 in
4326 def ORi_LSRri_V4 : MInst_acc<(outs IntRegs:$dst),
4327             (ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3),
4328             "$dst = or(#$src1, lsr($src2, #$src3))",
4329             [(set (i32 IntRegs:$dst),
4330                   (or (srl (i32 IntRegs:$src2), u5ImmPred:$src3),
4331                       u8ImmPred:$src1))],
4332             "$src2 = $dst">,
4333             Requires<[HasV4T]>;
4334
4335
4336 //Shift by register.
4337 //Rd=lsl(#s6,Rt)
4338 def LSLi_V4 : MInst<(outs IntRegs:$dst), (ins s6Imm:$src1, IntRegs:$src2),
4339             "$dst = lsl(#$src1, $src2)",
4340             [(set (i32 IntRegs:$dst), (shl s6ImmPred:$src1,
4341                                            (i32 IntRegs:$src2)))]>,
4342             Requires<[HasV4T]>;
4343
4344
4345 //Shift by register and logical.
4346 //Rxx^=asl(Rss,Rt)
4347 def ASLd_rr_xor_V4 : MInst_acc<(outs DoubleRegs:$dst),
4348             (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
4349             "$dst ^= asl($src2, $src3)",
4350             [(set (i64 DoubleRegs:$dst),
4351                   (xor (i64 DoubleRegs:$src1), (shl (i64 DoubleRegs:$src2),
4352                                                     (i32 IntRegs:$src3))))],
4353             "$src1 = $dst">,
4354             Requires<[HasV4T]>;
4355
4356 //Rxx^=asr(Rss,Rt)
4357 def ASRd_rr_xor_V4 : MInst_acc<(outs DoubleRegs:$dst),
4358             (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
4359             "$dst ^= asr($src2, $src3)",
4360             [(set (i64 DoubleRegs:$dst),
4361                   (xor (i64 DoubleRegs:$src1), (sra (i64 DoubleRegs:$src2),
4362                                                     (i32 IntRegs:$src3))))],
4363             "$src1 = $dst">,
4364             Requires<[HasV4T]>;
4365
4366 //Rxx^=lsl(Rss,Rt)
4367 def LSLd_rr_xor_V4 : MInst_acc<(outs DoubleRegs:$dst),
4368             (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
4369             "$dst ^= lsl($src2, $src3)",
4370             [(set (i64 DoubleRegs:$dst), (xor (i64 DoubleRegs:$src1),
4371                                               (shl (i64 DoubleRegs:$src2),
4372                                                    (i32 IntRegs:$src3))))],
4373             "$src1 = $dst">,
4374             Requires<[HasV4T]>;
4375
4376 //Rxx^=lsr(Rss,Rt)
4377 def LSRd_rr_xor_V4 : MInst_acc<(outs DoubleRegs:$dst),
4378             (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
4379             "$dst ^= lsr($src2, $src3)",
4380             [(set (i64 DoubleRegs:$dst),
4381                   (xor (i64 DoubleRegs:$src1), (srl (i64 DoubleRegs:$src2),
4382                                                     (i32 IntRegs:$src3))))],
4383             "$src1 = $dst">,
4384             Requires<[HasV4T]>;
4385
4386
4387 //===----------------------------------------------------------------------===//
4388 // XTYPE/SHIFT -
4389 //===----------------------------------------------------------------------===//
4390
4391 //===----------------------------------------------------------------------===//
4392 // MEMOP: Word, Half, Byte
4393 //===----------------------------------------------------------------------===//
4394
4395 //===----------------------------------------------------------------------===//
4396 // MEMOP: Word
4397 //
4398 //  Implemented:
4399 //     MEMw_ADDi_indexed_V4  : memw(Rs+#u6:2)+=#U5
4400 //     MEMw_SUBi_indexed_V4  : memw(Rs+#u6:2)-=#U5
4401 //     MEMw_ADDr_indexed_V4  : memw(Rs+#u6:2)+=Rt
4402 //     MEMw_SUBr_indexed_V4  : memw(Rs+#u6:2)-=Rt
4403 //     MEMw_CLRr_indexed_V4  : memw(Rs+#u6:2)&=Rt
4404 //     MEMw_SETr_indexed_V4  : memw(Rs+#u6:2)|=Rt
4405 //     MEMw_ADDi_V4          : memw(Rs+#u6:2)+=#U5
4406 //     MEMw_SUBi_V4          : memw(Rs+#u6:2)-=#U5
4407 //     MEMw_ADDr_V4          : memw(Rs+#u6:2)+=Rt
4408 //     MEMw_SUBr_V4          : memw(Rs+#u6:2)-=Rt
4409 //     MEMw_CLRr_V4          : memw(Rs+#u6:2)&=Rt
4410 //     MEMw_SETr_V4          : memw(Rs+#u6:2)|=Rt
4411 //
4412 //   Not implemented:
4413 //     MEMw_CLRi_indexed_V4  : memw(Rs+#u6:2)=clrbit(#U5)
4414 //     MEMw_SETi_indexed_V4  : memw(Rs+#u6:2)=setbit(#U5)
4415 //     MEMw_CLRi_V4          : memw(Rs+#u6:2)=clrbit(#U5)
4416 //     MEMw_SETi_V4          : memw(Rs+#u6:2)=setbit(#U5)
4417 //===----------------------------------------------------------------------===//
4418
4419
4420
4421 // memw(Rs+#u6:2) += #U5
4422 let AddedComplexity = 30 in
4423 def MEMw_ADDi_indexed_MEM_V4 : MEMInst_V4<(outs),
4424             (ins IntRegs:$base, u6_2Imm:$offset, u5Imm:$addend),
4425             "memw($base+#$offset) += #$addend",
4426             []>,
4427             Requires<[HasV4T, UseMEMOP]>;
4428
4429 // memw(Rs+#u6:2) -= #U5
4430 let AddedComplexity = 30 in
4431 def MEMw_SUBi_indexed_MEM_V4 : MEMInst_V4<(outs),
4432             (ins IntRegs:$base, u6_2Imm:$offset, u5Imm:$subend),
4433             "memw($base+#$offset) -= #$subend",
4434             []>,
4435             Requires<[HasV4T, UseMEMOP]>;
4436
4437 // memw(Rs+#u6:2) += Rt
4438 let AddedComplexity = 30 in
4439 def MEMw_ADDr_indexed_MEM_V4 : MEMInst_V4<(outs),
4440             (ins IntRegs:$base, u6_2Imm:$offset, IntRegs:$addend),
4441             "memw($base+#$offset) += $addend",
4442             [(store (add (load (add (i32 IntRegs:$base), u6_2ImmPred:$offset)),
4443                          (i32 IntRegs:$addend)),
4444                     (add (i32 IntRegs:$base), u6_2ImmPred:$offset))]>,
4445             Requires<[HasV4T, UseMEMOP]>;
4446
4447 // memw(Rs+#u6:2) -= Rt
4448 let AddedComplexity = 30 in
4449 def MEMw_SUBr_indexed_MEM_V4 : MEMInst_V4<(outs),
4450             (ins IntRegs:$base, u6_2Imm:$offset, IntRegs:$subend),
4451             "memw($base+#$offset) -= $subend",
4452             [(store (sub (load (add (i32 IntRegs:$base), u6_2ImmPred:$offset)),
4453                          (i32 IntRegs:$subend)),
4454                     (add (i32 IntRegs:$base), u6_2ImmPred:$offset))]>,
4455             Requires<[HasV4T, UseMEMOP]>;
4456
4457 // memw(Rs+#u6:2) &= Rt
4458 let AddedComplexity = 30 in
4459 def MEMw_ANDr_indexed_MEM_V4 : MEMInst_V4<(outs),
4460             (ins IntRegs:$base, u6_2Imm:$offset, IntRegs:$andend),
4461             "memw($base+#$offset) &= $andend",
4462             [(store (and (load (add (i32 IntRegs:$base), u6_2ImmPred:$offset)),
4463                          (i32 IntRegs:$andend)),
4464                     (add (i32 IntRegs:$base), u6_2ImmPred:$offset))]>,
4465             Requires<[HasV4T, UseMEMOP]>;
4466
4467 // memw(Rs+#u6:2) |= Rt
4468 let AddedComplexity = 30 in
4469 def MEMw_ORr_indexed_MEM_V4 : MEMInst_V4<(outs),
4470             (ins IntRegs:$base, u6_2Imm:$offset, IntRegs:$orend),
4471             "memw($base+#$offset) |= $orend",
4472             [(store (or (load (add (i32 IntRegs:$base), u6_2ImmPred:$offset)),
4473                         (i32 IntRegs:$orend)),
4474                     (add (i32 IntRegs:$base), u6_2ImmPred:$offset))]>,
4475             Requires<[HasV4T, UseMEMOP]>;
4476
4477 // memw(Rs+#u6:2) += #U5
4478 let AddedComplexity = 30 in
4479 def MEMw_ADDi_MEM_V4 : MEMInst_V4<(outs),
4480             (ins MEMri:$addr, u5Imm:$addend),
4481             "memw($addr) += $addend",
4482             []>,
4483             Requires<[HasV4T, UseMEMOP]>;
4484
4485 // memw(Rs+#u6:2) -= #U5
4486 let AddedComplexity = 30 in
4487 def MEMw_SUBi_MEM_V4 : MEMInst_V4<(outs),
4488             (ins MEMri:$addr, u5Imm:$subend),
4489             "memw($addr) -= $subend",
4490             []>,
4491             Requires<[HasV4T, UseMEMOP]>;
4492
4493 // memw(Rs+#u6:2) += Rt
4494 let AddedComplexity = 30 in
4495 def MEMw_ADDr_MEM_V4 : MEMInst_V4<(outs),
4496             (ins MEMri:$addr, IntRegs:$addend),
4497             "memw($addr) += $addend",
4498             [(store (add (load ADDRriU6_2:$addr), (i32 IntRegs:$addend)),
4499                     ADDRriU6_2:$addr)]>,
4500             Requires<[HasV4T, UseMEMOP]>;
4501
4502 // memw(Rs+#u6:2) -= Rt
4503 let AddedComplexity = 30 in
4504 def MEMw_SUBr_MEM_V4 : MEMInst_V4<(outs),
4505             (ins MEMri:$addr, IntRegs:$subend),
4506             "memw($addr) -= $subend",
4507             [(store (sub (load ADDRriU6_2:$addr), (i32 IntRegs:$subend)),
4508                     ADDRriU6_2:$addr)]>,
4509             Requires<[HasV4T, UseMEMOP]>;
4510
4511 // memw(Rs+#u6:2) &= Rt
4512 let AddedComplexity = 30 in
4513 def MEMw_ANDr_MEM_V4 : MEMInst_V4<(outs),
4514             (ins MEMri:$addr, IntRegs:$andend),
4515             "memw($addr) &= $andend",
4516             [(store (and (load ADDRriU6_2:$addr), (i32 IntRegs:$andend)),
4517                     ADDRriU6_2:$addr)]>,
4518             Requires<[HasV4T, UseMEMOP]>;
4519
4520 // memw(Rs+#u6:2) |= Rt
4521 let AddedComplexity = 30 in
4522 def MEMw_ORr_MEM_V4 : MEMInst_V4<(outs),
4523             (ins MEMri:$addr, IntRegs:$orend),
4524             "memw($addr) |= $orend",
4525             [(store (or (load ADDRriU6_2:$addr), (i32 IntRegs:$orend)),
4526                     ADDRriU6_2:$addr)]>,
4527             Requires<[HasV4T, UseMEMOP]>;
4528
4529 //===----------------------------------------------------------------------===//
4530 // MEMOP: Halfword
4531 //
4532 //  Implemented:
4533 //     MEMh_ADDi_indexed_V4  : memw(Rs+#u6:2)+=#U5
4534 //     MEMh_SUBi_indexed_V4  : memw(Rs+#u6:2)-=#U5
4535 //     MEMh_ADDr_indexed_V4  : memw(Rs+#u6:2)+=Rt
4536 //     MEMh_SUBr_indexed_V4  : memw(Rs+#u6:2)-=Rt
4537 //     MEMh_CLRr_indexed_V4  : memw(Rs+#u6:2)&=Rt
4538 //     MEMh_SETr_indexed_V4  : memw(Rs+#u6:2)|=Rt
4539 //     MEMh_ADDi_V4          : memw(Rs+#u6:2)+=#U5
4540 //     MEMh_SUBi_V4          : memw(Rs+#u6:2)-=#U5
4541 //     MEMh_ADDr_V4          : memw(Rs+#u6:2)+=Rt
4542 //     MEMh_SUBr_V4          : memw(Rs+#u6:2)-=Rt
4543 //     MEMh_CLRr_V4          : memw(Rs+#u6:2)&=Rt
4544 //     MEMh_SETr_V4          : memw(Rs+#u6:2)|=Rt
4545 //
4546 //   Not implemented:
4547 //     MEMh_CLRi_indexed_V4  : memw(Rs+#u6:2)=clrbit(#U5)
4548 //     MEMh_SETi_indexed_V4  : memw(Rs+#u6:2)=setbit(#U5)
4549 //     MEMh_CLRi_V4          : memw(Rs+#u6:2)=clrbit(#U5)
4550 //     MEMh_SETi_V4          : memw(Rs+#u6:2)=setbit(#U5)
4551 //===----------------------------------------------------------------------===//
4552
4553
4554 // memh(Rs+#u6:1) += #U5
4555 let AddedComplexity = 30 in
4556 def MEMh_ADDi_indexed_MEM_V4 : MEMInst_V4<(outs),
4557             (ins IntRegs:$base, u6_1Imm:$offset, u5Imm:$addend),
4558             "memh($base+#$offset) += $addend",
4559             []>,
4560             Requires<[HasV4T, UseMEMOP]>;
4561
4562 // memh(Rs+#u6:1) -= #U5
4563 let AddedComplexity = 30 in
4564 def MEMh_SUBi_indexed_MEM_V4 : MEMInst_V4<(outs),
4565             (ins IntRegs:$base, u6_1Imm:$offset, u5Imm:$subend),
4566             "memh($base+#$offset) -= $subend",
4567             []>,
4568             Requires<[HasV4T, UseMEMOP]>;
4569
4570 // memh(Rs+#u6:1) += Rt
4571 let AddedComplexity = 30 in
4572 def MEMh_ADDr_indexed_MEM_V4 : MEMInst_V4<(outs),
4573             (ins IntRegs:$base, u6_1Imm:$offset, IntRegs:$addend),
4574             "memh($base+#$offset) += $addend",
4575             [(truncstorei16 (add (sextloadi16 (add (i32 IntRegs:$base),
4576                                                    u6_1ImmPred:$offset)),
4577                                  (i32 IntRegs:$addend)),
4578                             (add (i32 IntRegs:$base), u6_1ImmPred:$offset))]>,
4579             Requires<[HasV4T, UseMEMOP]>;
4580
4581 // memh(Rs+#u6:1) -= Rt
4582 let AddedComplexity = 30 in
4583 def MEMh_SUBr_indexed_MEM_V4 : MEMInst_V4<(outs),
4584             (ins IntRegs:$base, u6_1Imm:$offset, IntRegs:$subend),
4585             "memh($base+#$offset) -= $subend",
4586             [(truncstorei16 (sub (sextloadi16 (add (i32 IntRegs:$base),
4587                                                    u6_1ImmPred:$offset)),
4588                                  (i32 IntRegs:$subend)),
4589                             (add (i32 IntRegs:$base), u6_1ImmPred:$offset))]>,
4590             Requires<[HasV4T, UseMEMOP]>;
4591
4592 // memh(Rs+#u6:1) &= Rt
4593 let AddedComplexity = 30 in
4594 def MEMh_ANDr_indexed_MEM_V4 : MEMInst_V4<(outs),
4595             (ins IntRegs:$base, u6_1Imm:$offset, IntRegs:$andend),
4596             "memh($base+#$offset) += $andend",
4597             [(truncstorei16 (and (sextloadi16 (add (i32 IntRegs:$base),
4598                                                    u6_1ImmPred:$offset)),
4599                                  (i32 IntRegs:$andend)),
4600                             (add (i32 IntRegs:$base), u6_1ImmPred:$offset))]>,
4601             Requires<[HasV4T, UseMEMOP]>;
4602
4603 // memh(Rs+#u6:1) |= Rt
4604 let AddedComplexity = 30 in
4605 def MEMh_ORr_indexed_MEM_V4 : MEMInst_V4<(outs),
4606             (ins IntRegs:$base, u6_1Imm:$offset, IntRegs:$orend),
4607             "memh($base+#$offset) |= $orend",
4608             [(truncstorei16 (or (sextloadi16 (add (i32 IntRegs:$base),
4609                                               u6_1ImmPred:$offset)),
4610                              (i32 IntRegs:$orend)),
4611                             (add (i32 IntRegs:$base), u6_1ImmPred:$offset))]>,
4612             Requires<[HasV4T, UseMEMOP]>;
4613
4614 // memh(Rs+#u6:1) += #U5
4615 let AddedComplexity = 30 in
4616 def MEMh_ADDi_MEM_V4 : MEMInst_V4<(outs),
4617             (ins MEMri:$addr, u5Imm:$addend),
4618             "memh($addr) += $addend",
4619             []>,
4620             Requires<[HasV4T, UseMEMOP]>;
4621
4622 // memh(Rs+#u6:1) -= #U5
4623 let AddedComplexity = 30 in
4624 def MEMh_SUBi_MEM_V4 : MEMInst_V4<(outs),
4625             (ins MEMri:$addr, u5Imm:$subend),
4626             "memh($addr) -= $subend",
4627             []>,
4628             Requires<[HasV4T, UseMEMOP]>;
4629
4630 // memh(Rs+#u6:1) += Rt
4631 let AddedComplexity = 30 in
4632 def MEMh_ADDr_MEM_V4 : MEMInst_V4<(outs),
4633             (ins MEMri:$addr, IntRegs:$addend),
4634             "memh($addr) += $addend",
4635             [(truncstorei16 (add (sextloadi16 ADDRriU6_1:$addr),
4636                                  (i32 IntRegs:$addend)), ADDRriU6_1:$addr)]>,
4637             Requires<[HasV4T, UseMEMOP]>;
4638
4639 // memh(Rs+#u6:1) -= Rt
4640 let AddedComplexity = 30 in
4641 def MEMh_SUBr_MEM_V4 : MEMInst_V4<(outs),
4642             (ins MEMri:$addr, IntRegs:$subend),
4643             "memh($addr) -= $subend",
4644             [(truncstorei16 (sub (sextloadi16 ADDRriU6_1:$addr),
4645                                  (i32 IntRegs:$subend)), ADDRriU6_1:$addr)]>,
4646             Requires<[HasV4T, UseMEMOP]>;
4647
4648 // memh(Rs+#u6:1) &= Rt
4649 let AddedComplexity = 30 in
4650 def MEMh_ANDr_MEM_V4 : MEMInst_V4<(outs),
4651             (ins MEMri:$addr, IntRegs:$andend),
4652             "memh($addr) &= $andend",
4653             [(truncstorei16 (and (sextloadi16 ADDRriU6_1:$addr),
4654                                  (i32 IntRegs:$andend)), ADDRriU6_1:$addr)]>,
4655             Requires<[HasV4T, UseMEMOP]>;
4656
4657 // memh(Rs+#u6:1) |= Rt
4658 let AddedComplexity = 30 in
4659 def MEMh_ORr_MEM_V4 : MEMInst_V4<(outs),
4660             (ins MEMri:$addr, IntRegs:$orend),
4661             "memh($addr) |= $orend",
4662             [(truncstorei16 (or (sextloadi16 ADDRriU6_1:$addr),
4663                                 (i32 IntRegs:$orend)), ADDRriU6_1:$addr)]>,
4664             Requires<[HasV4T, UseMEMOP]>;
4665
4666
4667 //===----------------------------------------------------------------------===//
4668 // MEMOP: Byte
4669 //
4670 //  Implemented:
4671 //     MEMb_ADDi_indexed_V4  : memb(Rs+#u6:0)+=#U5
4672 //     MEMb_SUBi_indexed_V4  : memb(Rs+#u6:0)-=#U5
4673 //     MEMb_ADDr_indexed_V4  : memb(Rs+#u6:0)+=Rt
4674 //     MEMb_SUBr_indexed_V4  : memb(Rs+#u6:0)-=Rt
4675 //     MEMb_CLRr_indexed_V4  : memb(Rs+#u6:0)&=Rt
4676 //     MEMb_SETr_indexed_V4  : memb(Rs+#u6:0)|=Rt
4677 //     MEMb_ADDi_V4          : memb(Rs+#u6:0)+=#U5
4678 //     MEMb_SUBi_V4          : memb(Rs+#u6:0)-=#U5
4679 //     MEMb_ADDr_V4          : memb(Rs+#u6:0)+=Rt
4680 //     MEMb_SUBr_V4          : memb(Rs+#u6:0)-=Rt
4681 //     MEMb_CLRr_V4          : memb(Rs+#u6:0)&=Rt
4682 //     MEMb_SETr_V4          : memb(Rs+#u6:0)|=Rt
4683 //
4684 //   Not implemented:
4685 //     MEMb_CLRi_indexed_V4  : memb(Rs+#u6:0)=clrbit(#U5)
4686 //     MEMb_SETi_indexed_V4  : memb(Rs+#u6:0)=setbit(#U5)
4687 //     MEMb_CLRi_V4          : memb(Rs+#u6:0)=clrbit(#U5)
4688 //     MEMb_SETi_V4          : memb(Rs+#u6:0)=setbit(#U5)
4689 //===----------------------------------------------------------------------===//
4690
4691 // memb(Rs+#u6:0) += #U5
4692 let AddedComplexity = 30 in
4693 def MEMb_ADDi_indexed_MEM_V4 : MEMInst_V4<(outs),
4694             (ins IntRegs:$base, u6_0Imm:$offset, u5Imm:$addend),
4695             "memb($base+#$offset) += $addend",
4696             []>,
4697             Requires<[HasV4T, UseMEMOP]>;
4698
4699 // memb(Rs+#u6:0) -= #U5
4700 let AddedComplexity = 30 in
4701 def MEMb_SUBi_indexed_MEM_V4 : MEMInst_V4<(outs),
4702             (ins IntRegs:$base, u6_0Imm:$offset, u5Imm:$subend),
4703             "memb($base+#$offset) -= $subend",
4704             []>,
4705             Requires<[HasV4T, UseMEMOP]>;
4706
4707 // memb(Rs+#u6:0) += Rt
4708 let AddedComplexity = 30 in
4709 def MEMb_ADDr_indexed_MEM_V4 : MEMInst_V4<(outs),
4710             (ins IntRegs:$base, u6_0Imm:$offset, IntRegs:$addend),
4711             "memb($base+#$offset) += $addend",
4712             [(truncstorei8 (add (sextloadi8 (add (i32 IntRegs:$base),
4713                                                  u6_0ImmPred:$offset)),
4714                                 (i32 IntRegs:$addend)),
4715                            (add (i32 IntRegs:$base), u6_0ImmPred:$offset))]>,
4716             Requires<[HasV4T, UseMEMOP]>;
4717
4718 // memb(Rs+#u6:0) -= Rt
4719 let AddedComplexity = 30 in
4720 def MEMb_SUBr_indexed_MEM_V4 : MEMInst_V4<(outs),
4721             (ins IntRegs:$base, u6_0Imm:$offset, IntRegs:$subend),
4722             "memb($base+#$offset) -= $subend",
4723             [(truncstorei8 (sub (sextloadi8 (add (i32 IntRegs:$base),
4724                                                  u6_0ImmPred:$offset)),
4725                                 (i32 IntRegs:$subend)),
4726                            (add (i32 IntRegs:$base), u6_0ImmPred:$offset))]>,
4727             Requires<[HasV4T, UseMEMOP]>;
4728
4729 // memb(Rs+#u6:0) &= Rt
4730 let AddedComplexity = 30 in
4731 def MEMb_ANDr_indexed_MEM_V4 : MEMInst_V4<(outs),
4732             (ins IntRegs:$base, u6_0Imm:$offset, IntRegs:$andend),
4733             "memb($base+#$offset) += $andend",
4734             [(truncstorei8 (and (sextloadi8 (add (i32 IntRegs:$base),
4735                                                  u6_0ImmPred:$offset)),
4736                                 (i32 IntRegs:$andend)),
4737                            (add (i32 IntRegs:$base), u6_0ImmPred:$offset))]>,
4738             Requires<[HasV4T, UseMEMOP]>;
4739
4740 // memb(Rs+#u6:0) |= Rt
4741 let AddedComplexity = 30 in
4742 def MEMb_ORr_indexed_MEM_V4 : MEMInst_V4<(outs),
4743             (ins IntRegs:$base, u6_0Imm:$offset, IntRegs:$orend),
4744             "memb($base+#$offset) |= $orend",
4745             [(truncstorei8 (or (sextloadi8 (add (i32 IntRegs:$base),
4746                                                 u6_0ImmPred:$offset)),
4747                                (i32 IntRegs:$orend)),
4748                            (add (i32 IntRegs:$base), u6_0ImmPred:$offset))]>,
4749             Requires<[HasV4T, UseMEMOP]>;
4750
4751 // memb(Rs+#u6:0) += #U5
4752 let AddedComplexity = 30 in
4753 def MEMb_ADDi_MEM_V4 : MEMInst_V4<(outs),
4754             (ins MEMri:$addr, u5Imm:$addend),
4755             "memb($addr) += $addend",
4756             []>,
4757             Requires<[HasV4T, UseMEMOP]>;
4758
4759 // memb(Rs+#u6:0) -= #U5
4760 let AddedComplexity = 30 in
4761 def MEMb_SUBi_MEM_V4 : MEMInst_V4<(outs),
4762             (ins MEMri:$addr, u5Imm:$subend),
4763             "memb($addr) -= $subend",
4764             []>,
4765             Requires<[HasV4T, UseMEMOP]>;
4766
4767 // memb(Rs+#u6:0) += Rt
4768 let AddedComplexity = 30 in
4769 def MEMb_ADDr_MEM_V4 : MEMInst_V4<(outs),
4770             (ins MEMri:$addr, IntRegs:$addend),
4771             "memb($addr) += $addend",
4772             [(truncstorei8 (add (sextloadi8 ADDRriU6_0:$addr),
4773                                 (i32 IntRegs:$addend)), ADDRriU6_0:$addr)]>,
4774             Requires<[HasV4T, UseMEMOP]>;
4775
4776 // memb(Rs+#u6:0) -= Rt
4777 let AddedComplexity = 30 in
4778 def MEMb_SUBr_MEM_V4 : MEMInst_V4<(outs),
4779             (ins MEMri:$addr, IntRegs:$subend),
4780             "memb($addr) -= $subend",
4781             [(truncstorei8 (sub (sextloadi8 ADDRriU6_0:$addr),
4782                                 (i32 IntRegs:$subend)), ADDRriU6_0:$addr)]>,
4783             Requires<[HasV4T, UseMEMOP]>;
4784
4785 // memb(Rs+#u6:0) &= Rt
4786 let AddedComplexity = 30 in
4787 def MEMb_ANDr_MEM_V4 : MEMInst_V4<(outs),
4788             (ins MEMri:$addr, IntRegs:$andend),
4789             "memb($addr) &= $andend",
4790             [(truncstorei8 (and (sextloadi8 ADDRriU6_0:$addr),
4791                                 (i32 IntRegs:$andend)), ADDRriU6_0:$addr)]>,
4792             Requires<[HasV4T, UseMEMOP]>;
4793
4794 // memb(Rs+#u6:0) |= Rt
4795 let AddedComplexity = 30 in
4796 def MEMb_ORr_MEM_V4 : MEMInst_V4<(outs),
4797             (ins MEMri:$addr, IntRegs:$orend),
4798             "memb($addr) |= $orend",
4799             [(truncstorei8 (or (sextloadi8 ADDRriU6_0:$addr),
4800                                (i32 IntRegs:$orend)), ADDRriU6_0:$addr)]>,
4801             Requires<[HasV4T, UseMEMOP]>;
4802
4803
4804 //===----------------------------------------------------------------------===//
4805 // XTYPE/PRED +
4806 //===----------------------------------------------------------------------===//
4807
4808 // Hexagon V4 only supports these flavors of byte/half compare instructions:
4809 // EQ/GT/GTU. Other flavors like GE/GEU/LT/LTU/LE/LEU are not supported by
4810 // hardware. However, compiler can still implement these patterns through
4811 // appropriate patterns combinations based on current implemented patterns.
4812 // The implemented patterns are: EQ/GT/GTU.
4813 // Missing patterns are: GE/GEU/LT/LTU/LE/LEU.
4814
4815 // Following instruction is not being extended as it results into the
4816 // incorrect code for negative numbers.
4817 // Pd=cmpb.eq(Rs,#u8)
4818
4819 let isCompare = 1 in
4820 def CMPbEQri_V4 : MInst<(outs PredRegs:$dst),
4821             (ins IntRegs:$src1, u8Imm:$src2),
4822             "$dst = cmpb.eq($src1, #$src2)",
4823             [(set (i1 PredRegs:$dst),
4824                   (seteq (and (i32 IntRegs:$src1), 255), u8ImmPred:$src2))]>,
4825             Requires<[HasV4T]>;
4826
4827 // Pd=cmpb.eq(Rs,Rt)
4828 let isCompare = 1 in
4829 def CMPbEQrr_ubub_V4 : MInst<(outs PredRegs:$dst),
4830             (ins IntRegs:$src1, IntRegs:$src2),
4831             "$dst = cmpb.eq($src1, $src2)",
4832             [(set (i1 PredRegs:$dst),
4833                   (seteq (and (xor (i32 IntRegs:$src1),
4834                                    (i32 IntRegs:$src2)), 255), 0))]>,
4835             Requires<[HasV4T]>;
4836
4837 // Pd=cmpb.eq(Rs,Rt)
4838 let isCompare = 1 in
4839 def CMPbEQrr_sbsb_V4 : MInst<(outs PredRegs:$dst),
4840             (ins IntRegs:$src1, IntRegs:$src2),
4841             "$dst = cmpb.eq($src1, $src2)",
4842             [(set (i1 PredRegs:$dst),
4843                   (seteq (shl (i32 IntRegs:$src1), (i32 24)),
4844                          (shl (i32 IntRegs:$src2), (i32 24))))]>,
4845             Requires<[HasV4T]>;
4846
4847 // Pd=cmpb.gt(Rs,Rt)
4848 let isCompare = 1 in
4849 def CMPbGTrr_V4 : MInst<(outs PredRegs:$dst),
4850             (ins IntRegs:$src1, IntRegs:$src2),
4851             "$dst = cmpb.gt($src1, $src2)",
4852             [(set (i1 PredRegs:$dst),
4853                   (setgt (shl (i32 IntRegs:$src1), (i32 24)),
4854                          (shl (i32 IntRegs:$src2), (i32 24))))]>,
4855             Requires<[HasV4T]>;
4856
4857 // Pd=cmpb.gtu(Rs,#u7)
4858 let isCompare = 1 in
4859 def CMPbGTUri_V4 : MInst<(outs PredRegs:$dst),
4860             (ins IntRegs:$src1, u7Imm:$src2),
4861             "$dst = cmpb.gtu($src1, #$src2)",
4862             [(set (i1 PredRegs:$dst), (setugt (and (i32 IntRegs:$src1), 255),
4863                                               u7ImmPred:$src2))]>,
4864             Requires<[HasV4T]>;
4865
4866 // Pd=cmpb.gtu(Rs,Rt)
4867 let isCompare = 1 in
4868 def CMPbGTUrr_V4 : MInst<(outs PredRegs:$dst),
4869             (ins IntRegs:$src1, IntRegs:$src2),
4870             "$dst = cmpb.gtu($src1, $src2)",
4871             [(set (i1 PredRegs:$dst), (setugt (and (i32 IntRegs:$src1), 255),
4872                                              (and (i32 IntRegs:$src2), 255)))]>,
4873             Requires<[HasV4T]>;
4874
4875 // Following instruction is not being extended as it results into the incorrect
4876 // code for negative numbers.
4877
4878 // Signed half compare(.eq) ri.
4879 // Pd=cmph.eq(Rs,#s8)
4880 let isCompare = 1 in
4881 def CMPhEQri_V4 : MInst<(outs PredRegs:$dst),
4882             (ins IntRegs:$src1, s8Imm:$src2),
4883             "$dst = cmph.eq($src1, #$src2)",
4884             [(set (i1 PredRegs:$dst), (seteq (and (i32 IntRegs:$src1), 65535),
4885                                              s8ImmPred:$src2))]>,
4886             Requires<[HasV4T]>;
4887
4888 // Signed half compare(.eq) rr.
4889 // Case 1: xor + and, then compare:
4890 //   r0=xor(r0,r1)
4891 //   r0=and(r0,#0xffff)
4892 //   p0=cmp.eq(r0,#0)
4893 // Pd=cmph.eq(Rs,Rt)
4894 let isCompare = 1 in
4895 def CMPhEQrr_xor_V4 : MInst<(outs PredRegs:$dst),
4896             (ins IntRegs:$src1, IntRegs:$src2),
4897             "$dst = cmph.eq($src1, $src2)",
4898             [(set (i1 PredRegs:$dst), (seteq (and (xor (i32 IntRegs:$src1),
4899                                                        (i32 IntRegs:$src2)),
4900                                                   65535), 0))]>,
4901             Requires<[HasV4T]>;
4902
4903 // Signed half compare(.eq) rr.
4904 // Case 2: shift left 16 bits then compare:
4905 //   r0=asl(r0,16)
4906 //   r1=asl(r1,16)
4907 //   p0=cmp.eq(r0,r1)
4908 // Pd=cmph.eq(Rs,Rt)
4909 let isCompare = 1 in
4910 def CMPhEQrr_shl_V4 : MInst<(outs PredRegs:$dst),
4911             (ins IntRegs:$src1, IntRegs:$src2),
4912             "$dst = cmph.eq($src1, $src2)",
4913             [(set (i1 PredRegs:$dst),
4914                   (seteq (shl (i32 IntRegs:$src1), (i32 16)),
4915                          (shl (i32 IntRegs:$src2), (i32 16))))]>,
4916             Requires<[HasV4T]>;
4917
4918 /* Incorrect Pattern -- immediate should be right shifted before being
4919 used in the cmph.gt instruction.
4920 // Signed half compare(.gt) ri.
4921 // Pd=cmph.gt(Rs,#s8)
4922
4923 let isCompare = 1 in
4924 def CMPhGTri_V4 : MInst<(outs PredRegs:$dst),
4925             (ins IntRegs:$src1, s8Imm:$src2),
4926             "$dst = cmph.gt($src1, #$src2)",
4927             [(set (i1 PredRegs:$dst),
4928                   (setgt (shl (i32 IntRegs:$src1), (i32 16)),
4929                          s8ImmPred:$src2))]>,
4930             Requires<[HasV4T]>;
4931 */
4932
4933 // Signed half compare(.gt) rr.
4934 // Pd=cmph.gt(Rs,Rt)
4935 let isCompare = 1 in
4936 def CMPhGTrr_shl_V4 : MInst<(outs PredRegs:$dst),
4937             (ins IntRegs:$src1, IntRegs:$src2),
4938             "$dst = cmph.gt($src1, $src2)",
4939             [(set (i1 PredRegs:$dst),
4940                   (setgt (shl (i32 IntRegs:$src1), (i32 16)),
4941                          (shl (i32 IntRegs:$src2), (i32 16))))]>,
4942             Requires<[HasV4T]>;
4943
4944 // Unsigned half compare rr (.gtu).
4945 // Pd=cmph.gtu(Rs,Rt)
4946 let isCompare = 1 in
4947 def CMPhGTUrr_V4 : MInst<(outs PredRegs:$dst),
4948             (ins IntRegs:$src1, IntRegs:$src2),
4949             "$dst = cmph.gtu($src1, $src2)",
4950             [(set (i1 PredRegs:$dst),
4951                   (setugt (and (i32 IntRegs:$src1), 65535),
4952                           (and (i32 IntRegs:$src2), 65535)))]>,
4953             Requires<[HasV4T]>;
4954
4955 // Unsigned half compare ri (.gtu).
4956 // Pd=cmph.gtu(Rs,#u7)
4957 let isCompare = 1 in
4958 def CMPhGTUri_V4 : MInst<(outs PredRegs:$dst),
4959             (ins IntRegs:$src1, u7Imm:$src2),
4960             "$dst = cmph.gtu($src1, #$src2)",
4961             [(set (i1 PredRegs:$dst), (setugt (and (i32 IntRegs:$src1), 65535),
4962                                               u7ImmPred:$src2))]>,
4963             Requires<[HasV4T]>;
4964
4965 //===----------------------------------------------------------------------===//
4966 // XTYPE/PRED -
4967 //===----------------------------------------------------------------------===//
4968
4969 //Deallocate frame and return.
4970 //    dealloc_return
4971 let isReturn = 1, isTerminator = 1, isBarrier = 1, isPredicable = 1,
4972   Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1 in {
4973   def DEALLOC_RET_V4 : NVInst_V4<(outs), (ins i32imm:$amt1),
4974             "dealloc_return",
4975             []>,
4976             Requires<[HasV4T]>;
4977 }
4978
4979 // Restore registers and dealloc return function call.
4980 let isCall = 1, isBarrier = 1, isReturn = 1, isTerminator = 1,
4981   Defs = [R29, R30, R31, PC] in {
4982   def RESTORE_DEALLOC_RET_JMP_V4 : JInst<(outs),
4983                                    (ins calltarget:$dst),
4984              "jump $dst // Restore_and_dealloc_return",
4985              []>,
4986              Requires<[HasV4T]>;
4987 }
4988
4989 // Restore registers and dealloc frame before a tail call.
4990 let isCall = 1, isBarrier = 1,
4991   Defs = [R29, R30, R31, PC] in {
4992   def RESTORE_DEALLOC_BEFORE_TAILCALL_V4 : JInst<(outs),
4993                                            (ins calltarget:$dst),
4994              "call $dst // Restore_and_dealloc_before_tailcall",
4995              []>,
4996              Requires<[HasV4T]>;
4997 }
4998
4999 // Save registers function call.
5000 let isCall = 1, isBarrier = 1,
5001   Uses = [R29, R31] in {
5002   def SAVE_REGISTERS_CALL_V4 : JInst<(outs),
5003                                (ins calltarget:$dst),
5004              "call $dst // Save_calle_saved_registers",
5005              []>,
5006              Requires<[HasV4T]>;
5007 }
5008
5009 //    if (Ps) dealloc_return
5010 let isReturn = 1, isTerminator = 1,
5011     Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1,
5012     isPredicated = 1 in {
5013   def DEALLOC_RET_cPt_V4 : NVInst_V4<(outs),
5014                            (ins PredRegs:$src1, i32imm:$amt1),
5015             "if ($src1) dealloc_return",
5016             []>,
5017             Requires<[HasV4T]>;
5018 }
5019
5020 //    if (!Ps) dealloc_return
5021 let isReturn = 1, isTerminator = 1,
5022     Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1,
5023     isPredicated = 1 in {
5024   def DEALLOC_RET_cNotPt_V4 : NVInst_V4<(outs), (ins PredRegs:$src1,
5025                                                      i32imm:$amt1),
5026             "if (!$src1) dealloc_return",
5027             []>,
5028             Requires<[HasV4T]>;
5029 }
5030
5031 //    if (Ps.new) dealloc_return:nt
5032 let isReturn = 1, isTerminator = 1,
5033     Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1,
5034     isPredicated = 1 in {
5035   def DEALLOC_RET_cdnPnt_V4 : NVInst_V4<(outs), (ins PredRegs:$src1,
5036                                                      i32imm:$amt1),
5037             "if ($src1.new) dealloc_return:nt",
5038             []>,
5039             Requires<[HasV4T]>;
5040 }
5041
5042 //    if (!Ps.new) dealloc_return:nt
5043 let isReturn = 1, isTerminator = 1,
5044     Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1,
5045     isPredicated = 1 in {
5046   def DEALLOC_RET_cNotdnPnt_V4 : NVInst_V4<(outs), (ins PredRegs:$src1,
5047                                                         i32imm:$amt1),
5048             "if (!$src1.new) dealloc_return:nt",
5049             []>,
5050             Requires<[HasV4T]>;
5051 }
5052
5053 //    if (Ps.new) dealloc_return:t
5054 let isReturn = 1, isTerminator = 1,
5055     Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1,
5056     isPredicated = 1 in {
5057   def DEALLOC_RET_cdnPt_V4 : NVInst_V4<(outs), (ins PredRegs:$src1,
5058                                                     i32imm:$amt1),
5059             "if ($src1.new) dealloc_return:t",
5060             []>,
5061             Requires<[HasV4T]>;
5062 }
5063
5064 //    if (!Ps.new) dealloc_return:nt
5065 let isReturn = 1, isTerminator = 1,
5066     Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1,
5067     isPredicated = 1 in {
5068   def DEALLOC_RET_cNotdnPt_V4 : NVInst_V4<(outs), (ins PredRegs:$src1,
5069                                                        i32imm:$amt1),
5070             "if (!$src1.new) dealloc_return:t",
5071             []>,
5072             Requires<[HasV4T]>;
5073 }
5074
5075
5076 // Load/Store with absolute addressing mode
5077 // memw(#u6)=Rt
5078
5079 multiclass ST_abs<string OpcStr> {
5080   let isPredicable = 1 in
5081   def _abs_V4 : STInst2<(outs),
5082             (ins globaladdress:$absaddr, IntRegs:$src),
5083             !strconcat(OpcStr, "(##$absaddr) = $src"),
5084             []>,
5085             Requires<[HasV4T]>;
5086
5087   let isPredicated = 1 in
5088   def _abs_cPt_V4 : STInst2<(outs),
5089             (ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2),
5090             !strconcat("if ($src1)",
5091             !strconcat(OpcStr, "(##$absaddr) = $src2")),
5092             []>,
5093             Requires<[HasV4T]>;
5094
5095   let isPredicated = 1 in
5096   def _abs_cNotPt_V4 : STInst2<(outs),
5097             (ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2),
5098             !strconcat("if (!$src1)",
5099             !strconcat(OpcStr, "(##$absaddr) = $src2")),
5100             []>,
5101             Requires<[HasV4T]>;
5102
5103   let isPredicated = 1 in
5104   def _abs_cdnPt_V4 : STInst2<(outs),
5105             (ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2),
5106             !strconcat("if ($src1.new)",
5107             !strconcat(OpcStr, "(##$absaddr) = $src2")),
5108             []>,
5109             Requires<[HasV4T]>;
5110
5111   let isPredicated = 1 in
5112   def _abs_cdnNotPt_V4 : STInst2<(outs),
5113             (ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2),
5114             !strconcat("if (!$src1.new)",
5115             !strconcat(OpcStr, "(##$absaddr) = $src2")),
5116             []>,
5117             Requires<[HasV4T]>;
5118
5119   def _abs_nv_V4 : STInst2<(outs),
5120             (ins globaladdress:$absaddr, IntRegs:$src),
5121             !strconcat(OpcStr, "(##$absaddr) = $src.new"),
5122             []>,
5123             Requires<[HasV4T]>;
5124
5125   let isPredicated = 1 in
5126   def _abs_cPt_nv_V4 : STInst2<(outs),
5127             (ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2),
5128             !strconcat("if ($src1)",
5129             !strconcat(OpcStr, "(##$absaddr) = $src2.new")),
5130             []>,
5131             Requires<[HasV4T]>;
5132
5133   let isPredicated = 1 in
5134   def _abs_cNotPt_nv_V4 : STInst2<(outs),
5135             (ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2),
5136             !strconcat("if (!$src1)",
5137             !strconcat(OpcStr, "(##$absaddr) = $src2.new")),
5138             []>,
5139             Requires<[HasV4T]>;
5140
5141   let isPredicated = 1 in
5142   def _abs_cdnPt_nv_V4 : STInst2<(outs),
5143             (ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2),
5144             !strconcat("if ($src1.new)",
5145             !strconcat(OpcStr, "(##$absaddr) = $src2.new")),
5146             []>,
5147             Requires<[HasV4T]>;
5148
5149   let isPredicated = 1 in
5150   def _abs_cdnNotPt_nv_V4 : STInst2<(outs),
5151             (ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2),
5152             !strconcat("if (!$src1.new)",
5153             !strconcat(OpcStr, "(##$absaddr) = $src2.new")),
5154             []>,
5155             Requires<[HasV4T]>;
5156 }
5157
5158 let AddedComplexity = 30, isPredicable = 1 in
5159 def STrid_abs_V4 : STInst<(outs),
5160           (ins globaladdress:$absaddr, DoubleRegs:$src),
5161            "memd(##$absaddr) = $src",
5162           [(store (i64 DoubleRegs:$src),
5163                   (HexagonCONST32 tglobaladdr:$absaddr))]>,
5164           Requires<[HasV4T]>;
5165
5166 let AddedComplexity = 30, isPredicated = 1 in
5167 def STrid_abs_cPt_V4 : STInst2<(outs),
5168           (ins PredRegs:$src1, globaladdress:$absaddr, DoubleRegs:$src2),
5169           "if ($src1) memd(##$absaddr) = $src2",
5170           []>,
5171           Requires<[HasV4T]>;
5172
5173 let AddedComplexity = 30, isPredicated = 1 in
5174 def STrid_abs_cNotPt_V4 : STInst2<(outs),
5175           (ins PredRegs:$src1, globaladdress:$absaddr, DoubleRegs:$src2),
5176           "if (!$src1) memd(##$absaddr) = $src2",
5177           []>,
5178           Requires<[HasV4T]>;
5179
5180 let AddedComplexity = 30, isPredicated = 1 in
5181 def STrid_abs_cdnPt_V4 : STInst2<(outs),
5182           (ins PredRegs:$src1, globaladdress:$absaddr, DoubleRegs:$src2),
5183           "if ($src1.new) memd(##$absaddr) = $src2",
5184           []>,
5185           Requires<[HasV4T]>;
5186
5187 let AddedComplexity = 30, isPredicated = 1 in
5188 def STrid_abs_cdnNotPt_V4 : STInst2<(outs),
5189           (ins PredRegs:$src1, globaladdress:$absaddr, DoubleRegs:$src2),
5190           "if (!$src1.new) memd(##$absaddr) = $src2",
5191           []>,
5192           Requires<[HasV4T]>;
5193
5194 defm STrib : ST_abs<"memb">;
5195 defm STrih : ST_abs<"memh">;
5196 defm STriw : ST_abs<"memw">;
5197
5198 let Predicates = [HasV4T], AddedComplexity  = 30 in
5199 def : Pat<(truncstorei8 (i32 IntRegs:$src1),
5200                         (HexagonCONST32 tglobaladdr:$absaddr)),
5201           (STrib_abs_V4 tglobaladdr: $absaddr, IntRegs: $src1)>;
5202
5203 let Predicates = [HasV4T], AddedComplexity  = 30 in
5204 def : Pat<(truncstorei16 (i32 IntRegs:$src1),
5205                           (HexagonCONST32 tglobaladdr:$absaddr)),
5206           (STrih_abs_V4 tglobaladdr: $absaddr, IntRegs: $src1)>;
5207
5208 let Predicates = [HasV4T], AddedComplexity  = 30 in
5209 def : Pat<(store (i32 IntRegs:$src1), (HexagonCONST32 tglobaladdr:$absaddr)),
5210           (STriw_abs_V4 tglobaladdr: $absaddr, IntRegs: $src1)>;
5211
5212
5213 multiclass LD_abs<string OpcStr> {
5214   let isPredicable = 1 in
5215   def _abs_V4 : LDInst2<(outs IntRegs:$dst),
5216             (ins globaladdress:$absaddr),
5217             !strconcat("$dst = ", !strconcat(OpcStr, "(##$absaddr)")),
5218             []>,
5219             Requires<[HasV4T]>;
5220
5221   let isPredicated = 1 in
5222   def _abs_cPt_V4 : LDInst2<(outs IntRegs:$dst),
5223             (ins PredRegs:$src1, globaladdress:$absaddr),
5224             !strconcat("if ($src1) $dst = ",
5225             !strconcat(OpcStr, "(##$absaddr)")),
5226             []>,
5227             Requires<[HasV4T]>;
5228
5229   let isPredicated = 1 in
5230   def _abs_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
5231             (ins PredRegs:$src1, globaladdress:$absaddr),
5232             !strconcat("if (!$src1) $dst = ",
5233             !strconcat(OpcStr, "(##$absaddr)")),
5234             []>,
5235             Requires<[HasV4T]>;
5236
5237   let isPredicated = 1 in
5238   def _abs_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
5239             (ins PredRegs:$src1, globaladdress:$absaddr),
5240             !strconcat("if ($src1.new) $dst = ",
5241             !strconcat(OpcStr, "(##$absaddr)")),
5242             []>,
5243             Requires<[HasV4T]>;
5244
5245   let isPredicated = 1 in
5246   def _abs_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
5247             (ins PredRegs:$src1, globaladdress:$absaddr),
5248             !strconcat("if (!$src1.new) $dst = ",
5249             !strconcat(OpcStr, "(##$absaddr)")),
5250             []>,
5251             Requires<[HasV4T]>;
5252 }
5253
5254 let AddedComplexity = 30 in
5255 def LDrid_abs_V4 : LDInst<(outs DoubleRegs:$dst),
5256           (ins globaladdress:$absaddr),
5257           "$dst = memd(##$absaddr)",
5258           [(set (i64 DoubleRegs:$dst),
5259                 (load (HexagonCONST32 tglobaladdr:$absaddr)))]>,
5260           Requires<[HasV4T]>;
5261
5262 let AddedComplexity = 30, isPredicated = 1 in
5263 def LDrid_abs_cPt_V4 : LDInst2<(outs DoubleRegs:$dst),
5264           (ins PredRegs:$src1, globaladdress:$absaddr),
5265           "if ($src1) $dst = memd(##$absaddr)",
5266           []>,
5267           Requires<[HasV4T]>;
5268
5269 let AddedComplexity = 30, isPredicated = 1 in
5270 def LDrid_abs_cNotPt_V4 : LDInst2<(outs DoubleRegs:$dst),
5271           (ins PredRegs:$src1, globaladdress:$absaddr),
5272           "if (!$src1) $dst = memd(##$absaddr)",
5273           []>,
5274           Requires<[HasV4T]>;
5275
5276 let AddedComplexity = 30, isPredicated = 1 in
5277 def LDrid_abs_cdnPt_V4 : LDInst2<(outs DoubleRegs:$dst),
5278           (ins PredRegs:$src1, globaladdress:$absaddr),
5279           "if ($src1.new) $dst = memd(##$absaddr)",
5280           []>,
5281           Requires<[HasV4T]>;
5282
5283 let AddedComplexity = 30, isPredicated = 1 in
5284 def LDrid_abs_cdnNotPt_V4 : LDInst2<(outs DoubleRegs:$dst),
5285           (ins PredRegs:$src1, globaladdress:$absaddr),
5286           "if (!$src1.new) $dst = memd(##$absaddr)",
5287           []>,
5288           Requires<[HasV4T]>;
5289
5290 defm LDrib : LD_abs<"memb">;
5291 defm LDriub : LD_abs<"memub">;
5292 defm LDrih : LD_abs<"memh">;
5293 defm LDriuh : LD_abs<"memuh">;
5294 defm LDriw : LD_abs<"memw">;
5295
5296
5297 let Predicates = [HasV4T], AddedComplexity  = 30 in
5298 def : Pat<(i32 (load (HexagonCONST32 tglobaladdr:$absaddr))),
5299           (LDriw_abs_V4 tglobaladdr: $absaddr)>;
5300
5301 let Predicates = [HasV4T], AddedComplexity=30 in
5302 def : Pat<(i32 (sextloadi8 (HexagonCONST32 tglobaladdr:$absaddr))),
5303           (LDrib_abs_V4 tglobaladdr:$absaddr)>;
5304
5305 let Predicates = [HasV4T], AddedComplexity=30 in
5306 def : Pat<(i32 (zextloadi8 (HexagonCONST32 tglobaladdr:$absaddr))),
5307           (LDriub_abs_V4 tglobaladdr:$absaddr)>;
5308
5309 let Predicates = [HasV4T], AddedComplexity=30 in
5310 def : Pat<(i32 (sextloadi16 (HexagonCONST32 tglobaladdr:$absaddr))),
5311           (LDrih_abs_V4 tglobaladdr:$absaddr)>;
5312
5313 let Predicates = [HasV4T], AddedComplexity=30 in
5314 def : Pat<(i32 (zextloadi16 (HexagonCONST32 tglobaladdr:$absaddr))),
5315           (LDriuh_abs_V4 tglobaladdr:$absaddr)>;
5316
5317 // Transfer global address into a register
5318 let AddedComplexity=50, isMoveImm = 1, isReMaterializable = 1 in
5319 def TFRI_V4 : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$src1),
5320            "$dst = ##$src1",
5321            [(set IntRegs:$dst, (HexagonCONST32 tglobaladdr:$src1))]>,
5322            Requires<[HasV4T]>;
5323
5324 let AddedComplexity=50, neverHasSideEffects = 1, isPredicated = 1 in
5325 def TFRI_cPt_V4 : ALU32_ri<(outs IntRegs:$dst),
5326                            (ins PredRegs:$src1, globaladdress:$src2),
5327            "if($src1) $dst = ##$src2",
5328            []>,
5329            Requires<[HasV4T]>;
5330
5331 let AddedComplexity=50, neverHasSideEffects = 1, isPredicated = 1 in
5332 def TFRI_cNotPt_V4 : ALU32_ri<(outs IntRegs:$dst),
5333                               (ins PredRegs:$src1, globaladdress:$src2),
5334            "if(!$src1) $dst = ##$src2",
5335            []>,
5336            Requires<[HasV4T]>;
5337
5338 let AddedComplexity=50, neverHasSideEffects = 1, isPredicated = 1 in
5339 def TFRI_cdnPt_V4 : ALU32_ri<(outs IntRegs:$dst),
5340                              (ins PredRegs:$src1, globaladdress:$src2),
5341            "if($src1.new) $dst = ##$src2",
5342            []>,
5343            Requires<[HasV4T]>;
5344
5345 let AddedComplexity=50, neverHasSideEffects = 1, isPredicated = 1 in
5346 def TFRI_cdnNotPt_V4 : ALU32_ri<(outs IntRegs:$dst),
5347                                 (ins PredRegs:$src1, globaladdress:$src2),
5348            "if(!$src1.new) $dst = ##$src2",
5349            []>,
5350            Requires<[HasV4T]>;
5351
5352 let AddedComplexity = 50, Predicates = [HasV4T] in
5353 def : Pat<(HexagonCONST32_GP tglobaladdr:$src1),
5354            (TFRI_V4 tglobaladdr:$src1)>;
5355
5356
5357 // Load - Indirect with long offset: These instructions take global address
5358 // as an operand
5359 let AddedComplexity = 10 in
5360 def LDrid_ind_lo_V4 : LDInst<(outs DoubleRegs:$dst),
5361             (ins IntRegs:$src1, u2Imm:$src2, globaladdress:$offset),
5362             "$dst=memd($src1<<#$src2+##$offset)",
5363             [(set (i64 DoubleRegs:$dst),
5364                   (load (add (shl IntRegs:$src1, u2ImmPred:$src2),
5365                         (HexagonCONST32 tglobaladdr:$offset))))]>,
5366             Requires<[HasV4T]>;
5367
5368 let AddedComplexity = 10 in
5369 multiclass LD_indirect_lo<string OpcStr, PatFrag OpNode> {
5370   def _lo_V4 : LDInst<(outs IntRegs:$dst),
5371             (ins IntRegs:$src1, u2Imm:$src2, globaladdress:$offset),
5372             !strconcat("$dst = ",
5373             !strconcat(OpcStr, "($src1<<#$src2+##$offset)")),
5374             [(set IntRegs:$dst,
5375                   (i32 (OpNode (add (shl IntRegs:$src1, u2ImmPred:$src2),
5376                           (HexagonCONST32 tglobaladdr:$offset)))))]>,
5377             Requires<[HasV4T]>;
5378 }
5379
5380 defm LDrib_ind : LD_indirect_lo<"memb", sextloadi8>;
5381 defm LDriub_ind : LD_indirect_lo<"memub", zextloadi8>;
5382 defm LDrih_ind : LD_indirect_lo<"memh", sextloadi16>;
5383 defm LDriuh_ind : LD_indirect_lo<"memuh", zextloadi16>;
5384 defm LDriw_ind : LD_indirect_lo<"memw", load>;
5385
5386 // Store - Indirect with long offset: These instructions take global address
5387 // as an operand
5388 let AddedComplexity = 10 in
5389 def STrid_ind_lo_V4 : STInst<(outs),
5390             (ins IntRegs:$src1, u2Imm:$src2, globaladdress:$src3,
5391                  DoubleRegs:$src4),
5392             "memd($src1<<#$src2+#$src3) = $src4",
5393             [(store (i64 DoubleRegs:$src4),
5394                  (add (shl IntRegs:$src1, u2ImmPred:$src2),
5395                       (HexagonCONST32 tglobaladdr:$src3)))]>,
5396              Requires<[HasV4T]>;
5397
5398 let AddedComplexity = 10 in
5399 multiclass ST_indirect_lo<string OpcStr, PatFrag OpNode> {
5400   def _lo_V4 : STInst<(outs),
5401             (ins IntRegs:$src1, u2Imm:$src2, globaladdress:$src3,
5402                  IntRegs:$src4),
5403             !strconcat(OpcStr, "($src1<<#$src2+##$src3) = $src4"),
5404             [(OpNode (i32 IntRegs:$src4),
5405                  (add (shl IntRegs:$src1, u2ImmPred:$src2),
5406                       (HexagonCONST32 tglobaladdr:$src3)))]>,
5407              Requires<[HasV4T]>;
5408 }
5409
5410 defm STrib_ind : ST_indirect_lo<"memb", truncstorei8>;
5411 defm STrih_ind : ST_indirect_lo<"memh", truncstorei16>;
5412 defm STriw_ind : ST_indirect_lo<"memw", store>;
5413
5414 // Store - absolute addressing mode: These instruction take constant
5415 // value as the extended operand
5416 multiclass ST_absimm<string OpcStr> {
5417   let isPredicable = 1 in
5418   def _abs_V4 : STInst2<(outs),
5419             (ins u6Imm:$src1, IntRegs:$src2),
5420             !strconcat(OpcStr, "(#$src1) = $src2"),
5421             []>,
5422             Requires<[HasV4T]>;
5423
5424   let isPredicated = 1 in
5425   def _abs_cPt_V4 : STInst2<(outs),
5426             (ins PredRegs:$src1, u6Imm:$src2, IntRegs:$src3),
5427             !strconcat("if ($src1)", !strconcat(OpcStr, "(#$src2) = $src3")),
5428             []>,
5429             Requires<[HasV4T]>;
5430
5431   let isPredicated = 1 in
5432   def _abs_cNotPt_V4 : STInst2<(outs),
5433             (ins PredRegs:$src1, u6Imm:$src2, IntRegs:$src3),
5434             !strconcat("if (!$src1)", !strconcat(OpcStr, "(#$src2) = $src3")),
5435             []>,
5436             Requires<[HasV4T]>;
5437
5438   let isPredicated = 1 in
5439   def _abs_cdnPt_V4 : STInst2<(outs),
5440             (ins PredRegs:$src1, u6Imm:$src2, IntRegs:$src3),
5441             !strconcat("if ($src1.new)",
5442             !strconcat(OpcStr, "(#$src2) = $src3")),
5443             []>,
5444             Requires<[HasV4T]>;
5445
5446   let isPredicated = 1 in
5447   def _abs_cdnNotPt_V4 : STInst2<(outs),
5448             (ins PredRegs:$src1, u6Imm:$src2, IntRegs:$src3),
5449             !strconcat("if (!$src1.new)",
5450             !strconcat(OpcStr, "(#$src2) = $src3")),
5451             []>,
5452             Requires<[HasV4T]>;
5453
5454   def _abs_nv_V4 : STInst2<(outs),
5455             (ins u6Imm:$src1, IntRegs:$src2),
5456             !strconcat(OpcStr, "(#$src1) = $src2.new"),
5457             []>,
5458             Requires<[HasV4T]>;
5459
5460   let isPredicated = 1 in
5461   def _abs_cPt_nv_V4 : STInst2<(outs),
5462             (ins PredRegs:$src1, u6Imm:$src2, IntRegs:$src3),
5463             !strconcat("if ($src1)",
5464             !strconcat(OpcStr, "(#$src2) = $src3.new")),
5465             []>,
5466             Requires<[HasV4T]>;
5467
5468   let isPredicated = 1 in
5469   def _abs_cNotPt_nv_V4 : STInst2<(outs),
5470             (ins PredRegs:$src1, u6Imm:$src2, IntRegs:$src3),
5471             !strconcat("if (!$src1)",
5472             !strconcat(OpcStr, "(#$src2) = $src3.new")),
5473             []>,
5474             Requires<[HasV4T]>;
5475
5476   let isPredicated = 1 in
5477   def _abs_cdnPt_nv_V4 : STInst2<(outs),
5478             (ins PredRegs:$src1, u6Imm:$src2, IntRegs:$src3),
5479             !strconcat("if ($src1.new)",
5480             !strconcat(OpcStr, "(#$src2) = $src3.new")),
5481             []>,
5482             Requires<[HasV4T]>;
5483
5484   let isPredicated = 1 in
5485   def _abs_cdnNotPt_nv_V4 : STInst2<(outs),
5486             (ins PredRegs:$src1, u6Imm:$src2, IntRegs:$src3),
5487             !strconcat("if (!$src1.new)",
5488             !strconcat(OpcStr, "(#$src2) = $src3.new")),
5489             []>,
5490             Requires<[HasV4T]>;
5491 }
5492
5493 defm STrib_imm : ST_absimm<"memb">;
5494 defm STrih_imm : ST_absimm<"memh">;
5495 defm STriw_imm : ST_absimm<"memw">;
5496
5497 let Predicates = [HasV4T], AddedComplexity  = 30 in
5498 def : Pat<(truncstorei8 (i32 IntRegs:$src1), u6ImmPred:$src2),
5499           (STrib_imm_abs_V4 u6ImmPred:$src2, IntRegs: $src1)>;
5500
5501 let Predicates = [HasV4T], AddedComplexity  = 30 in
5502 def : Pat<(truncstorei16 (i32 IntRegs:$src1), u6ImmPred:$src2),
5503           (STrih_imm_abs_V4 u6ImmPred:$src2, IntRegs: $src1)>;
5504
5505 let Predicates = [HasV4T], AddedComplexity  = 30 in
5506 def : Pat<(store (i32 IntRegs:$src1), u6ImmPred:$src2),
5507           (STriw_imm_abs_V4 u6ImmPred:$src2, IntRegs: $src1)>;
5508
5509
5510 // Load - absolute addressing mode: These instruction take constant
5511 // value as the extended operand
5512
5513 multiclass LD_absimm<string OpcStr> {
5514   let isPredicable = 1 in
5515   def _abs_V4 : LDInst2<(outs IntRegs:$dst),
5516             (ins u6Imm:$src),
5517             !strconcat("$dst = ",
5518             !strconcat(OpcStr, "(#$src)")),
5519             []>,
5520             Requires<[HasV4T]>;
5521
5522   let isPredicated = 1 in
5523   def _abs_cPt_V4 : LDInst2<(outs IntRegs:$dst),
5524             (ins PredRegs:$src1, u6Imm:$src2),
5525             !strconcat("if ($src1) $dst = ",
5526             !strconcat(OpcStr, "(#$src2)")),
5527             []>,
5528             Requires<[HasV4T]>;
5529
5530   let isPredicated = 1 in
5531   def _abs_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
5532             (ins PredRegs:$src1, u6Imm:$src2),
5533             !strconcat("if (!$src1) $dst = ",
5534             !strconcat(OpcStr, "(#$src2)")),
5535             []>,
5536             Requires<[HasV4T]>;
5537
5538   let isPredicated = 1 in
5539   def _abs_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
5540             (ins PredRegs:$src1, u6Imm:$src2),
5541             !strconcat("if ($src1.new) $dst = ",
5542             !strconcat(OpcStr, "(#$src2)")),
5543             []>,
5544             Requires<[HasV4T]>;
5545
5546   let isPredicated = 1 in
5547   def _abs_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
5548             (ins PredRegs:$src1, u6Imm:$src2),
5549             !strconcat("if (!$src1.new) $dst = ",
5550             !strconcat(OpcStr, "(#$src2)")),
5551             []>,
5552             Requires<[HasV4T]>;
5553 }
5554
5555 defm LDrib_imm : LD_absimm<"memb">;
5556 defm LDriub_imm : LD_absimm<"memub">;
5557 defm LDrih_imm : LD_absimm<"memh">;
5558 defm LDriuh_imm : LD_absimm<"memuh">;
5559 defm LDriw_imm : LD_absimm<"memw">;
5560
5561 let Predicates = [HasV4T], AddedComplexity  = 30 in
5562 def : Pat<(i32 (load u6ImmPred:$src)),
5563           (LDriw_imm_abs_V4 u6ImmPred:$src)>;
5564
5565 let Predicates = [HasV4T], AddedComplexity=30 in
5566 def : Pat<(i32 (sextloadi8 u6ImmPred:$src)),
5567           (LDrib_imm_abs_V4 u6ImmPred:$src)>;
5568
5569 let Predicates = [HasV4T], AddedComplexity=30 in
5570 def : Pat<(i32 (zextloadi8 u6ImmPred:$src)),
5571           (LDriub_imm_abs_V4 u6ImmPred:$src)>;
5572
5573 let Predicates = [HasV4T], AddedComplexity=30 in
5574 def : Pat<(i32 (sextloadi16 u6ImmPred:$src)),
5575           (LDrih_imm_abs_V4 u6ImmPred:$src)>;
5576
5577 let Predicates = [HasV4T], AddedComplexity=30 in
5578 def : Pat<(i32 (zextloadi16 u6ImmPred:$src)),
5579           (LDriuh_imm_abs_V4 u6ImmPred:$src)>;
5580
5581
5582 // Indexed store double word - global address.
5583 // memw(Rs+#u6:2)=#S8
5584 let AddedComplexity = 10 in
5585 def STriw_offset_ext_V4 : STInst<(outs),
5586             (ins IntRegs:$src1, u6_2Imm:$src2, globaladdress:$src3),
5587             "memw($src1+#$src2) = ##$src3",
5588             [(store (HexagonCONST32 tglobaladdr:$src3),
5589                     (add IntRegs:$src1, u6_2ImmPred:$src2))]>,
5590             Requires<[HasV4T]>;
5591
5592
5593 // Indexed store double word - global address.
5594 // memw(Rs+#u6:2)=#S8
5595 let AddedComplexity = 10 in
5596 def STrih_offset_ext_V4 : STInst<(outs),
5597             (ins IntRegs:$src1, u6_1Imm:$src2, globaladdress:$src3),
5598             "memh($src1+#$src2) = ##$src3",
5599             [(truncstorei16 (HexagonCONST32 tglobaladdr:$src3),
5600                     (add IntRegs:$src1, u6_1ImmPred:$src2))]>,
5601             Requires<[HasV4T]>;