lib/Target/Hexagon/HexagonInstrInfoV4.td

   1 //=- HexagonInstrInfoV4.td - Target Desc. for Hexagon Target -*- tablegen -*-=//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file describes the Hexagon V4 instructions in TableGen format.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 let neverHasSideEffects = 1 in
  15 def IMMEXT : Immext<(outs), (ins),
  16                     "/* immext #... */",
  17                     []>,
  18              Requires<[HasV4T]>;
  19
  20 // Hexagon V4 Architecture spec defines 8 instruction classes:
  21 // LD ST ALU32 XTYPE J JR MEMOP NV CR SYSTEM(system is not implemented in the
  22 // compiler)
  23
  24 // LD Instructions:
  25 // ========================================
  26 // Loads (8/16/32/64 bit)
  27 // Deallocframe
  28
  29 // ST Instructions:
  30 // ========================================
  31 // Stores (8/16/32/64 bit)
  32 // Allocframe
  33
  34 // ALU32 Instructions:
  35 // ========================================
  36 // Arithmetic / Logical (32 bit)
  37 // Vector Halfword
  38
  39 // XTYPE Instructions (32/64 bit):
  40 // ========================================
  41 // Arithmetic, Logical, Bit Manipulation
  42 // Multiply (Integer, Fractional, Complex)
  43 // Permute / Vector Permute Operations
  44 // Predicate Operations
  45 // Shift / Shift with Add/Sub/Logical
  46 // Vector Byte ALU
  47 // Vector Halfword (ALU, Shift, Multiply)
  48 // Vector Word (ALU, Shift)
  49
  50 // J Instructions:
  51 // ========================================
  52 // Jump/Call PC-relative
  53
  54 // JR Instructions:
  55 // ========================================
  56 // Jump/Call Register
  57
  58 // MEMOP Instructions:
  59 // ========================================
  60 // Operation on memory (8/16/32 bit)
  61
  62 // NV Instructions:
  63 // ========================================
  64 // New-value Jumps
  65 // New-value Stores
  66
  67 // CR Instructions:
  68 // ========================================
  69 // Control-Register Transfers
  70 // Hardware Loop Setup
  71 // Predicate Logicals & Reductions
  72
  73 // SYSTEM Instructions (not implemented in the compiler):
  74 // ========================================
  75 // Prefetch
  76 // Cache Maintenance
  77 // Bus Operations
  78
  79
  80 //===----------------------------------------------------------------------===//
  81 // ALU32 +
  82 //===----------------------------------------------------------------------===//
  83
  84 // Shift halfword.
  85
  86 let isPredicated = 1 in
  87 def ASLH_cPt_V4 : ALU32_rr<(outs IntRegs:$dst),
  88             (ins PredRegs:$src1, IntRegs:$src2),
  89             "if ($src1) $dst = aslh($src2)",
  90             []>,
  91             Requires<[HasV4T]>;
  92
  93 let isPredicated = 1 in
  94 def ASLH_cNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
  95             (ins PredRegs:$src1, IntRegs:$src2),
  96             "if (!$src1) $dst = aslh($src2)",
  97             []>,
  98             Requires<[HasV4T]>;
  99
 100 let isPredicated = 1 in
 101 def ASLH_cdnPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 102             (ins PredRegs:$src1, IntRegs:$src2),
 103             "if ($src1.new) $dst = aslh($src2)",
 104             []>,
 105             Requires<[HasV4T]>;
 106
 107 let isPredicated = 1 in
 108 def ASLH_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 109             (ins PredRegs:$src1, IntRegs:$src2),
 110             "if (!$src1.new) $dst = aslh($src2)",
 111             []>,
 112             Requires<[HasV4T]>;
 113
 114 let isPredicated = 1 in
 115 def ASRH_cPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 116             (ins PredRegs:$src1, IntRegs:$src2),
 117             "if ($src1) $dst = asrh($src2)",
 118             []>,
 119             Requires<[HasV4T]>;
 120
 121 let isPredicated = 1 in
 122 def ASRH_cNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 123             (ins PredRegs:$src1, IntRegs:$src2),
 124             "if (!$src1) $dst = asrh($src2)",
 125             []>,
 126             Requires<[HasV4T]>;
 127
 128 let isPredicated = 1 in
 129 def ASRH_cdnPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 130             (ins PredRegs:$src1, IntRegs:$src2),
 131             "if ($src1.new) $dst = asrh($src2)",
 132             []>,
 133             Requires<[HasV4T]>;
 134
 135 let isPredicated = 1 in
 136 def ASRH_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 137             (ins PredRegs:$src1, IntRegs:$src2),
 138             "if (!$src1.new) $dst = asrh($src2)",
 139             []>,
 140             Requires<[HasV4T]>;
 141
 142 // Sign extend.
 143
 144 let isPredicated = 1 in
 145 def SXTB_cPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 146             (ins PredRegs:$src1, IntRegs:$src2),
 147             "if ($src1) $dst = sxtb($src2)",
 148             []>,
 149             Requires<[HasV4T]>;
 150
 151 let isPredicated = 1 in
 152 def SXTB_cNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 153             (ins PredRegs:$src1, IntRegs:$src2),
 154             "if (!$src1) $dst = sxtb($src2)",
 155             []>,
 156             Requires<[HasV4T]>;
 157
 158 let isPredicated = 1 in
 159 def SXTB_cdnPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 160             (ins PredRegs:$src1, IntRegs:$src2),
 161             "if ($src1.new) $dst = sxtb($src2)",
 162             []>,
 163             Requires<[HasV4T]>;
 164
 165 let isPredicated = 1 in
 166 def SXTB_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 167             (ins PredRegs:$src1, IntRegs:$src2),
 168             "if (!$src1.new) $dst = sxtb($src2)",
 169             []>,
 170             Requires<[HasV4T]>;
 171
 172
 173 let isPredicated = 1 in
 174 def SXTH_cPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 175             (ins PredRegs:$src1, IntRegs:$src2),
 176             "if ($src1) $dst = sxth($src2)",
 177             []>,
 178             Requires<[HasV4T]>;
 179
 180 let isPredicated = 1 in
 181 def SXTH_cNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 182             (ins PredRegs:$src1, IntRegs:$src2),
 183             "if (!$src1) $dst = sxth($src2)",
 184             []>,
 185             Requires<[HasV4T]>;
 186
 187 let isPredicated = 1 in
 188 def SXTH_cdnPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 189             (ins PredRegs:$src1, IntRegs:$src2),
 190             "if ($src1.new) $dst = sxth($src2)",
 191             []>,
 192             Requires<[HasV4T]>;
 193
 194 let isPredicated = 1 in
 195 def SXTH_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 196             (ins PredRegs:$src1, IntRegs:$src2),
 197             "if (!$src1.new) $dst = sxth($src2)",
 198             []>,
 199             Requires<[HasV4T]>;
 200
 201 // Zero exten.
 202
 203 let neverHasSideEffects = 1, isPredicated = 1 in
 204 def ZXTB_cPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 205             (ins PredRegs:$src1, IntRegs:$src2),
 206             "if ($src1) $dst = zxtb($src2)",
 207             []>,
 208             Requires<[HasV4T]>;
 209
 210 let neverHasSideEffects = 1, isPredicated = 1 in
 211 def ZXTB_cNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 212             (ins PredRegs:$src1, IntRegs:$src2),
 213             "if (!$src1) $dst = zxtb($src2)",
 214             []>,
 215             Requires<[HasV4T]>;
 216
 217 let neverHasSideEffects = 1, isPredicated = 1 in
 218 def ZXTB_cdnPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 219             (ins PredRegs:$src1, IntRegs:$src2),
 220             "if ($src1.new) $dst = zxtb($src2)",
 221             []>,
 222             Requires<[HasV4T]>;
 223
 224 let neverHasSideEffects = 1, isPredicated = 1 in
 225 def ZXTB_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 226             (ins PredRegs:$src1, IntRegs:$src2),
 227             "if (!$src1.new) $dst = zxtb($src2)",
 228             []>,
 229             Requires<[HasV4T]>;
 230
 231 let neverHasSideEffects = 1, isPredicated = 1 in
 232 def ZXTH_cPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 233             (ins PredRegs:$src1, IntRegs:$src2),
 234             "if ($src1) $dst = zxth($src2)",
 235             []>,
 236             Requires<[HasV4T]>;
 237
 238 let neverHasSideEffects = 1, isPredicated = 1 in
 239 def ZXTH_cNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 240             (ins PredRegs:$src1, IntRegs:$src2),
 241             "if (!$src1) $dst = zxth($src2)",
 242             []>,
 243             Requires<[HasV4T]>;
 244
 245 let neverHasSideEffects = 1, isPredicated = 1 in
 246 def ZXTH_cdnPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 247             (ins PredRegs:$src1, IntRegs:$src2),
 248             "if ($src1.new) $dst = zxth($src2)",
 249             []>,
 250             Requires<[HasV4T]>;
 251
 252 let neverHasSideEffects = 1, isPredicated = 1 in
 253 def ZXTH_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 254             (ins PredRegs:$src1, IntRegs:$src2),
 255             "if (!$src1.new) $dst = zxth($src2)",
 256             []>,
 257             Requires<[HasV4T]>;
 258
 259 // Generate frame index addresses.
 260 let neverHasSideEffects = 1, isReMaterializable = 1 in
 261 def TFR_FI_immext_V4 : ALU32_ri<(outs IntRegs:$dst),
 262             (ins IntRegs:$src1, s32Imm:$offset),
 263             "$dst = add($src1, ##$offset)",
 264             []>,
 265             Requires<[HasV4T]>;
 266
 267
 268 //===----------------------------------------------------------------------===//
 269 // ALU32 -
 270 //===----------------------------------------------------------------------===//
 271
 272
 273 //===----------------------------------------------------------------------===//
 274 // ALU32/PERM +
 275 //===----------------------------------------------------------------------===//
 276
 277 // Combine
 278 // Rdd=combine(Rs, #s8)
 279 let neverHasSideEffects = 1 in
 280 def COMBINE_ri_V4 : ALU32_ri<(outs DoubleRegs:$dst),
 281             (ins IntRegs:$src1, s8Imm:$src2),
 282             "$dst = combine($src1, #$src2)",
 283             []>,
 284             Requires<[HasV4T]>;
 285 // Rdd=combine(#s8, Rs)
 286 let neverHasSideEffects = 1 in
 287 def COMBINE_ir_V4 : ALU32_ir<(outs DoubleRegs:$dst),
 288             (ins s8Imm:$src1, IntRegs:$src2),
 289             "$dst = combine(#$src1, $src2)",
 290             []>,
 291             Requires<[HasV4T]>;
 292 //===----------------------------------------------------------------------===//
 293 // ALU32/PERM +
 294 //===----------------------------------------------------------------------===//
 295
 296 //===----------------------------------------------------------------------===//
 297 // LD +
 298 //===----------------------------------------------------------------------===//
 299 //
 300 // These absolute set addressing mode instructions accept immediate as
 301 // an operand. We have duplicated these patterns to take global address.
 302
 303 let neverHasSideEffects = 1 in
 304 def LDrid_abs_setimm_V4 : LDInst2<(outs DoubleRegs:$dst1, IntRegs:$dst2),
 305             (ins u6Imm:$addr),
 306             "$dst1 = memd($dst2=#$addr)",
 307             []>,
 308             Requires<[HasV4T]>;
 309
 310 // Rd=memb(Re=#U6)
 311 let neverHasSideEffects = 1 in
 312 def LDrib_abs_setimm_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
 313             (ins u6Imm:$addr),
 314             "$dst1 = memb($dst2=#$addr)",
 315             []>,
 316             Requires<[HasV4T]>;
 317
 318 // Rd=memh(Re=#U6)
 319 let neverHasSideEffects = 1 in
 320 def LDrih_abs_setimm_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
 321             (ins u6Imm:$addr),
 322             "$dst1 = memh($dst2=#$addr)",
 323             []>,
 324             Requires<[HasV4T]>;
 325
 326 // Rd=memub(Re=#U6)
 327 let neverHasSideEffects = 1 in
 328 def LDriub_abs_setimm_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
 329             (ins u6Imm:$addr),
 330             "$dst1 = memub($dst2=#$addr)",
 331             []>,
 332             Requires<[HasV4T]>;
 333
 334 // Rd=memuh(Re=#U6)
 335 let neverHasSideEffects = 1 in
 336 def LDriuh_abs_setimm_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
 337             (ins u6Imm:$addr),
 338             "$dst1 = memuh($dst2=#$addr)",
 339             []>,
 340             Requires<[HasV4T]>;
 341
 342 // Rd=memw(Re=#U6)
 343 let neverHasSideEffects = 1 in
 344 def LDriw_abs_setimm_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
 345             (ins u6Imm:$addr),
 346             "$dst1 = memw($dst2=#$addr)",
 347             []>,
 348             Requires<[HasV4T]>;
 349
 350 // Following patterns are defined for absolute set addressing mode
 351 // instruction which take global address as operand.
 352 let neverHasSideEffects = 1 in
 353 def LDrid_abs_set_V4 : LDInst2<(outs DoubleRegs:$dst1, IntRegs:$dst2),
 354             (ins globaladdress:$addr),
 355             "$dst1 = memd($dst2=##$addr)",
 356             []>,
 357             Requires<[HasV4T]>;
 358
 359 // Rd=memb(Re=#U6)
 360 let neverHasSideEffects = 1 in
 361 def LDrib_abs_set_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
 362             (ins globaladdress:$addr),
 363             "$dst1 = memb($dst2=##$addr)",
 364             []>,
 365             Requires<[HasV4T]>;
 366
 367 // Rd=memh(Re=#U6)
 368 let neverHasSideEffects = 1 in
 369 def LDrih_abs_set_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
 370             (ins globaladdress:$addr),
 371             "$dst1 = memh($dst2=##$addr)",
 372             []>,
 373             Requires<[HasV4T]>;
 374
 375 // Rd=memub(Re=#U6)
 376 let neverHasSideEffects = 1 in
 377 def LDriub_abs_set_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
 378             (ins globaladdress:$addr),
 379             "$dst1 = memub($dst2=##$addr)",
 380             []>,
 381             Requires<[HasV4T]>;
 382
 383 // Rd=memuh(Re=#U6)
 384 let neverHasSideEffects = 1 in
 385 def LDriuh_abs_set_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
 386             (ins globaladdress:$addr),
 387             "$dst1 = memuh($dst2=##$addr)",
 388             []>,
 389             Requires<[HasV4T]>;
 390
 391 // Rd=memw(Re=#U6)
 392 let neverHasSideEffects = 1 in
 393 def LDriw_abs_set_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
 394             (ins globaladdress:$addr),
 395             "$dst1 = memw($dst2=##$addr)",
 396             []>,
 397             Requires<[HasV4T]>;
 398
 399 // Load doubleword.
 400 //
 401 // Make sure that in post increment load, the first operand is always the post
 402 // increment operand.
 403 //
 404 // Rdd=memd(Rs+Rt<<#u2)
 405 // Special case pattern for indexed load without offset which is easier to
 406 // match. AddedComplexity of this pattern should be lower than base+offset load
 407 // and lower yet than the more generic version with offset/shift below
 408 // Similar approach is taken for all other base+index loads.
 409 let AddedComplexity = 10, isPredicable = 1 in
 410 def LDrid_indexed_V4 : LDInst<(outs DoubleRegs:$dst),
 411                     (ins IntRegs:$src1, IntRegs:$src2),
 412                     "$dst=memd($src1+$src2<<#0)",
 413                     [(set (i64 DoubleRegs:$dst),
 414                           (i64 (load (add (i32 IntRegs:$src1),
 415                                           (i32 IntRegs:$src2)))))]>,
 416                     Requires<[HasV4T]>;
 417
 418 // multiclass for load instructions with base + register offset
 419 // addressing mode
 420 multiclass ld_idxd_shl_pbase<string mnemonic, RegisterClass RC, bit isNot,
 421                              bit isPredNew> {
 422   let PNewValue = #!if(isPredNew, "new", "") in
 423   def #NAME# : LDInst2<(outs RC:$dst),
 424             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$offset),
 425             !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
 426             ") ")#"$dst = "#mnemonic#"($src2+$src3<<#$offset)",
 427             []>, Requires<[HasV4T]>;
 428 }
 429
 430 multiclass ld_idxd_shl_pred<string mnemonic, RegisterClass RC, bit PredNot> {
 431   let PredSense = #!if(PredNot, "false", "true") in {
 432     defm _c#NAME# : ld_idxd_shl_pbase<mnemonic, RC, PredNot, 0>;
 433     // Predicate new
 434     defm _cdn#NAME# : ld_idxd_shl_pbase<mnemonic, RC, PredNot, 1>;
 435   }
 436 }
 437
 438 let neverHasSideEffects  = 1 in
 439 multiclass ld_idxd_shl<string mnemonic, string CextOp, RegisterClass RC> {
 440   let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed_shl in {
 441     let isPredicable = 1 in
 442     def #NAME#_V4 : LDInst2<(outs RC:$dst),
 443             (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$offset),
 444             "$dst = "#mnemonic#"($src1+$src2<<#$offset)",
 445             []>, Requires<[HasV4T]>;
 446
 447     let isPredicated = 1 in {
 448       defm Pt_V4 : ld_idxd_shl_pred<mnemonic, RC, 0 >;
 449       defm NotPt_V4 : ld_idxd_shl_pred<mnemonic, RC, 1>;
 450     }
 451   }
 452 }
 453
 454 let addrMode = BaseRegOffset in {
 455   defm LDrib_indexed_shl: ld_idxd_shl<"memb", "LDrib", IntRegs>, AddrModeRel;
 456   defm LDriub_indexed_shl: ld_idxd_shl<"memub", "LDriub", IntRegs>, AddrModeRel;
 457   defm LDrih_indexed_shl: ld_idxd_shl<"memh", "LDrih", IntRegs>, AddrModeRel;
 458   defm LDriuh_indexed_shl: ld_idxd_shl<"memuh", "LDriuh", IntRegs>, AddrModeRel;
 459   defm LDriw_indexed_shl: ld_idxd_shl<"memw", "LDriw", IntRegs>, AddrModeRel;
 460   defm LDrid_indexed_shl: ld_idxd_shl<"memd", "LDrid", DoubleRegs>, AddrModeRel;
 461 }
 462
 463 // 'def pats' for load instructions with base + register offset and non-zero
 464 // immediate value. Immediate value is used to left-shift the second
 465 // register operand.
 466 let AddedComplexity = 40 in {
 467 def : Pat <(i32 (sextloadi8 (add IntRegs:$src1,
 468                                  (shl IntRegs:$src2, u2ImmPred:$offset)))),
 469            (LDrib_indexed_shl_V4 IntRegs:$src1,
 470             IntRegs:$src2, u2ImmPred:$offset)>,
 471             Requires<[HasV4T]>;
 472
 473 def : Pat <(i32 (zextloadi8 (add IntRegs:$src1,
 474                                  (shl IntRegs:$src2, u2ImmPred:$offset)))),
 475            (LDriub_indexed_shl_V4 IntRegs:$src1,
 476             IntRegs:$src2, u2ImmPred:$offset)>,
 477             Requires<[HasV4T]>;
 478
 479 def : Pat <(i32 (extloadi8 (add IntRegs:$src1,
 480                                 (shl IntRegs:$src2, u2ImmPred:$offset)))),
 481            (LDriub_indexed_shl_V4 IntRegs:$src1,
 482             IntRegs:$src2, u2ImmPred:$offset)>,
 483             Requires<[HasV4T]>;
 484
 485 def : Pat <(i32 (sextloadi16 (add IntRegs:$src1,
 486                                   (shl IntRegs:$src2, u2ImmPred:$offset)))),
 487            (LDrih_indexed_shl_V4 IntRegs:$src1,
 488             IntRegs:$src2, u2ImmPred:$offset)>,
 489             Requires<[HasV4T]>;
 490
 491 def : Pat <(i32 (zextloadi16 (add IntRegs:$src1,
 492                                   (shl IntRegs:$src2, u2ImmPred:$offset)))),
 493            (LDriuh_indexed_shl_V4 IntRegs:$src1,
 494             IntRegs:$src2, u2ImmPred:$offset)>,
 495             Requires<[HasV4T]>;
 496
 497 def : Pat <(i32 (extloadi16 (add IntRegs:$src1,
 498                                  (shl IntRegs:$src2, u2ImmPred:$offset)))),
 499            (LDriuh_indexed_shl_V4 IntRegs:$src1,
 500             IntRegs:$src2, u2ImmPred:$offset)>,
 501             Requires<[HasV4T]>;
 502
 503 def : Pat <(i32 (load (add IntRegs:$src1,
 504                            (shl IntRegs:$src2, u2ImmPred:$offset)))),
 505            (LDriw_indexed_shl_V4 IntRegs:$src1,
 506             IntRegs:$src2, u2ImmPred:$offset)>,
 507             Requires<[HasV4T]>;
 508
 509 def : Pat <(i64 (load (add IntRegs:$src1,
 510                            (shl IntRegs:$src2, u2ImmPred:$offset)))),
 511            (LDrid_indexed_shl_V4 IntRegs:$src1,
 512             IntRegs:$src2, u2ImmPred:$offset)>,
 513             Requires<[HasV4T]>;
 514 }
 515
 516 //// Load doubleword conditionally.
 517 // if ([!]Pv[.new]) Rd=memd(Rs+Rt<<#u2)
 518 // if (Pv) Rd=memd(Rs+Rt<<#u2)
 519 let AddedComplexity = 15, isPredicated = 1 in
 520 def LDrid_indexed_cPt_V4 : LDInst2<(outs DoubleRegs:$dst),
 521                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 522                     "if ($src1) $dst=memd($src2+$src3<<#0)",
 523                     []>,
 524                     Requires<[HasV4T]>;
 525
 526 // if (Pv.new) Rd=memd(Rs+Rt<<#u2)
 527 let AddedComplexity = 15, isPredicated = 1 in
 528 def LDrid_indexed_cdnPt_V4 : LDInst2<(outs DoubleRegs:$dst),
 529                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 530                     "if ($src1.new) $dst=memd($src2+$src3<<#0)",
 531                     []>,
 532                     Requires<[HasV4T]>;
 533
 534 // if (!Pv) Rd=memd(Rs+Rt<<#u2)
 535 let AddedComplexity = 15, isPredicated = 1 in
 536 def LDrid_indexed_cNotPt_V4 : LDInst2<(outs DoubleRegs:$dst),
 537                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 538                     "if (!$src1) $dst=memd($src2+$src3<<#0)",
 539                     []>,
 540                     Requires<[HasV4T]>;
 541
 542 // if (!Pv.new) Rd=memd(Rs+Rt<<#u2)
 543 let AddedComplexity = 15, isPredicated = 1 in
 544 def LDrid_indexed_cdnNotPt_V4 : LDInst2<(outs DoubleRegs:$dst),
 545                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 546                     "if (!$src1.new) $dst=memd($src2+$src3<<#0)",
 547                     []>,
 548                     Requires<[HasV4T]>;
 549
 550 // Rdd=memd(Rt<<#u2+#U6)
 551
 552 //// Load byte.
 553 // Rd=memb(Rs+Rt<<#u2)
 554 let AddedComplexity = 10, isPredicable = 1 in
 555 def LDrib_indexed_V4 : LDInst<(outs IntRegs:$dst),
 556                     (ins IntRegs:$src1, IntRegs:$src2),
 557                     "$dst=memb($src1+$src2<<#0)",
 558                     [(set (i32 IntRegs:$dst),
 559                           (i32 (sextloadi8 (add (i32 IntRegs:$src1),
 560                                                 (i32 IntRegs:$src2)))))]>,
 561                     Requires<[HasV4T]>;
 562
 563 let AddedComplexity = 10, isPredicable = 1 in
 564 def LDriub_indexed_V4 : LDInst<(outs IntRegs:$dst),
 565                     (ins IntRegs:$src1, IntRegs:$src2),
 566                     "$dst=memub($src1+$src2<<#0)",
 567                     [(set (i32 IntRegs:$dst),
 568                           (i32 (zextloadi8 (add (i32 IntRegs:$src1),
 569                                                 (i32 IntRegs:$src2)))))]>,
 570                     Requires<[HasV4T]>;
 571
 572 let AddedComplexity = 10, isPredicable = 1 in
 573 def LDriub_ae_indexed_V4 : LDInst<(outs IntRegs:$dst),
 574                     (ins IntRegs:$src1, IntRegs:$src2),
 575                     "$dst=memub($src1+$src2<<#0)",
 576                     [(set (i32 IntRegs:$dst),
 577                           (i32 (extloadi8 (add (i32 IntRegs:$src1),
 578                                                (i32 IntRegs:$src2)))))]>,
 579                     Requires<[HasV4T]>;
 580
 581 let AddedComplexity = 40, isPredicable = 1 in
 582 def LDriub_ae_indexed_shl_V4 : LDInst<(outs IntRegs:$dst),
 583                     (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$offset),
 584                     "$dst=memub($src1+$src2<<#$offset)",
 585                     [(set (i32 IntRegs:$dst),
 586                           (i32 (extloadi8 (add (i32 IntRegs:$src1),
 587                                                (shl (i32 IntRegs:$src2),
 588                                                     u2ImmPred:$offset)))))]>,
 589                     Requires<[HasV4T]>;
 590
 591 //// Load byte conditionally.
 592 // if ([!]Pv[.new]) Rd=memb(Rs+Rt<<#u2)
 593 // if (Pv) Rd=memb(Rs+Rt<<#u2)
 594 let AddedComplexity = 15, isPredicated = 1 in
 595 def LDrib_indexed_cPt_V4 : LDInst2<(outs IntRegs:$dst),
 596                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 597                     "if ($src1) $dst=memb($src2+$src3<<#0)",
 598                     []>,
 599                     Requires<[HasV4T]>;
 600
 601 // if (Pv.new) Rd=memb(Rs+Rt<<#u2)
 602 let AddedComplexity = 15, isPredicated = 1 in
 603 def LDrib_indexed_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
 604                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 605                     "if ($src1.new) $dst=memb($src2+$src3<<#0)",
 606                     []>,
 607                     Requires<[HasV4T]>;
 608
 609 // if (!Pv) Rd=memb(Rs+Rt<<#u2)
 610 let AddedComplexity = 15, isPredicated = 1 in
 611 def LDrib_indexed_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 612                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 613                     "if (!$src1) $dst=memb($src2+$src3<<#0)",
 614                     []>,
 615                     Requires<[HasV4T]>;
 616
 617 // if (!Pv.new) Rd=memb(Rs+Rt<<#u2)
 618 let AddedComplexity = 15, isPredicated = 1 in
 619 def LDrib_indexed_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 620                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 621                     "if (!$src1.new) $dst=memb($src2+$src3<<#0)",
 622                     []>,
 623                     Requires<[HasV4T]>;
 624
 625 //// Load unsigned byte conditionally.
 626 // if ([!]Pv[.new]) Rd=memub(Rs+Rt<<#u2)
 627 // if (Pv) Rd=memub(Rs+Rt<<#u2)
 628 let AddedComplexity = 15, isPredicated = 1 in
 629 def LDriub_indexed_cPt_V4 : LDInst2<(outs IntRegs:$dst),
 630                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 631                     "if ($src1) $dst=memub($src2+$src3<<#0)",
 632                     []>,
 633                     Requires<[HasV4T]>;
 634
 635 // if (Pv.new) Rd=memub(Rs+Rt<<#u2)
 636 let AddedComplexity = 15, isPredicated = 1 in
 637 def LDriub_indexed_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
 638                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 639                     "if ($src1.new) $dst=memub($src2+$src3<<#0)",
 640                     []>,
 641                     Requires<[HasV4T]>;
 642
 643 // if (!Pv) Rd=memub(Rs+Rt<<#u2)
 644 let AddedComplexity = 15, isPredicated = 1 in
 645 def LDriub_indexed_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 646                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 647                     "if (!$src1) $dst=memub($src2+$src3<<#0)",
 648                     []>,
 649                     Requires<[HasV4T]>;
 650
 651 // if (!Pv.new) Rd=memub(Rs+Rt<<#u2)
 652 let AddedComplexity = 15, isPredicated = 1 in
 653 def LDriub_indexed_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 654                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 655                     "if (!$src1.new) $dst=memub($src2+$src3<<#0)",
 656                     []>,
 657                     Requires<[HasV4T]>;
 658
 659 // Rd=memb(Rt<<#u2+#U6)
 660
 661 //// Load halfword
 662 // Rd=memh(Rs+Rt<<#u2)
 663 let AddedComplexity = 10, isPredicable = 1 in
 664 def LDrih_indexed_V4 : LDInst<(outs IntRegs:$dst),
 665                     (ins IntRegs:$src1, IntRegs:$src2),
 666                     "$dst=memh($src1+$src2<<#0)",
 667                     [(set (i32 IntRegs:$dst),
 668                           (i32 (sextloadi16 (add (i32 IntRegs:$src1),
 669                                                  (i32 IntRegs:$src2)))))]>,
 670                     Requires<[HasV4T]>;
 671
 672 let AddedComplexity = 10, isPredicable = 1 in
 673 def LDriuh_indexed_V4 : LDInst<(outs IntRegs:$dst),
 674                     (ins IntRegs:$src1, IntRegs:$src2),
 675                     "$dst=memuh($src1+$src2<<#0)",
 676                     [(set (i32 IntRegs:$dst),
 677                           (i32 (zextloadi16 (add (i32 IntRegs:$src1),
 678                                                  (i32 IntRegs:$src2)))))]>,
 679                     Requires<[HasV4T]>;
 680
 681 let AddedComplexity = 10, isPredicable = 1 in
 682 def LDriuh_ae_indexed_V4 : LDInst<(outs IntRegs:$dst),
 683                     (ins IntRegs:$src1, IntRegs:$src2),
 684                     "$dst=memuh($src1+$src2<<#0)",
 685                     [(set (i32 IntRegs:$dst),
 686                           (i32 (extloadi16 (add (i32 IntRegs:$src1),
 687                                                 (i32 IntRegs:$src2)))))]>,
 688                     Requires<[HasV4T]>;
 689
 690 let AddedComplexity = 40, isPredicable = 1 in
 691 def LDriuh_ae_indexed_shl_V4 : LDInst<(outs IntRegs:$dst),
 692                     (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$offset),
 693                     "$dst=memuh($src1+$src2<<#$offset)",
 694                     [(set (i32 IntRegs:$dst),
 695                           (i32 (extloadi16 (add (i32 IntRegs:$src1),
 696                                                 (shl (i32 IntRegs:$src2),
 697                                                      u2ImmPred:$offset)))))]>,
 698                     Requires<[HasV4T]>;
 699
 700 //// Load halfword conditionally.
 701 // if ([!]Pv[.new]) Rd=memh(Rs+Rt<<#u2)
 702 // if (Pv) Rd=memh(Rs+Rt<<#u2)
 703 let AddedComplexity = 15, isPredicated = 1 in
 704 def LDrih_indexed_cPt_V4 : LDInst2<(outs IntRegs:$dst),
 705                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 706                     "if ($src1) $dst=memh($src2+$src3<<#0)",
 707                     []>,
 708                     Requires<[HasV4T]>;
 709
 710 // if (Pv.new) Rd=memh(Rs+Rt<<#u2)
 711 let AddedComplexity = 15, isPredicated = 1 in
 712 def LDrih_indexed_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
 713                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 714                     "if ($src1.new) $dst=memh($src2+$src3<<#0)",
 715                     []>,
 716                     Requires<[HasV4T]>;
 717
 718 // if (!Pv) Rd=memh(Rs+Rt<<#u2)
 719 let AddedComplexity = 15, isPredicated = 1 in
 720 def LDrih_indexed_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 721                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 722                     "if (!$src1) $dst=memh($src2+$src3<<#0)",
 723                     []>,
 724                     Requires<[HasV4T]>;
 725
 726 // if (!Pv.new) Rd=memh(Rs+Rt<<#u2)
 727 let AddedComplexity = 15, isPredicated = 1 in
 728 def LDrih_indexed_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 729                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 730                     "if (!$src1.new) $dst=memh($src2+$src3<<#0)",
 731                     []>,
 732                     Requires<[HasV4T]>;
 733
 734 //// Load unsigned halfword conditionally.
 735 // if ([!]Pv[.new]) Rd=memuh(Rs+Rt<<#u2)
 736 // if (Pv) Rd=memuh(Rs+Rt<<#u2)
 737 let AddedComplexity = 15, isPredicated = 1 in
 738 def LDriuh_indexed_cPt_V4 : LDInst2<(outs IntRegs:$dst),
 739                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 740                     "if ($src1) $dst=memuh($src2+$src3<<#0)",
 741                     []>,
 742                     Requires<[HasV4T]>;
 743
 744 // if (Pv.new) Rd=memuh(Rs+Rt<<#u2)
 745 let AddedComplexity = 15, isPredicated = 1 in
 746 def LDriuh_indexed_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
 747                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 748                     "if ($src1.new) $dst=memuh($src2+$src3<<#0)",
 749                     []>,
 750                     Requires<[HasV4T]>;
 751
 752 // if (!Pv) Rd=memuh(Rs+Rt<<#u2)
 753 let AddedComplexity = 15, isPredicated = 1 in
 754 def LDriuh_indexed_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 755                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 756                     "if (!$src1) $dst=memuh($src2+$src3<<#0)",
 757                     []>,
 758                     Requires<[HasV4T]>;
 759
 760 // if (!Pv.new) Rd=memuh(Rs+Rt<<#u2)
 761 let AddedComplexity = 15, isPredicated = 1 in
 762 def LDriuh_indexed_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 763                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 764                     "if (!$src1.new) $dst=memuh($src2+$src3<<#0)",
 765                     []>,
 766                     Requires<[HasV4T]>;
 767
 768 // Rd=memh(Rt<<#u2+#U6)
 769
 770 //// Load word.
 771 // Load predicate: Fix for bug 5279.
 772 let neverHasSideEffects = 1 in
 773 def LDriw_pred_V4 : LDInst2<(outs PredRegs:$dst),
 774             (ins MEMri:$addr),
 775             "Error; should not emit",
 776             []>,
 777             Requires<[HasV4T]>;
 778
 779 // Rd=memw(Re=#U6)
 780
 781 // Rd=memw(Rs+Rt<<#u2)
 782 let AddedComplexity = 10, isPredicable = 1 in
 783 def LDriw_indexed_V4 : LDInst<(outs IntRegs:$dst),
 784                     (ins IntRegs:$src1, IntRegs:$src2),
 785                     "$dst=memw($src1+$src2<<#0)",
 786                     [(set (i32 IntRegs:$dst),
 787                           (i32 (load (add (i32 IntRegs:$src1),
 788                                           (i32 IntRegs:$src2)))))]>,
 789                     Requires<[HasV4T]>;
 790
 791 //// Load word conditionally.
 792 // if ([!]Pv[.new]) Rd=memw(Rs+Rt<<#u2)
 793 // if (Pv) Rd=memw(Rs+Rt<<#u2)
 794 let AddedComplexity = 15, isPredicated = 1 in
 795 def LDriw_indexed_cPt_V4 : LDInst2<(outs IntRegs:$dst),
 796                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 797                     "if ($src1) $dst=memw($src2+$src3<<#0)",
 798                     []>,
 799                     Requires<[HasV4T]>;
 800
 801 // if (Pv.new) Rd=memh(Rs+Rt<<#u2)
 802 let AddedComplexity = 15, isPredicated = 1 in
 803 def LDriw_indexed_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
 804                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 805                     "if ($src1.new) $dst=memw($src2+$src3<<#0)",
 806                     []>,
 807                     Requires<[HasV4T]>;
 808
 809 // if (!Pv) Rd=memh(Rs+Rt<<#u2)
 810 let AddedComplexity = 15, isPredicated = 1 in
 811 def LDriw_indexed_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 812                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 813                     "if (!$src1) $dst=memw($src2+$src3<<#0)",
 814                     []>,
 815                     Requires<[HasV4T]>;
 816
 817 // if (!Pv.new) Rd=memh(Rs+Rt<<#u2)
 818 let AddedComplexity = 15, isPredicated = 1 in
 819 def LDriw_indexed_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 820                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 821                     "if (!$src1.new) $dst=memw($src2+$src3<<#0)",
 822                     []>,
 823                     Requires<[HasV4T]>;
 824
 825 /// Load from global offset
 826
 827 let isPredicable = 1, neverHasSideEffects = 1 in
 828 def LDrid_GP_V4 : LDInst2<(outs DoubleRegs:$dst),
 829             (ins globaladdress:$global, u16Imm:$offset),
 830             "$dst=memd(#$global+$offset)",
 831             []>,
 832             Requires<[HasV4T]>;
 833
 834 let neverHasSideEffects = 1, isPredicated = 1 in
 835 def LDrid_GP_cPt_V4 : LDInst2<(outs DoubleRegs:$dst),
 836             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 837             "if ($src1) $dst=memd(##$global+$offset)",
 838             []>,
 839             Requires<[HasV4T]>;
 840
 841 let neverHasSideEffects = 1, isPredicated = 1 in
 842 def LDrid_GP_cNotPt_V4 : LDInst2<(outs DoubleRegs:$dst),
 843             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 844             "if (!$src1) $dst=memd(##$global+$offset)",
 845             []>,
 846             Requires<[HasV4T]>;
 847
 848 let neverHasSideEffects = 1, isPredicated = 1 in
 849 def LDrid_GP_cdnPt_V4 : LDInst2<(outs DoubleRegs:$dst),
 850             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 851             "if ($src1.new) $dst=memd(##$global+$offset)",
 852             []>,
 853             Requires<[HasV4T]>;
 854
 855 let neverHasSideEffects = 1, isPredicated = 1 in
 856 def LDrid_GP_cdnNotPt_V4 : LDInst2<(outs DoubleRegs:$dst),
 857             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 858             "if (!$src1.new) $dst=memd(##$global+$offset)",
 859             []>,
 860             Requires<[HasV4T]>;
 861
 862 let isPredicable = 1, neverHasSideEffects = 1 in
 863 def LDrib_GP_V4 : LDInst2<(outs IntRegs:$dst),
 864             (ins globaladdress:$global, u16Imm:$offset),
 865             "$dst=memb(#$global+$offset)",
 866             []>,
 867             Requires<[HasV4T]>;
 868
 869 let neverHasSideEffects = 1, isPredicated = 1 in
 870 def LDrib_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst),
 871             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 872             "if ($src1) $dst=memb(##$global+$offset)",
 873             []>,
 874             Requires<[HasV4T]>;
 875
 876 let neverHasSideEffects = 1, isPredicated = 1 in
 877 def LDrib_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 878             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 879             "if (!$src1) $dst=memb(##$global+$offset)",
 880             []>,
 881             Requires<[HasV4T]>;
 882
 883 let neverHasSideEffects = 1, isPredicated = 1 in
 884 def LDrib_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
 885             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 886             "if ($src1.new) $dst=memb(##$global+$offset)",
 887             []>,
 888             Requires<[HasV4T]>;
 889
 890 let neverHasSideEffects = 1, isPredicated = 1 in
 891 def LDrib_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 892             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 893             "if (!$src1.new) $dst=memb(##$global+$offset)",
 894             []>,
 895             Requires<[HasV4T]>;
 896
 897
 898 let isPredicable = 1, neverHasSideEffects = 1 in
 899 def LDriub_GP_V4 : LDInst2<(outs IntRegs:$dst),
 900             (ins globaladdress:$global, u16Imm:$offset),
 901             "$dst=memub(#$global+$offset)",
 902             []>,
 903             Requires<[HasV4T]>;
 904
 905
 906 let neverHasSideEffects = 1, isPredicated = 1 in
 907 def LDriub_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst),
 908             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 909             "if ($src1) $dst=memub(##$global+$offset)",
 910             []>,
 911             Requires<[HasV4T]>;
 912
 913 let neverHasSideEffects = 1, isPredicated = 1 in
 914 def LDriub_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 915             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 916             "if (!$src1) $dst=memub(##$global+$offset)",
 917             []>,
 918             Requires<[HasV4T]>;
 919
 920 let neverHasSideEffects = 1, isPredicated = 1 in
 921 def LDriub_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
 922             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 923             "if ($src1.new) $dst=memub(##$global+$offset)",
 924             []>,
 925             Requires<[HasV4T]>;
 926
 927 let neverHasSideEffects = 1, isPredicated = 1 in
 928 def LDriub_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 929             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 930             "if (!$src1.new) $dst=memub(##$global+$offset)",
 931             []>,
 932             Requires<[HasV4T]>;
 933
 934
 935 let isPredicable = 1, neverHasSideEffects = 1 in
 936 def LDrih_GP_V4 : LDInst2<(outs IntRegs:$dst),
 937             (ins globaladdress:$global, u16Imm:$offset),
 938             "$dst=memh(#$global+$offset)",
 939             []>,
 940             Requires<[HasV4T]>;
 941
 942
 943 let neverHasSideEffects = 1, isPredicated = 1 in
 944 def LDrih_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst),
 945             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 946             "if ($src1) $dst=memh(##$global+$offset)",
 947             []>,
 948             Requires<[HasV4T]>;
 949
 950 let neverHasSideEffects = 1, isPredicated = 1 in
 951 def LDrih_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 952             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 953             "if (!$src1) $dst=memh(##$global+$offset)",
 954             []>,
 955             Requires<[HasV4T]>;
 956
 957 let neverHasSideEffects = 1, isPredicated = 1 in
 958 def LDrih_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
 959             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 960             "if ($src1.new) $dst=memh(##$global+$offset)",
 961             []>,
 962             Requires<[HasV4T]>;
 963
 964 let neverHasSideEffects = 1, isPredicated = 1 in
 965 def LDrih_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 966             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 967             "if (!$src1.new) $dst=memh(##$global+$offset)",
 968             []>,
 969             Requires<[HasV4T]>;
 970
 971
 972 let isPredicable = 1, neverHasSideEffects = 1 in
 973 def LDriuh_GP_V4 : LDInst2<(outs IntRegs:$dst),
 974             (ins globaladdress:$global, u16Imm:$offset),
 975             "$dst=memuh(#$global+$offset)",
 976             []>,
 977             Requires<[HasV4T]>;
 978
 979 let neverHasSideEffects = 1, isPredicated = 1 in
 980 def LDriuh_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst),
 981             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 982             "if ($src1) $dst=memuh(##$global+$offset)",
 983             []>,
 984             Requires<[HasV4T]>;
 985
 986 let neverHasSideEffects = 1, isPredicated = 1 in
 987 def LDriuh_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 988             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 989             "if (!$src1) $dst=memuh(##$global+$offset)",
 990             []>,
 991             Requires<[HasV4T]>;
 992
 993 let neverHasSideEffects = 1, isPredicated = 1 in
 994 def LDriuh_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
 995             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 996             "if ($src1.new) $dst=memuh(##$global+$offset)",
 997             []>,
 998             Requires<[HasV4T]>;
 999
1000 let neverHasSideEffects = 1, isPredicated = 1 in
1001 def LDriuh_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1002             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
1003             "if (!$src1.new) $dst=memuh(##$global+$offset)",
1004             []>,
1005             Requires<[HasV4T]>;
1006
1007 let isPredicable = 1, neverHasSideEffects = 1 in
1008 def LDriw_GP_V4 : LDInst2<(outs IntRegs:$dst),
1009             (ins globaladdress:$global, u16Imm:$offset),
1010             "$dst=memw(#$global+$offset)",
1011             []>,
1012             Requires<[HasV4T]>;
1013
1014
1015 let neverHasSideEffects = 1, isPredicated = 1 in
1016 def LDriw_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst),
1017             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
1018             "if ($src1) $dst=memw(##$global+$offset)",
1019             []>,
1020             Requires<[HasV4T]>;
1021
1022 let neverHasSideEffects = 1, isPredicated = 1 in
1023 def LDriw_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1024             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
1025             "if (!$src1) $dst=memw(##$global+$offset)",
1026             []>,
1027             Requires<[HasV4T]>;
1028
1029
1030 let neverHasSideEffects = 1, isPredicated = 1 in
1031 def LDriw_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
1032             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
1033             "if ($src1.new) $dst=memw(##$global+$offset)",
1034             []>,
1035             Requires<[HasV4T]>;
1036
1037 let neverHasSideEffects = 1, isPredicated = 1 in
1038 def LDriw_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1039             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
1040             "if (!$src1.new) $dst=memw(##$global+$offset)",
1041             []>,
1042             Requires<[HasV4T]>;
1043
1044
1045 let isPredicable = 1, neverHasSideEffects = 1 in
1046 def LDd_GP_V4 : LDInst2<(outs DoubleRegs:$dst),
1047             (ins globaladdress:$global),
1048             "$dst=memd(#$global)",
1049             []>,
1050             Requires<[HasV4T]>;
1051
1052 // if (Pv) Rtt=memd(##global)
1053 let neverHasSideEffects = 1, isPredicated = 1 in
1054 def LDd_GP_cPt_V4 : LDInst2<(outs DoubleRegs:$dst),
1055             (ins PredRegs:$src1, globaladdress:$global),
1056             "if ($src1) $dst=memd(##$global)",
1057             []>,
1058             Requires<[HasV4T]>;
1059
1060
1061 // if (!Pv) Rtt=memd(##global)
1062 let neverHasSideEffects = 1, isPredicated = 1 in
1063 def LDd_GP_cNotPt_V4 : LDInst2<(outs DoubleRegs:$dst),
1064             (ins PredRegs:$src1, globaladdress:$global),
1065             "if (!$src1) $dst=memd(##$global)",
1066             []>,
1067             Requires<[HasV4T]>;
1068
1069 // if (Pv) Rtt=memd(##global)
1070 let neverHasSideEffects = 1, isPredicated = 1 in
1071 def LDd_GP_cdnPt_V4 : LDInst2<(outs DoubleRegs:$dst),
1072             (ins PredRegs:$src1, globaladdress:$global),
1073             "if ($src1.new) $dst=memd(##$global)",
1074             []>,
1075             Requires<[HasV4T]>;
1076
1077
1078 // if (!Pv) Rtt=memd(##global)
1079 let neverHasSideEffects = 1, isPredicated = 1 in
1080 def LDd_GP_cdnNotPt_V4 : LDInst2<(outs DoubleRegs:$dst),
1081             (ins PredRegs:$src1, globaladdress:$global),
1082             "if (!$src1.new) $dst=memd(##$global)",
1083             []>,
1084             Requires<[HasV4T]>;
1085
1086 let isPredicable = 1, neverHasSideEffects = 1 in
1087 def LDb_GP_V4 : LDInst2<(outs IntRegs:$dst),
1088             (ins globaladdress:$global),
1089             "$dst=memb(#$global)",
1090             []>,
1091             Requires<[HasV4T]>;
1092
1093 // if (Pv) Rt=memb(##global)
1094 let neverHasSideEffects = 1, isPredicated = 1 in
1095 def LDb_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst),
1096             (ins PredRegs:$src1, globaladdress:$global),
1097             "if ($src1) $dst=memb(##$global)",
1098             []>,
1099             Requires<[HasV4T]>;
1100
1101 // if (!Pv) Rt=memb(##global)
1102 let neverHasSideEffects = 1, isPredicated = 1 in
1103 def LDb_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1104             (ins PredRegs:$src1, globaladdress:$global),
1105             "if (!$src1) $dst=memb(##$global)",
1106             []>,
1107             Requires<[HasV4T]>;
1108
1109 // if (Pv) Rt=memb(##global)
1110 let neverHasSideEffects = 1, isPredicated = 1 in
1111 def LDb_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
1112             (ins PredRegs:$src1, globaladdress:$global),
1113             "if ($src1.new) $dst=memb(##$global)",
1114             []>,
1115             Requires<[HasV4T]>;
1116
1117 // if (!Pv) Rt=memb(##global)
1118 let neverHasSideEffects = 1, isPredicated = 1 in
1119 def LDb_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1120             (ins PredRegs:$src1, globaladdress:$global),
1121             "if (!$src1.new) $dst=memb(##$global)",
1122             []>,
1123             Requires<[HasV4T]>;
1124
1125 let isPredicable = 1, neverHasSideEffects = 1 in
1126 def LDub_GP_V4 : LDInst2<(outs IntRegs:$dst),
1127             (ins globaladdress:$global),
1128             "$dst=memub(#$global)",
1129             []>,
1130             Requires<[HasV4T]>;
1131
1132 // if (Pv) Rt=memub(##global)
1133 let neverHasSideEffects = 1, isPredicated = 1 in
1134 def LDub_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst),
1135             (ins PredRegs:$src1, globaladdress:$global),
1136             "if ($src1) $dst=memub(##$global)",
1137             []>,
1138             Requires<[HasV4T]>;
1139
1140
1141 // if (!Pv) Rt=memub(##global)
1142 let neverHasSideEffects = 1, isPredicated = 1 in
1143 def LDub_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1144             (ins PredRegs:$src1, globaladdress:$global),
1145             "if (!$src1) $dst=memub(##$global)",
1146             []>,
1147             Requires<[HasV4T]>;
1148
1149 // if (Pv) Rt=memub(##global)
1150 let neverHasSideEffects = 1, isPredicated = 1 in
1151 def LDub_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
1152             (ins PredRegs:$src1, globaladdress:$global),
1153             "if ($src1.new) $dst=memub(##$global)",
1154             []>,
1155             Requires<[HasV4T]>;
1156
1157
1158 // if (!Pv) Rt=memub(##global)
1159 let neverHasSideEffects = 1, isPredicated = 1 in
1160 def LDub_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1161             (ins PredRegs:$src1, globaladdress:$global),
1162             "if (!$src1.new) $dst=memub(##$global)",
1163             []>,
1164             Requires<[HasV4T]>;
1165
1166 let isPredicable = 1, neverHasSideEffects = 1 in
1167 def LDh_GP_V4 : LDInst2<(outs IntRegs:$dst),
1168             (ins globaladdress:$global),
1169             "$dst=memh(#$global)",
1170             []>,
1171             Requires<[HasV4T]>;
1172
1173 // if (Pv) Rt=memh(##global)
1174 let neverHasSideEffects = 1, isPredicated = 1 in
1175 def LDh_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst),
1176             (ins PredRegs:$src1, globaladdress:$global),
1177             "if ($src1) $dst=memh(##$global)",
1178             []>,
1179             Requires<[HasV4T]>;
1180
1181 // if (!Pv) Rt=memh(##global)
1182 let neverHasSideEffects = 1, isPredicated = 1 in
1183 def LDh_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1184             (ins PredRegs:$src1, globaladdress:$global),
1185             "if (!$src1) $dst=memh(##$global)",
1186             []>,
1187             Requires<[HasV4T]>;
1188
1189 // if (Pv) Rt=memh(##global)
1190 let neverHasSideEffects = 1, isPredicated = 1 in
1191 def LDh_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
1192             (ins PredRegs:$src1, globaladdress:$global),
1193             "if ($src1.new) $dst=memh(##$global)",
1194             []>,
1195             Requires<[HasV4T]>;
1196
1197 // if (!Pv) Rt=memh(##global)
1198 let neverHasSideEffects = 1, isPredicated = 1 in
1199 def LDh_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1200             (ins PredRegs:$src1, globaladdress:$global),
1201             "if (!$src1.new) $dst=memh(##$global)",
1202             []>,
1203             Requires<[HasV4T]>;
1204
1205 let isPredicable = 1, neverHasSideEffects = 1 in
1206 def LDuh_GP_V4 : LDInst2<(outs IntRegs:$dst),
1207             (ins globaladdress:$global),
1208             "$dst=memuh(#$global)",
1209             []>,
1210             Requires<[HasV4T]>;
1211
1212 // if (Pv) Rt=memuh(##global)
1213 let neverHasSideEffects = 1, isPredicated = 1 in
1214 def LDuh_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst),
1215             (ins PredRegs:$src1, globaladdress:$global),
1216             "if ($src1) $dst=memuh(##$global)",
1217             []>,
1218             Requires<[HasV4T]>;
1219
1220 // if (!Pv) Rt=memuh(##global)
1221 let neverHasSideEffects = 1, isPredicated = 1 in
1222 def LDuh_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1223             (ins PredRegs:$src1, globaladdress:$global),
1224             "if (!$src1) $dst=memuh(##$global)",
1225             []>,
1226             Requires<[HasV4T]>;
1227
1228 // if (Pv) Rt=memuh(##global)
1229 let neverHasSideEffects = 1, isPredicated = 1 in
1230 def LDuh_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
1231             (ins PredRegs:$src1, globaladdress:$global),
1232             "if ($src1.new) $dst=memuh(##$global)",
1233             []>,
1234             Requires<[HasV4T]>;
1235
1236 // if (!Pv) Rt=memuh(##global)
1237 let neverHasSideEffects = 1, isPredicated = 1 in
1238 def LDuh_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1239             (ins PredRegs:$src1, globaladdress:$global),
1240             "if (!$src1.new) $dst=memuh(##$global)",
1241             []>,
1242             Requires<[HasV4T]>;
1243
1244 let isPredicable = 1, neverHasSideEffects = 1 in
1245 def LDw_GP_V4 : LDInst2<(outs IntRegs:$dst),
1246             (ins globaladdress:$global),
1247             "$dst=memw(#$global)",
1248             []>,
1249             Requires<[HasV4T]>;
1250
1251 // if (Pv) Rt=memw(##global)
1252 let neverHasSideEffects = 1, isPredicated = 1 in
1253 def LDw_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst),
1254             (ins PredRegs:$src1, globaladdress:$global),
1255             "if ($src1) $dst=memw(##$global)",
1256             []>,
1257             Requires<[HasV4T]>;
1258
1259
1260 // if (!Pv) Rt=memw(##global)
1261 let neverHasSideEffects = 1, isPredicated = 1 in
1262 def LDw_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1263             (ins PredRegs:$src1, globaladdress:$global),
1264             "if (!$src1) $dst=memw(##$global)",
1265             []>,
1266             Requires<[HasV4T]>;
1267
1268 // if (Pv) Rt=memw(##global)
1269 let neverHasSideEffects = 1, isPredicated = 1 in
1270 def LDw_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
1271             (ins PredRegs:$src1, globaladdress:$global),
1272             "if ($src1.new) $dst=memw(##$global)",
1273             []>,
1274             Requires<[HasV4T]>;
1275
1276
1277 // if (!Pv) Rt=memw(##global)
1278 let neverHasSideEffects = 1, isPredicated = 1 in
1279 def LDw_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1280             (ins PredRegs:$src1, globaladdress:$global),
1281             "if (!$src1.new) $dst=memw(##$global)",
1282             []>,
1283             Requires<[HasV4T]>;
1284
1285
1286
1287 def : Pat <(atomic_load_64 (HexagonCONST32_GP tglobaladdr:$global)),
1288            (i64 (LDd_GP_V4 tglobaladdr:$global))>,
1289             Requires<[HasV4T]>;
1290
1291 def : Pat <(atomic_load_32 (HexagonCONST32_GP tglobaladdr:$global)),
1292            (i32 (LDw_GP_V4 tglobaladdr:$global))>,
1293             Requires<[HasV4T]>;
1294
1295 def : Pat <(atomic_load_16 (HexagonCONST32_GP tglobaladdr:$global)),
1296            (i32 (LDuh_GP_V4 tglobaladdr:$global))>,
1297             Requires<[HasV4T]>;
1298
1299 def : Pat <(atomic_load_8 (HexagonCONST32_GP tglobaladdr:$global)),
1300            (i32 (LDub_GP_V4 tglobaladdr:$global))>,
1301             Requires<[HasV4T]>;
1302
1303 // Map from load(globaladdress) -> memw(#foo + 0)
1304 let AddedComplexity = 100 in
1305 def : Pat <(i64 (load (HexagonCONST32_GP tglobaladdr:$global))),
1306            (i64 (LDd_GP_V4 tglobaladdr:$global))>,
1307             Requires<[HasV4T]>;
1308
1309 // Map from Pd = load(globaladdress) -> Rd = memb(globaladdress), Pd = Rd
1310 let AddedComplexity = 100 in
1311 def : Pat <(i1 (load (HexagonCONST32_GP tglobaladdr:$global))),
1312            (i1 (TFR_PdRs (i32 (LDb_GP_V4 tglobaladdr:$global))))>,
1313            Requires<[HasV4T]>;
1314
1315 // When the Interprocedural Global Variable optimizer realizes that a certain
1316 // global variable takes only two constant values, it shrinks the global to
1317 // a boolean. Catch those loads here in the following 3 patterns.
1318 let AddedComplexity = 100 in
1319 def : Pat <(i32 (extloadi1 (HexagonCONST32_GP tglobaladdr:$global))),
1320            (i32 (LDb_GP_V4 tglobaladdr:$global))>,
1321             Requires<[HasV4T]>;
1322
1323 let AddedComplexity = 100 in
1324 def : Pat <(i32 (sextloadi1 (HexagonCONST32_GP tglobaladdr:$global))),
1325            (i32 (LDb_GP_V4 tglobaladdr:$global))>,
1326             Requires<[HasV4T]>;
1327
1328 // Map from load(globaladdress) -> memb(#foo)
1329 let AddedComplexity = 100 in
1330 def : Pat <(i32 (extloadi8 (HexagonCONST32_GP tglobaladdr:$global))),
1331            (i32 (LDb_GP_V4 tglobaladdr:$global))>,
1332             Requires<[HasV4T]>;
1333
1334 // Map from load(globaladdress) -> memb(#foo)
1335 let AddedComplexity = 100 in
1336 def : Pat <(i32 (sextloadi8 (HexagonCONST32_GP tglobaladdr:$global))),
1337            (i32 (LDb_GP_V4 tglobaladdr:$global))>,
1338             Requires<[HasV4T]>;
1339
1340 let AddedComplexity = 100 in
1341 def : Pat <(i32 (zextloadi1 (HexagonCONST32_GP tglobaladdr:$global))),
1342            (i32 (LDub_GP_V4 tglobaladdr:$global))>,
1343             Requires<[HasV4T]>;
1344
1345 // Map from load(globaladdress) -> memub(#foo)
1346 let AddedComplexity = 100 in
1347 def : Pat <(i32 (zextloadi8 (HexagonCONST32_GP tglobaladdr:$global))),
1348            (i32 (LDub_GP_V4 tglobaladdr:$global))>,
1349             Requires<[HasV4T]>;
1350
1351 // Map from load(globaladdress) -> memh(#foo)
1352 let AddedComplexity = 100 in
1353 def : Pat <(i32 (extloadi16 (HexagonCONST32_GP tglobaladdr:$global))),
1354            (i32 (LDh_GP_V4 tglobaladdr:$global))>,
1355             Requires<[HasV4T]>;
1356
1357 // Map from load(globaladdress) -> memh(#foo)
1358 let AddedComplexity = 100 in
1359 def : Pat <(i32 (sextloadi16 (HexagonCONST32_GP tglobaladdr:$global))),
1360            (i32 (LDh_GP_V4 tglobaladdr:$global))>,
1361             Requires<[HasV4T]>;
1362
1363 // Map from load(globaladdress) -> memuh(#foo)
1364 let AddedComplexity = 100 in
1365 def : Pat <(i32 (zextloadi16 (HexagonCONST32_GP tglobaladdr:$global))),
1366            (i32 (LDuh_GP_V4 tglobaladdr:$global))>,
1367             Requires<[HasV4T]>;
1368
1369 // Map from load(globaladdress) -> memw(#foo)
1370 let AddedComplexity = 100 in
1371 def : Pat <(i32 (load (HexagonCONST32_GP tglobaladdr:$global))),
1372            (i32 (LDw_GP_V4 tglobaladdr:$global))>,
1373             Requires<[HasV4T]>;
1374
1375 def : Pat <(atomic_load_64 (add (HexagonCONST32_GP tglobaladdr:$global),
1376                                 u16ImmPred:$offset)),
1377            (i64 (LDrid_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
1378            Requires<[HasV4T]>;
1379
1380 def : Pat <(atomic_load_32 (add (HexagonCONST32_GP tglobaladdr:$global),
1381                                 u16ImmPred:$offset)),
1382            (i32 (LDriw_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
1383             Requires<[HasV4T]>;
1384
1385 def : Pat <(atomic_load_16 (add (HexagonCONST32_GP tglobaladdr:$global),
1386                                 u16ImmPred:$offset)),
1387            (i32 (LDriuh_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
1388             Requires<[HasV4T]>;
1389
1390 def : Pat <(atomic_load_8 (add (HexagonCONST32_GP tglobaladdr:$global),
1391                                u16ImmPred:$offset)),
1392            (i32 (LDriub_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
1393            Requires<[HasV4T]>;
1394
1395 // Map from load(globaladdress + x) -> memd(#foo + x)
1396 let AddedComplexity = 100 in
1397 def : Pat <(i64 (load (add (HexagonCONST32_GP tglobaladdr:$global),
1398                            u16ImmPred:$offset))),
1399            (i64 (LDrid_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
1400            Requires<[HasV4T]>;
1401
1402 // Map from load(globaladdress + x) -> memb(#foo + x)
1403 let AddedComplexity = 100 in
1404 def : Pat <(i32 (extloadi8 (add (HexagonCONST32_GP tglobaladdr:$global),
1405                            u16ImmPred:$offset))),
1406            (i32 (LDrib_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
1407            Requires<[HasV4T]>;
1408
1409 // Map from load(globaladdress + x) -> memb(#foo + x)
1410 let AddedComplexity = 100 in
1411 def : Pat <(i32 (sextloadi8 (add (HexagonCONST32_GP tglobaladdr:$global),
1412                             u16ImmPred:$offset))),
1413            (i32 (LDrib_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
1414            Requires<[HasV4T]>;
1415
1416 // Map from load(globaladdress + x) -> memub(#foo + x)
1417 let AddedComplexity = 100 in
1418 def : Pat <(i32 (zextloadi8 (add (HexagonCONST32_GP tglobaladdr:$global),
1419                             u16ImmPred:$offset))),
1420            (i32 (LDriub_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
1421            Requires<[HasV4T]>;
1422
1423 // Map from load(globaladdress + x) -> memuh(#foo + x)
1424 let AddedComplexity = 100 in
1425 def : Pat <(i32 (extloadi16 (add (HexagonCONST32_GP tglobaladdr:$global),
1426                             u16ImmPred:$offset))),
1427            (i32 (LDrih_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
1428             Requires<[HasV4T]>;
1429
1430 // Map from load(globaladdress + x) -> memh(#foo + x)
1431 let AddedComplexity = 100 in
1432 def : Pat <(i32 (sextloadi16 (add (HexagonCONST32_GP tglobaladdr:$global),
1433                              u16ImmPred:$offset))),
1434            (i32 (LDrih_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
1435            Requires<[HasV4T]>;
1436
1437
1438 // Map from load(globaladdress + x) -> memuh(#foo + x)
1439 let AddedComplexity = 100 in
1440 def : Pat <(i32 (zextloadi16 (add (HexagonCONST32_GP tglobaladdr:$global),
1441                              u16ImmPred:$offset))),
1442            (i32 (LDriuh_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
1443             Requires<[HasV4T]>;
1444
1445 // Map from load(globaladdress + x) -> memw(#foo + x)
1446 let AddedComplexity = 100 in
1447 def : Pat <(i32 (load (add (HexagonCONST32_GP tglobaladdr:$global),
1448                       u16ImmPred:$offset))),
1449            (i32 (LDriw_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
1450             Requires<[HasV4T]>;
1451
1452
1453 //===----------------------------------------------------------------------===//
1454 // LD -
1455 //===----------------------------------------------------------------------===//
1456
1457 //===----------------------------------------------------------------------===//
1458 // ST +
1459 //===----------------------------------------------------------------------===//
1460 ///
1461 /// Assumptions::: ****** DO NOT IGNORE ********
1462 /// 1. Make sure that in post increment store, the zero'th operand is always the
1463 ///    post increment operand.
1464 /// 2. Make sure that the store value operand(Rt/Rtt) in a store is always the
1465 ///    last operand.
1466 ///
1467
1468 // memd(Re=#U6)=Rtt
1469 def STrid_abs_setimm_V4 : STInst2<(outs IntRegs:$dst1),
1470             (ins DoubleRegs:$src1, u6Imm:$src2),
1471             "memd($dst1=#$src2) = $src1",
1472             []>,
1473             Requires<[HasV4T]>;
1474
1475 // memb(Re=#U6)=Rs
1476 def STrib_abs_setimm_V4 : STInst2<(outs IntRegs:$dst1),
1477             (ins IntRegs:$src1, u6Imm:$src2),
1478             "memb($dst1=#$src2) = $src1",
1479             []>,
1480             Requires<[HasV4T]>;
1481
1482 // memh(Re=#U6)=Rs
1483 def STrih_abs_setimm_V4 : STInst2<(outs IntRegs:$dst1),
1484             (ins IntRegs:$src1, u6Imm:$src2),
1485             "memh($dst1=#$src2) = $src1",
1486             []>,
1487             Requires<[HasV4T]>;
1488
1489 // memw(Re=#U6)=Rs
1490 def STriw_abs_setimm_V4 : STInst2<(outs IntRegs:$dst1),
1491             (ins IntRegs:$src1, u6Imm:$src2),
1492             "memw($dst1=#$src2) = $src1",
1493             []>,
1494             Requires<[HasV4T]>;
1495
1496 // memd(Re=#U6)=Rtt
1497 def STrid_abs_set_V4 : STInst2<(outs IntRegs:$dst1),
1498             (ins DoubleRegs:$src1, globaladdress:$src2),
1499             "memd($dst1=##$src2) = $src1",
1500             []>,
1501             Requires<[HasV4T]>;
1502
1503 // memb(Re=#U6)=Rs
1504 def STrib_abs_set_V4 : STInst2<(outs IntRegs:$dst1),
1505             (ins IntRegs:$src1, globaladdress:$src2),
1506             "memb($dst1=##$src2) = $src1",
1507             []>,
1508             Requires<[HasV4T]>;
1509
1510 // memh(Re=#U6)=Rs
1511 def STrih_abs_set_V4 : STInst2<(outs IntRegs:$dst1),
1512             (ins IntRegs:$src1, globaladdress:$src2),
1513             "memh($dst1=##$src2) = $src1",
1514             []>,
1515             Requires<[HasV4T]>;
1516
1517 // memw(Re=#U6)=Rs
1518 def STriw_abs_set_V4 : STInst2<(outs IntRegs:$dst1),
1519             (ins IntRegs:$src1, globaladdress:$src2),
1520             "memw($dst1=##$src2) = $src1",
1521             []>,
1522             Requires<[HasV4T]>;
1523
1524 // memd(Rs+Ru<<#u2)=Rtt
1525 let AddedComplexity = 10, isPredicable = 1 in
1526 def STrid_indexed_shl_V4 : STInst<(outs),
1527             (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$src3, DoubleRegs:$src4),
1528             "memd($src1+$src2<<#$src3) = $src4",
1529             [(store (i64 DoubleRegs:$src4),
1530                     (add (i32 IntRegs:$src1),
1531                          (shl (i32 IntRegs:$src2), u2ImmPred:$src3)))]>,
1532             Requires<[HasV4T]>;
1533
1534 // memd(Ru<<#u2+#U6)=Rtt
1535 let AddedComplexity = 10 in
1536 def STrid_shl_V4 : STInst<(outs),
1537             (ins IntRegs:$src1, u2Imm:$src2, u6Imm:$src3, DoubleRegs:$src4),
1538             "memd($src1<<#$src2+#$src3) = $src4",
1539             [(store (i64 DoubleRegs:$src4),
1540                     (add (shl (i32 IntRegs:$src1), u2ImmPred:$src2),
1541                          u6ImmPred:$src3))]>,
1542             Requires<[HasV4T]>;
1543
1544 // memd(Rx++#s4:3)=Rtt
1545 // memd(Rx++#s4:3:circ(Mu))=Rtt
1546 // memd(Rx++I:circ(Mu))=Rtt
1547 // memd(Rx++Mu)=Rtt
1548 // memd(Rx++Mu:brev)=Rtt
1549 // memd(gp+#u16:3)=Rtt
1550
1551 // Store doubleword conditionally.
1552 // if ([!]Pv[.new]) memd(#u6)=Rtt
1553 // TODO: needs to be implemented.
1554
1555 // if ([!]Pv[.new]) memd(Rs+#u6:3)=Rtt
1556 // if (Pv) memd(Rs+#u6:3)=Rtt
1557 // if (Pv.new) memd(Rs+#u6:3)=Rtt
1558 let AddedComplexity = 10, neverHasSideEffects = 1,
1559     isPredicated = 1 in
1560 def STrid_cdnPt_V4 : STInst2<(outs),
1561             (ins PredRegs:$src1, MEMri:$addr, DoubleRegs:$src2),
1562             "if ($src1.new) memd($addr) = $src2",
1563             []>,
1564             Requires<[HasV4T]>;
1565
1566 // if (!Pv) memd(Rs+#u6:3)=Rtt
1567 // if (!Pv.new) memd(Rs+#u6:3)=Rtt
1568 let AddedComplexity = 10, neverHasSideEffects = 1,
1569     isPredicated = 1 in
1570 def STrid_cdnNotPt_V4 : STInst2<(outs),
1571             (ins PredRegs:$src1, MEMri:$addr, DoubleRegs:$src2),
1572             "if (!$src1.new) memd($addr) = $src2",
1573             []>,
1574             Requires<[HasV4T]>;
1575
1576 // if (Pv) memd(Rs+#u6:3)=Rtt
1577 // if (Pv.new) memd(Rs+#u6:3)=Rtt
1578 let AddedComplexity = 10, neverHasSideEffects = 1,
1579     isPredicated = 1 in
1580 def STrid_indexed_cdnPt_V4 : STInst2<(outs),
1581             (ins PredRegs:$src1, IntRegs:$src2, u6_3Imm:$src3,
1582                  DoubleRegs:$src4),
1583             "if ($src1.new) memd($src2+#$src3) = $src4",
1584             []>,
1585             Requires<[HasV4T]>;
1586
1587 // if (!Pv) memd(Rs+#u6:3)=Rtt
1588 // if (!Pv.new) memd(Rs+#u6:3)=Rtt
1589 let AddedComplexity = 10, neverHasSideEffects = 1,
1590     isPredicated = 1 in
1591 def STrid_indexed_cdnNotPt_V4 : STInst2<(outs),
1592             (ins PredRegs:$src1, IntRegs:$src2, u6_3Imm:$src3,
1593                  DoubleRegs:$src4),
1594             "if (!$src1.new) memd($src2+#$src3) = $src4",
1595             []>,
1596             Requires<[HasV4T]>;
1597
1598 // if ([!]Pv[.new]) memd(Rs+Ru<<#u2)=Rtt
1599 // if (Pv) memd(Rs+Ru<<#u2)=Rtt
1600 let AddedComplexity = 10, neverHasSideEffects = 1,
1601     isPredicated = 1 in
1602 def STrid_indexed_shl_cPt_V4 : STInst2<(outs),
1603             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
1604                  DoubleRegs:$src5),
1605             "if ($src1) memd($src2+$src3<<#$src4) = $src5",
1606             []>,
1607             Requires<[HasV4T]>;
1608
1609 // if (Pv.new) memd(Rs+Ru<<#u2)=Rtt
1610 let AddedComplexity = 10, neverHasSideEffects = 1,
1611     isPredicated = 1 in
1612 def STrid_indexed_shl_cdnPt_V4 : STInst2<(outs),
1613             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
1614                  DoubleRegs:$src5),
1615             "if ($src1.new) memd($src2+$src3<<#$src4) = $src5",
1616             []>,
1617             Requires<[HasV4T]>;
1618 // if (!Pv) memd(Rs+Ru<<#u2)=Rtt
1619 let AddedComplexity = 10, neverHasSideEffects = 1,
1620     isPredicated = 1 in
1621 def STrid_indexed_shl_cNotPt_V4 : STInst2<(outs),
1622             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
1623                  DoubleRegs:$src5),
1624             "if (!$src1) memd($src2+$src3<<#$src4) = $src5",
1625             []>,
1626             Requires<[HasV4T]>;
1627 // if (!Pv.new) memd(Rs+Ru<<#u2)=Rtt
1628 let AddedComplexity = 10, neverHasSideEffects = 1,
1629     isPredicated = 1 in
1630 def STrid_indexed_shl_cdnNotPt_V4 : STInst2<(outs),
1631             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
1632                  DoubleRegs:$src5),
1633             "if (!$src1.new) memd($src2+$src3<<#$src4) = $src5",
1634             []>,
1635             Requires<[HasV4T]>;
1636
1637 // if ([!]Pv[.new]) memd(Rx++#s4:3)=Rtt
1638 // if (Pv) memd(Rx++#s4:3)=Rtt
1639 // if (Pv.new) memd(Rx++#s4:3)=Rtt
1640 let AddedComplexity = 10, neverHasSideEffects = 1,
1641     isPredicated = 1 in
1642 def POST_STdri_cdnPt_V4 : STInst2PI<(outs IntRegs:$dst),
1643             (ins PredRegs:$src1, DoubleRegs:$src2, IntRegs:$src3,
1644                  s4_3Imm:$offset),
1645             "if ($src1.new) memd($src3++#$offset) = $src2",
1646             [],
1647             "$src3 = $dst">,
1648             Requires<[HasV4T]>;
1649
1650 // if (!Pv) memd(Rx++#s4:3)=Rtt
1651 // if (!Pv.new) memd(Rx++#s4:3)=Rtt
1652 let AddedComplexity = 10, neverHasSideEffects = 1,
1653     isPredicated = 1 in
1654 def POST_STdri_cdnNotPt_V4 : STInst2PI<(outs IntRegs:$dst),
1655             (ins PredRegs:$src1, DoubleRegs:$src2, IntRegs:$src3,
1656                  s4_3Imm:$offset),
1657             "if (!$src1.new) memd($src3++#$offset) = $src2",
1658             [],
1659             "$src3 = $dst">,
1660             Requires<[HasV4T]>;
1661
1662
1663 // Store byte.
1664 // memb(Rs+#u6:0)=#S8
1665 let AddedComplexity = 10, isPredicable = 1 in
1666 def STrib_imm_V4 : STInst<(outs),
1667             (ins IntRegs:$src1, u6_0Imm:$src2, s8Imm:$src3),
1668             "memb($src1+#$src2) = #$src3",
1669             [(truncstorei8 s8ImmPred:$src3, (add (i32 IntRegs:$src1),
1670                                                  u6_0ImmPred:$src2))]>,
1671             Requires<[HasV4T]>;
1672
1673 // memb(Rs+Ru<<#u2)=Rt
1674 let AddedComplexity = 10, isPredicable = 1 in
1675 def STrib_indexed_shl_V4 : STInst<(outs),
1676             (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$src3, IntRegs:$src4),
1677             "memb($src1+$src2<<#$src3) = $src4",
1678             [(truncstorei8 (i32 IntRegs:$src4),
1679                            (add (i32 IntRegs:$src1),
1680                                 (shl (i32 IntRegs:$src2),
1681                                           u2ImmPred:$src3)))]>,
1682             Requires<[HasV4T]>;
1683
1684 // memb(Ru<<#u2+#U6)=Rt
1685 let AddedComplexity = 10 in
1686 def STrib_shl_V4 : STInst<(outs),
1687             (ins IntRegs:$src1, u2Imm:$src2, u6Imm:$src3, IntRegs:$src4),
1688             "memb($src1<<#$src2+#$src3) = $src4",
1689             [(truncstorei8 (i32 IntRegs:$src4),
1690                            (add (shl (i32 IntRegs:$src1), u2ImmPred:$src2),
1691                                 u6ImmPred:$src3))]>,
1692             Requires<[HasV4T]>;
1693
1694 // memb(Rx++#s4:0:circ(Mu))=Rt
1695 // memb(Rx++I:circ(Mu))=Rt
1696 // memb(Rx++Mu)=Rt
1697 // memb(Rx++Mu:brev)=Rt
1698 // memb(gp+#u16:0)=Rt
1699
1700
1701 // Store byte conditionally.
1702 // if ([!]Pv[.new]) memb(#u6)=Rt
1703 // if ([!]Pv[.new]) memb(Rs+#u6:0)=#S6
1704 // if (Pv) memb(Rs+#u6:0)=#S6
1705 let neverHasSideEffects = 1,
1706     isPredicated = 1 in
1707 def STrib_imm_cPt_V4 : STInst2<(outs),
1708             (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, s6Imm:$src4),
1709             "if ($src1) memb($src2+#$src3) = #$src4",
1710             []>,
1711             Requires<[HasV4T]>;
1712
1713 // if (Pv.new) memb(Rs+#u6:0)=#S6
1714 let neverHasSideEffects = 1,
1715     isPredicated = 1 in
1716 def STrib_imm_cdnPt_V4 : STInst2<(outs),
1717             (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, s6Imm:$src4),
1718             "if ($src1.new) memb($src2+#$src3) = #$src4",
1719             []>,
1720             Requires<[HasV4T]>;
1721
1722 // if (!Pv) memb(Rs+#u6:0)=#S6
1723 let neverHasSideEffects = 1,
1724     isPredicated = 1 in
1725 def STrib_imm_cNotPt_V4 : STInst2<(outs),
1726             (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, s6Imm:$src4),
1727             "if (!$src1) memb($src2+#$src3) = #$src4",
1728             []>,
1729             Requires<[HasV4T]>;
1730
1731 // if (!Pv.new) memb(Rs+#u6:0)=#S6
1732 let neverHasSideEffects = 1,
1733     isPredicated = 1 in
1734 def STrib_imm_cdnNotPt_V4 : STInst2<(outs),
1735             (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, s6Imm:$src4),
1736             "if (!$src1.new) memb($src2+#$src3) = #$src4",
1737             []>,
1738             Requires<[HasV4T]>;
1739
1740 // if ([!]Pv[.new]) memb(Rs+#u6:0)=Rt
1741 // if (Pv) memb(Rs+#u6:0)=Rt
1742 // if (Pv.new) memb(Rs+#u6:0)=Rt
1743 let neverHasSideEffects = 1,
1744     isPredicated = 1 in
1745 def STrib_cdnPt_V4 : STInst2<(outs),
1746             (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
1747             "if ($src1.new) memb($addr) = $src2",
1748             []>,
1749             Requires<[HasV4T]>;
1750
1751 // if (!Pv) memb(Rs+#u6:0)=Rt
1752 // if (!Pv.new) memb(Rs+#u6:0)=Rt
1753 let neverHasSideEffects = 1,
1754     isPredicated = 1 in
1755 def STrib_cdnNotPt_V4 : STInst2<(outs),
1756             (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
1757             "if (!$src1.new) memb($addr) = $src2",
1758             []>,
1759             Requires<[HasV4T]>;
1760
1761 // if (Pv) memb(Rs+#u6:0)=Rt
1762 // if (!Pv) memb(Rs+#u6:0)=Rt
1763 // if (Pv.new) memb(Rs+#u6:0)=Rt
1764 let neverHasSideEffects = 1,
1765     isPredicated = 1 in
1766 def STrib_indexed_cdnPt_V4 : STInst2<(outs),
1767             (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, IntRegs:$src4),
1768             "if ($src1.new) memb($src2+#$src3) = $src4",
1769             []>,
1770             Requires<[HasV4T]>;
1771
1772 // if (!Pv.new) memb(Rs+#u6:0)=Rt
1773 let neverHasSideEffects = 1,
1774     isPredicated = 1 in
1775 def STrib_indexed_cdnNotPt_V4 : STInst2<(outs),
1776             (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, IntRegs:$src4),
1777             "if (!$src1.new) memb($src2+#$src3) = $src4",
1778             []>,
1779             Requires<[HasV4T]>;
1780
1781 // if ([!]Pv[.new]) memb(Rs+Ru<<#u2)=Rt
1782 // if (Pv) memb(Rs+Ru<<#u2)=Rt
1783 let AddedComplexity = 10,
1784     isPredicated = 1 in
1785 def STrib_indexed_shl_cPt_V4 : STInst2<(outs),
1786             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
1787                  IntRegs:$src5),
1788             "if ($src1) memb($src2+$src3<<#$src4) = $src5",
1789             []>,
1790             Requires<[HasV4T]>;
1791
1792 // if (Pv.new) memb(Rs+Ru<<#u2)=Rt
1793 let AddedComplexity = 10,
1794     isPredicated = 1 in
1795 def STrib_indexed_shl_cdnPt_V4 : STInst2<(outs),
1796             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
1797                  IntRegs:$src5),
1798             "if ($src1.new) memb($src2+$src3<<#$src4) = $src5",
1799             []>,
1800             Requires<[HasV4T]>;
1801
1802 // if (!Pv) memb(Rs+Ru<<#u2)=Rt
1803 let AddedComplexity = 10,
1804     isPredicated = 1 in
1805 def STrib_indexed_shl_cNotPt_V4 : STInst2<(outs),
1806             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
1807                  IntRegs:$src5),
1808             "if (!$src1) memb($src2+$src3<<#$src4) = $src5",
1809             []>,
1810             Requires<[HasV4T]>;
1811
1812 // if (!Pv.new) memb(Rs+Ru<<#u2)=Rt
1813 let AddedComplexity = 10,
1814     isPredicated = 1 in
1815 def STrib_indexed_shl_cdnNotPt_V4 : STInst2<(outs),
1816             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
1817                  IntRegs:$src5),
1818             "if (!$src1.new) memb($src2+$src3<<#$src4) = $src5",
1819             []>,
1820             Requires<[HasV4T]>;
1821
1822 // if ([!]Pv[.new]) memb(Rx++#s4:0)=Rt
1823 // if (Pv) memb(Rx++#s4:0)=Rt
1824 // if (Pv.new) memb(Rx++#s4:0)=Rt
1825 let hasCtrlDep = 1,
1826     isPredicated = 1 in
1827 def POST_STbri_cdnPt_V4 : STInst2PI<(outs IntRegs:$dst),
1828             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_0Imm:$offset),
1829             "if ($src1.new) memb($src3++#$offset) = $src2",
1830             [],"$src3 = $dst">,
1831             Requires<[HasV4T]>;
1832
1833 // if (!Pv) memb(Rx++#s4:0)=Rt
1834 // if (!Pv.new) memb(Rx++#s4:0)=Rt
1835 let hasCtrlDep = 1,
1836     isPredicated = 1 in
1837 def POST_STbri_cdnNotPt_V4 : STInst2PI<(outs IntRegs:$dst),
1838             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_0Imm:$offset),
1839             "if (!$src1.new) memb($src3++#$offset) = $src2",
1840             [],"$src3 = $dst">,
1841             Requires<[HasV4T]>;
1842
1843
1844 // Store halfword.
1845 // TODO: needs to be implemented
1846 // memh(Re=#U6)=Rt.H
1847 // memh(Rs+#s11:1)=Rt.H
1848 // memh(Rs+#u6:1)=#S8
1849 let AddedComplexity = 10, isPredicable = 1 in
1850 def STrih_imm_V4 : STInst<(outs),
1851             (ins IntRegs:$src1, u6_1Imm:$src2, s8Imm:$src3),
1852             "memh($src1+#$src2) = #$src3",
1853             [(truncstorei16 s8ImmPred:$src3, (add (i32 IntRegs:$src1),
1854                                                   u6_1ImmPred:$src2))]>,
1855             Requires<[HasV4T]>;
1856
1857 // memh(Rs+Ru<<#u2)=Rt.H
1858 // TODO: needs to be implemented.
1859
1860 // memh(Rs+Ru<<#u2)=Rt
1861 let AddedComplexity = 10, isPredicable = 1 in
1862 def STrih_indexed_shl_V4 : STInst<(outs),
1863             (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$src3, IntRegs:$src4),
1864             "memh($src1+$src2<<#$src3) = $src4",
1865             [(truncstorei16 (i32 IntRegs:$src4),
1866                             (add (i32 IntRegs:$src1),
1867                                  (shl (i32 IntRegs:$src2),
1868                                       u2ImmPred:$src3)))]>,
1869             Requires<[HasV4T]>;
1870
1871 // memh(Ru<<#u2+#U6)=Rt.H
1872 // memh(Ru<<#u2+#U6)=Rt
1873 let AddedComplexity = 10 in
1874 def STrih_shl_V4 : STInst<(outs),
1875             (ins IntRegs:$src1, u2Imm:$src2, u6Imm:$src3, IntRegs:$src4),
1876             "memh($src1<<#$src2+#$src3) = $src4",
1877             [(truncstorei16 (i32 IntRegs:$src4),
1878                             (add (shl (i32 IntRegs:$src1), u2ImmPred:$src2),
1879                                  u6ImmPred:$src3))]>,
1880             Requires<[HasV4T]>;
1881
1882 // memh(Rx++#s4:1:circ(Mu))=Rt.H
1883 // memh(Rx++#s4:1:circ(Mu))=Rt
1884 // memh(Rx++I:circ(Mu))=Rt.H
1885 // memh(Rx++I:circ(Mu))=Rt
1886 // memh(Rx++Mu)=Rt.H
1887 // memh(Rx++Mu)=Rt
1888 // memh(Rx++Mu:brev)=Rt.H
1889 // memh(Rx++Mu:brev)=Rt
1890 // memh(gp+#u16:1)=Rt
1891 // if ([!]Pv[.new]) memh(#u6)=Rt.H
1892 // if ([!]Pv[.new]) memh(#u6)=Rt
1893
1894 // if ([!]Pv[.new]) memh(Rs+#u6:1)=#S6
1895 // if (Pv) memh(Rs+#u6:1)=#S6
1896 let neverHasSideEffects = 1,
1897     isPredicated = 1 in
1898 def STrih_imm_cPt_V4 : STInst2<(outs),
1899             (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, s6Imm:$src4),
1900             "if ($src1) memh($src2+#$src3) = #$src4",
1901             []>,
1902             Requires<[HasV4T]>;
1903
1904 // if (Pv.new) memh(Rs+#u6:1)=#S6
1905 let neverHasSideEffects = 1,
1906     isPredicated = 1 in
1907 def STrih_imm_cdnPt_V4 : STInst2<(outs),
1908             (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, s6Imm:$src4),
1909             "if ($src1.new) memh($src2+#$src3) = #$src4",
1910             []>,
1911             Requires<[HasV4T]>;
1912
1913 // if (!Pv) memh(Rs+#u6:1)=#S6
1914 let neverHasSideEffects = 1,
1915     isPredicated = 1 in
1916 def STrih_imm_cNotPt_V4 : STInst2<(outs),
1917             (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, s6Imm:$src4),
1918             "if (!$src1) memh($src2+#$src3) = #$src4",
1919             []>,
1920             Requires<[HasV4T]>;
1921
1922 // if (!Pv.new) memh(Rs+#u6:1)=#S6
1923 let neverHasSideEffects = 1,
1924     isPredicated = 1 in
1925 def STrih_imm_cdnNotPt_V4 : STInst2<(outs),
1926             (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, s6Imm:$src4),
1927             "if (!$src1.new) memh($src2+#$src3) = #$src4",
1928             []>,
1929             Requires<[HasV4T]>;
1930
1931 // if ([!]Pv[.new]) memh(Rs+#u6:1)=Rt.H
1932 // TODO: needs to be implemented.
1933
1934 // if ([!]Pv[.new]) memh(Rs+#u6:1)=Rt
1935 // if (Pv) memh(Rs+#u6:1)=Rt
1936 // if (Pv.new) memh(Rs+#u6:1)=Rt
1937 let neverHasSideEffects = 1,
1938     isPredicated = 1 in
1939 def STrih_cdnPt_V4 : STInst2<(outs),
1940             (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
1941             "if ($src1.new) memh($addr) = $src2",
1942             []>,
1943             Requires<[HasV4T]>;
1944
1945 // if (!Pv) memh(Rs+#u6:1)=Rt
1946 // if (!Pv.new) memh(Rs+#u6:1)=Rt
1947 let neverHasSideEffects = 1,
1948     isPredicated = 1 in
1949 def STrih_cdnNotPt_V4 : STInst2<(outs),
1950             (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
1951             "if (!$src1.new) memh($addr) = $src2",
1952             []>,
1953             Requires<[HasV4T]>;
1954
1955 // if (Pv.new) memh(Rs+#u6:1)=Rt
1956 let neverHasSideEffects = 1,
1957     isPredicated = 1 in
1958 def STrih_indexed_cdnPt_V4 : STInst2<(outs),
1959             (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, IntRegs:$src4),
1960             "if ($src1.new) memh($src2+#$src3) = $src4",
1961             []>,
1962             Requires<[HasV4T]>;
1963
1964 // if (!Pv.new) memh(Rs+#u6:1)=Rt
1965 let neverHasSideEffects = 1,
1966     isPredicated = 1 in
1967 def STrih_indexed_cdnNotPt_V4 : STInst2<(outs),
1968             (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, IntRegs:$src4),
1969             "if (!$src1.new) memh($src2+#$src3) = $src4",
1970             []>,
1971             Requires<[HasV4T]>;
1972
1973 // if ([!]Pv[.new]) memh(Rs+Ru<<#u2)=Rt.H
1974 // if ([!]Pv[.new]) memh(Rs+Ru<<#u2)=Rt
1975 // if (Pv) memh(Rs+Ru<<#u2)=Rt
1976 let AddedComplexity = 10,
1977     isPredicated = 1 in
1978 def STrih_indexed_shl_cPt_V4 : STInst2<(outs),
1979             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
1980                  IntRegs:$src5),
1981             "if ($src1) memh($src2+$src3<<#$src4) = $src5",
1982             []>,
1983             Requires<[HasV4T]>;
1984
1985 // if (Pv.new) memh(Rs+Ru<<#u2)=Rt
1986 let AddedComplexity = 10,
1987     isPredicated = 1 in
1988 def STrih_indexed_shl_cdnPt_V4 : STInst2<(outs),
1989             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
1990                  IntRegs:$src5),
1991             "if ($src1.new) memh($src2+$src3<<#$src4) = $src5",
1992             []>,
1993             Requires<[HasV4T]>;
1994
1995 // if (!Pv) memh(Rs+Ru<<#u2)=Rt
1996 let AddedComplexity = 10,
1997     isPredicated = 1 in
1998 def STrih_indexed_shl_cNotPt_V4 : STInst2<(outs),
1999             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
2000                  IntRegs:$src5),
2001             "if (!$src1) memh($src2+$src3<<#$src4) = $src5",
2002             []>,
2003             Requires<[HasV4T]>;
2004
2005 // if (!Pv.new) memh(Rs+Ru<<#u2)=Rt
2006 let AddedComplexity = 10,
2007     isPredicated = 1 in
2008 def STrih_indexed_shl_cdnNotPt_V4 : STInst2<(outs),
2009             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
2010                  IntRegs:$src5),
2011             "if (!$src1.new) memh($src2+$src3<<#$src4) = $src5",
2012             []>,
2013             Requires<[HasV4T]>;
2014
2015 // if ([!]Pv[.new]) memh(Rx++#s4:1)=Rt.H
2016 // TODO: Needs to be implemented.
2017
2018 // if ([!]Pv[.new]) memh(Rx++#s4:1)=Rt
2019 // if (Pv) memh(Rx++#s4:1)=Rt
2020 // if (Pv.new) memh(Rx++#s4:1)=Rt
2021 let hasCtrlDep = 1,
2022     isPredicated = 1 in
2023 def POST_SThri_cdnPt_V4 : STInst2PI<(outs IntRegs:$dst),
2024             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_1Imm:$offset),
2025             "if ($src1.new) memh($src3++#$offset) = $src2",
2026             [],"$src3 = $dst">,
2027             Requires<[HasV4T]>;
2028
2029 // if (!Pv) memh(Rx++#s4:1)=Rt
2030 // if (!Pv.new) memh(Rx++#s4:1)=Rt
2031 let hasCtrlDep = 1,
2032     isPredicated = 1 in
2033 def POST_SThri_cdnNotPt_V4 : STInst2PI<(outs IntRegs:$dst),
2034             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_1Imm:$offset),
2035             "if (!$src1.new) memh($src3++#$offset) = $src2",
2036             [],"$src3 = $dst">,
2037             Requires<[HasV4T]>;
2038
2039
2040 // Store word.
2041 // memw(Re=#U6)=Rt
2042 // TODO: Needs to be implemented.
2043
2044 // Store predicate:
2045 let neverHasSideEffects = 1 in
2046 def STriw_pred_V4 : STInst2<(outs),
2047             (ins MEMri:$addr, PredRegs:$src1),
2048             "Error; should not emit",
2049             []>,
2050             Requires<[HasV4T]>;
2051
2052
2053 // memw(Rs+#u6:2)=#S8
2054 let AddedComplexity = 10, isPredicable = 1 in
2055 def STriw_imm_V4 : STInst<(outs),
2056             (ins IntRegs:$src1, u6_2Imm:$src2, s8Imm:$src3),
2057             "memw($src1+#$src2) = #$src3",
2058             [(store s8ImmPred:$src3, (add (i32 IntRegs:$src1),
2059                                           u6_2ImmPred:$src2))]>,
2060             Requires<[HasV4T]>;
2061
2062 // memw(Rs+Ru<<#u2)=Rt
2063 let AddedComplexity = 10, isPredicable = 1 in
2064 def STriw_indexed_shl_V4 : STInst<(outs),
2065             (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$src3, IntRegs:$src4),
2066             "memw($src1+$src2<<#$src3) = $src4",
2067             [(store (i32 IntRegs:$src4), (add (i32 IntRegs:$src1),
2068                                     (shl (i32 IntRegs:$src2),
2069                                          u2ImmPred:$src3)))]>,
2070             Requires<[HasV4T]>;
2071
2072 // memw(Ru<<#u2+#U6)=Rt
2073 let AddedComplexity = 10 in
2074 def STriw_shl_V4 : STInst<(outs),
2075             (ins IntRegs:$src1, u2Imm:$src2, u6Imm:$src3, IntRegs:$src4),
2076             "memw($src1<<#$src2+#$src3) = $src4",
2077             [(store (i32 IntRegs:$src4),
2078                     (add (shl (i32 IntRegs:$src1), u2ImmPred:$src2),
2079                               u6ImmPred:$src3))]>,
2080             Requires<[HasV4T]>;
2081
2082 // memw(Rx++#s4:2)=Rt
2083 // memw(Rx++#s4:2:circ(Mu))=Rt
2084 // memw(Rx++I:circ(Mu))=Rt
2085 // memw(Rx++Mu)=Rt
2086 // memw(Rx++Mu:brev)=Rt
2087 // memw(gp+#u16:2)=Rt
2088
2089
2090 // Store word conditionally.
2091
2092 // if ([!]Pv[.new]) memw(Rs+#u6:2)=#S6
2093 // if (Pv) memw(Rs+#u6:2)=#S6
2094 let neverHasSideEffects = 1,
2095     isPredicated = 1 in
2096 def STriw_imm_cPt_V4 : STInst2<(outs),
2097             (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, s6Imm:$src4),
2098             "if ($src1) memw($src2+#$src3) = #$src4",
2099             []>,
2100             Requires<[HasV4T]>;
2101
2102 // if (Pv.new) memw(Rs+#u6:2)=#S6
2103 let neverHasSideEffects = 1,
2104     isPredicated = 1 in
2105 def STriw_imm_cdnPt_V4 : STInst2<(outs),
2106             (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, s6Imm:$src4),
2107             "if ($src1.new) memw($src2+#$src3) = #$src4",
2108             []>,
2109             Requires<[HasV4T]>;
2110
2111 // if (!Pv) memw(Rs+#u6:2)=#S6
2112 let neverHasSideEffects = 1,
2113     isPredicated = 1 in
2114 def STriw_imm_cNotPt_V4 : STInst2<(outs),
2115             (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, s6Imm:$src4),
2116             "if (!$src1) memw($src2+#$src3) = #$src4",
2117             []>,
2118             Requires<[HasV4T]>;
2119
2120 // if (!Pv.new) memw(Rs+#u6:2)=#S6
2121 let neverHasSideEffects = 1,
2122     isPredicated = 1 in
2123 def STriw_imm_cdnNotPt_V4 : STInst2<(outs),
2124             (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, s6Imm:$src4),
2125             "if (!$src1.new) memw($src2+#$src3) = #$src4",
2126             []>,
2127             Requires<[HasV4T]>;
2128
2129 // if ([!]Pv[.new]) memw(Rs+#u6:2)=Rt
2130 // if (Pv) memw(Rs+#u6:2)=Rt
2131 // if (Pv.new) memw(Rs+#u6:2)=Rt
2132 let neverHasSideEffects = 1,
2133     isPredicated = 1 in
2134 def STriw_cdnPt_V4 : STInst2<(outs),
2135             (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
2136             "if ($src1.new) memw($addr) = $src2",
2137             []>,
2138             Requires<[HasV4T]>;
2139
2140 // if (!Pv) memw(Rs+#u6:2)=Rt
2141 // if (!Pv.new) memw(Rs+#u6:2)=Rt
2142 let neverHasSideEffects = 1,
2143     isPredicated = 1 in
2144 def STriw_cdnNotPt_V4 : STInst2<(outs),
2145             (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
2146             "if (!$src1.new) memw($addr) = $src2",
2147             []>,
2148             Requires<[HasV4T]>;
2149
2150 // if (Pv) memw(Rs+#u6:2)=Rt
2151 // if (!Pv) memw(Rs+#u6:2)=Rt
2152 // if (Pv.new) memw(Rs+#u6:2)=Rt
2153 let neverHasSideEffects = 1,
2154     isPredicated = 1 in
2155 def STriw_indexed_cdnPt_V4 : STInst2<(outs),
2156             (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, IntRegs:$src4),
2157             "if ($src1.new) memw($src2+#$src3) = $src4",
2158             []>,
2159             Requires<[HasV4T]>;
2160
2161 // if (!Pv.new) memw(Rs+#u6:2)=Rt
2162 let neverHasSideEffects = 1,
2163     isPredicated = 1 in
2164 def STriw_indexed_cdnNotPt_V4 : STInst2<(outs),
2165             (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, IntRegs:$src4),
2166             "if (!$src1.new) memw($src2+#$src3) = $src4",
2167             []>,
2168             Requires<[HasV4T]>;
2169
2170 // if ([!]Pv[.new]) memw(Rs+Ru<<#u2)=Rt
2171 // if (Pv) memw(Rs+Ru<<#u2)=Rt
2172 let AddedComplexity = 10,
2173     isPredicated = 1 in
2174 def STriw_indexed_shl_cPt_V4 : STInst2<(outs),
2175             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
2176                  IntRegs:$src5),
2177             "if ($src1) memw($src2+$src3<<#$src4) = $src5",
2178             []>,
2179             Requires<[HasV4T]>;
2180
2181 // if (Pv.new) memw(Rs+Ru<<#u2)=Rt
2182 let AddedComplexity = 10,
2183     isPredicated = 1 in
2184 def STriw_indexed_shl_cdnPt_V4 : STInst2<(outs),
2185             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
2186                  IntRegs:$src5),
2187             "if ($src1.new) memw($src2+$src3<<#$src4) = $src5",
2188             []>,
2189             Requires<[HasV4T]>;
2190
2191 // if (!Pv) memw(Rs+Ru<<#u2)=Rt
2192 let AddedComplexity = 10,
2193     isPredicated = 1 in
2194 def STriw_indexed_shl_cNotPt_V4 : STInst2<(outs),
2195             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
2196                  IntRegs:$src5),
2197             "if (!$src1) memw($src2+$src3<<#$src4) = $src5",
2198             []>,
2199             Requires<[HasV4T]>;
2200
2201 // if (!Pv.new) memw(Rs+Ru<<#u2)=Rt
2202 let AddedComplexity = 10,
2203     isPredicated = 1 in
2204 def STriw_indexed_shl_cdnNotPt_V4 : STInst2<(outs),
2205             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
2206                  IntRegs:$src5),
2207             "if (!$src1.new) memw($src2+$src3<<#$src4) = $src5",
2208             []>,
2209             Requires<[HasV4T]>;
2210
2211 // if ([!]Pv[.new]) memw(Rx++#s4:2)=Rt
2212 // if (Pv) memw(Rx++#s4:2)=Rt
2213 // if (Pv.new) memw(Rx++#s4:2)=Rt
2214 let hasCtrlDep = 1,
2215     isPredicated = 1 in
2216 def POST_STwri_cdnPt_V4 : STInst2PI<(outs IntRegs:$dst),
2217             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset),
2218             "if ($src1.new) memw($src3++#$offset) = $src2",
2219             [],"$src3 = $dst">,
2220             Requires<[HasV4T]>;
2221
2222 // if (!Pv) memw(Rx++#s4:2)=Rt
2223 // if (!Pv.new) memw(Rx++#s4:2)=Rt
2224 let hasCtrlDep = 1,
2225     isPredicated = 1 in
2226 def POST_STwri_cdnNotPt_V4 : STInst2PI<(outs IntRegs:$dst),
2227             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset),
2228             "if (!$src1.new) memw($src3++#$offset) = $src2",
2229             [],"$src3 = $dst">,
2230             Requires<[HasV4T]>;
2231
2232
2233 /// store to global address
2234
2235 let isPredicable = 1, neverHasSideEffects = 1 in
2236 def STrid_GP_V4 : STInst2<(outs),
2237             (ins globaladdress:$global, u16Imm:$offset, DoubleRegs:$src),
2238             "memd(#$global+$offset) = $src",
2239             []>,
2240             Requires<[HasV4T]>;
2241
2242 let neverHasSideEffects = 1, isPredicated = 1 in
2243 def STrid_GP_cPt_V4 : STInst2<(outs),
2244             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2245                                                         DoubleRegs:$src2),
2246             "if ($src1) memd(##$global+$offset) = $src2",
2247             []>,
2248             Requires<[HasV4T]>;
2249
2250 let neverHasSideEffects = 1, isPredicated = 1 in
2251 def STrid_GP_cNotPt_V4 : STInst2<(outs),
2252             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2253                                                         DoubleRegs:$src2),
2254             "if (!$src1) memd(##$global+$offset) = $src2",
2255             []>,
2256             Requires<[HasV4T]>;
2257
2258 let neverHasSideEffects = 1, isPredicated = 1 in
2259 def STrid_GP_cdnPt_V4 : STInst2<(outs),
2260             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2261                                                         DoubleRegs:$src2),
2262             "if ($src1.new) memd(##$global+$offset) = $src2",
2263             []>,
2264             Requires<[HasV4T]>;
2265
2266 let neverHasSideEffects = 1, isPredicated = 1 in
2267 def STrid_GP_cdnNotPt_V4 : STInst2<(outs),
2268             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2269                                                         DoubleRegs:$src2),
2270             "if (!$src1.new) memd(##$global+$offset) = $src2",
2271             []>,
2272             Requires<[HasV4T]>;
2273
2274 let isPredicable = 1, neverHasSideEffects = 1 in
2275 def STrib_GP_V4 : STInst2<(outs),
2276             (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),
2277             "memb(#$global+$offset) = $src",
2278             []>,
2279             Requires<[HasV4T]>;
2280
2281 let neverHasSideEffects = 1, isPredicated = 1 in
2282 def STrib_GP_cPt_V4 : STInst2<(outs),
2283             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2284                                                         IntRegs:$src2),
2285             "if ($src1) memb(##$global+$offset) = $src2",
2286             []>,
2287             Requires<[HasV4T]>;
2288
2289 let neverHasSideEffects = 1, isPredicated = 1 in
2290 def STrib_GP_cNotPt_V4 : STInst2<(outs),
2291             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2292                                                         IntRegs:$src2),
2293             "if (!$src1) memb(##$global+$offset) = $src2",
2294             []>,
2295             Requires<[HasV4T]>;
2296
2297 let neverHasSideEffects = 1, isPredicated = 1 in
2298 def STrib_GP_cdnPt_V4 : STInst2<(outs),
2299             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2300                                                         IntRegs:$src2),
2301             "if ($src1.new) memb(##$global+$offset) = $src2",
2302             []>,
2303             Requires<[HasV4T]>;
2304
2305 let neverHasSideEffects = 1, isPredicated = 1 in
2306 def STrib_GP_cdnNotPt_V4 : STInst2<(outs),
2307             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2308                                                         IntRegs:$src2),
2309             "if (!$src1.new) memb(##$global+$offset) = $src2",
2310             []>,
2311             Requires<[HasV4T]>;
2312
2313 let isPredicable = 1, neverHasSideEffects = 1 in
2314 def STrih_GP_V4 : STInst2<(outs),
2315             (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),
2316             "memh(#$global+$offset) = $src",
2317             []>,
2318             Requires<[HasV4T]>;
2319
2320 let neverHasSideEffects = 1, isPredicated = 1 in
2321 def STrih_GP_cPt_V4 : STInst2<(outs),
2322             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2323                                                         IntRegs:$src2),
2324             "if ($src1) memh(##$global+$offset) = $src2",
2325             []>,
2326             Requires<[HasV4T]>;
2327
2328 let neverHasSideEffects = 1, isPredicated = 1 in
2329 def STrih_GP_cNotPt_V4 : STInst2<(outs),
2330             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2331                                                         IntRegs:$src2),
2332             "if (!$src1) memh(##$global+$offset) = $src2",
2333             []>,
2334             Requires<[HasV4T]>;
2335
2336 let neverHasSideEffects = 1, isPredicated = 1 in
2337 def STrih_GP_cdnPt_V4 : STInst2<(outs),
2338             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2339                                                         IntRegs:$src2),
2340             "if ($src1.new) memh(##$global+$offset) = $src2",
2341             []>,
2342             Requires<[HasV4T]>;
2343
2344 let neverHasSideEffects = 1, isPredicated = 1 in
2345 def STrih_GP_cdnNotPt_V4 : STInst2<(outs),
2346             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2347                                                         IntRegs:$src2),
2348             "if (!$src1.new) memh(##$global+$offset) = $src2",
2349             []>,
2350             Requires<[HasV4T]>;
2351
2352 let isPredicable = 1, neverHasSideEffects = 1 in
2353 def STriw_GP_V4 : STInst2<(outs),
2354             (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),
2355             "memw(#$global+$offset) = $src",
2356             []>,
2357             Requires<[HasV4T]>;
2358
2359 let neverHasSideEffects = 1, isPredicated = 1 in
2360 def STriw_GP_cPt_V4 : STInst2<(outs),
2361             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2362                                                         IntRegs:$src2),
2363             "if ($src1) memw(##$global+$offset) = $src2",
2364             []>,
2365             Requires<[HasV4T]>;
2366
2367 let neverHasSideEffects = 1, isPredicated = 1 in
2368 def STriw_GP_cNotPt_V4 : STInst2<(outs),
2369             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2370                                                         IntRegs:$src2),
2371             "if (!$src1) memw(##$global+$offset) = $src2",
2372             []>,
2373             Requires<[HasV4T]>;
2374
2375 let neverHasSideEffects = 1, isPredicated = 1 in
2376 def STriw_GP_cdnPt_V4 : STInst2<(outs),
2377             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2378                                                         IntRegs:$src2),
2379             "if ($src1.new) memw(##$global+$offset) = $src2",
2380             []>,
2381             Requires<[HasV4T]>;
2382
2383 let neverHasSideEffects = 1, isPredicated = 1 in
2384 def STriw_GP_cdnNotPt_V4 : STInst2<(outs),
2385             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2386                                                         IntRegs:$src2),
2387             "if (!$src1.new) memw(##$global+$offset) = $src2",
2388             []>,
2389             Requires<[HasV4T]>;
2390
2391 // memd(#global)=Rtt
2392 let isPredicable = 1, neverHasSideEffects = 1 in
2393 def STd_GP_V4 : STInst2<(outs),
2394             (ins globaladdress:$global, DoubleRegs:$src),
2395             "memd(#$global) = $src",
2396             []>,
2397             Requires<[HasV4T]>;
2398
2399 // if (Pv) memd(##global) = Rtt
2400 let neverHasSideEffects = 1, isPredicated = 1 in
2401 def STd_GP_cPt_V4 : STInst2<(outs),
2402             (ins PredRegs:$src1, globaladdress:$global, DoubleRegs:$src2),
2403             "if ($src1) memd(##$global) = $src2",
2404             []>,
2405             Requires<[HasV4T]>;
2406
2407 // if (!Pv) memd(##global) = Rtt
2408 let neverHasSideEffects = 1, isPredicated = 1 in
2409 def STd_GP_cNotPt_V4 : STInst2<(outs),
2410             (ins PredRegs:$src1, globaladdress:$global, DoubleRegs:$src2),
2411             "if (!$src1) memd(##$global) = $src2",
2412             []>,
2413               Requires<[HasV4T]>;
2414
2415 // if (Pv) memd(##global) = Rtt
2416 let neverHasSideEffects = 1, isPredicated = 1 in
2417 def STd_GP_cdnPt_V4 : STInst2<(outs),
2418             (ins PredRegs:$src1, globaladdress:$global, DoubleRegs:$src2),
2419             "if ($src1.new) memd(##$global) = $src2",
2420             []>,
2421               Requires<[HasV4T]>;
2422
2423 // if (!Pv) memd(##global) = Rtt
2424 let neverHasSideEffects = 1, isPredicated = 1 in
2425 def STd_GP_cdnNotPt_V4 : STInst2<(outs),
2426             (ins PredRegs:$src1, globaladdress:$global, DoubleRegs:$src2),
2427             "if (!$src1.new) memd(##$global) = $src2",
2428             []>,
2429             Requires<[HasV4T]>;
2430
2431 // memb(#global)=Rt
2432 let isPredicable = 1, neverHasSideEffects = 1 in
2433 def STb_GP_V4 : STInst2<(outs),
2434             (ins globaladdress:$global, IntRegs:$src),
2435             "memb(#$global) = $src",
2436             []>,
2437             Requires<[HasV4T]>;
2438
2439 // if (Pv) memb(##global) = Rt
2440 let neverHasSideEffects = 1, isPredicated = 1 in
2441 def STb_GP_cPt_V4 : STInst2<(outs),
2442             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2443             "if ($src1) memb(##$global) = $src2",
2444               []>,
2445               Requires<[HasV4T]>;
2446
2447 // if (!Pv) memb(##global) = Rt
2448 let neverHasSideEffects = 1, isPredicated = 1 in
2449 def STb_GP_cNotPt_V4 : STInst2<(outs),
2450             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2451             "if (!$src1) memb(##$global) = $src2",
2452               []>,
2453               Requires<[HasV4T]>;
2454
2455 // if (Pv) memb(##global) = Rt
2456 let neverHasSideEffects = 1, isPredicated = 1 in
2457 def STb_GP_cdnPt_V4 : STInst2<(outs),
2458             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2459             "if ($src1.new) memb(##$global) = $src2",
2460               []>,
2461               Requires<[HasV4T]>;
2462
2463 // if (!Pv) memb(##global) = Rt
2464 let neverHasSideEffects = 1, isPredicated = 1 in
2465 def STb_GP_cdnNotPt_V4 : STInst2<(outs),
2466             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2467             "if (!$src1.new) memb(##$global) = $src2",
2468               []>,
2469               Requires<[HasV4T]>;
2470
2471 // memh(#global)=Rt
2472 let isPredicable = 1, neverHasSideEffects = 1 in
2473 def STh_GP_V4 : STInst2<(outs),
2474             (ins globaladdress:$global, IntRegs:$src),
2475             "memh(#$global) = $src",
2476             []>,
2477             Requires<[HasV4T]>;
2478
2479 // if (Pv) memh(##global) = Rt
2480 let neverHasSideEffects = 1, isPredicated = 1 in
2481 def STh_GP_cPt_V4 : STInst2<(outs),
2482             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2483             "if ($src1) memh(##$global) = $src2",
2484               []>,
2485               Requires<[HasV4T]>;
2486
2487 // if (!Pv) memh(##global) = Rt
2488 let neverHasSideEffects = 1, isPredicated = 1 in
2489 def STh_GP_cNotPt_V4 : STInst2<(outs),
2490             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2491             "if (!$src1) memh(##$global) = $src2",
2492               []>,
2493               Requires<[HasV4T]>;
2494
2495 // if (Pv) memh(##global) = Rt
2496 let neverHasSideEffects = 1, isPredicated = 1 in
2497 def STh_GP_cdnPt_V4 : STInst2<(outs),
2498             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2499             "if ($src1.new) memh(##$global) = $src2",
2500               []>,
2501               Requires<[HasV4T]>;
2502
2503 // if (!Pv) memh(##global) = Rt
2504 let neverHasSideEffects = 1, isPredicated = 1 in
2505 def STh_GP_cdnNotPt_V4 : STInst2<(outs),
2506             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2507             "if (!$src1.new) memh(##$global) = $src2",
2508               []>,
2509               Requires<[HasV4T]>;
2510
2511 // memw(#global)=Rt
2512 let isPredicable = 1, neverHasSideEffects = 1 in
2513 def STw_GP_V4 : STInst2<(outs),
2514             (ins globaladdress:$global, IntRegs:$src),
2515             "memw(#$global) = $src",
2516               []>,
2517               Requires<[HasV4T]>;
2518
2519 // if (Pv) memw(##global) = Rt
2520 let neverHasSideEffects = 1, isPredicated = 1 in
2521 def STw_GP_cPt_V4 : STInst2<(outs),
2522             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2523             "if ($src1) memw(##$global) = $src2",
2524               []>,
2525               Requires<[HasV4T]>;
2526
2527 // if (!Pv) memw(##global) = Rt
2528 let neverHasSideEffects = 1, isPredicated = 1 in
2529 def STw_GP_cNotPt_V4 : STInst2<(outs),
2530             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2531             "if (!$src1) memw(##$global) = $src2",
2532               []>,
2533               Requires<[HasV4T]>;
2534
2535 // if (Pv) memw(##global) = Rt
2536 let neverHasSideEffects = 1, isPredicated = 1 in
2537 def STw_GP_cdnPt_V4 : STInst2<(outs),
2538             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2539             "if ($src1.new) memw(##$global) = $src2",
2540               []>,
2541               Requires<[HasV4T]>;
2542
2543 // if (!Pv) memw(##global) = Rt
2544 let neverHasSideEffects = 1, isPredicated = 1 in
2545 def STw_GP_cdnNotPt_V4 : STInst2<(outs),
2546             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2547             "if (!$src1.new) memw(##$global) = $src2",
2548             []>,
2549               Requires<[HasV4T]>;
2550
2551 // 64 bit atomic store
2552 def : Pat <(atomic_store_64 (HexagonCONST32_GP tglobaladdr:$global),
2553                             (i64 DoubleRegs:$src1)),
2554            (STd_GP_V4 tglobaladdr:$global, (i64 DoubleRegs:$src1))>,
2555            Requires<[HasV4T]>;
2556
2557 // Map from store(globaladdress) -> memd(#foo)
2558 let AddedComplexity = 100 in
2559 def : Pat <(store (i64 DoubleRegs:$src1),
2560                   (HexagonCONST32_GP tglobaladdr:$global)),
2561            (STd_GP_V4 tglobaladdr:$global, (i64 DoubleRegs:$src1))>,
2562            Requires<[HasV4T]>;
2563
2564 // 8 bit atomic store
2565 def : Pat < (atomic_store_8 (HexagonCONST32_GP tglobaladdr:$global),
2566                             (i32 IntRegs:$src1)),
2567             (STb_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>,
2568               Requires<[HasV4T]>;
2569
2570 // Map from store(globaladdress) -> memb(#foo)
2571 let AddedComplexity = 100 in
2572 def : Pat<(truncstorei8 (i32 IntRegs:$src1),
2573           (HexagonCONST32_GP tglobaladdr:$global)),
2574           (STb_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>,
2575           Requires<[HasV4T]>;
2576
2577 // Map from "i1 = constant<-1>; memw(CONST32(#foo)) = i1"
2578 //       to "r0 = 1; memw(#foo) = r0"
2579 let AddedComplexity = 100 in
2580 def : Pat<(store (i1 -1), (HexagonCONST32_GP tglobaladdr:$global)),
2581           (STb_GP_V4 tglobaladdr:$global, (TFRI 1))>,
2582           Requires<[HasV4T]>;
2583
2584 def : Pat<(atomic_store_16 (HexagonCONST32_GP tglobaladdr:$global),
2585                            (i32 IntRegs:$src1)),
2586           (STh_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>,
2587           Requires<[HasV4T]>;
2588
2589 // Map from store(globaladdress) -> memh(#foo)
2590 let AddedComplexity = 100 in
2591 def : Pat<(truncstorei16 (i32 IntRegs:$src1),
2592                          (HexagonCONST32_GP tglobaladdr:$global)),
2593           (STh_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>,
2594           Requires<[HasV4T]>;
2595
2596 // 32 bit atomic store
2597 def : Pat<(atomic_store_32 (HexagonCONST32_GP tglobaladdr:$global),
2598                            (i32 IntRegs:$src1)),
2599           (STw_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>,
2600           Requires<[HasV4T]>;
2601
2602 // Map from store(globaladdress) -> memw(#foo)
2603 let AddedComplexity = 100 in
2604 def : Pat<(store (i32 IntRegs:$src1), (HexagonCONST32_GP tglobaladdr:$global)),
2605           (STw_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>,
2606           Requires<[HasV4T]>;
2607
2608 def : Pat<(atomic_store_64 (add (HexagonCONST32_GP tglobaladdr:$global),
2609                                 u16ImmPred:$offset),
2610                            (i64 DoubleRegs:$src1)),
2611           (STrid_GP_V4 tglobaladdr:$global, u16ImmPred:$offset,
2612                                             (i64 DoubleRegs:$src1))>,
2613           Requires<[HasV4T]>;
2614
2615 def : Pat<(atomic_store_32 (add (HexagonCONST32_GP tglobaladdr:$global),
2616                                 u16ImmPred:$offset),
2617                            (i32 IntRegs:$src1)),
2618           (STriw_GP_V4 tglobaladdr:$global, u16ImmPred:$offset,
2619                                             (i32 IntRegs:$src1))>,
2620           Requires<[HasV4T]>;
2621
2622 def : Pat<(atomic_store_16 (add (HexagonCONST32_GP tglobaladdr:$global),
2623                                 u16ImmPred:$offset),
2624                            (i32 IntRegs:$src1)),
2625           (STrih_GP_V4 tglobaladdr:$global, u16ImmPred:$offset,
2626                                             (i32 IntRegs:$src1))>,
2627           Requires<[HasV4T]>;
2628
2629 def : Pat<(atomic_store_8 (add (HexagonCONST32_GP tglobaladdr:$global),
2630                                u16ImmPred:$offset),
2631                           (i32 IntRegs:$src1)),
2632           (STrib_GP_V4 tglobaladdr:$global, u16ImmPred:$offset,
2633                                             (i32 IntRegs:$src1))>,
2634           Requires<[HasV4T]>;
2635
2636 // Map from store(globaladdress + x) -> memd(#foo + x)
2637 let AddedComplexity = 100 in
2638 def : Pat<(store (i64 DoubleRegs:$src1),
2639                     (add (HexagonCONST32_GP tglobaladdr:$global),
2640                                         u16ImmPred:$offset)),
2641           (STrid_GP_V4 tglobaladdr:$global, u16ImmPred:$offset,
2642                                             (i64 DoubleRegs:$src1))>,
2643           Requires<[HasV4T]>;
2644
2645 // Map from store(globaladdress + x) -> memb(#foo + x)
2646 let AddedComplexity = 100 in
2647 def : Pat<(truncstorei8 (i32 IntRegs:$src1),
2648                         (add (HexagonCONST32_GP tglobaladdr:$global),
2649                              u16ImmPred:$offset)),
2650           (STrib_GP_V4 tglobaladdr:$global, u16ImmPred:$offset,
2651                                             (i32 IntRegs:$src1))>,
2652           Requires<[HasV4T]>;
2653
2654 // Map from store(globaladdress + x) -> memh(#foo + x)
2655 let AddedComplexity = 100 in
2656 def : Pat<(truncstorei16 (i32 IntRegs:$src1),
2657                          (add (HexagonCONST32_GP tglobaladdr:$global),
2658                               u16ImmPred:$offset)),
2659           (STrih_GP_V4 tglobaladdr:$global, u16ImmPred:$offset,
2660                                             (i32 IntRegs:$src1))>,
2661           Requires<[HasV4T]>;
2662
2663 // Map from store(globaladdress + x) -> memw(#foo + x)
2664 let AddedComplexity = 100 in
2665 def : Pat<(store (i32 IntRegs:$src1),
2666                  (add (HexagonCONST32_GP tglobaladdr:$global),
2667                                 u16ImmPred:$offset)),
2668           (STriw_GP_V4 tglobaladdr:$global, u16ImmPred:$offset,
2669                                             (i32 IntRegs:$src1))>,
2670           Requires<[HasV4T]>;
2671
2672
2673
2674 //===----------------------------------------------------------------------===
2675 // ST -
2676 //===----------------------------------------------------------------------===
2677
2678
2679 //===----------------------------------------------------------------------===//
2680 // NV/ST +
2681 //===----------------------------------------------------------------------===//
2682
2683 // Store new-value byte.
2684
2685 // memb(Re=#U6)=Nt.new
2686 // memb(Rs+#s11:0)=Nt.new
2687 let mayStore = 1, isPredicable = 1 in
2688 def STrib_nv_V4 : NVInst_V4<(outs), (ins MEMri:$addr, IntRegs:$src1),
2689             "memb($addr) = $src1.new",
2690             []>,
2691             Requires<[HasV4T]>;
2692
2693 let mayStore = 1, isPredicable = 1 in
2694 def STrib_indexed_nv_V4 : NVInst_V4<(outs),
2695             (ins IntRegs:$src1, s11_0Imm:$src2, IntRegs:$src3),
2696             "memb($src1+#$src2) = $src3.new",
2697             []>,
2698             Requires<[HasV4T]>;
2699
2700 // memb(Rs+Ru<<#u2)=Nt.new
2701 let mayStore = 1, AddedComplexity = 10, isPredicable = 1 in
2702 def STrib_indexed_shl_nv_V4 : NVInst_V4<(outs),
2703             (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$src3, IntRegs:$src4),
2704             "memb($src1+$src2<<#$src3) = $src4.new",
2705             []>,
2706             Requires<[HasV4T]>;
2707
2708 // memb(Ru<<#u2+#U6)=Nt.new
2709 let mayStore = 1, AddedComplexity = 10 in
2710 def STrib_shl_nv_V4 : NVInst_V4<(outs),
2711             (ins IntRegs:$src1, u2Imm:$src2, u6Imm:$src3, IntRegs:$src4),
2712             "memb($src1<<#$src2+#$src3) = $src4.new",
2713             []>,
2714             Requires<[HasV4T]>;
2715
2716 // memb(Rx++#s4:0)=Nt.new
2717 let mayStore = 1, hasCtrlDep = 1, isPredicable = 1  in
2718 def POST_STbri_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
2719             (ins IntRegs:$src1, IntRegs:$src2, s4_0Imm:$offset),
2720             "memb($src2++#$offset) = $src1.new",
2721             [],
2722             "$src2 = $dst">,
2723             Requires<[HasV4T]>;
2724
2725 // memb(Rx++#s4:0:circ(Mu))=Nt.new
2726 // memb(Rx++I:circ(Mu))=Nt.new
2727 // memb(Rx++Mu)=Nt.new
2728 // memb(Rx++Mu:brev)=Nt.new
2729
2730 // memb(gp+#u16:0)=Nt.new
2731 let mayStore = 1, neverHasSideEffects = 1 in
2732 def STrib_GP_nv_V4 : NVInst_V4<(outs),
2733             (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),
2734             "memb(#$global+$offset) = $src.new",
2735             []>,
2736             Requires<[HasV4T]>;
2737
2738 // memb(#global)=Nt.new
2739 let mayStore = 1, neverHasSideEffects = 1 in
2740 def STb_GP_nv_V4 : NVInst_V4<(outs),
2741             (ins globaladdress:$global, IntRegs:$src),
2742             "memb(#$global) = $src.new",
2743             []>,
2744             Requires<[HasV4T]>;
2745
2746 // Store new-value byte conditionally.
2747 // if ([!]Pv[.new]) memb(#u6)=Nt.new
2748 // if (Pv) memb(Rs+#u6:0)=Nt.new
2749 let mayStore = 1, neverHasSideEffects = 1,
2750     isPredicated = 1 in
2751 def STrib_cPt_nv_V4 : NVInst_V4<(outs),
2752             (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
2753             "if ($src1) memb($addr) = $src2.new",
2754             []>,
2755             Requires<[HasV4T]>;
2756
2757 // if (Pv.new) memb(Rs+#u6:0)=Nt.new
2758 let mayStore = 1, neverHasSideEffects = 1,
2759     isPredicated = 1 in
2760 def STrib_cdnPt_nv_V4 : NVInst_V4<(outs),
2761             (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
2762             "if ($src1.new) memb($addr) = $src2.new",
2763             []>,
2764             Requires<[HasV4T]>;
2765
2766 // if (!Pv) memb(Rs+#u6:0)=Nt.new
2767 let mayStore = 1, neverHasSideEffects = 1,
2768     isPredicated = 1 in
2769 def STrib_cNotPt_nv_V4 : NVInst_V4<(outs),
2770             (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
2771             "if (!$src1) memb($addr) = $src2.new",
2772             []>,
2773             Requires<[HasV4T]>;
2774
2775 // if (!Pv.new) memb(Rs+#u6:0)=Nt.new
2776 let mayStore = 1, neverHasSideEffects = 1,
2777     isPredicated = 1 in
2778 def STrib_cdnNotPt_nv_V4 : NVInst_V4<(outs),
2779             (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
2780             "if (!$src1.new) memb($addr) = $src2.new",
2781             []>,
2782             Requires<[HasV4T]>;
2783
2784 // if (Pv) memb(Rs+#u6:0)=Nt.new
2785 let mayStore = 1, neverHasSideEffects = 1,
2786     isPredicated = 1 in
2787 def STrib_indexed_cPt_nv_V4 : NVInst_V4<(outs),
2788             (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, IntRegs:$src4),
2789             "if ($src1) memb($src2+#$src3) = $src4.new",
2790             []>,
2791             Requires<[HasV4T]>;
2792
2793 // if (Pv.new) memb(Rs+#u6:0)=Nt.new
2794 let mayStore = 1, neverHasSideEffects = 1,
2795     isPredicated = 1 in
2796 def STrib_indexed_cdnPt_nv_V4 : NVInst_V4<(outs),
2797             (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, IntRegs:$src4),
2798             "if ($src1.new) memb($src2+#$src3) = $src4.new",
2799             []>,
2800             Requires<[HasV4T]>;
2801
2802 // if (!Pv) memb(Rs+#u6:0)=Nt.new
2803 let mayStore = 1, neverHasSideEffects = 1,
2804     isPredicated = 1 in
2805 def STrib_indexed_cNotPt_nv_V4 : NVInst_V4<(outs),
2806             (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, IntRegs:$src4),
2807             "if (!$src1) memb($src2+#$src3) = $src4.new",
2808             []>,
2809             Requires<[HasV4T]>;
2810
2811 // if (!Pv.new) memb(Rs+#u6:0)=Nt.new
2812 let mayStore = 1, neverHasSideEffects = 1,
2813     isPredicated = 1 in
2814 def STrib_indexed_cdnNotPt_nv_V4 : NVInst_V4<(outs),
2815             (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, IntRegs:$src4),
2816             "if (!$src1.new) memb($src2+#$src3) = $src4.new",
2817             []>,
2818             Requires<[HasV4T]>;
2819
2820
2821 // if ([!]Pv[.new]) memb(Rs+Ru<<#u2)=Nt.new
2822 // if (Pv) memb(Rs+Ru<<#u2)=Nt.new
2823 let mayStore = 1, AddedComplexity = 10,
2824     isPredicated = 1 in
2825 def STrib_indexed_shl_cPt_nv_V4 : NVInst_V4<(outs),
2826             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
2827                  IntRegs:$src5),
2828             "if ($src1) memb($src2+$src3<<#$src4) = $src5.new",
2829             []>,
2830             Requires<[HasV4T]>;
2831
2832 // if (Pv.new) memb(Rs+Ru<<#u2)=Nt.new
2833 let mayStore = 1, AddedComplexity = 10,
2834     isPredicated = 1 in
2835 def STrib_indexed_shl_cdnPt_nv_V4 : NVInst_V4<(outs),
2836             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
2837                  IntRegs:$src5),
2838             "if ($src1.new) memb($src2+$src3<<#$src4) = $src5.new",
2839             []>,
2840             Requires<[HasV4T]>;
2841
2842 // if (!Pv) memb(Rs+Ru<<#u2)=Nt.new
2843 let mayStore = 1, AddedComplexity = 10,
2844     isPredicated = 1 in
2845 def STrib_indexed_shl_cNotPt_nv_V4 : NVInst_V4<(outs),
2846             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
2847                  IntRegs:$src5),
2848             "if (!$src1) memb($src2+$src3<<#$src4) = $src5.new",
2849             []>,
2850             Requires<[HasV4T]>;
2851
2852 // if (!Pv.new) memb(Rs+Ru<<#u2)=Nt.new
2853 let mayStore = 1, AddedComplexity = 10,
2854     isPredicated = 1 in
2855 def STrib_indexed_shl_cdnNotPt_nv_V4 : NVInst_V4<(outs),
2856             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
2857                  IntRegs:$src5),
2858             "if (!$src1.new) memb($src2+$src3<<#$src4) = $src5.new",
2859             []>,
2860             Requires<[HasV4T]>;
2861
2862 // if ([!]Pv[.new]) memb(Rx++#s4:0)=Nt.new
2863 // if (Pv) memb(Rx++#s4:0)=Nt.new
2864 let mayStore = 1, hasCtrlDep = 1,
2865     isPredicated = 1 in
2866 def POST_STbri_cPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
2867             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_0Imm:$offset),
2868             "if ($src1) memb($src3++#$offset) = $src2.new",
2869             [],"$src3 = $dst">,
2870             Requires<[HasV4T]>;
2871
2872 // if (Pv.new) memb(Rx++#s4:0)=Nt.new
2873 let mayStore = 1, hasCtrlDep = 1,
2874     isPredicated = 1 in
2875 def POST_STbri_cdnPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
2876             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_0Imm:$offset),
2877             "if ($src1.new) memb($src3++#$offset) = $src2.new",
2878             [],"$src3 = $dst">,
2879             Requires<[HasV4T]>;
2880
2881 // if (!Pv) memb(Rx++#s4:0)=Nt.new
2882 let mayStore = 1, hasCtrlDep = 1,
2883     isPredicated = 1 in
2884 def POST_STbri_cNotPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
2885             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_0Imm:$offset),
2886             "if (!$src1) memb($src3++#$offset) = $src2.new",
2887             [],"$src3 = $dst">,
2888             Requires<[HasV4T]>;
2889
2890 // if (!Pv.new) memb(Rx++#s4:0)=Nt.new
2891 let mayStore = 1, hasCtrlDep = 1,
2892     isPredicated = 1 in
2893 def POST_STbri_cdnNotPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
2894             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_0Imm:$offset),
2895             "if (!$src1.new) memb($src3++#$offset) = $src2.new",
2896             [],"$src3 = $dst">,
2897             Requires<[HasV4T]>;
2898
2899
2900 // Store new-value halfword.
2901 // memh(Re=#U6)=Nt.new
2902 // memh(Rs+#s11:1)=Nt.new
2903 let mayStore = 1, isPredicable = 1 in
2904 def STrih_nv_V4 : NVInst_V4<(outs), (ins MEMri:$addr, IntRegs:$src1),
2905             "memh($addr) = $src1.new",
2906             []>,
2907             Requires<[HasV4T]>;
2908
2909 let mayStore = 1, isPredicable = 1 in
2910 def STrih_indexed_nv_V4 : NVInst_V4<(outs),
2911             (ins IntRegs:$src1, s11_1Imm:$src2, IntRegs:$src3),
2912             "memh($src1+#$src2) = $src3.new",
2913             []>,
2914             Requires<[HasV4T]>;
2915
2916 // memh(Rs+Ru<<#u2)=Nt.new
2917 let mayStore = 1, AddedComplexity = 10, isPredicable = 1 in
2918 def STrih_indexed_shl_nv_V4 : NVInst_V4<(outs),
2919             (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$src3, IntRegs:$src4),
2920             "memh($src1+$src2<<#$src3) = $src4.new",
2921             []>,
2922             Requires<[HasV4T]>;
2923
2924 // memh(Ru<<#u2+#U6)=Nt.new
2925 let mayStore = 1, AddedComplexity = 10 in
2926 def STrih_shl_nv_V4 : NVInst_V4<(outs),
2927             (ins IntRegs:$src1, u2Imm:$src2, u6Imm:$src3, IntRegs:$src4),
2928             "memh($src1<<#$src2+#$src3) = $src4.new",
2929             []>,
2930             Requires<[HasV4T]>;
2931
2932 // memh(Rx++#s4:1)=Nt.new
2933 let mayStore = 1, hasCtrlDep = 1, isPredicable = 1  in
2934 def POST_SThri_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
2935             (ins IntRegs:$src1, IntRegs:$src2, s4_1Imm:$offset),
2936             "memh($src2++#$offset) = $src1.new",
2937             [],
2938             "$src2 = $dst">,
2939             Requires<[HasV4T]>;
2940
2941 // memh(Rx++#s4:1:circ(Mu))=Nt.new
2942 // memh(Rx++I:circ(Mu))=Nt.new
2943 // memh(Rx++Mu)=Nt.new
2944 // memh(Rx++Mu:brev)=Nt.new
2945
2946 // memh(gp+#u16:1)=Nt.new
2947 let mayStore = 1, neverHasSideEffects = 1 in
2948 def STrih_GP_nv_V4 : NVInst_V4<(outs),
2949             (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),
2950             "memh(#$global+$offset) = $src.new",
2951             []>,
2952             Requires<[HasV4T]>;
2953
2954 // memh(#global)=Nt.new
2955 let mayStore = 1, neverHasSideEffects = 1 in
2956 def STh_GP_nv_V4 : NVInst_V4<(outs),
2957             (ins globaladdress:$global, IntRegs:$src),
2958             "memh(#$global) = $src.new",
2959             []>,
2960             Requires<[HasV4T]>;
2961
2962
2963 // Store new-value halfword conditionally.
2964
2965 // if ([!]Pv[.new]) memh(#u6)=Nt.new
2966
2967 // if ([!]Pv[.new]) memh(Rs+#u6:1)=Nt.new
2968 // if (Pv) memh(Rs+#u6:1)=Nt.new
2969 let mayStore = 1, neverHasSideEffects = 1,
2970     isPredicated = 1 in
2971 def STrih_cPt_nv_V4 : NVInst_V4<(outs),
2972             (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
2973             "if ($src1) memh($addr) = $src2.new",
2974             []>,
2975             Requires<[HasV4T]>;
2976
2977 // if (Pv.new) memh(Rs+#u6:1)=Nt.new
2978 let mayStore = 1, neverHasSideEffects = 1,
2979     isPredicated = 1 in
2980 def STrih_cdnPt_nv_V4 : NVInst_V4<(outs),
2981             (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
2982             "if ($src1.new) memh($addr) = $src2.new",
2983             []>,
2984             Requires<[HasV4T]>;
2985
2986 // if (!Pv) memh(Rs+#u6:1)=Nt.new
2987 let mayStore = 1, neverHasSideEffects = 1,
2988     isPredicated = 1 in
2989 def STrih_cNotPt_nv_V4 : NVInst_V4<(outs),
2990             (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
2991             "if (!$src1) memh($addr) = $src2.new",
2992             []>,
2993             Requires<[HasV4T]>;
2994
2995 // if (!Pv.new) memh(Rs+#u6:1)=Nt.new
2996 let mayStore = 1, neverHasSideEffects = 1,
2997     isPredicated = 1 in
2998 def STrih_cdnNotPt_nv_V4 : NVInst_V4<(outs),
2999             (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
3000             "if (!$src1.new) memh($addr) = $src2.new",
3001             []>,
3002             Requires<[HasV4T]>;
3003
3004 // if (Pv) memh(Rs+#u6:1)=Nt.new
3005 let mayStore = 1, neverHasSideEffects = 1,
3006     isPredicated = 1 in
3007 def STrih_indexed_cPt_nv_V4 : NVInst_V4<(outs),
3008             (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, IntRegs:$src4),
3009             "if ($src1) memh($src2+#$src3) = $src4.new",
3010             []>,
3011             Requires<[HasV4T]>;
3012
3013 // if (Pv.new) memh(Rs+#u6:1)=Nt.new
3014 let mayStore = 1, neverHasSideEffects = 1,
3015     isPredicated = 1 in
3016 def STrih_indexed_cdnPt_nv_V4 : NVInst_V4<(outs),
3017             (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, IntRegs:$src4),
3018             "if ($src1.new) memh($src2+#$src3) = $src4.new",
3019             []>,
3020             Requires<[HasV4T]>;
3021
3022 // if (!Pv) memh(Rs+#u6:1)=Nt.new
3023 let mayStore = 1, neverHasSideEffects = 1,
3024     isPredicated = 1 in
3025 def STrih_indexed_cNotPt_nv_V4 : NVInst_V4<(outs),
3026             (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, IntRegs:$src4),
3027             "if (!$src1) memh($src2+#$src3) = $src4.new",
3028             []>,
3029             Requires<[HasV4T]>;
3030
3031 // if (!Pv.new) memh(Rs+#u6:1)=Nt.new
3032 let mayStore = 1, neverHasSideEffects = 1,
3033     isPredicated = 1 in
3034 def STrih_indexed_cdnNotPt_nv_V4 : NVInst_V4<(outs),
3035             (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, IntRegs:$src4),
3036             "if (!$src1.new) memh($src2+#$src3) = $src4.new",
3037             []>,
3038             Requires<[HasV4T]>;
3039
3040 // if ([!]Pv[.new]) memh(Rs+Ru<<#u2)=Nt.new
3041 // if (Pv) memh(Rs+Ru<<#u2)=Nt.new
3042 let mayStore = 1, AddedComplexity = 10,
3043     isPredicated = 1 in
3044 def STrih_indexed_shl_cPt_nv_V4 : NVInst_V4<(outs),
3045             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
3046                  IntRegs:$src5),
3047             "if ($src1) memh($src2+$src3<<#$src4) = $src5.new",
3048             []>,
3049             Requires<[HasV4T]>;
3050
3051 // if (Pv.new) memh(Rs+Ru<<#u2)=Nt.new
3052 let mayStore = 1, AddedComplexity = 10,
3053     isPredicated = 1 in
3054 def STrih_indexed_shl_cdnPt_nv_V4 : NVInst_V4<(outs),
3055             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
3056                  IntRegs:$src5),
3057             "if ($src1.new) memh($src2+$src3<<#$src4) = $src5.new",
3058             []>,
3059             Requires<[HasV4T]>;
3060
3061 // if (!Pv) memh(Rs+Ru<<#u2)=Nt.new
3062 let mayStore = 1, AddedComplexity = 10,
3063     isPredicated = 1 in
3064 def STrih_indexed_shl_cNotPt_nv_V4 : NVInst_V4<(outs),
3065             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
3066                  IntRegs:$src5),
3067             "if (!$src1) memh($src2+$src3<<#$src4) = $src5.new",
3068             []>,
3069             Requires<[HasV4T]>;
3070
3071 // if (!Pv.new) memh(Rs+Ru<<#u2)=Nt.new
3072 let mayStore = 1, AddedComplexity = 10,
3073     isPredicated = 1 in
3074 def STrih_indexed_shl_cdnNotPt_nv_V4 : NVInst_V4<(outs),
3075             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
3076                  IntRegs:$src5),
3077             "if (!$src1.new) memh($src2+$src3<<#$src4) = $src5.new",
3078             []>,
3079             Requires<[HasV4T]>;
3080
3081 // if ([!]Pv[]) memh(Rx++#s4:1)=Nt.new
3082 // if (Pv) memh(Rx++#s4:1)=Nt.new
3083 let mayStore = 1, hasCtrlDep = 1,
3084     isPredicated = 1 in
3085 def POST_SThri_cPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
3086             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_1Imm:$offset),
3087             "if ($src1) memh($src3++#$offset) = $src2.new",
3088             [],"$src3 = $dst">,
3089             Requires<[HasV4T]>;
3090
3091 // if (Pv.new) memh(Rx++#s4:1)=Nt.new
3092 let mayStore = 1, hasCtrlDep = 1,
3093     isPredicated = 1 in
3094 def POST_SThri_cdnPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
3095             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_1Imm:$offset),
3096             "if ($src1.new) memh($src3++#$offset) = $src2.new",
3097             [],"$src3 = $dst">,
3098             Requires<[HasV4T]>;
3099
3100 // if (!Pv) memh(Rx++#s4:1)=Nt.new
3101 let mayStore = 1, hasCtrlDep = 1,
3102     isPredicated = 1 in
3103 def POST_SThri_cNotPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
3104             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_1Imm:$offset),
3105             "if (!$src1) memh($src3++#$offset) = $src2.new",
3106             [],"$src3 = $dst">,
3107             Requires<[HasV4T]>;
3108
3109 // if (!Pv.new) memh(Rx++#s4:1)=Nt.new
3110 let mayStore = 1, hasCtrlDep = 1,
3111     isPredicated = 1 in
3112 def POST_SThri_cdnNotPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
3113             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_1Imm:$offset),
3114             "if (!$src1.new) memh($src3++#$offset) = $src2.new",
3115             [],"$src3 = $dst">,
3116             Requires<[HasV4T]>;
3117
3118
3119 // Store new-value word.
3120
3121 // memw(Re=#U6)=Nt.new
3122 // memw(Rs+#s11:2)=Nt.new
3123 let mayStore = 1, isPredicable = 1 in
3124 def STriw_nv_V4 : NVInst_V4<(outs),
3125             (ins MEMri:$addr, IntRegs:$src1),
3126             "memw($addr) = $src1.new",
3127             []>,
3128             Requires<[HasV4T]>;
3129
3130 let mayStore = 1, isPredicable = 1 in
3131 def STriw_indexed_nv_V4 : NVInst_V4<(outs),
3132             (ins IntRegs:$src1, s11_2Imm:$src2, IntRegs:$src3),
3133             "memw($src1+#$src2) = $src3.new",
3134             []>,
3135             Requires<[HasV4T]>;
3136
3137 // memw(Rs+Ru<<#u2)=Nt.new
3138 let mayStore = 1, AddedComplexity = 10, isPredicable = 1 in
3139 def STriw_indexed_shl_nv_V4 : NVInst_V4<(outs),
3140             (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$src3, IntRegs:$src4),
3141             "memw($src1+$src2<<#$src3) = $src4.new",
3142             []>,
3143             Requires<[HasV4T]>;
3144
3145 // memw(Ru<<#u2+#U6)=Nt.new
3146 let mayStore = 1, AddedComplexity = 10 in
3147 def STriw_shl_nv_V4 : NVInst_V4<(outs),
3148             (ins IntRegs:$src1, u2Imm:$src2, u6Imm:$src3, IntRegs:$src4),
3149             "memw($src1<<#$src2+#$src3) = $src4.new",
3150             []>,
3151             Requires<[HasV4T]>;
3152
3153 // memw(Rx++#s4:2)=Nt.new
3154 let mayStore = 1, hasCtrlDep = 1, isPredicable = 1  in
3155 def POST_STwri_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
3156             (ins IntRegs:$src1, IntRegs:$src2, s4_2Imm:$offset),
3157             "memw($src2++#$offset) = $src1.new",
3158             [],
3159             "$src2 = $dst">,
3160             Requires<[HasV4T]>;
3161
3162 // memw(Rx++#s4:2:circ(Mu))=Nt.new
3163 // memw(Rx++I:circ(Mu))=Nt.new
3164 // memw(Rx++Mu)=Nt.new
3165 // memw(Rx++Mu:brev)=Nt.new
3166 // memw(gp+#u16:2)=Nt.new
3167 let mayStore = 1, neverHasSideEffects = 1 in
3168 def STriw_GP_nv_V4 : NVInst_V4<(outs),
3169             (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),
3170             "memw(#$global+$offset) = $src.new",
3171             []>,
3172             Requires<[HasV4T]>;
3173
3174 let mayStore = 1, neverHasSideEffects = 1 in
3175 def STw_GP_nv_V4 : NVInst_V4<(outs),
3176             (ins globaladdress:$global, IntRegs:$src),
3177             "memw(#$global) = $src.new",
3178             []>,
3179             Requires<[HasV4T]>;
3180
3181 // Store new-value word conditionally.
3182
3183 // if ([!]Pv[.new]) memw(#u6)=Nt.new
3184
3185 // if ([!]Pv[.new]) memw(Rs+#u6:2)=Nt.new
3186 // if (Pv) memw(Rs+#u6:2)=Nt.new
3187 let mayStore = 1, neverHasSideEffects = 1,
3188     isPredicated = 1 in
3189 def STriw_cPt_nv_V4 : NVInst_V4<(outs),
3190             (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
3191             "if ($src1) memw($addr) = $src2.new",
3192             []>,
3193             Requires<[HasV4T]>;
3194
3195 // if (Pv.new) memw(Rs+#u6:2)=Nt.new
3196 let mayStore = 1, neverHasSideEffects = 1,
3197     isPredicated = 1 in
3198 def STriw_cdnPt_nv_V4 : NVInst_V4<(outs),
3199             (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
3200             "if ($src1.new) memw($addr) = $src2.new",
3201             []>,
3202             Requires<[HasV4T]>;
3203
3204 // if (!Pv) memw(Rs+#u6:2)=Nt.new
3205 let mayStore = 1, neverHasSideEffects = 1,
3206     isPredicated = 1 in
3207 def STriw_cNotPt_nv_V4 : NVInst_V4<(outs),
3208             (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
3209             "if (!$src1) memw($addr) = $src2.new",
3210             []>,
3211             Requires<[HasV4T]>;
3212
3213 // if (!Pv.new) memw(Rs+#u6:2)=Nt.new
3214 let mayStore = 1, neverHasSideEffects = 1,
3215     isPredicated = 1 in
3216 def STriw_cdnNotPt_nv_V4 : NVInst_V4<(outs),
3217             (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
3218             "if (!$src1.new) memw($addr) = $src2.new",
3219             []>,
3220             Requires<[HasV4T]>;
3221
3222 // if (Pv) memw(Rs+#u6:2)=Nt.new
3223 let mayStore = 1, neverHasSideEffects = 1,
3224     isPredicated = 1 in
3225 def STriw_indexed_cPt_nv_V4 : NVInst_V4<(outs),
3226             (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, IntRegs:$src4),
3227             "if ($src1) memw($src2+#$src3) = $src4.new",
3228             []>,
3229             Requires<[HasV4T]>;
3230
3231 // if (Pv.new) memw(Rs+#u6:2)=Nt.new
3232 let mayStore = 1, neverHasSideEffects = 1,
3233     isPredicated = 1 in
3234 def STriw_indexed_cdnPt_nv_V4 : NVInst_V4<(outs),
3235             (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, IntRegs:$src4),
3236             "if ($src1.new) memw($src2+#$src3) = $src4.new",
3237             []>,
3238             Requires<[HasV4T]>;
3239
3240 // if (!Pv) memw(Rs+#u6:2)=Nt.new
3241 let mayStore = 1, neverHasSideEffects = 1,
3242     isPredicated = 1 in
3243 def STriw_indexed_cNotPt_nv_V4 : NVInst_V4<(outs),
3244             (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, IntRegs:$src4),
3245             "if (!$src1) memw($src2+#$src3) = $src4.new",
3246             []>,
3247             Requires<[HasV4T]>;
3248
3249 // if (!Pv.new) memw(Rs+#u6:2)=Nt.new
3250 let mayStore = 1, neverHasSideEffects = 1,
3251     isPredicated = 1 in
3252 def STriw_indexed_cdnNotPt_nv_V4 : NVInst_V4<(outs),
3253             (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, IntRegs:$src4),
3254             "if (!$src1.new) memw($src2+#$src3) = $src4.new",
3255             []>,
3256             Requires<[HasV4T]>;
3257
3258
3259 // if ([!]Pv[.new]) memw(Rs+Ru<<#u2)=Nt.new
3260 // if (Pv) memw(Rs+Ru<<#u2)=Nt.new
3261 let mayStore = 1, AddedComplexity = 10,
3262     isPredicated = 1 in
3263 def STriw_indexed_shl_cPt_nv_V4 : NVInst_V4<(outs),
3264             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
3265                  IntRegs:$src5),
3266             "if ($src1) memw($src2+$src3<<#$src4) = $src5.new",
3267             []>,
3268             Requires<[HasV4T]>;
3269
3270 // if (Pv.new) memw(Rs+Ru<<#u2)=Nt.new
3271 let mayStore = 1, AddedComplexity = 10,
3272     isPredicated = 1 in
3273 def STriw_indexed_shl_cdnPt_nv_V4 : NVInst_V4<(outs),
3274             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
3275                  IntRegs:$src5),
3276             "if ($src1.new) memw($src2+$src3<<#$src4) = $src5.new",
3277             []>,
3278             Requires<[HasV4T]>;
3279
3280 // if (!Pv) memw(Rs+Ru<<#u2)=Nt.new
3281 let mayStore = 1, AddedComplexity = 10,
3282     isPredicated = 1 in
3283 def STriw_indexed_shl_cNotPt_nv_V4 : NVInst_V4<(outs),
3284             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
3285                  IntRegs:$src5),
3286             "if (!$src1) memw($src2+$src3<<#$src4) = $src5.new",
3287             []>,
3288             Requires<[HasV4T]>;
3289
3290 // if (!Pv.new) memw(Rs+Ru<<#u2)=Nt.new
3291 let mayStore = 1, AddedComplexity = 10,
3292     isPredicated = 1 in
3293 def STriw_indexed_shl_cdnNotPt_nv_V4 : NVInst_V4<(outs),
3294             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
3295                  IntRegs:$src5),
3296             "if (!$src1.new) memw($src2+$src3<<#$src4) = $src5.new",
3297             []>,
3298             Requires<[HasV4T]>;
3299
3300 // if ([!]Pv[.new]) memw(Rx++#s4:2)=Nt.new
3301 // if (Pv) memw(Rx++#s4:2)=Nt.new
3302 let mayStore = 1, hasCtrlDep = 1,
3303     isPredicated = 1 in
3304 def POST_STwri_cPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
3305             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset),
3306             "if ($src1) memw($src3++#$offset) = $src2.new",
3307             [],"$src3 = $dst">,
3308             Requires<[HasV4T]>;
3309
3310 // if (Pv.new) memw(Rx++#s4:2)=Nt.new
3311 let mayStore = 1, hasCtrlDep = 1,
3312     isPredicated = 1 in
3313 def POST_STwri_cdnPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
3314             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset),
3315             "if ($src1.new) memw($src3++#$offset) = $src2.new",
3316             [],"$src3 = $dst">,
3317             Requires<[HasV4T]>;
3318
3319 // if (!Pv) memw(Rx++#s4:2)=Nt.new
3320 let mayStore = 1, hasCtrlDep = 1,
3321     isPredicated = 1 in
3322 def POST_STwri_cNotPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
3323             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset),
3324             "if (!$src1) memw($src3++#$offset) = $src2.new",
3325             [],"$src3 = $dst">,
3326             Requires<[HasV4T]>;
3327
3328 // if (!Pv.new) memw(Rx++#s4:2)=Nt.new
3329 let mayStore = 1, hasCtrlDep = 1,
3330     isPredicated = 1 in
3331 def POST_STwri_cdnNotPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
3332             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset),
3333             "if (!$src1.new) memw($src3++#$offset) = $src2.new",
3334             [],"$src3 = $dst">,
3335             Requires<[HasV4T]>;
3336
3337
3338
3339 // if (Pv) memb(##global) = Rt
3340 let mayStore = 1, neverHasSideEffects = 1 in
3341 def STb_GP_cPt_nv_V4 : NVInst_V4<(outs),
3342             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
3343             "if ($src1) memb(##$global) = $src2.new",
3344             []>,
3345             Requires<[HasV4T]>;
3346
3347 // if (!Pv) memb(##global) = Rt
3348 let mayStore = 1, neverHasSideEffects = 1 in
3349 def STb_GP_cNotPt_nv_V4 : NVInst_V4<(outs),
3350             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
3351             "if (!$src1) memb(##$global) = $src2.new",
3352             []>,
3353             Requires<[HasV4T]>;
3354
3355 // if (Pv) memb(##global) = Rt
3356 let mayStore = 1, neverHasSideEffects = 1 in
3357 def STb_GP_cdnPt_nv_V4 : NVInst_V4<(outs),
3358             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
3359             "if ($src1.new) memb(##$global) = $src2.new",
3360             []>,
3361             Requires<[HasV4T]>;
3362
3363 // if (!Pv) memb(##global) = Rt
3364 let mayStore = 1, neverHasSideEffects = 1 in
3365 def STb_GP_cdnNotPt_nv_V4 : NVInst_V4<(outs),
3366             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
3367             "if (!$src1.new) memb(##$global) = $src2.new",
3368             []>,
3369             Requires<[HasV4T]>;
3370
3371 // if (Pv) memh(##global) = Rt
3372 let mayStore = 1, neverHasSideEffects = 1 in
3373 def STh_GP_cPt_nv_V4 : NVInst_V4<(outs),
3374             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
3375             "if ($src1) memh(##$global) = $src2.new",
3376             []>,
3377             Requires<[HasV4T]>;
3378
3379 // if (!Pv) memh(##global) = Rt
3380 let mayStore = 1, neverHasSideEffects = 1 in
3381 def STh_GP_cNotPt_nv_V4 : NVInst_V4<(outs),
3382             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
3383             "if (!$src1) memh(##$global) = $src2.new",
3384             []>,
3385             Requires<[HasV4T]>;
3386
3387 // if (Pv) memh(##global) = Rt
3388 let mayStore = 1, neverHasSideEffects = 1 in
3389 def STh_GP_cdnPt_nv_V4 : NVInst_V4<(outs),
3390             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
3391             "if ($src1.new) memh(##$global) = $src2.new",
3392             []>,
3393             Requires<[HasV4T]>;
3394
3395 // if (!Pv) memh(##global) = Rt
3396 let mayStore = 1, neverHasSideEffects = 1 in
3397 def STh_GP_cdnNotPt_nv_V4 : NVInst_V4<(outs),
3398             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
3399             "if (!$src1.new) memh(##$global) = $src2.new",
3400             []>,
3401             Requires<[HasV4T]>;
3402
3403 // if (Pv) memw(##global) = Rt
3404 let mayStore = 1, neverHasSideEffects = 1 in
3405 def STw_GP_cPt_nv_V4 : NVInst_V4<(outs),
3406             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
3407             "if ($src1) memw(##$global) = $src2.new",
3408             []>,
3409             Requires<[HasV4T]>;
3410
3411 // if (!Pv) memw(##global) = Rt
3412 let mayStore = 1, neverHasSideEffects = 1 in
3413 def STw_GP_cNotPt_nv_V4 : NVInst_V4<(outs),
3414             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
3415             "if (!$src1) memw(##$global) = $src2.new",
3416             []>,
3417             Requires<[HasV4T]>;
3418
3419 // if (Pv) memw(##global) = Rt
3420 let mayStore = 1, neverHasSideEffects = 1 in
3421 def STw_GP_cdnPt_nv_V4 : NVInst_V4<(outs),
3422             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
3423             "if ($src1.new) memw(##$global) = $src2.new",
3424             []>,
3425             Requires<[HasV4T]>;
3426
3427 // if (!Pv) memw(##global) = Rt
3428 let mayStore = 1, neverHasSideEffects = 1 in
3429 def STw_GP_cdnNotPt_nv_V4 : NVInst_V4<(outs),
3430             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
3431             "if (!$src1.new) memw(##$global) = $src2.new",
3432             []>,
3433             Requires<[HasV4T]>;
3434
3435 let mayStore = 1, neverHasSideEffects = 1 in
3436 def STrib_GP_cPt_nv_V4 : NVInst_V4<(outs),
3437             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
3438                                                         IntRegs:$src2),
3439             "if ($src1) memb(##$global+$offset) = $src2.new",
3440             []>,
3441             Requires<[HasV4T]>;
3442
3443 let mayStore = 1, neverHasSideEffects = 1 in
3444 def STrib_GP_cNotPt_nv_V4 : NVInst_V4<(outs),
3445             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
3446                                                         IntRegs:$src2),
3447             "if (!$src1) memb(##$global+$offset) = $src2.new",
3448             []>,
3449             Requires<[HasV4T]>;
3450
3451 let mayStore = 1, neverHasSideEffects = 1 in
3452 def STrib_GP_cdnPt_nv_V4 : NVInst_V4<(outs),
3453             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
3454                                                         IntRegs:$src2),
3455             "if ($src1.new) memb(##$global+$offset) = $src2.new",
3456             []>,
3457             Requires<[HasV4T]>;
3458
3459 let mayStore = 1, neverHasSideEffects = 1 in
3460 def STrib_GP_cdnNotPt_nv_V4 : NVInst_V4<(outs),
3461             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
3462                                                         IntRegs:$src2),
3463             "if (!$src1.new) memb(##$global+$offset) = $src2.new",
3464             []>,
3465             Requires<[HasV4T]>;
3466
3467 let mayStore = 1, neverHasSideEffects = 1 in
3468 def STrih_GP_cPt_nv_V4 : NVInst_V4<(outs),
3469             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
3470                                                         IntRegs:$src2),
3471             "if ($src1) memh(##$global+$offset) = $src2.new",
3472             []>,
3473             Requires<[HasV4T]>;
3474
3475 let mayStore = 1, neverHasSideEffects = 1 in
3476 def STrih_GP_cNotPt_nv_V4 : NVInst_V4<(outs),
3477             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
3478                                                         IntRegs:$src2),
3479             "if (!$src1) memh(##$global+$offset) = $src2.new",
3480             []>,
3481             Requires<[HasV4T]>;
3482
3483 let mayStore = 1, neverHasSideEffects = 1 in
3484 def STrih_GP_cdnPt_nv_V4 : NVInst_V4<(outs),
3485             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
3486                                                         IntRegs:$src2),
3487             "if ($src1.new) memh(##$global+$offset) = $src2.new",
3488             []>,
3489             Requires<[HasV4T]>;
3490
3491 let mayStore = 1, neverHasSideEffects = 1 in
3492 def STrih_GP_cdnNotPt_nv_V4 : NVInst_V4<(outs),
3493             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
3494                                                         IntRegs:$src2),
3495             "if (!$src1.new) memh(##$global+$offset) = $src2.new",
3496             []>,
3497             Requires<[HasV4T]>;
3498
3499 let mayStore = 1, neverHasSideEffects = 1 in
3500 def STriw_GP_cPt_nv_V4 : NVInst_V4<(outs),
3501             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
3502                                                         IntRegs:$src2),
3503             "if ($src1) memw(##$global+$offset) = $src2.new",
3504             []>,
3505             Requires<[HasV4T]>;
3506
3507 let mayStore = 1, neverHasSideEffects = 1 in
3508 def STriw_GP_cNotPt_nv_V4 : NVInst_V4<(outs),
3509             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
3510                                                         IntRegs:$src2),
3511             "if (!$src1) memw(##$global+$offset) = $src2.new",
3512             []>,
3513             Requires<[HasV4T]>;
3514
3515 let mayStore = 1, neverHasSideEffects = 1 in
3516 def STriw_GP_cdnPt_nv_V4 : NVInst_V4<(outs),
3517             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
3518                                                         IntRegs:$src2),
3519             "if ($src1.new) memw(##$global+$offset) = $src2.new",
3520             []>,
3521             Requires<[HasV4T]>;
3522
3523 let mayStore = 1, neverHasSideEffects = 1 in
3524 def STriw_GP_cdnNotPt_nv_V4 : NVInst_V4<(outs),
3525             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
3526                                                         IntRegs:$src2),
3527             "if (!$src1.new) memw(##$global+$offset) = $src2.new",
3528             []>,
3529             Requires<[HasV4T]>;
3530
3531 //===----------------------------------------------------------------------===//
3532 // NV/ST -
3533 //===----------------------------------------------------------------------===//
3534
3535 //===----------------------------------------------------------------------===//
3536 // NV/J +
3537 //===----------------------------------------------------------------------===//
3538
3539 multiclass NVJ_type_basic_reg<string NotStr, string OpcStr, string TakenStr> {
3540   def _ie_nv_V4 : NVInst_V4<(outs),
3541             (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset),
3542             !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
3543             !strconcat("($src1.new, $src2)) jump:",
3544             !strconcat(TakenStr, " $offset"))))),
3545             []>,
3546             Requires<[HasV4T]>;
3547
3548   def _nv_V4 : NVInst_V4<(outs),
3549             (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset),
3550             !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
3551             !strconcat("($src1.new, $src2)) jump:",
3552             !strconcat(TakenStr, " $offset"))))),
3553             []>,
3554             Requires<[HasV4T]>;
3555 }
3556
3557 multiclass NVJ_type_basic_2ndDotNew<string NotStr, string OpcStr,
3558                                                    string TakenStr> {
3559   def _ie_nv_V4 : NVInst_V4<(outs),
3560             (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset),
3561             !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
3562             !strconcat("($src1, $src2.new)) jump:",
3563             !strconcat(TakenStr, " $offset"))))),
3564             []>,
3565             Requires<[HasV4T]>;
3566
3567   def _nv_V4 : NVInst_V4<(outs),
3568             (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset),
3569             !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
3570             !strconcat("($src1, $src2.new)) jump:",
3571             !strconcat(TakenStr, " $offset"))))),
3572             []>,
3573             Requires<[HasV4T]>;
3574 }
3575
3576 multiclass NVJ_type_basic_imm<string NotStr, string OpcStr, string TakenStr> {
3577   def _ie_nv_V4 : NVInst_V4<(outs),
3578             (ins IntRegs:$src1, u5Imm:$src2, brtarget:$offset),
3579             !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
3580             !strconcat("($src1.new, #$src2)) jump:",
3581             !strconcat(TakenStr, " $offset"))))),
3582             []>,
3583             Requires<[HasV4T]>;
3584
3585   def _nv_V4 : NVInst_V4<(outs),
3586             (ins IntRegs:$src1, u5Imm:$src2, brtarget:$offset),
3587             !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
3588             !strconcat("($src1.new, #$src2)) jump:",
3589             !strconcat(TakenStr, " $offset"))))),
3590             []>,
3591             Requires<[HasV4T]>;
3592 }
3593
3594 multiclass NVJ_type_basic_neg<string NotStr, string OpcStr, string TakenStr> {
3595   def _ie_nv_V4 : NVInst_V4<(outs),
3596             (ins IntRegs:$src1, nOneImm:$src2, brtarget:$offset),
3597             !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
3598             !strconcat("($src1.new, #$src2)) jump:",
3599             !strconcat(TakenStr, " $offset"))))),
3600             []>,
3601             Requires<[HasV4T]>;
3602
3603   def _nv_V4 : NVInst_V4<(outs),
3604             (ins IntRegs:$src1, nOneImm:$src2, brtarget:$offset),
3605             !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
3606             !strconcat("($src1.new, #$src2)) jump:",
3607             !strconcat(TakenStr, " $offset"))))),
3608             []>,
3609             Requires<[HasV4T]>;
3610 }
3611
3612 multiclass NVJ_type_basic_tstbit<string NotStr, string OpcStr,
3613                                                 string TakenStr> {
3614   def _ie_nv_V4 : NVInst_V4<(outs),
3615             (ins IntRegs:$src1, u1Imm:$src2, brtarget:$offset),
3616             !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
3617             !strconcat("($src1.new, #$src2)) jump:",
3618             !strconcat(TakenStr, " $offset"))))),
3619             []>,
3620             Requires<[HasV4T]>;
3621
3622   def _nv_V4 : NVInst_V4<(outs),
3623             (ins IntRegs:$src1, u1Imm:$src2, brtarget:$offset),
3624             !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
3625             !strconcat("($src1.new, #$src2)) jump:",
3626             !strconcat(TakenStr, " $offset"))))),
3627             []>,
3628             Requires<[HasV4T]>;
3629 }
3630
3631 // Multiclass for regular dot new of Ist operand register.
3632 multiclass NVJ_type_br_pred_reg<string NotStr, string OpcStr> {
3633   defm Pt  : NVJ_type_basic_reg<NotStr, OpcStr, "t">;
3634   defm Pnt : NVJ_type_basic_reg<NotStr, OpcStr, "nt">;
3635 }
3636
3637 // Multiclass for dot new of 2nd operand register.
3638 multiclass NVJ_type_br_pred_2ndDotNew<string NotStr, string OpcStr> {
3639   defm Pt  : NVJ_type_basic_2ndDotNew<NotStr, OpcStr, "t">;
3640   defm Pnt : NVJ_type_basic_2ndDotNew<NotStr, OpcStr, "nt">;
3641 }
3642
3643 // Multiclass for 2nd operand immediate, including -1.
3644 multiclass NVJ_type_br_pred_imm<string NotStr, string OpcStr> {
3645   defm Pt     : NVJ_type_basic_imm<NotStr, OpcStr, "t">;
3646   defm Pnt    : NVJ_type_basic_imm<NotStr, OpcStr, "nt">;
3647   defm Ptneg  : NVJ_type_basic_neg<NotStr, OpcStr, "t">;
3648   defm Pntneg : NVJ_type_basic_neg<NotStr, OpcStr, "nt">;
3649 }
3650
3651 // Multiclass for 2nd operand immediate, excluding -1.
3652 multiclass NVJ_type_br_pred_imm_only<string NotStr, string OpcStr> {
3653   defm Pt     : NVJ_type_basic_imm<NotStr, OpcStr, "t">;
3654   defm Pnt    : NVJ_type_basic_imm<NotStr, OpcStr, "nt">;
3655 }
3656
3657 // Multiclass for tstbit, where 2nd operand is always #0.
3658 multiclass NVJ_type_br_pred_tstbit<string NotStr, string OpcStr> {
3659   defm Pt     : NVJ_type_basic_tstbit<NotStr, OpcStr, "t">;
3660   defm Pnt    : NVJ_type_basic_tstbit<NotStr, OpcStr, "nt">;
3661 }
3662
3663 // Multiclass for GT.
3664 multiclass NVJ_type_rr_ri<string OpcStr> {
3665   defm rrNot   : NVJ_type_br_pred_reg<"!", OpcStr>;
3666   defm rr      : NVJ_type_br_pred_reg<"",  OpcStr>;
3667   defm rrdnNot : NVJ_type_br_pred_2ndDotNew<"!", OpcStr>;
3668   defm rrdn    : NVJ_type_br_pred_2ndDotNew<"",  OpcStr>;
3669   defm riNot   : NVJ_type_br_pred_imm<"!", OpcStr>;
3670   defm ri      : NVJ_type_br_pred_imm<"",  OpcStr>;
3671 }
3672
3673 // Multiclass for EQ.
3674 multiclass NVJ_type_rr_ri_no_2ndDotNew<string OpcStr> {
3675   defm rrNot   : NVJ_type_br_pred_reg<"!", OpcStr>;
3676   defm rr      : NVJ_type_br_pred_reg<"",  OpcStr>;
3677   defm riNot   : NVJ_type_br_pred_imm<"!", OpcStr>;
3678   defm ri      : NVJ_type_br_pred_imm<"",  OpcStr>;
3679 }
3680
3681 // Multiclass for GTU.
3682 multiclass NVJ_type_rr_ri_no_nOne<string OpcStr> {
3683   defm rrNot   : NVJ_type_br_pred_reg<"!", OpcStr>;
3684   defm rr      : NVJ_type_br_pred_reg<"",  OpcStr>;
3685   defm rrdnNot : NVJ_type_br_pred_2ndDotNew<"!", OpcStr>;
3686   defm rrdn    : NVJ_type_br_pred_2ndDotNew<"",  OpcStr>;
3687   defm riNot   : NVJ_type_br_pred_imm_only<"!", OpcStr>;
3688   defm ri      : NVJ_type_br_pred_imm_only<"",  OpcStr>;
3689 }
3690
3691 // Multiclass for tstbit.
3692 multiclass NVJ_type_r0<string OpcStr> {
3693   defm r0Not : NVJ_type_br_pred_tstbit<"!", OpcStr>;
3694   defm r0    : NVJ_type_br_pred_tstbit<"",  OpcStr>;
3695  }
3696
3697 // Base Multiclass for New Value Jump.
3698 multiclass NVJ_type {
3699   defm GT     : NVJ_type_rr_ri<"cmp.gt">;
3700   defm EQ     : NVJ_type_rr_ri_no_2ndDotNew<"cmp.eq">;
3701   defm GTU    : NVJ_type_rr_ri_no_nOne<"cmp.gtu">;
3702   defm TSTBIT : NVJ_type_r0<"tstbit">;
3703 }
3704
3705 let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC] in {
3706   defm JMP_ : NVJ_type;
3707 }
3708
3709 //===----------------------------------------------------------------------===//
3710 // NV/J -
3711 //===----------------------------------------------------------------------===//
3712
3713 //===----------------------------------------------------------------------===//
3714 // XTYPE/ALU +
3715 //===----------------------------------------------------------------------===//
3716
3717 //  Add and accumulate.
3718 //  Rd=add(Rs,add(Ru,#s6))
3719 def ADDr_ADDri_V4 : MInst<(outs IntRegs:$dst),
3720           (ins IntRegs:$src1, IntRegs:$src2, s6Imm:$src3),
3721           "$dst = add($src1, add($src2, #$src3))",
3722           [(set (i32 IntRegs:$dst),
3723            (add (i32 IntRegs:$src1), (add (i32 IntRegs:$src2),
3724                                           s6ImmPred:$src3)))]>,
3725           Requires<[HasV4T]>;
3726
3727 //  Rd=add(Rs,sub(#s6,Ru))
3728 def ADDr_SUBri_V4 : MInst<(outs IntRegs:$dst),
3729           (ins IntRegs:$src1, s6Imm:$src2, IntRegs:$src3),
3730           "$dst = add($src1, sub(#$src2, $src3))",
3731           [(set (i32 IntRegs:$dst),
3732            (add (i32 IntRegs:$src1), (sub s6ImmPred:$src2,
3733                                           (i32 IntRegs:$src3))))]>,
3734           Requires<[HasV4T]>;
3735
3736 // Generates the same instruction as ADDr_SUBri_V4 but matches different
3737 // pattern.
3738 //  Rd=add(Rs,sub(#s6,Ru))
3739 def ADDri_SUBr_V4 : MInst<(outs IntRegs:$dst),
3740           (ins IntRegs:$src1, s6Imm:$src2, IntRegs:$src3),
3741           "$dst = add($src1, sub(#$src2, $src3))",
3742           [(set (i32 IntRegs:$dst),
3743                 (sub (add (i32 IntRegs:$src1), s6ImmPred:$src2),
3744                      (i32 IntRegs:$src3)))]>,
3745           Requires<[HasV4T]>;
3746
3747
3748 //  Add or subtract doublewords with carry.
3749 //TODO:
3750 //  Rdd=add(Rss,Rtt,Px):carry
3751 //TODO:
3752 //  Rdd=sub(Rss,Rtt,Px):carry
3753
3754
3755 //  Logical doublewords.
3756 //  Rdd=and(Rtt,~Rss)
3757 def ANDd_NOTd_V4 : MInst<(outs DoubleRegs:$dst),
3758           (ins DoubleRegs:$src1, DoubleRegs:$src2),
3759           "$dst = and($src1, ~$src2)",
3760           [(set (i64 DoubleRegs:$dst), (and (i64 DoubleRegs:$src1),
3761                                       (not (i64 DoubleRegs:$src2))))]>,
3762           Requires<[HasV4T]>;
3763
3764 //  Rdd=or(Rtt,~Rss)
3765 def ORd_NOTd_V4 : MInst<(outs DoubleRegs:$dst),
3766           (ins DoubleRegs:$src1, DoubleRegs:$src2),
3767           "$dst = or($src1, ~$src2)",
3768           [(set (i64 DoubleRegs:$dst),
3769            (or (i64 DoubleRegs:$src1), (not (i64 DoubleRegs:$src2))))]>,
3770           Requires<[HasV4T]>;
3771
3772
3773 //  Logical-logical doublewords.
3774 //  Rxx^=xor(Rss,Rtt)
3775 def XORd_XORdd: MInst_acc<(outs DoubleRegs:$dst),
3776           (ins DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),
3777           "$dst ^= xor($src2, $src3)",
3778           [(set (i64 DoubleRegs:$dst),
3779            (xor (i64 DoubleRegs:$src1), (xor (i64 DoubleRegs:$src2),
3780                                              (i64 DoubleRegs:$src3))))],
3781           "$src1 = $dst">,
3782           Requires<[HasV4T]>;
3783
3784
3785 // Logical-logical words.
3786 // Rx=or(Ru,and(Rx,#s10))
3787 def ORr_ANDri_V4 : MInst_acc<(outs IntRegs:$dst),
3788             (ins IntRegs:$src1, IntRegs: $src2, s10Imm:$src3),
3789             "$dst = or($src1, and($src2, #$src3))",
3790             [(set (i32 IntRegs:$dst),
3791                   (or (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
3792                                                 s10ImmPred:$src3)))],
3793             "$src2 = $dst">,
3794             Requires<[HasV4T]>;
3795
3796 // Rx[&|^]=and(Rs,Rt)
3797 // Rx&=and(Rs,Rt)
3798 def ANDr_ANDrr_V4 : MInst_acc<(outs IntRegs:$dst),
3799             (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
3800             "$dst &= and($src2, $src3)",
3801             [(set (i32 IntRegs:$dst),
3802                   (and (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
3803                                                  (i32 IntRegs:$src3))))],
3804             "$src1 = $dst">,
3805             Requires<[HasV4T]>;
3806
3807 // Rx|=and(Rs,Rt)
3808 def ORr_ANDrr_V4 : MInst_acc<(outs IntRegs:$dst),
3809             (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
3810             "$dst |= and($src2, $src3)",
3811             [(set (i32 IntRegs:$dst),
3812                   (or (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
3813                                                 (i32 IntRegs:$src3))))],
3814             "$src1 = $dst">,
3815             Requires<[HasV4T]>;
3816
3817 // Rx^=and(Rs,Rt)
3818 def XORr_ANDrr_V4 : MInst_acc<(outs IntRegs:$dst),
3819             (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
3820             "$dst ^= and($src2, $src3)",
3821             [(set (i32 IntRegs:$dst),
3822              (xor (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
3823                                             (i32 IntRegs:$src3))))],
3824             "$src1 = $dst">,
3825             Requires<[HasV4T]>;
3826
3827 // Rx[&|^]=and(Rs,~Rt)
3828 // Rx&=and(Rs,~Rt)
3829 def ANDr_ANDr_NOTr_V4 : MInst_acc<(outs IntRegs:$dst),
3830             (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
3831             "$dst &= and($src2, ~$src3)",
3832             [(set (i32 IntRegs:$dst),
3833                   (and (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
3834                                                  (not (i32 IntRegs:$src3)))))],
3835             "$src1 = $dst">,
3836             Requires<[HasV4T]>;
3837
3838 // Rx|=and(Rs,~Rt)
3839 def ORr_ANDr_NOTr_V4 : MInst_acc<(outs IntRegs:$dst),
3840             (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
3841             "$dst |= and($src2, ~$src3)",
3842             [(set (i32 IntRegs:$dst),
3843              (or (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
3844                                            (not (i32 IntRegs:$src3)))))],
3845             "$src1 = $dst">,
3846             Requires<[HasV4T]>;
3847
3848 // Rx^=and(Rs,~Rt)
3849 def XORr_ANDr_NOTr_V4 : MInst_acc<(outs IntRegs:$dst),
3850             (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
3851             "$dst ^= and($src2, ~$src3)",
3852             [(set (i32 IntRegs:$dst),
3853              (xor (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
3854                                             (not (i32 IntRegs:$src3)))))],
3855             "$src1 = $dst">,
3856             Requires<[HasV4T]>;
3857
3858 // Rx[&|^]=or(Rs,Rt)
3859 // Rx&=or(Rs,Rt)
3860 def ANDr_ORrr_V4 : MInst_acc<(outs IntRegs:$dst),
3861             (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
3862             "$dst &= or($src2, $src3)",
3863             [(set (i32 IntRegs:$dst),
3864                   (and (i32 IntRegs:$src1), (or (i32 IntRegs:$src2),
3865                                                 (i32 IntRegs:$src3))))],
3866             "$src1 = $dst">,
3867             Requires<[HasV4T]>;
3868
3869 // Rx|=or(Rs,Rt)
3870 def ORr_ORrr_V4 : MInst_acc<(outs IntRegs:$dst),
3871             (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
3872             "$dst |= or($src2, $src3)",
3873             [(set (i32 IntRegs:$dst),
3874                   (or (i32 IntRegs:$src1), (or (i32 IntRegs:$src2),
3875                                                (i32 IntRegs:$src3))))],
3876             "$src1 = $dst">,
3877             Requires<[HasV4T]>;
3878
3879 // Rx^=or(Rs,Rt)
3880 def XORr_ORrr_V4 : MInst_acc<(outs IntRegs:$dst),
3881             (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
3882             "$dst ^= or($src2, $src3)",
3883             [(set (i32 IntRegs:$dst),
3884              (xor (i32 IntRegs:$src1), (or (i32 IntRegs:$src2),
3885                                            (i32 IntRegs:$src3))))],
3886             "$src1 = $dst">,
3887             Requires<[HasV4T]>;
3888
3889 // Rx[&|^]=xor(Rs,Rt)
3890 // Rx&=xor(Rs,Rt)
3891 def ANDr_XORrr_V4 : MInst_acc<(outs IntRegs:$dst),
3892             (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
3893             "$dst &= xor($src2, $src3)",
3894             [(set (i32 IntRegs:$dst),
3895                   (and (i32 IntRegs:$src1), (xor (i32 IntRegs:$src2),
3896                                                  (i32 IntRegs:$src3))))],
3897             "$src1 = $dst">,
3898             Requires<[HasV4T]>;
3899
3900 // Rx|=xor(Rs,Rt)
3901 def ORr_XORrr_V4 : MInst_acc<(outs IntRegs:$dst),
3902             (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
3903             "$dst |= xor($src2, $src3)",
3904             [(set (i32 IntRegs:$dst),
3905                   (and (i32 IntRegs:$src1), (xor (i32 IntRegs:$src2),
3906                                                  (i32 IntRegs:$src3))))],
3907             "$src1 = $dst">,
3908             Requires<[HasV4T]>;
3909
3910 // Rx^=xor(Rs,Rt)
3911 def XORr_XORrr_V4 : MInst_acc<(outs IntRegs:$dst),
3912             (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
3913             "$dst ^= xor($src2, $src3)",
3914             [(set (i32 IntRegs:$dst),
3915              (and (i32 IntRegs:$src1), (xor (i32 IntRegs:$src2),
3916                                             (i32 IntRegs:$src3))))],
3917             "$src1 = $dst">,
3918             Requires<[HasV4T]>;
3919
3920 // Rx|=and(Rs,#s10)
3921 def ORr_ANDri2_V4 : MInst_acc<(outs IntRegs:$dst),
3922             (ins IntRegs:$src1, IntRegs: $src2, s10Imm:$src3),
3923             "$dst |= and($src2, #$src3)",
3924             [(set (i32 IntRegs:$dst),
3925                   (or (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
3926                                                 s10ImmPred:$src3)))],
3927             "$src1 = $dst">,
3928             Requires<[HasV4T]>;
3929
3930 // Rx|=or(Rs,#s10)
3931 def ORr_ORri_V4 : MInst_acc<(outs IntRegs:$dst),
3932             (ins IntRegs:$src1, IntRegs: $src2, s10Imm:$src3),
3933             "$dst |= or($src2, #$src3)",
3934             [(set (i32 IntRegs:$dst),
3935                   (or (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
3936                                                 s10ImmPred:$src3)))],
3937             "$src1 = $dst">,
3938             Requires<[HasV4T]>;
3939
3940
3941 //    Modulo wrap
3942 //        Rd=modwrap(Rs,Rt)
3943 //    Round
3944 //        Rd=cround(Rs,#u5)
3945 //        Rd=cround(Rs,Rt)
3946 //        Rd=round(Rs,#u5)[:sat]
3947 //        Rd=round(Rs,Rt)[:sat]
3948 //    Vector reduce add unsigned halfwords
3949 //        Rd=vraddh(Rss,Rtt)
3950 //    Vector add bytes
3951 //        Rdd=vaddb(Rss,Rtt)
3952 //    Vector conditional negate
3953 //        Rdd=vcnegh(Rss,Rt)
3954 //        Rxx+=vrcnegh(Rss,Rt)
3955 //    Vector maximum bytes
3956 //        Rdd=vmaxb(Rtt,Rss)
3957 //    Vector reduce maximum halfwords
3958 //        Rxx=vrmaxh(Rss,Ru)
3959 //        Rxx=vrmaxuh(Rss,Ru)
3960 //    Vector reduce maximum words
3961 //        Rxx=vrmaxuw(Rss,Ru)
3962 //        Rxx=vrmaxw(Rss,Ru)
3963 //    Vector minimum bytes
3964 //        Rdd=vminb(Rtt,Rss)
3965 //    Vector reduce minimum halfwords
3966 //        Rxx=vrminh(Rss,Ru)
3967 //        Rxx=vrminuh(Rss,Ru)
3968 //    Vector reduce minimum words
3969 //        Rxx=vrminuw(Rss,Ru)
3970 //        Rxx=vrminw(Rss,Ru)
3971 //    Vector subtract bytes
3972 //        Rdd=vsubb(Rss,Rtt)
3973
3974 //===----------------------------------------------------------------------===//
3975 // XTYPE/ALU -
3976 //===----------------------------------------------------------------------===//
3977
3978
3979 //===----------------------------------------------------------------------===//
3980 // XTYPE/MPY +
3981 //===----------------------------------------------------------------------===//
3982
3983 // Multiply and user lower result.
3984 // Rd=add(#u6,mpyi(Rs,#U6))
3985 def ADDi_MPYri_V4 : MInst<(outs IntRegs:$dst),
3986             (ins u6Imm:$src1, IntRegs:$src2, u6Imm:$src3),
3987             "$dst = add(#$src1, mpyi($src2, #$src3))",
3988             [(set (i32 IntRegs:$dst),
3989                   (add (mul (i32 IntRegs:$src2), u6ImmPred:$src3),
3990                        u6ImmPred:$src1))]>,
3991             Requires<[HasV4T]>;
3992
3993 // Rd=add(#u6,mpyi(Rs,Rt))
3994
3995 def ADDi_MPYrr_V4 : MInst<(outs IntRegs:$dst),
3996             (ins u6Imm:$src1, IntRegs:$src2, IntRegs:$src3),
3997             "$dst = add(#$src1, mpyi($src2, $src3))",
3998             [(set (i32 IntRegs:$dst),
3999                   (add (mul (i32 IntRegs:$src2), (i32 IntRegs:$src3)),
4000                        u6ImmPred:$src1))]>,
4001             Requires<[HasV4T]>;
4002
4003 // Rd=add(Ru,mpyi(#u6:2,Rs))
4004 def ADDr_MPYir_V4 : MInst<(outs IntRegs:$dst),
4005             (ins IntRegs:$src1, u6Imm:$src2, IntRegs:$src3),
4006             "$dst = add($src1, mpyi(#$src2, $src3))",
4007             [(set (i32 IntRegs:$dst),
4008              (add (i32 IntRegs:$src1), (mul (i32 IntRegs:$src3),
4009                                             u6_2ImmPred:$src2)))]>,
4010             Requires<[HasV4T]>;
4011
4012 // Rd=add(Ru,mpyi(Rs,#u6))
4013 def ADDr_MPYri_V4 : MInst<(outs IntRegs:$dst),
4014             (ins IntRegs:$src1, IntRegs:$src2, u6Imm:$src3),
4015             "$dst = add($src1, mpyi($src2, #$src3))",
4016             [(set (i32 IntRegs:$dst),
4017                   (add (i32 IntRegs:$src1), (mul (i32 IntRegs:$src2),
4018                                                  u6ImmPred:$src3)))]>,
4019             Requires<[HasV4T]>;
4020
4021 // Rx=add(Ru,mpyi(Rx,Rs))
4022 def ADDr_MPYrr_V4 : MInst_acc<(outs IntRegs:$dst),
4023             (ins IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
4024             "$dst = add($src1, mpyi($src2, $src3))",
4025             [(set (i32 IntRegs:$dst),
4026              (add (i32 IntRegs:$src1), (mul (i32 IntRegs:$src2),
4027                                             (i32 IntRegs:$src3))))],
4028             "$src2 = $dst">,
4029             Requires<[HasV4T]>;
4030
4031
4032 // Polynomial multiply words
4033 // Rdd=pmpyw(Rs,Rt)
4034 // Rxx^=pmpyw(Rs,Rt)
4035
4036 // Vector reduce multiply word by signed half (32x16)
4037 // Rdd=vrmpyweh(Rss,Rtt)[:<<1]
4038 // Rdd=vrmpywoh(Rss,Rtt)[:<<1]
4039 // Rxx+=vrmpyweh(Rss,Rtt)[:<<1]
4040 // Rxx+=vrmpywoh(Rss,Rtt)[:<<1]
4041
4042 // Multiply and use upper result
4043 // Rd=mpy(Rs,Rt.H):<<1:sat
4044 // Rd=mpy(Rs,Rt.L):<<1:sat
4045 // Rd=mpy(Rs,Rt):<<1
4046 // Rd=mpy(Rs,Rt):<<1:sat
4047 // Rd=mpysu(Rs,Rt)
4048 // Rx+=mpy(Rs,Rt):<<1:sat
4049 // Rx-=mpy(Rs,Rt):<<1:sat
4050
4051 // Vector multiply bytes
4052 // Rdd=vmpybsu(Rs,Rt)
4053 // Rdd=vmpybu(Rs,Rt)
4054 // Rxx+=vmpybsu(Rs,Rt)
4055 // Rxx+=vmpybu(Rs,Rt)
4056
4057 // Vector polynomial multiply halfwords
4058 // Rdd=vpmpyh(Rs,Rt)
4059 // Rxx^=vpmpyh(Rs,Rt)
4060
4061 //===----------------------------------------------------------------------===//
4062 // XTYPE/MPY -
4063 //===----------------------------------------------------------------------===//
4064
4065
4066 //===----------------------------------------------------------------------===//
4067 // XTYPE/SHIFT +
4068 //===----------------------------------------------------------------------===//
4069
4070 // Shift by immediate and accumulate.
4071 // Rx=add(#u8,asl(Rx,#U5))
4072 def ADDi_ASLri_V4 : MInst_acc<(outs IntRegs:$dst),
4073             (ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3),
4074             "$dst = add(#$src1, asl($src2, #$src3))",
4075             [(set (i32 IntRegs:$dst),
4076                   (add (shl (i32 IntRegs:$src2), u5ImmPred:$src3),
4077                        u8ImmPred:$src1))],
4078             "$src2 = $dst">,
4079             Requires<[HasV4T]>;
4080
4081 // Rx=add(#u8,lsr(Rx,#U5))
4082 def ADDi_LSRri_V4 : MInst_acc<(outs IntRegs:$dst),
4083             (ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3),
4084             "$dst = add(#$src1, lsr($src2, #$src3))",
4085             [(set (i32 IntRegs:$dst),
4086                   (add (srl (i32 IntRegs:$src2), u5ImmPred:$src3),
4087                        u8ImmPred:$src1))],
4088             "$src2 = $dst">,
4089             Requires<[HasV4T]>;
4090
4091 // Rx=sub(#u8,asl(Rx,#U5))
4092 def SUBi_ASLri_V4 : MInst_acc<(outs IntRegs:$dst),
4093             (ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3),
4094             "$dst = sub(#$src1, asl($src2, #$src3))",
4095             [(set (i32 IntRegs:$dst),
4096                   (sub (shl (i32 IntRegs:$src2), u5ImmPred:$src3),
4097                        u8ImmPred:$src1))],
4098             "$src2 = $dst">,
4099             Requires<[HasV4T]>;
4100
4101 // Rx=sub(#u8,lsr(Rx,#U5))
4102 def SUBi_LSRri_V4 : MInst_acc<(outs IntRegs:$dst),
4103             (ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3),
4104             "$dst = sub(#$src1, lsr($src2, #$src3))",
4105             [(set (i32 IntRegs:$dst),
4106                   (sub (srl (i32 IntRegs:$src2), u5ImmPred:$src3),
4107                        u8ImmPred:$src1))],
4108             "$src2 = $dst">,
4109             Requires<[HasV4T]>;
4110
4111
4112 //Shift by immediate and logical.
4113 //Rx=and(#u8,asl(Rx,#U5))
4114 def ANDi_ASLri_V4 : MInst_acc<(outs IntRegs:$dst),
4115             (ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3),
4116             "$dst = and(#$src1, asl($src2, #$src3))",
4117             [(set (i32 IntRegs:$dst),
4118                   (and (shl (i32 IntRegs:$src2), u5ImmPred:$src3),
4119                        u8ImmPred:$src1))],
4120             "$src2 = $dst">,
4121             Requires<[HasV4T]>;
4122
4123 //Rx=and(#u8,lsr(Rx,#U5))
4124 def ANDi_LSRri_V4 : MInst_acc<(outs IntRegs:$dst),
4125             (ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3),
4126             "$dst = and(#$src1, lsr($src2, #$src3))",
4127             [(set (i32 IntRegs:$dst),
4128                   (and (srl (i32 IntRegs:$src2), u5ImmPred:$src3),
4129                        u8ImmPred:$src1))],
4130             "$src2 = $dst">,
4131             Requires<[HasV4T]>;
4132
4133 //Rx=or(#u8,asl(Rx,#U5))
4134 let AddedComplexity = 30 in
4135 def ORi_ASLri_V4 : MInst_acc<(outs IntRegs:$dst),
4136             (ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3),
4137             "$dst = or(#$src1, asl($src2, #$src3))",
4138             [(set (i32 IntRegs:$dst),
4139                   (or (shl (i32 IntRegs:$src2), u5ImmPred:$src3),
4140                       u8ImmPred:$src1))],
4141             "$src2 = $dst">,
4142             Requires<[HasV4T]>;
4143
4144 //Rx=or(#u8,lsr(Rx,#U5))
4145 let AddedComplexity = 30 in
4146 def ORi_LSRri_V4 : MInst_acc<(outs IntRegs:$dst),
4147             (ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3),
4148             "$dst = or(#$src1, lsr($src2, #$src3))",
4149             [(set (i32 IntRegs:$dst),
4150                   (or (srl (i32 IntRegs:$src2), u5ImmPred:$src3),
4151                       u8ImmPred:$src1))],
4152             "$src2 = $dst">,
4153             Requires<[HasV4T]>;
4154
4155
4156 //Shift by register.
4157 //Rd=lsl(#s6,Rt)
4158 def LSLi_V4 : MInst<(outs IntRegs:$dst), (ins s6Imm:$src1, IntRegs:$src2),
4159             "$dst = lsl(#$src1, $src2)",
4160             [(set (i32 IntRegs:$dst), (shl s6ImmPred:$src1,
4161                                            (i32 IntRegs:$src2)))]>,
4162             Requires<[HasV4T]>;
4163
4164
4165 //Shift by register and logical.
4166 //Rxx^=asl(Rss,Rt)
4167 def ASLd_rr_xor_V4 : MInst_acc<(outs DoubleRegs:$dst),
4168             (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
4169             "$dst ^= asl($src2, $src3)",
4170             [(set (i64 DoubleRegs:$dst),
4171                   (xor (i64 DoubleRegs:$src1), (shl (i64 DoubleRegs:$src2),
4172                                                     (i32 IntRegs:$src3))))],
4173             "$src1 = $dst">,
4174             Requires<[HasV4T]>;
4175
4176 //Rxx^=asr(Rss,Rt)
4177 def ASRd_rr_xor_V4 : MInst_acc<(outs DoubleRegs:$dst),
4178             (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
4179             "$dst ^= asr($src2, $src3)",
4180             [(set (i64 DoubleRegs:$dst),
4181                   (xor (i64 DoubleRegs:$src1), (sra (i64 DoubleRegs:$src2),
4182                                                     (i32 IntRegs:$src3))))],
4183             "$src1 = $dst">,
4184             Requires<[HasV4T]>;
4185
4186 //Rxx^=lsl(Rss,Rt)
4187 def LSLd_rr_xor_V4 : MInst_acc<(outs DoubleRegs:$dst),
4188             (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
4189             "$dst ^= lsl($src2, $src3)",
4190             [(set (i64 DoubleRegs:$dst), (xor (i64 DoubleRegs:$src1),
4191                                               (shl (i64 DoubleRegs:$src2),
4192                                                    (i32 IntRegs:$src3))))],
4193             "$src1 = $dst">,
4194             Requires<[HasV4T]>;
4195
4196 //Rxx^=lsr(Rss,Rt)
4197 def LSRd_rr_xor_V4 : MInst_acc<(outs DoubleRegs:$dst),
4198             (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
4199             "$dst ^= lsr($src2, $src3)",
4200             [(set (i64 DoubleRegs:$dst),
4201                   (xor (i64 DoubleRegs:$src1), (srl (i64 DoubleRegs:$src2),
4202                                                     (i32 IntRegs:$src3))))],
4203             "$src1 = $dst">,
4204             Requires<[HasV4T]>;
4205
4206
4207 //===----------------------------------------------------------------------===//
4208 // XTYPE/SHIFT -
4209 //===----------------------------------------------------------------------===//
4210
4211 //===----------------------------------------------------------------------===//
4212 // MEMOP: Word, Half, Byte
4213 //===----------------------------------------------------------------------===//
4214
4215 //===----------------------------------------------------------------------===//
4216 // MEMOP: Word
4217 //
4218 //  Implemented:
4219 //     MEMw_ADDi_indexed_V4  : memw(Rs+#u6:2)+=#U5
4220 //     MEMw_SUBi_indexed_V4  : memw(Rs+#u6:2)-=#U5
4221 //     MEMw_ADDr_indexed_V4  : memw(Rs+#u6:2)+=Rt
4222 //     MEMw_SUBr_indexed_V4  : memw(Rs+#u6:2)-=Rt
4223 //     MEMw_CLRr_indexed_V4  : memw(Rs+#u6:2)&=Rt
4224 //     MEMw_SETr_indexed_V4  : memw(Rs+#u6:2)|=Rt
4225 //     MEMw_ADDi_V4          : memw(Rs+#u6:2)+=#U5
4226 //     MEMw_SUBi_V4          : memw(Rs+#u6:2)-=#U5
4227 //     MEMw_ADDr_V4          : memw(Rs+#u6:2)+=Rt
4228 //     MEMw_SUBr_V4          : memw(Rs+#u6:2)-=Rt
4229 //     MEMw_CLRr_V4          : memw(Rs+#u6:2)&=Rt
4230 //     MEMw_SETr_V4          : memw(Rs+#u6:2)|=Rt
4231 //
4232 //   Not implemented:
4233 //     MEMw_CLRi_indexed_V4  : memw(Rs+#u6:2)=clrbit(#U5)
4234 //     MEMw_SETi_indexed_V4  : memw(Rs+#u6:2)=setbit(#U5)
4235 //     MEMw_CLRi_V4          : memw(Rs+#u6:2)=clrbit(#U5)
4236 //     MEMw_SETi_V4          : memw(Rs+#u6:2)=setbit(#U5)
4237 //===----------------------------------------------------------------------===//
4238
4239
4240
4241 // memw(Rs+#u6:2) += #U5
4242 let AddedComplexity = 30 in
4243 def MEMw_ADDi_indexed_MEM_V4 : MEMInst_V4<(outs),
4244             (ins IntRegs:$base, u6_2Imm:$offset, u5Imm:$addend),
4245             "memw($base+#$offset) += #$addend",
4246             []>,
4247             Requires<[HasV4T, UseMEMOP]>;
4248
4249 // memw(Rs+#u6:2) -= #U5
4250 let AddedComplexity = 30 in
4251 def MEMw_SUBi_indexed_MEM_V4 : MEMInst_V4<(outs),
4252             (ins IntRegs:$base, u6_2Imm:$offset, u5Imm:$subend),
4253             "memw($base+#$offset) -= #$subend",
4254             []>,
4255             Requires<[HasV4T, UseMEMOP]>;
4256
4257 // memw(Rs+#u6:2) += Rt
4258 let AddedComplexity = 30 in
4259 def MEMw_ADDr_indexed_MEM_V4 : MEMInst_V4<(outs),
4260             (ins IntRegs:$base, u6_2Imm:$offset, IntRegs:$addend),
4261             "memw($base+#$offset) += $addend",
4262             [(store (add (load (add (i32 IntRegs:$base), u6_2ImmPred:$offset)),
4263                          (i32 IntRegs:$addend)),
4264                     (add (i32 IntRegs:$base), u6_2ImmPred:$offset))]>,
4265             Requires<[HasV4T, UseMEMOP]>;
4266
4267 // memw(Rs+#u6:2) -= Rt
4268 let AddedComplexity = 30 in
4269 def MEMw_SUBr_indexed_MEM_V4 : MEMInst_V4<(outs),
4270             (ins IntRegs:$base, u6_2Imm:$offset, IntRegs:$subend),
4271             "memw($base+#$offset) -= $subend",
4272             [(store (sub (load (add (i32 IntRegs:$base), u6_2ImmPred:$offset)),
4273                          (i32 IntRegs:$subend)),
4274                     (add (i32 IntRegs:$base), u6_2ImmPred:$offset))]>,
4275             Requires<[HasV4T, UseMEMOP]>;
4276
4277 // memw(Rs+#u6:2) &= Rt
4278 let AddedComplexity = 30 in
4279 def MEMw_ANDr_indexed_MEM_V4 : MEMInst_V4<(outs),
4280             (ins IntRegs:$base, u6_2Imm:$offset, IntRegs:$andend),
4281             "memw($base+#$offset) &= $andend",
4282             [(store (and (load (add (i32 IntRegs:$base), u6_2ImmPred:$offset)),
4283                          (i32 IntRegs:$andend)),
4284                     (add (i32 IntRegs:$base), u6_2ImmPred:$offset))]>,
4285             Requires<[HasV4T, UseMEMOP]>;
4286
4287 // memw(Rs+#u6:2) |= Rt
4288 let AddedComplexity = 30 in
4289 def MEMw_ORr_indexed_MEM_V4 : MEMInst_V4<(outs),
4290             (ins IntRegs:$base, u6_2Imm:$offset, IntRegs:$orend),
4291             "memw($base+#$offset) |= $orend",
4292             [(store (or (load (add (i32 IntRegs:$base), u6_2ImmPred:$offset)),
4293                         (i32 IntRegs:$orend)),
4294                     (add (i32 IntRegs:$base), u6_2ImmPred:$offset))]>,
4295             Requires<[HasV4T, UseMEMOP]>;
4296
4297 // memw(Rs+#u6:2) += #U5
4298 let AddedComplexity = 30 in
4299 def MEMw_ADDi_MEM_V4 : MEMInst_V4<(outs),
4300             (ins MEMri:$addr, u5Imm:$addend),
4301             "memw($addr) += $addend",
4302             []>,
4303             Requires<[HasV4T, UseMEMOP]>;
4304
4305 // memw(Rs+#u6:2) -= #U5
4306 let AddedComplexity = 30 in
4307 def MEMw_SUBi_MEM_V4 : MEMInst_V4<(outs),
4308             (ins MEMri:$addr, u5Imm:$subend),
4309             "memw($addr) -= $subend",
4310             []>,
4311             Requires<[HasV4T, UseMEMOP]>;
4312
4313 // memw(Rs+#u6:2) += Rt
4314 let AddedComplexity = 30 in
4315 def MEMw_ADDr_MEM_V4 : MEMInst_V4<(outs),
4316             (ins MEMri:$addr, IntRegs:$addend),
4317             "memw($addr) += $addend",
4318             [(store (add (load ADDRriU6_2:$addr), (i32 IntRegs:$addend)),
4319                     ADDRriU6_2:$addr)]>,
4320             Requires<[HasV4T, UseMEMOP]>;
4321
4322 // memw(Rs+#u6:2) -= Rt
4323 let AddedComplexity = 30 in
4324 def MEMw_SUBr_MEM_V4 : MEMInst_V4<(outs),
4325             (ins MEMri:$addr, IntRegs:$subend),
4326             "memw($addr) -= $subend",
4327             [(store (sub (load ADDRriU6_2:$addr), (i32 IntRegs:$subend)),
4328                     ADDRriU6_2:$addr)]>,
4329             Requires<[HasV4T, UseMEMOP]>;
4330
4331 // memw(Rs+#u6:2) &= Rt
4332 let AddedComplexity = 30 in
4333 def MEMw_ANDr_MEM_V4 : MEMInst_V4<(outs),
4334             (ins MEMri:$addr, IntRegs:$andend),
4335             "memw($addr) &= $andend",
4336             [(store (and (load ADDRriU6_2:$addr), (i32 IntRegs:$andend)),
4337                     ADDRriU6_2:$addr)]>,
4338             Requires<[HasV4T, UseMEMOP]>;
4339
4340 // memw(Rs+#u6:2) |= Rt
4341 let AddedComplexity = 30 in
4342 def MEMw_ORr_MEM_V4 : MEMInst_V4<(outs),
4343             (ins MEMri:$addr, IntRegs:$orend),
4344             "memw($addr) |= $orend",
4345             [(store (or (load ADDRriU6_2:$addr), (i32 IntRegs:$orend)),
4346                     ADDRriU6_2:$addr)]>,
4347             Requires<[HasV4T, UseMEMOP]>;
4348
4349 //===----------------------------------------------------------------------===//
4350 // MEMOP: Halfword
4351 //
4352 //  Implemented:
4353 //     MEMh_ADDi_indexed_V4  : memw(Rs+#u6:2)+=#U5
4354 //     MEMh_SUBi_indexed_V4  : memw(Rs+#u6:2)-=#U5
4355 //     MEMh_ADDr_indexed_V4  : memw(Rs+#u6:2)+=Rt
4356 //     MEMh_SUBr_indexed_V4  : memw(Rs+#u6:2)-=Rt
4357 //     MEMh_CLRr_indexed_V4  : memw(Rs+#u6:2)&=Rt
4358 //     MEMh_SETr_indexed_V4  : memw(Rs+#u6:2)|=Rt
4359 //     MEMh_ADDi_V4          : memw(Rs+#u6:2)+=#U5
4360 //     MEMh_SUBi_V4          : memw(Rs+#u6:2)-=#U5
4361 //     MEMh_ADDr_V4          : memw(Rs+#u6:2)+=Rt
4362 //     MEMh_SUBr_V4          : memw(Rs+#u6:2)-=Rt
4363 //     MEMh_CLRr_V4          : memw(Rs+#u6:2)&=Rt
4364 //     MEMh_SETr_V4          : memw(Rs+#u6:2)|=Rt
4365 //
4366 //   Not implemented:
4367 //     MEMh_CLRi_indexed_V4  : memw(Rs+#u6:2)=clrbit(#U5)
4368 //     MEMh_SETi_indexed_V4  : memw(Rs+#u6:2)=setbit(#U5)
4369 //     MEMh_CLRi_V4          : memw(Rs+#u6:2)=clrbit(#U5)
4370 //     MEMh_SETi_V4          : memw(Rs+#u6:2)=setbit(#U5)
4371 //===----------------------------------------------------------------------===//
4372
4373
4374 // memh(Rs+#u6:1) += #U5
4375 let AddedComplexity = 30 in
4376 def MEMh_ADDi_indexed_MEM_V4 : MEMInst_V4<(outs),
4377             (ins IntRegs:$base, u6_1Imm:$offset, u5Imm:$addend),
4378             "memh($base+#$offset) += $addend",
4379             []>,
4380             Requires<[HasV4T, UseMEMOP]>;
4381
4382 // memh(Rs+#u6:1) -= #U5
4383 let AddedComplexity = 30 in
4384 def MEMh_SUBi_indexed_MEM_V4 : MEMInst_V4<(outs),
4385             (ins IntRegs:$base, u6_1Imm:$offset, u5Imm:$subend),
4386             "memh($base+#$offset) -= $subend",
4387             []>,
4388             Requires<[HasV4T, UseMEMOP]>;
4389
4390 // memh(Rs+#u6:1) += Rt
4391 let AddedComplexity = 30 in
4392 def MEMh_ADDr_indexed_MEM_V4 : MEMInst_V4<(outs),
4393             (ins IntRegs:$base, u6_1Imm:$offset, IntRegs:$addend),
4394             "memh($base+#$offset) += $addend",
4395             [(truncstorei16 (add (sextloadi16 (add (i32 IntRegs:$base),
4396                                                    u6_1ImmPred:$offset)),
4397                                  (i32 IntRegs:$addend)),
4398                             (add (i32 IntRegs:$base), u6_1ImmPred:$offset))]>,
4399             Requires<[HasV4T, UseMEMOP]>;
4400
4401 // memh(Rs+#u6:1) -= Rt
4402 let AddedComplexity = 30 in
4403 def MEMh_SUBr_indexed_MEM_V4 : MEMInst_V4<(outs),
4404             (ins IntRegs:$base, u6_1Imm:$offset, IntRegs:$subend),
4405             "memh($base+#$offset) -= $subend",
4406             [(truncstorei16 (sub (sextloadi16 (add (i32 IntRegs:$base),
4407                                                    u6_1ImmPred:$offset)),
4408                                  (i32 IntRegs:$subend)),
4409                             (add (i32 IntRegs:$base), u6_1ImmPred:$offset))]>,
4410             Requires<[HasV4T, UseMEMOP]>;
4411
4412 // memh(Rs+#u6:1) &= Rt
4413 let AddedComplexity = 30 in
4414 def MEMh_ANDr_indexed_MEM_V4 : MEMInst_V4<(outs),
4415             (ins IntRegs:$base, u6_1Imm:$offset, IntRegs:$andend),
4416             "memh($base+#$offset) += $andend",
4417             [(truncstorei16 (and (sextloadi16 (add (i32 IntRegs:$base),
4418                                                    u6_1ImmPred:$offset)),
4419                                  (i32 IntRegs:$andend)),
4420                             (add (i32 IntRegs:$base), u6_1ImmPred:$offset))]>,
4421             Requires<[HasV4T, UseMEMOP]>;
4422
4423 // memh(Rs+#u6:1) |= Rt
4424 let AddedComplexity = 30 in
4425 def MEMh_ORr_indexed_MEM_V4 : MEMInst_V4<(outs),
4426             (ins IntRegs:$base, u6_1Imm:$offset, IntRegs:$orend),
4427             "memh($base+#$offset) |= $orend",
4428             [(truncstorei16 (or (sextloadi16 (add (i32 IntRegs:$base),
4429                                               u6_1ImmPred:$offset)),
4430                              (i32 IntRegs:$orend)),
4431                             (add (i32 IntRegs:$base), u6_1ImmPred:$offset))]>,
4432             Requires<[HasV4T, UseMEMOP]>;
4433
4434 // memh(Rs+#u6:1) += #U5
4435 let AddedComplexity = 30 in
4436 def MEMh_ADDi_MEM_V4 : MEMInst_V4<(outs),
4437             (ins MEMri:$addr, u5Imm:$addend),
4438             "memh($addr) += $addend",
4439             []>,
4440             Requires<[HasV4T, UseMEMOP]>;
4441
4442 // memh(Rs+#u6:1) -= #U5
4443 let AddedComplexity = 30 in
4444 def MEMh_SUBi_MEM_V4 : MEMInst_V4<(outs),
4445             (ins MEMri:$addr, u5Imm:$subend),
4446             "memh($addr) -= $subend",
4447             []>,
4448             Requires<[HasV4T, UseMEMOP]>;
4449
4450 // memh(Rs+#u6:1) += Rt
4451 let AddedComplexity = 30 in
4452 def MEMh_ADDr_MEM_V4 : MEMInst_V4<(outs),
4453             (ins MEMri:$addr, IntRegs:$addend),
4454             "memh($addr) += $addend",
4455             [(truncstorei16 (add (sextloadi16 ADDRriU6_1:$addr),
4456                                  (i32 IntRegs:$addend)), ADDRriU6_1:$addr)]>,
4457             Requires<[HasV4T, UseMEMOP]>;
4458
4459 // memh(Rs+#u6:1) -= Rt
4460 let AddedComplexity = 30 in
4461 def MEMh_SUBr_MEM_V4 : MEMInst_V4<(outs),
4462             (ins MEMri:$addr, IntRegs:$subend),
4463             "memh($addr) -= $subend",
4464             [(truncstorei16 (sub (sextloadi16 ADDRriU6_1:$addr),
4465                                  (i32 IntRegs:$subend)), ADDRriU6_1:$addr)]>,
4466             Requires<[HasV4T, UseMEMOP]>;
4467
4468 // memh(Rs+#u6:1) &= Rt
4469 let AddedComplexity = 30 in
4470 def MEMh_ANDr_MEM_V4 : MEMInst_V4<(outs),
4471             (ins MEMri:$addr, IntRegs:$andend),
4472             "memh($addr) &= $andend",
4473             [(truncstorei16 (and (sextloadi16 ADDRriU6_1:$addr),
4474                                  (i32 IntRegs:$andend)), ADDRriU6_1:$addr)]>,
4475             Requires<[HasV4T, UseMEMOP]>;
4476
4477 // memh(Rs+#u6:1) |= Rt
4478 let AddedComplexity = 30 in
4479 def MEMh_ORr_MEM_V4 : MEMInst_V4<(outs),
4480             (ins MEMri:$addr, IntRegs:$orend),
4481             "memh($addr) |= $orend",
4482             [(truncstorei16 (or (sextloadi16 ADDRriU6_1:$addr),
4483                                 (i32 IntRegs:$orend)), ADDRriU6_1:$addr)]>,
4484             Requires<[HasV4T, UseMEMOP]>;
4485
4486
4487 //===----------------------------------------------------------------------===//
4488 // MEMOP: Byte
4489 //
4490 //  Implemented:
4491 //     MEMb_ADDi_indexed_V4  : memb(Rs+#u6:0)+=#U5
4492 //     MEMb_SUBi_indexed_V4  : memb(Rs+#u6:0)-=#U5
4493 //     MEMb_ADDr_indexed_V4  : memb(Rs+#u6:0)+=Rt
4494 //     MEMb_SUBr_indexed_V4  : memb(Rs+#u6:0)-=Rt
4495 //     MEMb_CLRr_indexed_V4  : memb(Rs+#u6:0)&=Rt
4496 //     MEMb_SETr_indexed_V4  : memb(Rs+#u6:0)|=Rt
4497 //     MEMb_ADDi_V4          : memb(Rs+#u6:0)+=#U5
4498 //     MEMb_SUBi_V4          : memb(Rs+#u6:0)-=#U5
4499 //     MEMb_ADDr_V4          : memb(Rs+#u6:0)+=Rt
4500 //     MEMb_SUBr_V4          : memb(Rs+#u6:0)-=Rt
4501 //     MEMb_CLRr_V4          : memb(Rs+#u6:0)&=Rt
4502 //     MEMb_SETr_V4          : memb(Rs+#u6:0)|=Rt
4503 //
4504 //   Not implemented:
4505 //     MEMb_CLRi_indexed_V4  : memb(Rs+#u6:0)=clrbit(#U5)
4506 //     MEMb_SETi_indexed_V4  : memb(Rs+#u6:0)=setbit(#U5)
4507 //     MEMb_CLRi_V4          : memb(Rs+#u6:0)=clrbit(#U5)
4508 //     MEMb_SETi_V4          : memb(Rs+#u6:0)=setbit(#U5)
4509 //===----------------------------------------------------------------------===//
4510
4511 // memb(Rs+#u6:0) += #U5
4512 let AddedComplexity = 30 in
4513 def MEMb_ADDi_indexed_MEM_V4 : MEMInst_V4<(outs),
4514             (ins IntRegs:$base, u6_0Imm:$offset, u5Imm:$addend),
4515             "memb($base+#$offset) += $addend",
4516             []>,
4517             Requires<[HasV4T, UseMEMOP]>;
4518
4519 // memb(Rs+#u6:0) -= #U5
4520 let AddedComplexity = 30 in
4521 def MEMb_SUBi_indexed_MEM_V4 : MEMInst_V4<(outs),
4522             (ins IntRegs:$base, u6_0Imm:$offset, u5Imm:$subend),
4523             "memb($base+#$offset) -= $subend",
4524             []>,
4525             Requires<[HasV4T, UseMEMOP]>;
4526
4527 // memb(Rs+#u6:0) += Rt
4528 let AddedComplexity = 30 in
4529 def MEMb_ADDr_indexed_MEM_V4 : MEMInst_V4<(outs),
4530             (ins IntRegs:$base, u6_0Imm:$offset, IntRegs:$addend),
4531             "memb($base+#$offset) += $addend",
4532             [(truncstorei8 (add (sextloadi8 (add (i32 IntRegs:$base),
4533                                                  u6_0ImmPred:$offset)),
4534                                 (i32 IntRegs:$addend)),
4535                            (add (i32 IntRegs:$base), u6_0ImmPred:$offset))]>,
4536             Requires<[HasV4T, UseMEMOP]>;
4537
4538 // memb(Rs+#u6:0) -= Rt
4539 let AddedComplexity = 30 in
4540 def MEMb_SUBr_indexed_MEM_V4 : MEMInst_V4<(outs),
4541             (ins IntRegs:$base, u6_0Imm:$offset, IntRegs:$subend),
4542             "memb($base+#$offset) -= $subend",
4543             [(truncstorei8 (sub (sextloadi8 (add (i32 IntRegs:$base),
4544                                                  u6_0ImmPred:$offset)),
4545                                 (i32 IntRegs:$subend)),
4546                            (add (i32 IntRegs:$base), u6_0ImmPred:$offset))]>,
4547             Requires<[HasV4T, UseMEMOP]>;
4548
4549 // memb(Rs+#u6:0) &= Rt
4550 let AddedComplexity = 30 in
4551 def MEMb_ANDr_indexed_MEM_V4 : MEMInst_V4<(outs),
4552             (ins IntRegs:$base, u6_0Imm:$offset, IntRegs:$andend),
4553             "memb($base+#$offset) += $andend",
4554             [(truncstorei8 (and (sextloadi8 (add (i32 IntRegs:$base),
4555                                                  u6_0ImmPred:$offset)),
4556                                 (i32 IntRegs:$andend)),
4557                            (add (i32 IntRegs:$base), u6_0ImmPred:$offset))]>,
4558             Requires<[HasV4T, UseMEMOP]>;
4559
4560 // memb(Rs+#u6:0) |= Rt
4561 let AddedComplexity = 30 in
4562 def MEMb_ORr_indexed_MEM_V4 : MEMInst_V4<(outs),
4563             (ins IntRegs:$base, u6_0Imm:$offset, IntRegs:$orend),
4564             "memb($base+#$offset) |= $orend",
4565             [(truncstorei8 (or (sextloadi8 (add (i32 IntRegs:$base),
4566                                                 u6_0ImmPred:$offset)),
4567                                (i32 IntRegs:$orend)),
4568                            (add (i32 IntRegs:$base), u6_0ImmPred:$offset))]>,
4569             Requires<[HasV4T, UseMEMOP]>;
4570
4571 // memb(Rs+#u6:0) += #U5
4572 let AddedComplexity = 30 in
4573 def MEMb_ADDi_MEM_V4 : MEMInst_V4<(outs),
4574             (ins MEMri:$addr, u5Imm:$addend),
4575             "memb($addr) += $addend",
4576             []>,
4577             Requires<[HasV4T, UseMEMOP]>;
4578
4579 // memb(Rs+#u6:0) -= #U5
4580 let AddedComplexity = 30 in
4581 def MEMb_SUBi_MEM_V4 : MEMInst_V4<(outs),
4582             (ins MEMri:$addr, u5Imm:$subend),
4583             "memb($addr) -= $subend",
4584             []>,
4585             Requires<[HasV4T, UseMEMOP]>;
4586
4587 // memb(Rs+#u6:0) += Rt
4588 let AddedComplexity = 30 in
4589 def MEMb_ADDr_MEM_V4 : MEMInst_V4<(outs),
4590             (ins MEMri:$addr, IntRegs:$addend),
4591             "memb($addr) += $addend",
4592             [(truncstorei8 (add (sextloadi8 ADDRriU6_0:$addr),
4593                                 (i32 IntRegs:$addend)), ADDRriU6_0:$addr)]>,
4594             Requires<[HasV4T, UseMEMOP]>;
4595
4596 // memb(Rs+#u6:0) -= Rt
4597 let AddedComplexity = 30 in
4598 def MEMb_SUBr_MEM_V4 : MEMInst_V4<(outs),
4599             (ins MEMri:$addr, IntRegs:$subend),
4600             "memb($addr) -= $subend",
4601             [(truncstorei8 (sub (sextloadi8 ADDRriU6_0:$addr),
4602                                 (i32 IntRegs:$subend)), ADDRriU6_0:$addr)]>,
4603             Requires<[HasV4T, UseMEMOP]>;
4604
4605 // memb(Rs+#u6:0) &= Rt
4606 let AddedComplexity = 30 in
4607 def MEMb_ANDr_MEM_V4 : MEMInst_V4<(outs),
4608             (ins MEMri:$addr, IntRegs:$andend),
4609             "memb($addr) &= $andend",
4610             [(truncstorei8 (and (sextloadi8 ADDRriU6_0:$addr),
4611                                 (i32 IntRegs:$andend)), ADDRriU6_0:$addr)]>,
4612             Requires<[HasV4T, UseMEMOP]>;
4613
4614 // memb(Rs+#u6:0) |= Rt
4615 let AddedComplexity = 30 in
4616 def MEMb_ORr_MEM_V4 : MEMInst_V4<(outs),
4617             (ins MEMri:$addr, IntRegs:$orend),
4618             "memb($addr) |= $orend",
4619             [(truncstorei8 (or (sextloadi8 ADDRriU6_0:$addr),
4620                                (i32 IntRegs:$orend)), ADDRriU6_0:$addr)]>,
4621             Requires<[HasV4T, UseMEMOP]>;
4622
4623
4624 //===----------------------------------------------------------------------===//
4625 // XTYPE/PRED +
4626 //===----------------------------------------------------------------------===//
4627
4628 // Hexagon V4 only supports these flavors of byte/half compare instructions:
4629 // EQ/GT/GTU. Other flavors like GE/GEU/LT/LTU/LE/LEU are not supported by
4630 // hardware. However, compiler can still implement these patterns through
4631 // appropriate patterns combinations based on current implemented patterns.
4632 // The implemented patterns are: EQ/GT/GTU.
4633 // Missing patterns are: GE/GEU/LT/LTU/LE/LEU.
4634
4635 // Following instruction is not being extended as it results into the
4636 // incorrect code for negative numbers.
4637 // Pd=cmpb.eq(Rs,#u8)
4638
4639 let isCompare = 1 in
4640 def CMPbEQri_V4 : MInst<(outs PredRegs:$dst),
4641             (ins IntRegs:$src1, u8Imm:$src2),
4642             "$dst = cmpb.eq($src1, #$src2)",
4643             [(set (i1 PredRegs:$dst),
4644                   (seteq (and (i32 IntRegs:$src1), 255), u8ImmPred:$src2))]>,
4645             Requires<[HasV4T]>;
4646
4647 // Pd=cmpb.eq(Rs,Rt)
4648 let isCompare = 1 in
4649 def CMPbEQrr_ubub_V4 : MInst<(outs PredRegs:$dst),
4650             (ins IntRegs:$src1, IntRegs:$src2),
4651             "$dst = cmpb.eq($src1, $src2)",
4652             [(set (i1 PredRegs:$dst),
4653                   (seteq (and (xor (i32 IntRegs:$src1),
4654                                    (i32 IntRegs:$src2)), 255), 0))]>,
4655             Requires<[HasV4T]>;
4656
4657 // Pd=cmpb.eq(Rs,Rt)
4658 let isCompare = 1 in
4659 def CMPbEQrr_sbsb_V4 : MInst<(outs PredRegs:$dst),
4660             (ins IntRegs:$src1, IntRegs:$src2),
4661             "$dst = cmpb.eq($src1, $src2)",
4662             [(set (i1 PredRegs:$dst),
4663                   (seteq (shl (i32 IntRegs:$src1), (i32 24)),
4664                          (shl (i32 IntRegs:$src2), (i32 24))))]>,
4665             Requires<[HasV4T]>;
4666
4667 // Pd=cmpb.gt(Rs,Rt)
4668 let isCompare = 1 in
4669 def CMPbGTrr_V4 : MInst<(outs PredRegs:$dst),
4670             (ins IntRegs:$src1, IntRegs:$src2),
4671             "$dst = cmpb.gt($src1, $src2)",
4672             [(set (i1 PredRegs:$dst),
4673                   (setgt (shl (i32 IntRegs:$src1), (i32 24)),
4674                          (shl (i32 IntRegs:$src2), (i32 24))))]>,
4675             Requires<[HasV4T]>;
4676
4677 // Pd=cmpb.gtu(Rs,#u7)
4678 let isCompare = 1 in
4679 def CMPbGTUri_V4 : MInst<(outs PredRegs:$dst),
4680             (ins IntRegs:$src1, u7Imm:$src2),
4681             "$dst = cmpb.gtu($src1, #$src2)",
4682             [(set (i1 PredRegs:$dst), (setugt (and (i32 IntRegs:$src1), 255),
4683                                               u7ImmPred:$src2))]>,
4684             Requires<[HasV4T]>;
4685
4686 // Pd=cmpb.gtu(Rs,Rt)
4687 let isCompare = 1 in
4688 def CMPbGTUrr_V4 : MInst<(outs PredRegs:$dst),
4689             (ins IntRegs:$src1, IntRegs:$src2),
4690             "$dst = cmpb.gtu($src1, $src2)",
4691             [(set (i1 PredRegs:$dst), (setugt (and (i32 IntRegs:$src1), 255),
4692                                              (and (i32 IntRegs:$src2), 255)))]>,
4693             Requires<[HasV4T]>;
4694
4695 // Following instruction is not being extended as it results into the incorrect
4696 // code for negative numbers.
4697
4698 // Signed half compare(.eq) ri.
4699 // Pd=cmph.eq(Rs,#s8)
4700 let isCompare = 1 in
4701 def CMPhEQri_V4 : MInst<(outs PredRegs:$dst),
4702             (ins IntRegs:$src1, s8Imm:$src2),
4703             "$dst = cmph.eq($src1, #$src2)",
4704             [(set (i1 PredRegs:$dst), (seteq (and (i32 IntRegs:$src1), 65535),
4705                                              s8ImmPred:$src2))]>,
4706             Requires<[HasV4T]>;
4707
4708 // Signed half compare(.eq) rr.
4709 // Case 1: xor + and, then compare:
4710 //   r0=xor(r0,r1)
4711 //   r0=and(r0,#0xffff)
4712 //   p0=cmp.eq(r0,#0)
4713 // Pd=cmph.eq(Rs,Rt)
4714 let isCompare = 1 in
4715 def CMPhEQrr_xor_V4 : MInst<(outs PredRegs:$dst),
4716             (ins IntRegs:$src1, IntRegs:$src2),
4717             "$dst = cmph.eq($src1, $src2)",
4718             [(set (i1 PredRegs:$dst), (seteq (and (xor (i32 IntRegs:$src1),
4719                                                        (i32 IntRegs:$src2)),
4720                                                   65535), 0))]>,
4721             Requires<[HasV4T]>;
4722
4723 // Signed half compare(.eq) rr.
4724 // Case 2: shift left 16 bits then compare:
4725 //   r0=asl(r0,16)
4726 //   r1=asl(r1,16)
4727 //   p0=cmp.eq(r0,r1)
4728 // Pd=cmph.eq(Rs,Rt)
4729 let isCompare = 1 in
4730 def CMPhEQrr_shl_V4 : MInst<(outs PredRegs:$dst),
4731             (ins IntRegs:$src1, IntRegs:$src2),
4732             "$dst = cmph.eq($src1, $src2)",
4733             [(set (i1 PredRegs:$dst),
4734                   (seteq (shl (i32 IntRegs:$src1), (i32 16)),
4735                          (shl (i32 IntRegs:$src2), (i32 16))))]>,
4736             Requires<[HasV4T]>;
4737
4738 /* Incorrect Pattern -- immediate should be right shifted before being
4739 used in the cmph.gt instruction.
4740 // Signed half compare(.gt) ri.
4741 // Pd=cmph.gt(Rs,#s8)
4742
4743 let isCompare = 1 in
4744 def CMPhGTri_V4 : MInst<(outs PredRegs:$dst),
4745             (ins IntRegs:$src1, s8Imm:$src2),
4746             "$dst = cmph.gt($src1, #$src2)",
4747             [(set (i1 PredRegs:$dst),
4748                   (setgt (shl (i32 IntRegs:$src1), (i32 16)),
4749                          s8ImmPred:$src2))]>,
4750             Requires<[HasV4T]>;
4751 */
4752
4753 // Signed half compare(.gt) rr.
4754 // Pd=cmph.gt(Rs,Rt)
4755 let isCompare = 1 in
4756 def CMPhGTrr_shl_V4 : MInst<(outs PredRegs:$dst),
4757             (ins IntRegs:$src1, IntRegs:$src2),
4758             "$dst = cmph.gt($src1, $src2)",
4759             [(set (i1 PredRegs:$dst),
4760                   (setgt (shl (i32 IntRegs:$src1), (i32 16)),
4761                          (shl (i32 IntRegs:$src2), (i32 16))))]>,
4762             Requires<[HasV4T]>;
4763
4764 // Unsigned half compare rr (.gtu).
4765 // Pd=cmph.gtu(Rs,Rt)
4766 let isCompare = 1 in
4767 def CMPhGTUrr_V4 : MInst<(outs PredRegs:$dst),
4768             (ins IntRegs:$src1, IntRegs:$src2),
4769             "$dst = cmph.gtu($src1, $src2)",
4770             [(set (i1 PredRegs:$dst),
4771                   (setugt (and (i32 IntRegs:$src1), 65535),
4772                           (and (i32 IntRegs:$src2), 65535)))]>,
4773             Requires<[HasV4T]>;
4774
4775 // Unsigned half compare ri (.gtu).
4776 // Pd=cmph.gtu(Rs,#u7)
4777 let isCompare = 1 in
4778 def CMPhGTUri_V4 : MInst<(outs PredRegs:$dst),
4779             (ins IntRegs:$src1, u7Imm:$src2),
4780             "$dst = cmph.gtu($src1, #$src2)",
4781             [(set (i1 PredRegs:$dst), (setugt (and (i32 IntRegs:$src1), 65535),
4782                                               u7ImmPred:$src2))]>,
4783             Requires<[HasV4T]>;
4784
4785 //===----------------------------------------------------------------------===//
4786 // XTYPE/PRED -
4787 //===----------------------------------------------------------------------===//
4788
4789 //Deallocate frame and return.
4790 //    dealloc_return
4791 let isReturn = 1, isTerminator = 1, isBarrier = 1, isPredicable = 1,
4792   Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1 in {
4793   def DEALLOC_RET_V4 : NVInst_V4<(outs), (ins i32imm:$amt1),
4794             "dealloc_return",
4795             []>,
4796             Requires<[HasV4T]>;
4797 }
4798
4799 // Restore registers and dealloc return function call.
4800 let isCall = 1, isBarrier = 1, isReturn = 1, isTerminator = 1,
4801   Defs = [R29, R30, R31, PC] in {
4802   def RESTORE_DEALLOC_RET_JMP_V4 : JInst<(outs),
4803                                    (ins calltarget:$dst),
4804              "jump $dst // Restore_and_dealloc_return",
4805              []>,
4806              Requires<[HasV4T]>;
4807 }
4808
4809 // Restore registers and dealloc frame before a tail call.
4810 let isCall = 1, isBarrier = 1,
4811   Defs = [R29, R30, R31, PC] in {
4812   def RESTORE_DEALLOC_BEFORE_TAILCALL_V4 : JInst<(outs),
4813                                            (ins calltarget:$dst),
4814              "call $dst // Restore_and_dealloc_before_tailcall",
4815              []>,
4816              Requires<[HasV4T]>;
4817 }
4818
4819 // Save registers function call.
4820 let isCall = 1, isBarrier = 1,
4821   Uses = [R29, R31] in {
4822   def SAVE_REGISTERS_CALL_V4 : JInst<(outs),
4823                                (ins calltarget:$dst),
4824              "call $dst // Save_calle_saved_registers",
4825              []>,
4826              Requires<[HasV4T]>;
4827 }
4828
4829 //    if (Ps) dealloc_return
4830 let isReturn = 1, isTerminator = 1,
4831     Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1,
4832     isPredicated = 1 in {
4833   def DEALLOC_RET_cPt_V4 : NVInst_V4<(outs),
4834                            (ins PredRegs:$src1, i32imm:$amt1),
4835             "if ($src1) dealloc_return",
4836             []>,
4837             Requires<[HasV4T]>;
4838 }
4839
4840 //    if (!Ps) dealloc_return
4841 let isReturn = 1, isTerminator = 1,
4842     Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1,
4843     isPredicated = 1 in {
4844   def DEALLOC_RET_cNotPt_V4 : NVInst_V4<(outs), (ins PredRegs:$src1,
4845                                                      i32imm:$amt1),
4846             "if (!$src1) dealloc_return",
4847             []>,
4848             Requires<[HasV4T]>;
4849 }
4850
4851 //    if (Ps.new) dealloc_return:nt
4852 let isReturn = 1, isTerminator = 1,
4853     Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1,
4854     isPredicated = 1 in {
4855   def DEALLOC_RET_cdnPnt_V4 : NVInst_V4<(outs), (ins PredRegs:$src1,
4856                                                      i32imm:$amt1),
4857             "if ($src1.new) dealloc_return:nt",
4858             []>,
4859             Requires<[HasV4T]>;
4860 }
4861
4862 //    if (!Ps.new) dealloc_return:nt
4863 let isReturn = 1, isTerminator = 1,
4864     Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1,
4865     isPredicated = 1 in {
4866   def DEALLOC_RET_cNotdnPnt_V4 : NVInst_V4<(outs), (ins PredRegs:$src1,
4867                                                         i32imm:$amt1),
4868             "if (!$src1.new) dealloc_return:nt",
4869             []>,
4870             Requires<[HasV4T]>;
4871 }
4872
4873 //    if (Ps.new) dealloc_return:t
4874 let isReturn = 1, isTerminator = 1,
4875     Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1,
4876     isPredicated = 1 in {
4877   def DEALLOC_RET_cdnPt_V4 : NVInst_V4<(outs), (ins PredRegs:$src1,
4878                                                     i32imm:$amt1),
4879             "if ($src1.new) dealloc_return:t",
4880             []>,
4881             Requires<[HasV4T]>;
4882 }
4883
4884 //    if (!Ps.new) dealloc_return:nt
4885 let isReturn = 1, isTerminator = 1,
4886     Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1,
4887     isPredicated = 1 in {
4888   def DEALLOC_RET_cNotdnPt_V4 : NVInst_V4<(outs), (ins PredRegs:$src1,
4889                                                        i32imm:$amt1),
4890             "if (!$src1.new) dealloc_return:t",
4891             []>,
4892             Requires<[HasV4T]>;
4893 }
4894
4895
4896 // Load/Store with absolute addressing mode
4897 // memw(#u6)=Rt
4898
4899 multiclass ST_abs<string OpcStr> {
4900   let isPredicable = 1 in
4901   def _abs_V4 : STInst2<(outs),
4902             (ins globaladdress:$absaddr, IntRegs:$src),
4903             !strconcat(OpcStr, "(##$absaddr) = $src"),
4904             []>,
4905             Requires<[HasV4T]>;
4906
4907   let isPredicated = 1 in
4908   def _abs_cPt_V4 : STInst2<(outs),
4909             (ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2),
4910             !strconcat("if ($src1)",
4911             !strconcat(OpcStr, "(##$absaddr) = $src2")),
4912             []>,
4913             Requires<[HasV4T]>;
4914
4915   let isPredicated = 1 in
4916   def _abs_cNotPt_V4 : STInst2<(outs),
4917             (ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2),
4918             !strconcat("if (!$src1)",
4919             !strconcat(OpcStr, "(##$absaddr) = $src2")),
4920             []>,
4921             Requires<[HasV4T]>;
4922
4923   let isPredicated = 1 in
4924   def _abs_cdnPt_V4 : STInst2<(outs),
4925             (ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2),
4926             !strconcat("if ($src1.new)",
4927             !strconcat(OpcStr, "(##$absaddr) = $src2")),
4928             []>,
4929             Requires<[HasV4T]>;
4930
4931   let isPredicated = 1 in
4932   def _abs_cdnNotPt_V4 : STInst2<(outs),
4933             (ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2),
4934             !strconcat("if (!$src1.new)",
4935             !strconcat(OpcStr, "(##$absaddr) = $src2")),
4936             []>,
4937             Requires<[HasV4T]>;
4938
4939   def _abs_nv_V4 : STInst2<(outs),
4940             (ins globaladdress:$absaddr, IntRegs:$src),
4941             !strconcat(OpcStr, "(##$absaddr) = $src.new"),
4942             []>,
4943             Requires<[HasV4T]>;
4944
4945   let isPredicated = 1 in
4946   def _abs_cPt_nv_V4 : STInst2<(outs),
4947             (ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2),
4948             !strconcat("if ($src1)",
4949             !strconcat(OpcStr, "(##$absaddr) = $src2.new")),
4950             []>,
4951             Requires<[HasV4T]>;
4952
4953   let isPredicated = 1 in
4954   def _abs_cNotPt_nv_V4 : STInst2<(outs),
4955             (ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2),
4956             !strconcat("if (!$src1)",
4957             !strconcat(OpcStr, "(##$absaddr) = $src2.new")),
4958             []>,
4959             Requires<[HasV4T]>;
4960
4961   let isPredicated = 1 in
4962   def _abs_cdnPt_nv_V4 : STInst2<(outs),
4963             (ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2),
4964             !strconcat("if ($src1.new)",
4965             !strconcat(OpcStr, "(##$absaddr) = $src2.new")),
4966             []>,
4967             Requires<[HasV4T]>;
4968
4969   let isPredicated = 1 in
4970   def _abs_cdnNotPt_nv_V4 : STInst2<(outs),
4971             (ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2),
4972             !strconcat("if (!$src1.new)",
4973             !strconcat(OpcStr, "(##$absaddr) = $src2.new")),
4974             []>,
4975             Requires<[HasV4T]>;
4976 }
4977
4978 let AddedComplexity = 30, isPredicable = 1 in
4979 def STrid_abs_V4 : STInst<(outs),
4980           (ins globaladdress:$absaddr, DoubleRegs:$src),
4981            "memd(##$absaddr) = $src",
4982           [(store (i64 DoubleRegs:$src),
4983                   (HexagonCONST32 tglobaladdr:$absaddr))]>,
4984           Requires<[HasV4T]>;
4985
4986 let AddedComplexity = 30, isPredicated = 1 in
4987 def STrid_abs_cPt_V4 : STInst2<(outs),
4988           (ins PredRegs:$src1, globaladdress:$absaddr, DoubleRegs:$src2),
4989           "if ($src1) memd(##$absaddr) = $src2",
4990           []>,
4991           Requires<[HasV4T]>;
4992
4993 let AddedComplexity = 30, isPredicated = 1 in
4994 def STrid_abs_cNotPt_V4 : STInst2<(outs),
4995           (ins PredRegs:$src1, globaladdress:$absaddr, DoubleRegs:$src2),
4996           "if (!$src1) memd(##$absaddr) = $src2",
4997           []>,
4998           Requires<[HasV4T]>;
4999
5000 let AddedComplexity = 30, isPredicated = 1 in
5001 def STrid_abs_cdnPt_V4 : STInst2<(outs),
5002           (ins PredRegs:$src1, globaladdress:$absaddr, DoubleRegs:$src2),
5003           "if ($src1.new) memd(##$absaddr) = $src2",
5004           []>,
5005           Requires<[HasV4T]>;
5006
5007 let AddedComplexity = 30, isPredicated = 1 in
5008 def STrid_abs_cdnNotPt_V4 : STInst2<(outs),
5009           (ins PredRegs:$src1, globaladdress:$absaddr, DoubleRegs:$src2),
5010           "if (!$src1.new) memd(##$absaddr) = $src2",
5011           []>,
5012           Requires<[HasV4T]>;
5013
5014 defm STrib : ST_abs<"memb">;
5015 defm STrih : ST_abs<"memh">;
5016 defm STriw : ST_abs<"memw">;
5017
5018 let Predicates = [HasV4T], AddedComplexity  = 30 in
5019 def : Pat<(truncstorei8 (i32 IntRegs:$src1),
5020                         (HexagonCONST32 tglobaladdr:$absaddr)),
5021           (STrib_abs_V4 tglobaladdr: $absaddr, IntRegs: $src1)>;
5022
5023 let Predicates = [HasV4T], AddedComplexity  = 30 in
5024 def : Pat<(truncstorei16 (i32 IntRegs:$src1),
5025                           (HexagonCONST32 tglobaladdr:$absaddr)),
5026           (STrih_abs_V4 tglobaladdr: $absaddr, IntRegs: $src1)>;
5027
5028 let Predicates = [HasV4T], AddedComplexity  = 30 in
5029 def : Pat<(store (i32 IntRegs:$src1), (HexagonCONST32 tglobaladdr:$absaddr)),
5030           (STriw_abs_V4 tglobaladdr: $absaddr, IntRegs: $src1)>;
5031
5032
5033 multiclass LD_abs<string OpcStr> {
5034   let isPredicable = 1 in
5035   def _abs_V4 : LDInst2<(outs IntRegs:$dst),
5036             (ins globaladdress:$absaddr),
5037             !strconcat("$dst = ", !strconcat(OpcStr, "(##$absaddr)")),
5038             []>,
5039             Requires<[HasV4T]>;
5040
5041   let isPredicated = 1 in
5042   def _abs_cPt_V4 : LDInst2<(outs IntRegs:$dst),
5043             (ins PredRegs:$src1, globaladdress:$absaddr),
5044             !strconcat("if ($src1) $dst = ",
5045             !strconcat(OpcStr, "(##$absaddr)")),
5046             []>,
5047             Requires<[HasV4T]>;
5048
5049   let isPredicated = 1 in
5050   def _abs_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
5051             (ins PredRegs:$src1, globaladdress:$absaddr),
5052             !strconcat("if (!$src1) $dst = ",
5053             !strconcat(OpcStr, "(##$absaddr)")),
5054             []>,
5055             Requires<[HasV4T]>;
5056
5057   let isPredicated = 1 in
5058   def _abs_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
5059             (ins PredRegs:$src1, globaladdress:$absaddr),
5060             !strconcat("if ($src1.new) $dst = ",
5061             !strconcat(OpcStr, "(##$absaddr)")),
5062             []>,
5063             Requires<[HasV4T]>;
5064
5065   let isPredicated = 1 in
5066   def _abs_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
5067             (ins PredRegs:$src1, globaladdress:$absaddr),
5068             !strconcat("if (!$src1.new) $dst = ",
5069             !strconcat(OpcStr, "(##$absaddr)")),
5070             []>,
5071             Requires<[HasV4T]>;
5072 }
5073
5074 let AddedComplexity = 30 in
5075 def LDrid_abs_V4 : LDInst<(outs DoubleRegs:$dst),
5076           (ins globaladdress:$absaddr),
5077           "$dst = memd(##$absaddr)",
5078           [(set (i64 DoubleRegs:$dst),
5079                 (load (HexagonCONST32 tglobaladdr:$absaddr)))]>,
5080           Requires<[HasV4T]>;
5081
5082 let AddedComplexity = 30, isPredicated = 1 in
5083 def LDrid_abs_cPt_V4 : LDInst2<(outs DoubleRegs:$dst),
5084           (ins PredRegs:$src1, globaladdress:$absaddr),
5085           "if ($src1) $dst = memd(##$absaddr)",
5086           []>,
5087           Requires<[HasV4T]>;
5088
5089 let AddedComplexity = 30, isPredicated = 1 in
5090 def LDrid_abs_cNotPt_V4 : LDInst2<(outs DoubleRegs:$dst),
5091           (ins PredRegs:$src1, globaladdress:$absaddr),
5092           "if (!$src1) $dst = memd(##$absaddr)",
5093           []>,
5094           Requires<[HasV4T]>;
5095
5096 let AddedComplexity = 30, isPredicated = 1 in
5097 def LDrid_abs_cdnPt_V4 : LDInst2<(outs DoubleRegs:$dst),
5098           (ins PredRegs:$src1, globaladdress:$absaddr),
5099           "if ($src1.new) $dst = memd(##$absaddr)",
5100           []>,
5101           Requires<[HasV4T]>;
5102
5103 let AddedComplexity = 30, isPredicated = 1 in
5104 def LDrid_abs_cdnNotPt_V4 : LDInst2<(outs DoubleRegs:$dst),
5105           (ins PredRegs:$src1, globaladdress:$absaddr),
5106           "if (!$src1.new) $dst = memd(##$absaddr)",
5107           []>,
5108           Requires<[HasV4T]>;
5109
5110 defm LDrib : LD_abs<"memb">;
5111 defm LDriub : LD_abs<"memub">;
5112 defm LDrih : LD_abs<"memh">;
5113 defm LDriuh : LD_abs<"memuh">;
5114 defm LDriw : LD_abs<"memw">;
5115
5116
5117 let Predicates = [HasV4T], AddedComplexity  = 30 in
5118 def : Pat<(i32 (load (HexagonCONST32 tglobaladdr:$absaddr))),
5119           (LDriw_abs_V4 tglobaladdr: $absaddr)>;
5120
5121 let Predicates = [HasV4T], AddedComplexity=30 in
5122 def : Pat<(i32 (sextloadi8 (HexagonCONST32 tglobaladdr:$absaddr))),
5123           (LDrib_abs_V4 tglobaladdr:$absaddr)>;
5124
5125 let Predicates = [HasV4T], AddedComplexity=30 in
5126 def : Pat<(i32 (zextloadi8 (HexagonCONST32 tglobaladdr:$absaddr))),
5127           (LDriub_abs_V4 tglobaladdr:$absaddr)>;
5128
5129 let Predicates = [HasV4T], AddedComplexity=30 in
5130 def : Pat<(i32 (sextloadi16 (HexagonCONST32 tglobaladdr:$absaddr))),
5131           (LDrih_abs_V4 tglobaladdr:$absaddr)>;
5132
5133 let Predicates = [HasV4T], AddedComplexity=30 in
5134 def : Pat<(i32 (zextloadi16 (HexagonCONST32 tglobaladdr:$absaddr))),
5135           (LDriuh_abs_V4 tglobaladdr:$absaddr)>;
5136
5137 // Transfer global address into a register
5138 let AddedComplexity=50, isMoveImm = 1, isReMaterializable = 1 in
5139 def TFRI_V4 : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$src1),
5140            "$dst = ##$src1",
5141            [(set IntRegs:$dst, (HexagonCONST32 tglobaladdr:$src1))]>,
5142            Requires<[HasV4T]>;
5143
5144 let AddedComplexity=50, neverHasSideEffects = 1, isPredicated = 1 in
5145 def TFRI_cPt_V4 : ALU32_ri<(outs IntRegs:$dst),
5146                            (ins PredRegs:$src1, globaladdress:$src2),
5147            "if($src1) $dst = ##$src2",
5148            []>,
5149            Requires<[HasV4T]>;
5150
5151 let AddedComplexity=50, neverHasSideEffects = 1, isPredicated = 1 in
5152 def TFRI_cNotPt_V4 : ALU32_ri<(outs IntRegs:$dst),
5153                               (ins PredRegs:$src1, globaladdress:$src2),
5154            "if(!$src1) $dst = ##$src2",
5155            []>,
5156            Requires<[HasV4T]>;
5157
5158 let AddedComplexity=50, neverHasSideEffects = 1, isPredicated = 1 in
5159 def TFRI_cdnPt_V4 : ALU32_ri<(outs IntRegs:$dst),
5160                              (ins PredRegs:$src1, globaladdress:$src2),
5161            "if($src1.new) $dst = ##$src2",
5162            []>,
5163            Requires<[HasV4T]>;
5164
5165 let AddedComplexity=50, neverHasSideEffects = 1, isPredicated = 1 in
5166 def TFRI_cdnNotPt_V4 : ALU32_ri<(outs IntRegs:$dst),
5167                                 (ins PredRegs:$src1, globaladdress:$src2),
5168            "if(!$src1.new) $dst = ##$src2",
5169            []>,
5170            Requires<[HasV4T]>;
5171
5172 let AddedComplexity = 50, Predicates = [HasV4T] in
5173 def : Pat<(HexagonCONST32_GP tglobaladdr:$src1),
5174            (TFRI_V4 tglobaladdr:$src1)>;
5175
5176
5177 // Load - Indirect with long offset: These instructions take global address
5178 // as an operand
5179 let AddedComplexity = 10 in
5180 def LDrid_ind_lo_V4 : LDInst<(outs DoubleRegs:$dst),
5181             (ins IntRegs:$src1, u2Imm:$src2, globaladdress:$offset),
5182             "$dst=memd($src1<<#$src2+##$offset)",
5183             [(set (i64 DoubleRegs:$dst),
5184                   (load (add (shl IntRegs:$src1, u2ImmPred:$src2),
5185                         (HexagonCONST32 tglobaladdr:$offset))))]>,
5186             Requires<[HasV4T]>;
5187
5188 let AddedComplexity = 10 in
5189 multiclass LD_indirect_lo<string OpcStr, PatFrag OpNode> {
5190   def _lo_V4 : LDInst<(outs IntRegs:$dst),
5191             (ins IntRegs:$src1, u2Imm:$src2, globaladdress:$offset),
5192             !strconcat("$dst = ",
5193             !strconcat(OpcStr, "($src1<<#$src2+##$offset)")),
5194             [(set IntRegs:$dst,
5195                   (i32 (OpNode (add (shl IntRegs:$src1, u2ImmPred:$src2),
5196                           (HexagonCONST32 tglobaladdr:$offset)))))]>,
5197             Requires<[HasV4T]>;
5198 }
5199
5200 defm LDrib_ind : LD_indirect_lo<"memb", sextloadi8>;
5201 defm LDriub_ind : LD_indirect_lo<"memub", zextloadi8>;
5202 defm LDrih_ind : LD_indirect_lo<"memh", sextloadi16>;
5203 defm LDriuh_ind : LD_indirect_lo<"memuh", zextloadi16>;
5204 defm LDriw_ind : LD_indirect_lo<"memw", load>;
5205
5206 // Store - Indirect with long offset: These instructions take global address
5207 // as an operand
5208 let AddedComplexity = 10 in
5209 def STrid_ind_lo_V4 : STInst<(outs),
5210             (ins IntRegs:$src1, u2Imm:$src2, globaladdress:$src3,
5211                  DoubleRegs:$src4),
5212             "memd($src1<<#$src2+#$src3) = $src4",
5213             [(store (i64 DoubleRegs:$src4),
5214                  (add (shl IntRegs:$src1, u2ImmPred:$src2),
5215                       (HexagonCONST32 tglobaladdr:$src3)))]>,
5216              Requires<[HasV4T]>;
5217
5218 let AddedComplexity = 10 in
5219 multiclass ST_indirect_lo<string OpcStr, PatFrag OpNode> {
5220   def _lo_V4 : STInst<(outs),
5221             (ins IntRegs:$src1, u2Imm:$src2, globaladdress:$src3,
5222                  IntRegs:$src4),
5223             !strconcat(OpcStr, "($src1<<#$src2+##$src3) = $src4"),
5224             [(OpNode (i32 IntRegs:$src4),
5225                  (add (shl IntRegs:$src1, u2ImmPred:$src2),
5226                       (HexagonCONST32 tglobaladdr:$src3)))]>,
5227              Requires<[HasV4T]>;
5228 }
5229
5230 defm STrib_ind : ST_indirect_lo<"memb", truncstorei8>;
5231 defm STrih_ind : ST_indirect_lo<"memh", truncstorei16>;
5232 defm STriw_ind : ST_indirect_lo<"memw", store>;
5233
5234 // Store - absolute addressing mode: These instruction take constant
5235 // value as the extended operand
5236 multiclass ST_absimm<string OpcStr> {
5237   let isPredicable = 1 in
5238   def _abs_V4 : STInst2<(outs),
5239             (ins u6Imm:$src1, IntRegs:$src2),
5240             !strconcat(OpcStr, "(#$src1) = $src2"),
5241             []>,
5242             Requires<[HasV4T]>;
5243
5244   let isPredicated = 1 in
5245   def _abs_cPt_V4 : STInst2<(outs),
5246             (ins PredRegs:$src1, u6Imm:$src2, IntRegs:$src3),
5247             !strconcat("if ($src1)", !strconcat(OpcStr, "(#$src2) = $src3")),
5248             []>,
5249             Requires<[HasV4T]>;
5250
5251   let isPredicated = 1 in
5252   def _abs_cNotPt_V4 : STInst2<(outs),
5253             (ins PredRegs:$src1, u6Imm:$src2, IntRegs:$src3),
5254             !strconcat("if (!$src1)", !strconcat(OpcStr, "(#$src2) = $src3")),
5255             []>,
5256             Requires<[HasV4T]>;
5257
5258   let isPredicated = 1 in
5259   def _abs_cdnPt_V4 : STInst2<(outs),
5260             (ins PredRegs:$src1, u6Imm:$src2, IntRegs:$src3),
5261             !strconcat("if ($src1.new)",
5262             !strconcat(OpcStr, "(#$src2) = $src3")),
5263             []>,
5264             Requires<[HasV4T]>;
5265
5266   let isPredicated = 1 in
5267   def _abs_cdnNotPt_V4 : STInst2<(outs),
5268             (ins PredRegs:$src1, u6Imm:$src2, IntRegs:$src3),
5269             !strconcat("if (!$src1.new)",
5270             !strconcat(OpcStr, "(#$src2) = $src3")),
5271             []>,
5272             Requires<[HasV4T]>;
5273
5274   def _abs_nv_V4 : STInst2<(outs),
5275             (ins u6Imm:$src1, IntRegs:$src2),
5276             !strconcat(OpcStr, "(#$src1) = $src2.new"),
5277             []>,
5278             Requires<[HasV4T]>;
5279
5280   let isPredicated = 1 in
5281   def _abs_cPt_nv_V4 : STInst2<(outs),
5282             (ins PredRegs:$src1, u6Imm:$src2, IntRegs:$src3),
5283             !strconcat("if ($src1)",
5284             !strconcat(OpcStr, "(#$src2) = $src3.new")),
5285             []>,
5286             Requires<[HasV4T]>;
5287
5288   let isPredicated = 1 in
5289   def _abs_cNotPt_nv_V4 : STInst2<(outs),
5290             (ins PredRegs:$src1, u6Imm:$src2, IntRegs:$src3),
5291             !strconcat("if (!$src1)",
5292             !strconcat(OpcStr, "(#$src2) = $src3.new")),
5293             []>,
5294             Requires<[HasV4T]>;
5295
5296   let isPredicated = 1 in
5297   def _abs_cdnPt_nv_V4 : STInst2<(outs),
5298             (ins PredRegs:$src1, u6Imm:$src2, IntRegs:$src3),
5299             !strconcat("if ($src1.new)",
5300             !strconcat(OpcStr, "(#$src2) = $src3.new")),
5301             []>,
5302             Requires<[HasV4T]>;
5303
5304   let isPredicated = 1 in
5305   def _abs_cdnNotPt_nv_V4 : STInst2<(outs),
5306             (ins PredRegs:$src1, u6Imm:$src2, IntRegs:$src3),
5307             !strconcat("if (!$src1.new)",
5308             !strconcat(OpcStr, "(#$src2) = $src3.new")),
5309             []>,
5310             Requires<[HasV4T]>;
5311 }
5312
5313 defm STrib_imm : ST_absimm<"memb">;
5314 defm STrih_imm : ST_absimm<"memh">;
5315 defm STriw_imm : ST_absimm<"memw">;
5316
5317 let Predicates = [HasV4T], AddedComplexity  = 30 in
5318 def : Pat<(truncstorei8 (i32 IntRegs:$src1), u6ImmPred:$src2),
5319           (STrib_imm_abs_V4 u6ImmPred:$src2, IntRegs: $src1)>;
5320
5321 let Predicates = [HasV4T], AddedComplexity  = 30 in
5322 def : Pat<(truncstorei16 (i32 IntRegs:$src1), u6ImmPred:$src2),
5323           (STrih_imm_abs_V4 u6ImmPred:$src2, IntRegs: $src1)>;
5324
5325 let Predicates = [HasV4T], AddedComplexity  = 30 in
5326 def : Pat<(store (i32 IntRegs:$src1), u6ImmPred:$src2),
5327           (STriw_imm_abs_V4 u6ImmPred:$src2, IntRegs: $src1)>;
5328
5329
5330 // Load - absolute addressing mode: These instruction take constant
5331 // value as the extended operand
5332
5333 multiclass LD_absimm<string OpcStr> {
5334   let isPredicable = 1 in
5335   def _abs_V4 : LDInst2<(outs IntRegs:$dst),
5336             (ins u6Imm:$src),
5337             !strconcat("$dst = ",
5338             !strconcat(OpcStr, "(#$src)")),
5339             []>,
5340             Requires<[HasV4T]>;
5341
5342   let isPredicated = 1 in
5343   def _abs_cPt_V4 : LDInst2<(outs IntRegs:$dst),
5344             (ins PredRegs:$src1, u6Imm:$src2),
5345             !strconcat("if ($src1) $dst = ",
5346             !strconcat(OpcStr, "(#$src2)")),
5347             []>,
5348             Requires<[HasV4T]>;
5349
5350   let isPredicated = 1 in
5351   def _abs_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
5352             (ins PredRegs:$src1, u6Imm:$src2),
5353             !strconcat("if (!$src1) $dst = ",
5354             !strconcat(OpcStr, "(#$src2)")),
5355             []>,
5356             Requires<[HasV4T]>;
5357
5358   let isPredicated = 1 in
5359   def _abs_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
5360             (ins PredRegs:$src1, u6Imm:$src2),
5361             !strconcat("if ($src1.new) $dst = ",
5362             !strconcat(OpcStr, "(#$src2)")),
5363             []>,
5364             Requires<[HasV4T]>;
5365
5366   let isPredicated = 1 in
5367   def _abs_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
5368             (ins PredRegs:$src1, u6Imm:$src2),
5369             !strconcat("if (!$src1.new) $dst = ",
5370             !strconcat(OpcStr, "(#$src2)")),
5371             []>,
5372             Requires<[HasV4T]>;
5373 }
5374
5375 defm LDrib_imm : LD_absimm<"memb">;
5376 defm LDriub_imm : LD_absimm<"memub">;
5377 defm LDrih_imm : LD_absimm<"memh">;
5378 defm LDriuh_imm : LD_absimm<"memuh">;
5379 defm LDriw_imm : LD_absimm<"memw">;
5380
5381 let Predicates = [HasV4T], AddedComplexity  = 30 in
5382 def : Pat<(i32 (load u6ImmPred:$src)),
5383           (LDriw_imm_abs_V4 u6ImmPred:$src)>;
5384
5385 let Predicates = [HasV4T], AddedComplexity=30 in
5386 def : Pat<(i32 (sextloadi8 u6ImmPred:$src)),
5387           (LDrib_imm_abs_V4 u6ImmPred:$src)>;
5388
5389 let Predicates = [HasV4T], AddedComplexity=30 in
5390 def : Pat<(i32 (zextloadi8 u6ImmPred:$src)),
5391           (LDriub_imm_abs_V4 u6ImmPred:$src)>;
5392
5393 let Predicates = [HasV4T], AddedComplexity=30 in
5394 def : Pat<(i32 (sextloadi16 u6ImmPred:$src)),
5395           (LDrih_imm_abs_V4 u6ImmPred:$src)>;
5396
5397 let Predicates = [HasV4T], AddedComplexity=30 in
5398 def : Pat<(i32 (zextloadi16 u6ImmPred:$src)),
5399           (LDriuh_imm_abs_V4 u6ImmPred:$src)>;
5400
5401
5402 // Indexed store double word - global address.
5403 // memw(Rs+#u6:2)=#S8
5404 let AddedComplexity = 10 in
5405 def STriw_offset_ext_V4 : STInst<(outs),
5406             (ins IntRegs:$src1, u6_2Imm:$src2, globaladdress:$src3),
5407             "memw($src1+#$src2) = ##$src3",
5408             [(store (HexagonCONST32 tglobaladdr:$src3),
5409                     (add IntRegs:$src1, u6_2ImmPred:$src2))]>,
5410             Requires<[HasV4T]>;
5411
5412
5413 // Indexed store double word - global address.
5414 // memw(Rs+#u6:2)=#S8
5415 let AddedComplexity = 10 in
5416 def STrih_offset_ext_V4 : STInst<(outs),
5417             (ins IntRegs:$src1, u6_1Imm:$src2, globaladdress:$src3),
5418             "memh($src1+#$src2) = ##$src3",
5419             [(truncstorei16 (HexagonCONST32 tglobaladdr:$src3),
5420                     (add IntRegs:$src1, u6_1ImmPred:$src2))]>,
5421             Requires<[HasV4T]>;