lib/Target/Hexagon/HexagonInstrInfoV4.td

   1 //=- HexagonInstrInfoV4.td - Target Desc. for Hexagon Target -*- tablegen -*-=//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file describes the Hexagon V4 instructions in TableGen format.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 let neverHasSideEffects = 1 in
  15 class T_Immext<dag ins> :
  16   EXTENDERInst<(outs), ins, "immext(#$imm)", []>,
  17   Requires<[HasV4T]>;
  18
  19 def IMMEXT_b : T_Immext<(ins brtarget:$imm)>;
  20 def IMMEXT_c : T_Immext<(ins calltarget:$imm)>;
  21 def IMMEXT_g : T_Immext<(ins globaladdress:$imm)>;
  22 def IMMEXT_i : T_Immext<(ins u26_6Imm:$imm)>;
  23
  24 // Hexagon V4 Architecture spec defines 8 instruction classes:
  25 // LD ST ALU32 XTYPE J JR MEMOP NV CR SYSTEM(system is not implemented in the
  26 // compiler)
  27
  28 // LD Instructions:
  29 // ========================================
  30 // Loads (8/16/32/64 bit)
  31 // Deallocframe
  32
  33 // ST Instructions:
  34 // ========================================
  35 // Stores (8/16/32/64 bit)
  36 // Allocframe
  37
  38 // ALU32 Instructions:
  39 // ========================================
  40 // Arithmetic / Logical (32 bit)
  41 // Vector Halfword
  42
  43 // XTYPE Instructions (32/64 bit):
  44 // ========================================
  45 // Arithmetic, Logical, Bit Manipulation
  46 // Multiply (Integer, Fractional, Complex)
  47 // Permute / Vector Permute Operations
  48 // Predicate Operations
  49 // Shift / Shift with Add/Sub/Logical
  50 // Vector Byte ALU
  51 // Vector Halfword (ALU, Shift, Multiply)
  52 // Vector Word (ALU, Shift)
  53
  54 // J Instructions:
  55 // ========================================
  56 // Jump/Call PC-relative
  57
  58 // JR Instructions:
  59 // ========================================
  60 // Jump/Call Register
  61
  62 // MEMOP Instructions:
  63 // ========================================
  64 // Operation on memory (8/16/32 bit)
  65
  66 // NV Instructions:
  67 // ========================================
  68 // New-value Jumps
  69 // New-value Stores
  70
  71 // CR Instructions:
  72 // ========================================
  73 // Control-Register Transfers
  74 // Hardware Loop Setup
  75 // Predicate Logicals & Reductions
  76
  77 // SYSTEM Instructions (not implemented in the compiler):
  78 // ========================================
  79 // Prefetch
  80 // Cache Maintenance
  81 // Bus Operations
  82
  83
  84 //===----------------------------------------------------------------------===//
  85 // ALU32 +
  86 //===----------------------------------------------------------------------===//
  87
  88 // Shift halfword.
  89
  90 let isPredicated = 1, neverHasSideEffects = 1, validSubTargets = HasV4SubT in {
  91 def ASLH_cPt_V4 : ALU32_rr<(outs IntRegs:$dst),
  92             (ins PredRegs:$src1, IntRegs:$src2),
  93             "if ($src1) $dst = aslh($src2)",
  94             []>,
  95             Requires<[HasV4T]>;
  96
  97 def ASLH_cNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
  98             (ins PredRegs:$src1, IntRegs:$src2),
  99             "if (!$src1) $dst = aslh($src2)",
 100             []>,
 101             Requires<[HasV4T]>;
 102
 103 def ASLH_cdnPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 104             (ins PredRegs:$src1, IntRegs:$src2),
 105             "if ($src1.new) $dst = aslh($src2)",
 106             []>,
 107             Requires<[HasV4T]>;
 108
 109 def ASLH_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 110             (ins PredRegs:$src1, IntRegs:$src2),
 111             "if (!$src1.new) $dst = aslh($src2)",
 112             []>,
 113             Requires<[HasV4T]>;
 114
 115 def ASRH_cPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 116             (ins PredRegs:$src1, IntRegs:$src2),
 117             "if ($src1) $dst = asrh($src2)",
 118             []>,
 119             Requires<[HasV4T]>;
 120
 121 def ASRH_cNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 122             (ins PredRegs:$src1, IntRegs:$src2),
 123             "if (!$src1) $dst = asrh($src2)",
 124             []>,
 125             Requires<[HasV4T]>;
 126
 127 def ASRH_cdnPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 128             (ins PredRegs:$src1, IntRegs:$src2),
 129             "if ($src1.new) $dst = asrh($src2)",
 130             []>,
 131             Requires<[HasV4T]>;
 132
 133 def ASRH_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 134             (ins PredRegs:$src1, IntRegs:$src2),
 135             "if (!$src1.new) $dst = asrh($src2)",
 136             []>,
 137             Requires<[HasV4T]>;
 138 }
 139
 140 // Sign extend.
 141
 142 let isPredicated = 1, neverHasSideEffects = 1, validSubTargets = HasV4SubT in {
 143 def SXTB_cPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 144             (ins PredRegs:$src1, IntRegs:$src2),
 145             "if ($src1) $dst = sxtb($src2)",
 146             []>,
 147             Requires<[HasV4T]>;
 148
 149 def SXTB_cNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 150             (ins PredRegs:$src1, IntRegs:$src2),
 151             "if (!$src1) $dst = sxtb($src2)",
 152             []>,
 153             Requires<[HasV4T]>;
 154
 155 def SXTB_cdnPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 156             (ins PredRegs:$src1, IntRegs:$src2),
 157             "if ($src1.new) $dst = sxtb($src2)",
 158             []>,
 159             Requires<[HasV4T]>;
 160
 161 def SXTB_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 162             (ins PredRegs:$src1, IntRegs:$src2),
 163             "if (!$src1.new) $dst = sxtb($src2)",
 164             []>,
 165             Requires<[HasV4T]>;
 166
 167
 168 def SXTH_cPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 169             (ins PredRegs:$src1, IntRegs:$src2),
 170             "if ($src1) $dst = sxth($src2)",
 171             []>,
 172             Requires<[HasV4T]>;
 173
 174 def SXTH_cNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 175             (ins PredRegs:$src1, IntRegs:$src2),
 176             "if (!$src1) $dst = sxth($src2)",
 177             []>,
 178             Requires<[HasV4T]>;
 179
 180 def SXTH_cdnPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 181             (ins PredRegs:$src1, IntRegs:$src2),
 182             "if ($src1.new) $dst = sxth($src2)",
 183             []>,
 184             Requires<[HasV4T]>;
 185
 186 def SXTH_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 187             (ins PredRegs:$src1, IntRegs:$src2),
 188             "if (!$src1.new) $dst = sxth($src2)",
 189             []>,
 190             Requires<[HasV4T]>;
 191 }
 192
 193 // Zero exten.
 194
 195 let neverHasSideEffects = 1, isPredicated = 1, validSubTargets = HasV4SubT in {
 196 def ZXTB_cPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 197             (ins PredRegs:$src1, IntRegs:$src2),
 198             "if ($src1) $dst = zxtb($src2)",
 199             []>,
 200             Requires<[HasV4T]>;
 201
 202 def ZXTB_cNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 203             (ins PredRegs:$src1, IntRegs:$src2),
 204             "if (!$src1) $dst = zxtb($src2)",
 205             []>,
 206             Requires<[HasV4T]>;
 207
 208 def ZXTB_cdnPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 209             (ins PredRegs:$src1, IntRegs:$src2),
 210             "if ($src1.new) $dst = zxtb($src2)",
 211             []>,
 212             Requires<[HasV4T]>;
 213
 214 def ZXTB_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 215             (ins PredRegs:$src1, IntRegs:$src2),
 216             "if (!$src1.new) $dst = zxtb($src2)",
 217             []>,
 218             Requires<[HasV4T]>;
 219
 220 def ZXTH_cPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 221             (ins PredRegs:$src1, IntRegs:$src2),
 222             "if ($src1) $dst = zxth($src2)",
 223             []>,
 224             Requires<[HasV4T]>;
 225
 226 def ZXTH_cNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 227             (ins PredRegs:$src1, IntRegs:$src2),
 228             "if (!$src1) $dst = zxth($src2)",
 229             []>,
 230             Requires<[HasV4T]>;
 231
 232 def ZXTH_cdnPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 233             (ins PredRegs:$src1, IntRegs:$src2),
 234             "if ($src1.new) $dst = zxth($src2)",
 235             []>,
 236             Requires<[HasV4T]>;
 237
 238 def ZXTH_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
 239             (ins PredRegs:$src1, IntRegs:$src2),
 240             "if (!$src1.new) $dst = zxth($src2)",
 241             []>,
 242             Requires<[HasV4T]>;
 243 }
 244
 245 // Generate frame index addresses.
 246 let neverHasSideEffects = 1, isReMaterializable = 1,
 247 isExtended = 1, opExtendable = 2, validSubTargets = HasV4SubT in
 248 def TFR_FI_immext_V4 : ALU32_ri<(outs IntRegs:$dst),
 249             (ins IntRegs:$src1, s32Imm:$offset),
 250             "$dst = add($src1, ##$offset)",
 251             []>,
 252             Requires<[HasV4T]>;
 253
 254
 255 //===----------------------------------------------------------------------===//
 256 // ALU32 -
 257 //===----------------------------------------------------------------------===//
 258
 259
 260 //===----------------------------------------------------------------------===//
 261 // ALU32/PERM +
 262 //===----------------------------------------------------------------------===//
 263
 264 // Combine
 265 // Rdd=combine(Rs, #s8)
 266 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 8,
 267     neverHasSideEffects = 1, validSubTargets = HasV4SubT in
 268 def COMBINE_rI_V4 : ALU32_ri<(outs DoubleRegs:$dst),
 269             (ins IntRegs:$src1, s8Ext:$src2),
 270             "$dst = combine($src1, #$src2)",
 271             []>,
 272             Requires<[HasV4T]>;
 273
 274 // Rdd=combine(#s8, Rs)
 275 let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 8,
 276     neverHasSideEffects = 1, validSubTargets = HasV4SubT in
 277 def COMBINE_Ir_V4 : ALU32_ir<(outs DoubleRegs:$dst),
 278             (ins s8Ext:$src1, IntRegs:$src2),
 279             "$dst = combine(#$src1, $src2)",
 280             []>,
 281             Requires<[HasV4T]>;
 282
 283 let isExtendable = 1, opExtendable = 2, isExtentSigned = 0, opExtentBits = 6,
 284     neverHasSideEffects = 1, validSubTargets = HasV4SubT in
 285 def COMBINE_iI_V4 : ALU32_ii<(outs DoubleRegs:$dst),
 286             (ins s8Imm:$src1, u6Ext:$src2),
 287             "$dst = combine(#$src1, #$src2)",
 288             []>,
 289             Requires<[HasV4T]>;
 290
 291 //===----------------------------------------------------------------------===//
 292 // ALU32/PERM +
 293 //===----------------------------------------------------------------------===//
 294
 295 //===----------------------------------------------------------------------===//
 296 // LD +
 297 //===----------------------------------------------------------------------===//
 298 //
 299 // These absolute set addressing mode instructions accept immediate as
 300 // an operand. We have duplicated these patterns to take global address.
 301
 302 let isExtended = 1, opExtendable = 2, neverHasSideEffects = 1,
 303 validSubTargets = HasV4SubT in {
 304 def LDrid_abs_setimm_V4 : LDInst2<(outs DoubleRegs:$dst1, IntRegs:$dst2),
 305             (ins u0AlwaysExt:$addr),
 306             "$dst1 = memd($dst2=##$addr)",
 307             []>,
 308             Requires<[HasV4T]>;
 309
 310 // Rd=memb(Re=#U6)
 311 def LDrib_abs_setimm_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
 312             (ins u0AlwaysExt:$addr),
 313             "$dst1 = memb($dst2=##$addr)",
 314             []>,
 315             Requires<[HasV4T]>;
 316
 317 // Rd=memh(Re=#U6)
 318 def LDrih_abs_setimm_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
 319             (ins u0AlwaysExt:$addr),
 320             "$dst1 = memh($dst2=##$addr)",
 321             []>,
 322             Requires<[HasV4T]>;
 323
 324 // Rd=memub(Re=#U6)
 325 def LDriub_abs_setimm_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
 326             (ins u0AlwaysExt:$addr),
 327             "$dst1 = memub($dst2=##$addr)",
 328             []>,
 329             Requires<[HasV4T]>;
 330
 331 // Rd=memuh(Re=#U6)
 332 def LDriuh_abs_setimm_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
 333             (ins u0AlwaysExt:$addr),
 334             "$dst1 = memuh($dst2=##$addr)",
 335             []>,
 336             Requires<[HasV4T]>;
 337
 338 // Rd=memw(Re=#U6)
 339 def LDriw_abs_setimm_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
 340             (ins u0AlwaysExt:$addr),
 341             "$dst1 = memw($dst2=##$addr)",
 342             []>,
 343             Requires<[HasV4T]>;
 344 }
 345
 346 // Following patterns are defined for absolute set addressing mode
 347 // instruction which take global address as operand.
 348 let isExtended = 1, opExtendable = 2, neverHasSideEffects = 1,
 349 validSubTargets = HasV4SubT in {
 350 def LDrid_abs_set_V4 : LDInst2<(outs DoubleRegs:$dst1, IntRegs:$dst2),
 351             (ins globaladdressExt:$addr),
 352             "$dst1 = memd($dst2=##$addr)",
 353             []>,
 354             Requires<[HasV4T]>;
 355
 356 // Rd=memb(Re=#U6)
 357 def LDrib_abs_set_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
 358             (ins globaladdressExt:$addr),
 359             "$dst1 = memb($dst2=##$addr)",
 360             []>,
 361             Requires<[HasV4T]>;
 362
 363 // Rd=memh(Re=#U6)
 364 def LDrih_abs_set_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
 365             (ins globaladdressExt:$addr),
 366             "$dst1 = memh($dst2=##$addr)",
 367             []>,
 368             Requires<[HasV4T]>;
 369
 370 // Rd=memub(Re=#U6)
 371 def LDriub_abs_set_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
 372             (ins globaladdressExt:$addr),
 373             "$dst1 = memub($dst2=##$addr)",
 374             []>,
 375             Requires<[HasV4T]>;
 376
 377 // Rd=memuh(Re=#U6)
 378 def LDriuh_abs_set_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
 379             (ins globaladdressExt:$addr),
 380             "$dst1 = memuh($dst2=##$addr)",
 381             []>,
 382             Requires<[HasV4T]>;
 383
 384 // Rd=memw(Re=#U6)
 385 def LDriw_abs_set_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
 386             (ins globaladdressExt:$addr),
 387             "$dst1 = memw($dst2=##$addr)",
 388             []>,
 389             Requires<[HasV4T]>;
 390 }
 391
 392 // Load doubleword.
 393 //
 394 // Make sure that in post increment load, the first operand is always the post
 395 // increment operand.
 396 //
 397 // Rdd=memd(Rs+Rt<<#u2)
 398 // Special case pattern for indexed load without offset which is easier to
 399 // match. AddedComplexity of this pattern should be lower than base+offset load
 400 // and lower yet than the more generic version with offset/shift below
 401 // Similar approach is taken for all other base+index loads.
 402 let AddedComplexity = 10, isPredicable = 1 in
 403 def LDrid_indexed_V4 : LDInst<(outs DoubleRegs:$dst),
 404                     (ins IntRegs:$src1, IntRegs:$src2),
 405                     "$dst=memd($src1+$src2<<#0)",
 406                     [(set (i64 DoubleRegs:$dst),
 407                           (i64 (load (add (i32 IntRegs:$src1),
 408                                           (i32 IntRegs:$src2)))))]>,
 409                     Requires<[HasV4T]>;
 410
 411 // multiclass for load instructions with base + register offset
 412 // addressing mode
 413 multiclass ld_idxd_shl_pbase<string mnemonic, RegisterClass RC, bit isNot,
 414                              bit isPredNew> {
 415   let PNewValue = !if(isPredNew, "new", "") in
 416   def NAME : LDInst2<(outs RC:$dst),
 417             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$offset),
 418             !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
 419             ") ")#"$dst = "#mnemonic#"($src2+$src3<<#$offset)",
 420             []>, Requires<[HasV4T]>;
 421 }
 422
 423 multiclass ld_idxd_shl_pred<string mnemonic, RegisterClass RC, bit PredNot> {
 424   let PredSense = !if(PredNot, "false", "true") in {
 425     defm _c#NAME : ld_idxd_shl_pbase<mnemonic, RC, PredNot, 0>;
 426     // Predicate new
 427     defm _cdn#NAME : ld_idxd_shl_pbase<mnemonic, RC, PredNot, 1>;
 428   }
 429 }
 430
 431 let neverHasSideEffects  = 1 in
 432 multiclass ld_idxd_shl<string mnemonic, string CextOp, RegisterClass RC> {
 433   let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed_shl in {
 434     let isPredicable = 1 in
 435     def NAME#_V4 : LDInst2<(outs RC:$dst),
 436             (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$offset),
 437             "$dst = "#mnemonic#"($src1+$src2<<#$offset)",
 438             []>, Requires<[HasV4T]>;
 439
 440     let isPredicated = 1 in {
 441       defm Pt_V4 : ld_idxd_shl_pred<mnemonic, RC, 0 >;
 442       defm NotPt_V4 : ld_idxd_shl_pred<mnemonic, RC, 1>;
 443     }
 444   }
 445 }
 446
 447 let addrMode = BaseRegOffset in {
 448   defm LDrib_indexed_shl: ld_idxd_shl<"memb", "LDrib", IntRegs>, AddrModeRel;
 449   defm LDriub_indexed_shl: ld_idxd_shl<"memub", "LDriub", IntRegs>, AddrModeRel;
 450   defm LDrih_indexed_shl: ld_idxd_shl<"memh", "LDrih", IntRegs>, AddrModeRel;
 451   defm LDriuh_indexed_shl: ld_idxd_shl<"memuh", "LDriuh", IntRegs>, AddrModeRel;
 452   defm LDriw_indexed_shl: ld_idxd_shl<"memw", "LDriw", IntRegs>, AddrModeRel;
 453   defm LDrid_indexed_shl: ld_idxd_shl<"memd", "LDrid", DoubleRegs>, AddrModeRel;
 454 }
 455
 456 // 'def pats' for load instructions with base + register offset and non-zero
 457 // immediate value. Immediate value is used to left-shift the second
 458 // register operand.
 459 let AddedComplexity = 40 in {
 460 def : Pat <(i32 (sextloadi8 (add IntRegs:$src1,
 461                                  (shl IntRegs:$src2, u2ImmPred:$offset)))),
 462            (LDrib_indexed_shl_V4 IntRegs:$src1,
 463             IntRegs:$src2, u2ImmPred:$offset)>,
 464             Requires<[HasV4T]>;
 465
 466 def : Pat <(i32 (zextloadi8 (add IntRegs:$src1,
 467                                  (shl IntRegs:$src2, u2ImmPred:$offset)))),
 468            (LDriub_indexed_shl_V4 IntRegs:$src1,
 469             IntRegs:$src2, u2ImmPred:$offset)>,
 470             Requires<[HasV4T]>;
 471
 472 def : Pat <(i32 (extloadi8 (add IntRegs:$src1,
 473                                 (shl IntRegs:$src2, u2ImmPred:$offset)))),
 474            (LDriub_indexed_shl_V4 IntRegs:$src1,
 475             IntRegs:$src2, u2ImmPred:$offset)>,
 476             Requires<[HasV4T]>;
 477
 478 def : Pat <(i32 (sextloadi16 (add IntRegs:$src1,
 479                                   (shl IntRegs:$src2, u2ImmPred:$offset)))),
 480            (LDrih_indexed_shl_V4 IntRegs:$src1,
 481             IntRegs:$src2, u2ImmPred:$offset)>,
 482             Requires<[HasV4T]>;
 483
 484 def : Pat <(i32 (zextloadi16 (add IntRegs:$src1,
 485                                   (shl IntRegs:$src2, u2ImmPred:$offset)))),
 486            (LDriuh_indexed_shl_V4 IntRegs:$src1,
 487             IntRegs:$src2, u2ImmPred:$offset)>,
 488             Requires<[HasV4T]>;
 489
 490 def : Pat <(i32 (extloadi16 (add IntRegs:$src1,
 491                                  (shl IntRegs:$src2, u2ImmPred:$offset)))),
 492            (LDriuh_indexed_shl_V4 IntRegs:$src1,
 493             IntRegs:$src2, u2ImmPred:$offset)>,
 494             Requires<[HasV4T]>;
 495
 496 def : Pat <(i32 (load (add IntRegs:$src1,
 497                            (shl IntRegs:$src2, u2ImmPred:$offset)))),
 498            (LDriw_indexed_shl_V4 IntRegs:$src1,
 499             IntRegs:$src2, u2ImmPred:$offset)>,
 500             Requires<[HasV4T]>;
 501
 502 def : Pat <(i64 (load (add IntRegs:$src1,
 503                            (shl IntRegs:$src2, u2ImmPred:$offset)))),
 504            (LDrid_indexed_shl_V4 IntRegs:$src1,
 505             IntRegs:$src2, u2ImmPred:$offset)>,
 506             Requires<[HasV4T]>;
 507 }
 508
 509 //// Load doubleword conditionally.
 510 // if ([!]Pv[.new]) Rd=memd(Rs+Rt<<#u2)
 511 // if (Pv) Rd=memd(Rs+Rt<<#u2)
 512 let AddedComplexity = 15, isPredicated = 1 in
 513 def LDrid_indexed_cPt_V4 : LDInst2<(outs DoubleRegs:$dst),
 514                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 515                     "if ($src1) $dst=memd($src2+$src3<<#0)",
 516                     []>,
 517                     Requires<[HasV4T]>;
 518
 519 // if (Pv.new) Rd=memd(Rs+Rt<<#u2)
 520 let AddedComplexity = 15, isPredicated = 1 in
 521 def LDrid_indexed_cdnPt_V4 : LDInst2<(outs DoubleRegs:$dst),
 522                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 523                     "if ($src1.new) $dst=memd($src2+$src3<<#0)",
 524                     []>,
 525                     Requires<[HasV4T]>;
 526
 527 // if (!Pv) Rd=memd(Rs+Rt<<#u2)
 528 let AddedComplexity = 15, isPredicated = 1 in
 529 def LDrid_indexed_cNotPt_V4 : LDInst2<(outs DoubleRegs:$dst),
 530                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 531                     "if (!$src1) $dst=memd($src2+$src3<<#0)",
 532                     []>,
 533                     Requires<[HasV4T]>;
 534
 535 // if (!Pv.new) Rd=memd(Rs+Rt<<#u2)
 536 let AddedComplexity = 15, isPredicated = 1 in
 537 def LDrid_indexed_cdnNotPt_V4 : LDInst2<(outs DoubleRegs:$dst),
 538                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 539                     "if (!$src1.new) $dst=memd($src2+$src3<<#0)",
 540                     []>,
 541                     Requires<[HasV4T]>;
 542
 543 // Rdd=memd(Rt<<#u2+#U6)
 544
 545 //// Load byte.
 546 // Rd=memb(Rs+Rt<<#u2)
 547 let AddedComplexity = 10, isPredicable = 1 in
 548 def LDrib_indexed_V4 : LDInst<(outs IntRegs:$dst),
 549                     (ins IntRegs:$src1, IntRegs:$src2),
 550                     "$dst=memb($src1+$src2<<#0)",
 551                     [(set (i32 IntRegs:$dst),
 552                           (i32 (sextloadi8 (add (i32 IntRegs:$src1),
 553                                                 (i32 IntRegs:$src2)))))]>,
 554                     Requires<[HasV4T]>;
 555
 556 let AddedComplexity = 10, isPredicable = 1 in
 557 def LDriub_indexed_V4 : LDInst<(outs IntRegs:$dst),
 558                     (ins IntRegs:$src1, IntRegs:$src2),
 559                     "$dst=memub($src1+$src2<<#0)",
 560                     [(set (i32 IntRegs:$dst),
 561                           (i32 (zextloadi8 (add (i32 IntRegs:$src1),
 562                                                 (i32 IntRegs:$src2)))))]>,
 563                     Requires<[HasV4T]>;
 564
 565 let AddedComplexity = 10, isPredicable = 1 in
 566 def LDriub_ae_indexed_V4 : LDInst<(outs IntRegs:$dst),
 567                     (ins IntRegs:$src1, IntRegs:$src2),
 568                     "$dst=memub($src1+$src2<<#0)",
 569                     [(set (i32 IntRegs:$dst),
 570                           (i32 (extloadi8 (add (i32 IntRegs:$src1),
 571                                                (i32 IntRegs:$src2)))))]>,
 572                     Requires<[HasV4T]>;
 573
 574 let AddedComplexity = 40, isPredicable = 1 in
 575 def LDriub_ae_indexed_shl_V4 : LDInst<(outs IntRegs:$dst),
 576                     (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$offset),
 577                     "$dst=memub($src1+$src2<<#$offset)",
 578                     [(set (i32 IntRegs:$dst),
 579                           (i32 (extloadi8 (add (i32 IntRegs:$src1),
 580                                                (shl (i32 IntRegs:$src2),
 581                                                     u2ImmPred:$offset)))))]>,
 582                     Requires<[HasV4T]>;
 583
 584 //// Load byte conditionally.
 585 // if ([!]Pv[.new]) Rd=memb(Rs+Rt<<#u2)
 586 // if (Pv) Rd=memb(Rs+Rt<<#u2)
 587 let AddedComplexity = 15, isPredicated = 1 in
 588 def LDrib_indexed_cPt_V4 : LDInst2<(outs IntRegs:$dst),
 589                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 590                     "if ($src1) $dst=memb($src2+$src3<<#0)",
 591                     []>,
 592                     Requires<[HasV4T]>;
 593
 594 // if (Pv.new) Rd=memb(Rs+Rt<<#u2)
 595 let AddedComplexity = 15, isPredicated = 1 in
 596 def LDrib_indexed_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
 597                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 598                     "if ($src1.new) $dst=memb($src2+$src3<<#0)",
 599                     []>,
 600                     Requires<[HasV4T]>;
 601
 602 // if (!Pv) Rd=memb(Rs+Rt<<#u2)
 603 let AddedComplexity = 15, isPredicated = 1 in
 604 def LDrib_indexed_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 605                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 606                     "if (!$src1) $dst=memb($src2+$src3<<#0)",
 607                     []>,
 608                     Requires<[HasV4T]>;
 609
 610 // if (!Pv.new) Rd=memb(Rs+Rt<<#u2)
 611 let AddedComplexity = 15, isPredicated = 1 in
 612 def LDrib_indexed_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 613                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 614                     "if (!$src1.new) $dst=memb($src2+$src3<<#0)",
 615                     []>,
 616                     Requires<[HasV4T]>;
 617
 618 //// Load unsigned byte conditionally.
 619 // if ([!]Pv[.new]) Rd=memub(Rs+Rt<<#u2)
 620 // if (Pv) Rd=memub(Rs+Rt<<#u2)
 621 let AddedComplexity = 15, isPredicated = 1 in
 622 def LDriub_indexed_cPt_V4 : LDInst2<(outs IntRegs:$dst),
 623                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 624                     "if ($src1) $dst=memub($src2+$src3<<#0)",
 625                     []>,
 626                     Requires<[HasV4T]>;
 627
 628 // if (Pv.new) Rd=memub(Rs+Rt<<#u2)
 629 let AddedComplexity = 15, isPredicated = 1 in
 630 def LDriub_indexed_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
 631                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 632                     "if ($src1.new) $dst=memub($src2+$src3<<#0)",
 633                     []>,
 634                     Requires<[HasV4T]>;
 635
 636 // if (!Pv) Rd=memub(Rs+Rt<<#u2)
 637 let AddedComplexity = 15, isPredicated = 1 in
 638 def LDriub_indexed_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 639                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 640                     "if (!$src1) $dst=memub($src2+$src3<<#0)",
 641                     []>,
 642                     Requires<[HasV4T]>;
 643
 644 // if (!Pv.new) Rd=memub(Rs+Rt<<#u2)
 645 let AddedComplexity = 15, isPredicated = 1 in
 646 def LDriub_indexed_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 647                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 648                     "if (!$src1.new) $dst=memub($src2+$src3<<#0)",
 649                     []>,
 650                     Requires<[HasV4T]>;
 651
 652 // Rd=memb(Rt<<#u2+#U6)
 653
 654 //// Load halfword
 655 // Rd=memh(Rs+Rt<<#u2)
 656 let AddedComplexity = 10, isPredicable = 1 in
 657 def LDrih_indexed_V4 : LDInst<(outs IntRegs:$dst),
 658                     (ins IntRegs:$src1, IntRegs:$src2),
 659                     "$dst=memh($src1+$src2<<#0)",
 660                     [(set (i32 IntRegs:$dst),
 661                           (i32 (sextloadi16 (add (i32 IntRegs:$src1),
 662                                                  (i32 IntRegs:$src2)))))]>,
 663                     Requires<[HasV4T]>;
 664
 665 let AddedComplexity = 10, isPredicable = 1 in
 666 def LDriuh_indexed_V4 : LDInst<(outs IntRegs:$dst),
 667                     (ins IntRegs:$src1, IntRegs:$src2),
 668                     "$dst=memuh($src1+$src2<<#0)",
 669                     [(set (i32 IntRegs:$dst),
 670                           (i32 (zextloadi16 (add (i32 IntRegs:$src1),
 671                                                  (i32 IntRegs:$src2)))))]>,
 672                     Requires<[HasV4T]>;
 673
 674 let AddedComplexity = 10, isPredicable = 1 in
 675 def LDriuh_ae_indexed_V4 : LDInst<(outs IntRegs:$dst),
 676                     (ins IntRegs:$src1, IntRegs:$src2),
 677                     "$dst=memuh($src1+$src2<<#0)",
 678                     [(set (i32 IntRegs:$dst),
 679                           (i32 (extloadi16 (add (i32 IntRegs:$src1),
 680                                                 (i32 IntRegs:$src2)))))]>,
 681                     Requires<[HasV4T]>;
 682
 683 let AddedComplexity = 40, isPredicable = 1 in
 684 def LDriuh_ae_indexed_shl_V4 : LDInst<(outs IntRegs:$dst),
 685                     (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$offset),
 686                     "$dst=memuh($src1+$src2<<#$offset)",
 687                     [(set (i32 IntRegs:$dst),
 688                           (i32 (extloadi16 (add (i32 IntRegs:$src1),
 689                                                 (shl (i32 IntRegs:$src2),
 690                                                      u2ImmPred:$offset)))))]>,
 691                     Requires<[HasV4T]>;
 692
 693 //// Load halfword conditionally.
 694 // if ([!]Pv[.new]) Rd=memh(Rs+Rt<<#u2)
 695 // if (Pv) Rd=memh(Rs+Rt<<#u2)
 696 let AddedComplexity = 15, isPredicated = 1 in
 697 def LDrih_indexed_cPt_V4 : LDInst2<(outs IntRegs:$dst),
 698                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 699                     "if ($src1) $dst=memh($src2+$src3<<#0)",
 700                     []>,
 701                     Requires<[HasV4T]>;
 702
 703 // if (Pv.new) Rd=memh(Rs+Rt<<#u2)
 704 let AddedComplexity = 15, isPredicated = 1 in
 705 def LDrih_indexed_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
 706                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 707                     "if ($src1.new) $dst=memh($src2+$src3<<#0)",
 708                     []>,
 709                     Requires<[HasV4T]>;
 710
 711 // if (!Pv) Rd=memh(Rs+Rt<<#u2)
 712 let AddedComplexity = 15, isPredicated = 1 in
 713 def LDrih_indexed_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 714                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 715                     "if (!$src1) $dst=memh($src2+$src3<<#0)",
 716                     []>,
 717                     Requires<[HasV4T]>;
 718
 719 // if (!Pv.new) Rd=memh(Rs+Rt<<#u2)
 720 let AddedComplexity = 15, isPredicated = 1 in
 721 def LDrih_indexed_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 722                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 723                     "if (!$src1.new) $dst=memh($src2+$src3<<#0)",
 724                     []>,
 725                     Requires<[HasV4T]>;
 726
 727 //// Load unsigned halfword conditionally.
 728 // if ([!]Pv[.new]) Rd=memuh(Rs+Rt<<#u2)
 729 // if (Pv) Rd=memuh(Rs+Rt<<#u2)
 730 let AddedComplexity = 15, isPredicated = 1 in
 731 def LDriuh_indexed_cPt_V4 : LDInst2<(outs IntRegs:$dst),
 732                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 733                     "if ($src1) $dst=memuh($src2+$src3<<#0)",
 734                     []>,
 735                     Requires<[HasV4T]>;
 736
 737 // if (Pv.new) Rd=memuh(Rs+Rt<<#u2)
 738 let AddedComplexity = 15, isPredicated = 1 in
 739 def LDriuh_indexed_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
 740                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 741                     "if ($src1.new) $dst=memuh($src2+$src3<<#0)",
 742                     []>,
 743                     Requires<[HasV4T]>;
 744
 745 // if (!Pv) Rd=memuh(Rs+Rt<<#u2)
 746 let AddedComplexity = 15, isPredicated = 1 in
 747 def LDriuh_indexed_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 748                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 749                     "if (!$src1) $dst=memuh($src2+$src3<<#0)",
 750                     []>,
 751                     Requires<[HasV4T]>;
 752
 753 // if (!Pv.new) Rd=memuh(Rs+Rt<<#u2)
 754 let AddedComplexity = 15, isPredicated = 1 in
 755 def LDriuh_indexed_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 756                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 757                     "if (!$src1.new) $dst=memuh($src2+$src3<<#0)",
 758                     []>,
 759                     Requires<[HasV4T]>;
 760
 761 // Rd=memh(Rt<<#u2+#U6)
 762
 763 //// Load word.
 764 // Load predicate: Fix for bug 5279.
 765 let neverHasSideEffects = 1 in
 766 def LDriw_pred_V4 : LDInst2<(outs PredRegs:$dst),
 767             (ins MEMri:$addr),
 768             "Error; should not emit",
 769             []>,
 770             Requires<[HasV4T]>;
 771
 772 // Rd=memw(Re=#U6)
 773
 774 // Rd=memw(Rs+Rt<<#u2)
 775 let AddedComplexity = 10, isPredicable = 1 in
 776 def LDriw_indexed_V4 : LDInst<(outs IntRegs:$dst),
 777                     (ins IntRegs:$src1, IntRegs:$src2),
 778                     "$dst=memw($src1+$src2<<#0)",
 779                     [(set (i32 IntRegs:$dst),
 780                           (i32 (load (add (i32 IntRegs:$src1),
 781                                           (i32 IntRegs:$src2)))))]>,
 782                     Requires<[HasV4T]>;
 783
 784 //// Load word conditionally.
 785 // if ([!]Pv[.new]) Rd=memw(Rs+Rt<<#u2)
 786 // if (Pv) Rd=memw(Rs+Rt<<#u2)
 787 let AddedComplexity = 15, isPredicated = 1 in
 788 def LDriw_indexed_cPt_V4 : LDInst2<(outs IntRegs:$dst),
 789                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 790                     "if ($src1) $dst=memw($src2+$src3<<#0)",
 791                     []>,
 792                     Requires<[HasV4T]>;
 793
 794 // if (Pv.new) Rd=memh(Rs+Rt<<#u2)
 795 let AddedComplexity = 15, isPredicated = 1 in
 796 def LDriw_indexed_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
 797                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 798                     "if ($src1.new) $dst=memw($src2+$src3<<#0)",
 799                     []>,
 800                     Requires<[HasV4T]>;
 801
 802 // if (!Pv) Rd=memh(Rs+Rt<<#u2)
 803 let AddedComplexity = 15, isPredicated = 1 in
 804 def LDriw_indexed_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 805                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 806                     "if (!$src1) $dst=memw($src2+$src3<<#0)",
 807                     []>,
 808                     Requires<[HasV4T]>;
 809
 810 // if (!Pv.new) Rd=memh(Rs+Rt<<#u2)
 811 let AddedComplexity = 15, isPredicated = 1 in
 812 def LDriw_indexed_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 813                     (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
 814                     "if (!$src1.new) $dst=memw($src2+$src3<<#0)",
 815                     []>,
 816                     Requires<[HasV4T]>;
 817
 818 /// Load from global offset
 819
 820 let isPredicable = 1, neverHasSideEffects = 1 in
 821 def LDrid_GP_V4 : LDInst2<(outs DoubleRegs:$dst),
 822             (ins globaladdress:$global, u16Imm:$offset),
 823             "$dst=memd(#$global+$offset)",
 824             []>,
 825             Requires<[HasV4T]>;
 826
 827 let neverHasSideEffects = 1, isPredicated = 1 in
 828 def LDrid_GP_cPt_V4 : LDInst2<(outs DoubleRegs:$dst),
 829             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 830             "if ($src1) $dst=memd(##$global+$offset)",
 831             []>,
 832             Requires<[HasV4T]>;
 833
 834 let neverHasSideEffects = 1, isPredicated = 1 in
 835 def LDrid_GP_cNotPt_V4 : LDInst2<(outs DoubleRegs:$dst),
 836             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 837             "if (!$src1) $dst=memd(##$global+$offset)",
 838             []>,
 839             Requires<[HasV4T]>;
 840
 841 let neverHasSideEffects = 1, isPredicated = 1 in
 842 def LDrid_GP_cdnPt_V4 : LDInst2<(outs DoubleRegs:$dst),
 843             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 844             "if ($src1.new) $dst=memd(##$global+$offset)",
 845             []>,
 846             Requires<[HasV4T]>;
 847
 848 let neverHasSideEffects = 1, isPredicated = 1 in
 849 def LDrid_GP_cdnNotPt_V4 : LDInst2<(outs DoubleRegs:$dst),
 850             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 851             "if (!$src1.new) $dst=memd(##$global+$offset)",
 852             []>,
 853             Requires<[HasV4T]>;
 854
 855 let isPredicable = 1, neverHasSideEffects = 1 in
 856 def LDrib_GP_V4 : LDInst2<(outs IntRegs:$dst),
 857             (ins globaladdress:$global, u16Imm:$offset),
 858             "$dst=memb(#$global+$offset)",
 859             []>,
 860             Requires<[HasV4T]>;
 861
 862 let neverHasSideEffects = 1, isPredicated = 1 in
 863 def LDrib_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst),
 864             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 865             "if ($src1) $dst=memb(##$global+$offset)",
 866             []>,
 867             Requires<[HasV4T]>;
 868
 869 let neverHasSideEffects = 1, isPredicated = 1 in
 870 def LDrib_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 871             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 872             "if (!$src1) $dst=memb(##$global+$offset)",
 873             []>,
 874             Requires<[HasV4T]>;
 875
 876 let neverHasSideEffects = 1, isPredicated = 1 in
 877 def LDrib_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
 878             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 879             "if ($src1.new) $dst=memb(##$global+$offset)",
 880             []>,
 881             Requires<[HasV4T]>;
 882
 883 let neverHasSideEffects = 1, isPredicated = 1 in
 884 def LDrib_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 885             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 886             "if (!$src1.new) $dst=memb(##$global+$offset)",
 887             []>,
 888             Requires<[HasV4T]>;
 889
 890
 891 let isPredicable = 1, neverHasSideEffects = 1 in
 892 def LDriub_GP_V4 : LDInst2<(outs IntRegs:$dst),
 893             (ins globaladdress:$global, u16Imm:$offset),
 894             "$dst=memub(#$global+$offset)",
 895             []>,
 896             Requires<[HasV4T]>;
 897
 898
 899 let neverHasSideEffects = 1, isPredicated = 1 in
 900 def LDriub_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst),
 901             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 902             "if ($src1) $dst=memub(##$global+$offset)",
 903             []>,
 904             Requires<[HasV4T]>;
 905
 906 let neverHasSideEffects = 1, isPredicated = 1 in
 907 def LDriub_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 908             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 909             "if (!$src1) $dst=memub(##$global+$offset)",
 910             []>,
 911             Requires<[HasV4T]>;
 912
 913 let neverHasSideEffects = 1, isPredicated = 1 in
 914 def LDriub_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
 915             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 916             "if ($src1.new) $dst=memub(##$global+$offset)",
 917             []>,
 918             Requires<[HasV4T]>;
 919
 920 let neverHasSideEffects = 1, isPredicated = 1 in
 921 def LDriub_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 922             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 923             "if (!$src1.new) $dst=memub(##$global+$offset)",
 924             []>,
 925             Requires<[HasV4T]>;
 926
 927
 928 let isPredicable = 1, neverHasSideEffects = 1 in
 929 def LDrih_GP_V4 : LDInst2<(outs IntRegs:$dst),
 930             (ins globaladdress:$global, u16Imm:$offset),
 931             "$dst=memh(#$global+$offset)",
 932             []>,
 933             Requires<[HasV4T]>;
 934
 935
 936 let neverHasSideEffects = 1, isPredicated = 1 in
 937 def LDrih_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst),
 938             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 939             "if ($src1) $dst=memh(##$global+$offset)",
 940             []>,
 941             Requires<[HasV4T]>;
 942
 943 let neverHasSideEffects = 1, isPredicated = 1 in
 944 def LDrih_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 945             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 946             "if (!$src1) $dst=memh(##$global+$offset)",
 947             []>,
 948             Requires<[HasV4T]>;
 949
 950 let neverHasSideEffects = 1, isPredicated = 1 in
 951 def LDrih_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
 952             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 953             "if ($src1.new) $dst=memh(##$global+$offset)",
 954             []>,
 955             Requires<[HasV4T]>;
 956
 957 let neverHasSideEffects = 1, isPredicated = 1 in
 958 def LDrih_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 959             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 960             "if (!$src1.new) $dst=memh(##$global+$offset)",
 961             []>,
 962             Requires<[HasV4T]>;
 963
 964
 965 let isPredicable = 1, neverHasSideEffects = 1 in
 966 def LDriuh_GP_V4 : LDInst2<(outs IntRegs:$dst),
 967             (ins globaladdress:$global, u16Imm:$offset),
 968             "$dst=memuh(#$global+$offset)",
 969             []>,
 970             Requires<[HasV4T]>;
 971
 972 let neverHasSideEffects = 1, isPredicated = 1 in
 973 def LDriuh_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst),
 974             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 975             "if ($src1) $dst=memuh(##$global+$offset)",
 976             []>,
 977             Requires<[HasV4T]>;
 978
 979 let neverHasSideEffects = 1, isPredicated = 1 in
 980 def LDriuh_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 981             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 982             "if (!$src1) $dst=memuh(##$global+$offset)",
 983             []>,
 984             Requires<[HasV4T]>;
 985
 986 let neverHasSideEffects = 1, isPredicated = 1 in
 987 def LDriuh_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
 988             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 989             "if ($src1.new) $dst=memuh(##$global+$offset)",
 990             []>,
 991             Requires<[HasV4T]>;
 992
 993 let neverHasSideEffects = 1, isPredicated = 1 in
 994 def LDriuh_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
 995             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
 996             "if (!$src1.new) $dst=memuh(##$global+$offset)",
 997             []>,
 998             Requires<[HasV4T]>;
 999
1000 let isPredicable = 1, neverHasSideEffects = 1 in
1001 def LDriw_GP_V4 : LDInst2<(outs IntRegs:$dst),
1002             (ins globaladdress:$global, u16Imm:$offset),
1003             "$dst=memw(#$global+$offset)",
1004             []>,
1005             Requires<[HasV4T]>;
1006
1007
1008 let neverHasSideEffects = 1, isPredicated = 1 in
1009 def LDriw_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst),
1010             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
1011             "if ($src1) $dst=memw(##$global+$offset)",
1012             []>,
1013             Requires<[HasV4T]>;
1014
1015 let neverHasSideEffects = 1, isPredicated = 1 in
1016 def LDriw_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1017             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
1018             "if (!$src1) $dst=memw(##$global+$offset)",
1019             []>,
1020             Requires<[HasV4T]>;
1021
1022
1023 let neverHasSideEffects = 1, isPredicated = 1 in
1024 def LDriw_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
1025             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
1026             "if ($src1.new) $dst=memw(##$global+$offset)",
1027             []>,
1028             Requires<[HasV4T]>;
1029
1030 let neverHasSideEffects = 1, isPredicated = 1 in
1031 def LDriw_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1032             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
1033             "if (!$src1.new) $dst=memw(##$global+$offset)",
1034             []>,
1035             Requires<[HasV4T]>;
1036
1037
1038 let isPredicable = 1, neverHasSideEffects = 1, validSubTargets = HasV4SubT in
1039 def LDd_GP_V4 : LDInst2<(outs DoubleRegs:$dst),
1040             (ins globaladdress:$global),
1041             "$dst=memd(#$global)",
1042             []>,
1043             Requires<[HasV4T]>;
1044
1045 // if (Pv) Rtt=memd(##global)
1046 let neverHasSideEffects = 1, isPredicated = 1, isExtended = 1, opExtendable = 2,
1047 validSubTargets = HasV4SubT in {
1048 def LDd_GP_cPt_V4 : LDInst2<(outs DoubleRegs:$dst),
1049             (ins PredRegs:$src1, globaladdress:$global),
1050             "if ($src1) $dst=memd(##$global)",
1051             []>,
1052             Requires<[HasV4T]>;
1053
1054
1055 // if (!Pv) Rtt=memd(##global)
1056 def LDd_GP_cNotPt_V4 : LDInst2<(outs DoubleRegs:$dst),
1057             (ins PredRegs:$src1, globaladdress:$global),
1058             "if (!$src1) $dst=memd(##$global)",
1059             []>,
1060             Requires<[HasV4T]>;
1061
1062 // if (Pv) Rtt=memd(##global)
1063 def LDd_GP_cdnPt_V4 : LDInst2<(outs DoubleRegs:$dst),
1064             (ins PredRegs:$src1, globaladdress:$global),
1065             "if ($src1.new) $dst=memd(##$global)",
1066             []>,
1067             Requires<[HasV4T]>;
1068
1069
1070 // if (!Pv) Rtt=memd(##global)
1071 def LDd_GP_cdnNotPt_V4 : LDInst2<(outs DoubleRegs:$dst),
1072             (ins PredRegs:$src1, globaladdress:$global),
1073             "if (!$src1.new) $dst=memd(##$global)",
1074             []>,
1075             Requires<[HasV4T]>;
1076 }
1077
1078 let isPredicable = 1, neverHasSideEffects = 1, validSubTargets = HasV4SubT in
1079 def LDb_GP_V4 : LDInst2<(outs IntRegs:$dst),
1080             (ins globaladdress:$global),
1081             "$dst=memb(#$global)",
1082             []>,
1083             Requires<[HasV4T]>;
1084
1085 // if (Pv) Rt=memb(##global)
1086 let neverHasSideEffects = 1, isPredicated = 1, isExtended = 1, opExtendable = 2,
1087 validSubTargets = HasV4SubT in {
1088 def LDb_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst),
1089             (ins PredRegs:$src1, globaladdress:$global),
1090             "if ($src1) $dst=memb(##$global)",
1091             []>,
1092             Requires<[HasV4T]>;
1093
1094 // if (!Pv) Rt=memb(##global)
1095 def LDb_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1096             (ins PredRegs:$src1, globaladdress:$global),
1097             "if (!$src1) $dst=memb(##$global)",
1098             []>,
1099             Requires<[HasV4T]>;
1100
1101 // if (Pv) Rt=memb(##global)
1102 def LDb_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
1103             (ins PredRegs:$src1, globaladdress:$global),
1104             "if ($src1.new) $dst=memb(##$global)",
1105             []>,
1106             Requires<[HasV4T]>;
1107
1108 // if (!Pv) Rt=memb(##global)
1109 def LDb_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1110             (ins PredRegs:$src1, globaladdress:$global),
1111             "if (!$src1.new) $dst=memb(##$global)",
1112             []>,
1113             Requires<[HasV4T]>;
1114 }
1115
1116 let isPredicable = 1, neverHasSideEffects = 1, validSubTargets = HasV4SubT in
1117 def LDub_GP_V4 : LDInst2<(outs IntRegs:$dst),
1118             (ins globaladdress:$global),
1119             "$dst=memub(#$global)",
1120             []>,
1121             Requires<[HasV4T]>;
1122
1123 // if (Pv) Rt=memub(##global)
1124 let neverHasSideEffects = 1, isPredicated = 1, isExtended = 1, opExtendable = 2,
1125 validSubTargets = HasV4SubT in {
1126 def LDub_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst),
1127             (ins PredRegs:$src1, globaladdress:$global),
1128             "if ($src1) $dst=memub(##$global)",
1129             []>,
1130             Requires<[HasV4T]>;
1131
1132
1133 // if (!Pv) Rt=memub(##global)
1134 def LDub_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1135             (ins PredRegs:$src1, globaladdress:$global),
1136             "if (!$src1) $dst=memub(##$global)",
1137             []>,
1138             Requires<[HasV4T]>;
1139
1140 // if (Pv) Rt=memub(##global)
1141 def LDub_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
1142             (ins PredRegs:$src1, globaladdress:$global),
1143             "if ($src1.new) $dst=memub(##$global)",
1144             []>,
1145             Requires<[HasV4T]>;
1146
1147
1148 // if (!Pv) Rt=memub(##global)
1149 def LDub_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1150             (ins PredRegs:$src1, globaladdress:$global),
1151             "if (!$src1.new) $dst=memub(##$global)",
1152             []>,
1153             Requires<[HasV4T]>;
1154 }
1155
1156 let isPredicable = 1, neverHasSideEffects = 1, validSubTargets = HasV4SubT in
1157 def LDh_GP_V4 : LDInst2<(outs IntRegs:$dst),
1158             (ins globaladdress:$global),
1159             "$dst=memh(#$global)",
1160             []>,
1161             Requires<[HasV4T]>;
1162
1163 // if (Pv) Rt=memh(##global)
1164 let neverHasSideEffects = 1, isPredicated = 1, isExtended = 1, opExtendable = 2,
1165 validSubTargets = HasV4SubT in {
1166 def LDh_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst),
1167             (ins PredRegs:$src1, globaladdress:$global),
1168             "if ($src1) $dst=memh(##$global)",
1169             []>,
1170             Requires<[HasV4T]>;
1171
1172 // if (!Pv) Rt=memh(##global)
1173 def LDh_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1174             (ins PredRegs:$src1, globaladdress:$global),
1175             "if (!$src1) $dst=memh(##$global)",
1176             []>,
1177             Requires<[HasV4T]>;
1178
1179 // if (Pv) Rt=memh(##global)
1180 def LDh_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
1181             (ins PredRegs:$src1, globaladdress:$global),
1182             "if ($src1.new) $dst=memh(##$global)",
1183             []>,
1184             Requires<[HasV4T]>;
1185
1186 // if (!Pv) Rt=memh(##global)
1187 def LDh_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1188             (ins PredRegs:$src1, globaladdress:$global),
1189             "if (!$src1.new) $dst=memh(##$global)",
1190             []>,
1191             Requires<[HasV4T]>;
1192 }
1193
1194 let isPredicable = 1, neverHasSideEffects = 1, validSubTargets = HasV4SubT in
1195 def LDuh_GP_V4 : LDInst2<(outs IntRegs:$dst),
1196             (ins globaladdress:$global),
1197             "$dst=memuh(#$global)",
1198             []>,
1199             Requires<[HasV4T]>;
1200
1201 // if (Pv) Rt=memuh(##global)
1202 let neverHasSideEffects = 1, isPredicated = 1, isExtended = 1, opExtendable = 2,
1203 validSubTargets = HasV4SubT in {
1204 def LDuh_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst),
1205             (ins PredRegs:$src1, globaladdress:$global),
1206             "if ($src1) $dst=memuh(##$global)",
1207             []>,
1208             Requires<[HasV4T]>;
1209
1210 // if (!Pv) Rt=memuh(##global)
1211 def LDuh_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1212             (ins PredRegs:$src1, globaladdress:$global),
1213             "if (!$src1) $dst=memuh(##$global)",
1214             []>,
1215             Requires<[HasV4T]>;
1216
1217 // if (Pv) Rt=memuh(##global)
1218 def LDuh_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
1219             (ins PredRegs:$src1, globaladdress:$global),
1220             "if ($src1.new) $dst=memuh(##$global)",
1221             []>,
1222             Requires<[HasV4T]>;
1223
1224 // if (!Pv) Rt=memuh(##global)
1225 def LDuh_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1226             (ins PredRegs:$src1, globaladdress:$global),
1227             "if (!$src1.new) $dst=memuh(##$global)",
1228             []>,
1229             Requires<[HasV4T]>;
1230 }
1231
1232 let isPredicable = 1, neverHasSideEffects = 1, validSubTargets = HasV4SubT in
1233 def LDw_GP_V4 : LDInst2<(outs IntRegs:$dst),
1234             (ins globaladdress:$global),
1235             "$dst=memw(#$global)",
1236             []>,
1237             Requires<[HasV4T]>;
1238
1239 // if (Pv) Rt=memw(##global)
1240 let neverHasSideEffects = 1, isPredicated = 1, isExtended = 1, opExtendable = 2,
1241 validSubTargets = HasV4SubT in {
1242 def LDw_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst),
1243             (ins PredRegs:$src1, globaladdress:$global),
1244             "if ($src1) $dst=memw(##$global)",
1245             []>,
1246             Requires<[HasV4T]>;
1247
1248
1249 // if (!Pv) Rt=memw(##global)
1250 def LDw_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1251             (ins PredRegs:$src1, globaladdress:$global),
1252             "if (!$src1) $dst=memw(##$global)",
1253             []>,
1254             Requires<[HasV4T]>;
1255
1256 // if (Pv) Rt=memw(##global)
1257 def LDw_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
1258             (ins PredRegs:$src1, globaladdress:$global),
1259             "if ($src1.new) $dst=memw(##$global)",
1260             []>,
1261             Requires<[HasV4T]>;
1262
1263
1264 // if (!Pv) Rt=memw(##global)
1265 def LDw_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1266             (ins PredRegs:$src1, globaladdress:$global),
1267             "if (!$src1.new) $dst=memw(##$global)",
1268             []>,
1269             Requires<[HasV4T]>;
1270 }
1271
1272
1273 def : Pat <(atomic_load_64 (HexagonCONST32_GP tglobaladdr:$global)),
1274            (i64 (LDd_GP_V4 tglobaladdr:$global))>,
1275             Requires<[HasV4T]>;
1276
1277 def : Pat <(atomic_load_32 (HexagonCONST32_GP tglobaladdr:$global)),
1278            (i32 (LDw_GP_V4 tglobaladdr:$global))>,
1279             Requires<[HasV4T]>;
1280
1281 def : Pat <(atomic_load_16 (HexagonCONST32_GP tglobaladdr:$global)),
1282            (i32 (LDuh_GP_V4 tglobaladdr:$global))>,
1283             Requires<[HasV4T]>;
1284
1285 def : Pat <(atomic_load_8 (HexagonCONST32_GP tglobaladdr:$global)),
1286            (i32 (LDub_GP_V4 tglobaladdr:$global))>,
1287             Requires<[HasV4T]>;
1288
1289 // Map from load(globaladdress) -> memw(#foo + 0)
1290 let AddedComplexity = 100 in
1291 def : Pat <(i64 (load (HexagonCONST32_GP tglobaladdr:$global))),
1292            (i64 (LDd_GP_V4 tglobaladdr:$global))>,
1293             Requires<[HasV4T]>;
1294
1295 // Map from Pd = load(globaladdress) -> Rd = memb(globaladdress), Pd = Rd
1296 let AddedComplexity = 100 in
1297 def : Pat <(i1 (load (HexagonCONST32_GP tglobaladdr:$global))),
1298            (i1 (TFR_PdRs (i32 (LDb_GP_V4 tglobaladdr:$global))))>,
1299            Requires<[HasV4T]>;
1300
1301 // When the Interprocedural Global Variable optimizer realizes that a certain
1302 // global variable takes only two constant values, it shrinks the global to
1303 // a boolean. Catch those loads here in the following 3 patterns.
1304 let AddedComplexity = 100 in
1305 def : Pat <(i32 (extloadi1 (HexagonCONST32_GP tglobaladdr:$global))),
1306            (i32 (LDb_GP_V4 tglobaladdr:$global))>,
1307             Requires<[HasV4T]>;
1308
1309 let AddedComplexity = 100 in
1310 def : Pat <(i32 (sextloadi1 (HexagonCONST32_GP tglobaladdr:$global))),
1311            (i32 (LDb_GP_V4 tglobaladdr:$global))>,
1312             Requires<[HasV4T]>;
1313
1314 // Map from load(globaladdress) -> memb(#foo)
1315 let AddedComplexity = 100 in
1316 def : Pat <(i32 (extloadi8 (HexagonCONST32_GP tglobaladdr:$global))),
1317            (i32 (LDb_GP_V4 tglobaladdr:$global))>,
1318             Requires<[HasV4T]>;
1319
1320 // Map from load(globaladdress) -> memb(#foo)
1321 let AddedComplexity = 100 in
1322 def : Pat <(i32 (sextloadi8 (HexagonCONST32_GP tglobaladdr:$global))),
1323            (i32 (LDb_GP_V4 tglobaladdr:$global))>,
1324             Requires<[HasV4T]>;
1325
1326 let AddedComplexity = 100 in
1327 def : Pat <(i32 (zextloadi1 (HexagonCONST32_GP tglobaladdr:$global))),
1328            (i32 (LDub_GP_V4 tglobaladdr:$global))>,
1329             Requires<[HasV4T]>;
1330
1331 // Map from load(globaladdress) -> memub(#foo)
1332 let AddedComplexity = 100 in
1333 def : Pat <(i32 (zextloadi8 (HexagonCONST32_GP tglobaladdr:$global))),
1334            (i32 (LDub_GP_V4 tglobaladdr:$global))>,
1335             Requires<[HasV4T]>;
1336
1337 // Map from load(globaladdress) -> memh(#foo)
1338 let AddedComplexity = 100 in
1339 def : Pat <(i32 (extloadi16 (HexagonCONST32_GP tglobaladdr:$global))),
1340            (i32 (LDh_GP_V4 tglobaladdr:$global))>,
1341             Requires<[HasV4T]>;
1342
1343 // Map from load(globaladdress) -> memh(#foo)
1344 let AddedComplexity = 100 in
1345 def : Pat <(i32 (sextloadi16 (HexagonCONST32_GP tglobaladdr:$global))),
1346            (i32 (LDh_GP_V4 tglobaladdr:$global))>,
1347             Requires<[HasV4T]>;
1348
1349 // Map from load(globaladdress) -> memuh(#foo)
1350 let AddedComplexity = 100 in
1351 def : Pat <(i32 (zextloadi16 (HexagonCONST32_GP tglobaladdr:$global))),
1352            (i32 (LDuh_GP_V4 tglobaladdr:$global))>,
1353             Requires<[HasV4T]>;
1354
1355 // Map from load(globaladdress) -> memw(#foo)
1356 let AddedComplexity = 100 in
1357 def : Pat <(i32 (load (HexagonCONST32_GP tglobaladdr:$global))),
1358            (i32 (LDw_GP_V4 tglobaladdr:$global))>,
1359             Requires<[HasV4T]>;
1360
1361 def : Pat <(atomic_load_64 (add (HexagonCONST32_GP tglobaladdr:$global),
1362                                 u16ImmPred:$offset)),
1363            (i64 (LDrid_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
1364            Requires<[HasV4T]>;
1365
1366 def : Pat <(atomic_load_32 (add (HexagonCONST32_GP tglobaladdr:$global),
1367                                 u16ImmPred:$offset)),
1368            (i32 (LDriw_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
1369             Requires<[HasV4T]>;
1370
1371 def : Pat <(atomic_load_16 (add (HexagonCONST32_GP tglobaladdr:$global),
1372                                 u16ImmPred:$offset)),
1373            (i32 (LDriuh_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
1374             Requires<[HasV4T]>;
1375
1376 def : Pat <(atomic_load_8 (add (HexagonCONST32_GP tglobaladdr:$global),
1377                                u16ImmPred:$offset)),
1378            (i32 (LDriub_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
1379            Requires<[HasV4T]>;
1380
1381 // Map from load(globaladdress + x) -> memd(#foo + x)
1382 let AddedComplexity = 100 in
1383 def : Pat <(i64 (load (add (HexagonCONST32_GP tglobaladdr:$global),
1384                            u16ImmPred:$offset))),
1385            (i64 (LDrid_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
1386            Requires<[HasV4T]>;
1387
1388 // Map from load(globaladdress + x) -> memb(#foo + x)
1389 let AddedComplexity = 100 in
1390 def : Pat <(i32 (extloadi8 (add (HexagonCONST32_GP tglobaladdr:$global),
1391                            u16ImmPred:$offset))),
1392            (i32 (LDrib_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
1393            Requires<[HasV4T]>;
1394
1395 // Map from load(globaladdress + x) -> memb(#foo + x)
1396 let AddedComplexity = 100 in
1397 def : Pat <(i32 (sextloadi8 (add (HexagonCONST32_GP tglobaladdr:$global),
1398                             u16ImmPred:$offset))),
1399            (i32 (LDrib_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
1400            Requires<[HasV4T]>;
1401
1402 // Map from load(globaladdress + x) -> memub(#foo + x)
1403 let AddedComplexity = 100 in
1404 def : Pat <(i32 (zextloadi8 (add (HexagonCONST32_GP tglobaladdr:$global),
1405                             u16ImmPred:$offset))),
1406            (i32 (LDriub_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
1407            Requires<[HasV4T]>;
1408
1409 // Map from load(globaladdress + x) -> memuh(#foo + x)
1410 let AddedComplexity = 100 in
1411 def : Pat <(i32 (extloadi16 (add (HexagonCONST32_GP tglobaladdr:$global),
1412                             u16ImmPred:$offset))),
1413            (i32 (LDrih_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
1414             Requires<[HasV4T]>;
1415
1416 // Map from load(globaladdress + x) -> memh(#foo + x)
1417 let AddedComplexity = 100 in
1418 def : Pat <(i32 (sextloadi16 (add (HexagonCONST32_GP tglobaladdr:$global),
1419                              u16ImmPred:$offset))),
1420            (i32 (LDrih_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
1421            Requires<[HasV4T]>;
1422
1423
1424 // Map from load(globaladdress + x) -> memuh(#foo + x)
1425 let AddedComplexity = 100 in
1426 def : Pat <(i32 (zextloadi16 (add (HexagonCONST32_GP tglobaladdr:$global),
1427                              u16ImmPred:$offset))),
1428            (i32 (LDriuh_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
1429             Requires<[HasV4T]>;
1430
1431 // Map from load(globaladdress + x) -> memw(#foo + x)
1432 let AddedComplexity = 100 in
1433 def : Pat <(i32 (load (add (HexagonCONST32_GP tglobaladdr:$global),
1434                       u16ImmPred:$offset))),
1435            (i32 (LDriw_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
1436             Requires<[HasV4T]>;
1437
1438
1439 //===----------------------------------------------------------------------===//
1440 // LD -
1441 //===----------------------------------------------------------------------===//
1442
1443 //===----------------------------------------------------------------------===//
1444 // ST +
1445 //===----------------------------------------------------------------------===//
1446 ///
1447 /// Assumptions::: ****** DO NOT IGNORE ********
1448 /// 1. Make sure that in post increment store, the zero'th operand is always the
1449 ///    post increment operand.
1450 /// 2. Make sure that the store value operand(Rt/Rtt) in a store is always the
1451 ///    last operand.
1452 ///
1453
1454 // memd(Re=#U)=Rtt
1455 let isExtended = 1, opExtendable = 2, validSubTargets = HasV4SubT in {
1456 def STrid_abs_setimm_V4 : STInst2<(outs IntRegs:$dst1),
1457             (ins DoubleRegs:$src1, u0AlwaysExt:$src2),
1458             "memd($dst1=##$src2) = $src1",
1459             []>,
1460             Requires<[HasV4T]>;
1461
1462 // memb(Re=#U)=Rs
1463 def STrib_abs_setimm_V4 : STInst2<(outs IntRegs:$dst1),
1464             (ins IntRegs:$src1, u0AlwaysExt:$src2),
1465             "memb($dst1=##$src2) = $src1",
1466             []>,
1467             Requires<[HasV4T]>;
1468
1469 // memh(Re=#U)=Rs
1470 def STrih_abs_setimm_V4 : STInst2<(outs IntRegs:$dst1),
1471             (ins IntRegs:$src1, u0AlwaysExt:$src2),
1472             "memh($dst1=##$src2) = $src1",
1473             []>,
1474             Requires<[HasV4T]>;
1475
1476 // memw(Re=#U)=Rs
1477 def STriw_abs_setimm_V4 : STInst2<(outs IntRegs:$dst1),
1478             (ins IntRegs:$src1, u0AlwaysExt:$src2),
1479             "memw($dst1=##$src2) = $src1",
1480             []>,
1481             Requires<[HasV4T]>;
1482 }
1483
1484 // memd(Re=#U)=Rtt
1485 let isExtended = 1, opExtendable = 2, validSubTargets = HasV4SubT in {
1486 def STrid_abs_set_V4 : STInst2<(outs IntRegs:$dst1),
1487             (ins DoubleRegs:$src1, globaladdressExt:$src2),
1488             "memd($dst1=##$src2) = $src1",
1489             []>,
1490             Requires<[HasV4T]>;
1491
1492 // memb(Re=#U)=Rs
1493 def STrib_abs_set_V4 : STInst2<(outs IntRegs:$dst1),
1494             (ins IntRegs:$src1, globaladdressExt:$src2),
1495             "memb($dst1=##$src2) = $src1",
1496             []>,
1497             Requires<[HasV4T]>;
1498
1499 // memh(Re=#U)=Rs
1500 def STrih_abs_set_V4 : STInst2<(outs IntRegs:$dst1),
1501             (ins IntRegs:$src1, globaladdressExt:$src2),
1502             "memh($dst1=##$src2) = $src1",
1503             []>,
1504             Requires<[HasV4T]>;
1505
1506 // memw(Re=#U)=Rs
1507 def STriw_abs_set_V4 : STInst2<(outs IntRegs:$dst1),
1508             (ins IntRegs:$src1, globaladdressExt:$src2),
1509             "memw($dst1=##$src2) = $src1",
1510             []>,
1511             Requires<[HasV4T]>;
1512 }
1513
1514 // multiclass for store instructions with base + register offset addressing
1515 // mode
1516 multiclass ST_Idxd_shl_Pbase<string mnemonic, RegisterClass RC, bit isNot,
1517                              bit isPredNew> {
1518   let PNewValue = !if(isPredNew, "new", "") in
1519   def NAME : STInst2<(outs),
1520             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
1521                  RC:$src5),
1522             !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1523             ") ")#mnemonic#"($src2+$src3<<#$src4) = $src5",
1524             []>,
1525             Requires<[HasV4T]>;
1526 }
1527
1528 multiclass ST_Idxd_shl_Pred<string mnemonic, RegisterClass RC, bit PredNot> {
1529   let PredSense = !if(PredNot, "false", "true") in {
1530     defm _c#NAME : ST_Idxd_shl_Pbase<mnemonic, RC, PredNot, 0>;
1531     // Predicate new
1532     defm _cdn#NAME : ST_Idxd_shl_Pbase<mnemonic, RC, PredNot, 1>;
1533   }
1534 }
1535
1536 let isNVStorable = 1 in
1537 multiclass ST_Idxd_shl<string mnemonic, string CextOp, RegisterClass RC> {
1538   let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed_shl in {
1539     let isPredicable = 1 in
1540     def NAME#_V4 : STInst2<(outs),
1541             (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$src3, RC:$src4),
1542             mnemonic#"($src1+$src2<<#$src3) = $src4",
1543             []>,
1544             Requires<[HasV4T]>;
1545
1546     let isPredicated = 1 in {
1547       defm Pt_V4 : ST_Idxd_shl_Pred<mnemonic, RC, 0 >;
1548       defm NotPt_V4 : ST_Idxd_shl_Pred<mnemonic, RC, 1>;
1549     }
1550   }
1551 }
1552
1553 // multiclass for new-value store instructions with base + register offset
1554 // addressing mode.
1555 multiclass ST_Idxd_shl_Pbase_nv<string mnemonic, RegisterClass RC, bit isNot,
1556                              bit isPredNew> {
1557   let PNewValue = !if(isPredNew, "new", "") in
1558   def NAME#_nv_V4 : NVInst_V4<(outs),
1559             (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
1560                  RC:$src5),
1561             !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1562             ") ")#mnemonic#"($src2+$src3<<#$src4) = $src5.new",
1563             []>,
1564             Requires<[HasV4T]>;
1565 }
1566
1567 multiclass ST_Idxd_shl_Pred_nv<string mnemonic, RegisterClass RC, bit PredNot> {
1568   let PredSense = !if(PredNot, "false", "true") in {
1569     defm _c#NAME : ST_Idxd_shl_Pbase_nv<mnemonic, RC, PredNot, 0>;
1570     // Predicate new
1571     defm _cdn#NAME : ST_Idxd_shl_Pbase_nv<mnemonic, RC, PredNot, 1>;
1572   }
1573 }
1574
1575 let mayStore = 1, isNVStore = 1 in
1576 multiclass ST_Idxd_shl_nv<string mnemonic, string CextOp, RegisterClass RC> {
1577   let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed_shl in {
1578     let isPredicable = 1 in
1579     def NAME#_nv_V4 : NVInst_V4<(outs),
1580             (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$src3, RC:$src4),
1581             mnemonic#"($src1+$src2<<#$src3) = $src4.new",
1582             []>,
1583             Requires<[HasV4T]>;
1584
1585     let isPredicated = 1 in {
1586       defm Pt : ST_Idxd_shl_Pred_nv<mnemonic, RC, 0 >;
1587       defm NotPt : ST_Idxd_shl_Pred_nv<mnemonic, RC, 1>;
1588     }
1589   }
1590 }
1591
1592 let addrMode = BaseRegOffset, neverHasSideEffects = 1,
1593 validSubTargets = HasV4SubT in {
1594   defm STrib_indexed_shl: ST_Idxd_shl<"memb", "STrib", IntRegs>,
1595                           ST_Idxd_shl_nv<"memb", "STrib", IntRegs>, AddrModeRel;
1596
1597   defm STrih_indexed_shl: ST_Idxd_shl<"memh", "STrih", IntRegs>,
1598                           ST_Idxd_shl_nv<"memh", "STrih", IntRegs>, AddrModeRel;
1599
1600   defm STriw_indexed_shl: ST_Idxd_shl<"memw", "STriw", IntRegs>,
1601                           ST_Idxd_shl_nv<"memw", "STriw", IntRegs>, AddrModeRel;
1602
1603   let isNVStorable = 0 in
1604   defm STrid_indexed_shl: ST_Idxd_shl<"memd", "STrid", DoubleRegs>, AddrModeRel;
1605 }
1606
1607 let Predicates = [HasV4T], AddedComplexity = 10 in {
1608 def : Pat<(truncstorei8 (i32 IntRegs:$src4),
1609                        (add IntRegs:$src1, (shl IntRegs:$src2,
1610                                                 u2ImmPred:$src3))),
1611           (STrib_indexed_shl_V4 IntRegs:$src1, IntRegs:$src2,
1612                                 u2ImmPred:$src3, IntRegs:$src4)>;
1613
1614 def : Pat<(truncstorei16 (i32 IntRegs:$src4),
1615                         (add IntRegs:$src1, (shl IntRegs:$src2,
1616                                                  u2ImmPred:$src3))),
1617           (STrih_indexed_shl_V4 IntRegs:$src1, IntRegs:$src2,
1618                                 u2ImmPred:$src3, IntRegs:$src4)>;
1619
1620 def : Pat<(store (i32 IntRegs:$src4),
1621                  (add IntRegs:$src1, (shl IntRegs:$src2, u2ImmPred:$src3))),
1622           (STriw_indexed_shl_V4 IntRegs:$src1, IntRegs:$src2,
1623                                 u2ImmPred:$src3, IntRegs:$src4)>;
1624
1625 def : Pat<(store (i64 DoubleRegs:$src4),
1626                 (add IntRegs:$src1, (shl IntRegs:$src2, u2ImmPred:$src3))),
1627           (STrid_indexed_shl_V4 IntRegs:$src1, IntRegs:$src2,
1628                                 u2ImmPred:$src3, DoubleRegs:$src4)>;
1629 }
1630
1631 // memd(Ru<<#u2+#U6)=Rtt
1632 let isExtended = 1, opExtendable = 2, AddedComplexity = 10,
1633 validSubTargets = HasV4SubT in
1634 def STrid_shl_V4 : STInst<(outs),
1635             (ins IntRegs:$src1, u2Imm:$src2, u0AlwaysExt:$src3, DoubleRegs:$src4),
1636             "memd($src1<<#$src2+#$src3) = $src4",
1637             [(store (i64 DoubleRegs:$src4),
1638                     (add (shl (i32 IntRegs:$src1), u2ImmPred:$src2),
1639                          u0AlwaysExtPred:$src3))]>,
1640             Requires<[HasV4T]>;
1641
1642 // memd(Rx++#s4:3)=Rtt
1643 // memd(Rx++#s4:3:circ(Mu))=Rtt
1644 // memd(Rx++I:circ(Mu))=Rtt
1645 // memd(Rx++Mu)=Rtt
1646 // memd(Rx++Mu:brev)=Rtt
1647 // memd(gp+#u16:3)=Rtt
1648
1649 // Store doubleword conditionally.
1650 // if ([!]Pv[.new]) memd(#u6)=Rtt
1651 // TODO: needs to be implemented.
1652
1653 //===----------------------------------------------------------------------===//
1654 // multiclass for store instructions with base + immediate offset
1655 // addressing mode and immediate stored value.
1656 // mem[bhw](Rx++#s4:3)=#s8
1657 // if ([!]Pv[.new]) mem[bhw](Rx++#s4:3)=#s6
1658 //===----------------------------------------------------------------------===//
1659 multiclass ST_Imm_Pbase<string mnemonic, Operand OffsetOp, bit isNot,
1660                         bit isPredNew> {
1661   let PNewValue = !if(isPredNew, "new", "") in
1662   def NAME : STInst2<(outs),
1663             (ins PredRegs:$src1, IntRegs:$src2, OffsetOp:$src3, s6Ext:$src4),
1664             !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1665             ") ")#mnemonic#"($src2+#$src3) = #$src4",
1666             []>,
1667             Requires<[HasV4T]>;
1668 }
1669
1670 multiclass ST_Imm_Pred<string mnemonic, Operand OffsetOp, bit PredNot> {
1671   let PredSense = !if(PredNot, "false", "true") in {
1672     defm _c#NAME : ST_Imm_Pbase<mnemonic, OffsetOp, PredNot, 0>;
1673     // Predicate new
1674     defm _cdn#NAME : ST_Imm_Pbase<mnemonic, OffsetOp, PredNot, 1>;
1675   }
1676 }
1677
1678 let isExtendable = 1, isExtentSigned = 1, neverHasSideEffects = 1 in
1679 multiclass ST_Imm<string mnemonic, string CextOp, Operand OffsetOp> {
1680   let CextOpcode = CextOp, BaseOpcode = CextOp#_imm in {
1681     let opExtendable = 2, opExtentBits = 8, isPredicable = 1 in
1682     def NAME#_V4 : STInst2<(outs),
1683             (ins IntRegs:$src1, OffsetOp:$src2, s8Ext:$src3),
1684             mnemonic#"($src1+#$src2) = #$src3",
1685             []>,
1686             Requires<[HasV4T]>;
1687
1688     let opExtendable = 3, opExtentBits = 6, isPredicated = 1 in {
1689       defm Pt_V4 : ST_Imm_Pred<mnemonic, OffsetOp, 0>;
1690       defm NotPt_V4 : ST_Imm_Pred<mnemonic, OffsetOp, 1 >;
1691     }
1692   }
1693 }
1694
1695 let addrMode = BaseImmOffset, InputType = "imm",
1696     validSubTargets = HasV4SubT in {
1697   defm STrib_imm : ST_Imm<"memb", "STrib", u6_0Imm>, ImmRegRel, PredNewRel;
1698   defm STrih_imm : ST_Imm<"memh", "STrih", u6_1Imm>, ImmRegRel, PredNewRel;
1699   defm STriw_imm : ST_Imm<"memw", "STriw", u6_2Imm>, ImmRegRel, PredNewRel;
1700 }
1701
1702 let Predicates = [HasV4T], AddedComplexity = 10 in {
1703 def: Pat<(truncstorei8 s8ExtPred:$src3, (add IntRegs:$src1, u6_0ImmPred:$src2)),
1704             (STrib_imm_V4 IntRegs:$src1, u6_0ImmPred:$src2, s8ExtPred:$src3)>;
1705
1706 def: Pat<(truncstorei16 s8ExtPred:$src3, (add IntRegs:$src1,
1707                                               u6_1ImmPred:$src2)),
1708             (STrih_imm_V4 IntRegs:$src1, u6_1ImmPred:$src2, s8ExtPred:$src3)>;
1709
1710 def: Pat<(store s8ExtPred:$src3, (add IntRegs:$src1, u6_2ImmPred:$src2)),
1711             (STriw_imm_V4 IntRegs:$src1, u6_2ImmPred:$src2, s8ExtPred:$src3)>;
1712 }
1713
1714 let AddedComplexity = 6 in
1715 def : Pat <(truncstorei8 s8ExtPred:$src2, (i32 IntRegs:$src1)),
1716            (STrib_imm_V4 IntRegs:$src1, 0, s8ExtPred:$src2)>,
1717            Requires<[HasV4T]>;
1718
1719 // memb(Ru<<#u2+#U6)=Rt
1720 let isExtended = 1, opExtendable = 2, AddedComplexity = 10, isNVStorable = 1,
1721 validSubTargets = HasV4SubT in
1722 def STrib_shl_V4 : STInst<(outs),
1723             (ins IntRegs:$src1, u2Imm:$src2, u0AlwaysExt:$src3, IntRegs:$src4),
1724             "memb($src1<<#$src2+#$src3) = $src4",
1725             [(truncstorei8 (i32 IntRegs:$src4),
1726                            (add (shl (i32 IntRegs:$src1), u2ImmPred:$src2),
1727                                 u0AlwaysExtPred:$src3))]>,
1728             Requires<[HasV4T]>;
1729
1730 // memb(Rx++#s4:0:circ(Mu))=Rt
1731 // memb(Rx++I:circ(Mu))=Rt
1732 // memb(Rx++Mu)=Rt
1733 // memb(Rx++Mu:brev)=Rt
1734 // memb(gp+#u16:0)=Rt
1735
1736
1737 // Store halfword.
1738 // TODO: needs to be implemented
1739 // memh(Re=#U6)=Rt.H
1740 // memh(Rs+#s11:1)=Rt.H
1741 let AddedComplexity = 6 in
1742 def : Pat <(truncstorei16 s8ExtPred:$src2, (i32 IntRegs:$src1)),
1743            (STrih_imm_V4 IntRegs:$src1, 0, s8ExtPred:$src2)>,
1744            Requires<[HasV4T]>;
1745
1746 // memh(Rs+Ru<<#u2)=Rt.H
1747 // TODO: needs to be implemented.
1748
1749 // memh(Ru<<#u2+#U6)=Rt.H
1750 // memh(Ru<<#u2+#U6)=Rt
1751 let isExtended = 1, opExtendable = 2, AddedComplexity = 10, isNVStorable = 1,
1752 validSubTargets = HasV4SubT in
1753 def STrih_shl_V4 : STInst<(outs),
1754             (ins IntRegs:$src1, u2Imm:$src2, u0AlwaysExt:$src3, IntRegs:$src4),
1755             "memh($src1<<#$src2+#$src3) = $src4",
1756             [(truncstorei16 (i32 IntRegs:$src4),
1757                             (add (shl (i32 IntRegs:$src1), u2ImmPred:$src2),
1758                                  u0AlwaysExtPred:$src3))]>,
1759             Requires<[HasV4T]>;
1760
1761 // memh(Rx++#s4:1:circ(Mu))=Rt.H
1762 // memh(Rx++#s4:1:circ(Mu))=Rt
1763 // memh(Rx++I:circ(Mu))=Rt.H
1764 // memh(Rx++I:circ(Mu))=Rt
1765 // memh(Rx++Mu)=Rt.H
1766 // memh(Rx++Mu)=Rt
1767 // memh(Rx++Mu:brev)=Rt.H
1768 // memh(Rx++Mu:brev)=Rt
1769 // memh(gp+#u16:1)=Rt
1770 // if ([!]Pv[.new]) memh(#u6)=Rt.H
1771 // if ([!]Pv[.new]) memh(#u6)=Rt
1772
1773
1774 // if ([!]Pv[.new]) memh(Rs+#u6:1)=Rt.H
1775 // TODO: needs to be implemented.
1776
1777 // if ([!]Pv[.new]) memh(Rx++#s4:1)=Rt.H
1778 // TODO: Needs to be implemented.
1779
1780 // Store word.
1781 // memw(Re=#U6)=Rt
1782 // TODO: Needs to be implemented.
1783
1784 // Store predicate:
1785 let neverHasSideEffects = 1 in
1786 def STriw_pred_V4 : STInst2<(outs),
1787             (ins MEMri:$addr, PredRegs:$src1),
1788             "Error; should not emit",
1789             []>,
1790             Requires<[HasV4T]>;
1791
1792 let AddedComplexity = 6 in
1793 def : Pat <(store s8ExtPred:$src2, (i32 IntRegs:$src1)),
1794            (STriw_imm_V4 IntRegs:$src1, 0, s8ExtPred:$src2)>,
1795            Requires<[HasV4T]>;
1796
1797 // memw(Ru<<#u2+#U6)=Rt
1798 let isExtended = 1, opExtendable = 2, AddedComplexity = 10, isNVStorable = 1,
1799 validSubTargets = HasV4SubT in
1800 def STriw_shl_V4 : STInst<(outs),
1801             (ins IntRegs:$src1, u2Imm:$src2, u0AlwaysExt:$src3, IntRegs:$src4),
1802             "memw($src1<<#$src2+#$src3) = $src4",
1803             [(store (i32 IntRegs:$src4),
1804                     (add (shl (i32 IntRegs:$src1), u2ImmPred:$src2),
1805                               u0AlwaysExtPred:$src3))]>,
1806             Requires<[HasV4T]>;
1807
1808 // memw(Rx++#s4:2)=Rt
1809 // memw(Rx++#s4:2:circ(Mu))=Rt
1810 // memw(Rx++I:circ(Mu))=Rt
1811 // memw(Rx++Mu)=Rt
1812 // memw(Rx++Mu:brev)=Rt
1813 // memw(gp+#u16:2)=Rt
1814
1815 /// store to global address
1816
1817 let isPredicable = 1, neverHasSideEffects = 1 in
1818 def STrid_GP_V4 : STInst2<(outs),
1819             (ins globaladdress:$global, u16Imm:$offset, DoubleRegs:$src),
1820             "memd(#$global+$offset) = $src",
1821             []>,
1822             Requires<[HasV4T]>;
1823
1824 let neverHasSideEffects = 1, isPredicated = 1 in
1825 def STrid_GP_cPt_V4 : STInst2<(outs),
1826             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
1827                                                         DoubleRegs:$src2),
1828             "if ($src1) memd(##$global+$offset) = $src2",
1829             []>,
1830             Requires<[HasV4T]>;
1831
1832 let neverHasSideEffects = 1, isPredicated = 1 in
1833 def STrid_GP_cNotPt_V4 : STInst2<(outs),
1834             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
1835                                                         DoubleRegs:$src2),
1836             "if (!$src1) memd(##$global+$offset) = $src2",
1837             []>,
1838             Requires<[HasV4T]>;
1839
1840 let neverHasSideEffects = 1, isPredicated = 1 in
1841 def STrid_GP_cdnPt_V4 : STInst2<(outs),
1842             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
1843                                                         DoubleRegs:$src2),
1844             "if ($src1.new) memd(##$global+$offset) = $src2",
1845             []>,
1846             Requires<[HasV4T]>;
1847
1848 let neverHasSideEffects = 1, isPredicated = 1 in
1849 def STrid_GP_cdnNotPt_V4 : STInst2<(outs),
1850             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
1851                                                         DoubleRegs:$src2),
1852             "if (!$src1.new) memd(##$global+$offset) = $src2",
1853             []>,
1854             Requires<[HasV4T]>;
1855
1856 let isPredicable = 1, neverHasSideEffects = 1 in
1857 def STrib_GP_V4 : STInst2<(outs),
1858             (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),
1859             "memb(#$global+$offset) = $src",
1860             []>,
1861             Requires<[HasV4T]>;
1862
1863 let neverHasSideEffects = 1, isPredicated = 1 in
1864 def STrib_GP_cPt_V4 : STInst2<(outs),
1865             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
1866                                                         IntRegs:$src2),
1867             "if ($src1) memb(##$global+$offset) = $src2",
1868             []>,
1869             Requires<[HasV4T]>;
1870
1871 let neverHasSideEffects = 1, isPredicated = 1 in
1872 def STrib_GP_cNotPt_V4 : STInst2<(outs),
1873             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
1874                                                         IntRegs:$src2),
1875             "if (!$src1) memb(##$global+$offset) = $src2",
1876             []>,
1877             Requires<[HasV4T]>;
1878
1879 let neverHasSideEffects = 1, isPredicated = 1 in
1880 def STrib_GP_cdnPt_V4 : STInst2<(outs),
1881             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
1882                                                         IntRegs:$src2),
1883             "if ($src1.new) memb(##$global+$offset) = $src2",
1884             []>,
1885             Requires<[HasV4T]>;
1886
1887 let neverHasSideEffects = 1, isPredicated = 1 in
1888 def STrib_GP_cdnNotPt_V4 : STInst2<(outs),
1889             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
1890                                                         IntRegs:$src2),
1891             "if (!$src1.new) memb(##$global+$offset) = $src2",
1892             []>,
1893             Requires<[HasV4T]>;
1894
1895 let isPredicable = 1, neverHasSideEffects = 1 in
1896 def STrih_GP_V4 : STInst2<(outs),
1897             (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),
1898             "memh(#$global+$offset) = $src",
1899             []>,
1900             Requires<[HasV4T]>;
1901
1902 let neverHasSideEffects = 1, isPredicated = 1 in
1903 def STrih_GP_cPt_V4 : STInst2<(outs),
1904             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
1905                                                         IntRegs:$src2),
1906             "if ($src1) memh(##$global+$offset) = $src2",
1907             []>,
1908             Requires<[HasV4T]>;
1909
1910 let neverHasSideEffects = 1, isPredicated = 1 in
1911 def STrih_GP_cNotPt_V4 : STInst2<(outs),
1912             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
1913                                                         IntRegs:$src2),
1914             "if (!$src1) memh(##$global+$offset) = $src2",
1915             []>,
1916             Requires<[HasV4T]>;
1917
1918 let neverHasSideEffects = 1, isPredicated = 1 in
1919 def STrih_GP_cdnPt_V4 : STInst2<(outs),
1920             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
1921                                                         IntRegs:$src2),
1922             "if ($src1.new) memh(##$global+$offset) = $src2",
1923             []>,
1924             Requires<[HasV4T]>;
1925
1926 let neverHasSideEffects = 1, isPredicated = 1 in
1927 def STrih_GP_cdnNotPt_V4 : STInst2<(outs),
1928             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
1929                                                         IntRegs:$src2),
1930             "if (!$src1.new) memh(##$global+$offset) = $src2",
1931             []>,
1932             Requires<[HasV4T]>;
1933
1934 let isPredicable = 1, neverHasSideEffects = 1 in
1935 def STriw_GP_V4 : STInst2<(outs),
1936             (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),
1937             "memw(#$global+$offset) = $src",
1938             []>,
1939             Requires<[HasV4T]>;
1940
1941 let neverHasSideEffects = 1, isPredicated = 1 in
1942 def STriw_GP_cPt_V4 : STInst2<(outs),
1943             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
1944                                                         IntRegs:$src2),
1945             "if ($src1) memw(##$global+$offset) = $src2",
1946             []>,
1947             Requires<[HasV4T]>;
1948
1949 let neverHasSideEffects = 1, isPredicated = 1 in
1950 def STriw_GP_cNotPt_V4 : STInst2<(outs),
1951             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
1952                                                         IntRegs:$src2),
1953             "if (!$src1) memw(##$global+$offset) = $src2",
1954             []>,
1955             Requires<[HasV4T]>;
1956
1957 let neverHasSideEffects = 1, isPredicated = 1 in
1958 def STriw_GP_cdnPt_V4 : STInst2<(outs),
1959             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
1960                                                         IntRegs:$src2),
1961             "if ($src1.new) memw(##$global+$offset) = $src2",
1962             []>,
1963             Requires<[HasV4T]>;
1964
1965 let neverHasSideEffects = 1, isPredicated = 1 in
1966 def STriw_GP_cdnNotPt_V4 : STInst2<(outs),
1967             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
1968                                                         IntRegs:$src2),
1969             "if (!$src1.new) memw(##$global+$offset) = $src2",
1970             []>,
1971             Requires<[HasV4T]>;
1972
1973 // memd(#global)=Rtt
1974 let isPredicable = 1, neverHasSideEffects = 1 in
1975 def STd_GP_V4 : STInst2<(outs),
1976             (ins globaladdress:$global, DoubleRegs:$src),
1977             "memd(#$global) = $src",
1978             []>,
1979             Requires<[HasV4T]>;
1980
1981 // if (Pv) memd(##global) = Rtt
1982 let neverHasSideEffects = 1, isPredicated = 1 in
1983 def STd_GP_cPt_V4 : STInst2<(outs),
1984             (ins PredRegs:$src1, globaladdress:$global, DoubleRegs:$src2),
1985             "if ($src1) memd(##$global) = $src2",
1986             []>,
1987             Requires<[HasV4T]>;
1988
1989 // if (!Pv) memd(##global) = Rtt
1990 let neverHasSideEffects = 1, isPredicated = 1 in
1991 def STd_GP_cNotPt_V4 : STInst2<(outs),
1992             (ins PredRegs:$src1, globaladdress:$global, DoubleRegs:$src2),
1993             "if (!$src1) memd(##$global) = $src2",
1994             []>,
1995               Requires<[HasV4T]>;
1996
1997 // if (Pv) memd(##global) = Rtt
1998 let neverHasSideEffects = 1, isPredicated = 1 in
1999 def STd_GP_cdnPt_V4 : STInst2<(outs),
2000             (ins PredRegs:$src1, globaladdress:$global, DoubleRegs:$src2),
2001             "if ($src1.new) memd(##$global) = $src2",
2002             []>,
2003               Requires<[HasV4T]>;
2004
2005 // if (!Pv) memd(##global) = Rtt
2006 let neverHasSideEffects = 1, isPredicated = 1 in
2007 def STd_GP_cdnNotPt_V4 : STInst2<(outs),
2008             (ins PredRegs:$src1, globaladdress:$global, DoubleRegs:$src2),
2009             "if (!$src1.new) memd(##$global) = $src2",
2010             []>,
2011             Requires<[HasV4T]>;
2012
2013 // memb(#global)=Rt
2014 let isPredicable = 1, neverHasSideEffects = 1 in
2015 def STb_GP_V4 : STInst2<(outs),
2016             (ins globaladdress:$global, IntRegs:$src),
2017             "memb(#$global) = $src",
2018             []>,
2019             Requires<[HasV4T]>;
2020
2021 // if (Pv) memb(##global) = Rt
2022 let neverHasSideEffects = 1, isPredicated = 1 in
2023 def STb_GP_cPt_V4 : STInst2<(outs),
2024             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2025             "if ($src1) memb(##$global) = $src2",
2026               []>,
2027               Requires<[HasV4T]>;
2028
2029 // if (!Pv) memb(##global) = Rt
2030 let neverHasSideEffects = 1, isPredicated = 1 in
2031 def STb_GP_cNotPt_V4 : STInst2<(outs),
2032             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2033             "if (!$src1) memb(##$global) = $src2",
2034               []>,
2035               Requires<[HasV4T]>;
2036
2037 // if (Pv) memb(##global) = Rt
2038 let neverHasSideEffects = 1, isPredicated = 1 in
2039 def STb_GP_cdnPt_V4 : STInst2<(outs),
2040             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2041             "if ($src1.new) memb(##$global) = $src2",
2042               []>,
2043               Requires<[HasV4T]>;
2044
2045 // if (!Pv) memb(##global) = Rt
2046 let neverHasSideEffects = 1, isPredicated = 1 in
2047 def STb_GP_cdnNotPt_V4 : STInst2<(outs),
2048             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2049             "if (!$src1.new) memb(##$global) = $src2",
2050               []>,
2051               Requires<[HasV4T]>;
2052
2053 // memh(#global)=Rt
2054 let isPredicable = 1, neverHasSideEffects = 1 in
2055 def STh_GP_V4 : STInst2<(outs),
2056             (ins globaladdress:$global, IntRegs:$src),
2057             "memh(#$global) = $src",
2058             []>,
2059             Requires<[HasV4T]>;
2060
2061 // if (Pv) memh(##global) = Rt
2062 let neverHasSideEffects = 1, isPredicated = 1 in
2063 def STh_GP_cPt_V4 : STInst2<(outs),
2064             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2065             "if ($src1) memh(##$global) = $src2",
2066               []>,
2067               Requires<[HasV4T]>;
2068
2069 // if (!Pv) memh(##global) = Rt
2070 let neverHasSideEffects = 1, isPredicated = 1 in
2071 def STh_GP_cNotPt_V4 : STInst2<(outs),
2072             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2073             "if (!$src1) memh(##$global) = $src2",
2074               []>,
2075               Requires<[HasV4T]>;
2076
2077 // if (Pv) memh(##global) = Rt
2078 let neverHasSideEffects = 1, isPredicated = 1 in
2079 def STh_GP_cdnPt_V4 : STInst2<(outs),
2080             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2081             "if ($src1.new) memh(##$global) = $src2",
2082               []>,
2083               Requires<[HasV4T]>;
2084
2085 // if (!Pv) memh(##global) = Rt
2086 let neverHasSideEffects = 1, isPredicated = 1 in
2087 def STh_GP_cdnNotPt_V4 : STInst2<(outs),
2088             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2089             "if (!$src1.new) memh(##$global) = $src2",
2090               []>,
2091               Requires<[HasV4T]>;
2092
2093 // memw(#global)=Rt
2094 let isPredicable = 1, neverHasSideEffects = 1 in
2095 def STw_GP_V4 : STInst2<(outs),
2096             (ins globaladdress:$global, IntRegs:$src),
2097             "memw(#$global) = $src",
2098               []>,
2099               Requires<[HasV4T]>;
2100
2101 // if (Pv) memw(##global) = Rt
2102 let neverHasSideEffects = 1, isPredicated = 1 in
2103 def STw_GP_cPt_V4 : STInst2<(outs),
2104             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2105             "if ($src1) memw(##$global) = $src2",
2106               []>,
2107               Requires<[HasV4T]>;
2108
2109 // if (!Pv) memw(##global) = Rt
2110 let neverHasSideEffects = 1, isPredicated = 1 in
2111 def STw_GP_cNotPt_V4 : STInst2<(outs),
2112             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2113             "if (!$src1) memw(##$global) = $src2",
2114               []>,
2115               Requires<[HasV4T]>;
2116
2117 // if (Pv) memw(##global) = Rt
2118 let neverHasSideEffects = 1, isPredicated = 1 in
2119 def STw_GP_cdnPt_V4 : STInst2<(outs),
2120             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2121             "if ($src1.new) memw(##$global) = $src2",
2122               []>,
2123               Requires<[HasV4T]>;
2124
2125 // if (!Pv) memw(##global) = Rt
2126 let neverHasSideEffects = 1, isPredicated = 1 in
2127 def STw_GP_cdnNotPt_V4 : STInst2<(outs),
2128             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2129             "if (!$src1.new) memw(##$global) = $src2",
2130             []>,
2131               Requires<[HasV4T]>;
2132
2133 // 64 bit atomic store
2134 def : Pat <(atomic_store_64 (HexagonCONST32_GP tglobaladdr:$global),
2135                             (i64 DoubleRegs:$src1)),
2136            (STd_GP_V4 tglobaladdr:$global, (i64 DoubleRegs:$src1))>,
2137            Requires<[HasV4T]>;
2138
2139 // Map from store(globaladdress) -> memd(#foo)
2140 let AddedComplexity = 100 in
2141 def : Pat <(store (i64 DoubleRegs:$src1),
2142                   (HexagonCONST32_GP tglobaladdr:$global)),
2143            (STd_GP_V4 tglobaladdr:$global, (i64 DoubleRegs:$src1))>,
2144            Requires<[HasV4T]>;
2145
2146 // 8 bit atomic store
2147 def : Pat < (atomic_store_8 (HexagonCONST32_GP tglobaladdr:$global),
2148                             (i32 IntRegs:$src1)),
2149             (STb_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>,
2150               Requires<[HasV4T]>;
2151
2152 // Map from store(globaladdress) -> memb(#foo)
2153 let AddedComplexity = 100 in
2154 def : Pat<(truncstorei8 (i32 IntRegs:$src1),
2155           (HexagonCONST32_GP tglobaladdr:$global)),
2156           (STb_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>,
2157           Requires<[HasV4T]>;
2158
2159 // Map from "i1 = constant<-1>; memw(CONST32(#foo)) = i1"
2160 //       to "r0 = 1; memw(#foo) = r0"
2161 let AddedComplexity = 100 in
2162 def : Pat<(store (i1 -1), (HexagonCONST32_GP tglobaladdr:$global)),
2163           (STb_GP_V4 tglobaladdr:$global, (TFRI 1))>,
2164           Requires<[HasV4T]>;
2165
2166 def : Pat<(atomic_store_16 (HexagonCONST32_GP tglobaladdr:$global),
2167                            (i32 IntRegs:$src1)),
2168           (STh_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>,
2169           Requires<[HasV4T]>;
2170
2171 // Map from store(globaladdress) -> memh(#foo)
2172 let AddedComplexity = 100 in
2173 def : Pat<(truncstorei16 (i32 IntRegs:$src1),
2174                          (HexagonCONST32_GP tglobaladdr:$global)),
2175           (STh_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>,
2176           Requires<[HasV4T]>;
2177
2178 // 32 bit atomic store
2179 def : Pat<(atomic_store_32 (HexagonCONST32_GP tglobaladdr:$global),
2180                            (i32 IntRegs:$src1)),
2181           (STw_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>,
2182           Requires<[HasV4T]>;
2183
2184 // Map from store(globaladdress) -> memw(#foo)
2185 let AddedComplexity = 100 in
2186 def : Pat<(store (i32 IntRegs:$src1), (HexagonCONST32_GP tglobaladdr:$global)),
2187           (STw_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>,
2188           Requires<[HasV4T]>;
2189
2190 def : Pat<(atomic_store_64 (add (HexagonCONST32_GP tglobaladdr:$global),
2191                                 u16ImmPred:$offset),
2192                            (i64 DoubleRegs:$src1)),
2193           (STrid_GP_V4 tglobaladdr:$global, u16ImmPred:$offset,
2194                                             (i64 DoubleRegs:$src1))>,
2195           Requires<[HasV4T]>;
2196
2197 def : Pat<(atomic_store_32 (add (HexagonCONST32_GP tglobaladdr:$global),
2198                                 u16ImmPred:$offset),
2199                            (i32 IntRegs:$src1)),
2200           (STriw_GP_V4 tglobaladdr:$global, u16ImmPred:$offset,
2201                                             (i32 IntRegs:$src1))>,
2202           Requires<[HasV4T]>;
2203
2204 def : Pat<(atomic_store_16 (add (HexagonCONST32_GP tglobaladdr:$global),
2205                                 u16ImmPred:$offset),
2206                            (i32 IntRegs:$src1)),
2207           (STrih_GP_V4 tglobaladdr:$global, u16ImmPred:$offset,
2208                                             (i32 IntRegs:$src1))>,
2209           Requires<[HasV4T]>;
2210
2211 def : Pat<(atomic_store_8 (add (HexagonCONST32_GP tglobaladdr:$global),
2212                                u16ImmPred:$offset),
2213                           (i32 IntRegs:$src1)),
2214           (STrib_GP_V4 tglobaladdr:$global, u16ImmPred:$offset,
2215                                             (i32 IntRegs:$src1))>,
2216           Requires<[HasV4T]>;
2217
2218 // Map from store(globaladdress + x) -> memd(#foo + x)
2219 let AddedComplexity = 100 in
2220 def : Pat<(store (i64 DoubleRegs:$src1),
2221                     (add (HexagonCONST32_GP tglobaladdr:$global),
2222                                         u16ImmPred:$offset)),
2223           (STrid_GP_V4 tglobaladdr:$global, u16ImmPred:$offset,
2224                                             (i64 DoubleRegs:$src1))>,
2225           Requires<[HasV4T]>;
2226
2227 // Map from store(globaladdress + x) -> memb(#foo + x)
2228 let AddedComplexity = 100 in
2229 def : Pat<(truncstorei8 (i32 IntRegs:$src1),
2230                         (add (HexagonCONST32_GP tglobaladdr:$global),
2231                              u16ImmPred:$offset)),
2232           (STrib_GP_V4 tglobaladdr:$global, u16ImmPred:$offset,
2233                                             (i32 IntRegs:$src1))>,
2234           Requires<[HasV4T]>;
2235
2236 // Map from store(globaladdress + x) -> memh(#foo + x)
2237 let AddedComplexity = 100 in
2238 def : Pat<(truncstorei16 (i32 IntRegs:$src1),
2239                          (add (HexagonCONST32_GP tglobaladdr:$global),
2240                               u16ImmPred:$offset)),
2241           (STrih_GP_V4 tglobaladdr:$global, u16ImmPred:$offset,
2242                                             (i32 IntRegs:$src1))>,
2243           Requires<[HasV4T]>;
2244
2245 // Map from store(globaladdress + x) -> memw(#foo + x)
2246 let AddedComplexity = 100 in
2247 def : Pat<(store (i32 IntRegs:$src1),
2248                  (add (HexagonCONST32_GP tglobaladdr:$global),
2249                                 u16ImmPred:$offset)),
2250           (STriw_GP_V4 tglobaladdr:$global, u16ImmPred:$offset,
2251                                             (i32 IntRegs:$src1))>,
2252           Requires<[HasV4T]>;
2253
2254
2255
2256 //===----------------------------------------------------------------------===
2257 // ST -
2258 //===----------------------------------------------------------------------===
2259
2260
2261 //===----------------------------------------------------------------------===//
2262 // NV/ST +
2263 //===----------------------------------------------------------------------===//
2264
2265 // multiclass for new-value store instructions with base + immediate offset.
2266 //
2267 multiclass ST_Idxd_Pbase_nv<string mnemonic, RegisterClass RC,
2268                             Operand predImmOp, bit isNot, bit isPredNew> {
2269   let PNewValue = !if(isPredNew, "new", "") in
2270   def NAME#_nv_V4 : NVInst_V4<(outs),
2271             (ins PredRegs:$src1, IntRegs:$src2, predImmOp:$src3, RC: $src4),
2272             !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
2273             ") ")#mnemonic#"($src2+#$src3) = $src4.new",
2274             []>,
2275             Requires<[HasV4T]>;
2276 }
2277
2278 multiclass ST_Idxd_Pred_nv<string mnemonic, RegisterClass RC, Operand predImmOp,
2279                            bit PredNot> {
2280   let PredSense = !if(PredNot, "false", "true") in {
2281     defm _c#NAME : ST_Idxd_Pbase_nv<mnemonic, RC, predImmOp, PredNot, 0>;
2282     // Predicate new
2283     defm _cdn#NAME : ST_Idxd_Pbase_nv<mnemonic, RC, predImmOp, PredNot, 1>;
2284   }
2285 }
2286
2287 let mayStore = 1, isNVStore = 1, neverHasSideEffects = 1, isExtendable = 1 in
2288 multiclass ST_Idxd_nv<string mnemonic, string CextOp, RegisterClass RC,
2289                    Operand ImmOp, Operand predImmOp, bits<5> ImmBits,
2290                    bits<5> PredImmBits> {
2291
2292   let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed in {
2293     let opExtendable = 1, isExtentSigned = 1, opExtentBits = ImmBits,
2294     isPredicable = 1 in
2295     def NAME#_nv_V4 : NVInst_V4<(outs),
2296             (ins IntRegs:$src1, ImmOp:$src2, RC:$src3),
2297             mnemonic#"($src1+#$src2) = $src3.new",
2298             []>,
2299             Requires<[HasV4T]>;
2300
2301     let opExtendable = 2, isExtentSigned = 0, opExtentBits = PredImmBits,
2302     isPredicated = 1 in {
2303       defm Pt : ST_Idxd_Pred_nv<mnemonic, RC, predImmOp, 0>;
2304       defm NotPt : ST_Idxd_Pred_nv<mnemonic, RC, predImmOp, 1>;
2305     }
2306   }
2307 }
2308
2309 let addrMode = BaseImmOffset, validSubTargets = HasV4SubT in {
2310   defm STrib_indexed: ST_Idxd_nv<"memb", "STrib", IntRegs, s11_0Ext,
2311                                  u6_0Ext, 11, 6>, AddrModeRel;
2312   defm STrih_indexed: ST_Idxd_nv<"memh", "STrih", IntRegs, s11_1Ext,
2313                                  u6_1Ext, 12, 7>, AddrModeRel;
2314   defm STriw_indexed: ST_Idxd_nv<"memw", "STriw", IntRegs, s11_2Ext,
2315                                  u6_2Ext, 13, 8>, AddrModeRel;
2316 }
2317
2318 // multiclass for new-value store instructions with base + immediate offset.
2319 // and MEMri operand.
2320 multiclass ST_MEMri_Pbase_nv<string mnemonic, RegisterClass RC, bit isNot,
2321                           bit isPredNew> {
2322   let PNewValue = !if(isPredNew, "new", "") in
2323   def NAME#_nv_V4 : NVInst_V4<(outs),
2324             (ins PredRegs:$src1, MEMri:$addr, RC: $src2),
2325             !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
2326             ") ")#mnemonic#"($addr) = $src2.new",
2327             []>,
2328             Requires<[HasV4T]>;
2329 }
2330
2331 multiclass ST_MEMri_Pred_nv<string mnemonic, RegisterClass RC, bit PredNot> {
2332   let PredSense = !if(PredNot, "false", "true") in {
2333     defm _c#NAME : ST_MEMri_Pbase_nv<mnemonic, RC, PredNot, 0>;
2334
2335     // Predicate new
2336     defm _cdn#NAME : ST_MEMri_Pbase_nv<mnemonic, RC, PredNot, 1>;
2337   }
2338 }
2339
2340 let mayStore = 1, isNVStore = 1, isExtendable = 1, neverHasSideEffects = 1 in
2341 multiclass ST_MEMri_nv<string mnemonic, string CextOp, RegisterClass RC,
2342                     bits<5> ImmBits, bits<5> PredImmBits> {
2343
2344   let CextOpcode = CextOp, BaseOpcode = CextOp in {
2345     let opExtendable = 1, isExtentSigned = 1, opExtentBits = ImmBits,
2346          isPredicable = 1 in
2347     def NAME#_nv_V4 : NVInst_V4<(outs),
2348             (ins MEMri:$addr, RC:$src),
2349             mnemonic#"($addr) = $src.new",
2350             []>,
2351             Requires<[HasV4T]>;
2352
2353     let opExtendable = 2, isExtentSigned = 0, opExtentBits = PredImmBits,
2354         neverHasSideEffects = 1, isPredicated = 1 in {
2355       defm Pt : ST_MEMri_Pred_nv<mnemonic, RC, 0>;
2356       defm NotPt : ST_MEMri_Pred_nv<mnemonic, RC, 1>;
2357     }
2358   }
2359 }
2360
2361 let addrMode = BaseImmOffset, isMEMri = "true", validSubTargets = HasV4SubT,
2362 mayStore = 1 in {
2363   defm STrib: ST_MEMri_nv<"memb", "STrib", IntRegs, 11, 6>, AddrModeRel;
2364   defm STrih: ST_MEMri_nv<"memh", "STrih", IntRegs, 12, 7>, AddrModeRel;
2365   defm STriw: ST_MEMri_nv<"memw", "STriw", IntRegs, 13, 8>, AddrModeRel;
2366 }
2367
2368 // memb(Ru<<#u2+#U6)=Nt.new
2369 let isExtended = 1, opExtendable = 2, mayStore = 1, AddedComplexity = 10,
2370 isNVStore = 1, validSubTargets = HasV4SubT in
2371 def STrib_shl_nv_V4 : NVInst_V4<(outs),
2372             (ins IntRegs:$src1, u2Imm:$src2, u0AlwaysExt:$src3, IntRegs:$src4),
2373             "memb($src1<<#$src2+#$src3) = $src4.new",
2374             []>,
2375             Requires<[HasV4T]>;
2376
2377 //===----------------------------------------------------------------------===//
2378 // Post increment store
2379 // mem[bhwd](Rx++#s4:[0123])=Nt.new
2380 //===----------------------------------------------------------------------===//
2381
2382 multiclass ST_PostInc_Pbase_nv<string mnemonic, RegisterClass RC, Operand ImmOp,
2383                             bit isNot, bit isPredNew> {
2384   let PNewValue = !if(isPredNew, "new", "") in
2385   def NAME#_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
2386             (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset, RC:$src3),
2387             !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
2388             ") ")#mnemonic#"($src2++#$offset) = $src3.new",
2389             [],
2390             "$src2 = $dst">,
2391             Requires<[HasV4T]>;
2392 }
2393
2394 multiclass ST_PostInc_Pred_nv<string mnemonic, RegisterClass RC,
2395                            Operand ImmOp, bit PredNot> {
2396   let PredSense = !if(PredNot, "false", "true") in {
2397     defm _c#NAME : ST_PostInc_Pbase_nv<mnemonic, RC, ImmOp, PredNot, 0>;
2398     // Predicate new
2399     let Predicates = [HasV4T], validSubTargets = HasV4SubT in
2400     defm _cdn#NAME : ST_PostInc_Pbase_nv<mnemonic, RC, ImmOp, PredNot, 1>;
2401   }
2402 }
2403
2404 let hasCtrlDep = 1, isNVStore = 1, neverHasSideEffects = 1 in
2405 multiclass ST_PostInc_nv<string mnemonic, string BaseOp, RegisterClass RC,
2406                       Operand ImmOp> {
2407
2408   let BaseOpcode = "POST_"#BaseOp in {
2409     let isPredicable = 1 in
2410     def NAME#_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
2411                 (ins IntRegs:$src1, ImmOp:$offset, RC:$src2),
2412                 mnemonic#"($src1++#$offset) = $src2.new",
2413                 [],
2414                 "$src1 = $dst">,
2415                 Requires<[HasV4T]>;
2416
2417     let isPredicated = 1 in {
2418       defm Pt : ST_PostInc_Pred_nv<mnemonic, RC, ImmOp, 0 >;
2419       defm NotPt : ST_PostInc_Pred_nv<mnemonic, RC, ImmOp, 1 >;
2420     }
2421   }
2422 }
2423
2424 let validSubTargets = HasV4SubT in {
2425 defm POST_STbri: ST_PostInc_nv <"memb", "STrib", IntRegs, s4_0Imm>, AddrModeRel;
2426 defm POST_SThri: ST_PostInc_nv <"memh", "STrih", IntRegs, s4_1Imm>, AddrModeRel;
2427 defm POST_STwri: ST_PostInc_nv <"memw", "STriw", IntRegs, s4_2Imm>, AddrModeRel;
2428 }
2429
2430 // memb(Rx++#s4:0:circ(Mu))=Nt.new
2431 // memb(Rx++I:circ(Mu))=Nt.new
2432 // memb(Rx++Mu)=Nt.new
2433 // memb(Rx++Mu:brev)=Nt.new
2434
2435 // memb(gp+#u16:0)=Nt.new
2436 let mayStore = 1, neverHasSideEffects = 1 in
2437 def STrib_GP_nv_V4 : NVInst_V4<(outs),
2438             (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),
2439             "memb(#$global+$offset) = $src.new",
2440             []>,
2441             Requires<[HasV4T]>;
2442
2443 // memb(#global)=Nt.new
2444 let mayStore = 1, neverHasSideEffects = 1 in
2445 def STb_GP_nv_V4 : NVInst_V4<(outs),
2446             (ins globaladdress:$global, IntRegs:$src),
2447             "memb(#$global) = $src.new",
2448             []>,
2449             Requires<[HasV4T]>;
2450
2451 // memh(Ru<<#u2+#U6)=Nt.new
2452 let isExtended = 1, opExtendable = 2, mayStore = 1, AddedComplexity = 10,
2453 isNVStore = 1, validSubTargets = HasV4SubT in
2454 def STrih_shl_nv_V4 : NVInst_V4<(outs),
2455             (ins IntRegs:$src1, u2Imm:$src2, u0AlwaysExt:$src3, IntRegs:$src4),
2456             "memh($src1<<#$src2+#$src3) = $src4.new",
2457             []>,
2458             Requires<[HasV4T]>;
2459
2460 // memh(Rx++#s4:1:circ(Mu))=Nt.new
2461 // memh(Rx++I:circ(Mu))=Nt.new
2462 // memh(Rx++Mu)=Nt.new
2463 // memh(Rx++Mu:brev)=Nt.new
2464
2465 // memh(gp+#u16:1)=Nt.new
2466 let mayStore = 1, neverHasSideEffects = 1 in
2467 def STrih_GP_nv_V4 : NVInst_V4<(outs),
2468             (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),
2469             "memh(#$global+$offset) = $src.new",
2470             []>,
2471             Requires<[HasV4T]>;
2472
2473 // memh(#global)=Nt.new
2474 let mayStore = 1, neverHasSideEffects = 1 in
2475 def STh_GP_nv_V4 : NVInst_V4<(outs),
2476             (ins globaladdress:$global, IntRegs:$src),
2477             "memh(#$global) = $src.new",
2478             []>,
2479             Requires<[HasV4T]>;
2480
2481 // memw(Ru<<#u2+#U6)=Nt.new
2482 let isExtended = 1, opExtendable = 2, mayStore = 1, AddedComplexity = 10,
2483 isNVStore = 1, validSubTargets = HasV4SubT in
2484 def STriw_shl_nv_V4 : NVInst_V4<(outs),
2485             (ins IntRegs:$src1, u2Imm:$src2, u0AlwaysExt:$src3, IntRegs:$src4),
2486             "memw($src1<<#$src2+#$src3) = $src4.new",
2487             []>,
2488             Requires<[HasV4T]>;
2489
2490 // memw(Rx++#s4:2:circ(Mu))=Nt.new
2491 // memw(Rx++I:circ(Mu))=Nt.new
2492 // memw(Rx++Mu)=Nt.new
2493 // memw(Rx++Mu:brev)=Nt.new
2494 // memw(gp+#u16:2)=Nt.new
2495 let mayStore = 1, neverHasSideEffects = 1 in
2496 def STriw_GP_nv_V4 : NVInst_V4<(outs),
2497             (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),
2498             "memw(#$global+$offset) = $src.new",
2499             []>,
2500             Requires<[HasV4T]>;
2501
2502 let mayStore = 1, neverHasSideEffects = 1 in
2503 def STw_GP_nv_V4 : NVInst_V4<(outs),
2504             (ins globaladdress:$global, IntRegs:$src),
2505             "memw(#$global) = $src.new",
2506             []>,
2507             Requires<[HasV4T]>;
2508
2509 // if (Pv) memb(##global) = Rt
2510 let mayStore = 1, neverHasSideEffects = 1 in
2511 def STb_GP_cPt_nv_V4 : NVInst_V4<(outs),
2512             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2513             "if ($src1) memb(##$global) = $src2.new",
2514             []>,
2515             Requires<[HasV4T]>;
2516
2517 // if (!Pv) memb(##global) = Rt
2518 let mayStore = 1, neverHasSideEffects = 1 in
2519 def STb_GP_cNotPt_nv_V4 : NVInst_V4<(outs),
2520             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2521             "if (!$src1) memb(##$global) = $src2.new",
2522             []>,
2523             Requires<[HasV4T]>;
2524
2525 // if (Pv) memb(##global) = Rt
2526 let mayStore = 1, neverHasSideEffects = 1 in
2527 def STb_GP_cdnPt_nv_V4 : NVInst_V4<(outs),
2528             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2529             "if ($src1.new) memb(##$global) = $src2.new",
2530             []>,
2531             Requires<[HasV4T]>;
2532
2533 // if (!Pv) memb(##global) = Rt
2534 let mayStore = 1, neverHasSideEffects = 1 in
2535 def STb_GP_cdnNotPt_nv_V4 : NVInst_V4<(outs),
2536             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2537             "if (!$src1.new) memb(##$global) = $src2.new",
2538             []>,
2539             Requires<[HasV4T]>;
2540
2541 // if (Pv) memh(##global) = Rt
2542 let mayStore = 1, neverHasSideEffects = 1 in
2543 def STh_GP_cPt_nv_V4 : NVInst_V4<(outs),
2544             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2545             "if ($src1) memh(##$global) = $src2.new",
2546             []>,
2547             Requires<[HasV4T]>;
2548
2549 // if (!Pv) memh(##global) = Rt
2550 let mayStore = 1, neverHasSideEffects = 1 in
2551 def STh_GP_cNotPt_nv_V4 : NVInst_V4<(outs),
2552             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2553             "if (!$src1) memh(##$global) = $src2.new",
2554             []>,
2555             Requires<[HasV4T]>;
2556
2557 // if (Pv) memh(##global) = Rt
2558 let mayStore = 1, neverHasSideEffects = 1 in
2559 def STh_GP_cdnPt_nv_V4 : NVInst_V4<(outs),
2560             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2561             "if ($src1.new) memh(##$global) = $src2.new",
2562             []>,
2563             Requires<[HasV4T]>;
2564
2565 // if (!Pv) memh(##global) = Rt
2566 let mayStore = 1, neverHasSideEffects = 1 in
2567 def STh_GP_cdnNotPt_nv_V4 : NVInst_V4<(outs),
2568             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2569             "if (!$src1.new) memh(##$global) = $src2.new",
2570             []>,
2571             Requires<[HasV4T]>;
2572
2573 // if (Pv) memw(##global) = Rt
2574 let mayStore = 1, neverHasSideEffects = 1 in
2575 def STw_GP_cPt_nv_V4 : NVInst_V4<(outs),
2576             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2577             "if ($src1) memw(##$global) = $src2.new",
2578             []>,
2579             Requires<[HasV4T]>;
2580
2581 // if (!Pv) memw(##global) = Rt
2582 let mayStore = 1, neverHasSideEffects = 1 in
2583 def STw_GP_cNotPt_nv_V4 : NVInst_V4<(outs),
2584             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2585             "if (!$src1) memw(##$global) = $src2.new",
2586             []>,
2587             Requires<[HasV4T]>;
2588
2589 // if (Pv) memw(##global) = Rt
2590 let mayStore = 1, neverHasSideEffects = 1 in
2591 def STw_GP_cdnPt_nv_V4 : NVInst_V4<(outs),
2592             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2593             "if ($src1.new) memw(##$global) = $src2.new",
2594             []>,
2595             Requires<[HasV4T]>;
2596
2597 // if (!Pv) memw(##global) = Rt
2598 let mayStore = 1, neverHasSideEffects = 1 in
2599 def STw_GP_cdnNotPt_nv_V4 : NVInst_V4<(outs),
2600             (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2601             "if (!$src1.new) memw(##$global) = $src2.new",
2602             []>,
2603             Requires<[HasV4T]>;
2604
2605 let mayStore = 1, neverHasSideEffects = 1 in
2606 def STrib_GP_cPt_nv_V4 : NVInst_V4<(outs),
2607             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2608                                                         IntRegs:$src2),
2609             "if ($src1) memb(##$global+$offset) = $src2.new",
2610             []>,
2611             Requires<[HasV4T]>;
2612
2613 let mayStore = 1, neverHasSideEffects = 1 in
2614 def STrib_GP_cNotPt_nv_V4 : NVInst_V4<(outs),
2615             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2616                                                         IntRegs:$src2),
2617             "if (!$src1) memb(##$global+$offset) = $src2.new",
2618             []>,
2619             Requires<[HasV4T]>;
2620
2621 let mayStore = 1, neverHasSideEffects = 1 in
2622 def STrib_GP_cdnPt_nv_V4 : NVInst_V4<(outs),
2623             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2624                                                         IntRegs:$src2),
2625             "if ($src1.new) memb(##$global+$offset) = $src2.new",
2626             []>,
2627             Requires<[HasV4T]>;
2628
2629 let mayStore = 1, neverHasSideEffects = 1 in
2630 def STrib_GP_cdnNotPt_nv_V4 : NVInst_V4<(outs),
2631             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2632                                                         IntRegs:$src2),
2633             "if (!$src1.new) memb(##$global+$offset) = $src2.new",
2634             []>,
2635             Requires<[HasV4T]>;
2636
2637 let mayStore = 1, neverHasSideEffects = 1 in
2638 def STrih_GP_cPt_nv_V4 : NVInst_V4<(outs),
2639             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2640                                                         IntRegs:$src2),
2641             "if ($src1) memh(##$global+$offset) = $src2.new",
2642             []>,
2643             Requires<[HasV4T]>;
2644
2645 let mayStore = 1, neverHasSideEffects = 1 in
2646 def STrih_GP_cNotPt_nv_V4 : NVInst_V4<(outs),
2647             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2648                                                         IntRegs:$src2),
2649             "if (!$src1) memh(##$global+$offset) = $src2.new",
2650             []>,
2651             Requires<[HasV4T]>;
2652
2653 let mayStore = 1, neverHasSideEffects = 1 in
2654 def STrih_GP_cdnPt_nv_V4 : NVInst_V4<(outs),
2655             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2656                                                         IntRegs:$src2),
2657             "if ($src1.new) memh(##$global+$offset) = $src2.new",
2658             []>,
2659             Requires<[HasV4T]>;
2660
2661 let mayStore = 1, neverHasSideEffects = 1 in
2662 def STrih_GP_cdnNotPt_nv_V4 : NVInst_V4<(outs),
2663             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2664                                                         IntRegs:$src2),
2665             "if (!$src1.new) memh(##$global+$offset) = $src2.new",
2666             []>,
2667             Requires<[HasV4T]>;
2668
2669 let mayStore = 1, neverHasSideEffects = 1 in
2670 def STriw_GP_cPt_nv_V4 : NVInst_V4<(outs),
2671             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2672                                                         IntRegs:$src2),
2673             "if ($src1) memw(##$global+$offset) = $src2.new",
2674             []>,
2675             Requires<[HasV4T]>;
2676
2677 let mayStore = 1, neverHasSideEffects = 1 in
2678 def STriw_GP_cNotPt_nv_V4 : NVInst_V4<(outs),
2679             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2680                                                         IntRegs:$src2),
2681             "if (!$src1) memw(##$global+$offset) = $src2.new",
2682             []>,
2683             Requires<[HasV4T]>;
2684
2685 let mayStore = 1, neverHasSideEffects = 1 in
2686 def STriw_GP_cdnPt_nv_V4 : NVInst_V4<(outs),
2687             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2688                                                         IntRegs:$src2),
2689             "if ($src1.new) memw(##$global+$offset) = $src2.new",
2690             []>,
2691             Requires<[HasV4T]>;
2692
2693 let mayStore = 1, neverHasSideEffects = 1 in
2694 def STriw_GP_cdnNotPt_nv_V4 : NVInst_V4<(outs),
2695             (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2696                                                         IntRegs:$src2),
2697             "if (!$src1.new) memw(##$global+$offset) = $src2.new",
2698             []>,
2699             Requires<[HasV4T]>;
2700
2701 //===----------------------------------------------------------------------===//
2702 // NV/ST -
2703 //===----------------------------------------------------------------------===//
2704
2705 //===----------------------------------------------------------------------===//
2706 // NV/J +
2707 //===----------------------------------------------------------------------===//
2708
2709 multiclass NVJ_type_basic_reg<string NotStr, string OpcStr, string TakenStr> {
2710   def _ie_nv_V4 : NVInst_V4<(outs),
2711             (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset),
2712             !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
2713             !strconcat("($src1.new, $src2)) jump:",
2714             !strconcat(TakenStr, " $offset"))))),
2715             []>,
2716             Requires<[HasV4T]>;
2717
2718   def _nv_V4 : NVInst_V4<(outs),
2719             (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset),
2720             !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
2721             !strconcat("($src1.new, $src2)) jump:",
2722             !strconcat(TakenStr, " $offset"))))),
2723             []>,
2724             Requires<[HasV4T]>;
2725 }
2726
2727 multiclass NVJ_type_basic_2ndDotNew<string NotStr, string OpcStr,
2728                                                    string TakenStr> {
2729   def _ie_nv_V4 : NVInst_V4<(outs),
2730             (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset),
2731             !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
2732             !strconcat("($src1, $src2.new)) jump:",
2733             !strconcat(TakenStr, " $offset"))))),
2734             []>,
2735             Requires<[HasV4T]>;
2736
2737   def _nv_V4 : NVInst_V4<(outs),
2738             (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset),
2739             !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
2740             !strconcat("($src1, $src2.new)) jump:",
2741             !strconcat(TakenStr, " $offset"))))),
2742             []>,
2743             Requires<[HasV4T]>;
2744 }
2745
2746 multiclass NVJ_type_basic_imm<string NotStr, string OpcStr, string TakenStr> {
2747   def _ie_nv_V4 : NVInst_V4<(outs),
2748             (ins IntRegs:$src1, u5Imm:$src2, brtarget:$offset),
2749             !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
2750             !strconcat("($src1.new, #$src2)) jump:",
2751             !strconcat(TakenStr, " $offset"))))),
2752             []>,
2753             Requires<[HasV4T]>;
2754
2755   def _nv_V4 : NVInst_V4<(outs),
2756             (ins IntRegs:$src1, u5Imm:$src2, brtarget:$offset),
2757             !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
2758             !strconcat("($src1.new, #$src2)) jump:",
2759             !strconcat(TakenStr, " $offset"))))),
2760             []>,
2761             Requires<[HasV4T]>;
2762 }
2763
2764 multiclass NVJ_type_basic_neg<string NotStr, string OpcStr, string TakenStr> {
2765   def _ie_nv_V4 : NVInst_V4<(outs),
2766             (ins IntRegs:$src1, nOneImm:$src2, brtarget:$offset),
2767             !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
2768             !strconcat("($src1.new, #$src2)) jump:",
2769             !strconcat(TakenStr, " $offset"))))),
2770             []>,
2771             Requires<[HasV4T]>;
2772
2773   def _nv_V4 : NVInst_V4<(outs),
2774             (ins IntRegs:$src1, nOneImm:$src2, brtarget:$offset),
2775             !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
2776             !strconcat("($src1.new, #$src2)) jump:",
2777             !strconcat(TakenStr, " $offset"))))),
2778             []>,
2779             Requires<[HasV4T]>;
2780 }
2781
2782 multiclass NVJ_type_basic_tstbit<string NotStr, string OpcStr,
2783                                                 string TakenStr> {
2784   def _ie_nv_V4 : NVInst_V4<(outs),
2785             (ins IntRegs:$src1, u1Imm:$src2, brtarget:$offset),
2786             !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
2787             !strconcat("($src1.new, #$src2)) jump:",
2788             !strconcat(TakenStr, " $offset"))))),
2789             []>,
2790             Requires<[HasV4T]>;
2791
2792   def _nv_V4 : NVInst_V4<(outs),
2793             (ins IntRegs:$src1, u1Imm:$src2, brtarget:$offset),
2794             !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
2795             !strconcat("($src1.new, #$src2)) jump:",
2796             !strconcat(TakenStr, " $offset"))))),
2797             []>,
2798             Requires<[HasV4T]>;
2799 }
2800
2801 // Multiclass for regular dot new of Ist operand register.
2802 multiclass NVJ_type_br_pred_reg<string NotStr, string OpcStr> {
2803   defm Pt  : NVJ_type_basic_reg<NotStr, OpcStr, "t">;
2804   defm Pnt : NVJ_type_basic_reg<NotStr, OpcStr, "nt">;
2805 }
2806
2807 // Multiclass for dot new of 2nd operand register.
2808 multiclass NVJ_type_br_pred_2ndDotNew<string NotStr, string OpcStr> {
2809   defm Pt  : NVJ_type_basic_2ndDotNew<NotStr, OpcStr, "t">;
2810   defm Pnt : NVJ_type_basic_2ndDotNew<NotStr, OpcStr, "nt">;
2811 }
2812
2813 // Multiclass for 2nd operand immediate, including -1.
2814 multiclass NVJ_type_br_pred_imm<string NotStr, string OpcStr> {
2815   defm Pt     : NVJ_type_basic_imm<NotStr, OpcStr, "t">;
2816   defm Pnt    : NVJ_type_basic_imm<NotStr, OpcStr, "nt">;
2817   defm Ptneg  : NVJ_type_basic_neg<NotStr, OpcStr, "t">;
2818   defm Pntneg : NVJ_type_basic_neg<NotStr, OpcStr, "nt">;
2819 }
2820
2821 // Multiclass for 2nd operand immediate, excluding -1.
2822 multiclass NVJ_type_br_pred_imm_only<string NotStr, string OpcStr> {
2823   defm Pt     : NVJ_type_basic_imm<NotStr, OpcStr, "t">;
2824   defm Pnt    : NVJ_type_basic_imm<NotStr, OpcStr, "nt">;
2825 }
2826
2827 // Multiclass for tstbit, where 2nd operand is always #0.
2828 multiclass NVJ_type_br_pred_tstbit<string NotStr, string OpcStr> {
2829   defm Pt     : NVJ_type_basic_tstbit<NotStr, OpcStr, "t">;
2830   defm Pnt    : NVJ_type_basic_tstbit<NotStr, OpcStr, "nt">;
2831 }
2832
2833 // Multiclass for GT.
2834 multiclass NVJ_type_rr_ri<string OpcStr> {
2835   defm rrNot   : NVJ_type_br_pred_reg<"!", OpcStr>;
2836   defm rr      : NVJ_type_br_pred_reg<"",  OpcStr>;
2837   defm rrdnNot : NVJ_type_br_pred_2ndDotNew<"!", OpcStr>;
2838   defm rrdn    : NVJ_type_br_pred_2ndDotNew<"",  OpcStr>;
2839   defm riNot   : NVJ_type_br_pred_imm<"!", OpcStr>;
2840   defm ri      : NVJ_type_br_pred_imm<"",  OpcStr>;
2841 }
2842
2843 // Multiclass for EQ.
2844 multiclass NVJ_type_rr_ri_no_2ndDotNew<string OpcStr> {
2845   defm rrNot   : NVJ_type_br_pred_reg<"!", OpcStr>;
2846   defm rr      : NVJ_type_br_pred_reg<"",  OpcStr>;
2847   defm riNot   : NVJ_type_br_pred_imm<"!", OpcStr>;
2848   defm ri      : NVJ_type_br_pred_imm<"",  OpcStr>;
2849 }
2850
2851 // Multiclass for GTU.
2852 multiclass NVJ_type_rr_ri_no_nOne<string OpcStr> {
2853   defm rrNot   : NVJ_type_br_pred_reg<"!", OpcStr>;
2854   defm rr      : NVJ_type_br_pred_reg<"",  OpcStr>;
2855   defm rrdnNot : NVJ_type_br_pred_2ndDotNew<"!", OpcStr>;
2856   defm rrdn    : NVJ_type_br_pred_2ndDotNew<"",  OpcStr>;
2857   defm riNot   : NVJ_type_br_pred_imm_only<"!", OpcStr>;
2858   defm ri      : NVJ_type_br_pred_imm_only<"",  OpcStr>;
2859 }
2860
2861 // Multiclass for tstbit.
2862 multiclass NVJ_type_r0<string OpcStr> {
2863   defm r0Not : NVJ_type_br_pred_tstbit<"!", OpcStr>;
2864   defm r0    : NVJ_type_br_pred_tstbit<"",  OpcStr>;
2865  }
2866
2867 // Base Multiclass for New Value Jump.
2868 multiclass NVJ_type {
2869   defm GT     : NVJ_type_rr_ri<"cmp.gt">;
2870   defm EQ     : NVJ_type_rr_ri_no_2ndDotNew<"cmp.eq">;
2871   defm GTU    : NVJ_type_rr_ri_no_nOne<"cmp.gtu">;
2872   defm TSTBIT : NVJ_type_r0<"tstbit">;
2873 }
2874
2875 let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC] in {
2876   defm JMP_ : NVJ_type;
2877 }
2878
2879 //===----------------------------------------------------------------------===//
2880 // NV/J -
2881 //===----------------------------------------------------------------------===//
2882
2883 //===----------------------------------------------------------------------===//
2884 // XTYPE/ALU +
2885 //===----------------------------------------------------------------------===//
2886
2887 //  Add and accumulate.
2888 //  Rd=add(Rs,add(Ru,#s6))
2889 let isExtendable = 1, opExtendable = 3, isExtentSigned = 1, opExtentBits = 6,
2890 validSubTargets = HasV4SubT in
2891 def ADDr_ADDri_V4 : MInst<(outs IntRegs:$dst),
2892           (ins IntRegs:$src1, IntRegs:$src2, s6Ext:$src3),
2893           "$dst = add($src1, add($src2, #$src3))",
2894           [(set (i32 IntRegs:$dst),
2895            (add (i32 IntRegs:$src1), (add (i32 IntRegs:$src2),
2896                                           s6_16ExtPred:$src3)))]>,
2897           Requires<[HasV4T]>;
2898
2899 //  Rd=add(Rs,sub(#s6,Ru))
2900 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 6,
2901 validSubTargets = HasV4SubT in
2902 def ADDr_SUBri_V4 : MInst<(outs IntRegs:$dst),
2903           (ins IntRegs:$src1, s6Ext:$src2, IntRegs:$src3),
2904           "$dst = add($src1, sub(#$src2, $src3))",
2905           [(set (i32 IntRegs:$dst),
2906            (add (i32 IntRegs:$src1), (sub s6_10ExtPred:$src2,
2907                                           (i32 IntRegs:$src3))))]>,
2908           Requires<[HasV4T]>;
2909
2910 // Generates the same instruction as ADDr_SUBri_V4 but matches different
2911 // pattern.
2912 //  Rd=add(Rs,sub(#s6,Ru))
2913 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 6,
2914 validSubTargets = HasV4SubT in
2915 def ADDri_SUBr_V4 : MInst<(outs IntRegs:$dst),
2916           (ins IntRegs:$src1, s6Ext:$src2, IntRegs:$src3),
2917           "$dst = add($src1, sub(#$src2, $src3))",
2918           [(set (i32 IntRegs:$dst),
2919                 (sub (add (i32 IntRegs:$src1), s6_10ExtPred:$src2),
2920                      (i32 IntRegs:$src3)))]>,
2921           Requires<[HasV4T]>;
2922
2923
2924 //  Add or subtract doublewords with carry.
2925 //TODO:
2926 //  Rdd=add(Rss,Rtt,Px):carry
2927 //TODO:
2928 //  Rdd=sub(Rss,Rtt,Px):carry
2929
2930
2931 //  Logical doublewords.
2932 //  Rdd=and(Rtt,~Rss)
2933 let validSubTargets = HasV4SubT in
2934 def ANDd_NOTd_V4 : MInst<(outs DoubleRegs:$dst),
2935           (ins DoubleRegs:$src1, DoubleRegs:$src2),
2936           "$dst = and($src1, ~$src2)",
2937           [(set (i64 DoubleRegs:$dst), (and (i64 DoubleRegs:$src1),
2938                                       (not (i64 DoubleRegs:$src2))))]>,
2939           Requires<[HasV4T]>;
2940
2941 //  Rdd=or(Rtt,~Rss)
2942 let validSubTargets = HasV4SubT in
2943 def ORd_NOTd_V4 : MInst<(outs DoubleRegs:$dst),
2944           (ins DoubleRegs:$src1, DoubleRegs:$src2),
2945           "$dst = or($src1, ~$src2)",
2946           [(set (i64 DoubleRegs:$dst),
2947            (or (i64 DoubleRegs:$src1), (not (i64 DoubleRegs:$src2))))]>,
2948           Requires<[HasV4T]>;
2949
2950
2951 //  Logical-logical doublewords.
2952 //  Rxx^=xor(Rss,Rtt)
2953 let validSubTargets = HasV4SubT in
2954 def XORd_XORdd: MInst_acc<(outs DoubleRegs:$dst),
2955           (ins DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),
2956           "$dst ^= xor($src2, $src3)",
2957           [(set (i64 DoubleRegs:$dst),
2958            (xor (i64 DoubleRegs:$src1), (xor (i64 DoubleRegs:$src2),
2959                                              (i64 DoubleRegs:$src3))))],
2960           "$src1 = $dst">,
2961           Requires<[HasV4T]>;
2962
2963
2964 // Logical-logical words.
2965 // Rx=or(Ru,and(Rx,#s10))
2966 let isExtendable = 1, opExtendable = 3, isExtentSigned = 1, opExtentBits = 10,
2967 validSubTargets = HasV4SubT in
2968 def ORr_ANDri_V4 : MInst_acc<(outs IntRegs:$dst),
2969             (ins IntRegs:$src1, IntRegs: $src2, s10Ext:$src3),
2970             "$dst = or($src1, and($src2, #$src3))",
2971             [(set (i32 IntRegs:$dst),
2972                   (or (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
2973                                                 s10ExtPred:$src3)))],
2974             "$src2 = $dst">,
2975             Requires<[HasV4T]>;
2976
2977 // Rx[&|^]=and(Rs,Rt)
2978 // Rx&=and(Rs,Rt)
2979 let validSubTargets = HasV4SubT in
2980 def ANDr_ANDrr_V4 : MInst_acc<(outs IntRegs:$dst),
2981             (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
2982             "$dst &= and($src2, $src3)",
2983             [(set (i32 IntRegs:$dst),
2984                   (and (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
2985                                                  (i32 IntRegs:$src3))))],
2986             "$src1 = $dst">,
2987             Requires<[HasV4T]>;
2988
2989 // Rx|=and(Rs,Rt)
2990 let validSubTargets = HasV4SubT, CextOpcode = "ORr_ANDr", InputType = "reg" in
2991 def ORr_ANDrr_V4 : MInst_acc<(outs IntRegs:$dst),
2992             (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
2993             "$dst |= and($src2, $src3)",
2994             [(set (i32 IntRegs:$dst),
2995                   (or (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
2996                                                 (i32 IntRegs:$src3))))],
2997             "$src1 = $dst">,
2998             Requires<[HasV4T]>, ImmRegRel;
2999
3000 // Rx^=and(Rs,Rt)
3001 let validSubTargets = HasV4SubT in
3002 def XORr_ANDrr_V4 : MInst_acc<(outs IntRegs:$dst),
3003             (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
3004             "$dst ^= and($src2, $src3)",
3005             [(set (i32 IntRegs:$dst),
3006              (xor (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
3007                                             (i32 IntRegs:$src3))))],
3008             "$src1 = $dst">,
3009             Requires<[HasV4T]>;
3010
3011 // Rx[&|^]=and(Rs,~Rt)
3012 // Rx&=and(Rs,~Rt)
3013 let validSubTargets = HasV4SubT in
3014 def ANDr_ANDr_NOTr_V4 : MInst_acc<(outs IntRegs:$dst),
3015             (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
3016             "$dst &= and($src2, ~$src3)",
3017             [(set (i32 IntRegs:$dst),
3018                   (and (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
3019                                                  (not (i32 IntRegs:$src3)))))],
3020             "$src1 = $dst">,
3021             Requires<[HasV4T]>;
3022
3023 // Rx|=and(Rs,~Rt)
3024 let validSubTargets = HasV4SubT in
3025 def ORr_ANDr_NOTr_V4 : MInst_acc<(outs IntRegs:$dst),
3026             (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
3027             "$dst |= and($src2, ~$src3)",
3028             [(set (i32 IntRegs:$dst),
3029              (or (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
3030                                            (not (i32 IntRegs:$src3)))))],
3031             "$src1 = $dst">,
3032             Requires<[HasV4T]>;
3033
3034 // Rx^=and(Rs,~Rt)
3035 let validSubTargets = HasV4SubT in
3036 def XORr_ANDr_NOTr_V4 : MInst_acc<(outs IntRegs:$dst),
3037             (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
3038             "$dst ^= and($src2, ~$src3)",
3039             [(set (i32 IntRegs:$dst),
3040              (xor (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
3041                                             (not (i32 IntRegs:$src3)))))],
3042             "$src1 = $dst">,
3043             Requires<[HasV4T]>;
3044
3045 // Rx[&|^]=or(Rs,Rt)
3046 // Rx&=or(Rs,Rt)
3047 let validSubTargets = HasV4SubT in
3048 def ANDr_ORrr_V4 : MInst_acc<(outs IntRegs:$dst),
3049             (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
3050             "$dst &= or($src2, $src3)",
3051             [(set (i32 IntRegs:$dst),
3052                   (and (i32 IntRegs:$src1), (or (i32 IntRegs:$src2),
3053                                                 (i32 IntRegs:$src3))))],
3054             "$src1 = $dst">,
3055             Requires<[HasV4T]>;
3056
3057 // Rx|=or(Rs,Rt)
3058 let validSubTargets = HasV4SubT, CextOpcode = "ORr_ORr", InputType = "reg" in
3059 def ORr_ORrr_V4 : MInst_acc<(outs IntRegs:$dst),
3060             (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
3061             "$dst |= or($src2, $src3)",
3062             [(set (i32 IntRegs:$dst),
3063                   (or (i32 IntRegs:$src1), (or (i32 IntRegs:$src2),
3064                                                (i32 IntRegs:$src3))))],
3065             "$src1 = $dst">,
3066             Requires<[HasV4T]>, ImmRegRel;
3067
3068 // Rx^=or(Rs,Rt)
3069 let validSubTargets = HasV4SubT in
3070 def XORr_ORrr_V4 : MInst_acc<(outs IntRegs:$dst),
3071             (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
3072             "$dst ^= or($src2, $src3)",
3073             [(set (i32 IntRegs:$dst),
3074              (xor (i32 IntRegs:$src1), (or (i32 IntRegs:$src2),
3075                                            (i32 IntRegs:$src3))))],
3076             "$src1 = $dst">,
3077             Requires<[HasV4T]>;
3078
3079 // Rx[&|^]=xor(Rs,Rt)
3080 // Rx&=xor(Rs,Rt)
3081 let validSubTargets = HasV4SubT in
3082 def ANDr_XORrr_V4 : MInst_acc<(outs IntRegs:$dst),
3083             (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
3084             "$dst &= xor($src2, $src3)",
3085             [(set (i32 IntRegs:$dst),
3086                   (and (i32 IntRegs:$src1), (xor (i32 IntRegs:$src2),
3087                                                  (i32 IntRegs:$src3))))],
3088             "$src1 = $dst">,
3089             Requires<[HasV4T]>;
3090
3091 // Rx|=xor(Rs,Rt)
3092 let validSubTargets = HasV4SubT in
3093 def ORr_XORrr_V4 : MInst_acc<(outs IntRegs:$dst),
3094             (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
3095             "$dst |= xor($src2, $src3)",
3096             [(set (i32 IntRegs:$dst),
3097                   (and (i32 IntRegs:$src1), (xor (i32 IntRegs:$src2),
3098                                                  (i32 IntRegs:$src3))))],
3099             "$src1 = $dst">,
3100             Requires<[HasV4T]>;
3101
3102 // Rx^=xor(Rs,Rt)
3103 let validSubTargets = HasV4SubT in
3104 def XORr_XORrr_V4 : MInst_acc<(outs IntRegs:$dst),
3105             (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
3106             "$dst ^= xor($src2, $src3)",
3107             [(set (i32 IntRegs:$dst),
3108              (and (i32 IntRegs:$src1), (xor (i32 IntRegs:$src2),
3109                                             (i32 IntRegs:$src3))))],
3110             "$src1 = $dst">,
3111             Requires<[HasV4T]>;
3112
3113 // Rx|=and(Rs,#s10)
3114 let isExtendable = 1, opExtendable = 3, isExtentSigned = 1, opExtentBits = 10,
3115 validSubTargets = HasV4SubT, CextOpcode = "ORr_ANDr", InputType = "imm" in
3116 def ORr_ANDri2_V4 : MInst_acc<(outs IntRegs:$dst),
3117             (ins IntRegs:$src1, IntRegs: $src2, s10Ext:$src3),
3118             "$dst |= and($src2, #$src3)",
3119             [(set (i32 IntRegs:$dst),
3120                   (or (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
3121                                                 s10ExtPred:$src3)))],
3122             "$src1 = $dst">,
3123             Requires<[HasV4T]>, ImmRegRel;
3124
3125 // Rx|=or(Rs,#s10)
3126 let isExtendable = 1, opExtendable = 3, isExtentSigned = 1, opExtentBits = 10,
3127 validSubTargets = HasV4SubT, CextOpcode = "ORr_ORr", InputType = "imm" in
3128 def ORr_ORri_V4 : MInst_acc<(outs IntRegs:$dst),
3129             (ins IntRegs:$src1, IntRegs: $src2, s10Ext:$src3),
3130             "$dst |= or($src2, #$src3)",
3131             [(set (i32 IntRegs:$dst),
3132                   (or (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
3133                                                 s10ExtPred:$src3)))],
3134             "$src1 = $dst">,
3135             Requires<[HasV4T]>, ImmRegRel;
3136
3137
3138 //    Modulo wrap
3139 //        Rd=modwrap(Rs,Rt)
3140 //    Round
3141 //        Rd=cround(Rs,#u5)
3142 //        Rd=cround(Rs,Rt)
3143 //        Rd=round(Rs,#u5)[:sat]
3144 //        Rd=round(Rs,Rt)[:sat]
3145 //    Vector reduce add unsigned halfwords
3146 //        Rd=vraddh(Rss,Rtt)
3147 //    Vector add bytes
3148 //        Rdd=vaddb(Rss,Rtt)
3149 //    Vector conditional negate
3150 //        Rdd=vcnegh(Rss,Rt)
3151 //        Rxx+=vrcnegh(Rss,Rt)
3152 //    Vector maximum bytes
3153 //        Rdd=vmaxb(Rtt,Rss)
3154 //    Vector reduce maximum halfwords
3155 //        Rxx=vrmaxh(Rss,Ru)
3156 //        Rxx=vrmaxuh(Rss,Ru)
3157 //    Vector reduce maximum words
3158 //        Rxx=vrmaxuw(Rss,Ru)
3159 //        Rxx=vrmaxw(Rss,Ru)
3160 //    Vector minimum bytes
3161 //        Rdd=vminb(Rtt,Rss)
3162 //    Vector reduce minimum halfwords
3163 //        Rxx=vrminh(Rss,Ru)
3164 //        Rxx=vrminuh(Rss,Ru)
3165 //    Vector reduce minimum words
3166 //        Rxx=vrminuw(Rss,Ru)
3167 //        Rxx=vrminw(Rss,Ru)
3168 //    Vector subtract bytes
3169 //        Rdd=vsubb(Rss,Rtt)
3170
3171 //===----------------------------------------------------------------------===//
3172 // XTYPE/ALU -
3173 //===----------------------------------------------------------------------===//
3174
3175
3176 //===----------------------------------------------------------------------===//
3177 // XTYPE/MPY +
3178 //===----------------------------------------------------------------------===//
3179
3180 // Multiply and user lower result.
3181 // Rd=add(#u6,mpyi(Rs,#U6))
3182 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 6,
3183 validSubTargets = HasV4SubT in
3184 def ADDi_MPYri_V4 : MInst<(outs IntRegs:$dst),
3185             (ins u6Ext:$src1, IntRegs:$src2, u6Imm:$src3),
3186             "$dst = add(#$src1, mpyi($src2, #$src3))",
3187             [(set (i32 IntRegs:$dst),
3188                   (add (mul (i32 IntRegs:$src2), u6ImmPred:$src3),
3189                        u6ExtPred:$src1))]>,
3190             Requires<[HasV4T]>;
3191
3192 // Rd=add(##,mpyi(Rs,#U6))
3193 def : Pat <(add (mul (i32 IntRegs:$src2), u6ImmPred:$src3),
3194                      (HexagonCONST32 tglobaladdr:$src1)),
3195            (i32 (ADDi_MPYri_V4 tglobaladdr:$src1, IntRegs:$src2,
3196                                u6ImmPred:$src3))>;
3197
3198 // Rd=add(#u6,mpyi(Rs,Rt))
3199 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 6,
3200 validSubTargets = HasV4SubT, InputType = "imm", CextOpcode = "ADD_MPY" in
3201 def ADDi_MPYrr_V4 : MInst<(outs IntRegs:$dst),
3202             (ins u6Ext:$src1, IntRegs:$src2, IntRegs:$src3),
3203             "$dst = add(#$src1, mpyi($src2, $src3))",
3204             [(set (i32 IntRegs:$dst),
3205                   (add (mul (i32 IntRegs:$src2), (i32 IntRegs:$src3)),
3206                        u6ExtPred:$src1))]>,
3207             Requires<[HasV4T]>, ImmRegRel;
3208
3209 // Rd=add(##,mpyi(Rs,Rt))
3210 def : Pat <(add (mul (i32 IntRegs:$src2), (i32 IntRegs:$src3)),
3211                      (HexagonCONST32 tglobaladdr:$src1)),
3212            (i32 (ADDi_MPYrr_V4 tglobaladdr:$src1, IntRegs:$src2,
3213                                IntRegs:$src3))>;
3214
3215 // Rd=add(Ru,mpyi(#u6:2,Rs))
3216 let validSubTargets = HasV4SubT in
3217 def ADDr_MPYir_V4 : MInst<(outs IntRegs:$dst),
3218             (ins IntRegs:$src1, u6Imm:$src2, IntRegs:$src3),
3219             "$dst = add($src1, mpyi(#$src2, $src3))",
3220             [(set (i32 IntRegs:$dst),
3221              (add (i32 IntRegs:$src1), (mul (i32 IntRegs:$src3),
3222                                             u6_2ImmPred:$src2)))]>,
3223             Requires<[HasV4T]>;
3224
3225 // Rd=add(Ru,mpyi(Rs,#u6))
3226 let isExtendable = 1, opExtendable = 3, isExtentSigned = 0, opExtentBits = 6,
3227 validSubTargets = HasV4SubT, InputType = "imm", CextOpcode = "ADD_MPY" in
3228 def ADDr_MPYri_V4 : MInst<(outs IntRegs:$dst),
3229             (ins IntRegs:$src1, IntRegs:$src2, u6Ext:$src3),
3230             "$dst = add($src1, mpyi($src2, #$src3))",
3231             [(set (i32 IntRegs:$dst),
3232                   (add (i32 IntRegs:$src1), (mul (i32 IntRegs:$src2),
3233                                                  u6ExtPred:$src3)))]>,
3234             Requires<[HasV4T]>, ImmRegRel;
3235
3236 // Rx=add(Ru,mpyi(Rx,Rs))
3237 let validSubTargets = HasV4SubT, InputType = "reg", CextOpcode = "ADD_MPY" in
3238 def ADDr_MPYrr_V4 : MInst_acc<(outs IntRegs:$dst),
3239             (ins IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
3240             "$dst = add($src1, mpyi($src2, $src3))",
3241             [(set (i32 IntRegs:$dst),
3242              (add (i32 IntRegs:$src1), (mul (i32 IntRegs:$src2),
3243                                             (i32 IntRegs:$src3))))],
3244             "$src2 = $dst">,
3245             Requires<[HasV4T]>, ImmRegRel;
3246
3247
3248 // Polynomial multiply words
3249 // Rdd=pmpyw(Rs,Rt)
3250 // Rxx^=pmpyw(Rs,Rt)
3251
3252 // Vector reduce multiply word by signed half (32x16)
3253 // Rdd=vrmpyweh(Rss,Rtt)[:<<1]
3254 // Rdd=vrmpywoh(Rss,Rtt)[:<<1]
3255 // Rxx+=vrmpyweh(Rss,Rtt)[:<<1]
3256 // Rxx+=vrmpywoh(Rss,Rtt)[:<<1]
3257
3258 // Multiply and use upper result
3259 // Rd=mpy(Rs,Rt.H):<<1:sat
3260 // Rd=mpy(Rs,Rt.L):<<1:sat
3261 // Rd=mpy(Rs,Rt):<<1
3262 // Rd=mpy(Rs,Rt):<<1:sat
3263 // Rd=mpysu(Rs,Rt)
3264 // Rx+=mpy(Rs,Rt):<<1:sat
3265 // Rx-=mpy(Rs,Rt):<<1:sat
3266
3267 // Vector multiply bytes
3268 // Rdd=vmpybsu(Rs,Rt)
3269 // Rdd=vmpybu(Rs,Rt)
3270 // Rxx+=vmpybsu(Rs,Rt)
3271 // Rxx+=vmpybu(Rs,Rt)
3272
3273 // Vector polynomial multiply halfwords
3274 // Rdd=vpmpyh(Rs,Rt)
3275 // Rxx^=vpmpyh(Rs,Rt)
3276
3277 //===----------------------------------------------------------------------===//
3278 // XTYPE/MPY -
3279 //===----------------------------------------------------------------------===//
3280
3281
3282 //===----------------------------------------------------------------------===//
3283 // XTYPE/SHIFT +
3284 //===----------------------------------------------------------------------===//
3285
3286 // Shift by immediate and accumulate.
3287 // Rx=add(#u8,asl(Rx,#U5))
3288 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8,
3289 validSubTargets = HasV4SubT in
3290 def ADDi_ASLri_V4 : MInst_acc<(outs IntRegs:$dst),
3291             (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
3292             "$dst = add(#$src1, asl($src2, #$src3))",
3293             [(set (i32 IntRegs:$dst),
3294                   (add (shl (i32 IntRegs:$src2), u5ImmPred:$src3),
3295                        u8ExtPred:$src1))],
3296             "$src2 = $dst">,
3297             Requires<[HasV4T]>;
3298
3299 // Rx=add(#u8,lsr(Rx,#U5))
3300 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8,
3301 validSubTargets = HasV4SubT in
3302 def ADDi_LSRri_V4 : MInst_acc<(outs IntRegs:$dst),
3303             (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
3304             "$dst = add(#$src1, lsr($src2, #$src3))",
3305             [(set (i32 IntRegs:$dst),
3306                   (add (srl (i32 IntRegs:$src2), u5ImmPred:$src3),
3307                        u8ExtPred:$src1))],
3308             "$src2 = $dst">,
3309             Requires<[HasV4T]>;
3310
3311 // Rx=sub(#u8,asl(Rx,#U5))
3312 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8,
3313 validSubTargets = HasV4SubT in
3314 def SUBi_ASLri_V4 : MInst_acc<(outs IntRegs:$dst),
3315             (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
3316             "$dst = sub(#$src1, asl($src2, #$src3))",
3317             [(set (i32 IntRegs:$dst),
3318                   (sub (shl (i32 IntRegs:$src2), u5ImmPred:$src3),
3319                        u8ExtPred:$src1))],
3320             "$src2 = $dst">,
3321             Requires<[HasV4T]>;
3322
3323 // Rx=sub(#u8,lsr(Rx,#U5))
3324 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8,
3325 validSubTargets = HasV4SubT in
3326 def SUBi_LSRri_V4 : MInst_acc<(outs IntRegs:$dst),
3327             (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
3328             "$dst = sub(#$src1, lsr($src2, #$src3))",
3329             [(set (i32 IntRegs:$dst),
3330                   (sub (srl (i32 IntRegs:$src2), u5ImmPred:$src3),
3331                        u8ExtPred:$src1))],
3332             "$src2 = $dst">,
3333             Requires<[HasV4T]>;
3334
3335
3336 //Shift by immediate and logical.
3337 //Rx=and(#u8,asl(Rx,#U5))
3338 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8,
3339 validSubTargets = HasV4SubT in
3340 def ANDi_ASLri_V4 : MInst_acc<(outs IntRegs:$dst),
3341             (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
3342             "$dst = and(#$src1, asl($src2, #$src3))",
3343             [(set (i32 IntRegs:$dst),
3344                   (and (shl (i32 IntRegs:$src2), u5ImmPred:$src3),
3345                        u8ExtPred:$src1))],
3346             "$src2 = $dst">,
3347             Requires<[HasV4T]>;
3348
3349 //Rx=and(#u8,lsr(Rx,#U5))
3350 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8,
3351 validSubTargets = HasV4SubT in
3352 def ANDi_LSRri_V4 : MInst_acc<(outs IntRegs:$dst),
3353             (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
3354             "$dst = and(#$src1, lsr($src2, #$src3))",
3355             [(set (i32 IntRegs:$dst),
3356                   (and (srl (i32 IntRegs:$src2), u5ImmPred:$src3),
3357                        u8ExtPred:$src1))],
3358             "$src2 = $dst">,
3359             Requires<[HasV4T]>;
3360
3361 //Rx=or(#u8,asl(Rx,#U5))
3362 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8,
3363 AddedComplexity = 30, validSubTargets = HasV4SubT in
3364 def ORi_ASLri_V4 : MInst_acc<(outs IntRegs:$dst),
3365             (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
3366             "$dst = or(#$src1, asl($src2, #$src3))",
3367             [(set (i32 IntRegs:$dst),
3368                   (or (shl (i32 IntRegs:$src2), u5ImmPred:$src3),
3369                       u8ExtPred:$src1))],
3370             "$src2 = $dst">,
3371             Requires<[HasV4T]>;
3372
3373 //Rx=or(#u8,lsr(Rx,#U5))
3374 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8,
3375 AddedComplexity = 30, validSubTargets = HasV4SubT in
3376 def ORi_LSRri_V4 : MInst_acc<(outs IntRegs:$dst),
3377             (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
3378             "$dst = or(#$src1, lsr($src2, #$src3))",
3379             [(set (i32 IntRegs:$dst),
3380                   (or (srl (i32 IntRegs:$src2), u5ImmPred:$src3),
3381                       u8ExtPred:$src1))],
3382             "$src2 = $dst">,
3383             Requires<[HasV4T]>;
3384
3385
3386 //Shift by register.
3387 //Rd=lsl(#s6,Rt)
3388 let validSubTargets = HasV4SubT in {
3389 def LSLi_V4 : MInst<(outs IntRegs:$dst), (ins s6Imm:$src1, IntRegs:$src2),
3390             "$dst = lsl(#$src1, $src2)",
3391             [(set (i32 IntRegs:$dst), (shl s6ImmPred:$src1,
3392                                            (i32 IntRegs:$src2)))]>,
3393             Requires<[HasV4T]>;
3394
3395
3396 //Shift by register and logical.
3397 //Rxx^=asl(Rss,Rt)
3398 def ASLd_rr_xor_V4 : MInst_acc<(outs DoubleRegs:$dst),
3399             (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
3400             "$dst ^= asl($src2, $src3)",
3401             [(set (i64 DoubleRegs:$dst),
3402                   (xor (i64 DoubleRegs:$src1), (shl (i64 DoubleRegs:$src2),
3403                                                     (i32 IntRegs:$src3))))],
3404             "$src1 = $dst">,
3405             Requires<[HasV4T]>;
3406
3407 //Rxx^=asr(Rss,Rt)
3408 def ASRd_rr_xor_V4 : MInst_acc<(outs DoubleRegs:$dst),
3409             (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
3410             "$dst ^= asr($src2, $src3)",
3411             [(set (i64 DoubleRegs:$dst),
3412                   (xor (i64 DoubleRegs:$src1), (sra (i64 DoubleRegs:$src2),
3413                                                     (i32 IntRegs:$src3))))],
3414             "$src1 = $dst">,
3415             Requires<[HasV4T]>;
3416
3417 //Rxx^=lsl(Rss,Rt)
3418 def LSLd_rr_xor_V4 : MInst_acc<(outs DoubleRegs:$dst),
3419             (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
3420             "$dst ^= lsl($src2, $src3)",
3421             [(set (i64 DoubleRegs:$dst), (xor (i64 DoubleRegs:$src1),
3422                                               (shl (i64 DoubleRegs:$src2),
3423                                                    (i32 IntRegs:$src3))))],
3424             "$src1 = $dst">,
3425             Requires<[HasV4T]>;
3426
3427 //Rxx^=lsr(Rss,Rt)
3428 def LSRd_rr_xor_V4 : MInst_acc<(outs DoubleRegs:$dst),
3429             (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
3430             "$dst ^= lsr($src2, $src3)",
3431             [(set (i64 DoubleRegs:$dst),
3432                   (xor (i64 DoubleRegs:$src1), (srl (i64 DoubleRegs:$src2),
3433                                                     (i32 IntRegs:$src3))))],
3434             "$src1 = $dst">,
3435             Requires<[HasV4T]>;
3436 }
3437
3438 //===----------------------------------------------------------------------===//
3439 // XTYPE/SHIFT -
3440 //===----------------------------------------------------------------------===//
3441
3442 //===----------------------------------------------------------------------===//
3443 // MEMOP: Word, Half, Byte
3444 //===----------------------------------------------------------------------===//
3445
3446 //===----------------------------------------------------------------------===//
3447 // MEMOP: Word
3448 //
3449 //  Implemented:
3450 //     MEMw_ADDi_indexed_V4  : memw(Rs+#u6:2)+=#U5
3451 //     MEMw_SUBi_indexed_V4  : memw(Rs+#u6:2)-=#U5
3452 //     MEMw_ADDr_indexed_V4  : memw(Rs+#u6:2)+=Rt
3453 //     MEMw_SUBr_indexed_V4  : memw(Rs+#u6:2)-=Rt
3454 //     MEMw_CLRr_indexed_V4  : memw(Rs+#u6:2)&=Rt
3455 //     MEMw_SETr_indexed_V4  : memw(Rs+#u6:2)|=Rt
3456 //     MEMw_ADDi_V4          : memw(Rs+#u6:2)+=#U5
3457 //     MEMw_SUBi_V4          : memw(Rs+#u6:2)-=#U5
3458 //     MEMw_ADDr_V4          : memw(Rs+#u6:2)+=Rt
3459 //     MEMw_SUBr_V4          : memw(Rs+#u6:2)-=Rt
3460 //     MEMw_CLRr_V4          : memw(Rs+#u6:2)&=Rt
3461 //     MEMw_SETr_V4          : memw(Rs+#u6:2)|=Rt
3462 //
3463 //   Not implemented:
3464 //     MEMw_CLRi_indexed_V4  : memw(Rs+#u6:2)=clrbit(#U5)
3465 //     MEMw_SETi_indexed_V4  : memw(Rs+#u6:2)=setbit(#U5)
3466 //     MEMw_CLRi_V4          : memw(Rs+#u6:2)=clrbit(#U5)
3467 //     MEMw_SETi_V4          : memw(Rs+#u6:2)=setbit(#U5)
3468 //===----------------------------------------------------------------------===//
3469
3470
3471
3472 // memw(Rs+#u6:2) += #U5
3473 let AddedComplexity = 30 in
3474 def MEMw_ADDi_indexed_MEM_V4 : MEMInst_V4<(outs),
3475             (ins IntRegs:$base, u6_2Imm:$offset, u5Imm:$addend),
3476             "memw($base+#$offset) += #$addend",
3477             []>,
3478             Requires<[HasV4T, UseMEMOP]>;
3479
3480 // memw(Rs+#u6:2) -= #U5
3481 let AddedComplexity = 30 in
3482 def MEMw_SUBi_indexed_MEM_V4 : MEMInst_V4<(outs),
3483             (ins IntRegs:$base, u6_2Imm:$offset, u5Imm:$subend),
3484             "memw($base+#$offset) -= #$subend",
3485             []>,
3486             Requires<[HasV4T, UseMEMOP]>;
3487
3488 // memw(Rs+#u6:2) += Rt
3489 let AddedComplexity = 30 in
3490 def MEMw_ADDr_indexed_MEM_V4 : MEMInst_V4<(outs),
3491             (ins IntRegs:$base, u6_2Imm:$offset, IntRegs:$addend),
3492             "memw($base+#$offset) += $addend",
3493             [(store (add (load (add (i32 IntRegs:$base), u6_2ImmPred:$offset)),
3494                          (i32 IntRegs:$addend)),
3495                     (add (i32 IntRegs:$base), u6_2ImmPred:$offset))]>,
3496             Requires<[HasV4T, UseMEMOP]>;
3497
3498 // memw(Rs+#u6:2) -= Rt
3499 let AddedComplexity = 30 in
3500 def MEMw_SUBr_indexed_MEM_V4 : MEMInst_V4<(outs),
3501             (ins IntRegs:$base, u6_2Imm:$offset, IntRegs:$subend),
3502             "memw($base+#$offset) -= $subend",
3503             [(store (sub (load (add (i32 IntRegs:$base), u6_2ImmPred:$offset)),
3504                          (i32 IntRegs:$subend)),
3505                     (add (i32 IntRegs:$base), u6_2ImmPred:$offset))]>,
3506             Requires<[HasV4T, UseMEMOP]>;
3507
3508 // memw(Rs+#u6:2) &= Rt
3509 let AddedComplexity = 30 in
3510 def MEMw_ANDr_indexed_MEM_V4 : MEMInst_V4<(outs),
3511             (ins IntRegs:$base, u6_2Imm:$offset, IntRegs:$andend),
3512             "memw($base+#$offset) &= $andend",
3513             [(store (and (load (add (i32 IntRegs:$base), u6_2ImmPred:$offset)),
3514                          (i32 IntRegs:$andend)),
3515                     (add (i32 IntRegs:$base), u6_2ImmPred:$offset))]>,
3516             Requires<[HasV4T, UseMEMOP]>;
3517
3518 // memw(Rs+#u6:2) |= Rt
3519 let AddedComplexity = 30 in
3520 def MEMw_ORr_indexed_MEM_V4 : MEMInst_V4<(outs),
3521             (ins IntRegs:$base, u6_2Imm:$offset, IntRegs:$orend),
3522             "memw($base+#$offset) |= $orend",
3523             [(store (or (load (add (i32 IntRegs:$base), u6_2ImmPred:$offset)),
3524                         (i32 IntRegs:$orend)),
3525                     (add (i32 IntRegs:$base), u6_2ImmPred:$offset))]>,
3526             Requires<[HasV4T, UseMEMOP]>;
3527
3528 // memw(Rs+#u6:2) += #U5
3529 let AddedComplexity = 30 in
3530 def MEMw_ADDi_MEM_V4 : MEMInst_V4<(outs),
3531             (ins MEMri:$addr, u5Imm:$addend),
3532             "memw($addr) += $addend",
3533             []>,
3534             Requires<[HasV4T, UseMEMOP]>;
3535
3536 // memw(Rs+#u6:2) -= #U5
3537 let AddedComplexity = 30 in
3538 def MEMw_SUBi_MEM_V4 : MEMInst_V4<(outs),
3539             (ins MEMri:$addr, u5Imm:$subend),
3540             "memw($addr) -= $subend",
3541             []>,
3542             Requires<[HasV4T, UseMEMOP]>;
3543
3544 // memw(Rs+#u6:2) += Rt
3545 let AddedComplexity = 30 in
3546 def MEMw_ADDr_MEM_V4 : MEMInst_V4<(outs),
3547             (ins MEMri:$addr, IntRegs:$addend),
3548             "memw($addr) += $addend",
3549             [(store (add (load ADDRriU6_2:$addr), (i32 IntRegs:$addend)),
3550                     ADDRriU6_2:$addr)]>,
3551             Requires<[HasV4T, UseMEMOP]>;
3552
3553 // memw(Rs+#u6:2) -= Rt
3554 let AddedComplexity = 30 in
3555 def MEMw_SUBr_MEM_V4 : MEMInst_V4<(outs),
3556             (ins MEMri:$addr, IntRegs:$subend),
3557             "memw($addr) -= $subend",
3558             [(store (sub (load ADDRriU6_2:$addr), (i32 IntRegs:$subend)),
3559                     ADDRriU6_2:$addr)]>,
3560             Requires<[HasV4T, UseMEMOP]>;
3561
3562 // memw(Rs+#u6:2) &= Rt
3563 let AddedComplexity = 30 in
3564 def MEMw_ANDr_MEM_V4 : MEMInst_V4<(outs),
3565             (ins MEMri:$addr, IntRegs:$andend),
3566             "memw($addr) &= $andend",
3567             [(store (and (load ADDRriU6_2:$addr), (i32 IntRegs:$andend)),
3568                     ADDRriU6_2:$addr)]>,
3569             Requires<[HasV4T, UseMEMOP]>;
3570
3571 // memw(Rs+#u6:2) |= Rt
3572 let AddedComplexity = 30 in
3573 def MEMw_ORr_MEM_V4 : MEMInst_V4<(outs),
3574             (ins MEMri:$addr, IntRegs:$orend),
3575             "memw($addr) |= $orend",
3576             [(store (or (load ADDRriU6_2:$addr), (i32 IntRegs:$orend)),
3577                     ADDRriU6_2:$addr)]>,
3578             Requires<[HasV4T, UseMEMOP]>;
3579
3580 //===----------------------------------------------------------------------===//
3581 // MEMOP: Halfword
3582 //
3583 //  Implemented:
3584 //     MEMh_ADDi_indexed_V4  : memw(Rs+#u6:2)+=#U5
3585 //     MEMh_SUBi_indexed_V4  : memw(Rs+#u6:2)-=#U5
3586 //     MEMh_ADDr_indexed_V4  : memw(Rs+#u6:2)+=Rt
3587 //     MEMh_SUBr_indexed_V4  : memw(Rs+#u6:2)-=Rt
3588 //     MEMh_CLRr_indexed_V4  : memw(Rs+#u6:2)&=Rt
3589 //     MEMh_SETr_indexed_V4  : memw(Rs+#u6:2)|=Rt
3590 //     MEMh_ADDi_V4          : memw(Rs+#u6:2)+=#U5
3591 //     MEMh_SUBi_V4          : memw(Rs+#u6:2)-=#U5
3592 //     MEMh_ADDr_V4          : memw(Rs+#u6:2)+=Rt
3593 //     MEMh_SUBr_V4          : memw(Rs+#u6:2)-=Rt
3594 //     MEMh_CLRr_V4          : memw(Rs+#u6:2)&=Rt
3595 //     MEMh_SETr_V4          : memw(Rs+#u6:2)|=Rt
3596 //
3597 //   Not implemented:
3598 //     MEMh_CLRi_indexed_V4  : memw(Rs+#u6:2)=clrbit(#U5)
3599 //     MEMh_SETi_indexed_V4  : memw(Rs+#u6:2)=setbit(#U5)
3600 //     MEMh_CLRi_V4          : memw(Rs+#u6:2)=clrbit(#U5)
3601 //     MEMh_SETi_V4          : memw(Rs+#u6:2)=setbit(#U5)
3602 //===----------------------------------------------------------------------===//
3603
3604
3605 // memh(Rs+#u6:1) += #U5
3606 let AddedComplexity = 30 in
3607 def MEMh_ADDi_indexed_MEM_V4 : MEMInst_V4<(outs),
3608             (ins IntRegs:$base, u6_1Imm:$offset, u5Imm:$addend),
3609             "memh($base+#$offset) += $addend",
3610             []>,
3611             Requires<[HasV4T, UseMEMOP]>;
3612
3613 // memh(Rs+#u6:1) -= #U5
3614 let AddedComplexity = 30 in
3615 def MEMh_SUBi_indexed_MEM_V4 : MEMInst_V4<(outs),
3616             (ins IntRegs:$base, u6_1Imm:$offset, u5Imm:$subend),
3617             "memh($base+#$offset) -= $subend",
3618             []>,
3619             Requires<[HasV4T, UseMEMOP]>;
3620
3621 // memh(Rs+#u6:1) += Rt
3622 let AddedComplexity = 30 in
3623 def MEMh_ADDr_indexed_MEM_V4 : MEMInst_V4<(outs),
3624             (ins IntRegs:$base, u6_1Imm:$offset, IntRegs:$addend),
3625             "memh($base+#$offset) += $addend",
3626             [(truncstorei16 (add (sextloadi16 (add (i32 IntRegs:$base),
3627                                                    u6_1ImmPred:$offset)),
3628                                  (i32 IntRegs:$addend)),
3629                             (add (i32 IntRegs:$base), u6_1ImmPred:$offset))]>,
3630             Requires<[HasV4T, UseMEMOP]>;
3631
3632 // memh(Rs+#u6:1) -= Rt
3633 let AddedComplexity = 30 in
3634 def MEMh_SUBr_indexed_MEM_V4 : MEMInst_V4<(outs),
3635             (ins IntRegs:$base, u6_1Imm:$offset, IntRegs:$subend),
3636             "memh($base+#$offset) -= $subend",
3637             [(truncstorei16 (sub (sextloadi16 (add (i32 IntRegs:$base),
3638                                                    u6_1ImmPred:$offset)),
3639                                  (i32 IntRegs:$subend)),
3640                             (add (i32 IntRegs:$base), u6_1ImmPred:$offset))]>,
3641             Requires<[HasV4T, UseMEMOP]>;
3642
3643 // memh(Rs+#u6:1) &= Rt
3644 let AddedComplexity = 30 in
3645 def MEMh_ANDr_indexed_MEM_V4 : MEMInst_V4<(outs),
3646             (ins IntRegs:$base, u6_1Imm:$offset, IntRegs:$andend),
3647             "memh($base+#$offset) += $andend",
3648             [(truncstorei16 (and (sextloadi16 (add (i32 IntRegs:$base),
3649                                                    u6_1ImmPred:$offset)),
3650                                  (i32 IntRegs:$andend)),
3651                             (add (i32 IntRegs:$base), u6_1ImmPred:$offset))]>,
3652             Requires<[HasV4T, UseMEMOP]>;
3653
3654 // memh(Rs+#u6:1) |= Rt
3655 let AddedComplexity = 30 in
3656 def MEMh_ORr_indexed_MEM_V4 : MEMInst_V4<(outs),
3657             (ins IntRegs:$base, u6_1Imm:$offset, IntRegs:$orend),
3658             "memh($base+#$offset) |= $orend",
3659             [(truncstorei16 (or (sextloadi16 (add (i32 IntRegs:$base),
3660                                               u6_1ImmPred:$offset)),
3661                              (i32 IntRegs:$orend)),
3662                             (add (i32 IntRegs:$base), u6_1ImmPred:$offset))]>,
3663             Requires<[HasV4T, UseMEMOP]>;
3664
3665 // memh(Rs+#u6:1) += #U5
3666 let AddedComplexity = 30 in
3667 def MEMh_ADDi_MEM_V4 : MEMInst_V4<(outs),
3668             (ins MEMri:$addr, u5Imm:$addend),
3669             "memh($addr) += $addend",
3670             []>,
3671             Requires<[HasV4T, UseMEMOP]>;
3672
3673 // memh(Rs+#u6:1) -= #U5
3674 let AddedComplexity = 30 in
3675 def MEMh_SUBi_MEM_V4 : MEMInst_V4<(outs),
3676             (ins MEMri:$addr, u5Imm:$subend),
3677             "memh($addr) -= $subend",
3678             []>,
3679             Requires<[HasV4T, UseMEMOP]>;
3680
3681 // memh(Rs+#u6:1) += Rt
3682 let AddedComplexity = 30 in
3683 def MEMh_ADDr_MEM_V4 : MEMInst_V4<(outs),
3684             (ins MEMri:$addr, IntRegs:$addend),
3685             "memh($addr) += $addend",
3686             [(truncstorei16 (add (sextloadi16 ADDRriU6_1:$addr),
3687                                  (i32 IntRegs:$addend)), ADDRriU6_1:$addr)]>,
3688             Requires<[HasV4T, UseMEMOP]>;
3689
3690 // memh(Rs+#u6:1) -= Rt
3691 let AddedComplexity = 30 in
3692 def MEMh_SUBr_MEM_V4 : MEMInst_V4<(outs),
3693             (ins MEMri:$addr, IntRegs:$subend),
3694             "memh($addr) -= $subend",
3695             [(truncstorei16 (sub (sextloadi16 ADDRriU6_1:$addr),
3696                                  (i32 IntRegs:$subend)), ADDRriU6_1:$addr)]>,
3697             Requires<[HasV4T, UseMEMOP]>;
3698
3699 // memh(Rs+#u6:1) &= Rt
3700 let AddedComplexity = 30 in
3701 def MEMh_ANDr_MEM_V4 : MEMInst_V4<(outs),
3702             (ins MEMri:$addr, IntRegs:$andend),
3703             "memh($addr) &= $andend",
3704             [(truncstorei16 (and (sextloadi16 ADDRriU6_1:$addr),
3705                                  (i32 IntRegs:$andend)), ADDRriU6_1:$addr)]>,
3706             Requires<[HasV4T, UseMEMOP]>;
3707
3708 // memh(Rs+#u6:1) |= Rt
3709 let AddedComplexity = 30 in
3710 def MEMh_ORr_MEM_V4 : MEMInst_V4<(outs),
3711             (ins MEMri:$addr, IntRegs:$orend),
3712             "memh($addr) |= $orend",
3713             [(truncstorei16 (or (sextloadi16 ADDRriU6_1:$addr),
3714                                 (i32 IntRegs:$orend)), ADDRriU6_1:$addr)]>,
3715             Requires<[HasV4T, UseMEMOP]>;
3716
3717
3718 //===----------------------------------------------------------------------===//
3719 // MEMOP: Byte
3720 //
3721 //  Implemented:
3722 //     MEMb_ADDi_indexed_V4  : memb(Rs+#u6:0)+=#U5
3723 //     MEMb_SUBi_indexed_V4  : memb(Rs+#u6:0)-=#U5
3724 //     MEMb_ADDr_indexed_V4  : memb(Rs+#u6:0)+=Rt
3725 //     MEMb_SUBr_indexed_V4  : memb(Rs+#u6:0)-=Rt
3726 //     MEMb_CLRr_indexed_V4  : memb(Rs+#u6:0)&=Rt
3727 //     MEMb_SETr_indexed_V4  : memb(Rs+#u6:0)|=Rt
3728 //     MEMb_ADDi_V4          : memb(Rs+#u6:0)+=#U5
3729 //     MEMb_SUBi_V4          : memb(Rs+#u6:0)-=#U5
3730 //     MEMb_ADDr_V4          : memb(Rs+#u6:0)+=Rt
3731 //     MEMb_SUBr_V4          : memb(Rs+#u6:0)-=Rt
3732 //     MEMb_CLRr_V4          : memb(Rs+#u6:0)&=Rt
3733 //     MEMb_SETr_V4          : memb(Rs+#u6:0)|=Rt
3734 //
3735 //   Not implemented:
3736 //     MEMb_CLRi_indexed_V4  : memb(Rs+#u6:0)=clrbit(#U5)
3737 //     MEMb_SETi_indexed_V4  : memb(Rs+#u6:0)=setbit(#U5)
3738 //     MEMb_CLRi_V4          : memb(Rs+#u6:0)=clrbit(#U5)
3739 //     MEMb_SETi_V4          : memb(Rs+#u6:0)=setbit(#U5)
3740 //===----------------------------------------------------------------------===//
3741
3742 // memb(Rs+#u6:0) += #U5
3743 let AddedComplexity = 30 in
3744 def MEMb_ADDi_indexed_MEM_V4 : MEMInst_V4<(outs),
3745             (ins IntRegs:$base, u6_0Imm:$offset, u5Imm:$addend),
3746             "memb($base+#$offset) += $addend",
3747             []>,
3748             Requires<[HasV4T, UseMEMOP]>;
3749
3750 // memb(Rs+#u6:0) -= #U5
3751 let AddedComplexity = 30 in
3752 def MEMb_SUBi_indexed_MEM_V4 : MEMInst_V4<(outs),
3753             (ins IntRegs:$base, u6_0Imm:$offset, u5Imm:$subend),
3754             "memb($base+#$offset) -= $subend",
3755             []>,
3756             Requires<[HasV4T, UseMEMOP]>;
3757
3758 // memb(Rs+#u6:0) += Rt
3759 let AddedComplexity = 30 in
3760 def MEMb_ADDr_indexed_MEM_V4 : MEMInst_V4<(outs),
3761             (ins IntRegs:$base, u6_0Imm:$offset, IntRegs:$addend),
3762             "memb($base+#$offset) += $addend",
3763             [(truncstorei8 (add (sextloadi8 (add (i32 IntRegs:$base),
3764                                                  u6_0ImmPred:$offset)),
3765                                 (i32 IntRegs:$addend)),
3766                            (add (i32 IntRegs:$base), u6_0ImmPred:$offset))]>,
3767             Requires<[HasV4T, UseMEMOP]>;
3768
3769 // memb(Rs+#u6:0) -= Rt
3770 let AddedComplexity = 30 in
3771 def MEMb_SUBr_indexed_MEM_V4 : MEMInst_V4<(outs),
3772             (ins IntRegs:$base, u6_0Imm:$offset, IntRegs:$subend),
3773             "memb($base+#$offset) -= $subend",
3774             [(truncstorei8 (sub (sextloadi8 (add (i32 IntRegs:$base),
3775                                                  u6_0ImmPred:$offset)),
3776                                 (i32 IntRegs:$subend)),
3777                            (add (i32 IntRegs:$base), u6_0ImmPred:$offset))]>,
3778             Requires<[HasV4T, UseMEMOP]>;
3779
3780 // memb(Rs+#u6:0) &= Rt
3781 let AddedComplexity = 30 in
3782 def MEMb_ANDr_indexed_MEM_V4 : MEMInst_V4<(outs),
3783             (ins IntRegs:$base, u6_0Imm:$offset, IntRegs:$andend),
3784             "memb($base+#$offset) += $andend",
3785             [(truncstorei8 (and (sextloadi8 (add (i32 IntRegs:$base),
3786                                                  u6_0ImmPred:$offset)),
3787                                 (i32 IntRegs:$andend)),
3788                            (add (i32 IntRegs:$base), u6_0ImmPred:$offset))]>,
3789             Requires<[HasV4T, UseMEMOP]>;
3790
3791 // memb(Rs+#u6:0) |= Rt
3792 let AddedComplexity = 30 in
3793 def MEMb_ORr_indexed_MEM_V4 : MEMInst_V4<(outs),
3794             (ins IntRegs:$base, u6_0Imm:$offset, IntRegs:$orend),
3795             "memb($base+#$offset) |= $orend",
3796             [(truncstorei8 (or (sextloadi8 (add (i32 IntRegs:$base),
3797                                                 u6_0ImmPred:$offset)),
3798                                (i32 IntRegs:$orend)),
3799                            (add (i32 IntRegs:$base), u6_0ImmPred:$offset))]>,
3800             Requires<[HasV4T, UseMEMOP]>;
3801
3802 // memb(Rs+#u6:0) += #U5
3803 let AddedComplexity = 30 in
3804 def MEMb_ADDi_MEM_V4 : MEMInst_V4<(outs),
3805             (ins MEMri:$addr, u5Imm:$addend),
3806             "memb($addr) += $addend",
3807             []>,
3808             Requires<[HasV4T, UseMEMOP]>;
3809
3810 // memb(Rs+#u6:0) -= #U5
3811 let AddedComplexity = 30 in
3812 def MEMb_SUBi_MEM_V4 : MEMInst_V4<(outs),
3813             (ins MEMri:$addr, u5Imm:$subend),
3814             "memb($addr) -= $subend",
3815             []>,
3816             Requires<[HasV4T, UseMEMOP]>;
3817
3818 // memb(Rs+#u6:0) += Rt
3819 let AddedComplexity = 30 in
3820 def MEMb_ADDr_MEM_V4 : MEMInst_V4<(outs),
3821             (ins MEMri:$addr, IntRegs:$addend),
3822             "memb($addr) += $addend",
3823             [(truncstorei8 (add (sextloadi8 ADDRriU6_0:$addr),
3824                                 (i32 IntRegs:$addend)), ADDRriU6_0:$addr)]>,
3825             Requires<[HasV4T, UseMEMOP]>;
3826
3827 // memb(Rs+#u6:0) -= Rt
3828 let AddedComplexity = 30 in
3829 def MEMb_SUBr_MEM_V4 : MEMInst_V4<(outs),
3830             (ins MEMri:$addr, IntRegs:$subend),
3831             "memb($addr) -= $subend",
3832             [(truncstorei8 (sub (sextloadi8 ADDRriU6_0:$addr),
3833                                 (i32 IntRegs:$subend)), ADDRriU6_0:$addr)]>,
3834             Requires<[HasV4T, UseMEMOP]>;
3835
3836 // memb(Rs+#u6:0) &= Rt
3837 let AddedComplexity = 30 in
3838 def MEMb_ANDr_MEM_V4 : MEMInst_V4<(outs),
3839             (ins MEMri:$addr, IntRegs:$andend),
3840             "memb($addr) &= $andend",
3841             [(truncstorei8 (and (sextloadi8 ADDRriU6_0:$addr),
3842                                 (i32 IntRegs:$andend)), ADDRriU6_0:$addr)]>,
3843             Requires<[HasV4T, UseMEMOP]>;
3844
3845 // memb(Rs+#u6:0) |= Rt
3846 let AddedComplexity = 30 in
3847 def MEMb_ORr_MEM_V4 : MEMInst_V4<(outs),
3848             (ins MEMri:$addr, IntRegs:$orend),
3849             "memb($addr) |= $orend",
3850             [(truncstorei8 (or (sextloadi8 ADDRriU6_0:$addr),
3851                                (i32 IntRegs:$orend)), ADDRriU6_0:$addr)]>,
3852             Requires<[HasV4T, UseMEMOP]>;
3853
3854
3855 //===----------------------------------------------------------------------===//
3856 // XTYPE/PRED +
3857 //===----------------------------------------------------------------------===//
3858
3859 // Hexagon V4 only supports these flavors of byte/half compare instructions:
3860 // EQ/GT/GTU. Other flavors like GE/GEU/LT/LTU/LE/LEU are not supported by
3861 // hardware. However, compiler can still implement these patterns through
3862 // appropriate patterns combinations based on current implemented patterns.
3863 // The implemented patterns are: EQ/GT/GTU.
3864 // Missing patterns are: GE/GEU/LT/LTU/LE/LEU.
3865
3866 // Following instruction is not being extended as it results into the
3867 // incorrect code for negative numbers.
3868 // Pd=cmpb.eq(Rs,#u8)
3869
3870 let isCompare = 1 in
3871 def CMPbEQri_V4 : MInst<(outs PredRegs:$dst),
3872             (ins IntRegs:$src1, u8Imm:$src2),
3873             "$dst = cmpb.eq($src1, #$src2)",
3874             [(set (i1 PredRegs:$dst),
3875                   (seteq (and (i32 IntRegs:$src1), 255), u8ImmPred:$src2))]>,
3876             Requires<[HasV4T]>;
3877
3878 // Pd=cmpb.eq(Rs,Rt)
3879 let isCompare = 1, validSubTargets = HasV4SubT in
3880 def CMPbEQrr_ubub_V4 : MInst<(outs PredRegs:$dst),
3881             (ins IntRegs:$src1, IntRegs:$src2),
3882             "$dst = cmpb.eq($src1, $src2)",
3883             [(set (i1 PredRegs:$dst),
3884                   (seteq (and (xor (i32 IntRegs:$src1),
3885                                    (i32 IntRegs:$src2)), 255), 0))]>,
3886             Requires<[HasV4T]>;
3887
3888 // Pd=cmpb.eq(Rs,Rt)
3889 let isCompare = 1, validSubTargets = HasV4SubT in
3890 def CMPbEQrr_sbsb_V4 : MInst<(outs PredRegs:$dst),
3891             (ins IntRegs:$src1, IntRegs:$src2),
3892             "$dst = cmpb.eq($src1, $src2)",
3893             [(set (i1 PredRegs:$dst),
3894                   (seteq (shl (i32 IntRegs:$src1), (i32 24)),
3895                          (shl (i32 IntRegs:$src2), (i32 24))))]>,
3896             Requires<[HasV4T]>;
3897
3898 // Pd=cmpb.gt(Rs,Rt)
3899 let isCompare = 1, validSubTargets = HasV4SubT in
3900 def CMPbGTrr_V4 : MInst<(outs PredRegs:$dst),
3901             (ins IntRegs:$src1, IntRegs:$src2),
3902             "$dst = cmpb.gt($src1, $src2)",
3903             [(set (i1 PredRegs:$dst),
3904                   (setgt (shl (i32 IntRegs:$src1), (i32 24)),
3905                          (shl (i32 IntRegs:$src2), (i32 24))))]>,
3906             Requires<[HasV4T]>;
3907
3908 // Pd=cmpb.gtu(Rs,#u7)
3909 let isExtendable = 1, opExtendable = 2, isExtentSigned = 0, opExtentBits = 7,
3910 isCompare = 1, validSubTargets = HasV4SubT, CextOpcode = "CMPbGTU", InputType = "imm" in
3911 def CMPbGTUri_V4 : MInst<(outs PredRegs:$dst),
3912             (ins IntRegs:$src1, u7Ext:$src2),
3913             "$dst = cmpb.gtu($src1, #$src2)",
3914             [(set (i1 PredRegs:$dst), (setugt (and (i32 IntRegs:$src1), 255),
3915                                               u7ExtPred:$src2))]>,
3916             Requires<[HasV4T]>, ImmRegRel;
3917
3918 // Pd=cmpb.gtu(Rs,Rt)
3919 let isCompare = 1 in
3920 def CMPbGTUrr_V4 : MInst<(outs PredRegs:$dst),
3921             (ins IntRegs:$src1, IntRegs:$src2),
3922             "$dst = cmpb.gtu($src1, $src2)",
3923             [(set (i1 PredRegs:$dst), (setugt (and (i32 IntRegs:$src1), 255),
3924                                              (and (i32 IntRegs:$src2), 255)))]>,
3925             Requires<[HasV4T]>;
3926
3927 // Following instruction is not being extended as it results into the incorrect
3928 // code for negative numbers.
3929
3930 // Signed half compare(.eq) ri.
3931 // Pd=cmph.eq(Rs,#s8)
3932 let isCompare = 1 in
3933 def CMPhEQri_V4 : MInst<(outs PredRegs:$dst),
3934             (ins IntRegs:$src1, s8Imm:$src2),
3935             "$dst = cmph.eq($src1, #$src2)",
3936             [(set (i1 PredRegs:$dst), (seteq (and (i32 IntRegs:$src1), 65535),
3937                                              s8ImmPred:$src2))]>,
3938             Requires<[HasV4T]>;
3939
3940 // Signed half compare(.eq) rr.
3941 // Case 1: xor + and, then compare:
3942 //   r0=xor(r0,r1)
3943 //   r0=and(r0,#0xffff)
3944 //   p0=cmp.eq(r0,#0)
3945 // Pd=cmph.eq(Rs,Rt)
3946 let isCompare = 1 in
3947 def CMPhEQrr_xor_V4 : MInst<(outs PredRegs:$dst),
3948             (ins IntRegs:$src1, IntRegs:$src2),
3949             "$dst = cmph.eq($src1, $src2)",
3950             [(set (i1 PredRegs:$dst), (seteq (and (xor (i32 IntRegs:$src1),
3951                                                        (i32 IntRegs:$src2)),
3952                                                   65535), 0))]>,
3953             Requires<[HasV4T]>;
3954
3955 // Signed half compare(.eq) rr.
3956 // Case 2: shift left 16 bits then compare:
3957 //   r0=asl(r0,16)
3958 //   r1=asl(r1,16)
3959 //   p0=cmp.eq(r0,r1)
3960 // Pd=cmph.eq(Rs,Rt)
3961 let isCompare = 1 in
3962 def CMPhEQrr_shl_V4 : MInst<(outs PredRegs:$dst),
3963             (ins IntRegs:$src1, IntRegs:$src2),
3964             "$dst = cmph.eq($src1, $src2)",
3965             [(set (i1 PredRegs:$dst),
3966                   (seteq (shl (i32 IntRegs:$src1), (i32 16)),
3967                          (shl (i32 IntRegs:$src2), (i32 16))))]>,
3968             Requires<[HasV4T]>;
3969
3970 /* Incorrect Pattern -- immediate should be right shifted before being
3971 used in the cmph.gt instruction.
3972 // Signed half compare(.gt) ri.
3973 // Pd=cmph.gt(Rs,#s8)
3974
3975 let isCompare = 1 in
3976 def CMPhGTri_V4 : MInst<(outs PredRegs:$dst),
3977             (ins IntRegs:$src1, s8Imm:$src2),
3978             "$dst = cmph.gt($src1, #$src2)",
3979             [(set (i1 PredRegs:$dst),
3980                   (setgt (shl (i32 IntRegs:$src1), (i32 16)),
3981                          s8ImmPred:$src2))]>,
3982             Requires<[HasV4T]>;
3983 */
3984
3985 // Signed half compare(.gt) rr.
3986 // Pd=cmph.gt(Rs,Rt)
3987 let isCompare = 1 in
3988 def CMPhGTrr_shl_V4 : MInst<(outs PredRegs:$dst),
3989             (ins IntRegs:$src1, IntRegs:$src2),
3990             "$dst = cmph.gt($src1, $src2)",
3991             [(set (i1 PredRegs:$dst),
3992                   (setgt (shl (i32 IntRegs:$src1), (i32 16)),
3993                          (shl (i32 IntRegs:$src2), (i32 16))))]>,
3994             Requires<[HasV4T]>;
3995
3996 // Unsigned half compare rr (.gtu).
3997 // Pd=cmph.gtu(Rs,Rt)
3998 let isCompare = 1 in
3999 def CMPhGTUrr_V4 : MInst<(outs PredRegs:$dst),
4000             (ins IntRegs:$src1, IntRegs:$src2),
4001             "$dst = cmph.gtu($src1, $src2)",
4002             [(set (i1 PredRegs:$dst),
4003                   (setugt (and (i32 IntRegs:$src1), 65535),
4004                           (and (i32 IntRegs:$src2), 65535)))]>,
4005             Requires<[HasV4T]>;
4006
4007 // Unsigned half compare ri (.gtu).
4008 // Pd=cmph.gtu(Rs,#u7)
4009 let isCompare = 1 in
4010 def CMPhGTUri_V4 : MInst<(outs PredRegs:$dst),
4011             (ins IntRegs:$src1, u7Imm:$src2),
4012             "$dst = cmph.gtu($src1, #$src2)",
4013             [(set (i1 PredRegs:$dst), (setugt (and (i32 IntRegs:$src1), 65535),
4014                                               u7ImmPred:$src2))]>,
4015             Requires<[HasV4T]>;
4016
4017 //===----------------------------------------------------------------------===//
4018 // XTYPE/PRED -
4019 //===----------------------------------------------------------------------===//
4020
4021 //Deallocate frame and return.
4022 //    dealloc_return
4023 let isReturn = 1, isTerminator = 1, isBarrier = 1, isPredicable = 1,
4024   Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1 in {
4025   def DEALLOC_RET_V4 : NVInst_V4<(outs), (ins i32imm:$amt1),
4026             "dealloc_return",
4027             []>,
4028             Requires<[HasV4T]>;
4029 }
4030
4031 // Restore registers and dealloc return function call.
4032 let isCall = 1, isBarrier = 1, isReturn = 1, isTerminator = 1,
4033   Defs = [R29, R30, R31, PC] in {
4034   def RESTORE_DEALLOC_RET_JMP_V4 : JInst<(outs),
4035                                    (ins calltarget:$dst),
4036              "jump $dst // Restore_and_dealloc_return",
4037              []>,
4038              Requires<[HasV4T]>;
4039 }
4040
4041 // Restore registers and dealloc frame before a tail call.
4042 let isCall = 1, isBarrier = 1,
4043   Defs = [R29, R30, R31, PC] in {
4044   def RESTORE_DEALLOC_BEFORE_TAILCALL_V4 : JInst<(outs),
4045                                            (ins calltarget:$dst),
4046              "call $dst // Restore_and_dealloc_before_tailcall",
4047              []>,
4048              Requires<[HasV4T]>;
4049 }
4050
4051 // Save registers function call.
4052 let isCall = 1, isBarrier = 1,
4053   Uses = [R29, R31] in {
4054   def SAVE_REGISTERS_CALL_V4 : JInst<(outs),
4055                                (ins calltarget:$dst),
4056              "call $dst // Save_calle_saved_registers",
4057              []>,
4058              Requires<[HasV4T]>;
4059 }
4060
4061 //    if (Ps) dealloc_return
4062 let isReturn = 1, isTerminator = 1,
4063     Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1,
4064     isPredicated = 1 in {
4065   def DEALLOC_RET_cPt_V4 : NVInst_V4<(outs),
4066                            (ins PredRegs:$src1, i32imm:$amt1),
4067             "if ($src1) dealloc_return",
4068             []>,
4069             Requires<[HasV4T]>;
4070 }
4071
4072 //    if (!Ps) dealloc_return
4073 let isReturn = 1, isTerminator = 1,
4074     Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1,
4075     isPredicated = 1 in {
4076   def DEALLOC_RET_cNotPt_V4 : NVInst_V4<(outs), (ins PredRegs:$src1,
4077                                                      i32imm:$amt1),
4078             "if (!$src1) dealloc_return",
4079             []>,
4080             Requires<[HasV4T]>;
4081 }
4082
4083 //    if (Ps.new) dealloc_return:nt
4084 let isReturn = 1, isTerminator = 1,
4085     Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1,
4086     isPredicated = 1 in {
4087   def DEALLOC_RET_cdnPnt_V4 : NVInst_V4<(outs), (ins PredRegs:$src1,
4088                                                      i32imm:$amt1),
4089             "if ($src1.new) dealloc_return:nt",
4090             []>,
4091             Requires<[HasV4T]>;
4092 }
4093
4094 //    if (!Ps.new) dealloc_return:nt
4095 let isReturn = 1, isTerminator = 1,
4096     Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1,
4097     isPredicated = 1 in {
4098   def DEALLOC_RET_cNotdnPnt_V4 : NVInst_V4<(outs), (ins PredRegs:$src1,
4099                                                         i32imm:$amt1),
4100             "if (!$src1.new) dealloc_return:nt",
4101             []>,
4102             Requires<[HasV4T]>;
4103 }
4104
4105 //    if (Ps.new) dealloc_return:t
4106 let isReturn = 1, isTerminator = 1,
4107     Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1,
4108     isPredicated = 1 in {
4109   def DEALLOC_RET_cdnPt_V4 : NVInst_V4<(outs), (ins PredRegs:$src1,
4110                                                     i32imm:$amt1),
4111             "if ($src1.new) dealloc_return:t",
4112             []>,
4113             Requires<[HasV4T]>;
4114 }
4115
4116 //    if (!Ps.new) dealloc_return:nt
4117 let isReturn = 1, isTerminator = 1,
4118     Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1,
4119     isPredicated = 1 in {
4120   def DEALLOC_RET_cNotdnPt_V4 : NVInst_V4<(outs), (ins PredRegs:$src1,
4121                                                        i32imm:$amt1),
4122             "if (!$src1.new) dealloc_return:t",
4123             []>,
4124             Requires<[HasV4T]>;
4125 }
4126
4127
4128 // Load/Store with absolute addressing mode
4129 // memw(#u6)=Rt
4130
4131 multiclass ST_abs<string OpcStr> {
4132   let isPredicable = 1 in
4133   def _abs_V4 : STInst2<(outs),
4134             (ins globaladdress:$absaddr, IntRegs:$src),
4135             !strconcat(OpcStr, "(##$absaddr) = $src"),
4136             []>,
4137             Requires<[HasV4T]>;
4138
4139   let isPredicated = 1 in
4140   def _abs_cPt_V4 : STInst2<(outs),
4141             (ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2),
4142             !strconcat("if ($src1)",
4143             !strconcat(OpcStr, "(##$absaddr) = $src2")),
4144             []>,
4145             Requires<[HasV4T]>;
4146
4147   let isPredicated = 1 in
4148   def _abs_cNotPt_V4 : STInst2<(outs),
4149             (ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2),
4150             !strconcat("if (!$src1)",
4151             !strconcat(OpcStr, "(##$absaddr) = $src2")),
4152             []>,
4153             Requires<[HasV4T]>;
4154
4155   let isPredicated = 1 in
4156   def _abs_cdnPt_V4 : STInst2<(outs),
4157             (ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2),
4158             !strconcat("if ($src1.new)",
4159             !strconcat(OpcStr, "(##$absaddr) = $src2")),
4160             []>,
4161             Requires<[HasV4T]>;
4162
4163   let isPredicated = 1 in
4164   def _abs_cdnNotPt_V4 : STInst2<(outs),
4165             (ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2),
4166             !strconcat("if (!$src1.new)",
4167             !strconcat(OpcStr, "(##$absaddr) = $src2")),
4168             []>,
4169             Requires<[HasV4T]>;
4170
4171   def _abs_nv_V4 : STInst2<(outs),
4172             (ins globaladdress:$absaddr, IntRegs:$src),
4173             !strconcat(OpcStr, "(##$absaddr) = $src.new"),
4174             []>,
4175             Requires<[HasV4T]>;
4176
4177   let isPredicated = 1 in
4178   def _abs_cPt_nv_V4 : STInst2<(outs),
4179             (ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2),
4180             !strconcat("if ($src1)",
4181             !strconcat(OpcStr, "(##$absaddr) = $src2.new")),
4182             []>,
4183             Requires<[HasV4T]>;
4184
4185   let isPredicated = 1 in
4186   def _abs_cNotPt_nv_V4 : STInst2<(outs),
4187             (ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2),
4188             !strconcat("if (!$src1)",
4189             !strconcat(OpcStr, "(##$absaddr) = $src2.new")),
4190             []>,
4191             Requires<[HasV4T]>;
4192
4193   let isPredicated = 1 in
4194   def _abs_cdnPt_nv_V4 : STInst2<(outs),
4195             (ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2),
4196             !strconcat("if ($src1.new)",
4197             !strconcat(OpcStr, "(##$absaddr) = $src2.new")),
4198             []>,
4199             Requires<[HasV4T]>;
4200
4201   let isPredicated = 1 in
4202   def _abs_cdnNotPt_nv_V4 : STInst2<(outs),
4203             (ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2),
4204             !strconcat("if (!$src1.new)",
4205             !strconcat(OpcStr, "(##$absaddr) = $src2.new")),
4206             []>,
4207             Requires<[HasV4T]>;
4208 }
4209
4210 let AddedComplexity = 30, isPredicable = 1 in
4211 def STrid_abs_V4 : STInst<(outs),
4212           (ins globaladdress:$absaddr, DoubleRegs:$src),
4213            "memd(##$absaddr) = $src",
4214           [(store (i64 DoubleRegs:$src),
4215                   (HexagonCONST32 tglobaladdr:$absaddr))]>,
4216           Requires<[HasV4T]>;
4217
4218 let AddedComplexity = 30, isPredicated = 1 in
4219 def STrid_abs_cPt_V4 : STInst2<(outs),
4220           (ins PredRegs:$src1, globaladdress:$absaddr, DoubleRegs:$src2),
4221           "if ($src1) memd(##$absaddr) = $src2",
4222           []>,
4223           Requires<[HasV4T]>;
4224
4225 let AddedComplexity = 30, isPredicated = 1 in
4226 def STrid_abs_cNotPt_V4 : STInst2<(outs),
4227           (ins PredRegs:$src1, globaladdress:$absaddr, DoubleRegs:$src2),
4228           "if (!$src1) memd(##$absaddr) = $src2",
4229           []>,
4230           Requires<[HasV4T]>;
4231
4232 let AddedComplexity = 30, isPredicated = 1 in
4233 def STrid_abs_cdnPt_V4 : STInst2<(outs),
4234           (ins PredRegs:$src1, globaladdress:$absaddr, DoubleRegs:$src2),
4235           "if ($src1.new) memd(##$absaddr) = $src2",
4236           []>,
4237           Requires<[HasV4T]>;
4238
4239 let AddedComplexity = 30, isPredicated = 1 in
4240 def STrid_abs_cdnNotPt_V4 : STInst2<(outs),
4241           (ins PredRegs:$src1, globaladdress:$absaddr, DoubleRegs:$src2),
4242           "if (!$src1.new) memd(##$absaddr) = $src2",
4243           []>,
4244           Requires<[HasV4T]>;
4245
4246 defm STrib : ST_abs<"memb">;
4247 defm STrih : ST_abs<"memh">;
4248 defm STriw : ST_abs<"memw">;
4249
4250 let Predicates = [HasV4T], AddedComplexity  = 30 in
4251 def : Pat<(truncstorei8 (i32 IntRegs:$src1),
4252                         (HexagonCONST32 tglobaladdr:$absaddr)),
4253           (STrib_abs_V4 tglobaladdr: $absaddr, IntRegs: $src1)>;
4254
4255 let Predicates = [HasV4T], AddedComplexity  = 30 in
4256 def : Pat<(truncstorei16 (i32 IntRegs:$src1),
4257                           (HexagonCONST32 tglobaladdr:$absaddr)),
4258           (STrih_abs_V4 tglobaladdr: $absaddr, IntRegs: $src1)>;
4259
4260 let Predicates = [HasV4T], AddedComplexity  = 30 in
4261 def : Pat<(store (i32 IntRegs:$src1), (HexagonCONST32 tglobaladdr:$absaddr)),
4262           (STriw_abs_V4 tglobaladdr: $absaddr, IntRegs: $src1)>;
4263
4264
4265 multiclass LD_abs<string OpcStr> {
4266   let isPredicable = 1 in
4267   def _abs_V4 : LDInst2<(outs IntRegs:$dst),
4268             (ins globaladdress:$absaddr),
4269             !strconcat("$dst = ", !strconcat(OpcStr, "(##$absaddr)")),
4270             []>,
4271             Requires<[HasV4T]>;
4272
4273   let isPredicated = 1 in
4274   def _abs_cPt_V4 : LDInst2<(outs IntRegs:$dst),
4275             (ins PredRegs:$src1, globaladdress:$absaddr),
4276             !strconcat("if ($src1) $dst = ",
4277             !strconcat(OpcStr, "(##$absaddr)")),
4278             []>,
4279             Requires<[HasV4T]>;
4280
4281   let isPredicated = 1 in
4282   def _abs_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
4283             (ins PredRegs:$src1, globaladdress:$absaddr),
4284             !strconcat("if (!$src1) $dst = ",
4285             !strconcat(OpcStr, "(##$absaddr)")),
4286             []>,
4287             Requires<[HasV4T]>;
4288
4289   let isPredicated = 1 in
4290   def _abs_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
4291             (ins PredRegs:$src1, globaladdress:$absaddr),
4292             !strconcat("if ($src1.new) $dst = ",
4293             !strconcat(OpcStr, "(##$absaddr)")),
4294             []>,
4295             Requires<[HasV4T]>;
4296
4297   let isPredicated = 1 in
4298   def _abs_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
4299             (ins PredRegs:$src1, globaladdress:$absaddr),
4300             !strconcat("if (!$src1.new) $dst = ",
4301             !strconcat(OpcStr, "(##$absaddr)")),
4302             []>,
4303             Requires<[HasV4T]>;
4304 }
4305
4306 let AddedComplexity = 30 in
4307 def LDrid_abs_V4 : LDInst<(outs DoubleRegs:$dst),
4308           (ins globaladdress:$absaddr),
4309           "$dst = memd(##$absaddr)",
4310           [(set (i64 DoubleRegs:$dst),
4311                 (load (HexagonCONST32 tglobaladdr:$absaddr)))]>,
4312           Requires<[HasV4T]>;
4313
4314 let AddedComplexity = 30, isPredicated = 1 in
4315 def LDrid_abs_cPt_V4 : LDInst2<(outs DoubleRegs:$dst),
4316           (ins PredRegs:$src1, globaladdress:$absaddr),
4317           "if ($src1) $dst = memd(##$absaddr)",
4318           []>,
4319           Requires<[HasV4T]>;
4320
4321 let AddedComplexity = 30, isPredicated = 1 in
4322 def LDrid_abs_cNotPt_V4 : LDInst2<(outs DoubleRegs:$dst),
4323           (ins PredRegs:$src1, globaladdress:$absaddr),
4324           "if (!$src1) $dst = memd(##$absaddr)",
4325           []>,
4326           Requires<[HasV4T]>;
4327
4328 let AddedComplexity = 30, isPredicated = 1 in
4329 def LDrid_abs_cdnPt_V4 : LDInst2<(outs DoubleRegs:$dst),
4330           (ins PredRegs:$src1, globaladdress:$absaddr),
4331           "if ($src1.new) $dst = memd(##$absaddr)",
4332           []>,
4333           Requires<[HasV4T]>;
4334
4335 let AddedComplexity = 30, isPredicated = 1 in
4336 def LDrid_abs_cdnNotPt_V4 : LDInst2<(outs DoubleRegs:$dst),
4337           (ins PredRegs:$src1, globaladdress:$absaddr),
4338           "if (!$src1.new) $dst = memd(##$absaddr)",
4339           []>,
4340           Requires<[HasV4T]>;
4341
4342 defm LDrib : LD_abs<"memb">;
4343 defm LDriub : LD_abs<"memub">;
4344 defm LDrih : LD_abs<"memh">;
4345 defm LDriuh : LD_abs<"memuh">;
4346 defm LDriw : LD_abs<"memw">;
4347
4348
4349 let Predicates = [HasV4T], AddedComplexity  = 30 in
4350 def : Pat<(i32 (load (HexagonCONST32 tglobaladdr:$absaddr))),
4351           (LDriw_abs_V4 tglobaladdr: $absaddr)>;
4352
4353 let Predicates = [HasV4T], AddedComplexity=30 in
4354 def : Pat<(i32 (sextloadi8 (HexagonCONST32 tglobaladdr:$absaddr))),
4355           (LDrib_abs_V4 tglobaladdr:$absaddr)>;
4356
4357 let Predicates = [HasV4T], AddedComplexity=30 in
4358 def : Pat<(i32 (zextloadi8 (HexagonCONST32 tglobaladdr:$absaddr))),
4359           (LDriub_abs_V4 tglobaladdr:$absaddr)>;
4360
4361 let Predicates = [HasV4T], AddedComplexity=30 in
4362 def : Pat<(i32 (sextloadi16 (HexagonCONST32 tglobaladdr:$absaddr))),
4363           (LDrih_abs_V4 tglobaladdr:$absaddr)>;
4364
4365 let Predicates = [HasV4T], AddedComplexity=30 in
4366 def : Pat<(i32 (zextloadi16 (HexagonCONST32 tglobaladdr:$absaddr))),
4367           (LDriuh_abs_V4 tglobaladdr:$absaddr)>;
4368
4369 // Transfer global address into a register
4370 let AddedComplexity=50, isMoveImm = 1, isReMaterializable = 1 in
4371 def TFRI_V4 : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$src1),
4372            "$dst = ##$src1",
4373            [(set IntRegs:$dst, (HexagonCONST32 tglobaladdr:$src1))]>,
4374            Requires<[HasV4T]>;
4375
4376 let AddedComplexity=50, neverHasSideEffects = 1, isPredicated = 1 in
4377 def TFRI_cPt_V4 : ALU32_ri<(outs IntRegs:$dst),
4378                            (ins PredRegs:$src1, globaladdress:$src2),
4379            "if($src1) $dst = ##$src2",
4380            []>,
4381            Requires<[HasV4T]>;
4382
4383 let AddedComplexity=50, neverHasSideEffects = 1, isPredicated = 1 in
4384 def TFRI_cNotPt_V4 : ALU32_ri<(outs IntRegs:$dst),
4385                               (ins PredRegs:$src1, globaladdress:$src2),
4386            "if(!$src1) $dst = ##$src2",
4387            []>,
4388            Requires<[HasV4T]>;
4389
4390 let AddedComplexity=50, neverHasSideEffects = 1, isPredicated = 1 in
4391 def TFRI_cdnPt_V4 : ALU32_ri<(outs IntRegs:$dst),
4392                              (ins PredRegs:$src1, globaladdress:$src2),
4393            "if($src1.new) $dst = ##$src2",
4394            []>,
4395            Requires<[HasV4T]>;
4396
4397 let AddedComplexity=50, neverHasSideEffects = 1, isPredicated = 1 in
4398 def TFRI_cdnNotPt_V4 : ALU32_ri<(outs IntRegs:$dst),
4399                                 (ins PredRegs:$src1, globaladdress:$src2),
4400            "if(!$src1.new) $dst = ##$src2",
4401            []>,
4402            Requires<[HasV4T]>;
4403
4404 let AddedComplexity = 50, Predicates = [HasV4T] in
4405 def : Pat<(HexagonCONST32_GP tglobaladdr:$src1),
4406            (TFRI_V4 tglobaladdr:$src1)>;
4407
4408
4409 // Load - Indirect with long offset: These instructions take global address
4410 // as an operand
4411 let AddedComplexity = 10 in
4412 def LDrid_ind_lo_V4 : LDInst<(outs DoubleRegs:$dst),
4413             (ins IntRegs:$src1, u2Imm:$src2, globaladdress:$offset),
4414             "$dst=memd($src1<<#$src2+##$offset)",
4415             [(set (i64 DoubleRegs:$dst),
4416                   (load (add (shl IntRegs:$src1, u2ImmPred:$src2),
4417                         (HexagonCONST32 tglobaladdr:$offset))))]>,
4418             Requires<[HasV4T]>;
4419
4420 let AddedComplexity = 10 in
4421 multiclass LD_indirect_lo<string OpcStr, PatFrag OpNode> {
4422   def _lo_V4 : LDInst<(outs IntRegs:$dst),
4423             (ins IntRegs:$src1, u2Imm:$src2, globaladdress:$offset),
4424             !strconcat("$dst = ",
4425             !strconcat(OpcStr, "($src1<<#$src2+##$offset)")),
4426             [(set IntRegs:$dst,
4427                   (i32 (OpNode (add (shl IntRegs:$src1, u2ImmPred:$src2),
4428                           (HexagonCONST32 tglobaladdr:$offset)))))]>,
4429             Requires<[HasV4T]>;
4430 }
4431
4432 defm LDrib_ind : LD_indirect_lo<"memb", sextloadi8>;
4433 defm LDriub_ind : LD_indirect_lo<"memub", zextloadi8>;
4434 defm LDrih_ind : LD_indirect_lo<"memh", sextloadi16>;
4435 defm LDriuh_ind : LD_indirect_lo<"memuh", zextloadi16>;
4436 defm LDriw_ind : LD_indirect_lo<"memw", load>;
4437
4438 // Store - Indirect with long offset: These instructions take global address
4439 // as an operand
4440 let AddedComplexity = 10 in
4441 def STrid_ind_lo_V4 : STInst<(outs),
4442             (ins IntRegs:$src1, u2Imm:$src2, globaladdress:$src3,
4443                  DoubleRegs:$src4),
4444             "memd($src1<<#$src2+#$src3) = $src4",
4445             [(store (i64 DoubleRegs:$src4),
4446                  (add (shl IntRegs:$src1, u2ImmPred:$src2),
4447                       (HexagonCONST32 tglobaladdr:$src3)))]>,
4448              Requires<[HasV4T]>;
4449
4450 let AddedComplexity = 10 in
4451 multiclass ST_indirect_lo<string OpcStr, PatFrag OpNode> {
4452   def _lo_V4 : STInst<(outs),
4453             (ins IntRegs:$src1, u2Imm:$src2, globaladdress:$src3,
4454                  IntRegs:$src4),
4455             !strconcat(OpcStr, "($src1<<#$src2+##$src3) = $src4"),
4456             [(OpNode (i32 IntRegs:$src4),
4457                  (add (shl IntRegs:$src1, u2ImmPred:$src2),
4458                       (HexagonCONST32 tglobaladdr:$src3)))]>,
4459              Requires<[HasV4T]>;
4460 }
4461
4462 defm STrib_ind : ST_indirect_lo<"memb", truncstorei8>;
4463 defm STrih_ind : ST_indirect_lo<"memh", truncstorei16>;
4464 defm STriw_ind : ST_indirect_lo<"memw", store>;
4465
4466 // Store - absolute addressing mode: These instruction take constant
4467 // value as the extended operand.
4468 multiclass ST_absimm<string OpcStr> {
4469 let isExtended = 1, opExtendable = 0, isPredicable = 1,
4470 validSubTargets = HasV4SubT in
4471   def _abs_V4 : STInst2<(outs),
4472             (ins u0AlwaysExt:$src1, IntRegs:$src2),
4473             !strconcat(OpcStr, "(##$src1) = $src2"),
4474             []>,
4475             Requires<[HasV4T]>;
4476
4477 let isExtended = 1, opExtendable = 1, isPredicated = 1,
4478 validSubTargets = HasV4SubT in {
4479   def _abs_cPt_V4 : STInst2<(outs),
4480             (ins PredRegs:$src1, u0AlwaysExt:$src2, IntRegs:$src3),
4481             !strconcat("if ($src1)", !strconcat(OpcStr, "(##$src2) = $src3")),
4482             []>,
4483             Requires<[HasV4T]>;
4484
4485   def _abs_cNotPt_V4 : STInst2<(outs),
4486             (ins PredRegs:$src1, u0AlwaysExt:$src2, IntRegs:$src3),
4487             !strconcat("if (!$src1)", !strconcat(OpcStr, "(##$src2) = $src3")),
4488             []>,
4489             Requires<[HasV4T]>;
4490
4491   def _abs_cdnPt_V4 : STInst2<(outs),
4492             (ins PredRegs:$src1, u0AlwaysExt:$src2, IntRegs:$src3),
4493             !strconcat("if ($src1.new)",
4494             !strconcat(OpcStr, "(##$src2) = $src3")),
4495             []>,
4496             Requires<[HasV4T]>;
4497
4498   def _abs_cdnNotPt_V4 : STInst2<(outs),
4499             (ins PredRegs:$src1, u0AlwaysExt:$src2, IntRegs:$src3),
4500             !strconcat("if (!$src1.new)",
4501             !strconcat(OpcStr, "(##$src2) = $src3")),
4502             []>,
4503             Requires<[HasV4T]>;
4504 }
4505
4506 let isExtended = 1, opExtendable = 0, mayStore = 1, isNVStore = 1,
4507 validSubTargets = HasV4SubT in
4508   def _abs_nv_V4 : NVInst_V4<(outs),
4509             (ins u0AlwaysExt:$src1, IntRegs:$src2),
4510             !strconcat(OpcStr, "(##$src1) = $src2.new"),
4511             []>,
4512             Requires<[HasV4T]>;
4513
4514 let isExtended = 1, opExtendable = 1, mayStore = 1, isPredicated = 1,
4515 isNVStore = 1, validSubTargets = HasV4SubT in {
4516   def _abs_cPt_nv_V4 : NVInst_V4<(outs),
4517             (ins PredRegs:$src1, u0AlwaysExt:$src2, IntRegs:$src3),
4518             !strconcat("if ($src1)",
4519             !strconcat(OpcStr, "(##$src2) = $src3.new")),
4520             []>,
4521             Requires<[HasV4T]>;
4522
4523   def _abs_cNotPt_nv_V4 : NVInst_V4<(outs),
4524             (ins PredRegs:$src1, u0AlwaysExt:$src2, IntRegs:$src3),
4525             !strconcat("if (!$src1)",
4526             !strconcat(OpcStr, "(##$src2) = $src3.new")),
4527             []>,
4528             Requires<[HasV4T]>;
4529
4530   def _abs_cdnPt_nv_V4 : NVInst_V4<(outs),
4531             (ins PredRegs:$src1, u0AlwaysExt:$src2, IntRegs:$src3),
4532             !strconcat("if ($src1.new)",
4533             !strconcat(OpcStr, "(##$src2) = $src3.new")),
4534             []>,
4535             Requires<[HasV4T]>;
4536
4537   def _abs_cdnNotPt_nv_V4 : NVInst_V4<(outs),
4538             (ins PredRegs:$src1, u0AlwaysExt:$src2, IntRegs:$src3),
4539             !strconcat("if (!$src1.new)",
4540             !strconcat(OpcStr, "(##$src2) = $src3.new")),
4541             []>,
4542             Requires<[HasV4T]>;
4543 }
4544 }
4545
4546 defm STrib_imm : ST_absimm<"memb">;
4547 defm STrih_imm : ST_absimm<"memh">;
4548 defm STriw_imm : ST_absimm<"memw">;
4549
4550 let Predicates = [HasV4T], AddedComplexity  = 30 in {
4551 def : Pat<(truncstorei8 (i32 IntRegs:$src1), u0AlwaysExtPred:$src2),
4552           (STrib_imm_abs_V4 u0AlwaysExtPred:$src2, IntRegs: $src1)>;
4553
4554 def : Pat<(truncstorei16 (i32 IntRegs:$src1), u0AlwaysExtPred:$src2),
4555           (STrih_imm_abs_V4 u0AlwaysExtPred:$src2, IntRegs: $src1)>;
4556
4557 def : Pat<(store (i32 IntRegs:$src1), u0AlwaysExtPred:$src2),
4558           (STriw_imm_abs_V4 u0AlwaysExtPred:$src2, IntRegs: $src1)>;
4559 }
4560
4561 // Load - absolute addressing mode: These instruction take constant
4562 // value as the extended operand
4563
4564 multiclass LD_absimm<string OpcStr> {
4565 let isExtended = 1, opExtendable = 1, isPredicable = 1,
4566 validSubTargets = HasV4SubT in
4567   def _abs_V4 : LDInst2<(outs IntRegs:$dst),
4568             (ins u0AlwaysExt:$src),
4569             !strconcat("$dst = ",
4570             !strconcat(OpcStr, "(##$src)")),
4571             []>,
4572             Requires<[HasV4T]>;
4573
4574 let isExtended = 1, opExtendable = 2, isPredicated = 1,
4575 validSubTargets = HasV4SubT in {
4576   def _abs_cPt_V4 : LDInst2<(outs IntRegs:$dst),
4577             (ins PredRegs:$src1, u0AlwaysExt:$src2),
4578             !strconcat("if ($src1) $dst = ",
4579             !strconcat(OpcStr, "(##$src2)")),
4580             []>,
4581             Requires<[HasV4T]>;
4582
4583   def _abs_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
4584             (ins PredRegs:$src1, u0AlwaysExt:$src2),
4585             !strconcat("if (!$src1) $dst = ",
4586             !strconcat(OpcStr, "(##$src2)")),
4587             []>,
4588             Requires<[HasV4T]>;
4589
4590   def _abs_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
4591             (ins PredRegs:$src1, u0AlwaysExt:$src2),
4592             !strconcat("if ($src1.new) $dst = ",
4593             !strconcat(OpcStr, "(##$src2)")),
4594             []>,
4595             Requires<[HasV4T]>;
4596
4597   def _abs_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
4598             (ins PredRegs:$src1, u0AlwaysExt:$src2),
4599             !strconcat("if (!$src1.new) $dst = ",
4600             !strconcat(OpcStr, "(##$src2)")),
4601             []>,
4602             Requires<[HasV4T]>;
4603 }
4604 }
4605
4606 defm LDrib_imm  : LD_absimm<"memb">;
4607 defm LDriub_imm : LD_absimm<"memub">;
4608 defm LDrih_imm  : LD_absimm<"memh">;
4609 defm LDriuh_imm : LD_absimm<"memuh">;
4610 defm LDriw_imm  : LD_absimm<"memw">;
4611
4612 let Predicates = [HasV4T], AddedComplexity  = 30 in {
4613 def : Pat<(i32 (load u0AlwaysExtPred:$src)),
4614           (LDriw_imm_abs_V4 u0AlwaysExtPred:$src)>;
4615
4616 def : Pat<(i32 (sextloadi8 u0AlwaysExtPred:$src)),
4617           (LDrib_imm_abs_V4 u0AlwaysExtPred:$src)>;
4618
4619 def : Pat<(i32 (zextloadi8 u0AlwaysExtPred:$src)),
4620           (LDriub_imm_abs_V4 u0AlwaysExtPred:$src)>;
4621
4622 def : Pat<(i32 (sextloadi16 u0AlwaysExtPred:$src)),
4623           (LDrih_imm_abs_V4 u0AlwaysExtPred:$src)>;
4624
4625 def : Pat<(i32 (zextloadi16 u0AlwaysExtPred:$src)),
4626           (LDriuh_imm_abs_V4 u0AlwaysExtPred:$src)>;
4627 }
4628
4629 // Indexed store double word - global address.
4630 // memw(Rs+#u6:2)=#S8
4631 let AddedComplexity = 10 in
4632 def STriw_offset_ext_V4 : STInst<(outs),
4633             (ins IntRegs:$src1, u6_2Imm:$src2, globaladdress:$src3),
4634             "memw($src1+#$src2) = ##$src3",
4635             [(store (HexagonCONST32 tglobaladdr:$src3),
4636                     (add IntRegs:$src1, u6_2ImmPred:$src2))]>,
4637             Requires<[HasV4T]>;
4638
4639
4640 // Indexed store double word - global address.
4641 // memw(Rs+#u6:2)=#S8
4642 let AddedComplexity = 10 in
4643 def STrih_offset_ext_V4 : STInst<(outs),
4644             (ins IntRegs:$src1, u6_1Imm:$src2, globaladdress:$src3),
4645             "memh($src1+#$src2) = ##$src3",
4646             [(truncstorei16 (HexagonCONST32 tglobaladdr:$src3),
4647                     (add IntRegs:$src1, u6_1ImmPred:$src2))]>,
4648             Requires<[HasV4T]>;