1 //=- HexagonInstrInfoV4.td - Target Desc. for Hexagon Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Hexagon V4 instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 let neverHasSideEffects = 1 in
15 def IMMEXT : Immext<(outs), (ins),
20 // Hexagon V4 Architecture spec defines 8 instruction classes:
21 // LD ST ALU32 XTYPE J JR MEMOP NV CR SYSTEM(system is not implemented in the
25 // ========================================
26 // Loads (8/16/32/64 bit)
30 // ========================================
31 // Stores (8/16/32/64 bit)
34 // ALU32 Instructions:
35 // ========================================
36 // Arithmetic / Logical (32 bit)
39 // XTYPE Instructions (32/64 bit):
40 // ========================================
41 // Arithmetic, Logical, Bit Manipulation
42 // Multiply (Integer, Fractional, Complex)
43 // Permute / Vector Permute Operations
44 // Predicate Operations
45 // Shift / Shift with Add/Sub/Logical
47 // Vector Halfword (ALU, Shift, Multiply)
48 // Vector Word (ALU, Shift)
51 // ========================================
52 // Jump/Call PC-relative
55 // ========================================
58 // MEMOP Instructions:
59 // ========================================
60 // Operation on memory (8/16/32 bit)
63 // ========================================
68 // ========================================
69 // Control-Register Transfers
70 // Hardware Loop Setup
71 // Predicate Logicals & Reductions
73 // SYSTEM Instructions (not implemented in the compiler):
74 // ========================================
80 //===----------------------------------------------------------------------===//
82 //===----------------------------------------------------------------------===//
86 let isPredicated = 1 in
87 def ASLH_cPt_V4 : ALU32_rr<(outs IntRegs:$dst),
88 (ins PredRegs:$src1, IntRegs:$src2),
89 "if ($src1) $dst = aslh($src2)",
93 let isPredicated = 1 in
94 def ASLH_cNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
95 (ins PredRegs:$src1, IntRegs:$src2),
96 "if (!$src1) $dst = aslh($src2)",
100 let isPredicated = 1 in
101 def ASLH_cdnPt_V4 : ALU32_rr<(outs IntRegs:$dst),
102 (ins PredRegs:$src1, IntRegs:$src2),
103 "if ($src1.new) $dst = aslh($src2)",
107 let isPredicated = 1 in
108 def ASLH_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
109 (ins PredRegs:$src1, IntRegs:$src2),
110 "if (!$src1.new) $dst = aslh($src2)",
114 let isPredicated = 1 in
115 def ASRH_cPt_V4 : ALU32_rr<(outs IntRegs:$dst),
116 (ins PredRegs:$src1, IntRegs:$src2),
117 "if ($src1) $dst = asrh($src2)",
121 let isPredicated = 1 in
122 def ASRH_cNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
123 (ins PredRegs:$src1, IntRegs:$src2),
124 "if (!$src1) $dst = asrh($src2)",
128 let isPredicated = 1 in
129 def ASRH_cdnPt_V4 : ALU32_rr<(outs IntRegs:$dst),
130 (ins PredRegs:$src1, IntRegs:$src2),
131 "if ($src1.new) $dst = asrh($src2)",
135 let isPredicated = 1 in
136 def ASRH_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
137 (ins PredRegs:$src1, IntRegs:$src2),
138 "if (!$src1.new) $dst = asrh($src2)",
144 let isPredicated = 1 in
145 def SXTB_cPt_V4 : ALU32_rr<(outs IntRegs:$dst),
146 (ins PredRegs:$src1, IntRegs:$src2),
147 "if ($src1) $dst = sxtb($src2)",
151 let isPredicated = 1 in
152 def SXTB_cNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
153 (ins PredRegs:$src1, IntRegs:$src2),
154 "if (!$src1) $dst = sxtb($src2)",
158 let isPredicated = 1 in
159 def SXTB_cdnPt_V4 : ALU32_rr<(outs IntRegs:$dst),
160 (ins PredRegs:$src1, IntRegs:$src2),
161 "if ($src1.new) $dst = sxtb($src2)",
165 let isPredicated = 1 in
166 def SXTB_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
167 (ins PredRegs:$src1, IntRegs:$src2),
168 "if (!$src1.new) $dst = sxtb($src2)",
173 let isPredicated = 1 in
174 def SXTH_cPt_V4 : ALU32_rr<(outs IntRegs:$dst),
175 (ins PredRegs:$src1, IntRegs:$src2),
176 "if ($src1) $dst = sxth($src2)",
180 let isPredicated = 1 in
181 def SXTH_cNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
182 (ins PredRegs:$src1, IntRegs:$src2),
183 "if (!$src1) $dst = sxth($src2)",
187 let isPredicated = 1 in
188 def SXTH_cdnPt_V4 : ALU32_rr<(outs IntRegs:$dst),
189 (ins PredRegs:$src1, IntRegs:$src2),
190 "if ($src1.new) $dst = sxth($src2)",
194 let isPredicated = 1 in
195 def SXTH_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
196 (ins PredRegs:$src1, IntRegs:$src2),
197 "if (!$src1.new) $dst = sxth($src2)",
203 let neverHasSideEffects = 1, isPredicated = 1 in
204 def ZXTB_cPt_V4 : ALU32_rr<(outs IntRegs:$dst),
205 (ins PredRegs:$src1, IntRegs:$src2),
206 "if ($src1) $dst = zxtb($src2)",
210 let neverHasSideEffects = 1, isPredicated = 1 in
211 def ZXTB_cNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
212 (ins PredRegs:$src1, IntRegs:$src2),
213 "if (!$src1) $dst = zxtb($src2)",
217 let neverHasSideEffects = 1, isPredicated = 1 in
218 def ZXTB_cdnPt_V4 : ALU32_rr<(outs IntRegs:$dst),
219 (ins PredRegs:$src1, IntRegs:$src2),
220 "if ($src1.new) $dst = zxtb($src2)",
224 let neverHasSideEffects = 1, isPredicated = 1 in
225 def ZXTB_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
226 (ins PredRegs:$src1, IntRegs:$src2),
227 "if (!$src1.new) $dst = zxtb($src2)",
231 let neverHasSideEffects = 1, isPredicated = 1 in
232 def ZXTH_cPt_V4 : ALU32_rr<(outs IntRegs:$dst),
233 (ins PredRegs:$src1, IntRegs:$src2),
234 "if ($src1) $dst = zxth($src2)",
238 let neverHasSideEffects = 1, isPredicated = 1 in
239 def ZXTH_cNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
240 (ins PredRegs:$src1, IntRegs:$src2),
241 "if (!$src1) $dst = zxth($src2)",
245 let neverHasSideEffects = 1, isPredicated = 1 in
246 def ZXTH_cdnPt_V4 : ALU32_rr<(outs IntRegs:$dst),
247 (ins PredRegs:$src1, IntRegs:$src2),
248 "if ($src1.new) $dst = zxth($src2)",
252 let neverHasSideEffects = 1, isPredicated = 1 in
253 def ZXTH_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
254 (ins PredRegs:$src1, IntRegs:$src2),
255 "if (!$src1.new) $dst = zxth($src2)",
259 // Generate frame index addresses.
260 let neverHasSideEffects = 1, isReMaterializable = 1 in
261 def TFR_FI_immext_V4 : ALU32_ri<(outs IntRegs:$dst),
262 (ins IntRegs:$src1, s32Imm:$offset),
263 "$dst = add($src1, ##$offset)",
268 //===----------------------------------------------------------------------===//
270 //===----------------------------------------------------------------------===//
273 //===----------------------------------------------------------------------===//
275 //===----------------------------------------------------------------------===//
278 // Rdd=combine(Rs, #s8)
279 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 8,
280 neverHasSideEffects = 1, validSubTargets = HasV4SubT in
281 def COMBINE_rI_V4 : ALU32_ri<(outs DoubleRegs:$dst),
282 (ins IntRegs:$src1, s8Ext:$src2),
283 "$dst = combine($src1, #$src2)",
287 // Rdd=combine(#s8, Rs)
288 let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 8,
289 neverHasSideEffects = 1, validSubTargets = HasV4SubT in
290 def COMBINE_Ir_V4 : ALU32_ir<(outs DoubleRegs:$dst),
291 (ins s8Ext:$src1, IntRegs:$src2),
292 "$dst = combine(#$src1, $src2)",
296 let isExtendable = 1, opExtendable = 2, isExtentSigned = 0, opExtentBits = 6,
297 neverHasSideEffects = 1, validSubTargets = HasV4SubT in
298 def COMBINE_iI_V4 : ALU32_ii<(outs DoubleRegs:$dst),
299 (ins s8Imm:$src1, u6Ext:$src2),
300 "$dst = combine(#$src1, #$src2)",
304 //===----------------------------------------------------------------------===//
306 //===----------------------------------------------------------------------===//
308 //===----------------------------------------------------------------------===//
310 //===----------------------------------------------------------------------===//
312 // These absolute set addressing mode instructions accept immediate as
313 // an operand. We have duplicated these patterns to take global address.
315 let neverHasSideEffects = 1 in
316 def LDrid_abs_setimm_V4 : LDInst2<(outs DoubleRegs:$dst1, IntRegs:$dst2),
318 "$dst1 = memd($dst2=#$addr)",
323 let neverHasSideEffects = 1 in
324 def LDrib_abs_setimm_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
326 "$dst1 = memb($dst2=#$addr)",
331 let neverHasSideEffects = 1 in
332 def LDrih_abs_setimm_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
334 "$dst1 = memh($dst2=#$addr)",
339 let neverHasSideEffects = 1 in
340 def LDriub_abs_setimm_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
342 "$dst1 = memub($dst2=#$addr)",
347 let neverHasSideEffects = 1 in
348 def LDriuh_abs_setimm_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
350 "$dst1 = memuh($dst2=#$addr)",
355 let neverHasSideEffects = 1 in
356 def LDriw_abs_setimm_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
358 "$dst1 = memw($dst2=#$addr)",
362 // Following patterns are defined for absolute set addressing mode
363 // instruction which take global address as operand.
364 let neverHasSideEffects = 1 in
365 def LDrid_abs_set_V4 : LDInst2<(outs DoubleRegs:$dst1, IntRegs:$dst2),
366 (ins globaladdress:$addr),
367 "$dst1 = memd($dst2=##$addr)",
372 let neverHasSideEffects = 1 in
373 def LDrib_abs_set_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
374 (ins globaladdress:$addr),
375 "$dst1 = memb($dst2=##$addr)",
380 let neverHasSideEffects = 1 in
381 def LDrih_abs_set_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
382 (ins globaladdress:$addr),
383 "$dst1 = memh($dst2=##$addr)",
388 let neverHasSideEffects = 1 in
389 def LDriub_abs_set_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
390 (ins globaladdress:$addr),
391 "$dst1 = memub($dst2=##$addr)",
396 let neverHasSideEffects = 1 in
397 def LDriuh_abs_set_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
398 (ins globaladdress:$addr),
399 "$dst1 = memuh($dst2=##$addr)",
404 let neverHasSideEffects = 1 in
405 def LDriw_abs_set_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
406 (ins globaladdress:$addr),
407 "$dst1 = memw($dst2=##$addr)",
413 // Make sure that in post increment load, the first operand is always the post
414 // increment operand.
416 // Rdd=memd(Rs+Rt<<#u2)
417 // Special case pattern for indexed load without offset which is easier to
418 // match. AddedComplexity of this pattern should be lower than base+offset load
419 // and lower yet than the more generic version with offset/shift below
420 // Similar approach is taken for all other base+index loads.
421 let AddedComplexity = 10, isPredicable = 1 in
422 def LDrid_indexed_V4 : LDInst<(outs DoubleRegs:$dst),
423 (ins IntRegs:$src1, IntRegs:$src2),
424 "$dst=memd($src1+$src2<<#0)",
425 [(set (i64 DoubleRegs:$dst),
426 (i64 (load (add (i32 IntRegs:$src1),
427 (i32 IntRegs:$src2)))))]>,
430 // multiclass for load instructions with base + register offset
432 multiclass ld_idxd_shl_pbase<string mnemonic, RegisterClass RC, bit isNot,
434 let PNewValue = #!if(isPredNew, "new", "") in
435 def #NAME# : LDInst2<(outs RC:$dst),
436 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$offset),
437 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
438 ") ")#"$dst = "#mnemonic#"($src2+$src3<<#$offset)",
439 []>, Requires<[HasV4T]>;
442 multiclass ld_idxd_shl_pred<string mnemonic, RegisterClass RC, bit PredNot> {
443 let PredSense = #!if(PredNot, "false", "true") in {
444 defm _c#NAME# : ld_idxd_shl_pbase<mnemonic, RC, PredNot, 0>;
446 defm _cdn#NAME# : ld_idxd_shl_pbase<mnemonic, RC, PredNot, 1>;
450 let neverHasSideEffects = 1 in
451 multiclass ld_idxd_shl<string mnemonic, string CextOp, RegisterClass RC> {
452 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed_shl in {
453 let isPredicable = 1 in
454 def #NAME#_V4 : LDInst2<(outs RC:$dst),
455 (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$offset),
456 "$dst = "#mnemonic#"($src1+$src2<<#$offset)",
457 []>, Requires<[HasV4T]>;
459 let isPredicated = 1 in {
460 defm Pt_V4 : ld_idxd_shl_pred<mnemonic, RC, 0 >;
461 defm NotPt_V4 : ld_idxd_shl_pred<mnemonic, RC, 1>;
466 let addrMode = BaseRegOffset in {
467 defm LDrib_indexed_shl: ld_idxd_shl<"memb", "LDrib", IntRegs>, AddrModeRel;
468 defm LDriub_indexed_shl: ld_idxd_shl<"memub", "LDriub", IntRegs>, AddrModeRel;
469 defm LDrih_indexed_shl: ld_idxd_shl<"memh", "LDrih", IntRegs>, AddrModeRel;
470 defm LDriuh_indexed_shl: ld_idxd_shl<"memuh", "LDriuh", IntRegs>, AddrModeRel;
471 defm LDriw_indexed_shl: ld_idxd_shl<"memw", "LDriw", IntRegs>, AddrModeRel;
472 defm LDrid_indexed_shl: ld_idxd_shl<"memd", "LDrid", DoubleRegs>, AddrModeRel;
475 // 'def pats' for load instructions with base + register offset and non-zero
476 // immediate value. Immediate value is used to left-shift the second
478 let AddedComplexity = 40 in {
479 def : Pat <(i32 (sextloadi8 (add IntRegs:$src1,
480 (shl IntRegs:$src2, u2ImmPred:$offset)))),
481 (LDrib_indexed_shl_V4 IntRegs:$src1,
482 IntRegs:$src2, u2ImmPred:$offset)>,
485 def : Pat <(i32 (zextloadi8 (add IntRegs:$src1,
486 (shl IntRegs:$src2, u2ImmPred:$offset)))),
487 (LDriub_indexed_shl_V4 IntRegs:$src1,
488 IntRegs:$src2, u2ImmPred:$offset)>,
491 def : Pat <(i32 (extloadi8 (add IntRegs:$src1,
492 (shl IntRegs:$src2, u2ImmPred:$offset)))),
493 (LDriub_indexed_shl_V4 IntRegs:$src1,
494 IntRegs:$src2, u2ImmPred:$offset)>,
497 def : Pat <(i32 (sextloadi16 (add IntRegs:$src1,
498 (shl IntRegs:$src2, u2ImmPred:$offset)))),
499 (LDrih_indexed_shl_V4 IntRegs:$src1,
500 IntRegs:$src2, u2ImmPred:$offset)>,
503 def : Pat <(i32 (zextloadi16 (add IntRegs:$src1,
504 (shl IntRegs:$src2, u2ImmPred:$offset)))),
505 (LDriuh_indexed_shl_V4 IntRegs:$src1,
506 IntRegs:$src2, u2ImmPred:$offset)>,
509 def : Pat <(i32 (extloadi16 (add IntRegs:$src1,
510 (shl IntRegs:$src2, u2ImmPred:$offset)))),
511 (LDriuh_indexed_shl_V4 IntRegs:$src1,
512 IntRegs:$src2, u2ImmPred:$offset)>,
515 def : Pat <(i32 (load (add IntRegs:$src1,
516 (shl IntRegs:$src2, u2ImmPred:$offset)))),
517 (LDriw_indexed_shl_V4 IntRegs:$src1,
518 IntRegs:$src2, u2ImmPred:$offset)>,
521 def : Pat <(i64 (load (add IntRegs:$src1,
522 (shl IntRegs:$src2, u2ImmPred:$offset)))),
523 (LDrid_indexed_shl_V4 IntRegs:$src1,
524 IntRegs:$src2, u2ImmPred:$offset)>,
528 //// Load doubleword conditionally.
529 // if ([!]Pv[.new]) Rd=memd(Rs+Rt<<#u2)
530 // if (Pv) Rd=memd(Rs+Rt<<#u2)
531 let AddedComplexity = 15, isPredicated = 1 in
532 def LDrid_indexed_cPt_V4 : LDInst2<(outs DoubleRegs:$dst),
533 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
534 "if ($src1) $dst=memd($src2+$src3<<#0)",
538 // if (Pv.new) Rd=memd(Rs+Rt<<#u2)
539 let AddedComplexity = 15, isPredicated = 1 in
540 def LDrid_indexed_cdnPt_V4 : LDInst2<(outs DoubleRegs:$dst),
541 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
542 "if ($src1.new) $dst=memd($src2+$src3<<#0)",
546 // if (!Pv) Rd=memd(Rs+Rt<<#u2)
547 let AddedComplexity = 15, isPredicated = 1 in
548 def LDrid_indexed_cNotPt_V4 : LDInst2<(outs DoubleRegs:$dst),
549 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
550 "if (!$src1) $dst=memd($src2+$src3<<#0)",
554 // if (!Pv.new) Rd=memd(Rs+Rt<<#u2)
555 let AddedComplexity = 15, isPredicated = 1 in
556 def LDrid_indexed_cdnNotPt_V4 : LDInst2<(outs DoubleRegs:$dst),
557 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
558 "if (!$src1.new) $dst=memd($src2+$src3<<#0)",
562 // Rdd=memd(Rt<<#u2+#U6)
565 // Rd=memb(Rs+Rt<<#u2)
566 let AddedComplexity = 10, isPredicable = 1 in
567 def LDrib_indexed_V4 : LDInst<(outs IntRegs:$dst),
568 (ins IntRegs:$src1, IntRegs:$src2),
569 "$dst=memb($src1+$src2<<#0)",
570 [(set (i32 IntRegs:$dst),
571 (i32 (sextloadi8 (add (i32 IntRegs:$src1),
572 (i32 IntRegs:$src2)))))]>,
575 let AddedComplexity = 10, isPredicable = 1 in
576 def LDriub_indexed_V4 : LDInst<(outs IntRegs:$dst),
577 (ins IntRegs:$src1, IntRegs:$src2),
578 "$dst=memub($src1+$src2<<#0)",
579 [(set (i32 IntRegs:$dst),
580 (i32 (zextloadi8 (add (i32 IntRegs:$src1),
581 (i32 IntRegs:$src2)))))]>,
584 let AddedComplexity = 10, isPredicable = 1 in
585 def LDriub_ae_indexed_V4 : LDInst<(outs IntRegs:$dst),
586 (ins IntRegs:$src1, IntRegs:$src2),
587 "$dst=memub($src1+$src2<<#0)",
588 [(set (i32 IntRegs:$dst),
589 (i32 (extloadi8 (add (i32 IntRegs:$src1),
590 (i32 IntRegs:$src2)))))]>,
593 let AddedComplexity = 40, isPredicable = 1 in
594 def LDriub_ae_indexed_shl_V4 : LDInst<(outs IntRegs:$dst),
595 (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$offset),
596 "$dst=memub($src1+$src2<<#$offset)",
597 [(set (i32 IntRegs:$dst),
598 (i32 (extloadi8 (add (i32 IntRegs:$src1),
599 (shl (i32 IntRegs:$src2),
600 u2ImmPred:$offset)))))]>,
603 //// Load byte conditionally.
604 // if ([!]Pv[.new]) Rd=memb(Rs+Rt<<#u2)
605 // if (Pv) Rd=memb(Rs+Rt<<#u2)
606 let AddedComplexity = 15, isPredicated = 1 in
607 def LDrib_indexed_cPt_V4 : LDInst2<(outs IntRegs:$dst),
608 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
609 "if ($src1) $dst=memb($src2+$src3<<#0)",
613 // if (Pv.new) Rd=memb(Rs+Rt<<#u2)
614 let AddedComplexity = 15, isPredicated = 1 in
615 def LDrib_indexed_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
616 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
617 "if ($src1.new) $dst=memb($src2+$src3<<#0)",
621 // if (!Pv) Rd=memb(Rs+Rt<<#u2)
622 let AddedComplexity = 15, isPredicated = 1 in
623 def LDrib_indexed_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
624 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
625 "if (!$src1) $dst=memb($src2+$src3<<#0)",
629 // if (!Pv.new) Rd=memb(Rs+Rt<<#u2)
630 let AddedComplexity = 15, isPredicated = 1 in
631 def LDrib_indexed_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
632 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
633 "if (!$src1.new) $dst=memb($src2+$src3<<#0)",
637 //// Load unsigned byte conditionally.
638 // if ([!]Pv[.new]) Rd=memub(Rs+Rt<<#u2)
639 // if (Pv) Rd=memub(Rs+Rt<<#u2)
640 let AddedComplexity = 15, isPredicated = 1 in
641 def LDriub_indexed_cPt_V4 : LDInst2<(outs IntRegs:$dst),
642 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
643 "if ($src1) $dst=memub($src2+$src3<<#0)",
647 // if (Pv.new) Rd=memub(Rs+Rt<<#u2)
648 let AddedComplexity = 15, isPredicated = 1 in
649 def LDriub_indexed_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
650 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
651 "if ($src1.new) $dst=memub($src2+$src3<<#0)",
655 // if (!Pv) Rd=memub(Rs+Rt<<#u2)
656 let AddedComplexity = 15, isPredicated = 1 in
657 def LDriub_indexed_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
658 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
659 "if (!$src1) $dst=memub($src2+$src3<<#0)",
663 // if (!Pv.new) Rd=memub(Rs+Rt<<#u2)
664 let AddedComplexity = 15, isPredicated = 1 in
665 def LDriub_indexed_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
666 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
667 "if (!$src1.new) $dst=memub($src2+$src3<<#0)",
671 // Rd=memb(Rt<<#u2+#U6)
674 // Rd=memh(Rs+Rt<<#u2)
675 let AddedComplexity = 10, isPredicable = 1 in
676 def LDrih_indexed_V4 : LDInst<(outs IntRegs:$dst),
677 (ins IntRegs:$src1, IntRegs:$src2),
678 "$dst=memh($src1+$src2<<#0)",
679 [(set (i32 IntRegs:$dst),
680 (i32 (sextloadi16 (add (i32 IntRegs:$src1),
681 (i32 IntRegs:$src2)))))]>,
684 let AddedComplexity = 10, isPredicable = 1 in
685 def LDriuh_indexed_V4 : LDInst<(outs IntRegs:$dst),
686 (ins IntRegs:$src1, IntRegs:$src2),
687 "$dst=memuh($src1+$src2<<#0)",
688 [(set (i32 IntRegs:$dst),
689 (i32 (zextloadi16 (add (i32 IntRegs:$src1),
690 (i32 IntRegs:$src2)))))]>,
693 let AddedComplexity = 10, isPredicable = 1 in
694 def LDriuh_ae_indexed_V4 : LDInst<(outs IntRegs:$dst),
695 (ins IntRegs:$src1, IntRegs:$src2),
696 "$dst=memuh($src1+$src2<<#0)",
697 [(set (i32 IntRegs:$dst),
698 (i32 (extloadi16 (add (i32 IntRegs:$src1),
699 (i32 IntRegs:$src2)))))]>,
702 let AddedComplexity = 40, isPredicable = 1 in
703 def LDriuh_ae_indexed_shl_V4 : LDInst<(outs IntRegs:$dst),
704 (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$offset),
705 "$dst=memuh($src1+$src2<<#$offset)",
706 [(set (i32 IntRegs:$dst),
707 (i32 (extloadi16 (add (i32 IntRegs:$src1),
708 (shl (i32 IntRegs:$src2),
709 u2ImmPred:$offset)))))]>,
712 //// Load halfword conditionally.
713 // if ([!]Pv[.new]) Rd=memh(Rs+Rt<<#u2)
714 // if (Pv) Rd=memh(Rs+Rt<<#u2)
715 let AddedComplexity = 15, isPredicated = 1 in
716 def LDrih_indexed_cPt_V4 : LDInst2<(outs IntRegs:$dst),
717 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
718 "if ($src1) $dst=memh($src2+$src3<<#0)",
722 // if (Pv.new) Rd=memh(Rs+Rt<<#u2)
723 let AddedComplexity = 15, isPredicated = 1 in
724 def LDrih_indexed_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
725 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
726 "if ($src1.new) $dst=memh($src2+$src3<<#0)",
730 // if (!Pv) Rd=memh(Rs+Rt<<#u2)
731 let AddedComplexity = 15, isPredicated = 1 in
732 def LDrih_indexed_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
733 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
734 "if (!$src1) $dst=memh($src2+$src3<<#0)",
738 // if (!Pv.new) Rd=memh(Rs+Rt<<#u2)
739 let AddedComplexity = 15, isPredicated = 1 in
740 def LDrih_indexed_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
741 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
742 "if (!$src1.new) $dst=memh($src2+$src3<<#0)",
746 //// Load unsigned halfword conditionally.
747 // if ([!]Pv[.new]) Rd=memuh(Rs+Rt<<#u2)
748 // if (Pv) Rd=memuh(Rs+Rt<<#u2)
749 let AddedComplexity = 15, isPredicated = 1 in
750 def LDriuh_indexed_cPt_V4 : LDInst2<(outs IntRegs:$dst),
751 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
752 "if ($src1) $dst=memuh($src2+$src3<<#0)",
756 // if (Pv.new) Rd=memuh(Rs+Rt<<#u2)
757 let AddedComplexity = 15, isPredicated = 1 in
758 def LDriuh_indexed_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
759 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
760 "if ($src1.new) $dst=memuh($src2+$src3<<#0)",
764 // if (!Pv) Rd=memuh(Rs+Rt<<#u2)
765 let AddedComplexity = 15, isPredicated = 1 in
766 def LDriuh_indexed_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
767 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
768 "if (!$src1) $dst=memuh($src2+$src3<<#0)",
772 // if (!Pv.new) Rd=memuh(Rs+Rt<<#u2)
773 let AddedComplexity = 15, isPredicated = 1 in
774 def LDriuh_indexed_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
775 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
776 "if (!$src1.new) $dst=memuh($src2+$src3<<#0)",
780 // Rd=memh(Rt<<#u2+#U6)
783 // Load predicate: Fix for bug 5279.
784 let neverHasSideEffects = 1 in
785 def LDriw_pred_V4 : LDInst2<(outs PredRegs:$dst),
787 "Error; should not emit",
793 // Rd=memw(Rs+Rt<<#u2)
794 let AddedComplexity = 10, isPredicable = 1 in
795 def LDriw_indexed_V4 : LDInst<(outs IntRegs:$dst),
796 (ins IntRegs:$src1, IntRegs:$src2),
797 "$dst=memw($src1+$src2<<#0)",
798 [(set (i32 IntRegs:$dst),
799 (i32 (load (add (i32 IntRegs:$src1),
800 (i32 IntRegs:$src2)))))]>,
803 //// Load word conditionally.
804 // if ([!]Pv[.new]) Rd=memw(Rs+Rt<<#u2)
805 // if (Pv) Rd=memw(Rs+Rt<<#u2)
806 let AddedComplexity = 15, isPredicated = 1 in
807 def LDriw_indexed_cPt_V4 : LDInst2<(outs IntRegs:$dst),
808 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
809 "if ($src1) $dst=memw($src2+$src3<<#0)",
813 // if (Pv.new) Rd=memh(Rs+Rt<<#u2)
814 let AddedComplexity = 15, isPredicated = 1 in
815 def LDriw_indexed_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
816 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
817 "if ($src1.new) $dst=memw($src2+$src3<<#0)",
821 // if (!Pv) Rd=memh(Rs+Rt<<#u2)
822 let AddedComplexity = 15, isPredicated = 1 in
823 def LDriw_indexed_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
824 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
825 "if (!$src1) $dst=memw($src2+$src3<<#0)",
829 // if (!Pv.new) Rd=memh(Rs+Rt<<#u2)
830 let AddedComplexity = 15, isPredicated = 1 in
831 def LDriw_indexed_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
832 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
833 "if (!$src1.new) $dst=memw($src2+$src3<<#0)",
837 /// Load from global offset
839 let isPredicable = 1, neverHasSideEffects = 1 in
840 def LDrid_GP_V4 : LDInst2<(outs DoubleRegs:$dst),
841 (ins globaladdress:$global, u16Imm:$offset),
842 "$dst=memd(#$global+$offset)",
846 let neverHasSideEffects = 1, isPredicated = 1 in
847 def LDrid_GP_cPt_V4 : LDInst2<(outs DoubleRegs:$dst),
848 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
849 "if ($src1) $dst=memd(##$global+$offset)",
853 let neverHasSideEffects = 1, isPredicated = 1 in
854 def LDrid_GP_cNotPt_V4 : LDInst2<(outs DoubleRegs:$dst),
855 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
856 "if (!$src1) $dst=memd(##$global+$offset)",
860 let neverHasSideEffects = 1, isPredicated = 1 in
861 def LDrid_GP_cdnPt_V4 : LDInst2<(outs DoubleRegs:$dst),
862 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
863 "if ($src1.new) $dst=memd(##$global+$offset)",
867 let neverHasSideEffects = 1, isPredicated = 1 in
868 def LDrid_GP_cdnNotPt_V4 : LDInst2<(outs DoubleRegs:$dst),
869 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
870 "if (!$src1.new) $dst=memd(##$global+$offset)",
874 let isPredicable = 1, neverHasSideEffects = 1 in
875 def LDrib_GP_V4 : LDInst2<(outs IntRegs:$dst),
876 (ins globaladdress:$global, u16Imm:$offset),
877 "$dst=memb(#$global+$offset)",
881 let neverHasSideEffects = 1, isPredicated = 1 in
882 def LDrib_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst),
883 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
884 "if ($src1) $dst=memb(##$global+$offset)",
888 let neverHasSideEffects = 1, isPredicated = 1 in
889 def LDrib_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
890 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
891 "if (!$src1) $dst=memb(##$global+$offset)",
895 let neverHasSideEffects = 1, isPredicated = 1 in
896 def LDrib_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
897 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
898 "if ($src1.new) $dst=memb(##$global+$offset)",
902 let neverHasSideEffects = 1, isPredicated = 1 in
903 def LDrib_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
904 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
905 "if (!$src1.new) $dst=memb(##$global+$offset)",
910 let isPredicable = 1, neverHasSideEffects = 1 in
911 def LDriub_GP_V4 : LDInst2<(outs IntRegs:$dst),
912 (ins globaladdress:$global, u16Imm:$offset),
913 "$dst=memub(#$global+$offset)",
918 let neverHasSideEffects = 1, isPredicated = 1 in
919 def LDriub_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst),
920 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
921 "if ($src1) $dst=memub(##$global+$offset)",
925 let neverHasSideEffects = 1, isPredicated = 1 in
926 def LDriub_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
927 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
928 "if (!$src1) $dst=memub(##$global+$offset)",
932 let neverHasSideEffects = 1, isPredicated = 1 in
933 def LDriub_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
934 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
935 "if ($src1.new) $dst=memub(##$global+$offset)",
939 let neverHasSideEffects = 1, isPredicated = 1 in
940 def LDriub_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
941 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
942 "if (!$src1.new) $dst=memub(##$global+$offset)",
947 let isPredicable = 1, neverHasSideEffects = 1 in
948 def LDrih_GP_V4 : LDInst2<(outs IntRegs:$dst),
949 (ins globaladdress:$global, u16Imm:$offset),
950 "$dst=memh(#$global+$offset)",
955 let neverHasSideEffects = 1, isPredicated = 1 in
956 def LDrih_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst),
957 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
958 "if ($src1) $dst=memh(##$global+$offset)",
962 let neverHasSideEffects = 1, isPredicated = 1 in
963 def LDrih_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
964 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
965 "if (!$src1) $dst=memh(##$global+$offset)",
969 let neverHasSideEffects = 1, isPredicated = 1 in
970 def LDrih_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
971 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
972 "if ($src1.new) $dst=memh(##$global+$offset)",
976 let neverHasSideEffects = 1, isPredicated = 1 in
977 def LDrih_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
978 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
979 "if (!$src1.new) $dst=memh(##$global+$offset)",
984 let isPredicable = 1, neverHasSideEffects = 1 in
985 def LDriuh_GP_V4 : LDInst2<(outs IntRegs:$dst),
986 (ins globaladdress:$global, u16Imm:$offset),
987 "$dst=memuh(#$global+$offset)",
991 let neverHasSideEffects = 1, isPredicated = 1 in
992 def LDriuh_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst),
993 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
994 "if ($src1) $dst=memuh(##$global+$offset)",
998 let neverHasSideEffects = 1, isPredicated = 1 in
999 def LDriuh_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1000 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
1001 "if (!$src1) $dst=memuh(##$global+$offset)",
1005 let neverHasSideEffects = 1, isPredicated = 1 in
1006 def LDriuh_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
1007 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
1008 "if ($src1.new) $dst=memuh(##$global+$offset)",
1012 let neverHasSideEffects = 1, isPredicated = 1 in
1013 def LDriuh_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1014 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
1015 "if (!$src1.new) $dst=memuh(##$global+$offset)",
1019 let isPredicable = 1, neverHasSideEffects = 1 in
1020 def LDriw_GP_V4 : LDInst2<(outs IntRegs:$dst),
1021 (ins globaladdress:$global, u16Imm:$offset),
1022 "$dst=memw(#$global+$offset)",
1027 let neverHasSideEffects = 1, isPredicated = 1 in
1028 def LDriw_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst),
1029 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
1030 "if ($src1) $dst=memw(##$global+$offset)",
1034 let neverHasSideEffects = 1, isPredicated = 1 in
1035 def LDriw_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1036 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
1037 "if (!$src1) $dst=memw(##$global+$offset)",
1042 let neverHasSideEffects = 1, isPredicated = 1 in
1043 def LDriw_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
1044 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
1045 "if ($src1.new) $dst=memw(##$global+$offset)",
1049 let neverHasSideEffects = 1, isPredicated = 1 in
1050 def LDriw_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1051 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),
1052 "if (!$src1.new) $dst=memw(##$global+$offset)",
1057 let isPredicable = 1, neverHasSideEffects = 1 in
1058 def LDd_GP_V4 : LDInst2<(outs DoubleRegs:$dst),
1059 (ins globaladdress:$global),
1060 "$dst=memd(#$global)",
1064 // if (Pv) Rtt=memd(##global)
1065 let neverHasSideEffects = 1, isPredicated = 1 in
1066 def LDd_GP_cPt_V4 : LDInst2<(outs DoubleRegs:$dst),
1067 (ins PredRegs:$src1, globaladdress:$global),
1068 "if ($src1) $dst=memd(##$global)",
1073 // if (!Pv) Rtt=memd(##global)
1074 let neverHasSideEffects = 1, isPredicated = 1 in
1075 def LDd_GP_cNotPt_V4 : LDInst2<(outs DoubleRegs:$dst),
1076 (ins PredRegs:$src1, globaladdress:$global),
1077 "if (!$src1) $dst=memd(##$global)",
1081 // if (Pv) Rtt=memd(##global)
1082 let neverHasSideEffects = 1, isPredicated = 1 in
1083 def LDd_GP_cdnPt_V4 : LDInst2<(outs DoubleRegs:$dst),
1084 (ins PredRegs:$src1, globaladdress:$global),
1085 "if ($src1.new) $dst=memd(##$global)",
1090 // if (!Pv) Rtt=memd(##global)
1091 let neverHasSideEffects = 1, isPredicated = 1 in
1092 def LDd_GP_cdnNotPt_V4 : LDInst2<(outs DoubleRegs:$dst),
1093 (ins PredRegs:$src1, globaladdress:$global),
1094 "if (!$src1.new) $dst=memd(##$global)",
1098 let isPredicable = 1, neverHasSideEffects = 1 in
1099 def LDb_GP_V4 : LDInst2<(outs IntRegs:$dst),
1100 (ins globaladdress:$global),
1101 "$dst=memb(#$global)",
1105 // if (Pv) Rt=memb(##global)
1106 let neverHasSideEffects = 1, isPredicated = 1 in
1107 def LDb_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst),
1108 (ins PredRegs:$src1, globaladdress:$global),
1109 "if ($src1) $dst=memb(##$global)",
1113 // if (!Pv) Rt=memb(##global)
1114 let neverHasSideEffects = 1, isPredicated = 1 in
1115 def LDb_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1116 (ins PredRegs:$src1, globaladdress:$global),
1117 "if (!$src1) $dst=memb(##$global)",
1121 // if (Pv) Rt=memb(##global)
1122 let neverHasSideEffects = 1, isPredicated = 1 in
1123 def LDb_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
1124 (ins PredRegs:$src1, globaladdress:$global),
1125 "if ($src1.new) $dst=memb(##$global)",
1129 // if (!Pv) Rt=memb(##global)
1130 let neverHasSideEffects = 1, isPredicated = 1 in
1131 def LDb_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1132 (ins PredRegs:$src1, globaladdress:$global),
1133 "if (!$src1.new) $dst=memb(##$global)",
1137 let isPredicable = 1, neverHasSideEffects = 1 in
1138 def LDub_GP_V4 : LDInst2<(outs IntRegs:$dst),
1139 (ins globaladdress:$global),
1140 "$dst=memub(#$global)",
1144 // if (Pv) Rt=memub(##global)
1145 let neverHasSideEffects = 1, isPredicated = 1 in
1146 def LDub_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst),
1147 (ins PredRegs:$src1, globaladdress:$global),
1148 "if ($src1) $dst=memub(##$global)",
1153 // if (!Pv) Rt=memub(##global)
1154 let neverHasSideEffects = 1, isPredicated = 1 in
1155 def LDub_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1156 (ins PredRegs:$src1, globaladdress:$global),
1157 "if (!$src1) $dst=memub(##$global)",
1161 // if (Pv) Rt=memub(##global)
1162 let neverHasSideEffects = 1, isPredicated = 1 in
1163 def LDub_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
1164 (ins PredRegs:$src1, globaladdress:$global),
1165 "if ($src1.new) $dst=memub(##$global)",
1170 // if (!Pv) Rt=memub(##global)
1171 let neverHasSideEffects = 1, isPredicated = 1 in
1172 def LDub_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1173 (ins PredRegs:$src1, globaladdress:$global),
1174 "if (!$src1.new) $dst=memub(##$global)",
1178 let isPredicable = 1, neverHasSideEffects = 1 in
1179 def LDh_GP_V4 : LDInst2<(outs IntRegs:$dst),
1180 (ins globaladdress:$global),
1181 "$dst=memh(#$global)",
1185 // if (Pv) Rt=memh(##global)
1186 let neverHasSideEffects = 1, isPredicated = 1 in
1187 def LDh_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst),
1188 (ins PredRegs:$src1, globaladdress:$global),
1189 "if ($src1) $dst=memh(##$global)",
1193 // if (!Pv) Rt=memh(##global)
1194 let neverHasSideEffects = 1, isPredicated = 1 in
1195 def LDh_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1196 (ins PredRegs:$src1, globaladdress:$global),
1197 "if (!$src1) $dst=memh(##$global)",
1201 // if (Pv) Rt=memh(##global)
1202 let neverHasSideEffects = 1, isPredicated = 1 in
1203 def LDh_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
1204 (ins PredRegs:$src1, globaladdress:$global),
1205 "if ($src1.new) $dst=memh(##$global)",
1209 // if (!Pv) Rt=memh(##global)
1210 let neverHasSideEffects = 1, isPredicated = 1 in
1211 def LDh_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1212 (ins PredRegs:$src1, globaladdress:$global),
1213 "if (!$src1.new) $dst=memh(##$global)",
1217 let isPredicable = 1, neverHasSideEffects = 1 in
1218 def LDuh_GP_V4 : LDInst2<(outs IntRegs:$dst),
1219 (ins globaladdress:$global),
1220 "$dst=memuh(#$global)",
1224 // if (Pv) Rt=memuh(##global)
1225 let neverHasSideEffects = 1, isPredicated = 1 in
1226 def LDuh_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst),
1227 (ins PredRegs:$src1, globaladdress:$global),
1228 "if ($src1) $dst=memuh(##$global)",
1232 // if (!Pv) Rt=memuh(##global)
1233 let neverHasSideEffects = 1, isPredicated = 1 in
1234 def LDuh_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1235 (ins PredRegs:$src1, globaladdress:$global),
1236 "if (!$src1) $dst=memuh(##$global)",
1240 // if (Pv) Rt=memuh(##global)
1241 let neverHasSideEffects = 1, isPredicated = 1 in
1242 def LDuh_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
1243 (ins PredRegs:$src1, globaladdress:$global),
1244 "if ($src1.new) $dst=memuh(##$global)",
1248 // if (!Pv) Rt=memuh(##global)
1249 let neverHasSideEffects = 1, isPredicated = 1 in
1250 def LDuh_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1251 (ins PredRegs:$src1, globaladdress:$global),
1252 "if (!$src1.new) $dst=memuh(##$global)",
1256 let isPredicable = 1, neverHasSideEffects = 1 in
1257 def LDw_GP_V4 : LDInst2<(outs IntRegs:$dst),
1258 (ins globaladdress:$global),
1259 "$dst=memw(#$global)",
1263 // if (Pv) Rt=memw(##global)
1264 let neverHasSideEffects = 1, isPredicated = 1 in
1265 def LDw_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst),
1266 (ins PredRegs:$src1, globaladdress:$global),
1267 "if ($src1) $dst=memw(##$global)",
1272 // if (!Pv) Rt=memw(##global)
1273 let neverHasSideEffects = 1, isPredicated = 1 in
1274 def LDw_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1275 (ins PredRegs:$src1, globaladdress:$global),
1276 "if (!$src1) $dst=memw(##$global)",
1280 // if (Pv) Rt=memw(##global)
1281 let neverHasSideEffects = 1, isPredicated = 1 in
1282 def LDw_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
1283 (ins PredRegs:$src1, globaladdress:$global),
1284 "if ($src1.new) $dst=memw(##$global)",
1289 // if (!Pv) Rt=memw(##global)
1290 let neverHasSideEffects = 1, isPredicated = 1 in
1291 def LDw_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
1292 (ins PredRegs:$src1, globaladdress:$global),
1293 "if (!$src1.new) $dst=memw(##$global)",
1299 def : Pat <(atomic_load_64 (HexagonCONST32_GP tglobaladdr:$global)),
1300 (i64 (LDd_GP_V4 tglobaladdr:$global))>,
1303 def : Pat <(atomic_load_32 (HexagonCONST32_GP tglobaladdr:$global)),
1304 (i32 (LDw_GP_V4 tglobaladdr:$global))>,
1307 def : Pat <(atomic_load_16 (HexagonCONST32_GP tglobaladdr:$global)),
1308 (i32 (LDuh_GP_V4 tglobaladdr:$global))>,
1311 def : Pat <(atomic_load_8 (HexagonCONST32_GP tglobaladdr:$global)),
1312 (i32 (LDub_GP_V4 tglobaladdr:$global))>,
1315 // Map from load(globaladdress) -> memw(#foo + 0)
1316 let AddedComplexity = 100 in
1317 def : Pat <(i64 (load (HexagonCONST32_GP tglobaladdr:$global))),
1318 (i64 (LDd_GP_V4 tglobaladdr:$global))>,
1321 // Map from Pd = load(globaladdress) -> Rd = memb(globaladdress), Pd = Rd
1322 let AddedComplexity = 100 in
1323 def : Pat <(i1 (load (HexagonCONST32_GP tglobaladdr:$global))),
1324 (i1 (TFR_PdRs (i32 (LDb_GP_V4 tglobaladdr:$global))))>,
1327 // When the Interprocedural Global Variable optimizer realizes that a certain
1328 // global variable takes only two constant values, it shrinks the global to
1329 // a boolean. Catch those loads here in the following 3 patterns.
1330 let AddedComplexity = 100 in
1331 def : Pat <(i32 (extloadi1 (HexagonCONST32_GP tglobaladdr:$global))),
1332 (i32 (LDb_GP_V4 tglobaladdr:$global))>,
1335 let AddedComplexity = 100 in
1336 def : Pat <(i32 (sextloadi1 (HexagonCONST32_GP tglobaladdr:$global))),
1337 (i32 (LDb_GP_V4 tglobaladdr:$global))>,
1340 // Map from load(globaladdress) -> memb(#foo)
1341 let AddedComplexity = 100 in
1342 def : Pat <(i32 (extloadi8 (HexagonCONST32_GP tglobaladdr:$global))),
1343 (i32 (LDb_GP_V4 tglobaladdr:$global))>,
1346 // Map from load(globaladdress) -> memb(#foo)
1347 let AddedComplexity = 100 in
1348 def : Pat <(i32 (sextloadi8 (HexagonCONST32_GP tglobaladdr:$global))),
1349 (i32 (LDb_GP_V4 tglobaladdr:$global))>,
1352 let AddedComplexity = 100 in
1353 def : Pat <(i32 (zextloadi1 (HexagonCONST32_GP tglobaladdr:$global))),
1354 (i32 (LDub_GP_V4 tglobaladdr:$global))>,
1357 // Map from load(globaladdress) -> memub(#foo)
1358 let AddedComplexity = 100 in
1359 def : Pat <(i32 (zextloadi8 (HexagonCONST32_GP tglobaladdr:$global))),
1360 (i32 (LDub_GP_V4 tglobaladdr:$global))>,
1363 // Map from load(globaladdress) -> memh(#foo)
1364 let AddedComplexity = 100 in
1365 def : Pat <(i32 (extloadi16 (HexagonCONST32_GP tglobaladdr:$global))),
1366 (i32 (LDh_GP_V4 tglobaladdr:$global))>,
1369 // Map from load(globaladdress) -> memh(#foo)
1370 let AddedComplexity = 100 in
1371 def : Pat <(i32 (sextloadi16 (HexagonCONST32_GP tglobaladdr:$global))),
1372 (i32 (LDh_GP_V4 tglobaladdr:$global))>,
1375 // Map from load(globaladdress) -> memuh(#foo)
1376 let AddedComplexity = 100 in
1377 def : Pat <(i32 (zextloadi16 (HexagonCONST32_GP tglobaladdr:$global))),
1378 (i32 (LDuh_GP_V4 tglobaladdr:$global))>,
1381 // Map from load(globaladdress) -> memw(#foo)
1382 let AddedComplexity = 100 in
1383 def : Pat <(i32 (load (HexagonCONST32_GP tglobaladdr:$global))),
1384 (i32 (LDw_GP_V4 tglobaladdr:$global))>,
1387 def : Pat <(atomic_load_64 (add (HexagonCONST32_GP tglobaladdr:$global),
1388 u16ImmPred:$offset)),
1389 (i64 (LDrid_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
1392 def : Pat <(atomic_load_32 (add (HexagonCONST32_GP tglobaladdr:$global),
1393 u16ImmPred:$offset)),
1394 (i32 (LDriw_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
1397 def : Pat <(atomic_load_16 (add (HexagonCONST32_GP tglobaladdr:$global),
1398 u16ImmPred:$offset)),
1399 (i32 (LDriuh_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
1402 def : Pat <(atomic_load_8 (add (HexagonCONST32_GP tglobaladdr:$global),
1403 u16ImmPred:$offset)),
1404 (i32 (LDriub_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
1407 // Map from load(globaladdress + x) -> memd(#foo + x)
1408 let AddedComplexity = 100 in
1409 def : Pat <(i64 (load (add (HexagonCONST32_GP tglobaladdr:$global),
1410 u16ImmPred:$offset))),
1411 (i64 (LDrid_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
1414 // Map from load(globaladdress + x) -> memb(#foo + x)
1415 let AddedComplexity = 100 in
1416 def : Pat <(i32 (extloadi8 (add (HexagonCONST32_GP tglobaladdr:$global),
1417 u16ImmPred:$offset))),
1418 (i32 (LDrib_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
1421 // Map from load(globaladdress + x) -> memb(#foo + x)
1422 let AddedComplexity = 100 in
1423 def : Pat <(i32 (sextloadi8 (add (HexagonCONST32_GP tglobaladdr:$global),
1424 u16ImmPred:$offset))),
1425 (i32 (LDrib_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
1428 // Map from load(globaladdress + x) -> memub(#foo + x)
1429 let AddedComplexity = 100 in
1430 def : Pat <(i32 (zextloadi8 (add (HexagonCONST32_GP tglobaladdr:$global),
1431 u16ImmPred:$offset))),
1432 (i32 (LDriub_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
1435 // Map from load(globaladdress + x) -> memuh(#foo + x)
1436 let AddedComplexity = 100 in
1437 def : Pat <(i32 (extloadi16 (add (HexagonCONST32_GP tglobaladdr:$global),
1438 u16ImmPred:$offset))),
1439 (i32 (LDrih_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
1442 // Map from load(globaladdress + x) -> memh(#foo + x)
1443 let AddedComplexity = 100 in
1444 def : Pat <(i32 (sextloadi16 (add (HexagonCONST32_GP tglobaladdr:$global),
1445 u16ImmPred:$offset))),
1446 (i32 (LDrih_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
1450 // Map from load(globaladdress + x) -> memuh(#foo + x)
1451 let AddedComplexity = 100 in
1452 def : Pat <(i32 (zextloadi16 (add (HexagonCONST32_GP tglobaladdr:$global),
1453 u16ImmPred:$offset))),
1454 (i32 (LDriuh_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
1457 // Map from load(globaladdress + x) -> memw(#foo + x)
1458 let AddedComplexity = 100 in
1459 def : Pat <(i32 (load (add (HexagonCONST32_GP tglobaladdr:$global),
1460 u16ImmPred:$offset))),
1461 (i32 (LDriw_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,
1465 //===----------------------------------------------------------------------===//
1467 //===----------------------------------------------------------------------===//
1469 //===----------------------------------------------------------------------===//
1471 //===----------------------------------------------------------------------===//
1473 /// Assumptions::: ****** DO NOT IGNORE ********
1474 /// 1. Make sure that in post increment store, the zero'th operand is always the
1475 /// post increment operand.
1476 /// 2. Make sure that the store value operand(Rt/Rtt) in a store is always the
1481 def STrid_abs_setimm_V4 : STInst2<(outs IntRegs:$dst1),
1482 (ins DoubleRegs:$src1, u6Imm:$src2),
1483 "memd($dst1=#$src2) = $src1",
1488 def STrib_abs_setimm_V4 : STInst2<(outs IntRegs:$dst1),
1489 (ins IntRegs:$src1, u6Imm:$src2),
1490 "memb($dst1=#$src2) = $src1",
1495 def STrih_abs_setimm_V4 : STInst2<(outs IntRegs:$dst1),
1496 (ins IntRegs:$src1, u6Imm:$src2),
1497 "memh($dst1=#$src2) = $src1",
1502 def STriw_abs_setimm_V4 : STInst2<(outs IntRegs:$dst1),
1503 (ins IntRegs:$src1, u6Imm:$src2),
1504 "memw($dst1=#$src2) = $src1",
1509 def STrid_abs_set_V4 : STInst2<(outs IntRegs:$dst1),
1510 (ins DoubleRegs:$src1, globaladdress:$src2),
1511 "memd($dst1=##$src2) = $src1",
1516 def STrib_abs_set_V4 : STInst2<(outs IntRegs:$dst1),
1517 (ins IntRegs:$src1, globaladdress:$src2),
1518 "memb($dst1=##$src2) = $src1",
1523 def STrih_abs_set_V4 : STInst2<(outs IntRegs:$dst1),
1524 (ins IntRegs:$src1, globaladdress:$src2),
1525 "memh($dst1=##$src2) = $src1",
1530 def STriw_abs_set_V4 : STInst2<(outs IntRegs:$dst1),
1531 (ins IntRegs:$src1, globaladdress:$src2),
1532 "memw($dst1=##$src2) = $src1",
1537 // multiclass for store instructions with base + register offset addressing
1539 multiclass ST_Idxd_shl_Pbase<string mnemonic, RegisterClass RC, bit isNot,
1541 let PNewValue = #!if(isPredNew, "new", "") in
1542 def #NAME# : STInst2<(outs),
1543 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
1545 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1546 ") ")#mnemonic#"($src2+$src3<<#$src4) = $src5",
1551 multiclass ST_Idxd_shl_Pred<string mnemonic, RegisterClass RC, bit PredNot> {
1552 let PredSense = #!if(PredNot, "false", "true") in {
1553 defm _c#NAME# : ST_Idxd_shl_Pbase<mnemonic, RC, PredNot, 0>;
1555 defm _cdn#NAME# : ST_Idxd_shl_Pbase<mnemonic, RC, PredNot, 1>;
1559 let isNVStorable = 1 in
1560 multiclass ST_Idxd_shl<string mnemonic, string CextOp, RegisterClass RC> {
1561 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed_shl in {
1562 let isPredicable = 1 in
1563 def #NAME#_V4 : STInst2<(outs),
1564 (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$src3, RC:$src4),
1565 #mnemonic#"($src1+$src2<<#$src3) = $src4",
1569 let isPredicated = 1 in {
1570 defm Pt_V4 : ST_Idxd_shl_Pred<mnemonic, RC, 0 >;
1571 defm NotPt_V4 : ST_Idxd_shl_Pred<mnemonic, RC, 1>;
1576 // multiclass for new-value store instructions with base + register offset
1578 multiclass ST_Idxd_shl_Pbase_nv<string mnemonic, RegisterClass RC, bit isNot,
1580 let PNewValue = #!if(isPredNew, "new", "") in
1581 def #NAME#_nv_V4 : NVInst_V4<(outs),
1582 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
1584 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1585 ") ")#mnemonic#"($src2+$src3<<#$src4) = $src5.new",
1590 multiclass ST_Idxd_shl_Pred_nv<string mnemonic, RegisterClass RC, bit PredNot> {
1591 let PredSense = #!if(PredNot, "false", "true") in {
1592 defm _c#NAME# : ST_Idxd_shl_Pbase_nv<mnemonic, RC, PredNot, 0>;
1594 defm _cdn#NAME# : ST_Idxd_shl_Pbase_nv<mnemonic, RC, PredNot, 1>;
1598 let mayStore = 1, isNVStore = 1 in
1599 multiclass ST_Idxd_shl_nv<string mnemonic, string CextOp, RegisterClass RC> {
1600 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed_shl in {
1601 let isPredicable = 1 in
1602 def #NAME#_nv_V4 : NVInst_V4<(outs),
1603 (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$src3, RC:$src4),
1604 #mnemonic#"($src1+$src2<<#$src3) = $src4.new",
1608 let isPredicated = 1 in {
1609 defm Pt : ST_Idxd_shl_Pred_nv<mnemonic, RC, 0 >;
1610 defm NotPt : ST_Idxd_shl_Pred_nv<mnemonic, RC, 1>;
1615 let addrMode = BaseRegOffset, neverHasSideEffects = 1,
1616 validSubTargets = HasV4SubT in {
1617 defm STrib_indexed_shl: ST_Idxd_shl<"memb", "STrib", IntRegs>,
1618 ST_Idxd_shl_nv<"memb", "STrib", IntRegs>, AddrModeRel;
1620 defm STrih_indexed_shl: ST_Idxd_shl<"memh", "STrih", IntRegs>,
1621 ST_Idxd_shl_nv<"memh", "STrih", IntRegs>, AddrModeRel;
1623 defm STriw_indexed_shl: ST_Idxd_shl<"memw", "STriw", IntRegs>,
1624 ST_Idxd_shl_nv<"memw", "STriw", IntRegs>, AddrModeRel;
1626 let isNVStorable = 0 in
1627 defm STrid_indexed_shl: ST_Idxd_shl<"memd", "STrid", DoubleRegs>, AddrModeRel;
1630 let Predicates = [HasV4T], AddedComplexity = 10 in {
1631 def : Pat<(truncstorei8 (i32 IntRegs:$src4),
1632 (add IntRegs:$src1, (shl IntRegs:$src2,
1634 (STrib_indexed_shl_V4 IntRegs:$src1, IntRegs:$src2,
1635 u2ImmPred:$src3, IntRegs:$src4)>;
1637 def : Pat<(truncstorei16 (i32 IntRegs:$src4),
1638 (add IntRegs:$src1, (shl IntRegs:$src2,
1640 (STrih_indexed_shl_V4 IntRegs:$src1, IntRegs:$src2,
1641 u2ImmPred:$src3, IntRegs:$src4)>;
1643 def : Pat<(store (i32 IntRegs:$src4),
1644 (add IntRegs:$src1, (shl IntRegs:$src2, u2ImmPred:$src3))),
1645 (STriw_indexed_shl_V4 IntRegs:$src1, IntRegs:$src2,
1646 u2ImmPred:$src3, IntRegs:$src4)>;
1648 def : Pat<(store (i64 DoubleRegs:$src4),
1649 (add IntRegs:$src1, (shl IntRegs:$src2, u2ImmPred:$src3))),
1650 (STrid_indexed_shl_V4 IntRegs:$src1, IntRegs:$src2,
1651 u2ImmPred:$src3, DoubleRegs:$src4)>;
1654 // memd(Ru<<#u2+#U6)=Rtt
1655 let AddedComplexity = 10 in
1656 def STrid_shl_V4 : STInst<(outs),
1657 (ins IntRegs:$src1, u2Imm:$src2, u6Imm:$src3, DoubleRegs:$src4),
1658 "memd($src1<<#$src2+#$src3) = $src4",
1659 [(store (i64 DoubleRegs:$src4),
1660 (add (shl (i32 IntRegs:$src1), u2ImmPred:$src2),
1661 u6ImmPred:$src3))]>,
1664 // memd(Rx++#s4:3)=Rtt
1665 // memd(Rx++#s4:3:circ(Mu))=Rtt
1666 // memd(Rx++I:circ(Mu))=Rtt
1668 // memd(Rx++Mu:brev)=Rtt
1669 // memd(gp+#u16:3)=Rtt
1671 // Store doubleword conditionally.
1672 // if ([!]Pv[.new]) memd(#u6)=Rtt
1673 // TODO: needs to be implemented.
1675 // if ([!]Pv[.new]) memd(Rx++#s4:3)=Rtt
1676 // if (Pv) memd(Rx++#s4:3)=Rtt
1677 // if (Pv.new) memd(Rx++#s4:3)=Rtt
1678 let AddedComplexity = 10, neverHasSideEffects = 1,
1680 def POST_STdri_cdnPt_V4 : STInst2PI<(outs IntRegs:$dst),
1681 (ins PredRegs:$src1, DoubleRegs:$src2, IntRegs:$src3,
1683 "if ($src1.new) memd($src3++#$offset) = $src2",
1688 // if (!Pv) memd(Rx++#s4:3)=Rtt
1689 // if (!Pv.new) memd(Rx++#s4:3)=Rtt
1690 let AddedComplexity = 10, neverHasSideEffects = 1,
1692 def POST_STdri_cdnNotPt_V4 : STInst2PI<(outs IntRegs:$dst),
1693 (ins PredRegs:$src1, DoubleRegs:$src2, IntRegs:$src3,
1695 "if (!$src1.new) memd($src3++#$offset) = $src2",
1701 // multiclass for store instructions with base + immediate offset
1702 // addressing mode and immediate stored value.
1703 multiclass ST_Imm_Pbase<string mnemonic, Operand OffsetOp, bit isNot,
1705 let PNewValue = #!if(isPredNew, "new", "") in
1706 def #NAME# : STInst2<(outs),
1707 (ins PredRegs:$src1, IntRegs:$src2, OffsetOp:$src3, s6Ext:$src4),
1708 #!if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1709 ") ")#mnemonic#"($src2+#$src3) = #$src4",
1714 multiclass ST_Imm_Pred<string mnemonic, Operand OffsetOp, bit PredNot> {
1715 let PredSense = #!if(PredNot, "false", "true") in {
1716 defm _c#NAME# : ST_Imm_Pbase<mnemonic, OffsetOp, PredNot, 0>;
1718 defm _cdn#NAME# : ST_Imm_Pbase<mnemonic, OffsetOp, PredNot, 1>;
1722 let isExtendable = 1, isExtentSigned = 1, neverHasSideEffects = 1 in
1723 multiclass ST_Imm<string mnemonic, string CextOp, Operand OffsetOp> {
1724 let CextOpcode = CextOp, BaseOpcode = CextOp#_imm in {
1725 let opExtendable = 2, opExtentBits = 8, isPredicable = 1 in
1726 def #NAME#_V4 : STInst2<(outs),
1727 (ins IntRegs:$src1, OffsetOp:$src2, s8Ext:$src3),
1728 #mnemonic#"($src1+#$src2) = #$src3",
1732 let opExtendable = 3, opExtentBits = 6, isPredicated = 1 in {
1733 defm Pt_V4 : ST_Imm_Pred<mnemonic, OffsetOp, 0>;
1734 defm NotPt_V4 : ST_Imm_Pred<mnemonic, OffsetOp, 1 >;
1739 let addrMode = BaseImmOffset, InputType = "imm",
1740 validSubTargets = HasV4SubT in {
1741 defm STrib_imm : ST_Imm<"memb", "STrib", u6_0Imm>, ImmRegRel;
1742 defm STrih_imm : ST_Imm<"memh", "STrih", u6_1Imm>, ImmRegRel;
1743 defm STriw_imm : ST_Imm<"memw", "STriw", u6_2Imm>, ImmRegRel;
1746 let Predicates = [HasV4T], AddedComplexity = 10 in {
1747 def: Pat<(truncstorei8 s8ExtPred:$src3, (add IntRegs:$src1, u6_0ImmPred:$src2)),
1748 (STrib_imm_V4 IntRegs:$src1, u6_0ImmPred:$src2, s8ExtPred:$src3)>;
1750 def: Pat<(truncstorei16 s8ExtPred:$src3, (add IntRegs:$src1,
1751 u6_1ImmPred:$src2)),
1752 (STrih_imm_V4 IntRegs:$src1, u6_1ImmPred:$src2, s8ExtPred:$src3)>;
1754 def: Pat<(store s8ExtPred:$src3, (add IntRegs:$src1, u6_2ImmPred:$src2)),
1755 (STriw_imm_V4 IntRegs:$src1, u6_2ImmPred:$src2, s8ExtPred:$src3)>;
1758 let AddedComplexity = 6 in
1759 def : Pat <(truncstorei8 s8ExtPred:$src2, (i32 IntRegs:$src1)),
1760 (STrib_imm_V4 IntRegs:$src1, 0, s8ExtPred:$src2)>,
1763 // memb(Ru<<#u2+#U6)=Rt
1764 let AddedComplexity = 10 in
1765 def STrib_shl_V4 : STInst<(outs),
1766 (ins IntRegs:$src1, u2Imm:$src2, u6Imm:$src3, IntRegs:$src4),
1767 "memb($src1<<#$src2+#$src3) = $src4",
1768 [(truncstorei8 (i32 IntRegs:$src4),
1769 (add (shl (i32 IntRegs:$src1), u2ImmPred:$src2),
1770 u6ImmPred:$src3))]>,
1773 // memb(Rx++#s4:0:circ(Mu))=Rt
1774 // memb(Rx++I:circ(Mu))=Rt
1776 // memb(Rx++Mu:brev)=Rt
1777 // memb(gp+#u16:0)=Rt
1780 // Store byte conditionally.
1781 // if ([!]Pv[.new]) memb(#u6)=Rt
1782 // if ([!]Pv[.new]) memb(Rx++#s4:0)=Rt
1783 // if (Pv) memb(Rx++#s4:0)=Rt
1784 // if (Pv.new) memb(Rx++#s4:0)=Rt
1787 def POST_STbri_cdnPt_V4 : STInst2PI<(outs IntRegs:$dst),
1788 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_0Imm:$offset),
1789 "if ($src1.new) memb($src3++#$offset) = $src2",
1793 // if (!Pv) memb(Rx++#s4:0)=Rt
1794 // if (!Pv.new) memb(Rx++#s4:0)=Rt
1797 def POST_STbri_cdnNotPt_V4 : STInst2PI<(outs IntRegs:$dst),
1798 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_0Imm:$offset),
1799 "if (!$src1.new) memb($src3++#$offset) = $src2",
1805 // TODO: needs to be implemented
1806 // memh(Re=#U6)=Rt.H
1807 // memh(Rs+#s11:1)=Rt.H
1808 let AddedComplexity = 6 in
1809 def : Pat <(truncstorei16 s8ExtPred:$src2, (i32 IntRegs:$src1)),
1810 (STrih_imm_V4 IntRegs:$src1, 0, s8ExtPred:$src2)>,
1813 // memh(Rs+Ru<<#u2)=Rt.H
1814 // TODO: needs to be implemented.
1816 // memh(Ru<<#u2+#U6)=Rt.H
1817 // memh(Ru<<#u2+#U6)=Rt
1818 let AddedComplexity = 10 in
1819 def STrih_shl_V4 : STInst<(outs),
1820 (ins IntRegs:$src1, u2Imm:$src2, u6Imm:$src3, IntRegs:$src4),
1821 "memh($src1<<#$src2+#$src3) = $src4",
1822 [(truncstorei16 (i32 IntRegs:$src4),
1823 (add (shl (i32 IntRegs:$src1), u2ImmPred:$src2),
1824 u6ImmPred:$src3))]>,
1827 // memh(Rx++#s4:1:circ(Mu))=Rt.H
1828 // memh(Rx++#s4:1:circ(Mu))=Rt
1829 // memh(Rx++I:circ(Mu))=Rt.H
1830 // memh(Rx++I:circ(Mu))=Rt
1831 // memh(Rx++Mu)=Rt.H
1833 // memh(Rx++Mu:brev)=Rt.H
1834 // memh(Rx++Mu:brev)=Rt
1835 // memh(gp+#u16:1)=Rt
1836 // if ([!]Pv[.new]) memh(#u6)=Rt.H
1837 // if ([!]Pv[.new]) memh(#u6)=Rt
1840 // if ([!]Pv[.new]) memh(Rs+#u6:1)=Rt.H
1841 // TODO: needs to be implemented.
1843 // if ([!]Pv[.new]) memh(Rx++#s4:1)=Rt.H
1844 // TODO: Needs to be implemented.
1846 // if ([!]Pv[.new]) memh(Rx++#s4:1)=Rt
1847 // if (Pv) memh(Rx++#s4:1)=Rt
1848 // if (Pv.new) memh(Rx++#s4:1)=Rt
1851 def POST_SThri_cdnPt_V4 : STInst2PI<(outs IntRegs:$dst),
1852 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_1Imm:$offset),
1853 "if ($src1.new) memh($src3++#$offset) = $src2",
1857 // if (!Pv) memh(Rx++#s4:1)=Rt
1858 // if (!Pv.new) memh(Rx++#s4:1)=Rt
1861 def POST_SThri_cdnNotPt_V4 : STInst2PI<(outs IntRegs:$dst),
1862 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_1Imm:$offset),
1863 "if (!$src1.new) memh($src3++#$offset) = $src2",
1870 // TODO: Needs to be implemented.
1873 let neverHasSideEffects = 1 in
1874 def STriw_pred_V4 : STInst2<(outs),
1875 (ins MEMri:$addr, PredRegs:$src1),
1876 "Error; should not emit",
1880 let AddedComplexity = 6 in
1881 def : Pat <(store s8ExtPred:$src2, (i32 IntRegs:$src1)),
1882 (STriw_imm_V4 IntRegs:$src1, 0, s8ExtPred:$src2)>,
1885 // memw(Ru<<#u2+#U6)=Rt
1886 let AddedComplexity = 10 in
1887 def STriw_shl_V4 : STInst<(outs),
1888 (ins IntRegs:$src1, u2Imm:$src2, u6Imm:$src3, IntRegs:$src4),
1889 "memw($src1<<#$src2+#$src3) = $src4",
1890 [(store (i32 IntRegs:$src4),
1891 (add (shl (i32 IntRegs:$src1), u2ImmPred:$src2),
1892 u6ImmPred:$src3))]>,
1895 // memw(Rx++#s4:2)=Rt
1896 // memw(Rx++#s4:2:circ(Mu))=Rt
1897 // memw(Rx++I:circ(Mu))=Rt
1899 // memw(Rx++Mu:brev)=Rt
1900 // memw(gp+#u16:2)=Rt
1903 // if ([!]Pv[.new]) memw(Rx++#s4:2)=Rt
1904 // if (Pv) memw(Rx++#s4:2)=Rt
1905 // if (Pv.new) memw(Rx++#s4:2)=Rt
1908 def POST_STwri_cdnPt_V4 : STInst2PI<(outs IntRegs:$dst),
1909 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset),
1910 "if ($src1.new) memw($src3++#$offset) = $src2",
1914 // if (!Pv) memw(Rx++#s4:2)=Rt
1915 // if (!Pv.new) memw(Rx++#s4:2)=Rt
1918 def POST_STwri_cdnNotPt_V4 : STInst2PI<(outs IntRegs:$dst),
1919 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset),
1920 "if (!$src1.new) memw($src3++#$offset) = $src2",
1925 /// store to global address
1927 let isPredicable = 1, neverHasSideEffects = 1 in
1928 def STrid_GP_V4 : STInst2<(outs),
1929 (ins globaladdress:$global, u16Imm:$offset, DoubleRegs:$src),
1930 "memd(#$global+$offset) = $src",
1934 let neverHasSideEffects = 1, isPredicated = 1 in
1935 def STrid_GP_cPt_V4 : STInst2<(outs),
1936 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
1938 "if ($src1) memd(##$global+$offset) = $src2",
1942 let neverHasSideEffects = 1, isPredicated = 1 in
1943 def STrid_GP_cNotPt_V4 : STInst2<(outs),
1944 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
1946 "if (!$src1) memd(##$global+$offset) = $src2",
1950 let neverHasSideEffects = 1, isPredicated = 1 in
1951 def STrid_GP_cdnPt_V4 : STInst2<(outs),
1952 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
1954 "if ($src1.new) memd(##$global+$offset) = $src2",
1958 let neverHasSideEffects = 1, isPredicated = 1 in
1959 def STrid_GP_cdnNotPt_V4 : STInst2<(outs),
1960 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
1962 "if (!$src1.new) memd(##$global+$offset) = $src2",
1966 let isPredicable = 1, neverHasSideEffects = 1 in
1967 def STrib_GP_V4 : STInst2<(outs),
1968 (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),
1969 "memb(#$global+$offset) = $src",
1973 let neverHasSideEffects = 1, isPredicated = 1 in
1974 def STrib_GP_cPt_V4 : STInst2<(outs),
1975 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
1977 "if ($src1) memb(##$global+$offset) = $src2",
1981 let neverHasSideEffects = 1, isPredicated = 1 in
1982 def STrib_GP_cNotPt_V4 : STInst2<(outs),
1983 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
1985 "if (!$src1) memb(##$global+$offset) = $src2",
1989 let neverHasSideEffects = 1, isPredicated = 1 in
1990 def STrib_GP_cdnPt_V4 : STInst2<(outs),
1991 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
1993 "if ($src1.new) memb(##$global+$offset) = $src2",
1997 let neverHasSideEffects = 1, isPredicated = 1 in
1998 def STrib_GP_cdnNotPt_V4 : STInst2<(outs),
1999 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2001 "if (!$src1.new) memb(##$global+$offset) = $src2",
2005 let isPredicable = 1, neverHasSideEffects = 1 in
2006 def STrih_GP_V4 : STInst2<(outs),
2007 (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),
2008 "memh(#$global+$offset) = $src",
2012 let neverHasSideEffects = 1, isPredicated = 1 in
2013 def STrih_GP_cPt_V4 : STInst2<(outs),
2014 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2016 "if ($src1) memh(##$global+$offset) = $src2",
2020 let neverHasSideEffects = 1, isPredicated = 1 in
2021 def STrih_GP_cNotPt_V4 : STInst2<(outs),
2022 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2024 "if (!$src1) memh(##$global+$offset) = $src2",
2028 let neverHasSideEffects = 1, isPredicated = 1 in
2029 def STrih_GP_cdnPt_V4 : STInst2<(outs),
2030 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2032 "if ($src1.new) memh(##$global+$offset) = $src2",
2036 let neverHasSideEffects = 1, isPredicated = 1 in
2037 def STrih_GP_cdnNotPt_V4 : STInst2<(outs),
2038 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2040 "if (!$src1.new) memh(##$global+$offset) = $src2",
2044 let isPredicable = 1, neverHasSideEffects = 1 in
2045 def STriw_GP_V4 : STInst2<(outs),
2046 (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),
2047 "memw(#$global+$offset) = $src",
2051 let neverHasSideEffects = 1, isPredicated = 1 in
2052 def STriw_GP_cPt_V4 : STInst2<(outs),
2053 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2055 "if ($src1) memw(##$global+$offset) = $src2",
2059 let neverHasSideEffects = 1, isPredicated = 1 in
2060 def STriw_GP_cNotPt_V4 : STInst2<(outs),
2061 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2063 "if (!$src1) memw(##$global+$offset) = $src2",
2067 let neverHasSideEffects = 1, isPredicated = 1 in
2068 def STriw_GP_cdnPt_V4 : STInst2<(outs),
2069 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2071 "if ($src1.new) memw(##$global+$offset) = $src2",
2075 let neverHasSideEffects = 1, isPredicated = 1 in
2076 def STriw_GP_cdnNotPt_V4 : STInst2<(outs),
2077 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2079 "if (!$src1.new) memw(##$global+$offset) = $src2",
2083 // memd(#global)=Rtt
2084 let isPredicable = 1, neverHasSideEffects = 1 in
2085 def STd_GP_V4 : STInst2<(outs),
2086 (ins globaladdress:$global, DoubleRegs:$src),
2087 "memd(#$global) = $src",
2091 // if (Pv) memd(##global) = Rtt
2092 let neverHasSideEffects = 1, isPredicated = 1 in
2093 def STd_GP_cPt_V4 : STInst2<(outs),
2094 (ins PredRegs:$src1, globaladdress:$global, DoubleRegs:$src2),
2095 "if ($src1) memd(##$global) = $src2",
2099 // if (!Pv) memd(##global) = Rtt
2100 let neverHasSideEffects = 1, isPredicated = 1 in
2101 def STd_GP_cNotPt_V4 : STInst2<(outs),
2102 (ins PredRegs:$src1, globaladdress:$global, DoubleRegs:$src2),
2103 "if (!$src1) memd(##$global) = $src2",
2107 // if (Pv) memd(##global) = Rtt
2108 let neverHasSideEffects = 1, isPredicated = 1 in
2109 def STd_GP_cdnPt_V4 : STInst2<(outs),
2110 (ins PredRegs:$src1, globaladdress:$global, DoubleRegs:$src2),
2111 "if ($src1.new) memd(##$global) = $src2",
2115 // if (!Pv) memd(##global) = Rtt
2116 let neverHasSideEffects = 1, isPredicated = 1 in
2117 def STd_GP_cdnNotPt_V4 : STInst2<(outs),
2118 (ins PredRegs:$src1, globaladdress:$global, DoubleRegs:$src2),
2119 "if (!$src1.new) memd(##$global) = $src2",
2124 let isPredicable = 1, neverHasSideEffects = 1 in
2125 def STb_GP_V4 : STInst2<(outs),
2126 (ins globaladdress:$global, IntRegs:$src),
2127 "memb(#$global) = $src",
2131 // if (Pv) memb(##global) = Rt
2132 let neverHasSideEffects = 1, isPredicated = 1 in
2133 def STb_GP_cPt_V4 : STInst2<(outs),
2134 (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2135 "if ($src1) memb(##$global) = $src2",
2139 // if (!Pv) memb(##global) = Rt
2140 let neverHasSideEffects = 1, isPredicated = 1 in
2141 def STb_GP_cNotPt_V4 : STInst2<(outs),
2142 (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2143 "if (!$src1) memb(##$global) = $src2",
2147 // if (Pv) memb(##global) = Rt
2148 let neverHasSideEffects = 1, isPredicated = 1 in
2149 def STb_GP_cdnPt_V4 : STInst2<(outs),
2150 (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2151 "if ($src1.new) memb(##$global) = $src2",
2155 // if (!Pv) memb(##global) = Rt
2156 let neverHasSideEffects = 1, isPredicated = 1 in
2157 def STb_GP_cdnNotPt_V4 : STInst2<(outs),
2158 (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2159 "if (!$src1.new) memb(##$global) = $src2",
2164 let isPredicable = 1, neverHasSideEffects = 1 in
2165 def STh_GP_V4 : STInst2<(outs),
2166 (ins globaladdress:$global, IntRegs:$src),
2167 "memh(#$global) = $src",
2171 // if (Pv) memh(##global) = Rt
2172 let neverHasSideEffects = 1, isPredicated = 1 in
2173 def STh_GP_cPt_V4 : STInst2<(outs),
2174 (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2175 "if ($src1) memh(##$global) = $src2",
2179 // if (!Pv) memh(##global) = Rt
2180 let neverHasSideEffects = 1, isPredicated = 1 in
2181 def STh_GP_cNotPt_V4 : STInst2<(outs),
2182 (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2183 "if (!$src1) memh(##$global) = $src2",
2187 // if (Pv) memh(##global) = Rt
2188 let neverHasSideEffects = 1, isPredicated = 1 in
2189 def STh_GP_cdnPt_V4 : STInst2<(outs),
2190 (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2191 "if ($src1.new) memh(##$global) = $src2",
2195 // if (!Pv) memh(##global) = Rt
2196 let neverHasSideEffects = 1, isPredicated = 1 in
2197 def STh_GP_cdnNotPt_V4 : STInst2<(outs),
2198 (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2199 "if (!$src1.new) memh(##$global) = $src2",
2204 let isPredicable = 1, neverHasSideEffects = 1 in
2205 def STw_GP_V4 : STInst2<(outs),
2206 (ins globaladdress:$global, IntRegs:$src),
2207 "memw(#$global) = $src",
2211 // if (Pv) memw(##global) = Rt
2212 let neverHasSideEffects = 1, isPredicated = 1 in
2213 def STw_GP_cPt_V4 : STInst2<(outs),
2214 (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2215 "if ($src1) memw(##$global) = $src2",
2219 // if (!Pv) memw(##global) = Rt
2220 let neverHasSideEffects = 1, isPredicated = 1 in
2221 def STw_GP_cNotPt_V4 : STInst2<(outs),
2222 (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2223 "if (!$src1) memw(##$global) = $src2",
2227 // if (Pv) memw(##global) = Rt
2228 let neverHasSideEffects = 1, isPredicated = 1 in
2229 def STw_GP_cdnPt_V4 : STInst2<(outs),
2230 (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2231 "if ($src1.new) memw(##$global) = $src2",
2235 // if (!Pv) memw(##global) = Rt
2236 let neverHasSideEffects = 1, isPredicated = 1 in
2237 def STw_GP_cdnNotPt_V4 : STInst2<(outs),
2238 (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2239 "if (!$src1.new) memw(##$global) = $src2",
2243 // 64 bit atomic store
2244 def : Pat <(atomic_store_64 (HexagonCONST32_GP tglobaladdr:$global),
2245 (i64 DoubleRegs:$src1)),
2246 (STd_GP_V4 tglobaladdr:$global, (i64 DoubleRegs:$src1))>,
2249 // Map from store(globaladdress) -> memd(#foo)
2250 let AddedComplexity = 100 in
2251 def : Pat <(store (i64 DoubleRegs:$src1),
2252 (HexagonCONST32_GP tglobaladdr:$global)),
2253 (STd_GP_V4 tglobaladdr:$global, (i64 DoubleRegs:$src1))>,
2256 // 8 bit atomic store
2257 def : Pat < (atomic_store_8 (HexagonCONST32_GP tglobaladdr:$global),
2258 (i32 IntRegs:$src1)),
2259 (STb_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>,
2262 // Map from store(globaladdress) -> memb(#foo)
2263 let AddedComplexity = 100 in
2264 def : Pat<(truncstorei8 (i32 IntRegs:$src1),
2265 (HexagonCONST32_GP tglobaladdr:$global)),
2266 (STb_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>,
2269 // Map from "i1 = constant<-1>; memw(CONST32(#foo)) = i1"
2270 // to "r0 = 1; memw(#foo) = r0"
2271 let AddedComplexity = 100 in
2272 def : Pat<(store (i1 -1), (HexagonCONST32_GP tglobaladdr:$global)),
2273 (STb_GP_V4 tglobaladdr:$global, (TFRI 1))>,
2276 def : Pat<(atomic_store_16 (HexagonCONST32_GP tglobaladdr:$global),
2277 (i32 IntRegs:$src1)),
2278 (STh_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>,
2281 // Map from store(globaladdress) -> memh(#foo)
2282 let AddedComplexity = 100 in
2283 def : Pat<(truncstorei16 (i32 IntRegs:$src1),
2284 (HexagonCONST32_GP tglobaladdr:$global)),
2285 (STh_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>,
2288 // 32 bit atomic store
2289 def : Pat<(atomic_store_32 (HexagonCONST32_GP tglobaladdr:$global),
2290 (i32 IntRegs:$src1)),
2291 (STw_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>,
2294 // Map from store(globaladdress) -> memw(#foo)
2295 let AddedComplexity = 100 in
2296 def : Pat<(store (i32 IntRegs:$src1), (HexagonCONST32_GP tglobaladdr:$global)),
2297 (STw_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>,
2300 def : Pat<(atomic_store_64 (add (HexagonCONST32_GP tglobaladdr:$global),
2301 u16ImmPred:$offset),
2302 (i64 DoubleRegs:$src1)),
2303 (STrid_GP_V4 tglobaladdr:$global, u16ImmPred:$offset,
2304 (i64 DoubleRegs:$src1))>,
2307 def : Pat<(atomic_store_32 (add (HexagonCONST32_GP tglobaladdr:$global),
2308 u16ImmPred:$offset),
2309 (i32 IntRegs:$src1)),
2310 (STriw_GP_V4 tglobaladdr:$global, u16ImmPred:$offset,
2311 (i32 IntRegs:$src1))>,
2314 def : Pat<(atomic_store_16 (add (HexagonCONST32_GP tglobaladdr:$global),
2315 u16ImmPred:$offset),
2316 (i32 IntRegs:$src1)),
2317 (STrih_GP_V4 tglobaladdr:$global, u16ImmPred:$offset,
2318 (i32 IntRegs:$src1))>,
2321 def : Pat<(atomic_store_8 (add (HexagonCONST32_GP tglobaladdr:$global),
2322 u16ImmPred:$offset),
2323 (i32 IntRegs:$src1)),
2324 (STrib_GP_V4 tglobaladdr:$global, u16ImmPred:$offset,
2325 (i32 IntRegs:$src1))>,
2328 // Map from store(globaladdress + x) -> memd(#foo + x)
2329 let AddedComplexity = 100 in
2330 def : Pat<(store (i64 DoubleRegs:$src1),
2331 (add (HexagonCONST32_GP tglobaladdr:$global),
2332 u16ImmPred:$offset)),
2333 (STrid_GP_V4 tglobaladdr:$global, u16ImmPred:$offset,
2334 (i64 DoubleRegs:$src1))>,
2337 // Map from store(globaladdress + x) -> memb(#foo + x)
2338 let AddedComplexity = 100 in
2339 def : Pat<(truncstorei8 (i32 IntRegs:$src1),
2340 (add (HexagonCONST32_GP tglobaladdr:$global),
2341 u16ImmPred:$offset)),
2342 (STrib_GP_V4 tglobaladdr:$global, u16ImmPred:$offset,
2343 (i32 IntRegs:$src1))>,
2346 // Map from store(globaladdress + x) -> memh(#foo + x)
2347 let AddedComplexity = 100 in
2348 def : Pat<(truncstorei16 (i32 IntRegs:$src1),
2349 (add (HexagonCONST32_GP tglobaladdr:$global),
2350 u16ImmPred:$offset)),
2351 (STrih_GP_V4 tglobaladdr:$global, u16ImmPred:$offset,
2352 (i32 IntRegs:$src1))>,
2355 // Map from store(globaladdress + x) -> memw(#foo + x)
2356 let AddedComplexity = 100 in
2357 def : Pat<(store (i32 IntRegs:$src1),
2358 (add (HexagonCONST32_GP tglobaladdr:$global),
2359 u16ImmPred:$offset)),
2360 (STriw_GP_V4 tglobaladdr:$global, u16ImmPred:$offset,
2361 (i32 IntRegs:$src1))>,
2366 //===----------------------------------------------------------------------===
2368 //===----------------------------------------------------------------------===
2371 //===----------------------------------------------------------------------===//
2373 //===----------------------------------------------------------------------===//
2375 // multiclass for new-value store instructions with base + immediate offset.
2377 multiclass ST_Idxd_Pbase_nv<string mnemonic, RegisterClass RC,
2378 Operand predImmOp, bit isNot, bit isPredNew> {
2379 let PNewValue = #!if(isPredNew, "new", "") in
2380 def #NAME#_nv_V4 : NVInst_V4<(outs),
2381 (ins PredRegs:$src1, IntRegs:$src2, predImmOp:$src3, RC: $src4),
2382 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
2383 ") ")#mnemonic#"($src2+#$src3) = $src4.new",
2388 multiclass ST_Idxd_Pred_nv<string mnemonic, RegisterClass RC, Operand predImmOp,
2390 let PredSense = #!if(PredNot, "false", "true") in {
2391 defm _c#NAME# : ST_Idxd_Pbase_nv<mnemonic, RC, predImmOp, PredNot, 0>;
2393 defm _cdn#NAME# : ST_Idxd_Pbase_nv<mnemonic, RC, predImmOp, PredNot, 1>;
2397 let mayStore = 1, isNVStore = 1, neverHasSideEffects = 1, isExtendable = 1 in
2398 multiclass ST_Idxd_nv<string mnemonic, string CextOp, RegisterClass RC,
2399 Operand ImmOp, Operand predImmOp, bits<5> ImmBits,
2400 bits<5> PredImmBits> {
2402 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed in {
2403 let opExtendable = 1, isExtentSigned = 1, opExtentBits = ImmBits,
2405 def #NAME#_nv_V4 : NVInst_V4<(outs),
2406 (ins IntRegs:$src1, ImmOp:$src2, RC:$src3),
2407 #mnemonic#"($src1+#$src2) = $src3.new",
2411 let opExtendable = 2, isExtentSigned = 0, opExtentBits = PredImmBits,
2412 isPredicated = 1 in {
2413 defm Pt : ST_Idxd_Pred_nv<mnemonic, RC, predImmOp, 0>;
2414 defm NotPt : ST_Idxd_Pred_nv<mnemonic, RC, predImmOp, 1>;
2419 let addrMode = BaseImmOffset, validSubTargets = HasV4SubT in {
2420 defm STrib_indexed: ST_Idxd_nv<"memb", "STrib", IntRegs, s11_0Ext,
2421 u6_0Ext, 11, 6>, AddrModeRel;
2422 defm STrih_indexed: ST_Idxd_nv<"memh", "STrih", IntRegs, s11_1Ext,
2423 u6_1Ext, 12, 7>, AddrModeRel;
2424 defm STriw_indexed: ST_Idxd_nv<"memw", "STriw", IntRegs, s11_2Ext,
2425 u6_2Ext, 13, 8>, AddrModeRel;
2428 // Store new-value byte.
2430 // memb(Re=#U6)=Nt.new
2431 // memb(Rs+#s11:0)=Nt.new
2432 let mayStore = 1, isPredicable = 1 in
2433 def STrib_nv_V4 : NVInst_V4<(outs), (ins MEMri:$addr, IntRegs:$src1),
2434 "memb($addr) = $src1.new",
2438 // memb(Ru<<#u2+#U6)=Nt.new
2439 let mayStore = 1, AddedComplexity = 10 in
2440 def STrib_shl_nv_V4 : NVInst_V4<(outs),
2441 (ins IntRegs:$src1, u2Imm:$src2, u6Imm:$src3, IntRegs:$src4),
2442 "memb($src1<<#$src2+#$src3) = $src4.new",
2446 // memb(Rx++#s4:0)=Nt.new
2447 let mayStore = 1, hasCtrlDep = 1, isPredicable = 1 in
2448 def POST_STbri_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
2449 (ins IntRegs:$src1, IntRegs:$src2, s4_0Imm:$offset),
2450 "memb($src2++#$offset) = $src1.new",
2455 // memb(Rx++#s4:0:circ(Mu))=Nt.new
2456 // memb(Rx++I:circ(Mu))=Nt.new
2457 // memb(Rx++Mu)=Nt.new
2458 // memb(Rx++Mu:brev)=Nt.new
2460 // memb(gp+#u16:0)=Nt.new
2461 let mayStore = 1, neverHasSideEffects = 1 in
2462 def STrib_GP_nv_V4 : NVInst_V4<(outs),
2463 (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),
2464 "memb(#$global+$offset) = $src.new",
2468 // memb(#global)=Nt.new
2469 let mayStore = 1, neverHasSideEffects = 1 in
2470 def STb_GP_nv_V4 : NVInst_V4<(outs),
2471 (ins globaladdress:$global, IntRegs:$src),
2472 "memb(#$global) = $src.new",
2476 // Store new-value byte conditionally.
2477 // if ([!]Pv[.new]) memb(#u6)=Nt.new
2478 // if (Pv) memb(Rs+#u6:0)=Nt.new
2479 let mayStore = 1, neverHasSideEffects = 1,
2481 def STrib_cPt_nv_V4 : NVInst_V4<(outs),
2482 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
2483 "if ($src1) memb($addr) = $src2.new",
2487 // if (Pv.new) memb(Rs+#u6:0)=Nt.new
2488 let mayStore = 1, neverHasSideEffects = 1,
2490 def STrib_cdnPt_nv_V4 : NVInst_V4<(outs),
2491 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
2492 "if ($src1.new) memb($addr) = $src2.new",
2496 // if (!Pv) memb(Rs+#u6:0)=Nt.new
2497 let mayStore = 1, neverHasSideEffects = 1,
2499 def STrib_cNotPt_nv_V4 : NVInst_V4<(outs),
2500 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
2501 "if (!$src1) memb($addr) = $src2.new",
2505 // if (!Pv.new) memb(Rs+#u6:0)=Nt.new
2506 let mayStore = 1, neverHasSideEffects = 1,
2508 def STrib_cdnNotPt_nv_V4 : NVInst_V4<(outs),
2509 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
2510 "if (!$src1.new) memb($addr) = $src2.new",
2514 // if ([!]Pv[.new]) memb(Rx++#s4:0)=Nt.new
2515 // if (Pv) memb(Rx++#s4:0)=Nt.new
2516 let mayStore = 1, hasCtrlDep = 1,
2518 def POST_STbri_cPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
2519 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_0Imm:$offset),
2520 "if ($src1) memb($src3++#$offset) = $src2.new",
2524 // if (Pv.new) memb(Rx++#s4:0)=Nt.new
2525 let mayStore = 1, hasCtrlDep = 1,
2527 def POST_STbri_cdnPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
2528 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_0Imm:$offset),
2529 "if ($src1.new) memb($src3++#$offset) = $src2.new",
2533 // if (!Pv) memb(Rx++#s4:0)=Nt.new
2534 let mayStore = 1, hasCtrlDep = 1,
2536 def POST_STbri_cNotPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
2537 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_0Imm:$offset),
2538 "if (!$src1) memb($src3++#$offset) = $src2.new",
2542 // if (!Pv.new) memb(Rx++#s4:0)=Nt.new
2543 let mayStore = 1, hasCtrlDep = 1,
2545 def POST_STbri_cdnNotPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
2546 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_0Imm:$offset),
2547 "if (!$src1.new) memb($src3++#$offset) = $src2.new",
2552 // Store new-value halfword.
2553 // memh(Re=#U6)=Nt.new
2554 // memh(Rs+#s11:1)=Nt.new
2555 let mayStore = 1, isPredicable = 1 in
2556 def STrih_nv_V4 : NVInst_V4<(outs), (ins MEMri:$addr, IntRegs:$src1),
2557 "memh($addr) = $src1.new",
2561 // memh(Ru<<#u2+#U6)=Nt.new
2562 let mayStore = 1, AddedComplexity = 10 in
2563 def STrih_shl_nv_V4 : NVInst_V4<(outs),
2564 (ins IntRegs:$src1, u2Imm:$src2, u6Imm:$src3, IntRegs:$src4),
2565 "memh($src1<<#$src2+#$src3) = $src4.new",
2569 // memh(Rx++#s4:1)=Nt.new
2570 let mayStore = 1, hasCtrlDep = 1, isPredicable = 1 in
2571 def POST_SThri_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
2572 (ins IntRegs:$src1, IntRegs:$src2, s4_1Imm:$offset),
2573 "memh($src2++#$offset) = $src1.new",
2578 // memh(Rx++#s4:1:circ(Mu))=Nt.new
2579 // memh(Rx++I:circ(Mu))=Nt.new
2580 // memh(Rx++Mu)=Nt.new
2581 // memh(Rx++Mu:brev)=Nt.new
2583 // memh(gp+#u16:1)=Nt.new
2584 let mayStore = 1, neverHasSideEffects = 1 in
2585 def STrih_GP_nv_V4 : NVInst_V4<(outs),
2586 (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),
2587 "memh(#$global+$offset) = $src.new",
2591 // memh(#global)=Nt.new
2592 let mayStore = 1, neverHasSideEffects = 1 in
2593 def STh_GP_nv_V4 : NVInst_V4<(outs),
2594 (ins globaladdress:$global, IntRegs:$src),
2595 "memh(#$global) = $src.new",
2600 // Store new-value halfword conditionally.
2602 // if ([!]Pv[.new]) memh(#u6)=Nt.new
2604 // if ([!]Pv[.new]) memh(Rs+#u6:1)=Nt.new
2605 // if (Pv) memh(Rs+#u6:1)=Nt.new
2606 let mayStore = 1, neverHasSideEffects = 1,
2608 def STrih_cPt_nv_V4 : NVInst_V4<(outs),
2609 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
2610 "if ($src1) memh($addr) = $src2.new",
2614 // if (Pv.new) memh(Rs+#u6:1)=Nt.new
2615 let mayStore = 1, neverHasSideEffects = 1,
2617 def STrih_cdnPt_nv_V4 : NVInst_V4<(outs),
2618 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
2619 "if ($src1.new) memh($addr) = $src2.new",
2623 // if (!Pv) memh(Rs+#u6:1)=Nt.new
2624 let mayStore = 1, neverHasSideEffects = 1,
2626 def STrih_cNotPt_nv_V4 : NVInst_V4<(outs),
2627 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
2628 "if (!$src1) memh($addr) = $src2.new",
2632 // if (!Pv.new) memh(Rs+#u6:1)=Nt.new
2633 let mayStore = 1, neverHasSideEffects = 1,
2635 def STrih_cdnNotPt_nv_V4 : NVInst_V4<(outs),
2636 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
2637 "if (!$src1.new) memh($addr) = $src2.new",
2641 // if ([!]Pv[]) memh(Rx++#s4:1)=Nt.new
2642 // if (Pv) memh(Rx++#s4:1)=Nt.new
2643 let mayStore = 1, hasCtrlDep = 1,
2645 def POST_SThri_cPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
2646 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_1Imm:$offset),
2647 "if ($src1) memh($src3++#$offset) = $src2.new",
2651 // if (Pv.new) memh(Rx++#s4:1)=Nt.new
2652 let mayStore = 1, hasCtrlDep = 1,
2654 def POST_SThri_cdnPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
2655 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_1Imm:$offset),
2656 "if ($src1.new) memh($src3++#$offset) = $src2.new",
2660 // if (!Pv) memh(Rx++#s4:1)=Nt.new
2661 let mayStore = 1, hasCtrlDep = 1,
2663 def POST_SThri_cNotPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
2664 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_1Imm:$offset),
2665 "if (!$src1) memh($src3++#$offset) = $src2.new",
2669 // if (!Pv.new) memh(Rx++#s4:1)=Nt.new
2670 let mayStore = 1, hasCtrlDep = 1,
2672 def POST_SThri_cdnNotPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
2673 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_1Imm:$offset),
2674 "if (!$src1.new) memh($src3++#$offset) = $src2.new",
2679 // Store new-value word.
2681 // memw(Re=#U6)=Nt.new
2682 // memw(Rs+#s11:2)=Nt.new
2683 let mayStore = 1, isPredicable = 1 in
2684 def STriw_nv_V4 : NVInst_V4<(outs),
2685 (ins MEMri:$addr, IntRegs:$src1),
2686 "memw($addr) = $src1.new",
2690 // memw(Ru<<#u2+#U6)=Nt.new
2691 let mayStore = 1, AddedComplexity = 10 in
2692 def STriw_shl_nv_V4 : NVInst_V4<(outs),
2693 (ins IntRegs:$src1, u2Imm:$src2, u6Imm:$src3, IntRegs:$src4),
2694 "memw($src1<<#$src2+#$src3) = $src4.new",
2698 // memw(Rx++#s4:2)=Nt.new
2699 let mayStore = 1, hasCtrlDep = 1, isPredicable = 1 in
2700 def POST_STwri_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
2701 (ins IntRegs:$src1, IntRegs:$src2, s4_2Imm:$offset),
2702 "memw($src2++#$offset) = $src1.new",
2707 // memw(Rx++#s4:2:circ(Mu))=Nt.new
2708 // memw(Rx++I:circ(Mu))=Nt.new
2709 // memw(Rx++Mu)=Nt.new
2710 // memw(Rx++Mu:brev)=Nt.new
2711 // memw(gp+#u16:2)=Nt.new
2712 let mayStore = 1, neverHasSideEffects = 1 in
2713 def STriw_GP_nv_V4 : NVInst_V4<(outs),
2714 (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),
2715 "memw(#$global+$offset) = $src.new",
2719 let mayStore = 1, neverHasSideEffects = 1 in
2720 def STw_GP_nv_V4 : NVInst_V4<(outs),
2721 (ins globaladdress:$global, IntRegs:$src),
2722 "memw(#$global) = $src.new",
2726 // Store new-value word conditionally.
2728 // if ([!]Pv[.new]) memw(#u6)=Nt.new
2730 // if ([!]Pv[.new]) memw(Rs+#u6:2)=Nt.new
2731 // if (Pv) memw(Rs+#u6:2)=Nt.new
2732 let mayStore = 1, neverHasSideEffects = 1,
2734 def STriw_cPt_nv_V4 : NVInst_V4<(outs),
2735 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
2736 "if ($src1) memw($addr) = $src2.new",
2740 // if (Pv.new) memw(Rs+#u6:2)=Nt.new
2741 let mayStore = 1, neverHasSideEffects = 1,
2743 def STriw_cdnPt_nv_V4 : NVInst_V4<(outs),
2744 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
2745 "if ($src1.new) memw($addr) = $src2.new",
2749 // if (!Pv) memw(Rs+#u6:2)=Nt.new
2750 let mayStore = 1, neverHasSideEffects = 1,
2752 def STriw_cNotPt_nv_V4 : NVInst_V4<(outs),
2753 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
2754 "if (!$src1) memw($addr) = $src2.new",
2758 // if (!Pv.new) memw(Rs+#u6:2)=Nt.new
2759 let mayStore = 1, neverHasSideEffects = 1,
2761 def STriw_cdnNotPt_nv_V4 : NVInst_V4<(outs),
2762 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),
2763 "if (!$src1.new) memw($addr) = $src2.new",
2767 // if ([!]Pv[.new]) memw(Rx++#s4:2)=Nt.new
2768 // if (Pv) memw(Rx++#s4:2)=Nt.new
2769 let mayStore = 1, hasCtrlDep = 1,
2771 def POST_STwri_cPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
2772 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset),
2773 "if ($src1) memw($src3++#$offset) = $src2.new",
2777 // if (Pv.new) memw(Rx++#s4:2)=Nt.new
2778 let mayStore = 1, hasCtrlDep = 1,
2780 def POST_STwri_cdnPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
2781 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset),
2782 "if ($src1.new) memw($src3++#$offset) = $src2.new",
2786 // if (!Pv) memw(Rx++#s4:2)=Nt.new
2787 let mayStore = 1, hasCtrlDep = 1,
2789 def POST_STwri_cNotPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
2790 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset),
2791 "if (!$src1) memw($src3++#$offset) = $src2.new",
2795 // if (!Pv.new) memw(Rx++#s4:2)=Nt.new
2796 let mayStore = 1, hasCtrlDep = 1,
2798 def POST_STwri_cdnNotPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
2799 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset),
2800 "if (!$src1.new) memw($src3++#$offset) = $src2.new",
2806 // if (Pv) memb(##global) = Rt
2807 let mayStore = 1, neverHasSideEffects = 1 in
2808 def STb_GP_cPt_nv_V4 : NVInst_V4<(outs),
2809 (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2810 "if ($src1) memb(##$global) = $src2.new",
2814 // if (!Pv) memb(##global) = Rt
2815 let mayStore = 1, neverHasSideEffects = 1 in
2816 def STb_GP_cNotPt_nv_V4 : NVInst_V4<(outs),
2817 (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2818 "if (!$src1) memb(##$global) = $src2.new",
2822 // if (Pv) memb(##global) = Rt
2823 let mayStore = 1, neverHasSideEffects = 1 in
2824 def STb_GP_cdnPt_nv_V4 : NVInst_V4<(outs),
2825 (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2826 "if ($src1.new) memb(##$global) = $src2.new",
2830 // if (!Pv) memb(##global) = Rt
2831 let mayStore = 1, neverHasSideEffects = 1 in
2832 def STb_GP_cdnNotPt_nv_V4 : NVInst_V4<(outs),
2833 (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2834 "if (!$src1.new) memb(##$global) = $src2.new",
2838 // if (Pv) memh(##global) = Rt
2839 let mayStore = 1, neverHasSideEffects = 1 in
2840 def STh_GP_cPt_nv_V4 : NVInst_V4<(outs),
2841 (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2842 "if ($src1) memh(##$global) = $src2.new",
2846 // if (!Pv) memh(##global) = Rt
2847 let mayStore = 1, neverHasSideEffects = 1 in
2848 def STh_GP_cNotPt_nv_V4 : NVInst_V4<(outs),
2849 (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2850 "if (!$src1) memh(##$global) = $src2.new",
2854 // if (Pv) memh(##global) = Rt
2855 let mayStore = 1, neverHasSideEffects = 1 in
2856 def STh_GP_cdnPt_nv_V4 : NVInst_V4<(outs),
2857 (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2858 "if ($src1.new) memh(##$global) = $src2.new",
2862 // if (!Pv) memh(##global) = Rt
2863 let mayStore = 1, neverHasSideEffects = 1 in
2864 def STh_GP_cdnNotPt_nv_V4 : NVInst_V4<(outs),
2865 (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2866 "if (!$src1.new) memh(##$global) = $src2.new",
2870 // if (Pv) memw(##global) = Rt
2871 let mayStore = 1, neverHasSideEffects = 1 in
2872 def STw_GP_cPt_nv_V4 : NVInst_V4<(outs),
2873 (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2874 "if ($src1) memw(##$global) = $src2.new",
2878 // if (!Pv) memw(##global) = Rt
2879 let mayStore = 1, neverHasSideEffects = 1 in
2880 def STw_GP_cNotPt_nv_V4 : NVInst_V4<(outs),
2881 (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2882 "if (!$src1) memw(##$global) = $src2.new",
2886 // if (Pv) memw(##global) = Rt
2887 let mayStore = 1, neverHasSideEffects = 1 in
2888 def STw_GP_cdnPt_nv_V4 : NVInst_V4<(outs),
2889 (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2890 "if ($src1.new) memw(##$global) = $src2.new",
2894 // if (!Pv) memw(##global) = Rt
2895 let mayStore = 1, neverHasSideEffects = 1 in
2896 def STw_GP_cdnNotPt_nv_V4 : NVInst_V4<(outs),
2897 (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),
2898 "if (!$src1.new) memw(##$global) = $src2.new",
2902 let mayStore = 1, neverHasSideEffects = 1 in
2903 def STrib_GP_cPt_nv_V4 : NVInst_V4<(outs),
2904 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2906 "if ($src1) memb(##$global+$offset) = $src2.new",
2910 let mayStore = 1, neverHasSideEffects = 1 in
2911 def STrib_GP_cNotPt_nv_V4 : NVInst_V4<(outs),
2912 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2914 "if (!$src1) memb(##$global+$offset) = $src2.new",
2918 let mayStore = 1, neverHasSideEffects = 1 in
2919 def STrib_GP_cdnPt_nv_V4 : NVInst_V4<(outs),
2920 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2922 "if ($src1.new) memb(##$global+$offset) = $src2.new",
2926 let mayStore = 1, neverHasSideEffects = 1 in
2927 def STrib_GP_cdnNotPt_nv_V4 : NVInst_V4<(outs),
2928 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2930 "if (!$src1.new) memb(##$global+$offset) = $src2.new",
2934 let mayStore = 1, neverHasSideEffects = 1 in
2935 def STrih_GP_cPt_nv_V4 : NVInst_V4<(outs),
2936 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2938 "if ($src1) memh(##$global+$offset) = $src2.new",
2942 let mayStore = 1, neverHasSideEffects = 1 in
2943 def STrih_GP_cNotPt_nv_V4 : NVInst_V4<(outs),
2944 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2946 "if (!$src1) memh(##$global+$offset) = $src2.new",
2950 let mayStore = 1, neverHasSideEffects = 1 in
2951 def STrih_GP_cdnPt_nv_V4 : NVInst_V4<(outs),
2952 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2954 "if ($src1.new) memh(##$global+$offset) = $src2.new",
2958 let mayStore = 1, neverHasSideEffects = 1 in
2959 def STrih_GP_cdnNotPt_nv_V4 : NVInst_V4<(outs),
2960 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2962 "if (!$src1.new) memh(##$global+$offset) = $src2.new",
2966 let mayStore = 1, neverHasSideEffects = 1 in
2967 def STriw_GP_cPt_nv_V4 : NVInst_V4<(outs),
2968 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2970 "if ($src1) memw(##$global+$offset) = $src2.new",
2974 let mayStore = 1, neverHasSideEffects = 1 in
2975 def STriw_GP_cNotPt_nv_V4 : NVInst_V4<(outs),
2976 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2978 "if (!$src1) memw(##$global+$offset) = $src2.new",
2982 let mayStore = 1, neverHasSideEffects = 1 in
2983 def STriw_GP_cdnPt_nv_V4 : NVInst_V4<(outs),
2984 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2986 "if ($src1.new) memw(##$global+$offset) = $src2.new",
2990 let mayStore = 1, neverHasSideEffects = 1 in
2991 def STriw_GP_cdnNotPt_nv_V4 : NVInst_V4<(outs),
2992 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,
2994 "if (!$src1.new) memw(##$global+$offset) = $src2.new",
2998 //===----------------------------------------------------------------------===//
3000 //===----------------------------------------------------------------------===//
3002 //===----------------------------------------------------------------------===//
3004 //===----------------------------------------------------------------------===//
3006 multiclass NVJ_type_basic_reg<string NotStr, string OpcStr, string TakenStr> {
3007 def _ie_nv_V4 : NVInst_V4<(outs),
3008 (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset),
3009 !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
3010 !strconcat("($src1.new, $src2)) jump:",
3011 !strconcat(TakenStr, " $offset"))))),
3015 def _nv_V4 : NVInst_V4<(outs),
3016 (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset),
3017 !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
3018 !strconcat("($src1.new, $src2)) jump:",
3019 !strconcat(TakenStr, " $offset"))))),
3024 multiclass NVJ_type_basic_2ndDotNew<string NotStr, string OpcStr,
3026 def _ie_nv_V4 : NVInst_V4<(outs),
3027 (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset),
3028 !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
3029 !strconcat("($src1, $src2.new)) jump:",
3030 !strconcat(TakenStr, " $offset"))))),
3034 def _nv_V4 : NVInst_V4<(outs),
3035 (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset),
3036 !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
3037 !strconcat("($src1, $src2.new)) jump:",
3038 !strconcat(TakenStr, " $offset"))))),
3043 multiclass NVJ_type_basic_imm<string NotStr, string OpcStr, string TakenStr> {
3044 def _ie_nv_V4 : NVInst_V4<(outs),
3045 (ins IntRegs:$src1, u5Imm:$src2, brtarget:$offset),
3046 !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
3047 !strconcat("($src1.new, #$src2)) jump:",
3048 !strconcat(TakenStr, " $offset"))))),
3052 def _nv_V4 : NVInst_V4<(outs),
3053 (ins IntRegs:$src1, u5Imm:$src2, brtarget:$offset),
3054 !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
3055 !strconcat("($src1.new, #$src2)) jump:",
3056 !strconcat(TakenStr, " $offset"))))),
3061 multiclass NVJ_type_basic_neg<string NotStr, string OpcStr, string TakenStr> {
3062 def _ie_nv_V4 : NVInst_V4<(outs),
3063 (ins IntRegs:$src1, nOneImm:$src2, brtarget:$offset),
3064 !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
3065 !strconcat("($src1.new, #$src2)) jump:",
3066 !strconcat(TakenStr, " $offset"))))),
3070 def _nv_V4 : NVInst_V4<(outs),
3071 (ins IntRegs:$src1, nOneImm:$src2, brtarget:$offset),
3072 !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
3073 !strconcat("($src1.new, #$src2)) jump:",
3074 !strconcat(TakenStr, " $offset"))))),
3079 multiclass NVJ_type_basic_tstbit<string NotStr, string OpcStr,
3081 def _ie_nv_V4 : NVInst_V4<(outs),
3082 (ins IntRegs:$src1, u1Imm:$src2, brtarget:$offset),
3083 !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
3084 !strconcat("($src1.new, #$src2)) jump:",
3085 !strconcat(TakenStr, " $offset"))))),
3089 def _nv_V4 : NVInst_V4<(outs),
3090 (ins IntRegs:$src1, u1Imm:$src2, brtarget:$offset),
3091 !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr,
3092 !strconcat("($src1.new, #$src2)) jump:",
3093 !strconcat(TakenStr, " $offset"))))),
3098 // Multiclass for regular dot new of Ist operand register.
3099 multiclass NVJ_type_br_pred_reg<string NotStr, string OpcStr> {
3100 defm Pt : NVJ_type_basic_reg<NotStr, OpcStr, "t">;
3101 defm Pnt : NVJ_type_basic_reg<NotStr, OpcStr, "nt">;
3104 // Multiclass for dot new of 2nd operand register.
3105 multiclass NVJ_type_br_pred_2ndDotNew<string NotStr, string OpcStr> {
3106 defm Pt : NVJ_type_basic_2ndDotNew<NotStr, OpcStr, "t">;
3107 defm Pnt : NVJ_type_basic_2ndDotNew<NotStr, OpcStr, "nt">;
3110 // Multiclass for 2nd operand immediate, including -1.
3111 multiclass NVJ_type_br_pred_imm<string NotStr, string OpcStr> {
3112 defm Pt : NVJ_type_basic_imm<NotStr, OpcStr, "t">;
3113 defm Pnt : NVJ_type_basic_imm<NotStr, OpcStr, "nt">;
3114 defm Ptneg : NVJ_type_basic_neg<NotStr, OpcStr, "t">;
3115 defm Pntneg : NVJ_type_basic_neg<NotStr, OpcStr, "nt">;
3118 // Multiclass for 2nd operand immediate, excluding -1.
3119 multiclass NVJ_type_br_pred_imm_only<string NotStr, string OpcStr> {
3120 defm Pt : NVJ_type_basic_imm<NotStr, OpcStr, "t">;
3121 defm Pnt : NVJ_type_basic_imm<NotStr, OpcStr, "nt">;
3124 // Multiclass for tstbit, where 2nd operand is always #0.
3125 multiclass NVJ_type_br_pred_tstbit<string NotStr, string OpcStr> {
3126 defm Pt : NVJ_type_basic_tstbit<NotStr, OpcStr, "t">;
3127 defm Pnt : NVJ_type_basic_tstbit<NotStr, OpcStr, "nt">;
3130 // Multiclass for GT.
3131 multiclass NVJ_type_rr_ri<string OpcStr> {
3132 defm rrNot : NVJ_type_br_pred_reg<"!", OpcStr>;
3133 defm rr : NVJ_type_br_pred_reg<"", OpcStr>;
3134 defm rrdnNot : NVJ_type_br_pred_2ndDotNew<"!", OpcStr>;
3135 defm rrdn : NVJ_type_br_pred_2ndDotNew<"", OpcStr>;
3136 defm riNot : NVJ_type_br_pred_imm<"!", OpcStr>;
3137 defm ri : NVJ_type_br_pred_imm<"", OpcStr>;
3140 // Multiclass for EQ.
3141 multiclass NVJ_type_rr_ri_no_2ndDotNew<string OpcStr> {
3142 defm rrNot : NVJ_type_br_pred_reg<"!", OpcStr>;
3143 defm rr : NVJ_type_br_pred_reg<"", OpcStr>;
3144 defm riNot : NVJ_type_br_pred_imm<"!", OpcStr>;
3145 defm ri : NVJ_type_br_pred_imm<"", OpcStr>;
3148 // Multiclass for GTU.
3149 multiclass NVJ_type_rr_ri_no_nOne<string OpcStr> {
3150 defm rrNot : NVJ_type_br_pred_reg<"!", OpcStr>;
3151 defm rr : NVJ_type_br_pred_reg<"", OpcStr>;
3152 defm rrdnNot : NVJ_type_br_pred_2ndDotNew<"!", OpcStr>;
3153 defm rrdn : NVJ_type_br_pred_2ndDotNew<"", OpcStr>;
3154 defm riNot : NVJ_type_br_pred_imm_only<"!", OpcStr>;
3155 defm ri : NVJ_type_br_pred_imm_only<"", OpcStr>;
3158 // Multiclass for tstbit.
3159 multiclass NVJ_type_r0<string OpcStr> {
3160 defm r0Not : NVJ_type_br_pred_tstbit<"!", OpcStr>;
3161 defm r0 : NVJ_type_br_pred_tstbit<"", OpcStr>;
3164 // Base Multiclass for New Value Jump.
3165 multiclass NVJ_type {
3166 defm GT : NVJ_type_rr_ri<"cmp.gt">;
3167 defm EQ : NVJ_type_rr_ri_no_2ndDotNew<"cmp.eq">;
3168 defm GTU : NVJ_type_rr_ri_no_nOne<"cmp.gtu">;
3169 defm TSTBIT : NVJ_type_r0<"tstbit">;
3172 let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC] in {
3173 defm JMP_ : NVJ_type;
3176 //===----------------------------------------------------------------------===//
3178 //===----------------------------------------------------------------------===//
3180 //===----------------------------------------------------------------------===//
3182 //===----------------------------------------------------------------------===//
3184 // Add and accumulate.
3185 // Rd=add(Rs,add(Ru,#s6))
3186 def ADDr_ADDri_V4 : MInst<(outs IntRegs:$dst),
3187 (ins IntRegs:$src1, IntRegs:$src2, s6Imm:$src3),
3188 "$dst = add($src1, add($src2, #$src3))",
3189 [(set (i32 IntRegs:$dst),
3190 (add (i32 IntRegs:$src1), (add (i32 IntRegs:$src2),
3191 s6ImmPred:$src3)))]>,
3194 // Rd=add(Rs,sub(#s6,Ru))
3195 def ADDr_SUBri_V4 : MInst<(outs IntRegs:$dst),
3196 (ins IntRegs:$src1, s6Imm:$src2, IntRegs:$src3),
3197 "$dst = add($src1, sub(#$src2, $src3))",
3198 [(set (i32 IntRegs:$dst),
3199 (add (i32 IntRegs:$src1), (sub s6ImmPred:$src2,
3200 (i32 IntRegs:$src3))))]>,
3203 // Generates the same instruction as ADDr_SUBri_V4 but matches different
3205 // Rd=add(Rs,sub(#s6,Ru))
3206 def ADDri_SUBr_V4 : MInst<(outs IntRegs:$dst),
3207 (ins IntRegs:$src1, s6Imm:$src2, IntRegs:$src3),
3208 "$dst = add($src1, sub(#$src2, $src3))",
3209 [(set (i32 IntRegs:$dst),
3210 (sub (add (i32 IntRegs:$src1), s6ImmPred:$src2),
3211 (i32 IntRegs:$src3)))]>,
3215 // Add or subtract doublewords with carry.
3217 // Rdd=add(Rss,Rtt,Px):carry
3219 // Rdd=sub(Rss,Rtt,Px):carry
3222 // Logical doublewords.
3223 // Rdd=and(Rtt,~Rss)
3224 def ANDd_NOTd_V4 : MInst<(outs DoubleRegs:$dst),
3225 (ins DoubleRegs:$src1, DoubleRegs:$src2),
3226 "$dst = and($src1, ~$src2)",
3227 [(set (i64 DoubleRegs:$dst), (and (i64 DoubleRegs:$src1),
3228 (not (i64 DoubleRegs:$src2))))]>,
3232 def ORd_NOTd_V4 : MInst<(outs DoubleRegs:$dst),
3233 (ins DoubleRegs:$src1, DoubleRegs:$src2),
3234 "$dst = or($src1, ~$src2)",
3235 [(set (i64 DoubleRegs:$dst),
3236 (or (i64 DoubleRegs:$src1), (not (i64 DoubleRegs:$src2))))]>,
3240 // Logical-logical doublewords.
3241 // Rxx^=xor(Rss,Rtt)
3242 def XORd_XORdd: MInst_acc<(outs DoubleRegs:$dst),
3243 (ins DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),
3244 "$dst ^= xor($src2, $src3)",
3245 [(set (i64 DoubleRegs:$dst),
3246 (xor (i64 DoubleRegs:$src1), (xor (i64 DoubleRegs:$src2),
3247 (i64 DoubleRegs:$src3))))],
3252 // Logical-logical words.
3253 // Rx=or(Ru,and(Rx,#s10))
3254 def ORr_ANDri_V4 : MInst_acc<(outs IntRegs:$dst),
3255 (ins IntRegs:$src1, IntRegs: $src2, s10Imm:$src3),
3256 "$dst = or($src1, and($src2, #$src3))",
3257 [(set (i32 IntRegs:$dst),
3258 (or (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
3259 s10ImmPred:$src3)))],
3263 // Rx[&|^]=and(Rs,Rt)
3265 def ANDr_ANDrr_V4 : MInst_acc<(outs IntRegs:$dst),
3266 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
3267 "$dst &= and($src2, $src3)",
3268 [(set (i32 IntRegs:$dst),
3269 (and (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
3270 (i32 IntRegs:$src3))))],
3275 def ORr_ANDrr_V4 : MInst_acc<(outs IntRegs:$dst),
3276 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
3277 "$dst |= and($src2, $src3)",
3278 [(set (i32 IntRegs:$dst),
3279 (or (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
3280 (i32 IntRegs:$src3))))],
3285 def XORr_ANDrr_V4 : MInst_acc<(outs IntRegs:$dst),
3286 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
3287 "$dst ^= and($src2, $src3)",
3288 [(set (i32 IntRegs:$dst),
3289 (xor (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
3290 (i32 IntRegs:$src3))))],
3294 // Rx[&|^]=and(Rs,~Rt)
3296 def ANDr_ANDr_NOTr_V4 : MInst_acc<(outs IntRegs:$dst),
3297 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
3298 "$dst &= and($src2, ~$src3)",
3299 [(set (i32 IntRegs:$dst),
3300 (and (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
3301 (not (i32 IntRegs:$src3)))))],
3306 def ORr_ANDr_NOTr_V4 : MInst_acc<(outs IntRegs:$dst),
3307 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
3308 "$dst |= and($src2, ~$src3)",
3309 [(set (i32 IntRegs:$dst),
3310 (or (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
3311 (not (i32 IntRegs:$src3)))))],
3316 def XORr_ANDr_NOTr_V4 : MInst_acc<(outs IntRegs:$dst),
3317 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
3318 "$dst ^= and($src2, ~$src3)",
3319 [(set (i32 IntRegs:$dst),
3320 (xor (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
3321 (not (i32 IntRegs:$src3)))))],
3325 // Rx[&|^]=or(Rs,Rt)
3327 def ANDr_ORrr_V4 : MInst_acc<(outs IntRegs:$dst),
3328 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
3329 "$dst &= or($src2, $src3)",
3330 [(set (i32 IntRegs:$dst),
3331 (and (i32 IntRegs:$src1), (or (i32 IntRegs:$src2),
3332 (i32 IntRegs:$src3))))],
3337 def ORr_ORrr_V4 : MInst_acc<(outs IntRegs:$dst),
3338 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
3339 "$dst |= or($src2, $src3)",
3340 [(set (i32 IntRegs:$dst),
3341 (or (i32 IntRegs:$src1), (or (i32 IntRegs:$src2),
3342 (i32 IntRegs:$src3))))],
3347 def XORr_ORrr_V4 : MInst_acc<(outs IntRegs:$dst),
3348 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
3349 "$dst ^= or($src2, $src3)",
3350 [(set (i32 IntRegs:$dst),
3351 (xor (i32 IntRegs:$src1), (or (i32 IntRegs:$src2),
3352 (i32 IntRegs:$src3))))],
3356 // Rx[&|^]=xor(Rs,Rt)
3358 def ANDr_XORrr_V4 : MInst_acc<(outs IntRegs:$dst),
3359 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
3360 "$dst &= xor($src2, $src3)",
3361 [(set (i32 IntRegs:$dst),
3362 (and (i32 IntRegs:$src1), (xor (i32 IntRegs:$src2),
3363 (i32 IntRegs:$src3))))],
3368 def ORr_XORrr_V4 : MInst_acc<(outs IntRegs:$dst),
3369 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
3370 "$dst |= xor($src2, $src3)",
3371 [(set (i32 IntRegs:$dst),
3372 (and (i32 IntRegs:$src1), (xor (i32 IntRegs:$src2),
3373 (i32 IntRegs:$src3))))],
3378 def XORr_XORrr_V4 : MInst_acc<(outs IntRegs:$dst),
3379 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
3380 "$dst ^= xor($src2, $src3)",
3381 [(set (i32 IntRegs:$dst),
3382 (and (i32 IntRegs:$src1), (xor (i32 IntRegs:$src2),
3383 (i32 IntRegs:$src3))))],
3388 def ORr_ANDri2_V4 : MInst_acc<(outs IntRegs:$dst),
3389 (ins IntRegs:$src1, IntRegs: $src2, s10Imm:$src3),
3390 "$dst |= and($src2, #$src3)",
3391 [(set (i32 IntRegs:$dst),
3392 (or (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
3393 s10ImmPred:$src3)))],
3398 def ORr_ORri_V4 : MInst_acc<(outs IntRegs:$dst),
3399 (ins IntRegs:$src1, IntRegs: $src2, s10Imm:$src3),
3400 "$dst |= or($src2, #$src3)",
3401 [(set (i32 IntRegs:$dst),
3402 (or (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
3403 s10ImmPred:$src3)))],
3409 // Rd=modwrap(Rs,Rt)
3411 // Rd=cround(Rs,#u5)
3413 // Rd=round(Rs,#u5)[:sat]
3414 // Rd=round(Rs,Rt)[:sat]
3415 // Vector reduce add unsigned halfwords
3416 // Rd=vraddh(Rss,Rtt)
3418 // Rdd=vaddb(Rss,Rtt)
3419 // Vector conditional negate
3420 // Rdd=vcnegh(Rss,Rt)
3421 // Rxx+=vrcnegh(Rss,Rt)
3422 // Vector maximum bytes
3423 // Rdd=vmaxb(Rtt,Rss)
3424 // Vector reduce maximum halfwords
3425 // Rxx=vrmaxh(Rss,Ru)
3426 // Rxx=vrmaxuh(Rss,Ru)
3427 // Vector reduce maximum words
3428 // Rxx=vrmaxuw(Rss,Ru)
3429 // Rxx=vrmaxw(Rss,Ru)
3430 // Vector minimum bytes
3431 // Rdd=vminb(Rtt,Rss)
3432 // Vector reduce minimum halfwords
3433 // Rxx=vrminh(Rss,Ru)
3434 // Rxx=vrminuh(Rss,Ru)
3435 // Vector reduce minimum words
3436 // Rxx=vrminuw(Rss,Ru)
3437 // Rxx=vrminw(Rss,Ru)
3438 // Vector subtract bytes
3439 // Rdd=vsubb(Rss,Rtt)
3441 //===----------------------------------------------------------------------===//
3443 //===----------------------------------------------------------------------===//
3446 //===----------------------------------------------------------------------===//
3448 //===----------------------------------------------------------------------===//
3450 // Multiply and user lower result.
3451 // Rd=add(#u6,mpyi(Rs,#U6))
3452 def ADDi_MPYri_V4 : MInst<(outs IntRegs:$dst),
3453 (ins u6Imm:$src1, IntRegs:$src2, u6Imm:$src3),
3454 "$dst = add(#$src1, mpyi($src2, #$src3))",
3455 [(set (i32 IntRegs:$dst),
3456 (add (mul (i32 IntRegs:$src2), u6ImmPred:$src3),
3457 u6ImmPred:$src1))]>,
3460 // Rd=add(#u6,mpyi(Rs,Rt))
3462 def ADDi_MPYrr_V4 : MInst<(outs IntRegs:$dst),
3463 (ins u6Imm:$src1, IntRegs:$src2, IntRegs:$src3),
3464 "$dst = add(#$src1, mpyi($src2, $src3))",
3465 [(set (i32 IntRegs:$dst),
3466 (add (mul (i32 IntRegs:$src2), (i32 IntRegs:$src3)),
3467 u6ImmPred:$src1))]>,
3470 // Rd=add(Ru,mpyi(#u6:2,Rs))
3471 def ADDr_MPYir_V4 : MInst<(outs IntRegs:$dst),
3472 (ins IntRegs:$src1, u6Imm:$src2, IntRegs:$src3),
3473 "$dst = add($src1, mpyi(#$src2, $src3))",
3474 [(set (i32 IntRegs:$dst),
3475 (add (i32 IntRegs:$src1), (mul (i32 IntRegs:$src3),
3476 u6_2ImmPred:$src2)))]>,
3479 // Rd=add(Ru,mpyi(Rs,#u6))
3480 def ADDr_MPYri_V4 : MInst<(outs IntRegs:$dst),
3481 (ins IntRegs:$src1, IntRegs:$src2, u6Imm:$src3),
3482 "$dst = add($src1, mpyi($src2, #$src3))",
3483 [(set (i32 IntRegs:$dst),
3484 (add (i32 IntRegs:$src1), (mul (i32 IntRegs:$src2),
3485 u6ImmPred:$src3)))]>,
3488 // Rx=add(Ru,mpyi(Rx,Rs))
3489 def ADDr_MPYrr_V4 : MInst_acc<(outs IntRegs:$dst),
3490 (ins IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
3491 "$dst = add($src1, mpyi($src2, $src3))",
3492 [(set (i32 IntRegs:$dst),
3493 (add (i32 IntRegs:$src1), (mul (i32 IntRegs:$src2),
3494 (i32 IntRegs:$src3))))],
3499 // Polynomial multiply words
3501 // Rxx^=pmpyw(Rs,Rt)
3503 // Vector reduce multiply word by signed half (32x16)
3504 // Rdd=vrmpyweh(Rss,Rtt)[:<<1]
3505 // Rdd=vrmpywoh(Rss,Rtt)[:<<1]
3506 // Rxx+=vrmpyweh(Rss,Rtt)[:<<1]
3507 // Rxx+=vrmpywoh(Rss,Rtt)[:<<1]
3509 // Multiply and use upper result
3510 // Rd=mpy(Rs,Rt.H):<<1:sat
3511 // Rd=mpy(Rs,Rt.L):<<1:sat
3512 // Rd=mpy(Rs,Rt):<<1
3513 // Rd=mpy(Rs,Rt):<<1:sat
3515 // Rx+=mpy(Rs,Rt):<<1:sat
3516 // Rx-=mpy(Rs,Rt):<<1:sat
3518 // Vector multiply bytes
3519 // Rdd=vmpybsu(Rs,Rt)
3520 // Rdd=vmpybu(Rs,Rt)
3521 // Rxx+=vmpybsu(Rs,Rt)
3522 // Rxx+=vmpybu(Rs,Rt)
3524 // Vector polynomial multiply halfwords
3525 // Rdd=vpmpyh(Rs,Rt)
3526 // Rxx^=vpmpyh(Rs,Rt)
3528 //===----------------------------------------------------------------------===//
3530 //===----------------------------------------------------------------------===//
3533 //===----------------------------------------------------------------------===//
3535 //===----------------------------------------------------------------------===//
3537 // Shift by immediate and accumulate.
3538 // Rx=add(#u8,asl(Rx,#U5))
3539 def ADDi_ASLri_V4 : MInst_acc<(outs IntRegs:$dst),
3540 (ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3),
3541 "$dst = add(#$src1, asl($src2, #$src3))",
3542 [(set (i32 IntRegs:$dst),
3543 (add (shl (i32 IntRegs:$src2), u5ImmPred:$src3),
3548 // Rx=add(#u8,lsr(Rx,#U5))
3549 def ADDi_LSRri_V4 : MInst_acc<(outs IntRegs:$dst),
3550 (ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3),
3551 "$dst = add(#$src1, lsr($src2, #$src3))",
3552 [(set (i32 IntRegs:$dst),
3553 (add (srl (i32 IntRegs:$src2), u5ImmPred:$src3),
3558 // Rx=sub(#u8,asl(Rx,#U5))
3559 def SUBi_ASLri_V4 : MInst_acc<(outs IntRegs:$dst),
3560 (ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3),
3561 "$dst = sub(#$src1, asl($src2, #$src3))",
3562 [(set (i32 IntRegs:$dst),
3563 (sub (shl (i32 IntRegs:$src2), u5ImmPred:$src3),
3568 // Rx=sub(#u8,lsr(Rx,#U5))
3569 def SUBi_LSRri_V4 : MInst_acc<(outs IntRegs:$dst),
3570 (ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3),
3571 "$dst = sub(#$src1, lsr($src2, #$src3))",
3572 [(set (i32 IntRegs:$dst),
3573 (sub (srl (i32 IntRegs:$src2), u5ImmPred:$src3),
3579 //Shift by immediate and logical.
3580 //Rx=and(#u8,asl(Rx,#U5))
3581 def ANDi_ASLri_V4 : MInst_acc<(outs IntRegs:$dst),
3582 (ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3),
3583 "$dst = and(#$src1, asl($src2, #$src3))",
3584 [(set (i32 IntRegs:$dst),
3585 (and (shl (i32 IntRegs:$src2), u5ImmPred:$src3),
3590 //Rx=and(#u8,lsr(Rx,#U5))
3591 def ANDi_LSRri_V4 : MInst_acc<(outs IntRegs:$dst),
3592 (ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3),
3593 "$dst = and(#$src1, lsr($src2, #$src3))",
3594 [(set (i32 IntRegs:$dst),
3595 (and (srl (i32 IntRegs:$src2), u5ImmPred:$src3),
3600 //Rx=or(#u8,asl(Rx,#U5))
3601 let AddedComplexity = 30 in
3602 def ORi_ASLri_V4 : MInst_acc<(outs IntRegs:$dst),
3603 (ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3),
3604 "$dst = or(#$src1, asl($src2, #$src3))",
3605 [(set (i32 IntRegs:$dst),
3606 (or (shl (i32 IntRegs:$src2), u5ImmPred:$src3),
3611 //Rx=or(#u8,lsr(Rx,#U5))
3612 let AddedComplexity = 30 in
3613 def ORi_LSRri_V4 : MInst_acc<(outs IntRegs:$dst),
3614 (ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3),
3615 "$dst = or(#$src1, lsr($src2, #$src3))",
3616 [(set (i32 IntRegs:$dst),
3617 (or (srl (i32 IntRegs:$src2), u5ImmPred:$src3),
3623 //Shift by register.
3625 def LSLi_V4 : MInst<(outs IntRegs:$dst), (ins s6Imm:$src1, IntRegs:$src2),
3626 "$dst = lsl(#$src1, $src2)",
3627 [(set (i32 IntRegs:$dst), (shl s6ImmPred:$src1,
3628 (i32 IntRegs:$src2)))]>,
3632 //Shift by register and logical.
3634 def ASLd_rr_xor_V4 : MInst_acc<(outs DoubleRegs:$dst),
3635 (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
3636 "$dst ^= asl($src2, $src3)",
3637 [(set (i64 DoubleRegs:$dst),
3638 (xor (i64 DoubleRegs:$src1), (shl (i64 DoubleRegs:$src2),
3639 (i32 IntRegs:$src3))))],
3644 def ASRd_rr_xor_V4 : MInst_acc<(outs DoubleRegs:$dst),
3645 (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
3646 "$dst ^= asr($src2, $src3)",
3647 [(set (i64 DoubleRegs:$dst),
3648 (xor (i64 DoubleRegs:$src1), (sra (i64 DoubleRegs:$src2),
3649 (i32 IntRegs:$src3))))],
3654 def LSLd_rr_xor_V4 : MInst_acc<(outs DoubleRegs:$dst),
3655 (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
3656 "$dst ^= lsl($src2, $src3)",
3657 [(set (i64 DoubleRegs:$dst), (xor (i64 DoubleRegs:$src1),
3658 (shl (i64 DoubleRegs:$src2),
3659 (i32 IntRegs:$src3))))],
3664 def LSRd_rr_xor_V4 : MInst_acc<(outs DoubleRegs:$dst),
3665 (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
3666 "$dst ^= lsr($src2, $src3)",
3667 [(set (i64 DoubleRegs:$dst),
3668 (xor (i64 DoubleRegs:$src1), (srl (i64 DoubleRegs:$src2),
3669 (i32 IntRegs:$src3))))],
3674 //===----------------------------------------------------------------------===//
3676 //===----------------------------------------------------------------------===//
3678 //===----------------------------------------------------------------------===//
3679 // MEMOP: Word, Half, Byte
3680 //===----------------------------------------------------------------------===//
3682 //===----------------------------------------------------------------------===//
3686 // MEMw_ADDi_indexed_V4 : memw(Rs+#u6:2)+=#U5
3687 // MEMw_SUBi_indexed_V4 : memw(Rs+#u6:2)-=#U5
3688 // MEMw_ADDr_indexed_V4 : memw(Rs+#u6:2)+=Rt
3689 // MEMw_SUBr_indexed_V4 : memw(Rs+#u6:2)-=Rt
3690 // MEMw_CLRr_indexed_V4 : memw(Rs+#u6:2)&=Rt
3691 // MEMw_SETr_indexed_V4 : memw(Rs+#u6:2)|=Rt
3692 // MEMw_ADDi_V4 : memw(Rs+#u6:2)+=#U5
3693 // MEMw_SUBi_V4 : memw(Rs+#u6:2)-=#U5
3694 // MEMw_ADDr_V4 : memw(Rs+#u6:2)+=Rt
3695 // MEMw_SUBr_V4 : memw(Rs+#u6:2)-=Rt
3696 // MEMw_CLRr_V4 : memw(Rs+#u6:2)&=Rt
3697 // MEMw_SETr_V4 : memw(Rs+#u6:2)|=Rt
3700 // MEMw_CLRi_indexed_V4 : memw(Rs+#u6:2)=clrbit(#U5)
3701 // MEMw_SETi_indexed_V4 : memw(Rs+#u6:2)=setbit(#U5)
3702 // MEMw_CLRi_V4 : memw(Rs+#u6:2)=clrbit(#U5)
3703 // MEMw_SETi_V4 : memw(Rs+#u6:2)=setbit(#U5)
3704 //===----------------------------------------------------------------------===//
3708 // memw(Rs+#u6:2) += #U5
3709 let AddedComplexity = 30 in
3710 def MEMw_ADDi_indexed_MEM_V4 : MEMInst_V4<(outs),
3711 (ins IntRegs:$base, u6_2Imm:$offset, u5Imm:$addend),
3712 "memw($base+#$offset) += #$addend",
3714 Requires<[HasV4T, UseMEMOP]>;
3716 // memw(Rs+#u6:2) -= #U5
3717 let AddedComplexity = 30 in
3718 def MEMw_SUBi_indexed_MEM_V4 : MEMInst_V4<(outs),
3719 (ins IntRegs:$base, u6_2Imm:$offset, u5Imm:$subend),
3720 "memw($base+#$offset) -= #$subend",
3722 Requires<[HasV4T, UseMEMOP]>;
3724 // memw(Rs+#u6:2) += Rt
3725 let AddedComplexity = 30 in
3726 def MEMw_ADDr_indexed_MEM_V4 : MEMInst_V4<(outs),
3727 (ins IntRegs:$base, u6_2Imm:$offset, IntRegs:$addend),
3728 "memw($base+#$offset) += $addend",
3729 [(store (add (load (add (i32 IntRegs:$base), u6_2ImmPred:$offset)),
3730 (i32 IntRegs:$addend)),
3731 (add (i32 IntRegs:$base), u6_2ImmPred:$offset))]>,
3732 Requires<[HasV4T, UseMEMOP]>;
3734 // memw(Rs+#u6:2) -= Rt
3735 let AddedComplexity = 30 in
3736 def MEMw_SUBr_indexed_MEM_V4 : MEMInst_V4<(outs),
3737 (ins IntRegs:$base, u6_2Imm:$offset, IntRegs:$subend),
3738 "memw($base+#$offset) -= $subend",
3739 [(store (sub (load (add (i32 IntRegs:$base), u6_2ImmPred:$offset)),
3740 (i32 IntRegs:$subend)),
3741 (add (i32 IntRegs:$base), u6_2ImmPred:$offset))]>,
3742 Requires<[HasV4T, UseMEMOP]>;
3744 // memw(Rs+#u6:2) &= Rt
3745 let AddedComplexity = 30 in
3746 def MEMw_ANDr_indexed_MEM_V4 : MEMInst_V4<(outs),
3747 (ins IntRegs:$base, u6_2Imm:$offset, IntRegs:$andend),
3748 "memw($base+#$offset) &= $andend",
3749 [(store (and (load (add (i32 IntRegs:$base), u6_2ImmPred:$offset)),
3750 (i32 IntRegs:$andend)),
3751 (add (i32 IntRegs:$base), u6_2ImmPred:$offset))]>,
3752 Requires<[HasV4T, UseMEMOP]>;
3754 // memw(Rs+#u6:2) |= Rt
3755 let AddedComplexity = 30 in
3756 def MEMw_ORr_indexed_MEM_V4 : MEMInst_V4<(outs),
3757 (ins IntRegs:$base, u6_2Imm:$offset, IntRegs:$orend),
3758 "memw($base+#$offset) |= $orend",
3759 [(store (or (load (add (i32 IntRegs:$base), u6_2ImmPred:$offset)),
3760 (i32 IntRegs:$orend)),
3761 (add (i32 IntRegs:$base), u6_2ImmPred:$offset))]>,
3762 Requires<[HasV4T, UseMEMOP]>;
3764 // memw(Rs+#u6:2) += #U5
3765 let AddedComplexity = 30 in
3766 def MEMw_ADDi_MEM_V4 : MEMInst_V4<(outs),
3767 (ins MEMri:$addr, u5Imm:$addend),
3768 "memw($addr) += $addend",
3770 Requires<[HasV4T, UseMEMOP]>;
3772 // memw(Rs+#u6:2) -= #U5
3773 let AddedComplexity = 30 in
3774 def MEMw_SUBi_MEM_V4 : MEMInst_V4<(outs),
3775 (ins MEMri:$addr, u5Imm:$subend),
3776 "memw($addr) -= $subend",
3778 Requires<[HasV4T, UseMEMOP]>;
3780 // memw(Rs+#u6:2) += Rt
3781 let AddedComplexity = 30 in
3782 def MEMw_ADDr_MEM_V4 : MEMInst_V4<(outs),
3783 (ins MEMri:$addr, IntRegs:$addend),
3784 "memw($addr) += $addend",
3785 [(store (add (load ADDRriU6_2:$addr), (i32 IntRegs:$addend)),
3786 ADDRriU6_2:$addr)]>,
3787 Requires<[HasV4T, UseMEMOP]>;
3789 // memw(Rs+#u6:2) -= Rt
3790 let AddedComplexity = 30 in
3791 def MEMw_SUBr_MEM_V4 : MEMInst_V4<(outs),
3792 (ins MEMri:$addr, IntRegs:$subend),
3793 "memw($addr) -= $subend",
3794 [(store (sub (load ADDRriU6_2:$addr), (i32 IntRegs:$subend)),
3795 ADDRriU6_2:$addr)]>,
3796 Requires<[HasV4T, UseMEMOP]>;
3798 // memw(Rs+#u6:2) &= Rt
3799 let AddedComplexity = 30 in
3800 def MEMw_ANDr_MEM_V4 : MEMInst_V4<(outs),
3801 (ins MEMri:$addr, IntRegs:$andend),
3802 "memw($addr) &= $andend",
3803 [(store (and (load ADDRriU6_2:$addr), (i32 IntRegs:$andend)),
3804 ADDRriU6_2:$addr)]>,
3805 Requires<[HasV4T, UseMEMOP]>;
3807 // memw(Rs+#u6:2) |= Rt
3808 let AddedComplexity = 30 in
3809 def MEMw_ORr_MEM_V4 : MEMInst_V4<(outs),
3810 (ins MEMri:$addr, IntRegs:$orend),
3811 "memw($addr) |= $orend",
3812 [(store (or (load ADDRriU6_2:$addr), (i32 IntRegs:$orend)),
3813 ADDRriU6_2:$addr)]>,
3814 Requires<[HasV4T, UseMEMOP]>;
3816 //===----------------------------------------------------------------------===//
3820 // MEMh_ADDi_indexed_V4 : memw(Rs+#u6:2)+=#U5
3821 // MEMh_SUBi_indexed_V4 : memw(Rs+#u6:2)-=#U5
3822 // MEMh_ADDr_indexed_V4 : memw(Rs+#u6:2)+=Rt
3823 // MEMh_SUBr_indexed_V4 : memw(Rs+#u6:2)-=Rt
3824 // MEMh_CLRr_indexed_V4 : memw(Rs+#u6:2)&=Rt
3825 // MEMh_SETr_indexed_V4 : memw(Rs+#u6:2)|=Rt
3826 // MEMh_ADDi_V4 : memw(Rs+#u6:2)+=#U5
3827 // MEMh_SUBi_V4 : memw(Rs+#u6:2)-=#U5
3828 // MEMh_ADDr_V4 : memw(Rs+#u6:2)+=Rt
3829 // MEMh_SUBr_V4 : memw(Rs+#u6:2)-=Rt
3830 // MEMh_CLRr_V4 : memw(Rs+#u6:2)&=Rt
3831 // MEMh_SETr_V4 : memw(Rs+#u6:2)|=Rt
3834 // MEMh_CLRi_indexed_V4 : memw(Rs+#u6:2)=clrbit(#U5)
3835 // MEMh_SETi_indexed_V4 : memw(Rs+#u6:2)=setbit(#U5)
3836 // MEMh_CLRi_V4 : memw(Rs+#u6:2)=clrbit(#U5)
3837 // MEMh_SETi_V4 : memw(Rs+#u6:2)=setbit(#U5)
3838 //===----------------------------------------------------------------------===//
3841 // memh(Rs+#u6:1) += #U5
3842 let AddedComplexity = 30 in
3843 def MEMh_ADDi_indexed_MEM_V4 : MEMInst_V4<(outs),
3844 (ins IntRegs:$base, u6_1Imm:$offset, u5Imm:$addend),
3845 "memh($base+#$offset) += $addend",
3847 Requires<[HasV4T, UseMEMOP]>;
3849 // memh(Rs+#u6:1) -= #U5
3850 let AddedComplexity = 30 in
3851 def MEMh_SUBi_indexed_MEM_V4 : MEMInst_V4<(outs),
3852 (ins IntRegs:$base, u6_1Imm:$offset, u5Imm:$subend),
3853 "memh($base+#$offset) -= $subend",
3855 Requires<[HasV4T, UseMEMOP]>;
3857 // memh(Rs+#u6:1) += Rt
3858 let AddedComplexity = 30 in
3859 def MEMh_ADDr_indexed_MEM_V4 : MEMInst_V4<(outs),
3860 (ins IntRegs:$base, u6_1Imm:$offset, IntRegs:$addend),
3861 "memh($base+#$offset) += $addend",
3862 [(truncstorei16 (add (sextloadi16 (add (i32 IntRegs:$base),
3863 u6_1ImmPred:$offset)),
3864 (i32 IntRegs:$addend)),
3865 (add (i32 IntRegs:$base), u6_1ImmPred:$offset))]>,
3866 Requires<[HasV4T, UseMEMOP]>;
3868 // memh(Rs+#u6:1) -= Rt
3869 let AddedComplexity = 30 in
3870 def MEMh_SUBr_indexed_MEM_V4 : MEMInst_V4<(outs),
3871 (ins IntRegs:$base, u6_1Imm:$offset, IntRegs:$subend),
3872 "memh($base+#$offset) -= $subend",
3873 [(truncstorei16 (sub (sextloadi16 (add (i32 IntRegs:$base),
3874 u6_1ImmPred:$offset)),
3875 (i32 IntRegs:$subend)),
3876 (add (i32 IntRegs:$base), u6_1ImmPred:$offset))]>,
3877 Requires<[HasV4T, UseMEMOP]>;
3879 // memh(Rs+#u6:1) &= Rt
3880 let AddedComplexity = 30 in
3881 def MEMh_ANDr_indexed_MEM_V4 : MEMInst_V4<(outs),
3882 (ins IntRegs:$base, u6_1Imm:$offset, IntRegs:$andend),
3883 "memh($base+#$offset) += $andend",
3884 [(truncstorei16 (and (sextloadi16 (add (i32 IntRegs:$base),
3885 u6_1ImmPred:$offset)),
3886 (i32 IntRegs:$andend)),
3887 (add (i32 IntRegs:$base), u6_1ImmPred:$offset))]>,
3888 Requires<[HasV4T, UseMEMOP]>;
3890 // memh(Rs+#u6:1) |= Rt
3891 let AddedComplexity = 30 in
3892 def MEMh_ORr_indexed_MEM_V4 : MEMInst_V4<(outs),
3893 (ins IntRegs:$base, u6_1Imm:$offset, IntRegs:$orend),
3894 "memh($base+#$offset) |= $orend",
3895 [(truncstorei16 (or (sextloadi16 (add (i32 IntRegs:$base),
3896 u6_1ImmPred:$offset)),
3897 (i32 IntRegs:$orend)),
3898 (add (i32 IntRegs:$base), u6_1ImmPred:$offset))]>,
3899 Requires<[HasV4T, UseMEMOP]>;
3901 // memh(Rs+#u6:1) += #U5
3902 let AddedComplexity = 30 in
3903 def MEMh_ADDi_MEM_V4 : MEMInst_V4<(outs),
3904 (ins MEMri:$addr, u5Imm:$addend),
3905 "memh($addr) += $addend",
3907 Requires<[HasV4T, UseMEMOP]>;
3909 // memh(Rs+#u6:1) -= #U5
3910 let AddedComplexity = 30 in
3911 def MEMh_SUBi_MEM_V4 : MEMInst_V4<(outs),
3912 (ins MEMri:$addr, u5Imm:$subend),
3913 "memh($addr) -= $subend",
3915 Requires<[HasV4T, UseMEMOP]>;
3917 // memh(Rs+#u6:1) += Rt
3918 let AddedComplexity = 30 in
3919 def MEMh_ADDr_MEM_V4 : MEMInst_V4<(outs),
3920 (ins MEMri:$addr, IntRegs:$addend),
3921 "memh($addr) += $addend",
3922 [(truncstorei16 (add (sextloadi16 ADDRriU6_1:$addr),
3923 (i32 IntRegs:$addend)), ADDRriU6_1:$addr)]>,
3924 Requires<[HasV4T, UseMEMOP]>;
3926 // memh(Rs+#u6:1) -= Rt
3927 let AddedComplexity = 30 in
3928 def MEMh_SUBr_MEM_V4 : MEMInst_V4<(outs),
3929 (ins MEMri:$addr, IntRegs:$subend),
3930 "memh($addr) -= $subend",
3931 [(truncstorei16 (sub (sextloadi16 ADDRriU6_1:$addr),
3932 (i32 IntRegs:$subend)), ADDRriU6_1:$addr)]>,
3933 Requires<[HasV4T, UseMEMOP]>;
3935 // memh(Rs+#u6:1) &= Rt
3936 let AddedComplexity = 30 in
3937 def MEMh_ANDr_MEM_V4 : MEMInst_V4<(outs),
3938 (ins MEMri:$addr, IntRegs:$andend),
3939 "memh($addr) &= $andend",
3940 [(truncstorei16 (and (sextloadi16 ADDRriU6_1:$addr),
3941 (i32 IntRegs:$andend)), ADDRriU6_1:$addr)]>,
3942 Requires<[HasV4T, UseMEMOP]>;
3944 // memh(Rs+#u6:1) |= Rt
3945 let AddedComplexity = 30 in
3946 def MEMh_ORr_MEM_V4 : MEMInst_V4<(outs),
3947 (ins MEMri:$addr, IntRegs:$orend),
3948 "memh($addr) |= $orend",
3949 [(truncstorei16 (or (sextloadi16 ADDRriU6_1:$addr),
3950 (i32 IntRegs:$orend)), ADDRriU6_1:$addr)]>,
3951 Requires<[HasV4T, UseMEMOP]>;
3954 //===----------------------------------------------------------------------===//
3958 // MEMb_ADDi_indexed_V4 : memb(Rs+#u6:0)+=#U5
3959 // MEMb_SUBi_indexed_V4 : memb(Rs+#u6:0)-=#U5
3960 // MEMb_ADDr_indexed_V4 : memb(Rs+#u6:0)+=Rt
3961 // MEMb_SUBr_indexed_V4 : memb(Rs+#u6:0)-=Rt
3962 // MEMb_CLRr_indexed_V4 : memb(Rs+#u6:0)&=Rt
3963 // MEMb_SETr_indexed_V4 : memb(Rs+#u6:0)|=Rt
3964 // MEMb_ADDi_V4 : memb(Rs+#u6:0)+=#U5
3965 // MEMb_SUBi_V4 : memb(Rs+#u6:0)-=#U5
3966 // MEMb_ADDr_V4 : memb(Rs+#u6:0)+=Rt
3967 // MEMb_SUBr_V4 : memb(Rs+#u6:0)-=Rt
3968 // MEMb_CLRr_V4 : memb(Rs+#u6:0)&=Rt
3969 // MEMb_SETr_V4 : memb(Rs+#u6:0)|=Rt
3972 // MEMb_CLRi_indexed_V4 : memb(Rs+#u6:0)=clrbit(#U5)
3973 // MEMb_SETi_indexed_V4 : memb(Rs+#u6:0)=setbit(#U5)
3974 // MEMb_CLRi_V4 : memb(Rs+#u6:0)=clrbit(#U5)
3975 // MEMb_SETi_V4 : memb(Rs+#u6:0)=setbit(#U5)
3976 //===----------------------------------------------------------------------===//
3978 // memb(Rs+#u6:0) += #U5
3979 let AddedComplexity = 30 in
3980 def MEMb_ADDi_indexed_MEM_V4 : MEMInst_V4<(outs),
3981 (ins IntRegs:$base, u6_0Imm:$offset, u5Imm:$addend),
3982 "memb($base+#$offset) += $addend",
3984 Requires<[HasV4T, UseMEMOP]>;
3986 // memb(Rs+#u6:0) -= #U5
3987 let AddedComplexity = 30 in
3988 def MEMb_SUBi_indexed_MEM_V4 : MEMInst_V4<(outs),
3989 (ins IntRegs:$base, u6_0Imm:$offset, u5Imm:$subend),
3990 "memb($base+#$offset) -= $subend",
3992 Requires<[HasV4T, UseMEMOP]>;
3994 // memb(Rs+#u6:0) += Rt
3995 let AddedComplexity = 30 in
3996 def MEMb_ADDr_indexed_MEM_V4 : MEMInst_V4<(outs),
3997 (ins IntRegs:$base, u6_0Imm:$offset, IntRegs:$addend),
3998 "memb($base+#$offset) += $addend",
3999 [(truncstorei8 (add (sextloadi8 (add (i32 IntRegs:$base),
4000 u6_0ImmPred:$offset)),
4001 (i32 IntRegs:$addend)),
4002 (add (i32 IntRegs:$base), u6_0ImmPred:$offset))]>,
4003 Requires<[HasV4T, UseMEMOP]>;
4005 // memb(Rs+#u6:0) -= Rt
4006 let AddedComplexity = 30 in
4007 def MEMb_SUBr_indexed_MEM_V4 : MEMInst_V4<(outs),
4008 (ins IntRegs:$base, u6_0Imm:$offset, IntRegs:$subend),
4009 "memb($base+#$offset) -= $subend",
4010 [(truncstorei8 (sub (sextloadi8 (add (i32 IntRegs:$base),
4011 u6_0ImmPred:$offset)),
4012 (i32 IntRegs:$subend)),
4013 (add (i32 IntRegs:$base), u6_0ImmPred:$offset))]>,
4014 Requires<[HasV4T, UseMEMOP]>;
4016 // memb(Rs+#u6:0) &= Rt
4017 let AddedComplexity = 30 in
4018 def MEMb_ANDr_indexed_MEM_V4 : MEMInst_V4<(outs),
4019 (ins IntRegs:$base, u6_0Imm:$offset, IntRegs:$andend),
4020 "memb($base+#$offset) += $andend",
4021 [(truncstorei8 (and (sextloadi8 (add (i32 IntRegs:$base),
4022 u6_0ImmPred:$offset)),
4023 (i32 IntRegs:$andend)),
4024 (add (i32 IntRegs:$base), u6_0ImmPred:$offset))]>,
4025 Requires<[HasV4T, UseMEMOP]>;
4027 // memb(Rs+#u6:0) |= Rt
4028 let AddedComplexity = 30 in
4029 def MEMb_ORr_indexed_MEM_V4 : MEMInst_V4<(outs),
4030 (ins IntRegs:$base, u6_0Imm:$offset, IntRegs:$orend),
4031 "memb($base+#$offset) |= $orend",
4032 [(truncstorei8 (or (sextloadi8 (add (i32 IntRegs:$base),
4033 u6_0ImmPred:$offset)),
4034 (i32 IntRegs:$orend)),
4035 (add (i32 IntRegs:$base), u6_0ImmPred:$offset))]>,
4036 Requires<[HasV4T, UseMEMOP]>;
4038 // memb(Rs+#u6:0) += #U5
4039 let AddedComplexity = 30 in
4040 def MEMb_ADDi_MEM_V4 : MEMInst_V4<(outs),
4041 (ins MEMri:$addr, u5Imm:$addend),
4042 "memb($addr) += $addend",
4044 Requires<[HasV4T, UseMEMOP]>;
4046 // memb(Rs+#u6:0) -= #U5
4047 let AddedComplexity = 30 in
4048 def MEMb_SUBi_MEM_V4 : MEMInst_V4<(outs),
4049 (ins MEMri:$addr, u5Imm:$subend),
4050 "memb($addr) -= $subend",
4052 Requires<[HasV4T, UseMEMOP]>;
4054 // memb(Rs+#u6:0) += Rt
4055 let AddedComplexity = 30 in
4056 def MEMb_ADDr_MEM_V4 : MEMInst_V4<(outs),
4057 (ins MEMri:$addr, IntRegs:$addend),
4058 "memb($addr) += $addend",
4059 [(truncstorei8 (add (sextloadi8 ADDRriU6_0:$addr),
4060 (i32 IntRegs:$addend)), ADDRriU6_0:$addr)]>,
4061 Requires<[HasV4T, UseMEMOP]>;
4063 // memb(Rs+#u6:0) -= Rt
4064 let AddedComplexity = 30 in
4065 def MEMb_SUBr_MEM_V4 : MEMInst_V4<(outs),
4066 (ins MEMri:$addr, IntRegs:$subend),
4067 "memb($addr) -= $subend",
4068 [(truncstorei8 (sub (sextloadi8 ADDRriU6_0:$addr),
4069 (i32 IntRegs:$subend)), ADDRriU6_0:$addr)]>,
4070 Requires<[HasV4T, UseMEMOP]>;
4072 // memb(Rs+#u6:0) &= Rt
4073 let AddedComplexity = 30 in
4074 def MEMb_ANDr_MEM_V4 : MEMInst_V4<(outs),
4075 (ins MEMri:$addr, IntRegs:$andend),
4076 "memb($addr) &= $andend",
4077 [(truncstorei8 (and (sextloadi8 ADDRriU6_0:$addr),
4078 (i32 IntRegs:$andend)), ADDRriU6_0:$addr)]>,
4079 Requires<[HasV4T, UseMEMOP]>;
4081 // memb(Rs+#u6:0) |= Rt
4082 let AddedComplexity = 30 in
4083 def MEMb_ORr_MEM_V4 : MEMInst_V4<(outs),
4084 (ins MEMri:$addr, IntRegs:$orend),
4085 "memb($addr) |= $orend",
4086 [(truncstorei8 (or (sextloadi8 ADDRriU6_0:$addr),
4087 (i32 IntRegs:$orend)), ADDRriU6_0:$addr)]>,
4088 Requires<[HasV4T, UseMEMOP]>;
4091 //===----------------------------------------------------------------------===//
4093 //===----------------------------------------------------------------------===//
4095 // Hexagon V4 only supports these flavors of byte/half compare instructions:
4096 // EQ/GT/GTU. Other flavors like GE/GEU/LT/LTU/LE/LEU are not supported by
4097 // hardware. However, compiler can still implement these patterns through
4098 // appropriate patterns combinations based on current implemented patterns.
4099 // The implemented patterns are: EQ/GT/GTU.
4100 // Missing patterns are: GE/GEU/LT/LTU/LE/LEU.
4102 // Following instruction is not being extended as it results into the
4103 // incorrect code for negative numbers.
4104 // Pd=cmpb.eq(Rs,#u8)
4106 let isCompare = 1 in
4107 def CMPbEQri_V4 : MInst<(outs PredRegs:$dst),
4108 (ins IntRegs:$src1, u8Imm:$src2),
4109 "$dst = cmpb.eq($src1, #$src2)",
4110 [(set (i1 PredRegs:$dst),
4111 (seteq (and (i32 IntRegs:$src1), 255), u8ImmPred:$src2))]>,
4114 // Pd=cmpb.eq(Rs,Rt)
4115 let isCompare = 1 in
4116 def CMPbEQrr_ubub_V4 : MInst<(outs PredRegs:$dst),
4117 (ins IntRegs:$src1, IntRegs:$src2),
4118 "$dst = cmpb.eq($src1, $src2)",
4119 [(set (i1 PredRegs:$dst),
4120 (seteq (and (xor (i32 IntRegs:$src1),
4121 (i32 IntRegs:$src2)), 255), 0))]>,
4124 // Pd=cmpb.eq(Rs,Rt)
4125 let isCompare = 1 in
4126 def CMPbEQrr_sbsb_V4 : MInst<(outs PredRegs:$dst),
4127 (ins IntRegs:$src1, IntRegs:$src2),
4128 "$dst = cmpb.eq($src1, $src2)",
4129 [(set (i1 PredRegs:$dst),
4130 (seteq (shl (i32 IntRegs:$src1), (i32 24)),
4131 (shl (i32 IntRegs:$src2), (i32 24))))]>,
4134 // Pd=cmpb.gt(Rs,Rt)
4135 let isCompare = 1 in
4136 def CMPbGTrr_V4 : MInst<(outs PredRegs:$dst),
4137 (ins IntRegs:$src1, IntRegs:$src2),
4138 "$dst = cmpb.gt($src1, $src2)",
4139 [(set (i1 PredRegs:$dst),
4140 (setgt (shl (i32 IntRegs:$src1), (i32 24)),
4141 (shl (i32 IntRegs:$src2), (i32 24))))]>,
4144 // Pd=cmpb.gtu(Rs,#u7)
4145 let isCompare = 1 in
4146 def CMPbGTUri_V4 : MInst<(outs PredRegs:$dst),
4147 (ins IntRegs:$src1, u7Imm:$src2),
4148 "$dst = cmpb.gtu($src1, #$src2)",
4149 [(set (i1 PredRegs:$dst), (setugt (and (i32 IntRegs:$src1), 255),
4150 u7ImmPred:$src2))]>,
4153 // Pd=cmpb.gtu(Rs,Rt)
4154 let isCompare = 1 in
4155 def CMPbGTUrr_V4 : MInst<(outs PredRegs:$dst),
4156 (ins IntRegs:$src1, IntRegs:$src2),
4157 "$dst = cmpb.gtu($src1, $src2)",
4158 [(set (i1 PredRegs:$dst), (setugt (and (i32 IntRegs:$src1), 255),
4159 (and (i32 IntRegs:$src2), 255)))]>,
4162 // Following instruction is not being extended as it results into the incorrect
4163 // code for negative numbers.
4165 // Signed half compare(.eq) ri.
4166 // Pd=cmph.eq(Rs,#s8)
4167 let isCompare = 1 in
4168 def CMPhEQri_V4 : MInst<(outs PredRegs:$dst),
4169 (ins IntRegs:$src1, s8Imm:$src2),
4170 "$dst = cmph.eq($src1, #$src2)",
4171 [(set (i1 PredRegs:$dst), (seteq (and (i32 IntRegs:$src1), 65535),
4172 s8ImmPred:$src2))]>,
4175 // Signed half compare(.eq) rr.
4176 // Case 1: xor + and, then compare:
4178 // r0=and(r0,#0xffff)
4180 // Pd=cmph.eq(Rs,Rt)
4181 let isCompare = 1 in
4182 def CMPhEQrr_xor_V4 : MInst<(outs PredRegs:$dst),
4183 (ins IntRegs:$src1, IntRegs:$src2),
4184 "$dst = cmph.eq($src1, $src2)",
4185 [(set (i1 PredRegs:$dst), (seteq (and (xor (i32 IntRegs:$src1),
4186 (i32 IntRegs:$src2)),
4190 // Signed half compare(.eq) rr.
4191 // Case 2: shift left 16 bits then compare:
4195 // Pd=cmph.eq(Rs,Rt)
4196 let isCompare = 1 in
4197 def CMPhEQrr_shl_V4 : MInst<(outs PredRegs:$dst),
4198 (ins IntRegs:$src1, IntRegs:$src2),
4199 "$dst = cmph.eq($src1, $src2)",
4200 [(set (i1 PredRegs:$dst),
4201 (seteq (shl (i32 IntRegs:$src1), (i32 16)),
4202 (shl (i32 IntRegs:$src2), (i32 16))))]>,
4205 /* Incorrect Pattern -- immediate should be right shifted before being
4206 used in the cmph.gt instruction.
4207 // Signed half compare(.gt) ri.
4208 // Pd=cmph.gt(Rs,#s8)
4210 let isCompare = 1 in
4211 def CMPhGTri_V4 : MInst<(outs PredRegs:$dst),
4212 (ins IntRegs:$src1, s8Imm:$src2),
4213 "$dst = cmph.gt($src1, #$src2)",
4214 [(set (i1 PredRegs:$dst),
4215 (setgt (shl (i32 IntRegs:$src1), (i32 16)),
4216 s8ImmPred:$src2))]>,
4220 // Signed half compare(.gt) rr.
4221 // Pd=cmph.gt(Rs,Rt)
4222 let isCompare = 1 in
4223 def CMPhGTrr_shl_V4 : MInst<(outs PredRegs:$dst),
4224 (ins IntRegs:$src1, IntRegs:$src2),
4225 "$dst = cmph.gt($src1, $src2)",
4226 [(set (i1 PredRegs:$dst),
4227 (setgt (shl (i32 IntRegs:$src1), (i32 16)),
4228 (shl (i32 IntRegs:$src2), (i32 16))))]>,
4231 // Unsigned half compare rr (.gtu).
4232 // Pd=cmph.gtu(Rs,Rt)
4233 let isCompare = 1 in
4234 def CMPhGTUrr_V4 : MInst<(outs PredRegs:$dst),
4235 (ins IntRegs:$src1, IntRegs:$src2),
4236 "$dst = cmph.gtu($src1, $src2)",
4237 [(set (i1 PredRegs:$dst),
4238 (setugt (and (i32 IntRegs:$src1), 65535),
4239 (and (i32 IntRegs:$src2), 65535)))]>,
4242 // Unsigned half compare ri (.gtu).
4243 // Pd=cmph.gtu(Rs,#u7)
4244 let isCompare = 1 in
4245 def CMPhGTUri_V4 : MInst<(outs PredRegs:$dst),
4246 (ins IntRegs:$src1, u7Imm:$src2),
4247 "$dst = cmph.gtu($src1, #$src2)",
4248 [(set (i1 PredRegs:$dst), (setugt (and (i32 IntRegs:$src1), 65535),
4249 u7ImmPred:$src2))]>,
4252 //===----------------------------------------------------------------------===//
4254 //===----------------------------------------------------------------------===//
4256 //Deallocate frame and return.
4258 let isReturn = 1, isTerminator = 1, isBarrier = 1, isPredicable = 1,
4259 Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1 in {
4260 def DEALLOC_RET_V4 : NVInst_V4<(outs), (ins i32imm:$amt1),
4266 // Restore registers and dealloc return function call.
4267 let isCall = 1, isBarrier = 1, isReturn = 1, isTerminator = 1,
4268 Defs = [R29, R30, R31, PC] in {
4269 def RESTORE_DEALLOC_RET_JMP_V4 : JInst<(outs),
4270 (ins calltarget:$dst),
4271 "jump $dst // Restore_and_dealloc_return",
4276 // Restore registers and dealloc frame before a tail call.
4277 let isCall = 1, isBarrier = 1,
4278 Defs = [R29, R30, R31, PC] in {
4279 def RESTORE_DEALLOC_BEFORE_TAILCALL_V4 : JInst<(outs),
4280 (ins calltarget:$dst),
4281 "call $dst // Restore_and_dealloc_before_tailcall",
4286 // Save registers function call.
4287 let isCall = 1, isBarrier = 1,
4288 Uses = [R29, R31] in {
4289 def SAVE_REGISTERS_CALL_V4 : JInst<(outs),
4290 (ins calltarget:$dst),
4291 "call $dst // Save_calle_saved_registers",
4296 // if (Ps) dealloc_return
4297 let isReturn = 1, isTerminator = 1,
4298 Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1,
4299 isPredicated = 1 in {
4300 def DEALLOC_RET_cPt_V4 : NVInst_V4<(outs),
4301 (ins PredRegs:$src1, i32imm:$amt1),
4302 "if ($src1) dealloc_return",
4307 // if (!Ps) dealloc_return
4308 let isReturn = 1, isTerminator = 1,
4309 Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1,
4310 isPredicated = 1 in {
4311 def DEALLOC_RET_cNotPt_V4 : NVInst_V4<(outs), (ins PredRegs:$src1,
4313 "if (!$src1) dealloc_return",
4318 // if (Ps.new) dealloc_return:nt
4319 let isReturn = 1, isTerminator = 1,
4320 Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1,
4321 isPredicated = 1 in {
4322 def DEALLOC_RET_cdnPnt_V4 : NVInst_V4<(outs), (ins PredRegs:$src1,
4324 "if ($src1.new) dealloc_return:nt",
4329 // if (!Ps.new) dealloc_return:nt
4330 let isReturn = 1, isTerminator = 1,
4331 Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1,
4332 isPredicated = 1 in {
4333 def DEALLOC_RET_cNotdnPnt_V4 : NVInst_V4<(outs), (ins PredRegs:$src1,
4335 "if (!$src1.new) dealloc_return:nt",
4340 // if (Ps.new) dealloc_return:t
4341 let isReturn = 1, isTerminator = 1,
4342 Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1,
4343 isPredicated = 1 in {
4344 def DEALLOC_RET_cdnPt_V4 : NVInst_V4<(outs), (ins PredRegs:$src1,
4346 "if ($src1.new) dealloc_return:t",
4351 // if (!Ps.new) dealloc_return:nt
4352 let isReturn = 1, isTerminator = 1,
4353 Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1,
4354 isPredicated = 1 in {
4355 def DEALLOC_RET_cNotdnPt_V4 : NVInst_V4<(outs), (ins PredRegs:$src1,
4357 "if (!$src1.new) dealloc_return:t",
4363 // Load/Store with absolute addressing mode
4366 multiclass ST_abs<string OpcStr> {
4367 let isPredicable = 1 in
4368 def _abs_V4 : STInst2<(outs),
4369 (ins globaladdress:$absaddr, IntRegs:$src),
4370 !strconcat(OpcStr, "(##$absaddr) = $src"),
4374 let isPredicated = 1 in
4375 def _abs_cPt_V4 : STInst2<(outs),
4376 (ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2),
4377 !strconcat("if ($src1)",
4378 !strconcat(OpcStr, "(##$absaddr) = $src2")),
4382 let isPredicated = 1 in
4383 def _abs_cNotPt_V4 : STInst2<(outs),
4384 (ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2),
4385 !strconcat("if (!$src1)",
4386 !strconcat(OpcStr, "(##$absaddr) = $src2")),
4390 let isPredicated = 1 in
4391 def _abs_cdnPt_V4 : STInst2<(outs),
4392 (ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2),
4393 !strconcat("if ($src1.new)",
4394 !strconcat(OpcStr, "(##$absaddr) = $src2")),
4398 let isPredicated = 1 in
4399 def _abs_cdnNotPt_V4 : STInst2<(outs),
4400 (ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2),
4401 !strconcat("if (!$src1.new)",
4402 !strconcat(OpcStr, "(##$absaddr) = $src2")),
4406 def _abs_nv_V4 : STInst2<(outs),
4407 (ins globaladdress:$absaddr, IntRegs:$src),
4408 !strconcat(OpcStr, "(##$absaddr) = $src.new"),
4412 let isPredicated = 1 in
4413 def _abs_cPt_nv_V4 : STInst2<(outs),
4414 (ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2),
4415 !strconcat("if ($src1)",
4416 !strconcat(OpcStr, "(##$absaddr) = $src2.new")),
4420 let isPredicated = 1 in
4421 def _abs_cNotPt_nv_V4 : STInst2<(outs),
4422 (ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2),
4423 !strconcat("if (!$src1)",
4424 !strconcat(OpcStr, "(##$absaddr) = $src2.new")),
4428 let isPredicated = 1 in
4429 def _abs_cdnPt_nv_V4 : STInst2<(outs),
4430 (ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2),
4431 !strconcat("if ($src1.new)",
4432 !strconcat(OpcStr, "(##$absaddr) = $src2.new")),
4436 let isPredicated = 1 in
4437 def _abs_cdnNotPt_nv_V4 : STInst2<(outs),
4438 (ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2),
4439 !strconcat("if (!$src1.new)",
4440 !strconcat(OpcStr, "(##$absaddr) = $src2.new")),
4445 let AddedComplexity = 30, isPredicable = 1 in
4446 def STrid_abs_V4 : STInst<(outs),
4447 (ins globaladdress:$absaddr, DoubleRegs:$src),
4448 "memd(##$absaddr) = $src",
4449 [(store (i64 DoubleRegs:$src),
4450 (HexagonCONST32 tglobaladdr:$absaddr))]>,
4453 let AddedComplexity = 30, isPredicated = 1 in
4454 def STrid_abs_cPt_V4 : STInst2<(outs),
4455 (ins PredRegs:$src1, globaladdress:$absaddr, DoubleRegs:$src2),
4456 "if ($src1) memd(##$absaddr) = $src2",
4460 let AddedComplexity = 30, isPredicated = 1 in
4461 def STrid_abs_cNotPt_V4 : STInst2<(outs),
4462 (ins PredRegs:$src1, globaladdress:$absaddr, DoubleRegs:$src2),
4463 "if (!$src1) memd(##$absaddr) = $src2",
4467 let AddedComplexity = 30, isPredicated = 1 in
4468 def STrid_abs_cdnPt_V4 : STInst2<(outs),
4469 (ins PredRegs:$src1, globaladdress:$absaddr, DoubleRegs:$src2),
4470 "if ($src1.new) memd(##$absaddr) = $src2",
4474 let AddedComplexity = 30, isPredicated = 1 in
4475 def STrid_abs_cdnNotPt_V4 : STInst2<(outs),
4476 (ins PredRegs:$src1, globaladdress:$absaddr, DoubleRegs:$src2),
4477 "if (!$src1.new) memd(##$absaddr) = $src2",
4481 defm STrib : ST_abs<"memb">;
4482 defm STrih : ST_abs<"memh">;
4483 defm STriw : ST_abs<"memw">;
4485 let Predicates = [HasV4T], AddedComplexity = 30 in
4486 def : Pat<(truncstorei8 (i32 IntRegs:$src1),
4487 (HexagonCONST32 tglobaladdr:$absaddr)),
4488 (STrib_abs_V4 tglobaladdr: $absaddr, IntRegs: $src1)>;
4490 let Predicates = [HasV4T], AddedComplexity = 30 in
4491 def : Pat<(truncstorei16 (i32 IntRegs:$src1),
4492 (HexagonCONST32 tglobaladdr:$absaddr)),
4493 (STrih_abs_V4 tglobaladdr: $absaddr, IntRegs: $src1)>;
4495 let Predicates = [HasV4T], AddedComplexity = 30 in
4496 def : Pat<(store (i32 IntRegs:$src1), (HexagonCONST32 tglobaladdr:$absaddr)),
4497 (STriw_abs_V4 tglobaladdr: $absaddr, IntRegs: $src1)>;
4500 multiclass LD_abs<string OpcStr> {
4501 let isPredicable = 1 in
4502 def _abs_V4 : LDInst2<(outs IntRegs:$dst),
4503 (ins globaladdress:$absaddr),
4504 !strconcat("$dst = ", !strconcat(OpcStr, "(##$absaddr)")),
4508 let isPredicated = 1 in
4509 def _abs_cPt_V4 : LDInst2<(outs IntRegs:$dst),
4510 (ins PredRegs:$src1, globaladdress:$absaddr),
4511 !strconcat("if ($src1) $dst = ",
4512 !strconcat(OpcStr, "(##$absaddr)")),
4516 let isPredicated = 1 in
4517 def _abs_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
4518 (ins PredRegs:$src1, globaladdress:$absaddr),
4519 !strconcat("if (!$src1) $dst = ",
4520 !strconcat(OpcStr, "(##$absaddr)")),
4524 let isPredicated = 1 in
4525 def _abs_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
4526 (ins PredRegs:$src1, globaladdress:$absaddr),
4527 !strconcat("if ($src1.new) $dst = ",
4528 !strconcat(OpcStr, "(##$absaddr)")),
4532 let isPredicated = 1 in
4533 def _abs_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
4534 (ins PredRegs:$src1, globaladdress:$absaddr),
4535 !strconcat("if (!$src1.new) $dst = ",
4536 !strconcat(OpcStr, "(##$absaddr)")),
4541 let AddedComplexity = 30 in
4542 def LDrid_abs_V4 : LDInst<(outs DoubleRegs:$dst),
4543 (ins globaladdress:$absaddr),
4544 "$dst = memd(##$absaddr)",
4545 [(set (i64 DoubleRegs:$dst),
4546 (load (HexagonCONST32 tglobaladdr:$absaddr)))]>,
4549 let AddedComplexity = 30, isPredicated = 1 in
4550 def LDrid_abs_cPt_V4 : LDInst2<(outs DoubleRegs:$dst),
4551 (ins PredRegs:$src1, globaladdress:$absaddr),
4552 "if ($src1) $dst = memd(##$absaddr)",
4556 let AddedComplexity = 30, isPredicated = 1 in
4557 def LDrid_abs_cNotPt_V4 : LDInst2<(outs DoubleRegs:$dst),
4558 (ins PredRegs:$src1, globaladdress:$absaddr),
4559 "if (!$src1) $dst = memd(##$absaddr)",
4563 let AddedComplexity = 30, isPredicated = 1 in
4564 def LDrid_abs_cdnPt_V4 : LDInst2<(outs DoubleRegs:$dst),
4565 (ins PredRegs:$src1, globaladdress:$absaddr),
4566 "if ($src1.new) $dst = memd(##$absaddr)",
4570 let AddedComplexity = 30, isPredicated = 1 in
4571 def LDrid_abs_cdnNotPt_V4 : LDInst2<(outs DoubleRegs:$dst),
4572 (ins PredRegs:$src1, globaladdress:$absaddr),
4573 "if (!$src1.new) $dst = memd(##$absaddr)",
4577 defm LDrib : LD_abs<"memb">;
4578 defm LDriub : LD_abs<"memub">;
4579 defm LDrih : LD_abs<"memh">;
4580 defm LDriuh : LD_abs<"memuh">;
4581 defm LDriw : LD_abs<"memw">;
4584 let Predicates = [HasV4T], AddedComplexity = 30 in
4585 def : Pat<(i32 (load (HexagonCONST32 tglobaladdr:$absaddr))),
4586 (LDriw_abs_V4 tglobaladdr: $absaddr)>;
4588 let Predicates = [HasV4T], AddedComplexity=30 in
4589 def : Pat<(i32 (sextloadi8 (HexagonCONST32 tglobaladdr:$absaddr))),
4590 (LDrib_abs_V4 tglobaladdr:$absaddr)>;
4592 let Predicates = [HasV4T], AddedComplexity=30 in
4593 def : Pat<(i32 (zextloadi8 (HexagonCONST32 tglobaladdr:$absaddr))),
4594 (LDriub_abs_V4 tglobaladdr:$absaddr)>;
4596 let Predicates = [HasV4T], AddedComplexity=30 in
4597 def : Pat<(i32 (sextloadi16 (HexagonCONST32 tglobaladdr:$absaddr))),
4598 (LDrih_abs_V4 tglobaladdr:$absaddr)>;
4600 let Predicates = [HasV4T], AddedComplexity=30 in
4601 def : Pat<(i32 (zextloadi16 (HexagonCONST32 tglobaladdr:$absaddr))),
4602 (LDriuh_abs_V4 tglobaladdr:$absaddr)>;
4604 // Transfer global address into a register
4605 let AddedComplexity=50, isMoveImm = 1, isReMaterializable = 1 in
4606 def TFRI_V4 : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$src1),
4608 [(set IntRegs:$dst, (HexagonCONST32 tglobaladdr:$src1))]>,
4611 let AddedComplexity=50, neverHasSideEffects = 1, isPredicated = 1 in
4612 def TFRI_cPt_V4 : ALU32_ri<(outs IntRegs:$dst),
4613 (ins PredRegs:$src1, globaladdress:$src2),
4614 "if($src1) $dst = ##$src2",
4618 let AddedComplexity=50, neverHasSideEffects = 1, isPredicated = 1 in
4619 def TFRI_cNotPt_V4 : ALU32_ri<(outs IntRegs:$dst),
4620 (ins PredRegs:$src1, globaladdress:$src2),
4621 "if(!$src1) $dst = ##$src2",
4625 let AddedComplexity=50, neverHasSideEffects = 1, isPredicated = 1 in
4626 def TFRI_cdnPt_V4 : ALU32_ri<(outs IntRegs:$dst),
4627 (ins PredRegs:$src1, globaladdress:$src2),
4628 "if($src1.new) $dst = ##$src2",
4632 let AddedComplexity=50, neverHasSideEffects = 1, isPredicated = 1 in
4633 def TFRI_cdnNotPt_V4 : ALU32_ri<(outs IntRegs:$dst),
4634 (ins PredRegs:$src1, globaladdress:$src2),
4635 "if(!$src1.new) $dst = ##$src2",
4639 let AddedComplexity = 50, Predicates = [HasV4T] in
4640 def : Pat<(HexagonCONST32_GP tglobaladdr:$src1),
4641 (TFRI_V4 tglobaladdr:$src1)>;
4644 // Load - Indirect with long offset: These instructions take global address
4646 let AddedComplexity = 10 in
4647 def LDrid_ind_lo_V4 : LDInst<(outs DoubleRegs:$dst),
4648 (ins IntRegs:$src1, u2Imm:$src2, globaladdress:$offset),
4649 "$dst=memd($src1<<#$src2+##$offset)",
4650 [(set (i64 DoubleRegs:$dst),
4651 (load (add (shl IntRegs:$src1, u2ImmPred:$src2),
4652 (HexagonCONST32 tglobaladdr:$offset))))]>,
4655 let AddedComplexity = 10 in
4656 multiclass LD_indirect_lo<string OpcStr, PatFrag OpNode> {
4657 def _lo_V4 : LDInst<(outs IntRegs:$dst),
4658 (ins IntRegs:$src1, u2Imm:$src2, globaladdress:$offset),
4659 !strconcat("$dst = ",
4660 !strconcat(OpcStr, "($src1<<#$src2+##$offset)")),
4662 (i32 (OpNode (add (shl IntRegs:$src1, u2ImmPred:$src2),
4663 (HexagonCONST32 tglobaladdr:$offset)))))]>,
4667 defm LDrib_ind : LD_indirect_lo<"memb", sextloadi8>;
4668 defm LDriub_ind : LD_indirect_lo<"memub", zextloadi8>;
4669 defm LDrih_ind : LD_indirect_lo<"memh", sextloadi16>;
4670 defm LDriuh_ind : LD_indirect_lo<"memuh", zextloadi16>;
4671 defm LDriw_ind : LD_indirect_lo<"memw", load>;
4673 // Store - Indirect with long offset: These instructions take global address
4675 let AddedComplexity = 10 in
4676 def STrid_ind_lo_V4 : STInst<(outs),
4677 (ins IntRegs:$src1, u2Imm:$src2, globaladdress:$src3,
4679 "memd($src1<<#$src2+#$src3) = $src4",
4680 [(store (i64 DoubleRegs:$src4),
4681 (add (shl IntRegs:$src1, u2ImmPred:$src2),
4682 (HexagonCONST32 tglobaladdr:$src3)))]>,
4685 let AddedComplexity = 10 in
4686 multiclass ST_indirect_lo<string OpcStr, PatFrag OpNode> {
4687 def _lo_V4 : STInst<(outs),
4688 (ins IntRegs:$src1, u2Imm:$src2, globaladdress:$src3,
4690 !strconcat(OpcStr, "($src1<<#$src2+##$src3) = $src4"),
4691 [(OpNode (i32 IntRegs:$src4),
4692 (add (shl IntRegs:$src1, u2ImmPred:$src2),
4693 (HexagonCONST32 tglobaladdr:$src3)))]>,
4697 defm STrib_ind : ST_indirect_lo<"memb", truncstorei8>;
4698 defm STrih_ind : ST_indirect_lo<"memh", truncstorei16>;
4699 defm STriw_ind : ST_indirect_lo<"memw", store>;
4701 // Store - absolute addressing mode: These instruction take constant
4702 // value as the extended operand
4703 multiclass ST_absimm<string OpcStr> {
4704 let isPredicable = 1 in
4705 def _abs_V4 : STInst2<(outs),
4706 (ins u6Imm:$src1, IntRegs:$src2),
4707 !strconcat(OpcStr, "(#$src1) = $src2"),
4711 let isPredicated = 1 in
4712 def _abs_cPt_V4 : STInst2<(outs),
4713 (ins PredRegs:$src1, u6Imm:$src2, IntRegs:$src3),
4714 !strconcat("if ($src1)", !strconcat(OpcStr, "(#$src2) = $src3")),
4718 let isPredicated = 1 in
4719 def _abs_cNotPt_V4 : STInst2<(outs),
4720 (ins PredRegs:$src1, u6Imm:$src2, IntRegs:$src3),
4721 !strconcat("if (!$src1)", !strconcat(OpcStr, "(#$src2) = $src3")),
4725 let isPredicated = 1 in
4726 def _abs_cdnPt_V4 : STInst2<(outs),
4727 (ins PredRegs:$src1, u6Imm:$src2, IntRegs:$src3),
4728 !strconcat("if ($src1.new)",
4729 !strconcat(OpcStr, "(#$src2) = $src3")),
4733 let isPredicated = 1 in
4734 def _abs_cdnNotPt_V4 : STInst2<(outs),
4735 (ins PredRegs:$src1, u6Imm:$src2, IntRegs:$src3),
4736 !strconcat("if (!$src1.new)",
4737 !strconcat(OpcStr, "(#$src2) = $src3")),
4741 def _abs_nv_V4 : STInst2<(outs),
4742 (ins u6Imm:$src1, IntRegs:$src2),
4743 !strconcat(OpcStr, "(#$src1) = $src2.new"),
4747 let isPredicated = 1 in
4748 def _abs_cPt_nv_V4 : STInst2<(outs),
4749 (ins PredRegs:$src1, u6Imm:$src2, IntRegs:$src3),
4750 !strconcat("if ($src1)",
4751 !strconcat(OpcStr, "(#$src2) = $src3.new")),
4755 let isPredicated = 1 in
4756 def _abs_cNotPt_nv_V4 : STInst2<(outs),
4757 (ins PredRegs:$src1, u6Imm:$src2, IntRegs:$src3),
4758 !strconcat("if (!$src1)",
4759 !strconcat(OpcStr, "(#$src2) = $src3.new")),
4763 let isPredicated = 1 in
4764 def _abs_cdnPt_nv_V4 : STInst2<(outs),
4765 (ins PredRegs:$src1, u6Imm:$src2, IntRegs:$src3),
4766 !strconcat("if ($src1.new)",
4767 !strconcat(OpcStr, "(#$src2) = $src3.new")),
4771 let isPredicated = 1 in
4772 def _abs_cdnNotPt_nv_V4 : STInst2<(outs),
4773 (ins PredRegs:$src1, u6Imm:$src2, IntRegs:$src3),
4774 !strconcat("if (!$src1.new)",
4775 !strconcat(OpcStr, "(#$src2) = $src3.new")),
4780 defm STrib_imm : ST_absimm<"memb">;
4781 defm STrih_imm : ST_absimm<"memh">;
4782 defm STriw_imm : ST_absimm<"memw">;
4784 let Predicates = [HasV4T], AddedComplexity = 30 in
4785 def : Pat<(truncstorei8 (i32 IntRegs:$src1), u6ImmPred:$src2),
4786 (STrib_imm_abs_V4 u6ImmPred:$src2, IntRegs: $src1)>;
4788 let Predicates = [HasV4T], AddedComplexity = 30 in
4789 def : Pat<(truncstorei16 (i32 IntRegs:$src1), u6ImmPred:$src2),
4790 (STrih_imm_abs_V4 u6ImmPred:$src2, IntRegs: $src1)>;
4792 let Predicates = [HasV4T], AddedComplexity = 30 in
4793 def : Pat<(store (i32 IntRegs:$src1), u6ImmPred:$src2),
4794 (STriw_imm_abs_V4 u6ImmPred:$src2, IntRegs: $src1)>;
4797 // Load - absolute addressing mode: These instruction take constant
4798 // value as the extended operand
4800 multiclass LD_absimm<string OpcStr> {
4801 let isPredicable = 1 in
4802 def _abs_V4 : LDInst2<(outs IntRegs:$dst),
4804 !strconcat("$dst = ",
4805 !strconcat(OpcStr, "(#$src)")),
4809 let isPredicated = 1 in
4810 def _abs_cPt_V4 : LDInst2<(outs IntRegs:$dst),
4811 (ins PredRegs:$src1, u6Imm:$src2),
4812 !strconcat("if ($src1) $dst = ",
4813 !strconcat(OpcStr, "(#$src2)")),
4817 let isPredicated = 1 in
4818 def _abs_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
4819 (ins PredRegs:$src1, u6Imm:$src2),
4820 !strconcat("if (!$src1) $dst = ",
4821 !strconcat(OpcStr, "(#$src2)")),
4825 let isPredicated = 1 in
4826 def _abs_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
4827 (ins PredRegs:$src1, u6Imm:$src2),
4828 !strconcat("if ($src1.new) $dst = ",
4829 !strconcat(OpcStr, "(#$src2)")),
4833 let isPredicated = 1 in
4834 def _abs_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
4835 (ins PredRegs:$src1, u6Imm:$src2),
4836 !strconcat("if (!$src1.new) $dst = ",
4837 !strconcat(OpcStr, "(#$src2)")),
4842 defm LDrib_imm : LD_absimm<"memb">;
4843 defm LDriub_imm : LD_absimm<"memub">;
4844 defm LDrih_imm : LD_absimm<"memh">;
4845 defm LDriuh_imm : LD_absimm<"memuh">;
4846 defm LDriw_imm : LD_absimm<"memw">;
4848 let Predicates = [HasV4T], AddedComplexity = 30 in
4849 def : Pat<(i32 (load u6ImmPred:$src)),
4850 (LDriw_imm_abs_V4 u6ImmPred:$src)>;
4852 let Predicates = [HasV4T], AddedComplexity=30 in
4853 def : Pat<(i32 (sextloadi8 u6ImmPred:$src)),
4854 (LDrib_imm_abs_V4 u6ImmPred:$src)>;
4856 let Predicates = [HasV4T], AddedComplexity=30 in
4857 def : Pat<(i32 (zextloadi8 u6ImmPred:$src)),
4858 (LDriub_imm_abs_V4 u6ImmPred:$src)>;
4860 let Predicates = [HasV4T], AddedComplexity=30 in
4861 def : Pat<(i32 (sextloadi16 u6ImmPred:$src)),
4862 (LDrih_imm_abs_V4 u6ImmPred:$src)>;
4864 let Predicates = [HasV4T], AddedComplexity=30 in
4865 def : Pat<(i32 (zextloadi16 u6ImmPred:$src)),
4866 (LDriuh_imm_abs_V4 u6ImmPred:$src)>;
4869 // Indexed store double word - global address.
4870 // memw(Rs+#u6:2)=#S8
4871 let AddedComplexity = 10 in
4872 def STriw_offset_ext_V4 : STInst<(outs),
4873 (ins IntRegs:$src1, u6_2Imm:$src2, globaladdress:$src3),
4874 "memw($src1+#$src2) = ##$src3",
4875 [(store (HexagonCONST32 tglobaladdr:$src3),
4876 (add IntRegs:$src1, u6_2ImmPred:$src2))]>,
4880 // Indexed store double word - global address.
4881 // memw(Rs+#u6:2)=#S8
4882 let AddedComplexity = 10 in
4883 def STrih_offset_ext_V4 : STInst<(outs),
4884 (ins IntRegs:$src1, u6_1Imm:$src2, globaladdress:$src3),
4885 "memh($src1+#$src2) = ##$src3",
4886 [(truncstorei16 (HexagonCONST32 tglobaladdr:$src3),
4887 (add IntRegs:$src1, u6_1ImmPred:$src2))]>,