1 //=- HexagonInstrInfoV4.td - Target Desc. for Hexagon Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Hexagon V4 instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 def DuplexIClass0: InstDuplex < 0 >;
15 def DuplexIClass1: InstDuplex < 1 >;
16 def DuplexIClass2: InstDuplex < 2 >;
17 let isExtendable = 1 in {
18 def DuplexIClass3: InstDuplex < 3 >;
19 def DuplexIClass4: InstDuplex < 4 >;
20 def DuplexIClass5: InstDuplex < 5 >;
21 def DuplexIClass6: InstDuplex < 6 >;
22 def DuplexIClass7: InstDuplex < 7 >;
24 def DuplexIClass8: InstDuplex < 8 >;
25 def DuplexIClass9: InstDuplex < 9 >;
26 def DuplexIClassA: InstDuplex < 0xA >;
27 def DuplexIClassB: InstDuplex < 0xB >;
28 def DuplexIClassC: InstDuplex < 0xC >;
29 def DuplexIClassD: InstDuplex < 0xD >;
30 def DuplexIClassE: InstDuplex < 0xE >;
31 def DuplexIClassF: InstDuplex < 0xF >;
33 def addrga: PatLeaf<(i32 AddrGA:$Addr)>;
34 def addrgp: PatLeaf<(i32 AddrGP:$Addr)>;
36 let hasSideEffects = 0 in
37 class T_Immext<Operand ImmType>
38 : EXTENDERInst<(outs), (ins ImmType:$imm),
39 "immext(#$imm)", []> {
43 let Inst{27-16} = imm{31-20};
44 let Inst{13-0} = imm{19-6};
47 def A4_ext : T_Immext<u26_6Imm>;
48 let isCodeGenOnly = 1 in {
50 def A4_ext_b : T_Immext<brtarget>;
52 def A4_ext_c : T_Immext<calltarget>;
53 def A4_ext_g : T_Immext<globaladdress>;
56 def BITPOS32 : SDNodeXForm<imm, [{
57 // Return the bit position we will set [0-31].
59 int32_t imm = N->getSExtValue();
60 return XformMskToBitPosU5Imm(imm);
64 // Hexagon V4 Architecture spec defines 8 instruction classes:
65 // LD ST ALU32 XTYPE J JR MEMOP NV CR SYSTEM(system is not implemented in the
69 // ========================================
70 // Loads (8/16/32/64 bit)
74 // ========================================
75 // Stores (8/16/32/64 bit)
78 // ALU32 Instructions:
79 // ========================================
80 // Arithmetic / Logical (32 bit)
83 // XTYPE Instructions (32/64 bit):
84 // ========================================
85 // Arithmetic, Logical, Bit Manipulation
86 // Multiply (Integer, Fractional, Complex)
87 // Permute / Vector Permute Operations
88 // Predicate Operations
89 // Shift / Shift with Add/Sub/Logical
91 // Vector Halfword (ALU, Shift, Multiply)
92 // Vector Word (ALU, Shift)
95 // ========================================
96 // Jump/Call PC-relative
99 // ========================================
100 // Jump/Call Register
102 // MEMOP Instructions:
103 // ========================================
104 // Operation on memory (8/16/32 bit)
107 // ========================================
112 // ========================================
113 // Control-Register Transfers
114 // Hardware Loop Setup
115 // Predicate Logicals & Reductions
117 // SYSTEM Instructions (not implemented in the compiler):
118 // ========================================
124 //===----------------------------------------------------------------------===//
126 //===----------------------------------------------------------------------===//
128 class T_ALU32_3op_not<string mnemonic, bits<3> MajOp, bits<3> MinOp,
130 : T_ALU32_3op<mnemonic, MajOp, MinOp, OpsRev, 0> {
131 let AsmString = "$Rd = "#mnemonic#"($Rs, ~$Rt)";
134 let BaseOpcode = "andn_rr", CextOpcode = "andn" in
135 def A4_andn : T_ALU32_3op_not<"and", 0b001, 0b100, 1>;
136 let BaseOpcode = "orn_rr", CextOpcode = "orn" in
137 def A4_orn : T_ALU32_3op_not<"or", 0b001, 0b101, 1>;
139 let CextOpcode = "rcmp.eq" in
140 def A4_rcmpeq : T_ALU32_3op<"cmp.eq", 0b011, 0b010, 0, 1>;
141 let CextOpcode = "!rcmp.eq" in
142 def A4_rcmpneq : T_ALU32_3op<"!cmp.eq", 0b011, 0b011, 0, 1>;
144 def C4_cmpneq : T_ALU32_3op_cmp<"!cmp.eq", 0b00, 1, 1>;
145 def C4_cmplte : T_ALU32_3op_cmp<"!cmp.gt", 0b10, 1, 0>;
146 def C4_cmplteu : T_ALU32_3op_cmp<"!cmp.gtu", 0b11, 1, 0>;
148 // Pats for instruction selection.
150 // A class to embed the usual comparison patfrags within a zext to i32.
151 // The seteq/setne frags use "lhs" and "rhs" as operands, so use the same
152 // names, or else the frag's "body" won't match the operands.
153 class CmpInReg<PatFrag Op>
154 : PatFrag<(ops node:$lhs, node:$rhs),(i32 (zext (i1 Op.Fragment)))>;
156 def: T_cmp32_rr_pat<A4_rcmpeq, CmpInReg<seteq>, i32>;
157 def: T_cmp32_rr_pat<A4_rcmpneq, CmpInReg<setne>, i32>;
159 def: T_cmp32_rr_pat<C4_cmpneq, setne, i1>;
160 def: T_cmp32_rr_pat<C4_cmplteu, setule, i1>;
162 def: T_cmp32_rr_pat<C4_cmplteu, RevCmp<setuge>, i1>;
164 class T_CMP_rrbh<string mnemonic, bits<3> MinOp, bit IsComm>
165 : SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, IntRegs:$Rt),
166 "$Pd = "#mnemonic#"($Rs, $Rt)", [], "", S_3op_tc_2early_SLOT23>,
168 let InputType = "reg";
169 let CextOpcode = mnemonic;
171 let isCommutable = IsComm;
172 let hasSideEffects = 0;
179 let Inst{27-21} = 0b0111110;
180 let Inst{20-16} = Rs;
182 let Inst{7-5} = MinOp;
186 def A4_cmpbeq : T_CMP_rrbh<"cmpb.eq", 0b110, 1>;
187 def A4_cmpbgt : T_CMP_rrbh<"cmpb.gt", 0b010, 0>;
188 def A4_cmpbgtu : T_CMP_rrbh<"cmpb.gtu", 0b111, 0>;
189 def A4_cmpheq : T_CMP_rrbh<"cmph.eq", 0b011, 1>;
190 def A4_cmphgt : T_CMP_rrbh<"cmph.gt", 0b100, 0>;
191 def A4_cmphgtu : T_CMP_rrbh<"cmph.gtu", 0b101, 0>;
193 let AddedComplexity = 100 in {
194 def: Pat<(i1 (seteq (and (xor (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)),
196 (A4_cmpbeq IntRegs:$Rs, IntRegs:$Rt)>;
197 def: Pat<(i1 (setne (and (xor (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)),
199 (C2_not (A4_cmpbeq IntRegs:$Rs, IntRegs:$Rt))>;
200 def: Pat<(i1 (seteq (and (xor (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)),
202 (A4_cmpheq IntRegs:$Rs, IntRegs:$Rt)>;
203 def: Pat<(i1 (setne (and (xor (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)),
205 (C2_not (A4_cmpheq IntRegs:$Rs, IntRegs:$Rt))>;
208 class T_CMP_ribh<string mnemonic, bits<2> MajOp, bit IsHalf, bit IsComm,
209 Operand ImmType, bit IsImmExt, bit IsImmSigned, int ImmBits>
210 : ALU64Inst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, ImmType:$Imm),
211 "$Pd = "#mnemonic#"($Rs, #$Imm)", [], "", ALU64_tc_2early_SLOT23>,
213 let InputType = "imm";
214 let CextOpcode = mnemonic;
216 let isCommutable = IsComm;
217 let hasSideEffects = 0;
218 let isExtendable = IsImmExt;
219 let opExtendable = !if (IsImmExt, 2, 0);
220 let isExtentSigned = IsImmSigned;
221 let opExtentBits = ImmBits;
228 let Inst{27-24} = 0b1101;
229 let Inst{22-21} = MajOp;
230 let Inst{20-16} = Rs;
231 let Inst{12-5} = Imm;
233 let Inst{3} = IsHalf;
237 def A4_cmpbeqi : T_CMP_ribh<"cmpb.eq", 0b00, 0, 1, u8Imm, 0, 0, 8>;
238 def A4_cmpbgti : T_CMP_ribh<"cmpb.gt", 0b01, 0, 0, s8Imm, 0, 1, 8>;
239 def A4_cmpbgtui : T_CMP_ribh<"cmpb.gtu", 0b10, 0, 0, u7Ext, 1, 0, 7>;
240 def A4_cmpheqi : T_CMP_ribh<"cmph.eq", 0b00, 1, 1, s8Ext, 1, 1, 8>;
241 def A4_cmphgti : T_CMP_ribh<"cmph.gt", 0b01, 1, 0, s8Ext, 1, 1, 8>;
242 def A4_cmphgtui : T_CMP_ribh<"cmph.gtu", 0b10, 1, 0, u7Ext, 1, 0, 7>;
244 class T_RCMP_EQ_ri<string mnemonic, bit IsNeg>
245 : ALU32_ri<(outs IntRegs:$Rd), (ins IntRegs:$Rs, s8Ext:$s8),
246 "$Rd = "#mnemonic#"($Rs, #$s8)", [], "", ALU32_2op_tc_1_SLOT0123>,
248 let InputType = "imm";
249 let CextOpcode = !if (IsNeg, "!rcmp.eq", "rcmp.eq");
250 let isExtendable = 1;
251 let opExtendable = 2;
252 let isExtentSigned = 1;
253 let opExtentBits = 8;
261 let Inst{27-24} = 0b0011;
263 let Inst{21} = IsNeg;
264 let Inst{20-16} = Rs;
270 def A4_rcmpeqi : T_RCMP_EQ_ri<"cmp.eq", 0>;
271 def A4_rcmpneqi : T_RCMP_EQ_ri<"!cmp.eq", 1>;
273 def: Pat<(i32 (zext (i1 (seteq (i32 IntRegs:$Rs), s32ImmPred:$s8)))),
274 (A4_rcmpeqi IntRegs:$Rs, s32ImmPred:$s8)>;
275 def: Pat<(i32 (zext (i1 (setne (i32 IntRegs:$Rs), s32ImmPred:$s8)))),
276 (A4_rcmpneqi IntRegs:$Rs, s32ImmPred:$s8)>;
278 // Preserve the S2_tstbit_r generation
279 def: Pat<(i32 (zext (i1 (setne (i32 (and (i32 (shl 1, (i32 IntRegs:$src2))),
280 (i32 IntRegs:$src1))), 0)))),
281 (C2_muxii (S2_tstbit_r IntRegs:$src1, IntRegs:$src2), 1, 0)>;
283 //===----------------------------------------------------------------------===//
285 //===----------------------------------------------------------------------===//
288 //===----------------------------------------------------------------------===//
290 //===----------------------------------------------------------------------===//
292 // Combine a word and an immediate into a register pair.
293 let hasSideEffects = 0, isExtentSigned = 1, isExtendable = 1,
295 class T_Combine1 <bits<2> MajOp, dag ins, string AsmStr>
296 : ALU32Inst <(outs DoubleRegs:$Rdd), ins, AsmStr> {
302 let Inst{27-24} = 0b0011;
303 let Inst{22-21} = MajOp;
304 let Inst{20-16} = Rs;
310 let opExtendable = 2 in
311 def A4_combineri : T_Combine1<0b00, (ins IntRegs:$Rs, s8Ext:$s8),
312 "$Rdd = combine($Rs, #$s8)">;
314 let opExtendable = 1 in
315 def A4_combineir : T_Combine1<0b01, (ins s8Ext:$s8, IntRegs:$Rs),
316 "$Rdd = combine(#$s8, $Rs)">;
318 // The complexity of the combines involving immediates should be greater
319 // than the complexity of the combine with two registers.
320 let AddedComplexity = 50 in {
321 def: Pat<(HexagonCOMBINE IntRegs:$r, s32ImmPred:$i),
322 (A4_combineri IntRegs:$r, s32ImmPred:$i)>;
324 def: Pat<(HexagonCOMBINE s32ImmPred:$i, IntRegs:$r),
325 (A4_combineir s32ImmPred:$i, IntRegs:$r)>;
328 // A4_combineii: Set two small immediates.
329 let hasSideEffects = 0, isExtendable = 1, opExtentBits = 6, opExtendable = 2 in
330 def A4_combineii: ALU32Inst<(outs DoubleRegs:$Rdd), (ins s8Imm:$s8, u6Ext:$U6),
331 "$Rdd = combine(#$s8, #$U6)"> {
337 let Inst{27-23} = 0b11001;
338 let Inst{20-16} = U6{5-1};
339 let Inst{13} = U6{0};
344 // The complexity of the combine with two immediates should be greater than
345 // the complexity of a combine involving a register.
346 let AddedComplexity = 75 in
347 def: Pat<(HexagonCOMBINE s8ImmPred:$s8, u32ImmPred:$u6),
348 (A4_combineii imm:$s8, imm:$u6)>;
350 //===----------------------------------------------------------------------===//
352 //===----------------------------------------------------------------------===//
354 //===----------------------------------------------------------------------===//
356 //===----------------------------------------------------------------------===//
358 def Zext64: OutPatFrag<(ops node:$Rs),
359 (i64 (A4_combineir 0, (i32 $Rs)))>;
360 def Sext64: OutPatFrag<(ops node:$Rs),
361 (i64 (A2_sxtw (i32 $Rs)))>;
363 // Patterns to generate indexed loads with different forms of the address:
366 // - base (without offset).
367 multiclass Loadxm_pat<PatFrag Load, ValueType VT, PatFrag ValueMod,
368 PatLeaf ImmPred, InstHexagon MI> {
369 def: Pat<(VT (Load AddrFI:$fi)),
370 (VT (ValueMod (MI AddrFI:$fi, 0)))>;
371 def: Pat<(VT (Load (add AddrFI:$fi, ImmPred:$Off))),
372 (VT (ValueMod (MI AddrFI:$fi, imm:$Off)))>;
373 def: Pat<(VT (Load (add IntRegs:$Rs, ImmPred:$Off))),
374 (VT (ValueMod (MI IntRegs:$Rs, imm:$Off)))>;
375 def: Pat<(VT (Load (i32 IntRegs:$Rs))),
376 (VT (ValueMod (MI IntRegs:$Rs, 0)))>;
379 defm: Loadxm_pat<extloadi1, i64, Zext64, s32_0ImmPred, L2_loadrub_io>;
380 defm: Loadxm_pat<extloadi8, i64, Zext64, s32_0ImmPred, L2_loadrub_io>;
381 defm: Loadxm_pat<extloadi16, i64, Zext64, s31_1ImmPred, L2_loadruh_io>;
382 defm: Loadxm_pat<zextloadi1, i64, Zext64, s32_0ImmPred, L2_loadrub_io>;
383 defm: Loadxm_pat<zextloadi8, i64, Zext64, s32_0ImmPred, L2_loadrub_io>;
384 defm: Loadxm_pat<zextloadi16, i64, Zext64, s31_1ImmPred, L2_loadruh_io>;
385 defm: Loadxm_pat<sextloadi8, i64, Sext64, s32_0ImmPred, L2_loadrb_io>;
386 defm: Loadxm_pat<sextloadi16, i64, Sext64, s31_1ImmPred, L2_loadrh_io>;
388 // Map Rdd = anyext(Rs) -> Rdd = combine(#0, Rs).
389 def: Pat<(i64 (anyext (i32 IntRegs:$src1))), (Zext64 IntRegs:$src1)>;
391 //===----------------------------------------------------------------------===//
392 // Template class for load instructions with Absolute set addressing mode.
393 //===----------------------------------------------------------------------===//
394 let isExtended = 1, opExtendable = 2, opExtentBits = 6, addrMode = AbsoluteSet,
395 hasSideEffects = 0 in
396 class T_LD_abs_set<string mnemonic, RegisterClass RC, bits<4>MajOp>:
397 LDInst<(outs RC:$dst1, IntRegs:$dst2),
399 "$dst1 = "#mnemonic#"($dst2 = #$addr)",
407 let Inst{27-25} = 0b101;
408 let Inst{24-21} = MajOp;
409 let Inst{13-12} = 0b01;
410 let Inst{4-0} = dst1;
411 let Inst{20-16} = dst2;
412 let Inst{11-8} = addr{5-2};
413 let Inst{6-5} = addr{1-0};
416 let accessSize = ByteAccess, hasNewValue = 1 in {
417 def L4_loadrb_ap : T_LD_abs_set <"memb", IntRegs, 0b1000>;
418 def L4_loadrub_ap : T_LD_abs_set <"memub", IntRegs, 0b1001>;
421 let accessSize = HalfWordAccess, hasNewValue = 1 in {
422 def L4_loadrh_ap : T_LD_abs_set <"memh", IntRegs, 0b1010>;
423 def L4_loadruh_ap : T_LD_abs_set <"memuh", IntRegs, 0b1011>;
424 def L4_loadbsw2_ap : T_LD_abs_set <"membh", IntRegs, 0b0001>;
425 def L4_loadbzw2_ap : T_LD_abs_set <"memubh", IntRegs, 0b0011>;
428 let accessSize = WordAccess, hasNewValue = 1 in
429 def L4_loadri_ap : T_LD_abs_set <"memw", IntRegs, 0b1100>;
431 let accessSize = WordAccess in {
432 def L4_loadbzw4_ap : T_LD_abs_set <"memubh", DoubleRegs, 0b0101>;
433 def L4_loadbsw4_ap : T_LD_abs_set <"membh", DoubleRegs, 0b0111>;
436 let accessSize = DoubleWordAccess in
437 def L4_loadrd_ap : T_LD_abs_set <"memd", DoubleRegs, 0b1110>;
439 let accessSize = ByteAccess in
440 def L4_loadalignb_ap : T_LD_abs_set <"memb_fifo", DoubleRegs, 0b0100>;
442 let accessSize = HalfWordAccess in
443 def L4_loadalignh_ap : T_LD_abs_set <"memh_fifo", DoubleRegs, 0b0010>;
445 // Load - Indirect with long offset
446 let InputType = "imm", addrMode = BaseLongOffset, isExtended = 1,
447 opExtentBits = 6, opExtendable = 3 in
448 class T_LoadAbsReg <string mnemonic, string CextOp, RegisterClass RC,
450 : LDInst <(outs RC:$dst), (ins IntRegs:$src1, u2Imm:$src2, u6Ext:$src3),
451 "$dst = "#mnemonic#"($src1<<#$src2 + #$src3)",
457 let CextOpcode = CextOp;
458 let hasNewValue = !if (!eq(!cast<string>(RC), "DoubleRegs"), 0, 1);
461 let Inst{27-25} = 0b110;
462 let Inst{24-21} = MajOp;
463 let Inst{20-16} = src1;
464 let Inst{13} = src2{1};
466 let Inst{11-8} = src3{5-2};
467 let Inst{7} = src2{0};
468 let Inst{6-5} = src3{1-0};
472 let accessSize = ByteAccess in {
473 def L4_loadrb_ur : T_LoadAbsReg<"memb", "LDrib", IntRegs, 0b1000>;
474 def L4_loadrub_ur : T_LoadAbsReg<"memub", "LDriub", IntRegs, 0b1001>;
475 def L4_loadalignb_ur : T_LoadAbsReg<"memb_fifo", "LDrib_fifo",
479 let accessSize = HalfWordAccess in {
480 def L4_loadrh_ur : T_LoadAbsReg<"memh", "LDrih", IntRegs, 0b1010>;
481 def L4_loadruh_ur : T_LoadAbsReg<"memuh", "LDriuh", IntRegs, 0b1011>;
482 def L4_loadbsw2_ur : T_LoadAbsReg<"membh", "LDribh2", IntRegs, 0b0001>;
483 def L4_loadbzw2_ur : T_LoadAbsReg<"memubh", "LDriubh2", IntRegs, 0b0011>;
484 def L4_loadalignh_ur : T_LoadAbsReg<"memh_fifo", "LDrih_fifo",
488 let accessSize = WordAccess in {
489 def L4_loadri_ur : T_LoadAbsReg<"memw", "LDriw", IntRegs, 0b1100>;
490 def L4_loadbsw4_ur : T_LoadAbsReg<"membh", "LDribh4", DoubleRegs, 0b0111>;
491 def L4_loadbzw4_ur : T_LoadAbsReg<"memubh", "LDriubh4", DoubleRegs, 0b0101>;
494 let accessSize = DoubleWordAccess in
495 def L4_loadrd_ur : T_LoadAbsReg<"memd", "LDrid", DoubleRegs, 0b1110>;
498 multiclass T_LoadAbsReg_Pat <PatFrag ldOp, InstHexagon MI, ValueType VT = i32> {
499 def : Pat <(VT (ldOp (add (shl IntRegs:$src1, u2ImmPred:$src2),
500 (HexagonCONST32 tglobaladdr:$src3)))),
501 (MI IntRegs:$src1, u2ImmPred:$src2, tglobaladdr:$src3)>;
502 def : Pat <(VT (ldOp (add IntRegs:$src1,
503 (HexagonCONST32 tglobaladdr:$src2)))),
504 (MI IntRegs:$src1, 0, tglobaladdr:$src2)>;
506 def : Pat <(VT (ldOp (add (shl IntRegs:$src1, u2ImmPred:$src2),
507 (HexagonCONST32 tconstpool:$src3)))),
508 (MI IntRegs:$src1, u2ImmPred:$src2, tconstpool:$src3)>;
509 def : Pat <(VT (ldOp (add IntRegs:$src1,
510 (HexagonCONST32 tconstpool:$src2)))),
511 (MI IntRegs:$src1, 0, tconstpool:$src2)>;
513 def : Pat <(VT (ldOp (add (shl IntRegs:$src1, u2ImmPred:$src2),
514 (HexagonCONST32 tjumptable:$src3)))),
515 (MI IntRegs:$src1, u2ImmPred:$src2, tjumptable:$src3)>;
516 def : Pat <(VT (ldOp (add IntRegs:$src1,
517 (HexagonCONST32 tjumptable:$src2)))),
518 (MI IntRegs:$src1, 0, tjumptable:$src2)>;
521 let AddedComplexity = 60 in {
522 defm : T_LoadAbsReg_Pat <sextloadi8, L4_loadrb_ur>;
523 defm : T_LoadAbsReg_Pat <zextloadi8, L4_loadrub_ur>;
524 defm : T_LoadAbsReg_Pat <extloadi8, L4_loadrub_ur>;
526 defm : T_LoadAbsReg_Pat <sextloadi16, L4_loadrh_ur>;
527 defm : T_LoadAbsReg_Pat <zextloadi16, L4_loadruh_ur>;
528 defm : T_LoadAbsReg_Pat <extloadi16, L4_loadruh_ur>;
530 defm : T_LoadAbsReg_Pat <load, L4_loadri_ur>;
531 defm : T_LoadAbsReg_Pat <load, L4_loadrd_ur, i64>;
534 //===----------------------------------------------------------------------===//
535 // Template classes for the non-predicated load instructions with
536 // base + register offset addressing mode
537 //===----------------------------------------------------------------------===//
538 class T_load_rr <string mnemonic, RegisterClass RC, bits<3> MajOp>:
539 LDInst<(outs RC:$dst), (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$u2),
540 "$dst = "#mnemonic#"($src1 + $src2<<#$u2)",
541 [], "", V4LDST_tc_ld_SLOT01>, ImmRegShl, AddrModeRel {
549 let Inst{27-24} = 0b1010;
550 let Inst{23-21} = MajOp;
551 let Inst{20-16} = src1;
552 let Inst{12-8} = src2;
553 let Inst{13} = u2{1};
558 //===----------------------------------------------------------------------===//
559 // Template classes for the predicated load instructions with
560 // base + register offset addressing mode
561 //===----------------------------------------------------------------------===//
562 let isPredicated = 1 in
563 class T_pload_rr <string mnemonic, RegisterClass RC, bits<3> MajOp,
564 bit isNot, bit isPredNew>:
565 LDInst <(outs RC:$dst),
566 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$u2),
567 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
568 ") ")#"$dst = "#mnemonic#"($src2+$src3<<#$u2)",
569 [], "", V4LDST_tc_ld_SLOT01>, AddrModeRel {
576 let isPredicatedFalse = isNot;
577 let isPredicatedNew = isPredNew;
581 let Inst{27-26} = 0b00;
582 let Inst{25} = isPredNew;
583 let Inst{24} = isNot;
584 let Inst{23-21} = MajOp;
585 let Inst{20-16} = src2;
586 let Inst{12-8} = src3;
587 let Inst{13} = u2{1};
589 let Inst{6-5} = src1;
593 //===----------------------------------------------------------------------===//
594 // multiclass for load instructions with base + register offset
596 //===----------------------------------------------------------------------===//
597 let hasSideEffects = 0, addrMode = BaseRegOffset in
598 multiclass ld_idxd_shl <string mnemonic, string CextOp, RegisterClass RC,
600 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed_shl,
601 InputType = "reg" in {
602 let isPredicable = 1 in
603 def L4_#NAME#_rr : T_load_rr <mnemonic, RC, MajOp>;
606 def L4_p#NAME#t_rr : T_pload_rr <mnemonic, RC, MajOp, 0, 0>;
607 def L4_p#NAME#f_rr : T_pload_rr <mnemonic, RC, MajOp, 1, 0>;
610 def L4_p#NAME#tnew_rr : T_pload_rr <mnemonic, RC, MajOp, 0, 1>;
611 def L4_p#NAME#fnew_rr : T_pload_rr <mnemonic, RC, MajOp, 1, 1>;
615 let hasNewValue = 1, accessSize = ByteAccess in {
616 defm loadrb : ld_idxd_shl<"memb", "LDrib", IntRegs, 0b000>;
617 defm loadrub : ld_idxd_shl<"memub", "LDriub", IntRegs, 0b001>;
620 let hasNewValue = 1, accessSize = HalfWordAccess in {
621 defm loadrh : ld_idxd_shl<"memh", "LDrih", IntRegs, 0b010>;
622 defm loadruh : ld_idxd_shl<"memuh", "LDriuh", IntRegs, 0b011>;
625 let hasNewValue = 1, accessSize = WordAccess in
626 defm loadri : ld_idxd_shl<"memw", "LDriw", IntRegs, 0b100>;
628 let accessSize = DoubleWordAccess in
629 defm loadrd : ld_idxd_shl<"memd", "LDrid", DoubleRegs, 0b110>;
631 // 'def pats' for load instructions with base + register offset and non-zero
632 // immediate value. Immediate value is used to left-shift the second
634 class Loadxs_pat<PatFrag Load, ValueType VT, InstHexagon MI>
635 : Pat<(VT (Load (add (i32 IntRegs:$Rs),
636 (i32 (shl (i32 IntRegs:$Rt), u2ImmPred:$u2))))),
637 (VT (MI IntRegs:$Rs, IntRegs:$Rt, imm:$u2))>;
639 let AddedComplexity = 40 in {
640 def: Loadxs_pat<extloadi8, i32, L4_loadrub_rr>;
641 def: Loadxs_pat<zextloadi8, i32, L4_loadrub_rr>;
642 def: Loadxs_pat<sextloadi8, i32, L4_loadrb_rr>;
643 def: Loadxs_pat<extloadi16, i32, L4_loadruh_rr>;
644 def: Loadxs_pat<zextloadi16, i32, L4_loadruh_rr>;
645 def: Loadxs_pat<sextloadi16, i32, L4_loadrh_rr>;
646 def: Loadxs_pat<load, i32, L4_loadri_rr>;
647 def: Loadxs_pat<load, i64, L4_loadrd_rr>;
650 // 'def pats' for load instruction base + register offset and
651 // zero immediate value.
652 class Loadxs_simple_pat<PatFrag Load, ValueType VT, InstHexagon MI>
653 : Pat<(VT (Load (add (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)))),
654 (VT (MI IntRegs:$Rs, IntRegs:$Rt, 0))>;
656 let AddedComplexity = 20 in {
657 def: Loadxs_simple_pat<extloadi8, i32, L4_loadrub_rr>;
658 def: Loadxs_simple_pat<zextloadi8, i32, L4_loadrub_rr>;
659 def: Loadxs_simple_pat<sextloadi8, i32, L4_loadrb_rr>;
660 def: Loadxs_simple_pat<extloadi16, i32, L4_loadruh_rr>;
661 def: Loadxs_simple_pat<zextloadi16, i32, L4_loadruh_rr>;
662 def: Loadxs_simple_pat<sextloadi16, i32, L4_loadrh_rr>;
663 def: Loadxs_simple_pat<load, i32, L4_loadri_rr>;
664 def: Loadxs_simple_pat<load, i64, L4_loadrd_rr>;
668 def: Pat<(i64 (zext (i1 PredRegs:$src1))),
669 (Zext64 (C2_muxii PredRegs:$src1, 1, 0))>;
672 def: Pat<(i64 (zext (i32 IntRegs:$src1))),
673 (Zext64 IntRegs:$src1)>;
675 //===----------------------------------------------------------------------===//
677 //===----------------------------------------------------------------------===//
679 //===----------------------------------------------------------------------===//
681 //===----------------------------------------------------------------------===//
683 //===----------------------------------------------------------------------===//
684 // Template class for store instructions with Absolute set addressing mode.
685 //===----------------------------------------------------------------------===//
686 let isExtended = 1, opExtendable = 1, opExtentBits = 6,
687 addrMode = AbsoluteSet, isNVStorable = 1 in
688 class T_ST_absset <string mnemonic, string BaseOp, RegisterClass RC,
689 bits<3> MajOp, MemAccessSize AccessSz, bit isHalf = 0>
690 : STInst<(outs IntRegs:$dst),
691 (ins u6Ext:$addr, RC:$src),
692 mnemonic#"($dst = #$addr) = $src"#!if(isHalf, ".h","")>, NewValueRel {
696 let accessSize = AccessSz;
697 let BaseOpcode = BaseOp#"_AbsSet";
701 let Inst{27-24} = 0b1011;
702 let Inst{23-21} = MajOp;
703 let Inst{20-16} = dst;
705 let Inst{12-8} = src;
707 let Inst{5-0} = addr;
710 def S4_storerb_ap : T_ST_absset <"memb", "STrib", IntRegs, 0b000, ByteAccess>;
711 def S4_storerh_ap : T_ST_absset <"memh", "STrih", IntRegs, 0b010,
713 def S4_storeri_ap : T_ST_absset <"memw", "STriw", IntRegs, 0b100, WordAccess>;
715 let isNVStorable = 0 in {
716 def S4_storerf_ap : T_ST_absset <"memh", "STrif", IntRegs,
717 0b011, HalfWordAccess, 1>;
718 def S4_storerd_ap : T_ST_absset <"memd", "STrid", DoubleRegs,
719 0b110, DoubleWordAccess>;
722 let opExtendable = 1, isNewValue = 1, isNVStore = 1, opNewValue = 2,
723 isExtended = 1, opExtentBits= 6 in
724 class T_ST_absset_nv <string mnemonic, string BaseOp, bits<2> MajOp,
725 MemAccessSize AccessSz >
726 : NVInst <(outs IntRegs:$dst),
727 (ins u6Ext:$addr, IntRegs:$src),
728 mnemonic#"($dst = #$addr) = $src.new">, NewValueRel {
732 let accessSize = AccessSz;
733 let BaseOpcode = BaseOp#"_AbsSet";
737 let Inst{27-21} = 0b1011101;
738 let Inst{20-16} = dst;
739 let Inst{13-11} = 0b000;
740 let Inst{12-11} = MajOp;
741 let Inst{10-8} = src;
743 let Inst{5-0} = addr;
746 let mayStore = 1, addrMode = AbsoluteSet in {
747 def S4_storerbnew_ap : T_ST_absset_nv <"memb", "STrib", 0b00, ByteAccess>;
748 def S4_storerhnew_ap : T_ST_absset_nv <"memh", "STrih", 0b01, HalfWordAccess>;
749 def S4_storerinew_ap : T_ST_absset_nv <"memw", "STriw", 0b10, WordAccess>;
752 let isExtended = 1, opExtendable = 2, opExtentBits = 6, InputType = "imm",
753 addrMode = BaseLongOffset, AddedComplexity = 40 in
754 class T_StoreAbsReg <string mnemonic, string CextOp, RegisterClass RC,
755 bits<3> MajOp, MemAccessSize AccessSz, bit isHalf = 0>
757 (ins IntRegs:$src1, u2Imm:$src2, u6Ext:$src3, RC:$src4),
758 mnemonic#"($src1<<#$src2 + #$src3) = $src4"#!if(isHalf, ".h",""),
759 []>, ImmRegShl, NewValueRel {
766 let accessSize = AccessSz;
767 let CextOpcode = CextOp;
768 let BaseOpcode = CextOp#"_shl";
771 let Inst{27-24} =0b1101;
772 let Inst{23-21} = MajOp;
773 let Inst{20-16} = src1;
774 let Inst{13} = src2{1};
775 let Inst{12-8} = src4;
777 let Inst{6} = src2{0};
778 let Inst{5-0} = src3;
781 def S4_storerb_ur : T_StoreAbsReg <"memb", "STrib", IntRegs, 0b000, ByteAccess>;
782 def S4_storerh_ur : T_StoreAbsReg <"memh", "STrih", IntRegs, 0b010,
784 def S4_storerf_ur : T_StoreAbsReg <"memh", "STrif", IntRegs, 0b011,
786 def S4_storeri_ur : T_StoreAbsReg <"memw", "STriw", IntRegs, 0b100, WordAccess>;
787 def S4_storerd_ur : T_StoreAbsReg <"memd", "STrid", DoubleRegs, 0b110,
790 let AddedComplexity = 40 in
791 multiclass T_StoreAbsReg_Pats <InstHexagon MI, RegisterClass RC, ValueType VT,
793 def : Pat<(stOp (VT RC:$src4),
794 (add (shl (i32 IntRegs:$src1), u2ImmPred:$src2),
796 (MI IntRegs:$src1, u2ImmPred:$src2, u32ImmPred:$src3, RC:$src4)>;
798 def : Pat<(stOp (VT RC:$src4),
799 (add (shl IntRegs:$src1, u2ImmPred:$src2),
800 (HexagonCONST32 tglobaladdr:$src3))),
801 (MI IntRegs:$src1, u2ImmPred:$src2, tglobaladdr:$src3, RC:$src4)>;
803 def : Pat<(stOp (VT RC:$src4),
804 (add IntRegs:$src1, (HexagonCONST32 tglobaladdr:$src3))),
805 (MI IntRegs:$src1, 0, tglobaladdr:$src3, RC:$src4)>;
808 defm : T_StoreAbsReg_Pats <S4_storerd_ur, DoubleRegs, i64, store>;
809 defm : T_StoreAbsReg_Pats <S4_storeri_ur, IntRegs, i32, store>;
810 defm : T_StoreAbsReg_Pats <S4_storerb_ur, IntRegs, i32, truncstorei8>;
811 defm : T_StoreAbsReg_Pats <S4_storerh_ur, IntRegs, i32, truncstorei16>;
813 let mayStore = 1, isNVStore = 1, isExtended = 1, addrMode = BaseLongOffset,
814 opExtentBits = 6, isNewValue = 1, opNewValue = 3, opExtendable = 2 in
815 class T_StoreAbsRegNV <string mnemonic, string CextOp, bits<2> MajOp,
816 MemAccessSize AccessSz>
818 (ins IntRegs:$src1, u2Imm:$src2, u6Ext:$src3, IntRegs:$src4),
819 mnemonic#"($src1<<#$src2 + #$src3) = $src4.new">, NewValueRel {
825 let CextOpcode = CextOp;
826 let BaseOpcode = CextOp#"_shl";
829 let Inst{27-21} = 0b1101101;
830 let Inst{12-11} = 0b00;
832 let Inst{20-16} = src1;
833 let Inst{13} = src2{1};
834 let Inst{12-11} = MajOp;
835 let Inst{10-8} = src4;
836 let Inst{6} = src2{0};
837 let Inst{5-0} = src3;
840 def S4_storerbnew_ur : T_StoreAbsRegNV <"memb", "STrib", 0b00, ByteAccess>;
841 def S4_storerhnew_ur : T_StoreAbsRegNV <"memh", "STrih", 0b01, HalfWordAccess>;
842 def S4_storerinew_ur : T_StoreAbsRegNV <"memw", "STriw", 0b10, WordAccess>;
844 //===----------------------------------------------------------------------===//
845 // Template classes for the non-predicated store instructions with
846 // base + register offset addressing mode
847 //===----------------------------------------------------------------------===//
848 let isPredicable = 1 in
849 class T_store_rr <string mnemonic, RegisterClass RC, bits<3> MajOp, bit isH>
850 : STInst < (outs ), (ins IntRegs:$Rs, IntRegs:$Ru, u2Imm:$u2, RC:$Rt),
851 mnemonic#"($Rs + $Ru<<#$u2) = $Rt"#!if(isH, ".h",""),
852 [],"",V4LDST_tc_st_SLOT01>, ImmRegShl, AddrModeRel {
861 let Inst{27-24} = 0b1011;
862 let Inst{23-21} = MajOp;
863 let Inst{20-16} = Rs;
865 let Inst{13} = u2{1};
870 //===----------------------------------------------------------------------===//
871 // Template classes for the predicated store instructions with
872 // base + register offset addressing mode
873 //===----------------------------------------------------------------------===//
874 let isPredicated = 1 in
875 class T_pstore_rr <string mnemonic, RegisterClass RC, bits<3> MajOp,
876 bit isNot, bit isPredNew, bit isH>
878 (ins PredRegs:$Pv, IntRegs:$Rs, IntRegs:$Ru, u2Imm:$u2, RC:$Rt),
880 !if(isNot, "if (!$Pv", "if ($Pv")#!if(isPredNew, ".new) ",
881 ") ")#mnemonic#"($Rs+$Ru<<#$u2) = $Rt"#!if(isH, ".h",""),
882 [], "", V4LDST_tc_st_SLOT01> , AddrModeRel{
889 let isPredicatedFalse = isNot;
890 let isPredicatedNew = isPredNew;
894 let Inst{27-26} = 0b01;
895 let Inst{25} = isPredNew;
896 let Inst{24} = isNot;
897 let Inst{23-21} = MajOp;
898 let Inst{20-16} = Rs;
900 let Inst{13} = u2{1};
906 //===----------------------------------------------------------------------===//
907 // Template classes for the new-value store instructions with
908 // base + register offset addressing mode
909 //===----------------------------------------------------------------------===//
910 let isPredicable = 1, isNewValue = 1, opNewValue = 3 in
911 class T_store_new_rr <string mnemonic, bits<2> MajOp> :
912 NVInst < (outs ), (ins IntRegs:$Rs, IntRegs:$Ru, u2Imm:$u2, IntRegs:$Nt),
913 mnemonic#"($Rs + $Ru<<#$u2) = $Nt.new",
914 [],"",V4LDST_tc_st_SLOT0>, ImmRegShl, AddrModeRel {
923 let Inst{27-21} = 0b1011101;
924 let Inst{20-16} = Rs;
926 let Inst{13} = u2{1};
928 let Inst{4-3} = MajOp;
932 //===----------------------------------------------------------------------===//
933 // Template classes for the predicated new-value store instructions with
934 // base + register offset addressing mode
935 //===----------------------------------------------------------------------===//
936 let isPredicated = 1, isNewValue = 1, opNewValue = 4 in
937 class T_pstore_new_rr <string mnemonic, bits<2> MajOp, bit isNot, bit isPredNew>
939 (ins PredRegs:$Pv, IntRegs:$Rs, IntRegs:$Ru, u2Imm:$u2, IntRegs:$Nt),
940 !if(isNot, "if (!$Pv", "if ($Pv")#!if(isPredNew, ".new) ",
941 ") ")#mnemonic#"($Rs+$Ru<<#$u2) = $Nt.new",
942 [], "", V4LDST_tc_st_SLOT0>, AddrModeRel {
949 let isPredicatedFalse = isNot;
950 let isPredicatedNew = isPredNew;
953 let Inst{27-26} = 0b01;
954 let Inst{25} = isPredNew;
955 let Inst{24} = isNot;
956 let Inst{23-21} = 0b101;
957 let Inst{20-16} = Rs;
959 let Inst{13} = u2{1};
962 let Inst{4-3} = MajOp;
966 //===----------------------------------------------------------------------===//
967 // multiclass for store instructions with base + register offset addressing
969 //===----------------------------------------------------------------------===//
970 let isNVStorable = 1 in
971 multiclass ST_Idxd_shl<string mnemonic, string CextOp, RegisterClass RC,
972 bits<3> MajOp, bit isH = 0> {
973 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed_shl in {
974 def S4_#NAME#_rr : T_store_rr <mnemonic, RC, MajOp, isH>;
977 def S4_p#NAME#t_rr : T_pstore_rr <mnemonic, RC, MajOp, 0, 0, isH>;
978 def S4_p#NAME#f_rr : T_pstore_rr <mnemonic, RC, MajOp, 1, 0, isH>;
981 def S4_p#NAME#tnew_rr : T_pstore_rr <mnemonic, RC, MajOp, 0, 1, isH>;
982 def S4_p#NAME#fnew_rr : T_pstore_rr <mnemonic, RC, MajOp, 1, 1, isH>;
986 //===----------------------------------------------------------------------===//
987 // multiclass for new-value store instructions with base + register offset
989 //===----------------------------------------------------------------------===//
990 let mayStore = 1, isNVStore = 1 in
991 multiclass ST_Idxd_shl_nv <string mnemonic, string CextOp, RegisterClass RC,
993 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed_shl in {
994 def S4_#NAME#new_rr : T_store_new_rr<mnemonic, MajOp>;
997 def S4_p#NAME#newt_rr : T_pstore_new_rr <mnemonic, MajOp, 0, 0>;
998 def S4_p#NAME#newf_rr : T_pstore_new_rr <mnemonic, MajOp, 1, 0>;
1001 def S4_p#NAME#newtnew_rr : T_pstore_new_rr <mnemonic, MajOp, 0, 1>;
1002 def S4_p#NAME#newfnew_rr : T_pstore_new_rr <mnemonic, MajOp, 1, 1>;
1006 let addrMode = BaseRegOffset, InputType = "reg", hasSideEffects = 0 in {
1007 let accessSize = ByteAccess in
1008 defm storerb: ST_Idxd_shl<"memb", "STrib", IntRegs, 0b000>,
1009 ST_Idxd_shl_nv<"memb", "STrib", IntRegs, 0b00>;
1011 let accessSize = HalfWordAccess in
1012 defm storerh: ST_Idxd_shl<"memh", "STrih", IntRegs, 0b010>,
1013 ST_Idxd_shl_nv<"memh", "STrih", IntRegs, 0b01>;
1015 let accessSize = WordAccess in
1016 defm storeri: ST_Idxd_shl<"memw", "STriw", IntRegs, 0b100>,
1017 ST_Idxd_shl_nv<"memw", "STriw", IntRegs, 0b10>;
1019 let isNVStorable = 0, accessSize = DoubleWordAccess in
1020 defm storerd: ST_Idxd_shl<"memd", "STrid", DoubleRegs, 0b110>;
1022 let isNVStorable = 0, accessSize = HalfWordAccess in
1023 defm storerf: ST_Idxd_shl<"memh", "STrif", IntRegs, 0b011, 1>;
1026 class Storexs_pat<PatFrag Store, PatFrag Value, InstHexagon MI>
1027 : Pat<(Store Value:$Ru, (add (i32 IntRegs:$Rs),
1028 (i32 (shl (i32 IntRegs:$Rt), u2ImmPred:$u2)))),
1029 (MI IntRegs:$Rs, IntRegs:$Rt, imm:$u2, Value:$Ru)>;
1031 let AddedComplexity = 40 in {
1032 def: Storexs_pat<truncstorei8, I32, S4_storerb_rr>;
1033 def: Storexs_pat<truncstorei16, I32, S4_storerh_rr>;
1034 def: Storexs_pat<store, I32, S4_storeri_rr>;
1035 def: Storexs_pat<store, I64, S4_storerd_rr>;
1038 // memd(Rx++#s4:3)=Rtt
1039 // memd(Rx++#s4:3:circ(Mu))=Rtt
1040 // memd(Rx++I:circ(Mu))=Rtt
1042 // memd(Rx++Mu:brev)=Rtt
1043 // memd(gp+#u16:3)=Rtt
1045 // Store doubleword conditionally.
1046 // if ([!]Pv[.new]) memd(#u6)=Rtt
1047 // TODO: needs to be implemented.
1049 //===----------------------------------------------------------------------===//
1051 //===----------------------------------------------------------------------===//
1052 let isPredicable = 1, isExtendable = 1, isExtentSigned = 1, opExtentBits = 8,
1054 class T_StoreImm <string mnemonic, Operand OffsetOp, bits<2> MajOp >
1055 : STInst <(outs ), (ins IntRegs:$Rs, OffsetOp:$offset, s8Ext:$S8),
1056 mnemonic#"($Rs+#$offset)=#$S8",
1057 [], "", V4LDST_tc_st_SLOT01>,
1058 ImmRegRel, PredNewRel {
1064 string OffsetOpStr = !cast<string>(OffsetOp);
1065 let offsetBits = !if (!eq(OffsetOpStr, "u6_2Imm"), offset{7-2},
1066 !if (!eq(OffsetOpStr, "u6_1Imm"), offset{6-1},
1067 /* u6_0Imm */ offset{5-0}));
1069 let IClass = 0b0011;
1071 let Inst{27-25} = 0b110;
1072 let Inst{22-21} = MajOp;
1073 let Inst{20-16} = Rs;
1074 let Inst{12-7} = offsetBits;
1075 let Inst{13} = S8{7};
1076 let Inst{6-0} = S8{6-0};
1079 let isPredicated = 1, isExtendable = 1, isExtentSigned = 1, opExtentBits = 6,
1081 class T_StoreImm_pred <string mnemonic, Operand OffsetOp, bits<2> MajOp,
1082 bit isPredNot, bit isPredNew >
1084 (ins PredRegs:$Pv, IntRegs:$Rs, OffsetOp:$offset, s6Ext:$S6),
1085 !if(isPredNot, "if (!$Pv", "if ($Pv")#!if(isPredNew, ".new) ",
1086 ") ")#mnemonic#"($Rs+#$offset)=#$S6",
1087 [], "", V4LDST_tc_st_SLOT01>,
1088 ImmRegRel, PredNewRel {
1095 string OffsetOpStr = !cast<string>(OffsetOp);
1096 let offsetBits = !if (!eq(OffsetOpStr, "u6_2Imm"), offset{7-2},
1097 !if (!eq(OffsetOpStr, "u6_1Imm"), offset{6-1},
1098 /* u6_0Imm */ offset{5-0}));
1099 let isPredicatedNew = isPredNew;
1100 let isPredicatedFalse = isPredNot;
1102 let IClass = 0b0011;
1104 let Inst{27-25} = 0b100;
1105 let Inst{24} = isPredNew;
1106 let Inst{23} = isPredNot;
1107 let Inst{22-21} = MajOp;
1108 let Inst{20-16} = Rs;
1109 let Inst{13} = S6{5};
1110 let Inst{12-7} = offsetBits;
1112 let Inst{4-0} = S6{4-0};
1116 //===----------------------------------------------------------------------===//
1117 // multiclass for store instructions with base + immediate offset
1118 // addressing mode and immediate stored value.
1119 // mem[bhw](Rx++#s4:3)=#s8
1120 // if ([!]Pv[.new]) mem[bhw](Rx++#s4:3)=#s6
1121 //===----------------------------------------------------------------------===//
1123 multiclass ST_Imm_Pred <string mnemonic, Operand OffsetOp, bits<2> MajOp,
1125 def _io : T_StoreImm_pred <mnemonic, OffsetOp, MajOp, PredNot, 0>;
1127 def new_io : T_StoreImm_pred <mnemonic, OffsetOp, MajOp, PredNot, 1>;
1130 multiclass ST_Imm <string mnemonic, string CextOp, Operand OffsetOp,
1132 let CextOpcode = CextOp, BaseOpcode = CextOp#_imm in {
1133 def _io : T_StoreImm <mnemonic, OffsetOp, MajOp>;
1135 defm t : ST_Imm_Pred <mnemonic, OffsetOp, MajOp, 0>;
1136 defm f : ST_Imm_Pred <mnemonic, OffsetOp, MajOp, 1>;
1140 let hasSideEffects = 0, addrMode = BaseImmOffset,
1141 InputType = "imm" in {
1142 let accessSize = ByteAccess in
1143 defm S4_storeirb : ST_Imm<"memb", "STrib", u6_0Imm, 0b00>;
1145 let accessSize = HalfWordAccess in
1146 defm S4_storeirh : ST_Imm<"memh", "STrih", u6_1Imm, 0b01>;
1148 let accessSize = WordAccess in
1149 defm S4_storeiri : ST_Imm<"memw", "STriw", u6_2Imm, 0b10>;
1152 def IMM_BYTE : SDNodeXForm<imm, [{
1153 // -1 etc is represented as 255 etc
1154 // assigning to a byte restores our desired signed value.
1155 int8_t imm = N->getSExtValue();
1156 return CurDAG->getTargetConstant(imm, MVT::i32);
1159 def IMM_HALF : SDNodeXForm<imm, [{
1160 // -1 etc is represented as 65535 etc
1161 // assigning to a short restores our desired signed value.
1162 int16_t imm = N->getSExtValue();
1163 return CurDAG->getTargetConstant(imm, MVT::i32);
1166 def IMM_WORD : SDNodeXForm<imm, [{
1167 // -1 etc can be represented as 4294967295 etc
1168 // Currently, it's not doing this. But some optimization
1169 // might convert -1 to a large +ve number.
1170 // assigning to a word restores our desired signed value.
1171 int32_t imm = N->getSExtValue();
1172 return CurDAG->getTargetConstant(imm, MVT::i32);
1175 def ToImmByte : OutPatFrag<(ops node:$R), (IMM_BYTE $R)>;
1176 def ToImmHalf : OutPatFrag<(ops node:$R), (IMM_HALF $R)>;
1177 def ToImmWord : OutPatFrag<(ops node:$R), (IMM_WORD $R)>;
1179 let AddedComplexity = 40 in {
1180 // Not using frameindex patterns for these stores, because the offset
1181 // is not extendable. This could cause problems during removing the frame
1182 // indices, since the offset with respect to R29/R30 may not fit in the
1184 def: Storexm_add_pat<truncstorei8, s32ImmPred, u6_0ImmPred, ToImmByte,
1186 def: Storexm_add_pat<truncstorei16, s32ImmPred, u6_1ImmPred, ToImmHalf,
1188 def: Storexm_add_pat<store, s32ImmPred, u6_2ImmPred, ToImmWord,
1192 def: Storexm_simple_pat<truncstorei8, s32ImmPred, ToImmByte, S4_storeirb_io>;
1193 def: Storexm_simple_pat<truncstorei16, s32ImmPred, ToImmHalf, S4_storeirh_io>;
1194 def: Storexm_simple_pat<store, s32ImmPred, ToImmWord, S4_storeiri_io>;
1196 // memb(Rx++#s4:0:circ(Mu))=Rt
1197 // memb(Rx++I:circ(Mu))=Rt
1199 // memb(Rx++Mu:brev)=Rt
1200 // memb(gp+#u16:0)=Rt
1203 // TODO: needs to be implemented
1204 // memh(Re=#U6)=Rt.H
1205 // memh(Rs+#s11:1)=Rt.H
1206 // memh(Rs+Ru<<#u2)=Rt.H
1207 // TODO: needs to be implemented.
1209 // memh(Ru<<#u2+#U6)=Rt.H
1210 // memh(Rx++#s4:1:circ(Mu))=Rt.H
1211 // memh(Rx++#s4:1:circ(Mu))=Rt
1212 // memh(Rx++I:circ(Mu))=Rt.H
1213 // memh(Rx++I:circ(Mu))=Rt
1214 // memh(Rx++Mu)=Rt.H
1216 // memh(Rx++Mu:brev)=Rt.H
1217 // memh(Rx++Mu:brev)=Rt
1218 // memh(gp+#u16:1)=Rt
1219 // if ([!]Pv[.new]) memh(#u6)=Rt.H
1220 // if ([!]Pv[.new]) memh(#u6)=Rt
1222 // if ([!]Pv[.new]) memh(Rs+#u6:1)=Rt.H
1223 // TODO: needs to be implemented.
1225 // if ([!]Pv[.new]) memh(Rx++#s4:1)=Rt.H
1226 // TODO: Needs to be implemented.
1230 // TODO: Needs to be implemented.
1231 // memw(Rx++#s4:2)=Rt
1232 // memw(Rx++#s4:2:circ(Mu))=Rt
1233 // memw(Rx++I:circ(Mu))=Rt
1235 // memw(Rx++Mu:brev)=Rt
1237 //===----------------------------------------------------------------------===
1239 //===----------------------------------------------------------------------===
1242 //===----------------------------------------------------------------------===//
1244 //===----------------------------------------------------------------------===//
1246 let opNewValue = 2, opExtendable = 1, isExtentSigned = 1, isPredicable = 1 in
1247 class T_store_io_nv <string mnemonic, RegisterClass RC,
1248 Operand ImmOp, bits<2>MajOp>
1249 : NVInst_V4 <(outs),
1250 (ins IntRegs:$src1, ImmOp:$src2, RC:$src3),
1251 mnemonic#"($src1+#$src2) = $src3.new",
1252 [],"",ST_tc_st_SLOT0> {
1254 bits<13> src2; // Actual address offset
1256 bits<11> offsetBits; // Represents offset encoding
1258 let opExtentBits = !if (!eq(mnemonic, "memb"), 11,
1259 !if (!eq(mnemonic, "memh"), 12,
1260 !if (!eq(mnemonic, "memw"), 13, 0)));
1262 let opExtentAlign = !if (!eq(mnemonic, "memb"), 0,
1263 !if (!eq(mnemonic, "memh"), 1,
1264 !if (!eq(mnemonic, "memw"), 2, 0)));
1266 let offsetBits = !if (!eq(mnemonic, "memb"), src2{10-0},
1267 !if (!eq(mnemonic, "memh"), src2{11-1},
1268 !if (!eq(mnemonic, "memw"), src2{12-2}, 0)));
1270 let IClass = 0b1010;
1273 let Inst{26-25} = offsetBits{10-9};
1274 let Inst{24-21} = 0b1101;
1275 let Inst{20-16} = src1;
1276 let Inst{13} = offsetBits{8};
1277 let Inst{12-11} = MajOp;
1278 let Inst{10-8} = src3;
1279 let Inst{7-0} = offsetBits{7-0};
1282 let opExtendable = 2, opNewValue = 3, isPredicated = 1 in
1283 class T_pstore_io_nv <string mnemonic, RegisterClass RC, Operand predImmOp,
1284 bits<2>MajOp, bit PredNot, bit isPredNew>
1285 : NVInst_V4 <(outs),
1286 (ins PredRegs:$src1, IntRegs:$src2, predImmOp:$src3, RC:$src4),
1287 !if(PredNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1288 ") ")#mnemonic#"($src2+#$src3) = $src4.new",
1289 [],"",V2LDST_tc_st_SLOT0> {
1294 bits<6> offsetBits; // Represents offset encoding
1296 let isPredicatedNew = isPredNew;
1297 let isPredicatedFalse = PredNot;
1298 let opExtentBits = !if (!eq(mnemonic, "memb"), 6,
1299 !if (!eq(mnemonic, "memh"), 7,
1300 !if (!eq(mnemonic, "memw"), 8, 0)));
1302 let opExtentAlign = !if (!eq(mnemonic, "memb"), 0,
1303 !if (!eq(mnemonic, "memh"), 1,
1304 !if (!eq(mnemonic, "memw"), 2, 0)));
1306 let offsetBits = !if (!eq(mnemonic, "memb"), src3{5-0},
1307 !if (!eq(mnemonic, "memh"), src3{6-1},
1308 !if (!eq(mnemonic, "memw"), src3{7-2}, 0)));
1310 let IClass = 0b0100;
1313 let Inst{26} = PredNot;
1314 let Inst{25} = isPredNew;
1315 let Inst{24-21} = 0b0101;
1316 let Inst{20-16} = src2;
1317 let Inst{13} = offsetBits{5};
1318 let Inst{12-11} = MajOp;
1319 let Inst{10-8} = src4;
1320 let Inst{7-3} = offsetBits{4-0};
1322 let Inst{1-0} = src1;
1325 // multiclass for new-value store instructions with base + immediate offset.
1327 let mayStore = 1, isNVStore = 1, isNewValue = 1, hasSideEffects = 0,
1329 multiclass ST_Idxd_nv<string mnemonic, string CextOp, RegisterClass RC,
1330 Operand ImmOp, Operand predImmOp, bits<2> MajOp> {
1332 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed in {
1333 def S2_#NAME#new_io : T_store_io_nv <mnemonic, RC, ImmOp, MajOp>;
1335 def S2_p#NAME#newt_io :T_pstore_io_nv <mnemonic, RC, predImmOp, MajOp, 0, 0>;
1336 def S2_p#NAME#newf_io :T_pstore_io_nv <mnemonic, RC, predImmOp, MajOp, 1, 0>;
1338 def S4_p#NAME#newtnew_io :T_pstore_io_nv <mnemonic, RC, predImmOp,
1340 def S4_p#NAME#newfnew_io :T_pstore_io_nv <mnemonic, RC, predImmOp,
1345 let addrMode = BaseImmOffset, InputType = "imm" in {
1346 let accessSize = ByteAccess in
1347 defm storerb: ST_Idxd_nv<"memb", "STrib", IntRegs, s11_0Ext,
1348 u6_0Ext, 0b00>, AddrModeRel;
1350 let accessSize = HalfWordAccess, opExtentAlign = 1 in
1351 defm storerh: ST_Idxd_nv<"memh", "STrih", IntRegs, s11_1Ext,
1352 u6_1Ext, 0b01>, AddrModeRel;
1354 let accessSize = WordAccess, opExtentAlign = 2 in
1355 defm storeri: ST_Idxd_nv<"memw", "STriw", IntRegs, s11_2Ext,
1356 u6_2Ext, 0b10>, AddrModeRel;
1359 //===----------------------------------------------------------------------===//
1360 // Post increment loads with register offset.
1361 //===----------------------------------------------------------------------===//
1363 let hasNewValue = 1 in
1364 def L2_loadbsw2_pr : T_load_pr <"membh", IntRegs, 0b0001, HalfWordAccess>;
1366 def L2_loadbsw4_pr : T_load_pr <"membh", DoubleRegs, 0b0111, WordAccess>;
1368 let hasSideEffects = 0, addrMode = PostInc in
1369 class T_loadalign_pr <string mnemonic, bits<4> MajOp, MemAccessSize AccessSz>
1370 : LDInstPI <(outs DoubleRegs:$dst, IntRegs:$_dst_),
1371 (ins DoubleRegs:$src1, IntRegs:$src2, ModRegs:$src3),
1372 "$dst = "#mnemonic#"($src2++$src3)", [],
1373 "$src1 = $dst, $src2 = $_dst_"> {
1378 let accessSize = AccessSz;
1379 let IClass = 0b1001;
1381 let Inst{27-25} = 0b110;
1382 let Inst{24-21} = MajOp;
1383 let Inst{20-16} = src2;
1384 let Inst{13} = src3;
1387 let Inst{4-0} = dst;
1390 def L2_loadalignb_pr : T_loadalign_pr <"memb_fifo", 0b0100, ByteAccess>;
1391 def L2_loadalignh_pr : T_loadalign_pr <"memh_fifo", 0b0010, HalfWordAccess>;
1393 //===----------------------------------------------------------------------===//
1394 // Template class for non-predicated post increment .new stores
1395 // mem[bhwd](Rx++#s4:[0123])=Nt.new
1396 //===----------------------------------------------------------------------===//
1397 let isPredicable = 1, hasSideEffects = 0, addrMode = PostInc, isNVStore = 1,
1398 isNewValue = 1, opNewValue = 3 in
1399 class T_StorePI_nv <string mnemonic, Operand ImmOp, bits<2> MajOp >
1400 : NVInstPI_V4 <(outs IntRegs:$_dst_),
1401 (ins IntRegs:$src1, ImmOp:$offset, IntRegs:$src2),
1402 mnemonic#"($src1++#$offset) = $src2.new",
1403 [], "$src1 = $_dst_">,
1410 string ImmOpStr = !cast<string>(ImmOp);
1411 let offsetBits = !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2},
1412 !if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1},
1413 /* s4_0Imm */ offset{3-0}));
1414 let IClass = 0b1010;
1416 let Inst{27-21} = 0b1011101;
1417 let Inst{20-16} = src1;
1419 let Inst{12-11} = MajOp;
1420 let Inst{10-8} = src2;
1422 let Inst{6-3} = offsetBits;
1426 //===----------------------------------------------------------------------===//
1427 // Template class for predicated post increment .new stores
1428 // if([!]Pv[.new]) mem[bhwd](Rx++#s4:[0123])=Nt.new
1429 //===----------------------------------------------------------------------===//
1430 let isPredicated = 1, hasSideEffects = 0, addrMode = PostInc, isNVStore = 1,
1431 isNewValue = 1, opNewValue = 4 in
1432 class T_StorePI_nv_pred <string mnemonic, Operand ImmOp,
1433 bits<2> MajOp, bit isPredNot, bit isPredNew >
1434 : NVInstPI_V4 <(outs IntRegs:$_dst_),
1435 (ins PredRegs:$src1, IntRegs:$src2,
1436 ImmOp:$offset, IntRegs:$src3),
1437 !if(isPredNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1438 ") ")#mnemonic#"($src2++#$offset) = $src3.new",
1439 [], "$src2 = $_dst_">,
1447 string ImmOpStr = !cast<string>(ImmOp);
1448 let offsetBits = !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2},
1449 !if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1},
1450 /* s4_0Imm */ offset{3-0}));
1451 let isPredicatedNew = isPredNew;
1452 let isPredicatedFalse = isPredNot;
1454 let IClass = 0b1010;
1456 let Inst{27-21} = 0b1011101;
1457 let Inst{20-16} = src2;
1459 let Inst{12-11} = MajOp;
1460 let Inst{10-8} = src3;
1461 let Inst{7} = isPredNew;
1462 let Inst{6-3} = offsetBits;
1463 let Inst{2} = isPredNot;
1464 let Inst{1-0} = src1;
1467 multiclass ST_PostInc_Pred_nv<string mnemonic, Operand ImmOp,
1468 bits<2> MajOp, bit PredNot> {
1469 def _pi : T_StorePI_nv_pred <mnemonic, ImmOp, MajOp, PredNot, 0>;
1472 def new_pi : T_StorePI_nv_pred <mnemonic, ImmOp, MajOp, PredNot, 1>;
1475 multiclass ST_PostInc_nv<string mnemonic, string BaseOp, Operand ImmOp,
1477 let BaseOpcode = "POST_"#BaseOp in {
1478 def S2_#NAME#_pi : T_StorePI_nv <mnemonic, ImmOp, MajOp>;
1481 defm S2_p#NAME#t : ST_PostInc_Pred_nv <mnemonic, ImmOp, MajOp, 0>;
1482 defm S2_p#NAME#f : ST_PostInc_Pred_nv <mnemonic, ImmOp, MajOp, 1>;
1486 let accessSize = ByteAccess in
1487 defm storerbnew: ST_PostInc_nv <"memb", "STrib", s4_0Imm, 0b00>;
1489 let accessSize = HalfWordAccess in
1490 defm storerhnew: ST_PostInc_nv <"memh", "STrih", s4_1Imm, 0b01>;
1492 let accessSize = WordAccess in
1493 defm storerinew: ST_PostInc_nv <"memw", "STriw", s4_2Imm, 0b10>;
1495 //===----------------------------------------------------------------------===//
1496 // Template class for post increment .new stores with register offset
1497 //===----------------------------------------------------------------------===//
1498 let isNewValue = 1, mayStore = 1, isNVStore = 1, opNewValue = 3 in
1499 class T_StorePI_RegNV <string mnemonic, bits<2> MajOp, MemAccessSize AccessSz>
1500 : NVInstPI_V4 <(outs IntRegs:$_dst_),
1501 (ins IntRegs:$src1, ModRegs:$src2, IntRegs:$src3),
1502 #mnemonic#"($src1++$src2) = $src3.new",
1503 [], "$src1 = $_dst_"> {
1507 let accessSize = AccessSz;
1509 let IClass = 0b1010;
1511 let Inst{27-21} = 0b1101101;
1512 let Inst{20-16} = src1;
1513 let Inst{13} = src2;
1514 let Inst{12-11} = MajOp;
1515 let Inst{10-8} = src3;
1519 def S2_storerbnew_pr : T_StorePI_RegNV<"memb", 0b00, ByteAccess>;
1520 def S2_storerhnew_pr : T_StorePI_RegNV<"memh", 0b01, HalfWordAccess>;
1521 def S2_storerinew_pr : T_StorePI_RegNV<"memw", 0b10, WordAccess>;
1523 // memb(Rx++#s4:0:circ(Mu))=Nt.new
1524 // memb(Rx++I:circ(Mu))=Nt.new
1525 // memb(Rx++Mu:brev)=Nt.new
1526 // memh(Rx++#s4:1:circ(Mu))=Nt.new
1527 // memh(Rx++I:circ(Mu))=Nt.new
1528 // memh(Rx++Mu)=Nt.new
1529 // memh(Rx++Mu:brev)=Nt.new
1531 // memw(Rx++#s4:2:circ(Mu))=Nt.new
1532 // memw(Rx++I:circ(Mu))=Nt.new
1533 // memw(Rx++Mu)=Nt.new
1534 // memw(Rx++Mu:brev)=Nt.new
1536 //===----------------------------------------------------------------------===//
1538 //===----------------------------------------------------------------------===//
1540 //===----------------------------------------------------------------------===//
1542 //===----------------------------------------------------------------------===//
1544 //===----------------------------------------------------------------------===//
1545 // multiclass/template class for the new-value compare jumps with the register
1547 //===----------------------------------------------------------------------===//
1549 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 11,
1550 opExtentAlign = 2 in
1551 class NVJrr_template<string mnemonic, bits<3> majOp, bit NvOpNum,
1552 bit isNegCond, bit isTak>
1554 (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset),
1555 "if ("#!if(isNegCond, "!","")#mnemonic#
1556 "($src1"#!if(!eq(NvOpNum, 0),".new, ",", ")#
1557 "$src2"#!if(!eq(NvOpNum, 1),".new))","))")#" jump:"
1558 #!if(isTak, "t","nt")#" $offset", []> {
1562 bits<3> Ns; // New-Value Operand
1563 bits<5> RegOp; // Non-New-Value Operand
1566 let isTaken = isTak;
1567 let isPredicatedFalse = isNegCond;
1568 let opNewValue{0} = NvOpNum;
1570 let Ns = !if(!eq(NvOpNum, 0), src1{2-0}, src2{2-0});
1571 let RegOp = !if(!eq(NvOpNum, 0), src2, src1);
1573 let IClass = 0b0010;
1574 let Inst{27-26} = 0b00;
1575 let Inst{25-23} = majOp;
1576 let Inst{22} = isNegCond;
1577 let Inst{18-16} = Ns;
1578 let Inst{13} = isTak;
1579 let Inst{12-8} = RegOp;
1580 let Inst{21-20} = offset{10-9};
1581 let Inst{7-1} = offset{8-2};
1585 multiclass NVJrr_cond<string mnemonic, bits<3> majOp, bit NvOpNum,
1587 // Branch not taken:
1588 def _nt: NVJrr_template<mnemonic, majOp, NvOpNum, isNegCond, 0>;
1590 def _t : NVJrr_template<mnemonic, majOp, NvOpNum, isNegCond, 1>;
1593 // NvOpNum = 0 -> First Operand is a new-value Register
1594 // NvOpNum = 1 -> Second Operand is a new-value Register
1596 multiclass NVJrr_base<string mnemonic, string BaseOp, bits<3> majOp,
1598 let BaseOpcode = BaseOp#_NVJ in {
1599 defm _t_jumpnv : NVJrr_cond<mnemonic, majOp, NvOpNum, 0>; // True cond
1600 defm _f_jumpnv : NVJrr_cond<mnemonic, majOp, NvOpNum, 1>; // False cond
1604 // if ([!]cmp.eq(Ns.new,Rt)) jump:[n]t #r9:2
1605 // if ([!]cmp.gt(Ns.new,Rt)) jump:[n]t #r9:2
1606 // if ([!]cmp.gtu(Ns.new,Rt)) jump:[n]t #r9:2
1607 // if ([!]cmp.gt(Rt,Ns.new)) jump:[n]t #r9:2
1608 // if ([!]cmp.gtu(Rt,Ns.new)) jump:[n]t #r9:2
1610 let isPredicated = 1, isBranch = 1, isNewValue = 1, isTerminator = 1,
1611 Defs = [PC], hasSideEffects = 0 in {
1612 defm J4_cmpeq : NVJrr_base<"cmp.eq", "CMPEQ", 0b000, 0>, PredRel;
1613 defm J4_cmpgt : NVJrr_base<"cmp.gt", "CMPGT", 0b001, 0>, PredRel;
1614 defm J4_cmpgtu : NVJrr_base<"cmp.gtu", "CMPGTU", 0b010, 0>, PredRel;
1615 defm J4_cmplt : NVJrr_base<"cmp.gt", "CMPLT", 0b011, 1>, PredRel;
1616 defm J4_cmpltu : NVJrr_base<"cmp.gtu", "CMPLTU", 0b100, 1>, PredRel;
1619 //===----------------------------------------------------------------------===//
1620 // multiclass/template class for the new-value compare jumps instruction
1621 // with a register and an unsigned immediate (U5) operand.
1622 //===----------------------------------------------------------------------===//
1624 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 11,
1625 opExtentAlign = 2 in
1626 class NVJri_template<string mnemonic, bits<3> majOp, bit isNegCond,
1629 (ins IntRegs:$src1, u5Imm:$src2, brtarget:$offset),
1630 "if ("#!if(isNegCond, "!","")#mnemonic#"($src1.new, #$src2)) jump:"
1631 #!if(isTak, "t","nt")#" $offset", []> {
1633 let isTaken = isTak;
1634 let isPredicatedFalse = isNegCond;
1635 let isTaken = isTak;
1641 let IClass = 0b0010;
1643 let Inst{25-23} = majOp;
1644 let Inst{22} = isNegCond;
1645 let Inst{18-16} = src1;
1646 let Inst{13} = isTak;
1647 let Inst{12-8} = src2;
1648 let Inst{21-20} = offset{10-9};
1649 let Inst{7-1} = offset{8-2};
1652 multiclass NVJri_cond<string mnemonic, bits<3> majOp, bit isNegCond> {
1653 // Branch not taken:
1654 def _nt: NVJri_template<mnemonic, majOp, isNegCond, 0>;
1656 def _t : NVJri_template<mnemonic, majOp, isNegCond, 1>;
1659 multiclass NVJri_base<string mnemonic, string BaseOp, bits<3> majOp> {
1660 let BaseOpcode = BaseOp#_NVJri in {
1661 defm _t_jumpnv : NVJri_cond<mnemonic, majOp, 0>; // True Cond
1662 defm _f_jumpnv : NVJri_cond<mnemonic, majOp, 1>; // False cond
1666 // if ([!]cmp.eq(Ns.new,#U5)) jump:[n]t #r9:2
1667 // if ([!]cmp.gt(Ns.new,#U5)) jump:[n]t #r9:2
1668 // if ([!]cmp.gtu(Ns.new,#U5)) jump:[n]t #r9:2
1670 let isPredicated = 1, isBranch = 1, isNewValue = 1, isTerminator = 1,
1671 Defs = [PC], hasSideEffects = 0 in {
1672 defm J4_cmpeqi : NVJri_base<"cmp.eq", "CMPEQ", 0b000>, PredRel;
1673 defm J4_cmpgti : NVJri_base<"cmp.gt", "CMPGT", 0b001>, PredRel;
1674 defm J4_cmpgtui : NVJri_base<"cmp.gtu", "CMPGTU", 0b010>, PredRel;
1677 //===----------------------------------------------------------------------===//
1678 // multiclass/template class for the new-value compare jumps instruction
1679 // with a register and an hardcoded 0/-1 immediate value.
1680 //===----------------------------------------------------------------------===//
1682 let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 11,
1683 opExtentAlign = 2 in
1684 class NVJ_ConstImm_template<string mnemonic, bits<3> majOp, string ImmVal,
1685 bit isNegCond, bit isTak>
1687 (ins IntRegs:$src1, brtarget:$offset),
1688 "if ("#!if(isNegCond, "!","")#mnemonic
1689 #"($src1.new, #"#ImmVal#")) jump:"
1690 #!if(isTak, "t","nt")#" $offset", []> {
1692 let isTaken = isTak;
1693 let isPredicatedFalse = isNegCond;
1694 let isTaken = isTak;
1698 let IClass = 0b0010;
1700 let Inst{25-23} = majOp;
1701 let Inst{22} = isNegCond;
1702 let Inst{18-16} = src1;
1703 let Inst{13} = isTak;
1704 let Inst{21-20} = offset{10-9};
1705 let Inst{7-1} = offset{8-2};
1708 multiclass NVJ_ConstImm_cond<string mnemonic, bits<3> majOp, string ImmVal,
1710 // Branch not taken:
1711 def _nt: NVJ_ConstImm_template<mnemonic, majOp, ImmVal, isNegCond, 0>;
1713 def _t : NVJ_ConstImm_template<mnemonic, majOp, ImmVal, isNegCond, 1>;
1716 multiclass NVJ_ConstImm_base<string mnemonic, string BaseOp, bits<3> majOp,
1718 let BaseOpcode = BaseOp#_NVJ_ConstImm in {
1719 defm _t_jumpnv : NVJ_ConstImm_cond<mnemonic, majOp, ImmVal, 0>; // True
1720 defm _f_jumpnv : NVJ_ConstImm_cond<mnemonic, majOp, ImmVal, 1>; // False
1724 // if ([!]tstbit(Ns.new,#0)) jump:[n]t #r9:2
1725 // if ([!]cmp.eq(Ns.new,#-1)) jump:[n]t #r9:2
1726 // if ([!]cmp.gt(Ns.new,#-1)) jump:[n]t #r9:2
1728 let isPredicated = 1, isBranch = 1, isNewValue = 1, isTerminator=1,
1729 Defs = [PC], hasSideEffects = 0 in {
1730 defm J4_tstbit0 : NVJ_ConstImm_base<"tstbit", "TSTBIT", 0b011, "0">, PredRel;
1731 defm J4_cmpeqn1 : NVJ_ConstImm_base<"cmp.eq", "CMPEQ", 0b100, "-1">, PredRel;
1732 defm J4_cmpgtn1 : NVJ_ConstImm_base<"cmp.gt", "CMPGT", 0b101, "-1">, PredRel;
1735 // J4_hintjumpr: Hint indirect conditional jump.
1736 let isBranch = 1, isIndirectBranch = 1, hasSideEffects = 0 in
1737 def J4_hintjumpr: JRInst <
1742 let IClass = 0b0101;
1743 let Inst{27-21} = 0b0010101;
1744 let Inst{20-16} = Rs;
1747 //===----------------------------------------------------------------------===//
1749 //===----------------------------------------------------------------------===//
1751 //===----------------------------------------------------------------------===//
1753 //===----------------------------------------------------------------------===//
1756 let hasNewValue = 1, isExtendable = 1, opExtendable = 1,
1757 isExtentSigned = 0, opExtentBits = 6, hasSideEffects = 0, Uses = [PC] in
1758 def C4_addipc : CRInst <(outs IntRegs:$Rd), (ins u6Ext:$u6),
1759 "$Rd = add(pc, #$u6)", [], "", CR_tc_2_SLOT3 > {
1763 let IClass = 0b0110;
1764 let Inst{27-16} = 0b101001001001;
1765 let Inst{12-7} = u6;
1771 let hasSideEffects = 0 in
1772 class T_LOGICAL_3OP<string MnOp1, string MnOp2, bits<2> OpBits, bit IsNeg>
1773 : CRInst<(outs PredRegs:$Pd),
1774 (ins PredRegs:$Ps, PredRegs:$Pt, PredRegs:$Pu),
1775 "$Pd = " # MnOp1 # "($Ps, " # MnOp2 # "($Pt, " #
1776 !if (IsNeg,"!","") # "$Pu))",
1777 [], "", CR_tc_2early_SLOT23> {
1783 let IClass = 0b0110;
1784 let Inst{27-24} = 0b1011;
1785 let Inst{23} = IsNeg;
1786 let Inst{22-21} = OpBits;
1788 let Inst{17-16} = Ps;
1795 def C4_and_and : T_LOGICAL_3OP<"and", "and", 0b00, 0>;
1796 def C4_and_or : T_LOGICAL_3OP<"and", "or", 0b01, 0>;
1797 def C4_or_and : T_LOGICAL_3OP<"or", "and", 0b10, 0>;
1798 def C4_or_or : T_LOGICAL_3OP<"or", "or", 0b11, 0>;
1799 def C4_and_andn : T_LOGICAL_3OP<"and", "and", 0b00, 1>;
1800 def C4_and_orn : T_LOGICAL_3OP<"and", "or", 0b01, 1>;
1801 def C4_or_andn : T_LOGICAL_3OP<"or", "and", 0b10, 1>;
1802 def C4_or_orn : T_LOGICAL_3OP<"or", "or", 0b11, 1>;
1804 // op(Ps, op(Pt, Pu))
1805 class LogLog_pat<SDNode Op1, SDNode Op2, InstHexagon MI>
1806 : Pat<(i1 (Op1 I1:$Ps, (Op2 I1:$Pt, I1:$Pu))),
1807 (MI I1:$Ps, I1:$Pt, I1:$Pu)>;
1809 // op(Ps, op(Pt, ~Pu))
1810 class LogLogNot_pat<SDNode Op1, SDNode Op2, InstHexagon MI>
1811 : Pat<(i1 (Op1 I1:$Ps, (Op2 I1:$Pt, (not I1:$Pu)))),
1812 (MI I1:$Ps, I1:$Pt, I1:$Pu)>;
1814 def: LogLog_pat<and, and, C4_and_and>;
1815 def: LogLog_pat<and, or, C4_and_or>;
1816 def: LogLog_pat<or, and, C4_or_and>;
1817 def: LogLog_pat<or, or, C4_or_or>;
1819 def: LogLogNot_pat<and, and, C4_and_andn>;
1820 def: LogLogNot_pat<and, or, C4_and_orn>;
1821 def: LogLogNot_pat<or, and, C4_or_andn>;
1822 def: LogLogNot_pat<or, or, C4_or_orn>;
1824 //===----------------------------------------------------------------------===//
1825 // PIC: Support for PIC compilations. The patterns and SD nodes defined
1826 // below are needed to support code generation for PIC
1827 //===----------------------------------------------------------------------===//
1829 def SDT_HexagonPICAdd
1830 : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
1831 def SDT_HexagonGOTAdd
1832 : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
1834 def SDT_HexagonGOTAddInternal : SDTypeProfile<1, 1, [SDTCisVT<0, i32>]>;
1835 def SDT_HexagonGOTAddInternalJT : SDTypeProfile<1, 1, [SDTCisVT<0, i32>]>;
1836 def SDT_HexagonGOTAddInternalBA : SDTypeProfile<1, 1, [SDTCisVT<0, i32>]>;
1838 def Hexagonpic_add : SDNode<"HexagonISD::PIC_ADD", SDT_HexagonPICAdd>;
1839 def Hexagonat_got : SDNode<"HexagonISD::AT_GOT", SDT_HexagonGOTAdd>;
1840 def Hexagongat_pcrel : SDNode<"HexagonISD::AT_PCREL",
1841 SDT_HexagonGOTAddInternal>;
1842 def Hexagongat_pcrel_jt : SDNode<"HexagonISD::AT_PCREL",
1843 SDT_HexagonGOTAddInternalJT>;
1844 def Hexagongat_pcrel_ba : SDNode<"HexagonISD::AT_PCREL",
1845 SDT_HexagonGOTAddInternalBA>;
1847 // PIC: Map from a block address computation to a PC-relative add
1848 def: Pat<(Hexagongat_pcrel_ba tblockaddress:$src1),
1849 (C4_addipc u32ImmPred:$src1)>;
1851 // PIC: Map from the computation to generate a GOT pointer to a PC-relative add
1852 def: Pat<(Hexagonpic_add texternalsym:$src1),
1853 (C4_addipc u32ImmPred:$src1)>;
1855 // PIC: Map from a jump table address computation to a PC-relative add
1856 def: Pat<(Hexagongat_pcrel_jt tjumptable:$src1),
1857 (C4_addipc u32ImmPred:$src1)>;
1859 // PIC: Map from a GOT-relative symbol reference to a load
1860 def: Pat<(Hexagonat_got (i32 IntRegs:$src1), tglobaladdr:$src2),
1861 (L2_loadri_io IntRegs:$src1, s30_2ImmPred:$src2)>;
1863 // PIC: Map from a static symbol reference to a PC-relative add
1864 def: Pat<(Hexagongat_pcrel tglobaladdr:$src1),
1865 (C4_addipc u32ImmPred:$src1)>;
1867 //===----------------------------------------------------------------------===//
1869 //===----------------------------------------------------------------------===//
1871 //===----------------------------------------------------------------------===//
1873 //===----------------------------------------------------------------------===//
1875 // Logical with-not instructions.
1876 def A4_andnp : T_ALU64_logical<"and", 0b001, 1, 0, 1>;
1877 def A4_ornp : T_ALU64_logical<"or", 0b011, 1, 0, 1>;
1879 def: Pat<(i64 (and (i64 DoubleRegs:$Rs), (i64 (not (i64 DoubleRegs:$Rt))))),
1880 (A4_andnp DoubleRegs:$Rs, DoubleRegs:$Rt)>;
1881 def: Pat<(i64 (or (i64 DoubleRegs:$Rs), (i64 (not (i64 DoubleRegs:$Rt))))),
1882 (A4_ornp DoubleRegs:$Rs, DoubleRegs:$Rt)>;
1884 let hasNewValue = 1, hasSideEffects = 0 in
1885 def S4_parity: ALU64Inst<(outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt),
1886 "$Rd = parity($Rs, $Rt)", [], "", ALU64_tc_2_SLOT23> {
1891 let IClass = 0b1101;
1892 let Inst{27-21} = 0b0101111;
1893 let Inst{20-16} = Rs;
1894 let Inst{12-8} = Rt;
1898 // Add and accumulate.
1899 // Rd=add(Rs,add(Ru,#s6))
1900 let isExtentSigned = 1, hasNewValue = 1, isExtendable = 1, opExtentBits = 6,
1902 def S4_addaddi : ALU64Inst <(outs IntRegs:$Rd),
1903 (ins IntRegs:$Rs, IntRegs:$Ru, s6Ext:$s6),
1904 "$Rd = add($Rs, add($Ru, #$s6))" ,
1905 [(set (i32 IntRegs:$Rd), (add (i32 IntRegs:$Rs),
1906 (add (i32 IntRegs:$Ru), s16_16ImmPred:$s6)))],
1907 "", ALU64_tc_2_SLOT23> {
1913 let IClass = 0b1101;
1915 let Inst{27-23} = 0b10110;
1916 let Inst{22-21} = s6{5-4};
1917 let Inst{20-16} = Rs;
1918 let Inst{13} = s6{3};
1919 let Inst{12-8} = Rd;
1920 let Inst{7-5} = s6{2-0};
1924 let isExtentSigned = 1, hasSideEffects = 0, hasNewValue = 1, isExtendable = 1,
1925 opExtentBits = 6, opExtendable = 2 in
1926 def S4_subaddi: ALU64Inst <(outs IntRegs:$Rd),
1927 (ins IntRegs:$Rs, s6Ext:$s6, IntRegs:$Ru),
1928 "$Rd = add($Rs, sub(#$s6, $Ru))",
1929 [], "", ALU64_tc_2_SLOT23> {
1935 let IClass = 0b1101;
1937 let Inst{27-23} = 0b10111;
1938 let Inst{22-21} = s6{5-4};
1939 let Inst{20-16} = Rs;
1940 let Inst{13} = s6{3};
1941 let Inst{12-8} = Rd;
1942 let Inst{7-5} = s6{2-0};
1946 // Rd=add(Rs,sub(#s6,Ru))
1947 def: Pat<(add (i32 IntRegs:$src1), (sub s32ImmPred:$src2,
1948 (i32 IntRegs:$src3))),
1949 (S4_subaddi IntRegs:$src1, s32ImmPred:$src2, IntRegs:$src3)>;
1951 // Rd=sub(add(Rs,#s6),Ru)
1952 def: Pat<(sub (add (i32 IntRegs:$src1), s32ImmPred:$src2),
1953 (i32 IntRegs:$src3)),
1954 (S4_subaddi IntRegs:$src1, s32ImmPred:$src2, IntRegs:$src3)>;
1956 // Rd=add(sub(Rs,Ru),#s6)
1957 def: Pat<(add (sub (i32 IntRegs:$src1), (i32 IntRegs:$src3)),
1958 (s32ImmPred:$src2)),
1959 (S4_subaddi IntRegs:$src1, s32ImmPred:$src2, IntRegs:$src3)>;
1962 // Add or subtract doublewords with carry.
1964 // Rdd=add(Rss,Rtt,Px):carry
1966 // Rdd=sub(Rss,Rtt,Px):carry
1969 // Rdd=extract(Rss,#u6,#U6)
1970 // Rdd=extract(Rss,Rtt)
1971 // Rd=extract(Rs,Rtt)
1972 // Rd=extract(Rs,#u5,#U5)
1974 def S4_extractp_rp : T_S3op_64 < "extract", 0b11, 0b100, 0>;
1975 def S4_extractp : T_S2op_extract <"extract", 0b1010, DoubleRegs, u6Imm>;
1977 let hasNewValue = 1 in {
1978 def S4_extract_rp : T_S3op_extract<"extract", 0b01>;
1979 def S4_extract : T_S2op_extract <"extract", 0b1101, IntRegs, u5Imm>;
1982 // Complex add/sub halfwords/words
1983 let Defs = [USR_OVF] in {
1984 def S4_vxaddsubh : T_S3op_64 < "vxaddsubh", 0b01, 0b100, 0, 1>;
1985 def S4_vxaddsubw : T_S3op_64 < "vxaddsubw", 0b01, 0b000, 0, 1>;
1986 def S4_vxsubaddh : T_S3op_64 < "vxsubaddh", 0b01, 0b110, 0, 1>;
1987 def S4_vxsubaddw : T_S3op_64 < "vxsubaddw", 0b01, 0b010, 0, 1>;
1990 let Defs = [USR_OVF] in {
1991 def S4_vxaddsubhr : T_S3op_64 < "vxaddsubh", 0b11, 0b000, 0, 1, 1, 1>;
1992 def S4_vxsubaddhr : T_S3op_64 < "vxsubaddh", 0b11, 0b010, 0, 1, 1, 1>;
1995 let Itinerary = M_tc_3x_SLOT23, Defs = [USR_OVF] in {
1996 def M4_mac_up_s1_sat: T_MType_acc_rr<"+= mpy", 0b011, 0b000, 0, [], 0, 1, 1>;
1997 def M4_nac_up_s1_sat: T_MType_acc_rr<"-= mpy", 0b011, 0b001, 0, [], 0, 1, 1>;
2000 // Logical xor with xor accumulation.
2001 // Rxx^=xor(Rss,Rtt)
2002 let hasSideEffects = 0 in
2004 : SInst <(outs DoubleRegs:$Rxx),
2005 (ins DoubleRegs:$dst2, DoubleRegs:$Rss, DoubleRegs:$Rtt),
2006 "$Rxx ^= xor($Rss, $Rtt)",
2007 [(set (i64 DoubleRegs:$Rxx),
2008 (xor (i64 DoubleRegs:$dst2), (xor (i64 DoubleRegs:$Rss),
2009 (i64 DoubleRegs:$Rtt))))],
2010 "$dst2 = $Rxx", S_3op_tc_1_SLOT23> {
2015 let IClass = 0b1100;
2017 let Inst{27-22} = 0b101010;
2018 let Inst{20-16} = Rss;
2019 let Inst{12-8} = Rtt;
2020 let Inst{7-5} = 0b000;
2021 let Inst{4-0} = Rxx;
2024 // Rotate and reduce bytes
2025 // Rdd=vrcrotate(Rss,Rt,#u2)
2026 let hasSideEffects = 0 in
2028 : SInst <(outs DoubleRegs:$Rdd),
2029 (ins DoubleRegs:$Rss, IntRegs:$Rt, u2Imm:$u2),
2030 "$Rdd = vrcrotate($Rss, $Rt, #$u2)",
2031 [], "", S_3op_tc_3x_SLOT23> {
2037 let IClass = 0b1100;
2039 let Inst{27-22} = 0b001111;
2040 let Inst{20-16} = Rss;
2041 let Inst{13} = u2{1};
2042 let Inst{12-8} = Rt;
2043 let Inst{7-6} = 0b11;
2044 let Inst{5} = u2{0};
2045 let Inst{4-0} = Rdd;
2048 // Rotate and reduce bytes with accumulation
2049 // Rxx+=vrcrotate(Rss,Rt,#u2)
2050 let hasSideEffects = 0 in
2051 def S4_vrcrotate_acc
2052 : SInst <(outs DoubleRegs:$Rxx),
2053 (ins DoubleRegs:$dst2, DoubleRegs:$Rss, IntRegs:$Rt, u2Imm:$u2),
2054 "$Rxx += vrcrotate($Rss, $Rt, #$u2)", [],
2055 "$dst2 = $Rxx", S_3op_tc_3x_SLOT23> {
2061 let IClass = 0b1100;
2063 let Inst{27-21} = 0b1011101;
2064 let Inst{20-16} = Rss;
2065 let Inst{13} = u2{1};
2066 let Inst{12-8} = Rt;
2067 let Inst{5} = u2{0};
2068 let Inst{4-0} = Rxx;
2071 // Vector reduce conditional negate halfwords
2072 let hasSideEffects = 0 in
2074 : SInst <(outs DoubleRegs:$Rxx),
2075 (ins DoubleRegs:$dst2, DoubleRegs:$Rss, IntRegs:$Rt),
2076 "$Rxx += vrcnegh($Rss, $Rt)", [],
2077 "$dst2 = $Rxx", S_3op_tc_3x_SLOT23> {
2082 let IClass = 0b1100;
2084 let Inst{27-21} = 0b1011001;
2085 let Inst{20-16} = Rss;
2087 let Inst{12-8} = Rt;
2088 let Inst{7-5} = 0b111;
2089 let Inst{4-0} = Rxx;
2093 def A4_bitspliti : T_S2op_2_di <"bitsplit", 0b110, 0b100>;
2095 // Arithmetic/Convergent round
2096 def A4_cround_ri : T_S2op_2_ii <"cround", 0b111, 0b000>;
2098 def A4_round_ri : T_S2op_2_ii <"round", 0b111, 0b100>;
2100 let Defs = [USR_OVF] in
2101 def A4_round_ri_sat : T_S2op_2_ii <"round", 0b111, 0b110, 1>;
2103 // Logical-logical words.
2104 // Compound or-and -- Rx=or(Ru,and(Rx,#s10))
2105 let isExtentSigned = 1, hasNewValue = 1, isExtendable = 1, opExtentBits = 10,
2108 ALU64Inst<(outs IntRegs:$Rx),
2109 (ins IntRegs:$Ru, IntRegs:$_src_, s10Ext:$s10),
2110 "$Rx = or($Ru, and($_src_, #$s10))" ,
2111 [(set (i32 IntRegs:$Rx),
2112 (or (i32 IntRegs:$Ru), (and (i32 IntRegs:$_src_), s32ImmPred:$s10)))] ,
2113 "$_src_ = $Rx", ALU64_tc_2_SLOT23> {
2118 let IClass = 0b1101;
2120 let Inst{27-22} = 0b101001;
2121 let Inst{20-16} = Rx;
2122 let Inst{21} = s10{9};
2123 let Inst{13-5} = s10{8-0};
2127 // Miscellaneous ALU64 instructions.
2129 let hasNewValue = 1, hasSideEffects = 0 in
2130 def A4_modwrapu: ALU64Inst<(outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt),
2131 "$Rd = modwrap($Rs, $Rt)", [], "", ALU64_tc_2_SLOT23> {
2136 let IClass = 0b1101;
2137 let Inst{27-21} = 0b0011111;
2138 let Inst{20-16} = Rs;
2139 let Inst{12-8} = Rt;
2140 let Inst{7-5} = 0b111;
2144 let hasSideEffects = 0 in
2145 def A4_bitsplit: ALU64Inst<(outs DoubleRegs:$Rd),
2146 (ins IntRegs:$Rs, IntRegs:$Rt),
2147 "$Rd = bitsplit($Rs, $Rt)", [], "", ALU64_tc_1_SLOT23> {
2152 let IClass = 0b1101;
2153 let Inst{27-24} = 0b0100;
2155 let Inst{20-16} = Rs;
2156 let Inst{12-8} = Rt;
2160 let hasSideEffects = 0 in
2161 def dep_S2_packhl: ALU64Inst<(outs DoubleRegs:$Rd),
2162 (ins IntRegs:$Rs, IntRegs:$Rt),
2163 "$Rd = packhl($Rs, $Rt):deprecated", [], "", ALU64_tc_1_SLOT23> {
2168 let IClass = 0b1101;
2169 let Inst{27-24} = 0b0100;
2171 let Inst{20-16} = Rs;
2172 let Inst{12-8} = Rt;
2176 let hasNewValue = 1, hasSideEffects = 0 in
2177 def dep_A2_addsat: ALU64Inst<(outs IntRegs:$Rd),
2178 (ins IntRegs:$Rs, IntRegs:$Rt),
2179 "$Rd = add($Rs, $Rt):sat:deprecated", [], "", ALU64_tc_2_SLOT23> {
2184 let IClass = 0b1101;
2185 let Inst{27-21} = 0b0101100;
2186 let Inst{20-16} = Rs;
2187 let Inst{12-8} = Rt;
2192 let hasNewValue = 1, hasSideEffects = 0 in
2193 def dep_A2_subsat: ALU64Inst<(outs IntRegs:$Rd),
2194 (ins IntRegs:$Rs, IntRegs:$Rt),
2195 "$Rd = sub($Rs, $Rt):sat:deprecated", [], "", ALU64_tc_2_SLOT23> {
2200 let IClass = 0b1101;
2201 let Inst{27-21} = 0b0101100;
2202 let Inst{20-16} = Rt;
2203 let Inst{12-8} = Rs;
2208 // Rx[&|]=xor(Rs,Rt)
2209 def M4_or_xor : T_MType_acc_rr < "|= xor", 0b110, 0b001, 0>;
2210 def M4_and_xor : T_MType_acc_rr < "&= xor", 0b010, 0b010, 0>;
2212 // Rx[&|^]=or(Rs,Rt)
2213 def M4_xor_or : T_MType_acc_rr < "^= or", 0b110, 0b011, 0>;
2215 let CextOpcode = "ORr_ORr" in
2216 def M4_or_or : T_MType_acc_rr < "|= or", 0b110, 0b000, 0>;
2217 def M4_and_or : T_MType_acc_rr < "&= or", 0b010, 0b001, 0>;
2219 // Rx[&|^]=and(Rs,Rt)
2220 def M4_xor_and : T_MType_acc_rr < "^= and", 0b110, 0b010, 0>;
2222 let CextOpcode = "ORr_ANDr" in
2223 def M4_or_and : T_MType_acc_rr < "|= and", 0b010, 0b011, 0>;
2224 def M4_and_and : T_MType_acc_rr < "&= and", 0b010, 0b000, 0>;
2226 // Rx[&|^]=and(Rs,~Rt)
2227 def M4_xor_andn : T_MType_acc_rr < "^= and", 0b001, 0b010, 0, [], 1>;
2228 def M4_or_andn : T_MType_acc_rr < "|= and", 0b001, 0b000, 0, [], 1>;
2229 def M4_and_andn : T_MType_acc_rr < "&= and", 0b001, 0b001, 0, [], 1>;
2231 def: T_MType_acc_pat2 <M4_or_xor, xor, or>;
2232 def: T_MType_acc_pat2 <M4_and_xor, xor, and>;
2233 def: T_MType_acc_pat2 <M4_or_and, and, or>;
2234 def: T_MType_acc_pat2 <M4_and_and, and, and>;
2235 def: T_MType_acc_pat2 <M4_xor_and, and, xor>;
2236 def: T_MType_acc_pat2 <M4_or_or, or, or>;
2237 def: T_MType_acc_pat2 <M4_and_or, or, and>;
2238 def: T_MType_acc_pat2 <M4_xor_or, or, xor>;
2240 class T_MType_acc_pat3 <InstHexagon MI, SDNode firstOp, SDNode secOp>
2241 : Pat <(i32 (secOp IntRegs:$src1, (firstOp IntRegs:$src2,
2242 (not IntRegs:$src3)))),
2243 (i32 (MI IntRegs:$src1, IntRegs:$src2, IntRegs:$src3))>;
2245 def: T_MType_acc_pat3 <M4_or_andn, and, or>;
2246 def: T_MType_acc_pat3 <M4_and_andn, and, and>;
2247 def: T_MType_acc_pat3 <M4_xor_andn, and, xor>;
2249 // Compound or-or and or-and
2250 let isExtentSigned = 1, InputType = "imm", hasNewValue = 1, isExtendable = 1,
2251 opExtentBits = 10, opExtendable = 3 in
2252 class T_CompOR <string mnemonic, bits<2> MajOp, SDNode OpNode>
2253 : MInst_acc <(outs IntRegs:$Rx),
2254 (ins IntRegs:$src1, IntRegs:$Rs, s10Ext:$s10),
2255 "$Rx |= "#mnemonic#"($Rs, #$s10)",
2256 [(set (i32 IntRegs:$Rx), (or (i32 IntRegs:$src1),
2257 (OpNode (i32 IntRegs:$Rs), s32ImmPred:$s10)))],
2258 "$src1 = $Rx", ALU64_tc_2_SLOT23>, ImmRegRel {
2263 let IClass = 0b1101;
2265 let Inst{27-24} = 0b1010;
2266 let Inst{23-22} = MajOp;
2267 let Inst{20-16} = Rs;
2268 let Inst{21} = s10{9};
2269 let Inst{13-5} = s10{8-0};
2273 let CextOpcode = "ORr_ANDr" in
2274 def S4_or_andi : T_CompOR <"and", 0b00, and>;
2276 let CextOpcode = "ORr_ORr" in
2277 def S4_or_ori : T_CompOR <"or", 0b10, or>;
2280 // Rd=modwrap(Rs,Rt)
2282 // Rd=cround(Rs,#u5)
2284 // Rd=round(Rs,#u5)[:sat]
2285 // Rd=round(Rs,Rt)[:sat]
2286 // Vector reduce add unsigned halfwords
2287 // Rd=vraddh(Rss,Rtt)
2289 // Rdd=vaddb(Rss,Rtt)
2290 // Vector conditional negate
2291 // Rdd=vcnegh(Rss,Rt)
2292 // Rxx+=vrcnegh(Rss,Rt)
2293 // Vector maximum bytes
2294 // Rdd=vmaxb(Rtt,Rss)
2295 // Vector reduce maximum halfwords
2296 // Rxx=vrmaxh(Rss,Ru)
2297 // Rxx=vrmaxuh(Rss,Ru)
2298 // Vector reduce maximum words
2299 // Rxx=vrmaxuw(Rss,Ru)
2300 // Rxx=vrmaxw(Rss,Ru)
2301 // Vector minimum bytes
2302 // Rdd=vminb(Rtt,Rss)
2303 // Vector reduce minimum halfwords
2304 // Rxx=vrminh(Rss,Ru)
2305 // Rxx=vrminuh(Rss,Ru)
2306 // Vector reduce minimum words
2307 // Rxx=vrminuw(Rss,Ru)
2308 // Rxx=vrminw(Rss,Ru)
2309 // Vector subtract bytes
2310 // Rdd=vsubb(Rss,Rtt)
2312 //===----------------------------------------------------------------------===//
2314 //===----------------------------------------------------------------------===//
2316 //===----------------------------------------------------------------------===//
2318 //===----------------------------------------------------------------------===//
2321 def S2_brevp : T_S2op_3 <"brev", 0b11, 0b110>;
2324 def S2_ct0p : T_COUNT_LEADING_64<"ct0", 0b111, 0b010>;
2325 def S2_ct1p : T_COUNT_LEADING_64<"ct1", 0b111, 0b100>;
2326 def S4_clbpnorm : T_COUNT_LEADING_64<"normamt", 0b011, 0b000>;
2328 def: Pat<(i32 (trunc (cttz (i64 DoubleRegs:$Rss)))),
2329 (S2_ct0p (i64 DoubleRegs:$Rss))>;
2330 def: Pat<(i32 (trunc (cttz (not (i64 DoubleRegs:$Rss))))),
2331 (S2_ct1p (i64 DoubleRegs:$Rss))>;
2333 let hasSideEffects = 0, hasNewValue = 1 in
2334 def S4_clbaddi : SInst<(outs IntRegs:$Rd), (ins IntRegs:$Rs, s6Imm:$s6),
2335 "$Rd = add(clb($Rs), #$s6)", [], "", S_2op_tc_2_SLOT23> {
2339 let IClass = 0b1000;
2340 let Inst{27-24} = 0b1100;
2341 let Inst{23-21} = 0b001;
2342 let Inst{20-16} = Rs;
2343 let Inst{13-8} = s6;
2344 let Inst{7-5} = 0b000;
2348 let hasSideEffects = 0, hasNewValue = 1 in
2349 def S4_clbpaddi : SInst<(outs IntRegs:$Rd), (ins DoubleRegs:$Rs, s6Imm:$s6),
2350 "$Rd = add(clb($Rs), #$s6)", [], "", S_2op_tc_2_SLOT23> {
2354 let IClass = 0b1000;
2355 let Inst{27-24} = 0b1000;
2356 let Inst{23-21} = 0b011;
2357 let Inst{20-16} = Rs;
2358 let Inst{13-8} = s6;
2359 let Inst{7-5} = 0b010;
2364 // Bit test/set/clear
2365 def S4_ntstbit_i : T_TEST_BIT_IMM<"!tstbit", 0b001>;
2366 def S4_ntstbit_r : T_TEST_BIT_REG<"!tstbit", 1>;
2368 let AddedComplexity = 20 in { // Complexity greater than cmp reg-imm.
2369 def: Pat<(i1 (seteq (and (shl 1, u5ImmPred:$u5), (i32 IntRegs:$Rs)), 0)),
2370 (S4_ntstbit_i (i32 IntRegs:$Rs), u5ImmPred:$u5)>;
2371 def: Pat<(i1 (seteq (and (shl 1, (i32 IntRegs:$Rt)), (i32 IntRegs:$Rs)), 0)),
2372 (S4_ntstbit_r (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))>;
2375 // Add extra complexity to prefer these instructions over bitsset/bitsclr.
2376 // The reason is that tstbit/ntstbit can be folded into a compound instruction:
2377 // if ([!]tstbit(...)) jump ...
2378 let AddedComplexity = 100 in
2379 def: Pat<(i1 (setne (and (i32 IntRegs:$Rs), (i32 Set5ImmPred:$u5)), (i32 0))),
2380 (S2_tstbit_i (i32 IntRegs:$Rs), (BITPOS32 Set5ImmPred:$u5))>;
2382 let AddedComplexity = 100 in
2383 def: Pat<(i1 (seteq (and (i32 IntRegs:$Rs), (i32 Set5ImmPred:$u5)), (i32 0))),
2384 (S4_ntstbit_i (i32 IntRegs:$Rs), (BITPOS32 Set5ImmPred:$u5))>;
2386 def C4_nbitsset : T_TEST_BITS_REG<"!bitsset", 0b01, 1>;
2387 def C4_nbitsclr : T_TEST_BITS_REG<"!bitsclr", 0b10, 1>;
2388 def C4_nbitsclri : T_TEST_BITS_IMM<"!bitsclr", 0b10, 1>;
2390 // Do not increase complexity of these patterns. In the DAG, "cmp i8" may be
2391 // represented as a compare against "value & 0xFF", which is an exact match
2392 // for cmpb (same for cmph). The patterns below do not contain any additional
2393 // complexity that would make them preferable, and if they were actually used
2394 // instead of cmpb/cmph, they would result in a compare against register that
2395 // is loaded with the byte/half mask (i.e. 0xFF or 0xFFFF).
2396 def: Pat<(i1 (setne (and I32:$Rs, u6ImmPred:$u6), 0)),
2397 (C4_nbitsclri I32:$Rs, u6ImmPred:$u6)>;
2398 def: Pat<(i1 (setne (and I32:$Rs, I32:$Rt), 0)),
2399 (C4_nbitsclr I32:$Rs, I32:$Rt)>;
2400 def: Pat<(i1 (setne (and I32:$Rs, I32:$Rt), I32:$Rt)),
2401 (C4_nbitsset I32:$Rs, I32:$Rt)>;
2403 //===----------------------------------------------------------------------===//
2405 //===----------------------------------------------------------------------===//
2407 //===----------------------------------------------------------------------===//
2409 //===----------------------------------------------------------------------===//
2411 // Rd=add(#u6,mpyi(Rs,#U6)) -- Multiply by immed and add immed.
2413 let hasNewValue = 1, isExtendable = 1, opExtentBits = 6, opExtendable = 1 in
2414 def M4_mpyri_addi : MInst<(outs IntRegs:$Rd),
2415 (ins u6Ext:$u6, IntRegs:$Rs, u6Imm:$U6),
2416 "$Rd = add(#$u6, mpyi($Rs, #$U6))" ,
2417 [(set (i32 IntRegs:$Rd),
2418 (add (mul (i32 IntRegs:$Rs), u6ImmPred:$U6),
2419 u32ImmPred:$u6))] ,"",ALU64_tc_3x_SLOT23> {
2425 let IClass = 0b1101;
2427 let Inst{27-24} = 0b1000;
2428 let Inst{23} = U6{5};
2429 let Inst{22-21} = u6{5-4};
2430 let Inst{20-16} = Rs;
2431 let Inst{13} = u6{3};
2432 let Inst{12-8} = Rd;
2433 let Inst{7-5} = u6{2-0};
2434 let Inst{4-0} = U6{4-0};
2437 // Rd=add(#u6,mpyi(Rs,Rt))
2438 let CextOpcode = "ADD_MPY", InputType = "imm", hasNewValue = 1,
2439 isExtendable = 1, opExtentBits = 6, opExtendable = 1 in
2440 def M4_mpyrr_addi : MInst <(outs IntRegs:$Rd),
2441 (ins u6Ext:$u6, IntRegs:$Rs, IntRegs:$Rt),
2442 "$Rd = add(#$u6, mpyi($Rs, $Rt))" ,
2443 [(set (i32 IntRegs:$Rd),
2444 (add (mul (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)), u32ImmPred:$u6))],
2445 "", ALU64_tc_3x_SLOT23>, ImmRegRel {
2451 let IClass = 0b1101;
2453 let Inst{27-23} = 0b01110;
2454 let Inst{22-21} = u6{5-4};
2455 let Inst{20-16} = Rs;
2456 let Inst{13} = u6{3};
2457 let Inst{12-8} = Rt;
2458 let Inst{7-5} = u6{2-0};
2462 let hasNewValue = 1 in
2463 class T_AddMpy <bit MajOp, PatLeaf ImmPred, dag ins>
2464 : ALU64Inst <(outs IntRegs:$dst), ins,
2465 "$dst = add($src1, mpyi("#!if(MajOp,"$src3, #$src2))",
2467 [(set (i32 IntRegs:$dst),
2468 (add (i32 IntRegs:$src1), (mul (i32 IntRegs:$src3), ImmPred:$src2)))],
2469 "", ALU64_tc_3x_SLOT23> {
2475 let IClass = 0b1101;
2477 bits<6> ImmValue = !if(MajOp, src2{5-0}, src2{7-2});
2479 let Inst{27-24} = 0b1111;
2480 let Inst{23} = MajOp;
2481 let Inst{22-21} = ImmValue{5-4};
2482 let Inst{20-16} = src3;
2483 let Inst{13} = ImmValue{3};
2484 let Inst{12-8} = dst;
2485 let Inst{7-5} = ImmValue{2-0};
2486 let Inst{4-0} = src1;
2489 def M4_mpyri_addr_u2 : T_AddMpy<0b0, u6_2ImmPred,
2490 (ins IntRegs:$src1, u6_2Imm:$src2, IntRegs:$src3)>;
2492 let isExtendable = 1, opExtentBits = 6, opExtendable = 3,
2493 CextOpcode = "ADD_MPY", InputType = "imm" in
2494 def M4_mpyri_addr : T_AddMpy<0b1, u32ImmPred,
2495 (ins IntRegs:$src1, IntRegs:$src3, u6Ext:$src2)>, ImmRegRel;
2497 // Rx=add(Ru,mpyi(Rx,Rs))
2498 let CextOpcode = "ADD_MPY", InputType = "reg", hasNewValue = 1 in
2499 def M4_mpyrr_addr: MInst_acc <(outs IntRegs:$Rx),
2500 (ins IntRegs:$Ru, IntRegs:$_src_, IntRegs:$Rs),
2501 "$Rx = add($Ru, mpyi($_src_, $Rs))",
2502 [(set (i32 IntRegs:$Rx), (add (i32 IntRegs:$Ru),
2503 (mul (i32 IntRegs:$_src_), (i32 IntRegs:$Rs))))],
2504 "$_src_ = $Rx", M_tc_3x_SLOT23>, ImmRegRel {
2509 let IClass = 0b1110;
2511 let Inst{27-21} = 0b0011000;
2512 let Inst{12-8} = Rx;
2514 let Inst{20-16} = Rs;
2518 // Vector reduce multiply word by signed half (32x16)
2519 //Rdd=vrmpyweh(Rss,Rtt)[:<<1]
2520 def M4_vrmpyeh_s0 : T_M2_vmpy<"vrmpyweh", 0b010, 0b100, 0, 0, 0>;
2521 def M4_vrmpyeh_s1 : T_M2_vmpy<"vrmpyweh", 0b110, 0b100, 1, 0, 0>;
2523 //Rdd=vrmpywoh(Rss,Rtt)[:<<1]
2524 def M4_vrmpyoh_s0 : T_M2_vmpy<"vrmpywoh", 0b001, 0b010, 0, 0, 0>;
2525 def M4_vrmpyoh_s1 : T_M2_vmpy<"vrmpywoh", 0b101, 0b010, 1, 0, 0>;
2527 //Rdd+=vrmpyweh(Rss,Rtt)[:<<1]
2528 def M4_vrmpyeh_acc_s0: T_M2_vmpy_acc<"vrmpyweh", 0b001, 0b110, 0, 0>;
2529 def M4_vrmpyeh_acc_s1: T_M2_vmpy_acc<"vrmpyweh", 0b101, 0b110, 1, 0>;
2531 //Rdd=vrmpywoh(Rss,Rtt)[:<<1]
2532 def M4_vrmpyoh_acc_s0: T_M2_vmpy_acc<"vrmpywoh", 0b011, 0b110, 0, 0>;
2533 def M4_vrmpyoh_acc_s1: T_M2_vmpy_acc<"vrmpywoh", 0b111, 0b110, 1, 0>;
2535 // Vector multiply halfwords, signed by unsigned
2536 // Rdd=vmpyhsu(Rs,Rt)[:<<]:sat
2537 def M2_vmpy2su_s0 : T_XTYPE_mpy64 < "vmpyhsu", 0b000, 0b111, 1, 0, 0>;
2538 def M2_vmpy2su_s1 : T_XTYPE_mpy64 < "vmpyhsu", 0b100, 0b111, 1, 1, 0>;
2540 // Rxx+=vmpyhsu(Rs,Rt)[:<<1]:sat
2541 def M2_vmac2su_s0 : T_XTYPE_mpy64_acc < "vmpyhsu", "+", 0b011, 0b101, 1, 0, 0>;
2542 def M2_vmac2su_s1 : T_XTYPE_mpy64_acc < "vmpyhsu", "+", 0b111, 0b101, 1, 1, 0>;
2544 // Vector polynomial multiply halfwords
2545 // Rdd=vpmpyh(Rs,Rt)
2546 def M4_vpmpyh : T_XTYPE_mpy64 < "vpmpyh", 0b110, 0b111, 0, 0, 0>;
2548 // Rxx^=vpmpyh(Rs,Rt)
2549 def M4_vpmpyh_acc : T_XTYPE_mpy64_acc < "vpmpyh", "^", 0b101, 0b111, 0, 0, 0>;
2551 // Polynomial multiply words
2553 def M4_pmpyw : T_XTYPE_mpy64 < "pmpyw", 0b010, 0b111, 0, 0, 0>;
2555 // Rxx^=pmpyw(Rs,Rt)
2556 def M4_pmpyw_acc : T_XTYPE_mpy64_acc < "pmpyw", "^", 0b001, 0b111, 0, 0, 0>;
2558 //===----------------------------------------------------------------------===//
2560 //===----------------------------------------------------------------------===//
2562 //===----------------------------------------------------------------------===//
2563 // ALU64/Vector compare
2564 //===----------------------------------------------------------------------===//
2565 //===----------------------------------------------------------------------===//
2566 // Template class for vector compare
2567 //===----------------------------------------------------------------------===//
2569 let hasSideEffects = 0 in
2570 class T_vcmpImm <string Str, bits<2> cmpOp, bits<2> minOp, Operand ImmOprnd>
2571 : ALU64_rr <(outs PredRegs:$Pd),
2572 (ins DoubleRegs:$Rss, ImmOprnd:$Imm),
2573 "$Pd = "#Str#"($Rss, #$Imm)",
2574 [], "", ALU64_tc_2early_SLOT23> {
2579 let ImmBits{6-0} = Imm{6-0};
2580 let ImmBits{7} = !if (!eq(cmpOp,0b10), 0b0, Imm{7}); // 0 for vcmp[bhw].gtu
2582 let IClass = 0b1101;
2584 let Inst{27-24} = 0b1100;
2585 let Inst{22-21} = cmpOp;
2586 let Inst{20-16} = Rss;
2587 let Inst{12-5} = ImmBits;
2588 let Inst{4-3} = minOp;
2592 // Vector compare bytes
2593 def A4_vcmpbgt : T_vcmp <"vcmpb.gt", 0b1010>;
2594 def: T_vcmp_pat<A4_vcmpbgt, setgt, v8i8>;
2596 let AsmString = "$Pd = any8(vcmpb.eq($Rss, $Rtt))" in
2597 def A4_vcmpbeq_any : T_vcmp <"any8(vcmpb.gt", 0b1000>;
2599 def A4_vcmpbeqi : T_vcmpImm <"vcmpb.eq", 0b00, 0b00, u8Imm>;
2600 def A4_vcmpbgti : T_vcmpImm <"vcmpb.gt", 0b01, 0b00, s8Imm>;
2601 def A4_vcmpbgtui : T_vcmpImm <"vcmpb.gtu", 0b10, 0b00, u7Imm>;
2603 // Vector compare halfwords
2604 def A4_vcmpheqi : T_vcmpImm <"vcmph.eq", 0b00, 0b01, s8Imm>;
2605 def A4_vcmphgti : T_vcmpImm <"vcmph.gt", 0b01, 0b01, s8Imm>;
2606 def A4_vcmphgtui : T_vcmpImm <"vcmph.gtu", 0b10, 0b01, u7Imm>;
2608 // Vector compare words
2609 def A4_vcmpweqi : T_vcmpImm <"vcmpw.eq", 0b00, 0b10, s8Imm>;
2610 def A4_vcmpwgti : T_vcmpImm <"vcmpw.gt", 0b01, 0b10, s8Imm>;
2611 def A4_vcmpwgtui : T_vcmpImm <"vcmpw.gtu", 0b10, 0b10, u7Imm>;
2613 //===----------------------------------------------------------------------===//
2615 //===----------------------------------------------------------------------===//
2616 // Shift by immediate and accumulate/logical.
2617 // Rx=add(#u8,asl(Rx,#U5)) Rx=add(#u8,lsr(Rx,#U5))
2618 // Rx=sub(#u8,asl(Rx,#U5)) Rx=sub(#u8,lsr(Rx,#U5))
2619 // Rx=and(#u8,asl(Rx,#U5)) Rx=and(#u8,lsr(Rx,#U5))
2620 // Rx=or(#u8,asl(Rx,#U5)) Rx=or(#u8,lsr(Rx,#U5))
2621 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8,
2622 hasNewValue = 1, opNewValue = 0 in
2623 class T_S4_ShiftOperate<string MnOp, string MnSh, SDNode Op, SDNode Sh,
2624 bit asl_lsr, bits<2> MajOp, InstrItinClass Itin>
2625 : MInst_acc<(outs IntRegs:$Rd), (ins u8Ext:$u8, IntRegs:$Rx, u5Imm:$U5),
2626 "$Rd = "#MnOp#"(#$u8, "#MnSh#"($Rx, #$U5))",
2627 [(set (i32 IntRegs:$Rd),
2628 (Op (Sh I32:$Rx, u5ImmPred:$U5), u32ImmPred:$u8))],
2629 "$Rd = $Rx", Itin> {
2636 let IClass = 0b1101;
2637 let Inst{27-24} = 0b1110;
2638 let Inst{23-21} = u8{7-5};
2639 let Inst{20-16} = Rd;
2640 let Inst{13} = u8{4};
2641 let Inst{12-8} = U5;
2642 let Inst{7-5} = u8{3-1};
2643 let Inst{4} = asl_lsr;
2644 let Inst{3} = u8{0};
2645 let Inst{2-1} = MajOp;
2648 multiclass T_ShiftOperate<string mnemonic, SDNode Op, bits<2> MajOp,
2649 InstrItinClass Itin> {
2650 def _asl_ri : T_S4_ShiftOperate<mnemonic, "asl", Op, shl, 0, MajOp, Itin>;
2651 def _lsr_ri : T_S4_ShiftOperate<mnemonic, "lsr", Op, srl, 1, MajOp, Itin>;
2654 let AddedComplexity = 200 in {
2655 defm S4_addi : T_ShiftOperate<"add", add, 0b10, ALU64_tc_2_SLOT23>;
2656 defm S4_andi : T_ShiftOperate<"and", and, 0b00, ALU64_tc_2_SLOT23>;
2659 let AddedComplexity = 30 in
2660 defm S4_ori : T_ShiftOperate<"or", or, 0b01, ALU64_tc_1_SLOT23>;
2662 defm S4_subi : T_ShiftOperate<"sub", sub, 0b11, ALU64_tc_1_SLOT23>;
2664 let AddedComplexity = 200 in {
2665 def: Pat<(add addrga:$addr, (shl I32:$src2, u5ImmPred:$src3)),
2666 (S4_addi_asl_ri addrga:$addr, IntRegs:$src2, u5ImmPred:$src3)>;
2667 def: Pat<(add addrga:$addr, (srl I32:$src2, u5ImmPred:$src3)),
2668 (S4_addi_lsr_ri addrga:$addr, IntRegs:$src2, u5ImmPred:$src3)>;
2669 def: Pat<(sub addrga:$addr, (shl I32:$src2, u5ImmPred:$src3)),
2670 (S4_subi_asl_ri addrga:$addr, IntRegs:$src2, u5ImmPred:$src3)>;
2671 def: Pat<(sub addrga:$addr, (srl I32:$src2, u5ImmPred:$src3)),
2672 (S4_subi_lsr_ri addrga:$addr, IntRegs:$src2, u5ImmPred:$src3)>;
2675 // Vector conditional negate
2676 // Rdd=vcnegh(Rss,Rt)
2677 let Defs = [USR_OVF], Itinerary = S_3op_tc_2_SLOT23 in
2678 def S2_vcnegh : T_S3op_shiftVect < "vcnegh", 0b11, 0b01>;
2680 // Rd=[cround|round](Rs,Rt)
2681 let hasNewValue = 1, Itinerary = S_3op_tc_2_SLOT23 in {
2682 def A4_cround_rr : T_S3op_3 < "cround", IntRegs, 0b11, 0b00>;
2683 def A4_round_rr : T_S3op_3 < "round", IntRegs, 0b11, 0b10>;
2686 // Rd=round(Rs,Rt):sat
2687 let hasNewValue = 1, Defs = [USR_OVF], Itinerary = S_3op_tc_2_SLOT23 in
2688 def A4_round_rr_sat : T_S3op_3 < "round", IntRegs, 0b11, 0b11, 1>;
2690 // Rd=[cmpyiwh|cmpyrwh](Rss,Rt):<<1:rnd:sat
2691 let Defs = [USR_OVF], Itinerary = S_3op_tc_3x_SLOT23 in {
2692 def M4_cmpyi_wh : T_S3op_8<"cmpyiwh", 0b100, 1, 1, 1>;
2693 def M4_cmpyr_wh : T_S3op_8<"cmpyrwh", 0b110, 1, 1, 1>;
2696 // Rdd=[add|sub](Rss,Rtt,Px):carry
2697 let isPredicateLate = 1, hasSideEffects = 0 in
2698 class T_S3op_carry <string mnemonic, bits<3> MajOp>
2699 : SInst < (outs DoubleRegs:$Rdd, PredRegs:$Px),
2700 (ins DoubleRegs:$Rss, DoubleRegs:$Rtt, PredRegs:$Pu),
2701 "$Rdd = "#mnemonic#"($Rss, $Rtt, $Pu):carry",
2702 [], "$Px = $Pu", S_3op_tc_1_SLOT23 > {
2708 let IClass = 0b1100;
2710 let Inst{27-24} = 0b0010;
2711 let Inst{23-21} = MajOp;
2712 let Inst{20-16} = Rss;
2713 let Inst{12-8} = Rtt;
2715 let Inst{4-0} = Rdd;
2718 def A4_addp_c : T_S3op_carry < "add", 0b110 >;
2719 def A4_subp_c : T_S3op_carry < "sub", 0b111 >;
2721 let Itinerary = S_3op_tc_3_SLOT23, hasSideEffects = 0 in
2722 class T_S3op_6 <string mnemonic, bits<3> MinOp, bit isUnsigned>
2723 : SInst <(outs DoubleRegs:$Rxx),
2724 (ins DoubleRegs:$dst2, DoubleRegs:$Rss, IntRegs:$Ru),
2725 "$Rxx = "#mnemonic#"($Rss, $Ru)" ,
2726 [] , "$dst2 = $Rxx"> {
2731 let IClass = 0b1100;
2733 let Inst{27-21} = 0b1011001;
2734 let Inst{20-16} = Rss;
2735 let Inst{13} = isUnsigned;
2736 let Inst{12-8} = Rxx;
2737 let Inst{7-5} = MinOp;
2741 // Vector reduce maximum halfwords
2742 // Rxx=vrmax[u]h(Rss,Ru)
2743 def A4_vrmaxh : T_S3op_6 < "vrmaxh", 0b001, 0>;
2744 def A4_vrmaxuh : T_S3op_6 < "vrmaxuh", 0b001, 1>;
2746 // Vector reduce maximum words
2747 // Rxx=vrmax[u]w(Rss,Ru)
2748 def A4_vrmaxw : T_S3op_6 < "vrmaxw", 0b010, 0>;
2749 def A4_vrmaxuw : T_S3op_6 < "vrmaxuw", 0b010, 1>;
2751 // Vector reduce minimum halfwords
2752 // Rxx=vrmin[u]h(Rss,Ru)
2753 def A4_vrminh : T_S3op_6 < "vrminh", 0b101, 0>;
2754 def A4_vrminuh : T_S3op_6 < "vrminuh", 0b101, 1>;
2756 // Vector reduce minimum words
2757 // Rxx=vrmin[u]w(Rss,Ru)
2758 def A4_vrminw : T_S3op_6 < "vrminw", 0b110, 0>;
2759 def A4_vrminuw : T_S3op_6 < "vrminuw", 0b110, 1>;
2761 // Shift an immediate left by register amount.
2762 let hasNewValue = 1, hasSideEffects = 0 in
2763 def S4_lsli: SInst <(outs IntRegs:$Rd), (ins s6Imm:$s6, IntRegs:$Rt),
2764 "$Rd = lsl(#$s6, $Rt)" ,
2765 [(set (i32 IntRegs:$Rd), (shl s6ImmPred:$s6,
2766 (i32 IntRegs:$Rt)))],
2767 "", S_3op_tc_1_SLOT23> {
2772 let IClass = 0b1100;
2774 let Inst{27-22} = 0b011010;
2775 let Inst{20-16} = s6{5-1};
2776 let Inst{12-8} = Rt;
2777 let Inst{7-6} = 0b11;
2779 let Inst{5} = s6{0};
2782 //===----------------------------------------------------------------------===//
2784 //===----------------------------------------------------------------------===//
2786 //===----------------------------------------------------------------------===//
2787 // MEMOP: Word, Half, Byte
2788 //===----------------------------------------------------------------------===//
2790 def MEMOPIMM : SDNodeXForm<imm, [{
2791 // Call the transformation function XformM5ToU5Imm to get the negative
2792 // immediate's positive counterpart.
2793 int32_t imm = N->getSExtValue();
2794 return XformM5ToU5Imm(imm);
2797 def MEMOPIMM_HALF : SDNodeXForm<imm, [{
2798 // -1 .. -31 represented as 65535..65515
2799 // assigning to a short restores our desired signed value.
2800 // Call the transformation function XformM5ToU5Imm to get the negative
2801 // immediate's positive counterpart.
2802 int16_t imm = N->getSExtValue();
2803 return XformM5ToU5Imm(imm);
2806 def MEMOPIMM_BYTE : SDNodeXForm<imm, [{
2807 // -1 .. -31 represented as 255..235
2808 // assigning to a char restores our desired signed value.
2809 // Call the transformation function XformM5ToU5Imm to get the negative
2810 // immediate's positive counterpart.
2811 int8_t imm = N->getSExtValue();
2812 return XformM5ToU5Imm(imm);
2815 def SETMEMIMM : SDNodeXForm<imm, [{
2816 // Return the bit position we will set [0-31].
2818 int32_t imm = N->getSExtValue();
2819 return XformMskToBitPosU5Imm(imm);
2822 def CLRMEMIMM : SDNodeXForm<imm, [{
2823 // Return the bit position we will clear [0-31].
2825 // we bit negate the value first
2826 int32_t imm = ~(N->getSExtValue());
2827 return XformMskToBitPosU5Imm(imm);
2830 def SETMEMIMM_SHORT : SDNodeXForm<imm, [{
2831 // Return the bit position we will set [0-15].
2833 int16_t imm = N->getSExtValue();
2834 return XformMskToBitPosU4Imm(imm);
2837 def CLRMEMIMM_SHORT : SDNodeXForm<imm, [{
2838 // Return the bit position we will clear [0-15].
2840 // we bit negate the value first
2841 int16_t imm = ~(N->getSExtValue());
2842 return XformMskToBitPosU4Imm(imm);
2845 def SETMEMIMM_BYTE : SDNodeXForm<imm, [{
2846 // Return the bit position we will set [0-7].
2848 int8_t imm = N->getSExtValue();
2849 return XformMskToBitPosU3Imm(imm);
2852 def CLRMEMIMM_BYTE : SDNodeXForm<imm, [{
2853 // Return the bit position we will clear [0-7].
2855 // we bit negate the value first
2856 int8_t imm = ~(N->getSExtValue());
2857 return XformMskToBitPosU3Imm(imm);
2860 //===----------------------------------------------------------------------===//
2861 // Template class for MemOp instructions with the register value.
2862 //===----------------------------------------------------------------------===//
2863 class MemOp_rr_base <string opc, bits<2> opcBits, Operand ImmOp,
2864 string memOp, bits<2> memOpBits> :
2866 (ins IntRegs:$base, ImmOp:$offset, IntRegs:$delta),
2867 opc#"($base+#$offset)"#memOp#"$delta",
2869 Requires<[UseMEMOP]> {
2874 bits<6> offsetBits; // memb - u6:0 , memh - u6:1, memw - u6:2
2876 let offsetBits = !if (!eq(opcBits, 0b00), offset{5-0},
2877 !if (!eq(opcBits, 0b01), offset{6-1},
2878 !if (!eq(opcBits, 0b10), offset{7-2},0)));
2880 let opExtentAlign = opcBits;
2881 let IClass = 0b0011;
2882 let Inst{27-24} = 0b1110;
2883 let Inst{22-21} = opcBits;
2884 let Inst{20-16} = base;
2886 let Inst{12-7} = offsetBits;
2887 let Inst{6-5} = memOpBits;
2888 let Inst{4-0} = delta;
2891 //===----------------------------------------------------------------------===//
2892 // Template class for MemOp instructions with the immediate value.
2893 //===----------------------------------------------------------------------===//
2894 class MemOp_ri_base <string opc, bits<2> opcBits, Operand ImmOp,
2895 string memOp, bits<2> memOpBits> :
2897 (ins IntRegs:$base, ImmOp:$offset, u5Imm:$delta),
2898 opc#"($base+#$offset)"#memOp#"#$delta"
2899 #!if(memOpBits{1},")", ""), // clrbit, setbit - include ')'
2901 Requires<[UseMEMOP]> {
2906 bits<6> offsetBits; // memb - u6:0 , memh - u6:1, memw - u6:2
2908 let offsetBits = !if (!eq(opcBits, 0b00), offset{5-0},
2909 !if (!eq(opcBits, 0b01), offset{6-1},
2910 !if (!eq(opcBits, 0b10), offset{7-2},0)));
2912 let opExtentAlign = opcBits;
2913 let IClass = 0b0011;
2914 let Inst{27-24} = 0b1111;
2915 let Inst{22-21} = opcBits;
2916 let Inst{20-16} = base;
2918 let Inst{12-7} = offsetBits;
2919 let Inst{6-5} = memOpBits;
2920 let Inst{4-0} = delta;
2923 // multiclass to define MemOp instructions with register operand.
2924 multiclass MemOp_rr<string opc, bits<2> opcBits, Operand ImmOp> {
2925 def L4_add#NAME : MemOp_rr_base <opc, opcBits, ImmOp, " += ", 0b00>; // add
2926 def L4_sub#NAME : MemOp_rr_base <opc, opcBits, ImmOp, " -= ", 0b01>; // sub
2927 def L4_and#NAME : MemOp_rr_base <opc, opcBits, ImmOp, " &= ", 0b10>; // and
2928 def L4_or#NAME : MemOp_rr_base <opc, opcBits, ImmOp, " |= ", 0b11>; // or
2931 // multiclass to define MemOp instructions with immediate Operand.
2932 multiclass MemOp_ri<string opc, bits<2> opcBits, Operand ImmOp> {
2933 def L4_iadd#NAME : MemOp_ri_base <opc, opcBits, ImmOp, " += ", 0b00 >;
2934 def L4_isub#NAME : MemOp_ri_base <opc, opcBits, ImmOp, " -= ", 0b01 >;
2935 def L4_iand#NAME : MemOp_ri_base<opc, opcBits, ImmOp, " = clrbit(", 0b10>;
2936 def L4_ior#NAME : MemOp_ri_base<opc, opcBits, ImmOp, " = setbit(", 0b11>;
2939 multiclass MemOp_base <string opc, bits<2> opcBits, Operand ImmOp> {
2940 defm _#NAME : MemOp_rr <opc, opcBits, ImmOp>;
2941 defm _#NAME : MemOp_ri <opc, opcBits, ImmOp>;
2944 // Define MemOp instructions.
2945 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0 in {
2946 let opExtentBits = 6, accessSize = ByteAccess in
2947 defm memopb_io : MemOp_base <"memb", 0b00, u6_0Ext>;
2949 let opExtentBits = 7, accessSize = HalfWordAccess in
2950 defm memoph_io : MemOp_base <"memh", 0b01, u6_1Ext>;
2952 let opExtentBits = 8, accessSize = WordAccess in
2953 defm memopw_io : MemOp_base <"memw", 0b10, u6_2Ext>;
2956 //===----------------------------------------------------------------------===//
2957 // Multiclass to define 'Def Pats' for ALU operations on the memory
2958 // Here value used for the ALU operation is an immediate value.
2959 // mem[bh](Rs+#0) += #U5
2960 // mem[bh](Rs+#u6) += #U5
2961 //===----------------------------------------------------------------------===//
2963 multiclass MemOpi_u5Pats <PatFrag ldOp, PatFrag stOp, PatLeaf ImmPred,
2964 InstHexagon MI, SDNode OpNode> {
2965 let AddedComplexity = 180 in
2966 def: Pat<(stOp (OpNode (ldOp IntRegs:$addr), u5ImmPred:$addend),
2968 (MI IntRegs:$addr, 0, u5ImmPred:$addend)>;
2970 let AddedComplexity = 190 in
2971 def: Pat<(stOp (OpNode (ldOp (add IntRegs:$base, ImmPred:$offset)),
2973 (add IntRegs:$base, ImmPred:$offset)),
2974 (MI IntRegs:$base, ImmPred:$offset, u5ImmPred:$addend)>;
2977 multiclass MemOpi_u5ALUOp<PatFrag ldOp, PatFrag stOp, PatLeaf ImmPred,
2978 InstHexagon addMI, InstHexagon subMI> {
2979 defm: MemOpi_u5Pats<ldOp, stOp, ImmPred, addMI, add>;
2980 defm: MemOpi_u5Pats<ldOp, stOp, ImmPred, subMI, sub>;
2983 multiclass MemOpi_u5ExtType<PatFrag ldOpByte, PatFrag ldOpHalf > {
2985 defm: MemOpi_u5ALUOp <ldOpHalf, truncstorei16, u31_1ImmPred,
2986 L4_iadd_memoph_io, L4_isub_memoph_io>;
2988 defm: MemOpi_u5ALUOp <ldOpByte, truncstorei8, u32ImmPred,
2989 L4_iadd_memopb_io, L4_isub_memopb_io>;
2992 let Predicates = [UseMEMOP] in {
2993 defm: MemOpi_u5ExtType<zextloadi8, zextloadi16>; // zero extend
2994 defm: MemOpi_u5ExtType<sextloadi8, sextloadi16>; // sign extend
2995 defm: MemOpi_u5ExtType<extloadi8, extloadi16>; // any extend
2998 defm: MemOpi_u5ALUOp <load, store, u30_2ImmPred, L4_iadd_memopw_io,
3002 //===----------------------------------------------------------------------===//
3003 // multiclass to define 'Def Pats' for ALU operations on the memory.
3004 // Here value used for the ALU operation is a negative value.
3005 // mem[bh](Rs+#0) += #m5
3006 // mem[bh](Rs+#u6) += #m5
3007 //===----------------------------------------------------------------------===//
3009 multiclass MemOpi_m5Pats <PatFrag ldOp, PatFrag stOp, PatLeaf ImmPred,
3010 PatLeaf immPred, SDNodeXForm xformFunc,
3012 let AddedComplexity = 190 in
3013 def: Pat<(stOp (add (ldOp IntRegs:$addr), immPred:$subend), IntRegs:$addr),
3014 (MI IntRegs:$addr, 0, (xformFunc immPred:$subend))>;
3016 let AddedComplexity = 195 in
3017 def: Pat<(stOp (add (ldOp (add IntRegs:$base, ImmPred:$offset)),
3019 (add IntRegs:$base, ImmPred:$offset)),
3020 (MI IntRegs:$base, ImmPred:$offset, (xformFunc immPred:$subend))>;
3023 multiclass MemOpi_m5ExtType<PatFrag ldOpByte, PatFrag ldOpHalf > {
3025 defm: MemOpi_m5Pats <ldOpHalf, truncstorei16, u31_1ImmPred, m5HImmPred,
3026 MEMOPIMM_HALF, L4_isub_memoph_io>;
3028 defm: MemOpi_m5Pats <ldOpByte, truncstorei8, u32ImmPred, m5BImmPred,
3029 MEMOPIMM_BYTE, L4_isub_memopb_io>;
3032 let Predicates = [UseMEMOP] in {
3033 defm: MemOpi_m5ExtType<zextloadi8, zextloadi16>; // zero extend
3034 defm: MemOpi_m5ExtType<sextloadi8, sextloadi16>; // sign extend
3035 defm: MemOpi_m5ExtType<extloadi8, extloadi16>; // any extend
3038 defm: MemOpi_m5Pats <load, store, u30_2ImmPred, m5ImmPred,
3039 MEMOPIMM, L4_isub_memopw_io>;
3042 //===----------------------------------------------------------------------===//
3043 // Multiclass to define 'def Pats' for bit operations on the memory.
3044 // mem[bhw](Rs+#0) = [clrbit|setbit](#U5)
3045 // mem[bhw](Rs+#u6) = [clrbit|setbit](#U5)
3046 //===----------------------------------------------------------------------===//
3048 multiclass MemOpi_bitPats <PatFrag ldOp, PatFrag stOp, PatLeaf immPred,
3049 PatLeaf extPred, SDNodeXForm xformFunc, InstHexagon MI,
3052 // mem[bhw](Rs+#u6:[012]) = [clrbit|setbit](#U5)
3053 let AddedComplexity = 250 in
3054 def: Pat<(stOp (OpNode (ldOp (add IntRegs:$base, extPred:$offset)),
3056 (add IntRegs:$base, extPred:$offset)),
3057 (MI IntRegs:$base, extPred:$offset, (xformFunc immPred:$bitend))>;
3059 // mem[bhw](Rs+#0) = [clrbit|setbit](#U5)
3060 let AddedComplexity = 225 in
3061 def: Pat<(stOp (OpNode (ldOp IntRegs:$addr), immPred:$bitend), IntRegs:$addr),
3062 (MI IntRegs:$addr, 0, (xformFunc immPred:$bitend))>;
3065 multiclass MemOpi_bitExtType<PatFrag ldOpByte, PatFrag ldOpHalf> {
3067 defm: MemOpi_bitPats<ldOpByte, truncstorei8, Clr3ImmPred, u32ImmPred,
3068 CLRMEMIMM_BYTE, L4_iand_memopb_io, and>;
3070 defm: MemOpi_bitPats<ldOpByte, truncstorei8, Set3ImmPred, u32ImmPred,
3071 SETMEMIMM_BYTE, L4_ior_memopb_io, or>;
3072 // Half Word - clrbit
3073 defm: MemOpi_bitPats<ldOpHalf, truncstorei16, Clr4ImmPred, u31_1ImmPred,
3074 CLRMEMIMM_SHORT, L4_iand_memoph_io, and>;
3075 // Half Word - setbit
3076 defm: MemOpi_bitPats<ldOpHalf, truncstorei16, Set4ImmPred, u31_1ImmPred,
3077 SETMEMIMM_SHORT, L4_ior_memoph_io, or>;
3080 let Predicates = [UseMEMOP] in {
3081 // mem[bh](Rs+#0) = [clrbit|setbit](#U5)
3082 // mem[bh](Rs+#u6:[01]) = [clrbit|setbit](#U5)
3083 defm: MemOpi_bitExtType<zextloadi8, zextloadi16>; // zero extend
3084 defm: MemOpi_bitExtType<sextloadi8, sextloadi16>; // sign extend
3085 defm: MemOpi_bitExtType<extloadi8, extloadi16>; // any extend
3087 // memw(Rs+#0) = [clrbit|setbit](#U5)
3088 // memw(Rs+#u6:2) = [clrbit|setbit](#U5)
3089 defm: MemOpi_bitPats<load, store, Clr5ImmPred, u30_2ImmPred, CLRMEMIMM,
3090 L4_iand_memopw_io, and>;
3091 defm: MemOpi_bitPats<load, store, Set5ImmPred, u30_2ImmPred, SETMEMIMM,
3092 L4_ior_memopw_io, or>;
3095 //===----------------------------------------------------------------------===//
3096 // Multiclass to define 'def Pats' for ALU operations on the memory
3097 // where addend is a register.
3098 // mem[bhw](Rs+#0) [+-&|]= Rt
3099 // mem[bhw](Rs+#U6:[012]) [+-&|]= Rt
3100 //===----------------------------------------------------------------------===//
3102 multiclass MemOpr_Pats <PatFrag ldOp, PatFrag stOp, PatLeaf extPred,
3103 InstHexagon MI, SDNode OpNode> {
3104 let AddedComplexity = 141 in
3105 // mem[bhw](Rs+#0) [+-&|]= Rt
3106 def: Pat<(stOp (OpNode (ldOp IntRegs:$addr), (i32 IntRegs:$addend)),
3108 (MI IntRegs:$addr, 0, (i32 IntRegs:$addend))>;
3110 // mem[bhw](Rs+#U6:[012]) [+-&|]= Rt
3111 let AddedComplexity = 150 in
3112 def: Pat<(stOp (OpNode (ldOp (add IntRegs:$base, extPred:$offset)),
3113 (i32 IntRegs:$orend)),
3114 (add IntRegs:$base, extPred:$offset)),
3115 (MI IntRegs:$base, extPred:$offset, (i32 IntRegs:$orend))>;
3118 multiclass MemOPr_ALUOp<PatFrag ldOp, PatFrag stOp, PatLeaf extPred,
3119 InstHexagon addMI, InstHexagon subMI,
3120 InstHexagon andMI, InstHexagon orMI> {
3121 defm: MemOpr_Pats <ldOp, stOp, extPred, addMI, add>;
3122 defm: MemOpr_Pats <ldOp, stOp, extPred, subMI, sub>;
3123 defm: MemOpr_Pats <ldOp, stOp, extPred, andMI, and>;
3124 defm: MemOpr_Pats <ldOp, stOp, extPred, orMI, or>;
3127 multiclass MemOPr_ExtType<PatFrag ldOpByte, PatFrag ldOpHalf > {
3129 defm: MemOPr_ALUOp <ldOpHalf, truncstorei16, u31_1ImmPred,
3130 L4_add_memoph_io, L4_sub_memoph_io,
3131 L4_and_memoph_io, L4_or_memoph_io>;
3133 defm: MemOPr_ALUOp <ldOpByte, truncstorei8, u32ImmPred,
3134 L4_add_memopb_io, L4_sub_memopb_io,
3135 L4_and_memopb_io, L4_or_memopb_io>;
3138 // Define 'def Pats' for MemOps with register addend.
3139 let Predicates = [UseMEMOP] in {
3141 defm: MemOPr_ExtType<zextloadi8, zextloadi16>; // zero extend
3142 defm: MemOPr_ExtType<sextloadi8, sextloadi16>; // sign extend
3143 defm: MemOPr_ExtType<extloadi8, extloadi16>; // any extend
3145 defm: MemOPr_ALUOp <load, store, u30_2ImmPred, L4_add_memopw_io,
3146 L4_sub_memopw_io, L4_and_memopw_io, L4_or_memopw_io>;
3149 //===----------------------------------------------------------------------===//
3151 //===----------------------------------------------------------------------===//
3153 // Hexagon V4 only supports these flavors of byte/half compare instructions:
3154 // EQ/GT/GTU. Other flavors like GE/GEU/LT/LTU/LE/LEU are not supported by
3155 // hardware. However, compiler can still implement these patterns through
3156 // appropriate patterns combinations based on current implemented patterns.
3157 // The implemented patterns are: EQ/GT/GTU.
3158 // Missing patterns are: GE/GEU/LT/LTU/LE/LEU.
3160 // Following instruction is not being extended as it results into the
3161 // incorrect code for negative numbers.
3162 // Pd=cmpb.eq(Rs,#u8)
3164 // p=!cmp.eq(r1,#s10)
3165 def C4_cmpneqi : T_CMP <"cmp.eq", 0b00, 1, s10Ext>;
3166 def C4_cmpltei : T_CMP <"cmp.gt", 0b01, 1, s10Ext>;
3167 def C4_cmplteui : T_CMP <"cmp.gtu", 0b10, 1, u9Ext>;
3169 def : T_CMP_pat <C4_cmpneqi, setne, s32ImmPred>;
3170 def : T_CMP_pat <C4_cmpltei, setle, s32ImmPred>;
3171 def : T_CMP_pat <C4_cmplteui, setule, u9ImmPred>;
3173 // rs <= rt -> !(rs > rt).
3175 def: Pat<(i1 (setle (i32 IntRegs:$src1), s32ImmPred:$src2)),
3176 (C2_not (C2_cmpgti IntRegs:$src1, s32ImmPred:$src2))>;
3177 // (C4_cmpltei IntRegs:$src1, s32ImmPred:$src2)>;
3179 // Map cmplt(Rs, Imm) -> !cmpgt(Rs, Imm-1).
3180 def: Pat<(i1 (setlt (i32 IntRegs:$src1), s32ImmPred:$src2)),
3181 (C4_cmpltei IntRegs:$src1, (DEC_CONST_SIGNED s32ImmPred:$src2))>;
3183 // rs != rt -> !(rs == rt).
3184 def: Pat<(i1 (setne (i32 IntRegs:$src1), s32ImmPred:$src2)),
3185 (C4_cmpneqi IntRegs:$src1, s32ImmPred:$src2)>;
3187 // SDNode for converting immediate C to C-1.
3188 def DEC_CONST_BYTE : SDNodeXForm<imm, [{
3189 // Return the byte immediate const-1 as an SDNode.
3190 int32_t imm = N->getSExtValue();
3191 return XformU7ToU7M1Imm(imm);
3195 // zext( setult ( and(Rs, 255), u8))
3196 // Use the isdigit transformation below
3198 // Generate code of the form 'C2_muxii(cmpbgtui(Rdd, C-1),0,1)'
3199 // for C code of the form r = ((c>='0') & (c<='9')) ? 1 : 0;.
3200 // The isdigit transformation relies on two 'clever' aspects:
3201 // 1) The data type is unsigned which allows us to eliminate a zero test after
3202 // biasing the expression by 48. We are depending on the representation of
3203 // the unsigned types, and semantics.
3204 // 2) The front end has converted <= 9 into < 10 on entry to LLVM
3207 // retval = ((c>='0') & (c<='9')) ? 1 : 0;
3208 // The code is transformed upstream of llvm into
3209 // retval = (c-48) < 10 ? 1 : 0;
3210 let AddedComplexity = 139 in
3211 def: Pat<(i32 (zext (i1 (setult (i32 (and (i32 IntRegs:$src1), 255)),
3212 u7StrictPosImmPred:$src2)))),
3213 (C2_muxii (A4_cmpbgtui IntRegs:$src1,
3214 (DEC_CONST_BYTE u7StrictPosImmPred:$src2)),
3217 //===----------------------------------------------------------------------===//
3219 //===----------------------------------------------------------------------===//
3221 //===----------------------------------------------------------------------===//
3222 // Multiclass for DeallocReturn
3223 //===----------------------------------------------------------------------===//
3224 class L4_RETURN<string mnemonic, bit isNot, bit isPredNew, bit isTak>
3225 : LD0Inst<(outs), (ins PredRegs:$src),
3226 !if(isNot, "if (!$src", "if ($src")#
3227 !if(isPredNew, ".new) ", ") ")#mnemonic#
3228 !if(isPredNew, #!if(isTak,":t", ":nt"),""),
3229 [], "", LD_tc_3or4stall_SLOT0> {
3232 let BaseOpcode = "L4_RETURN";
3233 let isPredicatedFalse = isNot;
3234 let isPredicatedNew = isPredNew;
3235 let isTaken = isTak;
3236 let IClass = 0b1001;
3238 let Inst{27-16} = 0b011000011110;
3240 let Inst{13} = isNot;
3241 let Inst{12} = isTak;
3242 let Inst{11} = isPredNew;
3244 let Inst{9-8} = src;
3245 let Inst{4-0} = 0b11110;
3248 // Produce all predicated forms, p, !p, p.new, !p.new, :t, :nt
3249 multiclass L4_RETURN_PRED<string mnemonic, bit PredNot> {
3250 let isPredicated = 1 in {
3251 def _#NAME# : L4_RETURN <mnemonic, PredNot, 0, 1>;
3252 def _#NAME#new_pnt : L4_RETURN <mnemonic, PredNot, 1, 0>;
3253 def _#NAME#new_pt : L4_RETURN <mnemonic, PredNot, 1, 1>;
3257 multiclass LD_MISC_L4_RETURN<string mnemonic> {
3258 let isBarrier = 1, isPredicable = 1 in
3259 def NAME : LD0Inst <(outs), (ins), mnemonic, [], "",
3260 LD_tc_3or4stall_SLOT0> {
3261 let BaseOpcode = "L4_RETURN";
3262 let IClass = 0b1001;
3263 let Inst{27-16} = 0b011000011110;
3264 let Inst{13-10} = 0b0000;
3265 let Inst{4-0} = 0b11110;
3267 defm t : L4_RETURN_PRED<mnemonic, 0 >;
3268 defm f : L4_RETURN_PRED<mnemonic, 1 >;
3271 let isReturn = 1, isTerminator = 1,
3272 Defs = [R29, R30, R31, PC], Uses = [R30], hasSideEffects = 0 in
3273 defm L4_return: LD_MISC_L4_RETURN <"dealloc_return">, PredNewRel;
3275 // Restore registers and dealloc return function call.
3276 let isCall = 1, isBarrier = 1, isReturn = 1, isTerminator = 1,
3277 Defs = [R29, R30, R31, PC], isPredicable = 0, isAsmParserOnly = 1 in {
3278 def RESTORE_DEALLOC_RET_JMP_V4 : T_JMP<"">;
3281 // Restore registers and dealloc frame before a tail call.
3282 let isCall = 1, Defs = [R29, R30, R31, PC], isAsmParserOnly = 1 in {
3283 def RESTORE_DEALLOC_BEFORE_TAILCALL_V4 : T_Call<"">, PredRel;
3286 // Save registers function call.
3287 let isCall = 1, Uses = [R29, R31], isAsmParserOnly = 1 in {
3288 def SAVE_REGISTERS_CALL_V4 : T_Call<"">, PredRel;
3291 //===----------------------------------------------------------------------===//
3292 // Template class for non predicated store instructions with
3293 // GP-Relative or absolute addressing.
3294 //===----------------------------------------------------------------------===//
3295 let hasSideEffects = 0, isPredicable = 1, isNVStorable = 1 in
3296 class T_StoreAbsGP <string mnemonic, RegisterClass RC, Operand ImmOp,
3297 bits<2>MajOp, Operand AddrOp, bit isAbs, bit isHalf>
3298 : STInst<(outs), (ins AddrOp:$addr, RC:$src),
3299 mnemonic # !if(isAbs, "(##", "(#")#"$addr) = $src"#!if(isHalf, ".h",""),
3300 [], "", V2LDST_tc_st_SLOT01> {
3303 bits<16> offsetBits;
3305 string ImmOpStr = !cast<string>(ImmOp);
3306 let offsetBits = !if (!eq(ImmOpStr, "u16_3Imm"), addr{18-3},
3307 !if (!eq(ImmOpStr, "u16_2Imm"), addr{17-2},
3308 !if (!eq(ImmOpStr, "u16_1Imm"), addr{16-1},
3309 /* u16_0Imm */ addr{15-0})));
3310 let IClass = 0b0100;
3312 let Inst{26-25} = offsetBits{15-14};
3314 let Inst{23-22} = MajOp;
3315 let Inst{21} = isHalf;
3316 let Inst{20-16} = offsetBits{13-9};
3317 let Inst{13} = offsetBits{8};
3318 let Inst{12-8} = src;
3319 let Inst{7-0} = offsetBits{7-0};
3322 //===----------------------------------------------------------------------===//
3323 // Template class for predicated store instructions with
3324 // GP-Relative or absolute addressing.
3325 //===----------------------------------------------------------------------===//
3326 let hasSideEffects = 0, isPredicated = 1, isNVStorable = 1, opExtentBits = 6,
3328 class T_StoreAbs_Pred <string mnemonic, RegisterClass RC, bits<2> MajOp,
3329 bit isHalf, bit isNot, bit isNew>
3330 : STInst<(outs), (ins PredRegs:$src1, u6Ext:$absaddr, RC: $src2),
3331 !if(isNot, "if (!$src1", "if ($src1")#!if(isNew, ".new) ",
3332 ") ")#mnemonic#"(#$absaddr) = $src2"#!if(isHalf, ".h",""),
3333 [], "", ST_tc_st_SLOT01>, AddrModeRel {
3338 let isPredicatedNew = isNew;
3339 let isPredicatedFalse = isNot;
3341 let IClass = 0b1010;
3343 let Inst{27-24} = 0b1111;
3344 let Inst{23-22} = MajOp;
3345 let Inst{21} = isHalf;
3346 let Inst{17-16} = absaddr{5-4};
3347 let Inst{13} = isNew;
3348 let Inst{12-8} = src2;
3350 let Inst{6-3} = absaddr{3-0};
3351 let Inst{2} = isNot;
3352 let Inst{1-0} = src1;
3355 //===----------------------------------------------------------------------===//
3356 // Template class for predicated store instructions with absolute addressing.
3357 //===----------------------------------------------------------------------===//
3358 class T_StoreAbs <string mnemonic, RegisterClass RC, Operand ImmOp,
3359 bits<2> MajOp, bit isHalf>
3360 : T_StoreAbsGP <mnemonic, RC, ImmOp, MajOp, u32Imm, 1, isHalf>,
3362 string ImmOpStr = !cast<string>(ImmOp);
3363 let opExtentBits = !if (!eq(ImmOpStr, "u16_3Imm"), 19,
3364 !if (!eq(ImmOpStr, "u16_2Imm"), 18,
3365 !if (!eq(ImmOpStr, "u16_1Imm"), 17,
3366 /* u16_0Imm */ 16)));
3368 let opExtentAlign = !if (!eq(ImmOpStr, "u16_3Imm"), 3,
3369 !if (!eq(ImmOpStr, "u16_2Imm"), 2,
3370 !if (!eq(ImmOpStr, "u16_1Imm"), 1,
3371 /* u16_0Imm */ 0)));
3374 //===----------------------------------------------------------------------===//
3375 // Multiclass for store instructions with absolute addressing.
3376 //===----------------------------------------------------------------------===//
3377 let addrMode = Absolute, isExtended = 1 in
3378 multiclass ST_Abs<string mnemonic, string CextOp, RegisterClass RC,
3379 Operand ImmOp, bits<2> MajOp, bit isHalf = 0> {
3380 let CextOpcode = CextOp, BaseOpcode = CextOp#_abs in {
3381 let opExtendable = 0, isPredicable = 1 in
3382 def S2_#NAME#abs : T_StoreAbs <mnemonic, RC, ImmOp, MajOp, isHalf>;
3385 def S4_p#NAME#t_abs : T_StoreAbs_Pred<mnemonic, RC, MajOp, isHalf, 0, 0>;
3386 def S4_p#NAME#f_abs : T_StoreAbs_Pred<mnemonic, RC, MajOp, isHalf, 1, 0>;
3389 def S4_p#NAME#tnew_abs : T_StoreAbs_Pred<mnemonic, RC, MajOp, isHalf, 0, 1>;
3390 def S4_p#NAME#fnew_abs : T_StoreAbs_Pred<mnemonic, RC, MajOp, isHalf, 1, 1>;
3394 //===----------------------------------------------------------------------===//
3395 // Template class for non predicated new-value store instructions with
3396 // GP-Relative or absolute addressing.
3397 //===----------------------------------------------------------------------===//
3398 let hasSideEffects = 0, isPredicable = 1, mayStore = 1, isNVStore = 1,
3399 isNewValue = 1, opNewValue = 1 in
3400 class T_StoreAbsGP_NV <string mnemonic, Operand ImmOp, bits<2>MajOp, bit isAbs>
3401 : NVInst_V4<(outs), (ins u32Imm:$addr, IntRegs:$src),
3402 mnemonic # !if(isAbs, "(##", "(#")#"$addr) = $src.new",
3403 [], "", V2LDST_tc_st_SLOT0> {
3406 bits<16> offsetBits;
3408 string ImmOpStr = !cast<string>(ImmOp);
3409 let offsetBits = !if (!eq(ImmOpStr, "u16_3Imm"), addr{18-3},
3410 !if (!eq(ImmOpStr, "u16_2Imm"), addr{17-2},
3411 !if (!eq(ImmOpStr, "u16_1Imm"), addr{16-1},
3412 /* u16_0Imm */ addr{15-0})));
3413 let IClass = 0b0100;
3416 let Inst{26-25} = offsetBits{15-14};
3417 let Inst{24-21} = 0b0101;
3418 let Inst{20-16} = offsetBits{13-9};
3419 let Inst{13} = offsetBits{8};
3420 let Inst{12-11} = MajOp;
3421 let Inst{10-8} = src;
3422 let Inst{7-0} = offsetBits{7-0};
3425 //===----------------------------------------------------------------------===//
3426 // Template class for predicated new-value store instructions with
3427 // absolute addressing.
3428 //===----------------------------------------------------------------------===//
3429 let hasSideEffects = 0, isPredicated = 1, mayStore = 1, isNVStore = 1,
3430 isNewValue = 1, opNewValue = 2, opExtentBits = 6, opExtendable = 1 in
3431 class T_StoreAbs_NV_Pred <string mnemonic, bits<2> MajOp, bit isNot, bit isNew>
3432 : NVInst_V4<(outs), (ins PredRegs:$src1, u6Ext:$absaddr, IntRegs:$src2),
3433 !if(isNot, "if (!$src1", "if ($src1")#!if(isNew, ".new) ",
3434 ") ")#mnemonic#"(#$absaddr) = $src2.new",
3435 [], "", ST_tc_st_SLOT0>, AddrModeRel {
3440 let isPredicatedNew = isNew;
3441 let isPredicatedFalse = isNot;
3443 let IClass = 0b1010;
3445 let Inst{27-24} = 0b1111;
3446 let Inst{23-21} = 0b101;
3447 let Inst{17-16} = absaddr{5-4};
3448 let Inst{13} = isNew;
3449 let Inst{12-11} = MajOp;
3450 let Inst{10-8} = src2;
3452 let Inst{6-3} = absaddr{3-0};
3453 let Inst{2} = isNot;
3454 let Inst{1-0} = src1;
3457 //===----------------------------------------------------------------------===//
3458 // Template class for non-predicated new-value store instructions with
3459 // absolute addressing.
3460 //===----------------------------------------------------------------------===//
3461 class T_StoreAbs_NV <string mnemonic, Operand ImmOp, bits<2> MajOp>
3462 : T_StoreAbsGP_NV <mnemonic, ImmOp, MajOp, 1>, AddrModeRel {
3464 string ImmOpStr = !cast<string>(ImmOp);
3465 let opExtentBits = !if (!eq(ImmOpStr, "u16_3Imm"), 19,
3466 !if (!eq(ImmOpStr, "u16_2Imm"), 18,
3467 !if (!eq(ImmOpStr, "u16_1Imm"), 17,
3468 /* u16_0Imm */ 16)));
3470 let opExtentAlign = !if (!eq(ImmOpStr, "u16_3Imm"), 3,
3471 !if (!eq(ImmOpStr, "u16_2Imm"), 2,
3472 !if (!eq(ImmOpStr, "u16_1Imm"), 1,
3473 /* u16_0Imm */ 0)));
3476 //===----------------------------------------------------------------------===//
3477 // Multiclass for new-value store instructions with absolute addressing.
3478 //===----------------------------------------------------------------------===//
3479 let addrMode = Absolute, isExtended = 1 in
3480 multiclass ST_Abs_NV <string mnemonic, string CextOp, Operand ImmOp,
3482 let CextOpcode = CextOp, BaseOpcode = CextOp#_abs in {
3483 let opExtendable = 0, isPredicable = 1 in
3484 def S2_#NAME#newabs : T_StoreAbs_NV <mnemonic, ImmOp, MajOp>;
3487 def S4_p#NAME#newt_abs : T_StoreAbs_NV_Pred <mnemonic, MajOp, 0, 0>;
3488 def S4_p#NAME#newf_abs : T_StoreAbs_NV_Pred <mnemonic, MajOp, 1, 0>;
3491 def S4_p#NAME#newtnew_abs : T_StoreAbs_NV_Pred <mnemonic, MajOp, 0, 1>;
3492 def S4_p#NAME#newfnew_abs : T_StoreAbs_NV_Pred <mnemonic, MajOp, 1, 1>;
3496 //===----------------------------------------------------------------------===//
3497 // Stores with absolute addressing
3498 //===----------------------------------------------------------------------===//
3499 let accessSize = ByteAccess in
3500 defm storerb : ST_Abs <"memb", "STrib", IntRegs, u16_0Imm, 0b00>,
3501 ST_Abs_NV <"memb", "STrib", u16_0Imm, 0b00>;
3503 let accessSize = HalfWordAccess in
3504 defm storerh : ST_Abs <"memh", "STrih", IntRegs, u16_1Imm, 0b01>,
3505 ST_Abs_NV <"memh", "STrih", u16_1Imm, 0b01>;
3507 let accessSize = WordAccess in
3508 defm storeri : ST_Abs <"memw", "STriw", IntRegs, u16_2Imm, 0b10>,
3509 ST_Abs_NV <"memw", "STriw", u16_2Imm, 0b10>;
3511 let isNVStorable = 0, accessSize = DoubleWordAccess in
3512 defm storerd : ST_Abs <"memd", "STrid", DoubleRegs, u16_3Imm, 0b11>;
3514 let isNVStorable = 0, accessSize = HalfWordAccess in
3515 defm storerf : ST_Abs <"memh", "STrif", IntRegs, u16_1Imm, 0b01, 1>;
3517 //===----------------------------------------------------------------------===//
3518 // GP-relative stores.
3519 // mem[bhwd](#global)=Rt
3520 // Once predicated, these instructions map to absolute addressing mode.
3521 // if ([!]Pv[.new]) mem[bhwd](##global)=Rt
3522 //===----------------------------------------------------------------------===//
3524 let isAsmParserOnly = 1 in
3525 class T_StoreGP <string mnemonic, string BaseOp, RegisterClass RC,
3526 Operand ImmOp, bits<2> MajOp, bit isHalf = 0>
3527 : T_StoreAbsGP <mnemonic, RC, ImmOp, MajOp, globaladdress, 0, isHalf> {
3528 // Set BaseOpcode same as absolute addressing instructions so that
3529 // non-predicated GP-Rel instructions can have relate with predicated
3530 // Absolute instruction.
3531 let BaseOpcode = BaseOp#_abs;
3534 let isAsmParserOnly = 1 in
3535 multiclass ST_GP <string mnemonic, string BaseOp, Operand ImmOp,
3536 bits<2> MajOp, bit isHalf = 0> {
3537 // Set BaseOpcode same as absolute addressing instructions so that
3538 // non-predicated GP-Rel instructions can have relate with predicated
3539 // Absolute instruction.
3540 let BaseOpcode = BaseOp#_abs in {
3541 def NAME#gp : T_StoreAbsGP <mnemonic, IntRegs, ImmOp, MajOp,
3542 globaladdress, 0, isHalf>;
3544 def NAME#newgp : T_StoreAbsGP_NV <mnemonic, ImmOp, MajOp, 0> ;
3548 let accessSize = ByteAccess in
3549 defm S2_storerb : ST_GP<"memb", "STrib", u16_0Imm, 0b00>, NewValueRel;
3551 let accessSize = HalfWordAccess in
3552 defm S2_storerh : ST_GP<"memh", "STrih", u16_1Imm, 0b01>, NewValueRel;
3554 let accessSize = WordAccess in
3555 defm S2_storeri : ST_GP<"memw", "STriw", u16_2Imm, 0b10>, NewValueRel;
3557 let isNVStorable = 0, accessSize = DoubleWordAccess in
3558 def S2_storerdgp : T_StoreGP <"memd", "STrid", DoubleRegs,
3559 u16_3Imm, 0b11>, PredNewRel;
3561 let isNVStorable = 0, accessSize = HalfWordAccess in
3562 def S2_storerfgp : T_StoreGP <"memh", "STrif", IntRegs,
3563 u16_1Imm, 0b01, 1>, PredNewRel;
3565 class Loada_pat<PatFrag Load, ValueType VT, PatFrag Addr, InstHexagon MI>
3566 : Pat<(VT (Load Addr:$addr)), (MI Addr:$addr)>;
3568 class Loadam_pat<PatFrag Load, ValueType VT, PatFrag Addr, PatFrag ValueMod,
3570 : Pat<(VT (Load Addr:$addr)), (ValueMod (MI Addr:$addr))>;
3572 class Storea_pat<PatFrag Store, PatFrag Value, PatFrag Addr, InstHexagon MI>
3573 : Pat<(Store Value:$val, Addr:$addr), (MI Addr:$addr, Value:$val)>;
3575 class Stoream_pat<PatFrag Store, PatFrag Value, PatFrag Addr, PatFrag ValueMod,
3577 : Pat<(Store Value:$val, Addr:$addr),
3578 (MI Addr:$addr, (ValueMod Value:$val))>;
3580 def: Storea_pat<SwapSt<atomic_store_8>, I32, addrgp, S2_storerbgp>;
3581 def: Storea_pat<SwapSt<atomic_store_16>, I32, addrgp, S2_storerhgp>;
3582 def: Storea_pat<SwapSt<atomic_store_32>, I32, addrgp, S2_storerigp>;
3583 def: Storea_pat<SwapSt<atomic_store_64>, I64, addrgp, S2_storerdgp>;
3585 let AddedComplexity = 100 in {
3586 def: Storea_pat<truncstorei8, I32, addrgp, S2_storerbgp>;
3587 def: Storea_pat<truncstorei16, I32, addrgp, S2_storerhgp>;
3588 def: Storea_pat<store, I32, addrgp, S2_storerigp>;
3589 def: Storea_pat<store, I64, addrgp, S2_storerdgp>;
3591 // Map from "i1 = constant<-1>; memw(CONST32(#foo)) = i1"
3592 // to "r0 = 1; memw(#foo) = r0"
3593 let AddedComplexity = 100 in
3594 def: Pat<(store (i1 -1), (HexagonCONST32_GP tglobaladdr:$global)),
3595 (S2_storerbgp tglobaladdr:$global, (A2_tfrsi 1))>;
3598 //===----------------------------------------------------------------------===//
3599 // Template class for non predicated load instructions with
3600 // absolute addressing mode.
3601 //===----------------------------------------------------------------------===//
3602 let isPredicable = 1, hasSideEffects = 0 in
3603 class T_LoadAbsGP <string mnemonic, RegisterClass RC, Operand ImmOp,
3604 bits<3> MajOp, Operand AddrOp, bit isAbs>
3605 : LDInst <(outs RC:$dst), (ins AddrOp:$addr),
3606 "$dst = "#mnemonic# !if(isAbs, "(##", "(#")#"$addr)",
3607 [], "", V2LDST_tc_ld_SLOT01> {
3610 bits<16> offsetBits;
3612 string ImmOpStr = !cast<string>(ImmOp);
3613 let offsetBits = !if (!eq(ImmOpStr, "u16_3Imm"), addr{18-3},
3614 !if (!eq(ImmOpStr, "u16_2Imm"), addr{17-2},
3615 !if (!eq(ImmOpStr, "u16_1Imm"), addr{16-1},
3616 /* u16_0Imm */ addr{15-0})));
3618 let IClass = 0b0100;
3621 let Inst{26-25} = offsetBits{15-14};
3623 let Inst{23-21} = MajOp;
3624 let Inst{20-16} = offsetBits{13-9};
3625 let Inst{13-5} = offsetBits{8-0};
3626 let Inst{4-0} = dst;
3629 class T_LoadAbs <string mnemonic, RegisterClass RC, Operand ImmOp,
3631 : T_LoadAbsGP <mnemonic, RC, ImmOp, MajOp, u32Imm, 1>, AddrModeRel {
3633 string ImmOpStr = !cast<string>(ImmOp);
3634 let opExtentBits = !if (!eq(ImmOpStr, "u16_3Imm"), 19,
3635 !if (!eq(ImmOpStr, "u16_2Imm"), 18,
3636 !if (!eq(ImmOpStr, "u16_1Imm"), 17,
3637 /* u16_0Imm */ 16)));
3639 let opExtentAlign = !if (!eq(ImmOpStr, "u16_3Imm"), 3,
3640 !if (!eq(ImmOpStr, "u16_2Imm"), 2,
3641 !if (!eq(ImmOpStr, "u16_1Imm"), 1,
3642 /* u16_0Imm */ 0)));
3645 //===----------------------------------------------------------------------===//
3646 // Template class for predicated load instructions with
3647 // absolute addressing mode.
3648 //===----------------------------------------------------------------------===//
3649 let isPredicated = 1, opExtentBits = 6, opExtendable = 2 in
3650 class T_LoadAbs_Pred <string mnemonic, RegisterClass RC, bits<3> MajOp,
3651 bit isPredNot, bit isPredNew>
3652 : LDInst <(outs RC:$dst), (ins PredRegs:$src1, u6Ext:$absaddr),
3653 !if(isPredNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
3654 ") ")#"$dst = "#mnemonic#"(#$absaddr)">, AddrModeRel {
3659 let isPredicatedNew = isPredNew;
3660 let isPredicatedFalse = isPredNot;
3661 let hasNewValue = !if (!eq(!cast<string>(RC), "DoubleRegs"), 0, 1);
3663 let IClass = 0b1001;
3665 let Inst{27-24} = 0b1111;
3666 let Inst{23-21} = MajOp;
3667 let Inst{20-16} = absaddr{5-1};
3669 let Inst{12} = isPredNew;
3670 let Inst{11} = isPredNot;
3671 let Inst{10-9} = src1;
3672 let Inst{8} = absaddr{0};
3674 let Inst{4-0} = dst;
3677 //===----------------------------------------------------------------------===//
3678 // Multiclass for the load instructions with absolute addressing mode.
3679 //===----------------------------------------------------------------------===//
3680 multiclass LD_Abs_Pred<string mnemonic, RegisterClass RC, bits<3> MajOp,
3682 def _abs : T_LoadAbs_Pred <mnemonic, RC, MajOp, PredNot, 0>;
3684 def new_abs : T_LoadAbs_Pred <mnemonic, RC, MajOp, PredNot, 1>;
3687 let addrMode = Absolute, isExtended = 1 in
3688 multiclass LD_Abs<string mnemonic, string CextOp, RegisterClass RC,
3689 Operand ImmOp, bits<3> MajOp> {
3690 let CextOpcode = CextOp, BaseOpcode = CextOp#_abs in {
3691 let opExtendable = 1, isPredicable = 1 in
3692 def L4_#NAME#_abs: T_LoadAbs <mnemonic, RC, ImmOp, MajOp>;
3695 defm L4_p#NAME#t : LD_Abs_Pred<mnemonic, RC, MajOp, 0>;
3696 defm L4_p#NAME#f : LD_Abs_Pred<mnemonic, RC, MajOp, 1>;
3700 let accessSize = ByteAccess, hasNewValue = 1 in {
3701 defm loadrb : LD_Abs<"memb", "LDrib", IntRegs, u16_0Imm, 0b000>;
3702 defm loadrub : LD_Abs<"memub", "LDriub", IntRegs, u16_0Imm, 0b001>;
3705 let accessSize = HalfWordAccess, hasNewValue = 1 in {
3706 defm loadrh : LD_Abs<"memh", "LDrih", IntRegs, u16_1Imm, 0b010>;
3707 defm loadruh : LD_Abs<"memuh", "LDriuh", IntRegs, u16_1Imm, 0b011>;
3710 let accessSize = WordAccess, hasNewValue = 1 in
3711 defm loadri : LD_Abs<"memw", "LDriw", IntRegs, u16_2Imm, 0b100>;
3713 let accessSize = DoubleWordAccess in
3714 defm loadrd : LD_Abs<"memd", "LDrid", DoubleRegs, u16_3Imm, 0b110>;
3716 //===----------------------------------------------------------------------===//
3717 // multiclass for load instructions with GP-relative addressing mode.
3718 // Rx=mem[bhwd](##global)
3719 // Once predicated, these instructions map to absolute addressing mode.
3720 // if ([!]Pv[.new]) Rx=mem[bhwd](##global)
3721 //===----------------------------------------------------------------------===//
3723 let isAsmParserOnly = 1 in
3724 class T_LoadGP <string mnemonic, string BaseOp, RegisterClass RC, Operand ImmOp,
3726 : T_LoadAbsGP <mnemonic, RC, ImmOp, MajOp, globaladdress, 0>, PredNewRel {
3727 let BaseOpcode = BaseOp#_abs;
3730 let accessSize = ByteAccess, hasNewValue = 1 in {
3731 def L2_loadrbgp : T_LoadGP<"memb", "LDrib", IntRegs, u16_0Imm, 0b000>;
3732 def L2_loadrubgp : T_LoadGP<"memub", "LDriub", IntRegs, u16_0Imm, 0b001>;
3735 let accessSize = HalfWordAccess, hasNewValue = 1 in {
3736 def L2_loadrhgp : T_LoadGP<"memh", "LDrih", IntRegs, u16_1Imm, 0b010>;
3737 def L2_loadruhgp : T_LoadGP<"memuh", "LDriuh", IntRegs, u16_1Imm, 0b011>;
3740 let accessSize = WordAccess, hasNewValue = 1 in
3741 def L2_loadrigp : T_LoadGP<"memw", "LDriw", IntRegs, u16_2Imm, 0b100>;
3743 let accessSize = DoubleWordAccess in
3744 def L2_loadrdgp : T_LoadGP<"memd", "LDrid", DoubleRegs, u16_3Imm, 0b110>;
3746 def: Loada_pat<atomic_load_8, i32, addrgp, L2_loadrubgp>;
3747 def: Loada_pat<atomic_load_16, i32, addrgp, L2_loadruhgp>;
3748 def: Loada_pat<atomic_load_32, i32, addrgp, L2_loadrigp>;
3749 def: Loada_pat<atomic_load_64, i64, addrgp, L2_loadrdgp>;
3751 // Map from Pd = load(globaladdress) -> Rd = memb(globaladdress), Pd = Rd
3752 def: Loadam_pat<load, i1, addrga, I32toI1, L4_loadrub_abs>;
3753 def: Loadam_pat<load, i1, addrgp, I32toI1, L2_loadrubgp>;
3755 def: Stoream_pat<store, I1, addrga, I1toI32, S2_storerbabs>;
3756 def: Stoream_pat<store, I1, addrgp, I1toI32, S2_storerbgp>;
3758 // Map from load(globaladdress) -> mem[u][bhwd](#foo)
3759 class LoadGP_pats <PatFrag ldOp, InstHexagon MI, ValueType VT = i32>
3760 : Pat <(VT (ldOp (HexagonCONST32_GP tglobaladdr:$global))),
3761 (VT (MI tglobaladdr:$global))>;
3763 let AddedComplexity = 100 in {
3764 def: LoadGP_pats <extloadi8, L2_loadrbgp>;
3765 def: LoadGP_pats <sextloadi8, L2_loadrbgp>;
3766 def: LoadGP_pats <zextloadi8, L2_loadrubgp>;
3767 def: LoadGP_pats <extloadi16, L2_loadrhgp>;
3768 def: LoadGP_pats <sextloadi16, L2_loadrhgp>;
3769 def: LoadGP_pats <zextloadi16, L2_loadruhgp>;
3770 def: LoadGP_pats <load, L2_loadrigp>;
3771 def: LoadGP_pats <load, L2_loadrdgp, i64>;
3774 // When the Interprocedural Global Variable optimizer realizes that a certain
3775 // global variable takes only two constant values, it shrinks the global to
3776 // a boolean. Catch those loads here in the following 3 patterns.
3777 let AddedComplexity = 100 in {
3778 def: LoadGP_pats <extloadi1, L2_loadrubgp>;
3779 def: LoadGP_pats <zextloadi1, L2_loadrubgp>;
3782 // Transfer global address into a register
3783 def: Pat<(HexagonCONST32 tglobaladdr:$Rs), (A2_tfrsi s16Ext:$Rs)>;
3784 def: Pat<(HexagonCONST32_GP tblockaddress:$Rs), (A2_tfrsi s16Ext:$Rs)>;
3785 def: Pat<(HexagonCONST32_GP tglobaladdr:$Rs), (A2_tfrsi s16Ext:$Rs)>;
3787 def: Pat<(i64 (ctlz I64:$src1)), (Zext64 (S2_cl0p I64:$src1))>;
3788 def: Pat<(i64 (cttz I64:$src1)), (Zext64 (S2_ct0p I64:$src1))>;
3790 let AddedComplexity = 30 in {
3791 def: Storea_pat<truncstorei8, I32, u32ImmPred, S2_storerbabs>;
3792 def: Storea_pat<truncstorei16, I32, u32ImmPred, S2_storerhabs>;
3793 def: Storea_pat<store, I32, u32ImmPred, S2_storeriabs>;
3796 let AddedComplexity = 30 in {
3797 def: Loada_pat<load, i32, u32ImmPred, L4_loadri_abs>;
3798 def: Loada_pat<sextloadi8, i32, u32ImmPred, L4_loadrb_abs>;
3799 def: Loada_pat<zextloadi8, i32, u32ImmPred, L4_loadrub_abs>;
3800 def: Loada_pat<sextloadi16, i32, u32ImmPred, L4_loadrh_abs>;
3801 def: Loada_pat<zextloadi16, i32, u32ImmPred, L4_loadruh_abs>;
3804 // Indexed store word - global address.
3805 // memw(Rs+#u6:2)=#S8
3806 let AddedComplexity = 100 in
3807 def: Storex_add_pat<store, addrga, u6_2ImmPred, S4_storeiri_io>;
3809 // Load from a global address that has only one use in the current basic block.
3810 let AddedComplexity = 100 in {
3811 def: Loada_pat<extloadi8, i32, addrga, L4_loadrub_abs>;
3812 def: Loada_pat<sextloadi8, i32, addrga, L4_loadrb_abs>;
3813 def: Loada_pat<zextloadi8, i32, addrga, L4_loadrub_abs>;
3815 def: Loada_pat<extloadi16, i32, addrga, L4_loadruh_abs>;
3816 def: Loada_pat<sextloadi16, i32, addrga, L4_loadrh_abs>;
3817 def: Loada_pat<zextloadi16, i32, addrga, L4_loadruh_abs>;
3819 def: Loada_pat<load, i32, addrga, L4_loadri_abs>;
3820 def: Loada_pat<load, i64, addrga, L4_loadrd_abs>;
3823 // Store to a global address that has only one use in the current basic block.
3824 let AddedComplexity = 100 in {
3825 def: Storea_pat<truncstorei8, I32, addrga, S2_storerbabs>;
3826 def: Storea_pat<truncstorei16, I32, addrga, S2_storerhabs>;
3827 def: Storea_pat<store, I32, addrga, S2_storeriabs>;
3828 def: Storea_pat<store, I64, addrga, S2_storerdabs>;
3830 def: Stoream_pat<truncstorei32, I64, addrga, LoReg, S2_storeriabs>;
3833 // Map from Pd = load(globaladdress) -> Rd = memb(globaladdress), Pd = Rd
3834 let AddedComplexity = 100 in
3835 def : Pat <(i1 (load (HexagonCONST32_GP tglobaladdr:$global))),
3836 (i1 (C2_tfrrp (i32 (L2_loadrbgp tglobaladdr:$global))))>;
3838 // Transfer global address into a register
3839 let isExtended = 1, opExtendable = 1, AddedComplexity=50, isMoveImm = 1,
3840 isAsCheapAsAMove = 1, isReMaterializable = 1, isCodeGenOnly = 1 in
3841 def TFRI_V4 : ALU32_ri<(outs IntRegs:$dst), (ins s16Ext:$src1),
3843 [(set IntRegs:$dst, (HexagonCONST32 tglobaladdr:$src1))]>;
3845 // Transfer a block address into a register
3846 def : Pat<(HexagonCONST32_GP tblockaddress:$src1),
3847 (TFRI_V4 tblockaddress:$src1)>;
3849 let AddedComplexity = 50 in
3850 def : Pat<(HexagonCONST32_GP tglobaladdr:$src1),
3851 (TFRI_V4 tglobaladdr:$src1)>;
3853 // i8/i16/i32 -> i64 loads
3854 // We need a complexity of 120 here to override preceding handling of
3856 let AddedComplexity = 120 in {
3857 def: Loadam_pat<extloadi8, i64, addrga, Zext64, L4_loadrub_abs>;
3858 def: Loadam_pat<sextloadi8, i64, addrga, Sext64, L4_loadrb_abs>;
3859 def: Loadam_pat<zextloadi8, i64, addrga, Zext64, L4_loadrub_abs>;
3861 def: Loadam_pat<extloadi16, i64, addrga, Zext64, L4_loadruh_abs>;
3862 def: Loadam_pat<sextloadi16, i64, addrga, Sext64, L4_loadrh_abs>;
3863 def: Loadam_pat<zextloadi16, i64, addrga, Zext64, L4_loadruh_abs>;
3865 def: Loadam_pat<extloadi32, i64, addrga, Zext64, L4_loadri_abs>;
3866 def: Loadam_pat<sextloadi32, i64, addrga, Sext64, L4_loadri_abs>;
3867 def: Loadam_pat<zextloadi32, i64, addrga, Zext64, L4_loadri_abs>;
3870 let AddedComplexity = 100 in {
3871 def: Loada_pat<extloadi8, i32, addrgp, L4_loadrub_abs>;
3872 def: Loada_pat<sextloadi8, i32, addrgp, L4_loadrb_abs>;
3873 def: Loada_pat<zextloadi8, i32, addrgp, L4_loadrub_abs>;
3875 def: Loada_pat<extloadi16, i32, addrgp, L4_loadruh_abs>;
3876 def: Loada_pat<sextloadi16, i32, addrgp, L4_loadrh_abs>;
3877 def: Loada_pat<zextloadi16, i32, addrgp, L4_loadruh_abs>;
3879 def: Loada_pat<load, i32, addrgp, L4_loadri_abs>;
3880 def: Loada_pat<load, i64, addrgp, L4_loadrd_abs>;
3883 let AddedComplexity = 100 in {
3884 def: Storea_pat<truncstorei8, I32, addrgp, S2_storerbabs>;
3885 def: Storea_pat<truncstorei16, I32, addrgp, S2_storerhabs>;
3886 def: Storea_pat<store, I32, addrgp, S2_storeriabs>;
3887 def: Storea_pat<store, I64, addrgp, S2_storerdabs>;
3890 def: Loada_pat<atomic_load_8, i32, addrgp, L4_loadrub_abs>;
3891 def: Loada_pat<atomic_load_16, i32, addrgp, L4_loadruh_abs>;
3892 def: Loada_pat<atomic_load_32, i32, addrgp, L4_loadri_abs>;
3893 def: Loada_pat<atomic_load_64, i64, addrgp, L4_loadrd_abs>;
3895 def: Storea_pat<SwapSt<atomic_store_8>, I32, addrgp, S2_storerbabs>;
3896 def: Storea_pat<SwapSt<atomic_store_16>, I32, addrgp, S2_storerhabs>;
3897 def: Storea_pat<SwapSt<atomic_store_32>, I32, addrgp, S2_storeriabs>;
3898 def: Storea_pat<SwapSt<atomic_store_64>, I64, addrgp, S2_storerdabs>;
3900 let Constraints = "@earlyclobber $dst" in
3901 def Insert4 : PseudoM<(outs DoubleRegs:$dst), (ins IntRegs:$a, IntRegs:$b,
3902 IntRegs:$c, IntRegs:$d),
3903 ".error \"Should never try to emit Insert4\"",
3904 [(set (i64 DoubleRegs:$dst),
3905 (or (or (or (shl (i64 (zext (i32 (and (i32 IntRegs:$b), (i32 65535))))),
3907 (i64 (zext (i32 (and (i32 IntRegs:$a), (i32 65535)))))),
3908 (shl (i64 (anyext (i32 (and (i32 IntRegs:$c), (i32 65535))))),
3910 (shl (i64 (anyext (i32 IntRegs:$d))), (i32 48))))]>;
3912 //===----------------------------------------------------------------------===//
3913 // :raw for of boundscheck:hi:lo insns
3914 //===----------------------------------------------------------------------===//
3916 // A4_boundscheck_lo: Detect if a register is within bounds.
3917 let hasSideEffects = 0 in
3918 def A4_boundscheck_lo: ALU64Inst <
3919 (outs PredRegs:$Pd),
3920 (ins DoubleRegs:$Rss, DoubleRegs:$Rtt),
3921 "$Pd = boundscheck($Rss, $Rtt):raw:lo"> {
3926 let IClass = 0b1101;
3928 let Inst{27-23} = 0b00100;
3930 let Inst{7-5} = 0b100;
3932 let Inst{20-16} = Rss;
3933 let Inst{12-8} = Rtt;
3936 // A4_boundscheck_hi: Detect if a register is within bounds.
3937 let hasSideEffects = 0 in
3938 def A4_boundscheck_hi: ALU64Inst <
3939 (outs PredRegs:$Pd),
3940 (ins DoubleRegs:$Rss, DoubleRegs:$Rtt),
3941 "$Pd = boundscheck($Rss, $Rtt):raw:hi"> {
3946 let IClass = 0b1101;
3948 let Inst{27-23} = 0b00100;
3950 let Inst{7-5} = 0b101;
3952 let Inst{20-16} = Rss;
3953 let Inst{12-8} = Rtt;
3956 let hasSideEffects = 0, isAsmParserOnly = 1 in
3957 def A4_boundscheck : MInst <
3958 (outs PredRegs:$Pd), (ins IntRegs:$Rs, DoubleRegs:$Rtt),
3959 "$Pd=boundscheck($Rs,$Rtt)">;
3961 // A4_tlbmatch: Detect if a VA/ASID matches a TLB entry.
3962 let isPredicateLate = 1, hasSideEffects = 0 in
3963 def A4_tlbmatch : ALU64Inst<(outs PredRegs:$Pd),
3964 (ins DoubleRegs:$Rs, IntRegs:$Rt),
3965 "$Pd = tlbmatch($Rs, $Rt)",
3966 [], "", ALU64_tc_2early_SLOT23> {
3971 let IClass = 0b1101;
3972 let Inst{27-23} = 0b00100;
3973 let Inst{20-16} = Rs;
3975 let Inst{12-8} = Rt;
3976 let Inst{7-5} = 0b011;
3980 // We need custom lowering of ISD::PREFETCH into HexagonISD::DCFETCH
3981 // because the SDNode ISD::PREFETCH has properties MayLoad and MayStore.
3982 // We don't really want either one here.
3983 def SDTHexagonDCFETCH : SDTypeProfile<0, 2, [SDTCisPtrTy<0>,SDTCisInt<1>]>;
3984 def HexagonDCFETCH : SDNode<"HexagonISD::DCFETCH", SDTHexagonDCFETCH,
3987 // Use LD0Inst for dcfetch, but set "mayLoad" to 0 because this doesn't
3988 // really do a load.
3989 let hasSideEffects = 1, mayLoad = 0 in
3990 def Y2_dcfetchbo : LD0Inst<(outs), (ins IntRegs:$Rs, u11_3Imm:$u11_3),
3991 "dcfetch($Rs + #$u11_3)",
3992 [(HexagonDCFETCH IntRegs:$Rs, u11_3ImmPred:$u11_3)],
3993 "", LD_tc_ld_SLOT0> {
3997 let IClass = 0b1001;
3998 let Inst{27-21} = 0b0100000;
3999 let Inst{20-16} = Rs;
4001 let Inst{10-0} = u11_3{13-3};
4004 //===----------------------------------------------------------------------===//
4005 // Compound instructions
4006 //===----------------------------------------------------------------------===//
4008 let isBranch = 1, hasSideEffects = 0, isExtentSigned = 1,
4009 isPredicated = 1, isPredicatedNew = 1, isExtendable = 1,
4010 opExtentBits = 11, opExtentAlign = 2, opExtendable = 1,
4012 class CJInst_tstbit_R0<string px, bit np, string tnt>
4013 : InstHexagon<(outs), (ins IntRegs:$Rs, brtarget:$r9_2),
4014 ""#px#" = tstbit($Rs, #0); if ("
4015 #!if(np, "!","")#""#px#".new) jump:"#tnt#" $r9_2",
4016 [], "", COMPOUND, TypeCOMPOUND>, OpcodeHexagon {
4021 let isPredicatedFalse = np;
4022 // tnt: Taken/Not Taken
4023 let isBrTaken = !if (!eq(tnt, "t"), "true", "false");
4024 let isTaken = !if (!eq(tnt, "t"), 1, 0);
4026 let IClass = 0b0001;
4027 let Inst{27-26} = 0b00;
4028 let Inst{25} = !if (!eq(px, "!p1"), 1,
4029 !if (!eq(px, "p1"), 1, 0));
4030 let Inst{24-23} = 0b11;
4032 let Inst{21-20} = r9_2{10-9};
4033 let Inst{19-16} = Rs;
4034 let Inst{13} = !if (!eq(tnt, "t"), 1, 0);
4035 let Inst{9-8} = 0b11;
4036 let Inst{7-1} = r9_2{8-2};
4039 let Defs = [PC, P0], Uses = [P0] in {
4040 def J4_tstbit0_tp0_jump_nt : CJInst_tstbit_R0<"p0", 0, "nt">;
4041 def J4_tstbit0_tp0_jump_t : CJInst_tstbit_R0<"p0", 0, "t">;
4042 def J4_tstbit0_fp0_jump_nt : CJInst_tstbit_R0<"p0", 1, "nt">;
4043 def J4_tstbit0_fp0_jump_t : CJInst_tstbit_R0<"p0", 1, "t">;
4046 let Defs = [PC, P1], Uses = [P1] in {
4047 def J4_tstbit0_tp1_jump_nt : CJInst_tstbit_R0<"p1", 0, "nt">;
4048 def J4_tstbit0_tp1_jump_t : CJInst_tstbit_R0<"p1", 0, "t">;
4049 def J4_tstbit0_fp1_jump_nt : CJInst_tstbit_R0<"p1", 1, "nt">;
4050 def J4_tstbit0_fp1_jump_t : CJInst_tstbit_R0<"p1", 1, "t">;
4054 let isBranch = 1, hasSideEffects = 0,
4055 isExtentSigned = 1, isPredicated = 1, isPredicatedNew = 1,
4056 isExtendable = 1, opExtentBits = 11, opExtentAlign = 2,
4057 opExtendable = 2, isTerminator = 1 in
4058 class CJInst_RR<string px, string op, bit np, string tnt>
4059 : InstHexagon<(outs), (ins IntRegs:$Rs, IntRegs:$Rt, brtarget:$r9_2),
4060 ""#px#" = cmp."#op#"($Rs, $Rt); if ("
4061 #!if(np, "!","")#""#px#".new) jump:"#tnt#" $r9_2",
4062 [], "", COMPOUND, TypeCOMPOUND>, OpcodeHexagon {
4068 let isPredicatedFalse = np;
4069 // tnt: Taken/Not Taken
4070 let isBrTaken = !if (!eq(tnt, "t"), "true", "false");
4071 let isTaken = !if (!eq(tnt, "t"), 1, 0);
4073 let IClass = 0b0001;
4074 let Inst{27-23} = !if (!eq(op, "eq"), 0b01000,
4075 !if (!eq(op, "gt"), 0b01001,
4076 !if (!eq(op, "gtu"), 0b01010, 0)));
4078 let Inst{21-20} = r9_2{10-9};
4079 let Inst{19-16} = Rs;
4080 let Inst{13} = !if (!eq(tnt, "t"), 1, 0);
4081 // px: Predicate reg 0/1
4082 let Inst{12} = !if (!eq(px, "!p1"), 1,
4083 !if (!eq(px, "p1"), 1, 0));
4084 let Inst{11-8} = Rt;
4085 let Inst{7-1} = r9_2{8-2};
4088 // P[10] taken/not taken.
4089 multiclass T_tnt_CJInst_RR<string op, bit np> {
4090 let Defs = [PC, P0], Uses = [P0] in {
4091 def NAME#p0_jump_nt : CJInst_RR<"p0", op, np, "nt">;
4092 def NAME#p0_jump_t : CJInst_RR<"p0", op, np, "t">;
4094 let Defs = [PC, P1], Uses = [P1] in {
4095 def NAME#p1_jump_nt : CJInst_RR<"p1", op, np, "nt">;
4096 def NAME#p1_jump_t : CJInst_RR<"p1", op, np, "t">;
4099 // Predicate / !Predicate
4100 multiclass T_pnp_CJInst_RR<string op>{
4101 defm J4_cmp#NAME#_t : T_tnt_CJInst_RR<op, 0>;
4102 defm J4_cmp#NAME#_f : T_tnt_CJInst_RR<op, 1>;
4104 // TypeCJ Instructions compare RR and jump
4105 defm eq : T_pnp_CJInst_RR<"eq">;
4106 defm gt : T_pnp_CJInst_RR<"gt">;
4107 defm gtu : T_pnp_CJInst_RR<"gtu">;
4109 let isBranch = 1, hasSideEffects = 0, isExtentSigned = 1,
4110 isPredicated = 1, isPredicatedNew = 1, isExtendable = 1, opExtentBits = 11,
4111 opExtentAlign = 2, opExtendable = 2, isTerminator = 1 in
4112 class CJInst_RU5<string px, string op, bit np, string tnt>
4113 : InstHexagon<(outs), (ins IntRegs:$Rs, u5Imm:$U5, brtarget:$r9_2),
4114 ""#px#" = cmp."#op#"($Rs, #$U5); if ("
4115 #!if(np, "!","")#""#px#".new) jump:"#tnt#" $r9_2",
4116 [], "", COMPOUND, TypeCOMPOUND>, OpcodeHexagon {
4122 let isPredicatedFalse = np;
4123 // tnt: Taken/Not Taken
4124 let isBrTaken = !if (!eq(tnt, "t"), "true", "false");
4125 let isTaken = !if (!eq(tnt, "t"), 1, 0);
4127 let IClass = 0b0001;
4128 let Inst{27-26} = 0b00;
4129 // px: Predicate reg 0/1
4130 let Inst{25} = !if (!eq(px, "!p1"), 1,
4131 !if (!eq(px, "p1"), 1, 0));
4132 let Inst{24-23} = !if (!eq(op, "eq"), 0b00,
4133 !if (!eq(op, "gt"), 0b01,
4134 !if (!eq(op, "gtu"), 0b10, 0)));
4136 let Inst{21-20} = r9_2{10-9};
4137 let Inst{19-16} = Rs;
4138 let Inst{13} = !if (!eq(tnt, "t"), 1, 0);
4139 let Inst{12-8} = U5;
4140 let Inst{7-1} = r9_2{8-2};
4142 // P[10] taken/not taken.
4143 multiclass T_tnt_CJInst_RU5<string op, bit np> {
4144 let Defs = [PC, P0], Uses = [P0] in {
4145 def NAME#p0_jump_nt : CJInst_RU5<"p0", op, np, "nt">;
4146 def NAME#p0_jump_t : CJInst_RU5<"p0", op, np, "t">;
4148 let Defs = [PC, P1], Uses = [P1] in {
4149 def NAME#p1_jump_nt : CJInst_RU5<"p1", op, np, "nt">;
4150 def NAME#p1_jump_t : CJInst_RU5<"p1", op, np, "t">;
4153 // Predicate / !Predicate
4154 multiclass T_pnp_CJInst_RU5<string op>{
4155 defm J4_cmp#NAME#i_t : T_tnt_CJInst_RU5<op, 0>;
4156 defm J4_cmp#NAME#i_f : T_tnt_CJInst_RU5<op, 1>;
4158 // TypeCJ Instructions compare RI and jump
4159 defm eq : T_pnp_CJInst_RU5<"eq">;
4160 defm gt : T_pnp_CJInst_RU5<"gt">;
4161 defm gtu : T_pnp_CJInst_RU5<"gtu">;
4163 let isBranch = 1, hasSideEffects = 0, isExtentSigned = 1,
4164 isPredicated = 1, isPredicatedFalse = 1, isPredicatedNew = 1,
4165 isExtendable = 1, opExtentBits = 11, opExtentAlign = 2, opExtendable = 1,
4167 class CJInst_Rn1<string px, string op, bit np, string tnt>
4168 : InstHexagon<(outs), (ins IntRegs:$Rs, brtarget:$r9_2),
4169 ""#px#" = cmp."#op#"($Rs,#-1); if ("
4170 #!if(np, "!","")#""#px#".new) jump:"#tnt#" $r9_2",
4171 [], "", COMPOUND, TypeCOMPOUND>, OpcodeHexagon {
4176 let isPredicatedFalse = np;
4177 // tnt: Taken/Not Taken
4178 let isBrTaken = !if (!eq(tnt, "t"), "true", "false");
4179 let isTaken = !if (!eq(tnt, "t"), 1, 0);
4181 let IClass = 0b0001;
4182 let Inst{27-26} = 0b00;
4183 let Inst{25} = !if (!eq(px, "!p1"), 1,
4184 !if (!eq(px, "p1"), 1, 0));
4186 let Inst{24-23} = 0b11;
4188 let Inst{21-20} = r9_2{10-9};
4189 let Inst{19-16} = Rs;
4190 let Inst{13} = !if (!eq(tnt, "t"), 1, 0);
4191 let Inst{9-8} = !if (!eq(op, "eq"), 0b00,
4192 !if (!eq(op, "gt"), 0b01, 0));
4193 let Inst{7-1} = r9_2{8-2};
4196 // P[10] taken/not taken.
4197 multiclass T_tnt_CJInst_Rn1<string op, bit np> {
4198 let Defs = [PC, P0], Uses = [P0] in {
4199 def NAME#p0_jump_nt : CJInst_Rn1<"p0", op, np, "nt">;
4200 def NAME#p0_jump_t : CJInst_Rn1<"p0", op, np, "t">;
4202 let Defs = [PC, P1], Uses = [P1] in {
4203 def NAME#p1_jump_nt : CJInst_Rn1<"p1", op, np, "nt">;
4204 def NAME#p1_jump_t : CJInst_Rn1<"p1", op, np, "t">;
4207 // Predicate / !Predicate
4208 multiclass T_pnp_CJInst_Rn1<string op>{
4209 defm J4_cmp#NAME#n1_t : T_tnt_CJInst_Rn1<op, 0>;
4210 defm J4_cmp#NAME#n1_f : T_tnt_CJInst_Rn1<op, 1>;
4212 // TypeCJ Instructions compare -1 and jump
4213 defm eq : T_pnp_CJInst_Rn1<"eq">;
4214 defm gt : T_pnp_CJInst_Rn1<"gt">;
4216 // J4_jumpseti: Direct unconditional jump and set register to immediate.
4217 let Defs = [PC], isBranch = 1, hasSideEffects = 0, hasNewValue = 1,
4218 isExtentSigned = 1, opNewValue = 0, isExtendable = 1, opExtentBits = 11,
4219 opExtentAlign = 2, opExtendable = 2 in
4220 def J4_jumpseti: CJInst <
4222 (ins u6Imm:$U6, brtarget:$r9_2),
4223 "$Rd = #$U6 ; jump $r9_2"> {
4228 let IClass = 0b0001;
4229 let Inst{27-24} = 0b0110;
4230 let Inst{21-20} = r9_2{10-9};
4231 let Inst{19-16} = Rd;
4232 let Inst{13-8} = U6;
4233 let Inst{7-1} = r9_2{8-2};
4236 // J4_jumpsetr: Direct unconditional jump and transfer register.
4237 let Defs = [PC], isBranch = 1, hasSideEffects = 0, hasNewValue = 1,
4238 isExtentSigned = 1, opNewValue = 0, isExtendable = 1, opExtentBits = 11,
4239 opExtentAlign = 2, opExtendable = 2 in
4240 def J4_jumpsetr: CJInst <
4242 (ins IntRegs:$Rs, brtarget:$r9_2),
4243 "$Rd = $Rs ; jump $r9_2"> {
4248 let IClass = 0b0001;
4249 let Inst{27-24} = 0b0111;
4250 let Inst{21-20} = r9_2{10-9};
4251 let Inst{11-8} = Rd;
4252 let Inst{19-16} = Rs;
4253 let Inst{7-1} = r9_2{8-2};