1 //=- HexagonInstrInfoV4.td - Target Desc. for Hexagon Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Hexagon V4 instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 let hasSideEffects = 0 in
15 class T_Immext<Operand ImmType>
16 : EXTENDERInst<(outs), (ins ImmType:$imm),
17 "immext(#$imm)", []> {
21 let Inst{27-16} = imm{31-20};
22 let Inst{13-0} = imm{19-6};
25 def A4_ext : T_Immext<u26_6Imm>;
26 let isCodeGenOnly = 1 in {
28 def A4_ext_b : T_Immext<brtarget>;
30 def A4_ext_c : T_Immext<calltarget>;
31 def A4_ext_g : T_Immext<globaladdress>;
34 def BITPOS32 : SDNodeXForm<imm, [{
35 // Return the bit position we will set [0-31].
37 int32_t imm = N->getSExtValue();
38 return XformMskToBitPosU5Imm(imm);
41 // Fold (add (CONST32 tglobaladdr:$addr) <offset>) into a global address.
42 def FoldGlobalAddr : ComplexPattern<i32, 1, "foldGlobalAddress", [], []>;
44 // Fold (add (CONST32_GP tglobaladdr:$addr) <offset>) into a global address.
45 def FoldGlobalAddrGP : ComplexPattern<i32, 1, "foldGlobalAddressGP", [], []>;
47 def NumUsesBelowThresCONST32 : PatFrag<(ops node:$addr),
48 (HexagonCONST32 node:$addr), [{
49 return hasNumUsesBelowThresGA(N->getOperand(0).getNode());
52 // Hexagon V4 Architecture spec defines 8 instruction classes:
53 // LD ST ALU32 XTYPE J JR MEMOP NV CR SYSTEM(system is not implemented in the
57 // ========================================
58 // Loads (8/16/32/64 bit)
62 // ========================================
63 // Stores (8/16/32/64 bit)
66 // ALU32 Instructions:
67 // ========================================
68 // Arithmetic / Logical (32 bit)
71 // XTYPE Instructions (32/64 bit):
72 // ========================================
73 // Arithmetic, Logical, Bit Manipulation
74 // Multiply (Integer, Fractional, Complex)
75 // Permute / Vector Permute Operations
76 // Predicate Operations
77 // Shift / Shift with Add/Sub/Logical
79 // Vector Halfword (ALU, Shift, Multiply)
80 // Vector Word (ALU, Shift)
83 // ========================================
84 // Jump/Call PC-relative
87 // ========================================
90 // MEMOP Instructions:
91 // ========================================
92 // Operation on memory (8/16/32 bit)
95 // ========================================
100 // ========================================
101 // Control-Register Transfers
102 // Hardware Loop Setup
103 // Predicate Logicals & Reductions
105 // SYSTEM Instructions (not implemented in the compiler):
106 // ========================================
112 //===----------------------------------------------------------------------===//
114 //===----------------------------------------------------------------------===//
116 class T_ALU32_3op_not<string mnemonic, bits<3> MajOp, bits<3> MinOp,
118 : T_ALU32_3op<mnemonic, MajOp, MinOp, OpsRev, 0> {
119 let AsmString = "$Rd = "#mnemonic#"($Rs, ~$Rt)";
122 let BaseOpcode = "andn_rr", CextOpcode = "andn", isCodeGenOnly = 0 in
123 def A4_andn : T_ALU32_3op_not<"and", 0b001, 0b100, 1>;
124 let BaseOpcode = "orn_rr", CextOpcode = "orn", isCodeGenOnly = 0 in
125 def A4_orn : T_ALU32_3op_not<"or", 0b001, 0b101, 1>;
127 let CextOpcode = "rcmp.eq", isCodeGenOnly = 0 in
128 def A4_rcmpeq : T_ALU32_3op<"cmp.eq", 0b011, 0b010, 0, 1>;
129 let CextOpcode = "!rcmp.eq", isCodeGenOnly = 0 in
130 def A4_rcmpneq : T_ALU32_3op<"!cmp.eq", 0b011, 0b011, 0, 1>;
132 let isCodeGenOnly = 0 in {
133 def C4_cmpneq : T_ALU32_3op_cmp<"!cmp.eq", 0b00, 1, 1>;
134 def C4_cmplte : T_ALU32_3op_cmp<"!cmp.gt", 0b10, 1, 0>;
135 def C4_cmplteu : T_ALU32_3op_cmp<"!cmp.gtu", 0b11, 1, 0>;
138 // Pats for instruction selection.
140 // A class to embed the usual comparison patfrags within a zext to i32.
141 // The seteq/setne frags use "lhs" and "rhs" as operands, so use the same
142 // names, or else the frag's "body" won't match the operands.
143 class CmpInReg<PatFrag Op>
144 : PatFrag<(ops node:$lhs, node:$rhs),(i32 (zext (i1 Op.Fragment)))>;
146 def: T_cmp32_rr_pat<A4_rcmpeq, CmpInReg<seteq>, i32>;
147 def: T_cmp32_rr_pat<A4_rcmpneq, CmpInReg<setne>, i32>;
149 def: T_cmp32_rr_pat<C4_cmpneq, setne, i1>;
151 class T_CMP_rrbh<string mnemonic, bits<3> MinOp, bit IsComm>
152 : SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, IntRegs:$Rt),
153 "$Pd = "#mnemonic#"($Rs, $Rt)", [], "", S_3op_tc_2early_SLOT23>,
155 let validSubTargets = HasV4SubT;
156 let InputType = "reg";
157 let CextOpcode = mnemonic;
159 let isCommutable = IsComm;
160 let hasSideEffects = 0;
167 let Inst{27-21} = 0b0111110;
168 let Inst{20-16} = Rs;
170 let Inst{7-5} = MinOp;
174 let isCodeGenOnly = 0 in {
175 def A4_cmpbeq : T_CMP_rrbh<"cmpb.eq", 0b110, 1>;
176 def A4_cmpbgt : T_CMP_rrbh<"cmpb.gt", 0b010, 0>;
177 def A4_cmpbgtu : T_CMP_rrbh<"cmpb.gtu", 0b111, 0>;
178 def A4_cmpheq : T_CMP_rrbh<"cmph.eq", 0b011, 1>;
179 def A4_cmphgt : T_CMP_rrbh<"cmph.gt", 0b100, 0>;
180 def A4_cmphgtu : T_CMP_rrbh<"cmph.gtu", 0b101, 0>;
183 class T_CMP_ribh<string mnemonic, bits<2> MajOp, bit IsHalf, bit IsComm,
184 Operand ImmType, bit IsImmExt, bit IsImmSigned, int ImmBits>
185 : ALU64Inst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, ImmType:$Imm),
186 "$Pd = "#mnemonic#"($Rs, #$Imm)", [], "", ALU64_tc_2early_SLOT23>,
188 let validSubTargets = HasV4SubT;
189 let InputType = "imm";
190 let CextOpcode = mnemonic;
192 let isCommutable = IsComm;
193 let hasSideEffects = 0;
194 let isExtendable = IsImmExt;
195 let opExtendable = !if (IsImmExt, 2, 0);
196 let isExtentSigned = IsImmSigned;
197 let opExtentBits = ImmBits;
204 let Inst{27-24} = 0b1101;
205 let Inst{22-21} = MajOp;
206 let Inst{20-16} = Rs;
207 let Inst{12-5} = Imm;
209 let Inst{3} = IsHalf;
213 let isCodeGenOnly = 0 in {
214 def A4_cmpbeqi : T_CMP_ribh<"cmpb.eq", 0b00, 0, 1, u8Imm, 0, 0, 8>;
215 def A4_cmpbgti : T_CMP_ribh<"cmpb.gt", 0b01, 0, 0, s8Imm, 0, 1, 8>;
216 def A4_cmpbgtui : T_CMP_ribh<"cmpb.gtu", 0b10, 0, 0, u7Ext, 1, 0, 7>;
217 def A4_cmpheqi : T_CMP_ribh<"cmph.eq", 0b00, 1, 1, s8Ext, 1, 1, 8>;
218 def A4_cmphgti : T_CMP_ribh<"cmph.gt", 0b01, 1, 0, s8Ext, 1, 1, 8>;
219 def A4_cmphgtui : T_CMP_ribh<"cmph.gtu", 0b10, 1, 0, u7Ext, 1, 0, 7>;
221 class T_RCMP_EQ_ri<string mnemonic, bit IsNeg>
222 : ALU32_ri<(outs IntRegs:$Rd), (ins IntRegs:$Rs, s8Ext:$s8),
223 "$Rd = "#mnemonic#"($Rs, #$s8)", [], "", ALU32_2op_tc_1_SLOT0123>,
225 let validSubTargets = HasV4SubT;
226 let InputType = "imm";
227 let CextOpcode = !if (IsNeg, "!rcmp.eq", "rcmp.eq");
228 let isExtendable = 1;
229 let opExtendable = 2;
230 let isExtentSigned = 1;
231 let opExtentBits = 8;
239 let Inst{27-24} = 0b0011;
241 let Inst{21} = IsNeg;
242 let Inst{20-16} = Rs;
248 let isCodeGenOnly = 0 in {
249 def A4_rcmpeqi : T_RCMP_EQ_ri<"cmp.eq", 0>;
250 def A4_rcmpneqi : T_RCMP_EQ_ri<"!cmp.eq", 1>;
253 def: Pat<(i32 (zext (i1 (seteq (i32 IntRegs:$Rs), s8ExtPred:$s8)))),
254 (A4_rcmpeqi IntRegs:$Rs, s8ExtPred:$s8)>;
255 def: Pat<(i32 (zext (i1 (setne (i32 IntRegs:$Rs), s8ExtPred:$s8)))),
256 (A4_rcmpneqi IntRegs:$Rs, s8ExtPred:$s8)>;
258 // Preserve the S2_tstbit_r generation
259 def: Pat<(i32 (zext (i1 (setne (i32 (and (i32 (shl 1, (i32 IntRegs:$src2))),
260 (i32 IntRegs:$src1))), 0)))),
261 (C2_muxii (S2_tstbit_r IntRegs:$src1, IntRegs:$src2), 1, 0)>;
264 //===----------------------------------------------------------------------===//
266 //===----------------------------------------------------------------------===//
269 //===----------------------------------------------------------------------===//
271 //===----------------------------------------------------------------------===//
273 // Combine a word and an immediate into a register pair.
274 let hasSideEffects = 0, isExtentSigned = 1, isExtendable = 1,
276 class T_Combine1 <bits<2> MajOp, dag ins, string AsmStr>
277 : ALU32Inst <(outs DoubleRegs:$Rdd), ins, AsmStr> {
283 let Inst{27-24} = 0b0011;
284 let Inst{22-21} = MajOp;
285 let Inst{20-16} = Rs;
291 let opExtendable = 2, isCodeGenOnly = 0 in
292 def A4_combineri : T_Combine1<0b00, (ins IntRegs:$Rs, s8Ext:$s8),
293 "$Rdd = combine($Rs, #$s8)">;
295 let opExtendable = 1, isCodeGenOnly = 0 in
296 def A4_combineir : T_Combine1<0b01, (ins s8Ext:$s8, IntRegs:$Rs),
297 "$Rdd = combine(#$s8, $Rs)">;
299 def HexagonWrapperCombineRI_V4 :
300 SDNode<"HexagonISD::WrapperCombineRI_V4", SDTHexagonI64I32I32>;
301 def HexagonWrapperCombineIR_V4 :
302 SDNode<"HexagonISD::WrapperCombineIR_V4", SDTHexagonI64I32I32>;
304 def : Pat <(HexagonWrapperCombineRI_V4 IntRegs:$r, s8ExtPred:$i),
305 (A4_combineri IntRegs:$r, s8ExtPred:$i)>,
308 def : Pat <(HexagonWrapperCombineIR_V4 s8ExtPred:$i, IntRegs:$r),
309 (A4_combineir s8ExtPred:$i, IntRegs:$r)>,
312 // A4_combineii: Set two small immediates.
313 let hasSideEffects = 0, isExtendable = 1, opExtentBits = 6, opExtendable = 2 in
314 def A4_combineii: ALU32Inst<(outs DoubleRegs:$Rdd), (ins s8Imm:$s8, u6Ext:$U6),
315 "$Rdd = combine(#$s8, #$U6)"> {
321 let Inst{27-23} = 0b11001;
322 let Inst{20-16} = U6{5-1};
323 let Inst{13} = U6{0};
328 //===----------------------------------------------------------------------===//
330 //===----------------------------------------------------------------------===//
332 //===----------------------------------------------------------------------===//
334 //===----------------------------------------------------------------------===//
335 //===----------------------------------------------------------------------===//
336 // Template class for load instructions with Absolute set addressing mode.
337 //===----------------------------------------------------------------------===//
338 let isExtended = 1, opExtendable = 2, opExtentBits = 6, addrMode = AbsoluteSet,
339 hasSideEffects = 0 in
340 class T_LD_abs_set<string mnemonic, RegisterClass RC, bits<4>MajOp>:
341 LDInst<(outs RC:$dst1, IntRegs:$dst2),
343 "$dst1 = "#mnemonic#"($dst2 = #$addr)",
351 let Inst{27-25} = 0b101;
352 let Inst{24-21} = MajOp;
353 let Inst{13-12} = 0b01;
354 let Inst{4-0} = dst1;
355 let Inst{20-16} = dst2;
356 let Inst{11-8} = addr{5-2};
357 let Inst{6-5} = addr{1-0};
360 let accessSize = ByteAccess, hasNewValue = 1, isCodeGenOnly = 0 in {
361 def L4_loadrb_ap : T_LD_abs_set <"memb", IntRegs, 0b1000>;
362 def L4_loadrub_ap : T_LD_abs_set <"memub", IntRegs, 0b1001>;
365 let accessSize = HalfWordAccess, hasNewValue = 1, isCodeGenOnly = 0 in {
366 def L4_loadrh_ap : T_LD_abs_set <"memh", IntRegs, 0b1010>;
367 def L4_loadruh_ap : T_LD_abs_set <"memuh", IntRegs, 0b1011>;
370 let accessSize = WordAccess, hasNewValue = 1, isCodeGenOnly = 0 in
371 def L4_loadri_ap : T_LD_abs_set <"memw", IntRegs, 0b1100>;
373 let accessSize = DoubleWordAccess, isCodeGenOnly = 0 in
374 def L4_loadrd_ap : T_LD_abs_set <"memd", DoubleRegs, 0b1110>;
376 //===----------------------------------------------------------------------===//
377 // Template classes for the non-predicated load instructions with
378 // base + register offset addressing mode
379 //===----------------------------------------------------------------------===//
380 class T_load_rr <string mnemonic, RegisterClass RC, bits<3> MajOp>:
381 LDInst<(outs RC:$dst), (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$u2),
382 "$dst = "#mnemonic#"($src1 + $src2<<#$u2)",
383 [], "", V4LDST_tc_ld_SLOT01>, ImmRegShl, AddrModeRel {
391 let Inst{27-24} = 0b1010;
392 let Inst{23-21} = MajOp;
393 let Inst{20-16} = src1;
394 let Inst{12-8} = src2;
395 let Inst{13} = u2{1};
400 //===----------------------------------------------------------------------===//
401 // Template classes for the predicated load instructions with
402 // base + register offset addressing mode
403 //===----------------------------------------------------------------------===//
404 let isPredicated = 1 in
405 class T_pload_rr <string mnemonic, RegisterClass RC, bits<3> MajOp,
406 bit isNot, bit isPredNew>:
407 LDInst <(outs RC:$dst),
408 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$u2),
409 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
410 ") ")#"$dst = "#mnemonic#"($src2+$src3<<#$u2)",
411 [], "", V4LDST_tc_ld_SLOT01>, AddrModeRel {
418 let isPredicatedFalse = isNot;
419 let isPredicatedNew = isPredNew;
423 let Inst{27-26} = 0b00;
424 let Inst{25} = isPredNew;
425 let Inst{24} = isNot;
426 let Inst{23-21} = MajOp;
427 let Inst{20-16} = src2;
428 let Inst{12-8} = src3;
429 let Inst{13} = u2{1};
431 let Inst{6-5} = src1;
435 //===----------------------------------------------------------------------===//
436 // multiclass for load instructions with base + register offset
438 //===----------------------------------------------------------------------===//
439 let hasSideEffects = 0, addrMode = BaseRegOffset in
440 multiclass ld_idxd_shl <string mnemonic, string CextOp, RegisterClass RC,
442 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed_shl,
443 InputType = "reg" in {
444 let isPredicable = 1 in
445 def L4_#NAME#_rr : T_load_rr <mnemonic, RC, MajOp>;
448 def L4_p#NAME#t_rr : T_pload_rr <mnemonic, RC, MajOp, 0, 0>;
449 def L4_p#NAME#f_rr : T_pload_rr <mnemonic, RC, MajOp, 1, 0>;
452 def L4_p#NAME#tnew_rr : T_pload_rr <mnemonic, RC, MajOp, 0, 1>;
453 def L4_p#NAME#fnew_rr : T_pload_rr <mnemonic, RC, MajOp, 1, 1>;
457 let hasNewValue = 1, accessSize = ByteAccess, isCodeGenOnly = 0 in {
458 defm loadrb : ld_idxd_shl<"memb", "LDrib", IntRegs, 0b000>;
459 defm loadrub : ld_idxd_shl<"memub", "LDriub", IntRegs, 0b001>;
462 let hasNewValue = 1, accessSize = HalfWordAccess, isCodeGenOnly = 0 in {
463 defm loadrh : ld_idxd_shl<"memh", "LDrih", IntRegs, 0b010>;
464 defm loadruh : ld_idxd_shl<"memuh", "LDriuh", IntRegs, 0b011>;
467 let hasNewValue = 1, accessSize = WordAccess, isCodeGenOnly = 0 in
468 defm loadri : ld_idxd_shl<"memw", "LDriw", IntRegs, 0b100>;
470 let accessSize = DoubleWordAccess, isCodeGenOnly = 0 in
471 defm loadrd : ld_idxd_shl<"memd", "LDrid", DoubleRegs, 0b110>;
473 // 'def pats' for load instructions with base + register offset and non-zero
474 // immediate value. Immediate value is used to left-shift the second
476 let AddedComplexity = 40 in {
477 def : Pat <(i32 (sextloadi8 (add IntRegs:$src1,
478 (shl IntRegs:$src2, u2ImmPred:$offset)))),
479 (L4_loadrb_rr IntRegs:$src1,
480 IntRegs:$src2, u2ImmPred:$offset)>,
483 def : Pat <(i32 (zextloadi8 (add IntRegs:$src1,
484 (shl IntRegs:$src2, u2ImmPred:$offset)))),
485 (L4_loadrub_rr IntRegs:$src1,
486 IntRegs:$src2, u2ImmPred:$offset)>,
489 def : Pat <(i32 (extloadi8 (add IntRegs:$src1,
490 (shl IntRegs:$src2, u2ImmPred:$offset)))),
491 (L4_loadrub_rr IntRegs:$src1,
492 IntRegs:$src2, u2ImmPred:$offset)>,
495 def : Pat <(i32 (sextloadi16 (add IntRegs:$src1,
496 (shl IntRegs:$src2, u2ImmPred:$offset)))),
497 (L4_loadrh_rr IntRegs:$src1,
498 IntRegs:$src2, u2ImmPred:$offset)>,
501 def : Pat <(i32 (zextloadi16 (add IntRegs:$src1,
502 (shl IntRegs:$src2, u2ImmPred:$offset)))),
503 (L4_loadruh_rr IntRegs:$src1,
504 IntRegs:$src2, u2ImmPred:$offset)>,
507 def : Pat <(i32 (extloadi16 (add IntRegs:$src1,
508 (shl IntRegs:$src2, u2ImmPred:$offset)))),
509 (L4_loadruh_rr IntRegs:$src1,
510 IntRegs:$src2, u2ImmPred:$offset)>,
513 def : Pat <(i32 (load (add IntRegs:$src1,
514 (shl IntRegs:$src2, u2ImmPred:$offset)))),
515 (L4_loadri_rr IntRegs:$src1,
516 IntRegs:$src2, u2ImmPred:$offset)>,
519 def : Pat <(i64 (load (add IntRegs:$src1,
520 (shl IntRegs:$src2, u2ImmPred:$offset)))),
521 (L4_loadrd_rr IntRegs:$src1,
522 IntRegs:$src2, u2ImmPred:$offset)>,
526 // 'def pats' for load instruction base + register offset and
527 // zero immediate value.
528 class Loadxs_simple_pat<PatFrag Load, ValueType VT, InstHexagon MI>
529 : Pat<(VT (Load (add (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)))),
530 (VT (MI IntRegs:$Rs, IntRegs:$Rt, 0))>;
532 let AddedComplexity = 20 in {
533 def: Loadxs_simple_pat<extloadi8, i32, L4_loadrub_rr>;
534 def: Loadxs_simple_pat<zextloadi8, i32, L4_loadrub_rr>;
535 def: Loadxs_simple_pat<sextloadi8, i32, L4_loadrb_rr>;
536 def: Loadxs_simple_pat<extloadi16, i32, L4_loadruh_rr>;
537 def: Loadxs_simple_pat<zextloadi16, i32, L4_loadruh_rr>;
538 def: Loadxs_simple_pat<sextloadi16, i32, L4_loadrh_rr>;
539 def: Loadxs_simple_pat<load, i32, L4_loadri_rr>;
540 def: Loadxs_simple_pat<load, i64, L4_loadrd_rr>;
544 def : Pat <(i64 (zext (i1 PredRegs:$src1))),
545 (i64 (A4_combineir 0, (C2_muxii (i1 PredRegs:$src1), 1, 0)))>,
549 def : Pat <(i64 (zext (i32 IntRegs:$src1))),
550 (i64 (A4_combineir 0, (i32 IntRegs:$src1)))>,
553 def: Pat <(i64 (zextloadi8 ADDRriS11_0:$src1)),
554 (i64 (A4_combineir 0, (L2_loadrub_io AddrFI:$src1, 0)))>,
557 let AddedComplexity = 20 in
558 def: Pat <(i64 (zextloadi8 (add (i32 IntRegs:$src1),
559 s11_0ExtPred:$offset))),
560 (i64 (A4_combineir 0, (L2_loadrub_io IntRegs:$src1,
561 s11_0ExtPred:$offset)))>,
565 def: Pat <(i64 (zextloadi1 ADDRriS11_0:$src1)),
566 (i64 (A4_combineir 0, (L2_loadrub_io AddrFI:$src1, 0)))>,
569 let AddedComplexity = 20 in
570 def: Pat <(i64 (zextloadi1 (add (i32 IntRegs:$src1),
571 s11_0ExtPred:$offset))),
572 (i64 (A4_combineir 0, (L2_loadrub_io IntRegs:$src1,
573 s11_0ExtPred:$offset)))>,
577 def: Pat <(i64 (zextloadi16 ADDRriS11_1:$src1)),
578 (i64 (A4_combineir 0, (L2_loadruh_io AddrFI:$src1, 0)))>,
581 let AddedComplexity = 20 in
582 def: Pat <(i64 (zextloadi16 (add (i32 IntRegs:$src1),
583 s11_1ExtPred:$offset))),
584 (i64 (A4_combineir 0, (L2_loadruh_io IntRegs:$src1,
585 s11_1ExtPred:$offset)))>,
589 def: Pat <(i64 (extloadi16 ADDRriS11_2:$src1)),
590 (i64 (A4_combineir 0, (L2_loadrh_io AddrFI:$src1, 0)))>,
593 let AddedComplexity = 20 in
594 def: Pat <(i64 (extloadi16 (add (i32 IntRegs:$src1),
595 s11_1ExtPred:$offset))),
596 (i64 (A4_combineir 0, (L2_loadrh_io IntRegs:$src1,
597 s11_1ExtPred:$offset)))>,
601 def: Pat <(i64 (zextloadi32 ADDRriS11_2:$src1)),
602 (i64 (A4_combineir 0, (L2_loadri_io AddrFI:$src1, 0)))>,
605 let AddedComplexity = 100 in
606 def: Pat <(i64 (zextloadi32 (i32 (add IntRegs:$src1, s11_2ExtPred:$offset)))),
607 (i64 (A4_combineir 0, (L2_loadri_io IntRegs:$src1,
608 s11_2ExtPred:$offset)))>,
612 def: Pat <(i64 (extloadi32 ADDRriS11_2:$src1)),
613 (i64 (A4_combineir 0, (L2_loadri_io AddrFI:$src1, 0)))>,
616 let AddedComplexity = 100 in
617 def: Pat <(i64 (extloadi32 (i32 (add IntRegs:$src1, s11_2ExtPred:$offset)))),
618 (i64 (A4_combineir 0, (L2_loadri_io IntRegs:$src1,
619 s11_2ExtPred:$offset)))>,
624 //===----------------------------------------------------------------------===//
626 //===----------------------------------------------------------------------===//
628 //===----------------------------------------------------------------------===//
630 //===----------------------------------------------------------------------===//
632 //===----------------------------------------------------------------------===//
633 // Template class for store instructions with Absolute set addressing mode.
634 //===----------------------------------------------------------------------===//
635 let isExtended = 1, opExtendable = 2, validSubTargets = HasV4SubT,
636 addrMode = AbsoluteSet in
637 class T_ST_abs_set<string mnemonic, RegisterClass RC>:
638 STInst2<(outs IntRegs:$dst1),
639 (ins RC:$src1, u0AlwaysExt:$src2),
640 mnemonic#"($dst1=##$src2) = $src1",
644 def STrid_abs_set_V4 : T_ST_abs_set <"memd", DoubleRegs>;
645 def STrib_abs_set_V4 : T_ST_abs_set <"memb", IntRegs>;
646 def STrih_abs_set_V4 : T_ST_abs_set <"memh", IntRegs>;
647 def STriw_abs_set_V4 : T_ST_abs_set <"memw", IntRegs>;
649 //===----------------------------------------------------------------------===//
650 // Template classes for the non-predicated store instructions with
651 // base + register offset addressing mode
652 //===----------------------------------------------------------------------===//
653 let isPredicable = 1 in
654 class T_store_rr <string mnemonic, RegisterClass RC, bits<3> MajOp, bit isH>
655 : STInst < (outs ), (ins IntRegs:$Rs, IntRegs:$Ru, u2Imm:$u2, RC:$Rt),
656 mnemonic#"($Rs + $Ru<<#$u2) = $Rt"#!if(isH, ".h",""),
657 [],"",V4LDST_tc_st_SLOT01>, ImmRegShl, AddrModeRel {
666 let Inst{27-24} = 0b1011;
667 let Inst{23-21} = MajOp;
668 let Inst{20-16} = Rs;
670 let Inst{13} = u2{1};
675 //===----------------------------------------------------------------------===//
676 // Template classes for the predicated store instructions with
677 // base + register offset addressing mode
678 //===----------------------------------------------------------------------===//
679 let isPredicated = 1 in
680 class T_pstore_rr <string mnemonic, RegisterClass RC, bits<3> MajOp,
681 bit isNot, bit isPredNew, bit isH>
683 (ins PredRegs:$Pv, IntRegs:$Rs, IntRegs:$Ru, u2Imm:$u2, RC:$Rt),
685 !if(isNot, "if (!$Pv", "if ($Pv")#!if(isPredNew, ".new) ",
686 ") ")#mnemonic#"($Rs+$Ru<<#$u2) = $Rt"#!if(isH, ".h",""),
687 [], "", V4LDST_tc_st_SLOT01> , AddrModeRel{
694 let isPredicatedFalse = isNot;
695 let isPredicatedNew = isPredNew;
699 let Inst{27-26} = 0b01;
700 let Inst{25} = isPredNew;
701 let Inst{24} = isNot;
702 let Inst{23-21} = MajOp;
703 let Inst{20-16} = Rs;
705 let Inst{13} = u2{1};
711 //===----------------------------------------------------------------------===//
712 // Template classes for the new-value store instructions with
713 // base + register offset addressing mode
714 //===----------------------------------------------------------------------===//
715 let isPredicable = 1, isNewValue = 1, opNewValue = 3 in
716 class T_store_new_rr <string mnemonic, bits<2> MajOp> :
717 NVInst < (outs ), (ins IntRegs:$Rs, IntRegs:$Ru, u2Imm:$u2, IntRegs:$Nt),
718 mnemonic#"($Rs + $Ru<<#$u2) = $Nt.new",
719 [],"",V4LDST_tc_st_SLOT0>, ImmRegShl, AddrModeRel {
728 let Inst{27-21} = 0b1011101;
729 let Inst{20-16} = Rs;
731 let Inst{13} = u2{1};
733 let Inst{4-3} = MajOp;
737 //===----------------------------------------------------------------------===//
738 // Template classes for the predicated new-value store instructions with
739 // base + register offset addressing mode
740 //===----------------------------------------------------------------------===//
741 let isPredicated = 1, isNewValue = 1, opNewValue = 4 in
742 class T_pstore_new_rr <string mnemonic, bits<2> MajOp, bit isNot, bit isPredNew>
744 (ins PredRegs:$Pv, IntRegs:$Rs, IntRegs:$Ru, u2Imm:$u2, IntRegs:$Nt),
745 !if(isNot, "if (!$Pv", "if ($Pv")#!if(isPredNew, ".new) ",
746 ") ")#mnemonic#"($Rs+$Ru<<#$u2) = $Nt.new",
747 [], "", V4LDST_tc_st_SLOT0>, AddrModeRel {
754 let isPredicatedFalse = isNot;
755 let isPredicatedNew = isPredNew;
758 let Inst{27-26} = 0b01;
759 let Inst{25} = isPredNew;
760 let Inst{24} = isNot;
761 let Inst{23-21} = 0b101;
762 let Inst{20-16} = Rs;
764 let Inst{13} = u2{1};
767 let Inst{4-3} = MajOp;
771 //===----------------------------------------------------------------------===//
772 // multiclass for store instructions with base + register offset addressing
774 //===----------------------------------------------------------------------===//
775 let isNVStorable = 1 in
776 multiclass ST_Idxd_shl<string mnemonic, string CextOp, RegisterClass RC,
777 bits<3> MajOp, bit isH = 0> {
778 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed_shl in {
779 def S4_#NAME#_rr : T_store_rr <mnemonic, RC, MajOp, isH>;
782 def S4_p#NAME#t_rr : T_pstore_rr <mnemonic, RC, MajOp, 0, 0, isH>;
783 def S4_p#NAME#f_rr : T_pstore_rr <mnemonic, RC, MajOp, 1, 0, isH>;
786 def S4_p#NAME#tnew_rr : T_pstore_rr <mnemonic, RC, MajOp, 0, 1, isH>;
787 def S4_p#NAME#fnew_rr : T_pstore_rr <mnemonic, RC, MajOp, 1, 1, isH>;
791 //===----------------------------------------------------------------------===//
792 // multiclass for new-value store instructions with base + register offset
794 //===----------------------------------------------------------------------===//
795 let mayStore = 1, isNVStore = 1 in
796 multiclass ST_Idxd_shl_nv <string mnemonic, string CextOp, RegisterClass RC,
798 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed_shl in {
799 def S4_#NAME#new_rr : T_store_new_rr<mnemonic, MajOp>;
802 def S4_p#NAME#newt_rr : T_pstore_new_rr <mnemonic, MajOp, 0, 0>;
803 def S4_p#NAME#newf_rr : T_pstore_new_rr <mnemonic, MajOp, 1, 0>;
806 def S4_p#NAME#newtnew_rr : T_pstore_new_rr <mnemonic, MajOp, 0, 1>;
807 def S4_p#NAME#newfnew_rr : T_pstore_new_rr <mnemonic, MajOp, 1, 1>;
811 let addrMode = BaseRegOffset, InputType = "reg", hasSideEffects = 0,
812 isCodeGenOnly = 0 in {
813 let accessSize = ByteAccess in
814 defm storerb: ST_Idxd_shl<"memb", "STrib", IntRegs, 0b000>,
815 ST_Idxd_shl_nv<"memb", "STrib", IntRegs, 0b00>;
817 let accessSize = HalfWordAccess in
818 defm storerh: ST_Idxd_shl<"memh", "STrih", IntRegs, 0b010>,
819 ST_Idxd_shl_nv<"memh", "STrih", IntRegs, 0b01>;
821 let accessSize = WordAccess in
822 defm storeri: ST_Idxd_shl<"memw", "STriw", IntRegs, 0b100>,
823 ST_Idxd_shl_nv<"memw", "STriw", IntRegs, 0b10>;
825 let isNVStorable = 0, accessSize = DoubleWordAccess in
826 defm storerd: ST_Idxd_shl<"memd", "STrid", DoubleRegs, 0b110>;
828 let isNVStorable = 0, accessSize = HalfWordAccess in
829 defm storerf: ST_Idxd_shl<"memh", "STrif", IntRegs, 0b011, 1>;
832 let Predicates = [HasV4T], AddedComplexity = 10 in {
833 def : Pat<(truncstorei8 (i32 IntRegs:$src4),
834 (add IntRegs:$src1, (shl IntRegs:$src2,
836 (S4_storerb_rr IntRegs:$src1, IntRegs:$src2,
837 u2ImmPred:$src3, IntRegs:$src4)>;
839 def : Pat<(truncstorei16 (i32 IntRegs:$src4),
840 (add IntRegs:$src1, (shl IntRegs:$src2,
842 (S4_storerh_rr IntRegs:$src1, IntRegs:$src2,
843 u2ImmPred:$src3, IntRegs:$src4)>;
845 def : Pat<(store (i32 IntRegs:$src4),
846 (add IntRegs:$src1, (shl IntRegs:$src2, u2ImmPred:$src3))),
847 (S4_storeri_rr IntRegs:$src1, IntRegs:$src2,
848 u2ImmPred:$src3, IntRegs:$src4)>;
850 def : Pat<(store (i64 DoubleRegs:$src4),
851 (add IntRegs:$src1, (shl IntRegs:$src2, u2ImmPred:$src3))),
852 (S4_storerd_rr IntRegs:$src1, IntRegs:$src2,
853 u2ImmPred:$src3, DoubleRegs:$src4)>;
856 let isExtended = 1, opExtendable = 2 in
857 class T_ST_LongOff <string mnemonic, PatFrag stOp, RegisterClass RC, ValueType VT> :
859 (ins IntRegs:$src1, u2Imm:$src2, u0AlwaysExt:$src3, RC:$src4),
860 mnemonic#"($src1<<#$src2+##$src3) = $src4",
861 [(stOp (VT RC:$src4),
862 (add (shl (i32 IntRegs:$src1), u2ImmPred:$src2),
863 u0AlwaysExtPred:$src3))]>,
866 let isExtended = 1, opExtendable = 2, mayStore = 1, isNVStore = 1 in
867 class T_ST_LongOff_nv <string mnemonic> :
869 (ins IntRegs:$src1, u2Imm:$src2, u0AlwaysExt:$src3, IntRegs:$src4),
870 mnemonic#"($src1<<#$src2+##$src3) = $src4.new",
874 multiclass ST_LongOff <string mnemonic, string BaseOp, PatFrag stOp> {
875 let BaseOpcode = BaseOp#"_shl" in {
876 let isNVStorable = 1 in
877 def NAME#_V4 : T_ST_LongOff<mnemonic, stOp, IntRegs, i32>;
879 def NAME#_nv_V4 : T_ST_LongOff_nv<mnemonic>;
883 let AddedComplexity = 10, validSubTargets = HasV4SubT in {
884 def STrid_shl_V4 : T_ST_LongOff<"memd", store, DoubleRegs, i64>;
885 defm STrib_shl : ST_LongOff <"memb", "STrib", truncstorei8>, NewValueRel;
886 defm STrih_shl : ST_LongOff <"memh", "Strih", truncstorei16>, NewValueRel;
887 defm STriw_shl : ST_LongOff <"memw", "STriw", store>, NewValueRel;
890 let AddedComplexity = 40 in
891 multiclass T_ST_LOff_Pats <InstHexagon I, RegisterClass RC, ValueType VT,
893 def : Pat<(stOp (VT RC:$src4),
894 (add (shl IntRegs:$src1, u2ImmPred:$src2),
895 (NumUsesBelowThresCONST32 tglobaladdr:$src3))),
896 (I IntRegs:$src1, u2ImmPred:$src2, tglobaladdr:$src3, RC:$src4)>;
898 def : Pat<(stOp (VT RC:$src4),
900 (NumUsesBelowThresCONST32 tglobaladdr:$src3))),
901 (I IntRegs:$src1, 0, tglobaladdr:$src3, RC:$src4)>;
904 defm : T_ST_LOff_Pats<STrid_shl_V4, DoubleRegs, i64, store>;
905 defm : T_ST_LOff_Pats<STriw_shl_V4, IntRegs, i32, store>;
906 defm : T_ST_LOff_Pats<STrib_shl_V4, IntRegs, i32, truncstorei8>;
907 defm : T_ST_LOff_Pats<STrih_shl_V4, IntRegs, i32, truncstorei16>;
909 // memd(Rx++#s4:3)=Rtt
910 // memd(Rx++#s4:3:circ(Mu))=Rtt
911 // memd(Rx++I:circ(Mu))=Rtt
913 // memd(Rx++Mu:brev)=Rtt
914 // memd(gp+#u16:3)=Rtt
916 // Store doubleword conditionally.
917 // if ([!]Pv[.new]) memd(#u6)=Rtt
918 // TODO: needs to be implemented.
920 //===----------------------------------------------------------------------===//
922 //===----------------------------------------------------------------------===//
923 let isPredicable = 1, isExtendable = 1, isExtentSigned = 1, opExtentBits = 8,
925 class T_StoreImm <string mnemonic, Operand OffsetOp, bits<2> MajOp >
926 : STInst <(outs ), (ins IntRegs:$Rs, OffsetOp:$offset, s8Ext:$S8),
927 mnemonic#"($Rs+#$offset)=#$S8",
928 [], "", V4LDST_tc_st_SLOT01>,
929 ImmRegRel, PredNewRel {
935 string OffsetOpStr = !cast<string>(OffsetOp);
936 let offsetBits = !if (!eq(OffsetOpStr, "u6_2Imm"), offset{7-2},
937 !if (!eq(OffsetOpStr, "u6_1Imm"), offset{6-1},
938 /* u6_0Imm */ offset{5-0}));
942 let Inst{27-25} = 0b110;
943 let Inst{22-21} = MajOp;
944 let Inst{20-16} = Rs;
945 let Inst{12-7} = offsetBits;
946 let Inst{13} = S8{7};
947 let Inst{6-0} = S8{6-0};
950 let isPredicated = 1, isExtendable = 1, isExtentSigned = 1, opExtentBits = 6,
952 class T_StoreImm_pred <string mnemonic, Operand OffsetOp, bits<2> MajOp,
953 bit isPredNot, bit isPredNew >
955 (ins PredRegs:$Pv, IntRegs:$Rs, OffsetOp:$offset, s6Ext:$S6),
956 !if(isPredNot, "if (!$Pv", "if ($Pv")#!if(isPredNew, ".new) ",
957 ") ")#mnemonic#"($Rs+#$offset)=#$S6",
958 [], "", V4LDST_tc_st_SLOT01>,
959 ImmRegRel, PredNewRel {
966 string OffsetOpStr = !cast<string>(OffsetOp);
967 let offsetBits = !if (!eq(OffsetOpStr, "u6_2Imm"), offset{7-2},
968 !if (!eq(OffsetOpStr, "u6_1Imm"), offset{6-1},
969 /* u6_0Imm */ offset{5-0}));
970 let isPredicatedNew = isPredNew;
971 let isPredicatedFalse = isPredNot;
975 let Inst{27-25} = 0b100;
976 let Inst{24} = isPredNew;
977 let Inst{23} = isPredNot;
978 let Inst{22-21} = MajOp;
979 let Inst{20-16} = Rs;
980 let Inst{13} = S6{5};
981 let Inst{12-7} = offsetBits;
983 let Inst{4-0} = S6{4-0};
987 //===----------------------------------------------------------------------===//
988 // multiclass for store instructions with base + immediate offset
989 // addressing mode and immediate stored value.
990 // mem[bhw](Rx++#s4:3)=#s8
991 // if ([!]Pv[.new]) mem[bhw](Rx++#s4:3)=#s6
992 //===----------------------------------------------------------------------===//
994 multiclass ST_Imm_Pred <string mnemonic, Operand OffsetOp, bits<2> MajOp,
996 def _io : T_StoreImm_pred <mnemonic, OffsetOp, MajOp, PredNot, 0>;
998 def new_io : T_StoreImm_pred <mnemonic, OffsetOp, MajOp, PredNot, 1>;
1001 multiclass ST_Imm <string mnemonic, string CextOp, Operand OffsetOp,
1003 let CextOpcode = CextOp, BaseOpcode = CextOp#_imm in {
1004 def _io : T_StoreImm <mnemonic, OffsetOp, MajOp>;
1006 defm t : ST_Imm_Pred <mnemonic, OffsetOp, MajOp, 0>;
1007 defm f : ST_Imm_Pred <mnemonic, OffsetOp, MajOp, 1>;
1011 let hasSideEffects = 0, validSubTargets = HasV4SubT, addrMode = BaseImmOffset,
1012 InputType = "imm", isCodeGenOnly = 0 in {
1013 let accessSize = ByteAccess in
1014 defm S4_storeirb : ST_Imm<"memb", "STrib", u6_0Imm, 0b00>;
1016 let accessSize = HalfWordAccess in
1017 defm S4_storeirh : ST_Imm<"memh", "STrih", u6_1Imm, 0b01>;
1019 let accessSize = WordAccess in
1020 defm S4_storeiri : ST_Imm<"memw", "STriw", u6_2Imm, 0b10>;
1023 let Predicates = [HasV4T], AddedComplexity = 10 in {
1024 def: Pat<(truncstorei8 s8ExtPred:$src3, (add IntRegs:$src1, u6_0ImmPred:$src2)),
1025 (S4_storeirb_io IntRegs:$src1, u6_0ImmPred:$src2, s8ExtPred:$src3)>;
1027 def: Pat<(truncstorei16 s8ExtPred:$src3, (add IntRegs:$src1,
1028 u6_1ImmPred:$src2)),
1029 (S4_storeirh_io IntRegs:$src1, u6_1ImmPred:$src2, s8ExtPred:$src3)>;
1031 def: Pat<(store s8ExtPred:$src3, (add IntRegs:$src1, u6_2ImmPred:$src2)),
1032 (S4_storeiri_io IntRegs:$src1, u6_2ImmPred:$src2, s8ExtPred:$src3)>;
1035 let AddedComplexity = 6 in
1036 def : Pat <(truncstorei8 s8ExtPred:$src2, (i32 IntRegs:$src1)),
1037 (S4_storeirb_io IntRegs:$src1, 0, s8ExtPred:$src2)>,
1040 // memb(Rx++#s4:0:circ(Mu))=Rt
1041 // memb(Rx++I:circ(Mu))=Rt
1043 // memb(Rx++Mu:brev)=Rt
1044 // memb(gp+#u16:0)=Rt
1048 // TODO: needs to be implemented
1049 // memh(Re=#U6)=Rt.H
1050 // memh(Rs+#s11:1)=Rt.H
1051 let AddedComplexity = 6 in
1052 def : Pat <(truncstorei16 s8ExtPred:$src2, (i32 IntRegs:$src1)),
1053 (S4_storeirh_io IntRegs:$src1, 0, s8ExtPred:$src2)>,
1056 // memh(Rs+Ru<<#u2)=Rt.H
1057 // TODO: needs to be implemented.
1059 // memh(Ru<<#u2+#U6)=Rt.H
1060 // memh(Rx++#s4:1:circ(Mu))=Rt.H
1061 // memh(Rx++#s4:1:circ(Mu))=Rt
1062 // memh(Rx++I:circ(Mu))=Rt.H
1063 // memh(Rx++I:circ(Mu))=Rt
1064 // memh(Rx++Mu)=Rt.H
1066 // memh(Rx++Mu:brev)=Rt.H
1067 // memh(Rx++Mu:brev)=Rt
1068 // memh(gp+#u16:1)=Rt
1069 // if ([!]Pv[.new]) memh(#u6)=Rt.H
1070 // if ([!]Pv[.new]) memh(#u6)=Rt
1073 // if ([!]Pv[.new]) memh(Rs+#u6:1)=Rt.H
1074 // TODO: needs to be implemented.
1076 // if ([!]Pv[.new]) memh(Rx++#s4:1)=Rt.H
1077 // TODO: Needs to be implemented.
1081 // TODO: Needs to be implemented.
1084 let hasSideEffects = 0 in
1085 def STriw_pred_V4 : STInst2<(outs),
1086 (ins MEMri:$addr, PredRegs:$src1),
1087 "Error; should not emit",
1091 let AddedComplexity = 6 in
1092 def : Pat <(store s8ExtPred:$src2, (i32 IntRegs:$src1)),
1093 (S4_storeiri_io IntRegs:$src1, 0, s8ExtPred:$src2)>,
1096 // memw(Rx++#s4:2)=Rt
1097 // memw(Rx++#s4:2:circ(Mu))=Rt
1098 // memw(Rx++I:circ(Mu))=Rt
1100 // memw(Rx++Mu:brev)=Rt
1102 //===----------------------------------------------------------------------===
1104 //===----------------------------------------------------------------------===
1107 //===----------------------------------------------------------------------===//
1109 //===----------------------------------------------------------------------===//
1111 let opNewValue = 2, opExtendable = 1, isExtentSigned = 1, isPredicable = 1 in
1112 class T_store_io_nv <string mnemonic, RegisterClass RC,
1113 Operand ImmOp, bits<2>MajOp>
1114 : NVInst_V4 <(outs),
1115 (ins IntRegs:$src1, ImmOp:$src2, RC:$src3),
1116 mnemonic#"($src1+#$src2) = $src3.new",
1117 [],"",ST_tc_st_SLOT0> {
1119 bits<13> src2; // Actual address offset
1121 bits<11> offsetBits; // Represents offset encoding
1123 let opExtentBits = !if (!eq(mnemonic, "memb"), 11,
1124 !if (!eq(mnemonic, "memh"), 12,
1125 !if (!eq(mnemonic, "memw"), 13, 0)));
1127 let opExtentAlign = !if (!eq(mnemonic, "memb"), 0,
1128 !if (!eq(mnemonic, "memh"), 1,
1129 !if (!eq(mnemonic, "memw"), 2, 0)));
1131 let offsetBits = !if (!eq(mnemonic, "memb"), src2{10-0},
1132 !if (!eq(mnemonic, "memh"), src2{11-1},
1133 !if (!eq(mnemonic, "memw"), src2{12-2}, 0)));
1135 let IClass = 0b1010;
1138 let Inst{26-25} = offsetBits{10-9};
1139 let Inst{24-21} = 0b1101;
1140 let Inst{20-16} = src1;
1141 let Inst{13} = offsetBits{8};
1142 let Inst{12-11} = MajOp;
1143 let Inst{10-8} = src3;
1144 let Inst{7-0} = offsetBits{7-0};
1147 let opExtendable = 2, opNewValue = 3, isPredicated = 1 in
1148 class T_pstore_io_nv <string mnemonic, RegisterClass RC, Operand predImmOp,
1149 bits<2>MajOp, bit PredNot, bit isPredNew>
1150 : NVInst_V4 <(outs),
1151 (ins PredRegs:$src1, IntRegs:$src2, predImmOp:$src3, RC:$src4),
1152 !if(PredNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1153 ") ")#mnemonic#"($src2+#$src3) = $src4.new",
1154 [],"",V2LDST_tc_st_SLOT0> {
1159 bits<6> offsetBits; // Represents offset encoding
1161 let isPredicatedNew = isPredNew;
1162 let isPredicatedFalse = PredNot;
1163 let opExtentBits = !if (!eq(mnemonic, "memb"), 6,
1164 !if (!eq(mnemonic, "memh"), 7,
1165 !if (!eq(mnemonic, "memw"), 8, 0)));
1167 let opExtentAlign = !if (!eq(mnemonic, "memb"), 0,
1168 !if (!eq(mnemonic, "memh"), 1,
1169 !if (!eq(mnemonic, "memw"), 2, 0)));
1171 let offsetBits = !if (!eq(mnemonic, "memb"), src3{5-0},
1172 !if (!eq(mnemonic, "memh"), src3{6-1},
1173 !if (!eq(mnemonic, "memw"), src3{7-2}, 0)));
1175 let IClass = 0b0100;
1178 let Inst{26} = PredNot;
1179 let Inst{25} = isPredNew;
1180 let Inst{24-21} = 0b0101;
1181 let Inst{20-16} = src2;
1182 let Inst{13} = offsetBits{5};
1183 let Inst{12-11} = MajOp;
1184 let Inst{10-8} = src4;
1185 let Inst{7-3} = offsetBits{4-0};
1187 let Inst{1-0} = src1;
1190 // multiclass for new-value store instructions with base + immediate offset.
1192 let mayStore = 1, isNVStore = 1, isNewValue = 1, hasSideEffects = 0,
1194 multiclass ST_Idxd_nv<string mnemonic, string CextOp, RegisterClass RC,
1195 Operand ImmOp, Operand predImmOp, bits<2> MajOp> {
1197 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed in {
1198 def S2_#NAME#new_io : T_store_io_nv <mnemonic, RC, ImmOp, MajOp>;
1200 def S2_p#NAME#newt_io :T_pstore_io_nv <mnemonic, RC, predImmOp, MajOp, 0, 0>;
1201 def S2_p#NAME#newf_io :T_pstore_io_nv <mnemonic, RC, predImmOp, MajOp, 1, 0>;
1203 def S4_p#NAME#newtnew_io :T_pstore_io_nv <mnemonic, RC, predImmOp,
1205 def S4_p#NAME#newfnew_io :T_pstore_io_nv <mnemonic, RC, predImmOp,
1210 let addrMode = BaseImmOffset, InputType = "imm", isCodeGenOnly = 0 in {
1211 let accessSize = ByteAccess in
1212 defm storerb: ST_Idxd_nv<"memb", "STrib", IntRegs, s11_0Ext,
1213 u6_0Ext, 0b00>, AddrModeRel;
1215 let accessSize = HalfWordAccess, opExtentAlign = 1 in
1216 defm storerh: ST_Idxd_nv<"memh", "STrih", IntRegs, s11_1Ext,
1217 u6_1Ext, 0b01>, AddrModeRel;
1219 let accessSize = WordAccess, opExtentAlign = 2 in
1220 defm storeri: ST_Idxd_nv<"memw", "STriw", IntRegs, s11_2Ext,
1221 u6_2Ext, 0b10>, AddrModeRel;
1224 //===----------------------------------------------------------------------===//
1225 // Post increment loads with register offset.
1226 //===----------------------------------------------------------------------===//
1228 let hasNewValue = 1, isCodeGenOnly = 0 in
1229 def L2_loadbsw2_pr : T_load_pr <"membh", IntRegs, 0b0001, HalfWordAccess>;
1231 let isCodeGenOnly = 0 in
1232 def L2_loadbsw4_pr : T_load_pr <"membh", DoubleRegs, 0b0111, WordAccess>;
1234 //===----------------------------------------------------------------------===//
1235 // Template class for non-predicated post increment .new stores
1236 // mem[bhwd](Rx++#s4:[0123])=Nt.new
1237 //===----------------------------------------------------------------------===//
1238 let isPredicable = 1, hasSideEffects = 0, validSubTargets = HasV4SubT,
1239 addrMode = PostInc, isNVStore = 1, isNewValue = 1, opNewValue = 3 in
1240 class T_StorePI_nv <string mnemonic, Operand ImmOp, bits<2> MajOp >
1241 : NVInstPI_V4 <(outs IntRegs:$_dst_),
1242 (ins IntRegs:$src1, ImmOp:$offset, IntRegs:$src2),
1243 mnemonic#"($src1++#$offset) = $src2.new",
1244 [], "$src1 = $_dst_">,
1251 string ImmOpStr = !cast<string>(ImmOp);
1252 let offsetBits = !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2},
1253 !if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1},
1254 /* s4_0Imm */ offset{3-0}));
1255 let IClass = 0b1010;
1257 let Inst{27-21} = 0b1011101;
1258 let Inst{20-16} = src1;
1260 let Inst{12-11} = MajOp;
1261 let Inst{10-8} = src2;
1263 let Inst{6-3} = offsetBits;
1267 //===----------------------------------------------------------------------===//
1268 // Template class for predicated post increment .new stores
1269 // if([!]Pv[.new]) mem[bhwd](Rx++#s4:[0123])=Nt.new
1270 //===----------------------------------------------------------------------===//
1271 let isPredicated = 1, hasSideEffects = 0, validSubTargets = HasV4SubT,
1272 addrMode = PostInc, isNVStore = 1, isNewValue = 1, opNewValue = 4 in
1273 class T_StorePI_nv_pred <string mnemonic, Operand ImmOp,
1274 bits<2> MajOp, bit isPredNot, bit isPredNew >
1275 : NVInstPI_V4 <(outs IntRegs:$_dst_),
1276 (ins PredRegs:$src1, IntRegs:$src2,
1277 ImmOp:$offset, IntRegs:$src3),
1278 !if(isPredNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1279 ") ")#mnemonic#"($src2++#$offset) = $src3.new",
1280 [], "$src2 = $_dst_">,
1288 string ImmOpStr = !cast<string>(ImmOp);
1289 let offsetBits = !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2},
1290 !if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1},
1291 /* s4_0Imm */ offset{3-0}));
1292 let isPredicatedNew = isPredNew;
1293 let isPredicatedFalse = isPredNot;
1295 let IClass = 0b1010;
1297 let Inst{27-21} = 0b1011101;
1298 let Inst{20-16} = src2;
1300 let Inst{12-11} = MajOp;
1301 let Inst{10-8} = src3;
1302 let Inst{7} = isPredNew;
1303 let Inst{6-3} = offsetBits;
1304 let Inst{2} = isPredNot;
1305 let Inst{1-0} = src1;
1308 multiclass ST_PostInc_Pred_nv<string mnemonic, Operand ImmOp,
1309 bits<2> MajOp, bit PredNot> {
1310 def _pi : T_StorePI_nv_pred <mnemonic, ImmOp, MajOp, PredNot, 0>;
1313 def new_pi : T_StorePI_nv_pred <mnemonic, ImmOp, MajOp, PredNot, 1>;
1316 multiclass ST_PostInc_nv<string mnemonic, string BaseOp, Operand ImmOp,
1318 let BaseOpcode = "POST_"#BaseOp in {
1319 def S2_#NAME#_pi : T_StorePI_nv <mnemonic, ImmOp, MajOp>;
1322 defm S2_p#NAME#t : ST_PostInc_Pred_nv <mnemonic, ImmOp, MajOp, 0>;
1323 defm S2_p#NAME#f : ST_PostInc_Pred_nv <mnemonic, ImmOp, MajOp, 1>;
1327 let accessSize = ByteAccess, isCodeGenOnly = 0 in
1328 defm storerbnew: ST_PostInc_nv <"memb", "STrib", s4_0Imm, 0b00>;
1330 let accessSize = HalfWordAccess, isCodeGenOnly = 0 in
1331 defm storerhnew: ST_PostInc_nv <"memh", "STrih", s4_1Imm, 0b01>;
1333 let accessSize = WordAccess, isCodeGenOnly = 0 in
1334 defm storerinew: ST_PostInc_nv <"memw", "STriw", s4_2Imm, 0b10>;
1336 //===----------------------------------------------------------------------===//
1337 // Template class for post increment .new stores with register offset
1338 //===----------------------------------------------------------------------===//
1339 let isNewValue = 1, mayStore = 1, isNVStore = 1, opNewValue = 3 in
1340 class T_StorePI_RegNV <string mnemonic, bits<2> MajOp, MemAccessSize AccessSz>
1341 : NVInstPI_V4 <(outs IntRegs:$_dst_),
1342 (ins IntRegs:$src1, ModRegs:$src2, IntRegs:$src3),
1343 #mnemonic#"($src1++$src2) = $src3.new",
1344 [], "$src1 = $_dst_"> {
1348 let accessSize = AccessSz;
1350 let IClass = 0b1010;
1352 let Inst{27-21} = 0b1101101;
1353 let Inst{20-16} = src1;
1354 let Inst{13} = src2;
1355 let Inst{12-11} = MajOp;
1356 let Inst{10-8} = src3;
1360 let isCodeGenOnly = 0 in {
1361 def S2_storerbnew_pr : T_StorePI_RegNV<"memb", 0b00, ByteAccess>;
1362 def S2_storerhnew_pr : T_StorePI_RegNV<"memh", 0b01, HalfWordAccess>;
1363 def S2_storerinew_pr : T_StorePI_RegNV<"memw", 0b10, WordAccess>;
1366 // memb(Rx++#s4:0:circ(Mu))=Nt.new
1367 // memb(Rx++I:circ(Mu))=Nt.new
1368 // memb(Rx++Mu)=Nt.new
1369 // memb(Rx++Mu:brev)=Nt.new
1370 // memh(Rx++#s4:1:circ(Mu))=Nt.new
1371 // memh(Rx++I:circ(Mu))=Nt.new
1372 // memh(Rx++Mu)=Nt.new
1373 // memh(Rx++Mu:brev)=Nt.new
1375 // memw(Rx++#s4:2:circ(Mu))=Nt.new
1376 // memw(Rx++I:circ(Mu))=Nt.new
1377 // memw(Rx++Mu)=Nt.new
1378 // memw(Rx++Mu:brev)=Nt.new
1380 //===----------------------------------------------------------------------===//
1382 //===----------------------------------------------------------------------===//
1384 //===----------------------------------------------------------------------===//
1386 //===----------------------------------------------------------------------===//
1388 //===----------------------------------------------------------------------===//
1389 // multiclass/template class for the new-value compare jumps with the register
1391 //===----------------------------------------------------------------------===//
1393 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 11,
1394 opExtentAlign = 2 in
1395 class NVJrr_template<string mnemonic, bits<3> majOp, bit NvOpNum,
1396 bit isNegCond, bit isTak>
1398 (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset),
1399 "if ("#!if(isNegCond, "!","")#mnemonic#
1400 "($src1"#!if(!eq(NvOpNum, 0),".new, ",", ")#
1401 "$src2"#!if(!eq(NvOpNum, 1),".new))","))")#" jump:"
1402 #!if(isTak, "t","nt")#" $offset", []> {
1406 bits<3> Ns; // New-Value Operand
1407 bits<5> RegOp; // Non-New-Value Operand
1410 let isTaken = isTak;
1411 let isPredicatedFalse = isNegCond;
1412 let opNewValue{0} = NvOpNum;
1414 let Ns = !if(!eq(NvOpNum, 0), src1{2-0}, src2{2-0});
1415 let RegOp = !if(!eq(NvOpNum, 0), src2, src1);
1417 let IClass = 0b0010;
1419 let Inst{25-23} = majOp;
1420 let Inst{22} = isNegCond;
1421 let Inst{18-16} = Ns;
1422 let Inst{13} = isTak;
1423 let Inst{12-8} = RegOp;
1424 let Inst{21-20} = offset{10-9};
1425 let Inst{7-1} = offset{8-2};
1429 multiclass NVJrr_cond<string mnemonic, bits<3> majOp, bit NvOpNum,
1431 // Branch not taken:
1432 def _nt_V4: NVJrr_template<mnemonic, majOp, NvOpNum, isNegCond, 0>;
1434 def _t_V4: NVJrr_template<mnemonic, majOp, NvOpNum, isNegCond, 1>;
1437 // NvOpNum = 0 -> First Operand is a new-value Register
1438 // NvOpNum = 1 -> Second Operand is a new-value Register
1440 multiclass NVJrr_base<string mnemonic, string BaseOp, bits<3> majOp,
1442 let BaseOpcode = BaseOp#_NVJ in {
1443 defm _t_Jumpnv : NVJrr_cond<mnemonic, majOp, NvOpNum, 0>; // True cond
1444 defm _f_Jumpnv : NVJrr_cond<mnemonic, majOp, NvOpNum, 1>; // False cond
1448 // if ([!]cmp.eq(Ns.new,Rt)) jump:[n]t #r9:2
1449 // if ([!]cmp.gt(Ns.new,Rt)) jump:[n]t #r9:2
1450 // if ([!]cmp.gtu(Ns.new,Rt)) jump:[n]t #r9:2
1451 // if ([!]cmp.gt(Rt,Ns.new)) jump:[n]t #r9:2
1452 // if ([!]cmp.gtu(Rt,Ns.new)) jump:[n]t #r9:2
1454 let isPredicated = 1, isBranch = 1, isNewValue = 1, isTerminator = 1,
1455 Defs = [PC], hasSideEffects = 0, validSubTargets = HasV4SubT,
1456 isCodeGenOnly = 0 in {
1457 defm CMPEQrr : NVJrr_base<"cmp.eq", "CMPEQ", 0b000, 0>, PredRel;
1458 defm CMPGTrr : NVJrr_base<"cmp.gt", "CMPGT", 0b001, 0>, PredRel;
1459 defm CMPGTUrr : NVJrr_base<"cmp.gtu", "CMPGTU", 0b010, 0>, PredRel;
1460 defm CMPLTrr : NVJrr_base<"cmp.gt", "CMPLT", 0b011, 1>, PredRel;
1461 defm CMPLTUrr : NVJrr_base<"cmp.gtu", "CMPLTU", 0b100, 1>, PredRel;
1464 //===----------------------------------------------------------------------===//
1465 // multiclass/template class for the new-value compare jumps instruction
1466 // with a register and an unsigned immediate (U5) operand.
1467 //===----------------------------------------------------------------------===//
1469 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 11,
1470 opExtentAlign = 2 in
1471 class NVJri_template<string mnemonic, bits<3> majOp, bit isNegCond,
1474 (ins IntRegs:$src1, u5Imm:$src2, brtarget:$offset),
1475 "if ("#!if(isNegCond, "!","")#mnemonic#"($src1.new, #$src2)) jump:"
1476 #!if(isTak, "t","nt")#" $offset", []> {
1478 let isTaken = isTak;
1479 let isPredicatedFalse = isNegCond;
1480 let isTaken = isTak;
1486 let IClass = 0b0010;
1488 let Inst{25-23} = majOp;
1489 let Inst{22} = isNegCond;
1490 let Inst{18-16} = src1;
1491 let Inst{13} = isTak;
1492 let Inst{12-8} = src2;
1493 let Inst{21-20} = offset{10-9};
1494 let Inst{7-1} = offset{8-2};
1497 multiclass NVJri_cond<string mnemonic, bits<3> majOp, bit isNegCond> {
1498 // Branch not taken:
1499 def _nt_V4: NVJri_template<mnemonic, majOp, isNegCond, 0>;
1501 def _t_V4: NVJri_template<mnemonic, majOp, isNegCond, 1>;
1504 multiclass NVJri_base<string mnemonic, string BaseOp, bits<3> majOp> {
1505 let BaseOpcode = BaseOp#_NVJri in {
1506 defm _t_Jumpnv : NVJri_cond<mnemonic, majOp, 0>; // True Cond
1507 defm _f_Jumpnv : NVJri_cond<mnemonic, majOp, 1>; // False cond
1511 // if ([!]cmp.eq(Ns.new,#U5)) jump:[n]t #r9:2
1512 // if ([!]cmp.gt(Ns.new,#U5)) jump:[n]t #r9:2
1513 // if ([!]cmp.gtu(Ns.new,#U5)) jump:[n]t #r9:2
1515 let isPredicated = 1, isBranch = 1, isNewValue = 1, isTerminator = 1,
1516 Defs = [PC], hasSideEffects = 0, validSubTargets = HasV4SubT,
1517 isCodeGenOnly = 0 in {
1518 defm CMPEQri : NVJri_base<"cmp.eq", "CMPEQ", 0b000>, PredRel;
1519 defm CMPGTri : NVJri_base<"cmp.gt", "CMPGT", 0b001>, PredRel;
1520 defm CMPGTUri : NVJri_base<"cmp.gtu", "CMPGTU", 0b010>, PredRel;
1523 //===----------------------------------------------------------------------===//
1524 // multiclass/template class for the new-value compare jumps instruction
1525 // with a register and an hardcoded 0/-1 immediate value.
1526 //===----------------------------------------------------------------------===//
1528 let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 11,
1529 opExtentAlign = 2 in
1530 class NVJ_ConstImm_template<string mnemonic, bits<3> majOp, string ImmVal,
1531 bit isNegCond, bit isTak>
1533 (ins IntRegs:$src1, brtarget:$offset),
1534 "if ("#!if(isNegCond, "!","")#mnemonic
1535 #"($src1.new, #"#ImmVal#")) jump:"
1536 #!if(isTak, "t","nt")#" $offset", []> {
1538 let isTaken = isTak;
1539 let isPredicatedFalse = isNegCond;
1540 let isTaken = isTak;
1544 let IClass = 0b0010;
1546 let Inst{25-23} = majOp;
1547 let Inst{22} = isNegCond;
1548 let Inst{18-16} = src1;
1549 let Inst{13} = isTak;
1550 let Inst{21-20} = offset{10-9};
1551 let Inst{7-1} = offset{8-2};
1554 multiclass NVJ_ConstImm_cond<string mnemonic, bits<3> majOp, string ImmVal,
1556 // Branch not taken:
1557 def _nt_V4: NVJ_ConstImm_template<mnemonic, majOp, ImmVal, isNegCond, 0>;
1559 def _t_V4: NVJ_ConstImm_template<mnemonic, majOp, ImmVal, isNegCond, 1>;
1562 multiclass NVJ_ConstImm_base<string mnemonic, string BaseOp, bits<3> majOp,
1564 let BaseOpcode = BaseOp#_NVJ_ConstImm in {
1565 defm _t_Jumpnv : NVJ_ConstImm_cond<mnemonic, majOp, ImmVal, 0>; // True
1566 defm _f_Jumpnv : NVJ_ConstImm_cond<mnemonic, majOp, ImmVal, 1>; // False
1570 // if ([!]tstbit(Ns.new,#0)) jump:[n]t #r9:2
1571 // if ([!]cmp.eq(Ns.new,#-1)) jump:[n]t #r9:2
1572 // if ([!]cmp.gt(Ns.new,#-1)) jump:[n]t #r9:2
1574 let isPredicated = 1, isBranch = 1, isNewValue = 1, isTerminator=1,
1575 Defs = [PC], hasSideEffects = 0, isCodeGenOnly = 0 in {
1576 defm TSTBIT0 : NVJ_ConstImm_base<"tstbit", "TSTBIT", 0b011, "0">, PredRel;
1577 defm CMPEQn1 : NVJ_ConstImm_base<"cmp.eq", "CMPEQ", 0b100, "-1">, PredRel;
1578 defm CMPGTn1 : NVJ_ConstImm_base<"cmp.gt", "CMPGT", 0b101, "-1">, PredRel;
1581 // J4_hintjumpr: Hint indirect conditional jump.
1582 let isBranch = 1, isIndirectBranch = 1, hasSideEffects = 0, isCodeGenOnly = 0 in
1583 def J4_hintjumpr: JRInst <
1588 let IClass = 0b0101;
1589 let Inst{27-21} = 0b0010101;
1590 let Inst{20-16} = Rs;
1593 //===----------------------------------------------------------------------===//
1595 //===----------------------------------------------------------------------===//
1597 //===----------------------------------------------------------------------===//
1599 //===----------------------------------------------------------------------===//
1602 let hasNewValue = 1, isExtendable = 1, opExtendable = 1,
1603 isExtentSigned = 0, opExtentBits = 6, hasSideEffects = 0,
1604 Uses = [PC], validSubTargets = HasV4SubT, isCodeGenOnly = 0 in
1605 def C4_addipc : CRInst <(outs IntRegs:$Rd), (ins u6Ext:$u6),
1606 "$Rd = add(pc, #$u6)", [], "", CR_tc_2_SLOT3 > {
1610 let IClass = 0b0110;
1611 let Inst{27-16} = 0b101001001001;
1612 let Inst{12-7} = u6;
1618 let hasSideEffects = 0 in
1619 class T_LOGICAL_3OP<string MnOp1, string MnOp2, bits<2> OpBits, bit IsNeg>
1620 : CRInst<(outs PredRegs:$Pd),
1621 (ins PredRegs:$Ps, PredRegs:$Pt, PredRegs:$Pu),
1622 "$Pd = " # MnOp1 # "($Ps, " # MnOp2 # "($Pt, " #
1623 !if (IsNeg,"!","") # "$Pu))",
1624 [], "", CR_tc_2early_SLOT23> {
1630 let IClass = 0b0110;
1631 let Inst{27-24} = 0b1011;
1632 let Inst{23} = IsNeg;
1633 let Inst{22-21} = OpBits;
1635 let Inst{17-16} = Ps;
1642 let isCodeGenOnly = 0 in {
1643 def C4_and_and : T_LOGICAL_3OP<"and", "and", 0b00, 0>;
1644 def C4_and_or : T_LOGICAL_3OP<"and", "or", 0b01, 0>;
1645 def C4_or_and : T_LOGICAL_3OP<"or", "and", 0b10, 0>;
1646 def C4_or_or : T_LOGICAL_3OP<"or", "or", 0b11, 0>;
1647 def C4_and_andn : T_LOGICAL_3OP<"and", "and", 0b00, 1>;
1648 def C4_and_orn : T_LOGICAL_3OP<"and", "or", 0b01, 1>;
1649 def C4_or_andn : T_LOGICAL_3OP<"or", "and", 0b10, 1>;
1650 def C4_or_orn : T_LOGICAL_3OP<"or", "or", 0b11, 1>;
1653 //===----------------------------------------------------------------------===//
1655 //===----------------------------------------------------------------------===//
1657 //===----------------------------------------------------------------------===//
1659 //===----------------------------------------------------------------------===//
1661 // Logical with-not instructions.
1662 let validSubTargets = HasV4SubT, isCodeGenOnly = 0 in {
1663 def A4_andnp : T_ALU64_logical<"and", 0b001, 1, 0, 1>;
1664 def A4_ornp : T_ALU64_logical<"or", 0b011, 1, 0, 1>;
1667 let hasNewValue = 1, hasSideEffects = 0, isCodeGenOnly = 0 in
1668 def S4_parity: ALU64Inst<(outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt),
1669 "$Rd = parity($Rs, $Rt)", [], "", ALU64_tc_2_SLOT23> {
1674 let IClass = 0b1101;
1675 let Inst{27-21} = 0b0101111;
1676 let Inst{20-16} = Rs;
1677 let Inst{12-8} = Rt;
1680 // Add and accumulate.
1681 // Rd=add(Rs,add(Ru,#s6))
1682 let isExtentSigned = 1, hasNewValue = 1, isExtendable = 1, opExtentBits = 6,
1683 opExtendable = 3, isCodeGenOnly = 0 in
1684 def S4_addaddi : ALU64Inst <(outs IntRegs:$Rd),
1685 (ins IntRegs:$Rs, IntRegs:$Ru, s6Ext:$s6),
1686 "$Rd = add($Rs, add($Ru, #$s6))" ,
1687 [(set (i32 IntRegs:$Rd), (add (i32 IntRegs:$Rs),
1688 (add (i32 IntRegs:$Ru), s6_16ExtPred:$s6)))],
1689 "", ALU64_tc_2_SLOT23> {
1695 let IClass = 0b1101;
1697 let Inst{27-23} = 0b10110;
1698 let Inst{22-21} = s6{5-4};
1699 let Inst{20-16} = Rs;
1700 let Inst{13} = s6{3};
1701 let Inst{12-8} = Rd;
1702 let Inst{7-5} = s6{2-0};
1706 let isExtentSigned = 1, hasSideEffects = 0, hasNewValue = 1, isExtendable = 1,
1707 opExtentBits = 6, opExtendable = 2, isCodeGenOnly = 0 in
1708 def S4_subaddi: ALU64Inst <(outs IntRegs:$Rd),
1709 (ins IntRegs:$Rs, s6Ext:$s6, IntRegs:$Ru),
1710 "$Rd = add($Rs, sub(#$s6, $Ru))",
1711 [], "", ALU64_tc_2_SLOT23> {
1717 let IClass = 0b1101;
1719 let Inst{27-23} = 0b10111;
1720 let Inst{22-21} = s6{5-4};
1721 let Inst{20-16} = Rs;
1722 let Inst{13} = s6{3};
1723 let Inst{12-8} = Rd;
1724 let Inst{7-5} = s6{2-0};
1729 // Rdd=extract(Rss,#u6,#U6)
1730 // Rdd=extract(Rss,Rtt)
1731 // Rd=extract(Rs,Rtt)
1732 // Rd=extract(Rs,#u5,#U5)
1734 let isCodeGenOnly = 0 in {
1735 def S4_extractp_rp : T_S3op_64 < "extract", 0b11, 0b100, 0>;
1736 def S4_extractp : T_S2op_extract <"extract", 0b1010, DoubleRegs, u6Imm>;
1739 let hasNewValue = 1, isCodeGenOnly = 0 in {
1740 def S4_extract_rp : T_S3op_extract<"extract", 0b01>;
1741 def S4_extract : T_S2op_extract <"extract", 0b1101, IntRegs, u5Imm>;
1744 // Complex add/sub halfwords/words
1745 let Defs = [USR_OVF], isCodeGenOnly = 0 in {
1746 def S4_vxaddsubh : T_S3op_64 < "vxaddsubh", 0b01, 0b100, 0, 1>;
1747 def S4_vxaddsubw : T_S3op_64 < "vxaddsubw", 0b01, 0b000, 0, 1>;
1748 def S4_vxsubaddh : T_S3op_64 < "vxsubaddh", 0b01, 0b110, 0, 1>;
1749 def S4_vxsubaddw : T_S3op_64 < "vxsubaddw", 0b01, 0b010, 0, 1>;
1752 let Defs = [USR_OVF], isCodeGenOnly = 0 in {
1753 def S4_vxaddsubhr : T_S3op_64 < "vxaddsubh", 0b11, 0b000, 0, 1, 1, 1>;
1754 def S4_vxsubaddhr : T_S3op_64 < "vxsubaddh", 0b11, 0b010, 0, 1, 1, 1>;
1757 let Itinerary = M_tc_3x_SLOT23, Defs = [USR_OVF], isCodeGenOnly = 0 in {
1758 def M4_mac_up_s1_sat: T_MType_acc_rr<"+= mpy", 0b011, 0b000, 0, [], 0, 1, 1>;
1759 def M4_nac_up_s1_sat: T_MType_acc_rr<"-= mpy", 0b011, 0b001, 0, [], 0, 1, 1>;
1762 // Logical xor with xor accumulation.
1763 // Rxx^=xor(Rss,Rtt)
1764 let hasSideEffects = 0, isCodeGenOnly = 0 in
1766 : SInst <(outs DoubleRegs:$Rxx),
1767 (ins DoubleRegs:$dst2, DoubleRegs:$Rss, DoubleRegs:$Rtt),
1768 "$Rxx ^= xor($Rss, $Rtt)",
1769 [(set (i64 DoubleRegs:$Rxx),
1770 (xor (i64 DoubleRegs:$dst2), (xor (i64 DoubleRegs:$Rss),
1771 (i64 DoubleRegs:$Rtt))))],
1772 "$dst2 = $Rxx", S_3op_tc_1_SLOT23> {
1777 let IClass = 0b1100;
1779 let Inst{27-23} = 0b10101;
1780 let Inst{20-16} = Rss;
1781 let Inst{12-8} = Rtt;
1782 let Inst{4-0} = Rxx;
1785 // Rotate and reduce bytes
1786 // Rdd=vrcrotate(Rss,Rt,#u2)
1787 let hasSideEffects = 0, isCodeGenOnly = 0 in
1789 : SInst <(outs DoubleRegs:$Rdd),
1790 (ins DoubleRegs:$Rss, IntRegs:$Rt, u2Imm:$u2),
1791 "$Rdd = vrcrotate($Rss, $Rt, #$u2)",
1792 [], "", S_3op_tc_3x_SLOT23> {
1798 let IClass = 0b1100;
1800 let Inst{27-22} = 0b001111;
1801 let Inst{20-16} = Rss;
1802 let Inst{13} = u2{1};
1803 let Inst{12-8} = Rt;
1804 let Inst{7-6} = 0b11;
1805 let Inst{5} = u2{0};
1806 let Inst{4-0} = Rdd;
1809 // Rotate and reduce bytes with accumulation
1810 // Rxx+=vrcrotate(Rss,Rt,#u2)
1811 let hasSideEffects = 0, isCodeGenOnly = 0 in
1812 def S4_vrcrotate_acc
1813 : SInst <(outs DoubleRegs:$Rxx),
1814 (ins DoubleRegs:$dst2, DoubleRegs:$Rss, IntRegs:$Rt, u2Imm:$u2),
1815 "$Rxx += vrcrotate($Rss, $Rt, #$u2)", [],
1816 "$dst2 = $Rxx", S_3op_tc_3x_SLOT23> {
1822 let IClass = 0b1100;
1824 let Inst{27-21} = 0b1011101;
1825 let Inst{20-16} = Rss;
1826 let Inst{13} = u2{1};
1827 let Inst{12-8} = Rt;
1828 let Inst{5} = u2{0};
1829 let Inst{4-0} = Rxx;
1833 // Vector reduce conditional negate halfwords
1834 let hasSideEffects = 0, isCodeGenOnly = 0 in
1836 : SInst <(outs DoubleRegs:$Rxx),
1837 (ins DoubleRegs:$dst2, DoubleRegs:$Rss, IntRegs:$Rt),
1838 "$Rxx += vrcnegh($Rss, $Rt)", [],
1839 "$dst2 = $Rxx", S_3op_tc_3x_SLOT23> {
1844 let IClass = 0b1100;
1846 let Inst{27-21} = 0b1011001;
1847 let Inst{20-16} = Rss;
1849 let Inst{12-8} = Rt;
1850 let Inst{7-5} = 0b111;
1851 let Inst{4-0} = Rxx;
1855 let isCodeGenOnly = 0 in
1856 def A4_bitspliti : T_S2op_2_di <"bitsplit", 0b110, 0b100>;
1858 // Arithmetic/Convergent round
1859 let isCodeGenOnly = 0 in
1860 def A4_cround_ri : T_S2op_2_ii <"cround", 0b111, 0b000>;
1862 let isCodeGenOnly = 0 in
1863 def A4_round_ri : T_S2op_2_ii <"round", 0b111, 0b100>;
1865 let Defs = [USR_OVF], isCodeGenOnly = 0 in
1866 def A4_round_ri_sat : T_S2op_2_ii <"round", 0b111, 0b110, 1>;
1868 // Logical-logical words.
1869 // Compound or-and -- Rx=or(Ru,and(Rx,#s10))
1870 let isExtentSigned = 1, hasNewValue = 1, isExtendable = 1, opExtentBits = 10,
1871 opExtendable = 3, isCodeGenOnly = 0 in
1873 ALU64Inst<(outs IntRegs:$Rx),
1874 (ins IntRegs:$Ru, IntRegs:$_src_, s10Ext:$s10),
1875 "$Rx = or($Ru, and($_src_, #$s10))" ,
1876 [(set (i32 IntRegs:$Rx),
1877 (or (i32 IntRegs:$Ru), (and (i32 IntRegs:$_src_), s10ExtPred:$s10)))] ,
1878 "$_src_ = $Rx", ALU64_tc_2_SLOT23> {
1883 let IClass = 0b1101;
1885 let Inst{27-22} = 0b101001;
1886 let Inst{20-16} = Rx;
1887 let Inst{21} = s10{9};
1888 let Inst{13-5} = s10{8-0};
1892 // Miscellaneous ALU64 instructions.
1894 let hasNewValue = 1, hasSideEffects = 0, isCodeGenOnly = 0 in
1895 def A4_modwrapu: ALU64Inst<(outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt),
1896 "$Rd = modwrap($Rs, $Rt)", [], "", ALU64_tc_2_SLOT23> {
1901 let IClass = 0b1101;
1902 let Inst{27-21} = 0b0011111;
1903 let Inst{20-16} = Rs;
1904 let Inst{12-8} = Rt;
1905 let Inst{7-5} = 0b111;
1909 let hasSideEffects = 0, isCodeGenOnly = 0 in
1910 def A4_bitsplit: ALU64Inst<(outs DoubleRegs:$Rd),
1911 (ins IntRegs:$Rs, IntRegs:$Rt),
1912 "$Rd = bitsplit($Rs, $Rt)", [], "", ALU64_tc_1_SLOT23> {
1917 let IClass = 0b1101;
1918 let Inst{27-24} = 0b0100;
1920 let Inst{20-16} = Rs;
1921 let Inst{12-8} = Rt;
1925 let isCodeGenOnly = 0 in {
1926 // Rx[&|]=xor(Rs,Rt)
1927 def M4_or_xor : T_MType_acc_rr < "|= xor", 0b110, 0b001, 0>;
1928 def M4_and_xor : T_MType_acc_rr < "&= xor", 0b010, 0b010, 0>;
1930 // Rx[&|^]=or(Rs,Rt)
1931 def M4_xor_or : T_MType_acc_rr < "^= or", 0b110, 0b011, 0>;
1933 let CextOpcode = "ORr_ORr" in
1934 def M4_or_or : T_MType_acc_rr < "|= or", 0b110, 0b000, 0>;
1935 def M4_and_or : T_MType_acc_rr < "&= or", 0b010, 0b001, 0>;
1937 // Rx[&|^]=and(Rs,Rt)
1938 def M4_xor_and : T_MType_acc_rr < "^= and", 0b110, 0b010, 0>;
1940 let CextOpcode = "ORr_ANDr" in
1941 def M4_or_and : T_MType_acc_rr < "|= and", 0b010, 0b011, 0>;
1942 def M4_and_and : T_MType_acc_rr < "&= and", 0b010, 0b000, 0>;
1944 // Rx[&|^]=and(Rs,~Rt)
1945 def M4_xor_andn : T_MType_acc_rr < "^= and", 0b001, 0b010, 0, [], 1>;
1946 def M4_or_andn : T_MType_acc_rr < "|= and", 0b001, 0b000, 0, [], 1>;
1947 def M4_and_andn : T_MType_acc_rr < "&= and", 0b001, 0b001, 0, [], 1>;
1950 // Compound or-or and or-and
1951 let isExtentSigned = 1, InputType = "imm", hasNewValue = 1, isExtendable = 1,
1952 opExtentBits = 10, opExtendable = 3 in
1953 class T_CompOR <string mnemonic, bits<2> MajOp, SDNode OpNode>
1954 : MInst_acc <(outs IntRegs:$Rx),
1955 (ins IntRegs:$src1, IntRegs:$Rs, s10Ext:$s10),
1956 "$Rx |= "#mnemonic#"($Rs, #$s10)",
1957 [(set (i32 IntRegs:$Rx), (or (i32 IntRegs:$src1),
1958 (OpNode (i32 IntRegs:$Rs), s10ExtPred:$s10)))],
1959 "$src1 = $Rx", ALU64_tc_2_SLOT23>, ImmRegRel {
1964 let IClass = 0b1101;
1966 let Inst{27-24} = 0b1010;
1967 let Inst{23-22} = MajOp;
1968 let Inst{20-16} = Rs;
1969 let Inst{21} = s10{9};
1970 let Inst{13-5} = s10{8-0};
1974 let CextOpcode = "ORr_ANDr", isCodeGenOnly = 0 in
1975 def S4_or_andi : T_CompOR <"and", 0b00, and>;
1977 let CextOpcode = "ORr_ORr", isCodeGenOnly = 0 in
1978 def S4_or_ori : T_CompOR <"or", 0b10, or>;
1981 // Rd=modwrap(Rs,Rt)
1983 // Rd=cround(Rs,#u5)
1985 // Rd=round(Rs,#u5)[:sat]
1986 // Rd=round(Rs,Rt)[:sat]
1987 // Vector reduce add unsigned halfwords
1988 // Rd=vraddh(Rss,Rtt)
1990 // Rdd=vaddb(Rss,Rtt)
1991 // Vector conditional negate
1992 // Rdd=vcnegh(Rss,Rt)
1993 // Rxx+=vrcnegh(Rss,Rt)
1994 // Vector maximum bytes
1995 // Rdd=vmaxb(Rtt,Rss)
1996 // Vector reduce maximum halfwords
1997 // Rxx=vrmaxh(Rss,Ru)
1998 // Rxx=vrmaxuh(Rss,Ru)
1999 // Vector reduce maximum words
2000 // Rxx=vrmaxuw(Rss,Ru)
2001 // Rxx=vrmaxw(Rss,Ru)
2002 // Vector minimum bytes
2003 // Rdd=vminb(Rtt,Rss)
2004 // Vector reduce minimum halfwords
2005 // Rxx=vrminh(Rss,Ru)
2006 // Rxx=vrminuh(Rss,Ru)
2007 // Vector reduce minimum words
2008 // Rxx=vrminuw(Rss,Ru)
2009 // Rxx=vrminw(Rss,Ru)
2010 // Vector subtract bytes
2011 // Rdd=vsubb(Rss,Rtt)
2013 //===----------------------------------------------------------------------===//
2015 //===----------------------------------------------------------------------===//
2017 //===----------------------------------------------------------------------===//
2019 //===----------------------------------------------------------------------===//
2022 let isCodeGenOnly = 0 in
2023 def S2_brevp : T_S2op_3 <"brev", 0b11, 0b110>;
2026 let isCodeGenOnly = 0 in {
2027 def S2_ct0p : T_COUNT_LEADING_64<"ct0", 0b111, 0b010>;
2028 def S2_ct1p : T_COUNT_LEADING_64<"ct1", 0b111, 0b100>;
2029 def S4_clbpnorm : T_COUNT_LEADING_64<"normamt", 0b011, 0b000>;
2032 def: Pat<(i32 (trunc (cttz (i64 DoubleRegs:$Rss)))),
2033 (S2_ct0p (i64 DoubleRegs:$Rss))>;
2034 def: Pat<(i32 (trunc (cttz (not (i64 DoubleRegs:$Rss))))),
2035 (S2_ct1p (i64 DoubleRegs:$Rss))>;
2037 let hasSideEffects = 0, hasNewValue = 1, isCodeGenOnly = 0 in
2038 def S4_clbaddi : SInst<(outs IntRegs:$Rd), (ins IntRegs:$Rs, s6Imm:$s6),
2039 "$Rd = add(clb($Rs), #$s6)", [], "", S_2op_tc_2_SLOT23> {
2043 let IClass = 0b1000;
2044 let Inst{27-24} = 0b1100;
2045 let Inst{23-21} = 0b001;
2046 let Inst{20-16} = Rs;
2047 let Inst{13-8} = s6;
2048 let Inst{7-5} = 0b000;
2052 let hasSideEffects = 0, hasNewValue = 1, isCodeGenOnly = 0 in
2053 def S4_clbpaddi : SInst<(outs IntRegs:$Rd), (ins DoubleRegs:$Rs, s6Imm:$s6),
2054 "$Rd = add(clb($Rs), #$s6)", [], "", S_2op_tc_2_SLOT23> {
2058 let IClass = 0b1000;
2059 let Inst{27-24} = 0b1000;
2060 let Inst{23-21} = 0b011;
2061 let Inst{20-16} = Rs;
2062 let Inst{13-8} = s6;
2063 let Inst{7-5} = 0b010;
2068 // Bit test/set/clear
2069 let isCodeGenOnly = 0 in {
2070 def S4_ntstbit_i : T_TEST_BIT_IMM<"!tstbit", 0b001>;
2071 def S4_ntstbit_r : T_TEST_BIT_REG<"!tstbit", 1>;
2074 let AddedComplexity = 20 in { // Complexity greater than cmp reg-imm.
2075 def: Pat<(i1 (seteq (and (shl 1, u5ImmPred:$u5), (i32 IntRegs:$Rs)), 0)),
2076 (S4_ntstbit_i (i32 IntRegs:$Rs), u5ImmPred:$u5)>;
2077 def: Pat<(i1 (seteq (and (shl 1, (i32 IntRegs:$Rt)), (i32 IntRegs:$Rs)), 0)),
2078 (S4_ntstbit_r (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))>;
2081 // Add extra complexity to prefer these instructions over bitsset/bitsclr.
2082 // The reason is that tstbit/ntstbit can be folded into a compound instruction:
2083 // if ([!]tstbit(...)) jump ...
2084 let AddedComplexity = 100 in
2085 def: Pat<(i1 (setne (and (i32 IntRegs:$Rs), (i32 Set5ImmPred:$u5)), (i32 0))),
2086 (S2_tstbit_i (i32 IntRegs:$Rs), (BITPOS32 Set5ImmPred:$u5))>;
2088 let AddedComplexity = 100 in
2089 def: Pat<(i1 (seteq (and (i32 IntRegs:$Rs), (i32 Set5ImmPred:$u5)), (i32 0))),
2090 (S4_ntstbit_i (i32 IntRegs:$Rs), (BITPOS32 Set5ImmPred:$u5))>;
2092 let isCodeGenOnly = 0 in {
2093 def C4_nbitsset : T_TEST_BITS_REG<"!bitsset", 0b01, 1>;
2094 def C4_nbitsclr : T_TEST_BITS_REG<"!bitsclr", 0b10, 1>;
2095 def C4_nbitsclri : T_TEST_BITS_IMM<"!bitsclr", 0b10, 1>;
2098 // Do not increase complexity of these patterns. In the DAG, "cmp i8" may be
2099 // represented as a compare against "value & 0xFF", which is an exact match
2100 // for cmpb (same for cmph). The patterns below do not contain any additional
2101 // complexity that would make them preferable, and if they were actually used
2102 // instead of cmpb/cmph, they would result in a compare against register that
2103 // is loaded with the byte/half mask (i.e. 0xFF or 0xFFFF).
2104 def: Pat<(i1 (setne (and I32:$Rs, u6ImmPred:$u6), 0)),
2105 (C4_nbitsclri I32:$Rs, u6ImmPred:$u6)>;
2106 def: Pat<(i1 (setne (and I32:$Rs, I32:$Rt), 0)),
2107 (C4_nbitsclr I32:$Rs, I32:$Rt)>;
2108 def: Pat<(i1 (setne (and I32:$Rs, I32:$Rt), I32:$Rt)),
2109 (C4_nbitsset I32:$Rs, I32:$Rt)>;
2111 //===----------------------------------------------------------------------===//
2113 //===----------------------------------------------------------------------===//
2115 //===----------------------------------------------------------------------===//
2117 //===----------------------------------------------------------------------===//
2119 // Rd=add(#u6,mpyi(Rs,#U6)) -- Multiply by immed and add immed.
2121 let hasNewValue = 1, isExtendable = 1, opExtentBits = 6, opExtendable = 1,
2122 isCodeGenOnly = 0 in
2123 def M4_mpyri_addi : MInst<(outs IntRegs:$Rd),
2124 (ins u6Ext:$u6, IntRegs:$Rs, u6Imm:$U6),
2125 "$Rd = add(#$u6, mpyi($Rs, #$U6))" ,
2126 [(set (i32 IntRegs:$Rd),
2127 (add (mul (i32 IntRegs:$Rs), u6ImmPred:$U6),
2128 u6ExtPred:$u6))] ,"",ALU64_tc_3x_SLOT23> {
2134 let IClass = 0b1101;
2136 let Inst{27-24} = 0b1000;
2137 let Inst{23} = U6{5};
2138 let Inst{22-21} = u6{5-4};
2139 let Inst{20-16} = Rs;
2140 let Inst{13} = u6{3};
2141 let Inst{12-8} = Rd;
2142 let Inst{7-5} = u6{2-0};
2143 let Inst{4-0} = U6{4-0};
2146 // Rd=add(#u6,mpyi(Rs,Rt))
2147 let CextOpcode = "ADD_MPY", InputType = "imm", hasNewValue = 1,
2148 isExtendable = 1, opExtentBits = 6, opExtendable = 1, isCodeGenOnly = 0 in
2149 def M4_mpyrr_addi : MInst <(outs IntRegs:$Rd),
2150 (ins u6Ext:$u6, IntRegs:$Rs, IntRegs:$Rt),
2151 "$Rd = add(#$u6, mpyi($Rs, $Rt))" ,
2152 [(set (i32 IntRegs:$Rd),
2153 (add (mul (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)), u6ExtPred:$u6))],
2154 "", ALU64_tc_3x_SLOT23>, ImmRegRel {
2160 let IClass = 0b1101;
2162 let Inst{27-23} = 0b01110;
2163 let Inst{22-21} = u6{5-4};
2164 let Inst{20-16} = Rs;
2165 let Inst{13} = u6{3};
2166 let Inst{12-8} = Rt;
2167 let Inst{7-5} = u6{2-0};
2171 let hasNewValue = 1 in
2172 class T_AddMpy <bit MajOp, PatLeaf ImmPred, dag ins>
2173 : ALU64Inst <(outs IntRegs:$dst), ins,
2174 "$dst = add($src1, mpyi("#!if(MajOp,"$src3, #$src2))",
2176 [(set (i32 IntRegs:$dst),
2177 (add (i32 IntRegs:$src1), (mul (i32 IntRegs:$src3), ImmPred:$src2)))],
2178 "", ALU64_tc_3x_SLOT23> {
2184 let IClass = 0b1101;
2186 bits<6> ImmValue = !if(MajOp, src2{5-0}, src2{7-2});
2188 let Inst{27-24} = 0b1111;
2189 let Inst{23} = MajOp;
2190 let Inst{22-21} = ImmValue{5-4};
2191 let Inst{20-16} = src3;
2192 let Inst{13} = ImmValue{3};
2193 let Inst{12-8} = dst;
2194 let Inst{7-5} = ImmValue{2-0};
2195 let Inst{4-0} = src1;
2198 let isCodeGenOnly = 0 in
2199 def M4_mpyri_addr_u2 : T_AddMpy<0b0, u6_2ImmPred,
2200 (ins IntRegs:$src1, u6_2Imm:$src2, IntRegs:$src3)>;
2202 let isExtendable = 1, opExtentBits = 6, opExtendable = 3,
2203 CextOpcode = "ADD_MPY", InputType = "imm", isCodeGenOnly = 0 in
2204 def M4_mpyri_addr : T_AddMpy<0b1, u6ExtPred,
2205 (ins IntRegs:$src1, IntRegs:$src3, u6Ext:$src2)>, ImmRegRel;
2207 // Rx=add(Ru,mpyi(Rx,Rs))
2208 let validSubTargets = HasV4SubT, CextOpcode = "ADD_MPY", InputType = "reg",
2209 hasNewValue = 1, isCodeGenOnly = 0 in
2210 def M4_mpyrr_addr: MInst_acc <(outs IntRegs:$Rx),
2211 (ins IntRegs:$Ru, IntRegs:$_src_, IntRegs:$Rs),
2212 "$Rx = add($Ru, mpyi($_src_, $Rs))",
2213 [(set (i32 IntRegs:$Rx), (add (i32 IntRegs:$Ru),
2214 (mul (i32 IntRegs:$_src_), (i32 IntRegs:$Rs))))],
2215 "$_src_ = $Rx", M_tc_3x_SLOT23>, ImmRegRel {
2220 let IClass = 0b1110;
2222 let Inst{27-21} = 0b0011000;
2223 let Inst{12-8} = Rx;
2225 let Inst{20-16} = Rs;
2228 // Rd=add(##,mpyi(Rs,#U6))
2229 def : Pat <(add (mul (i32 IntRegs:$src2), u6ImmPred:$src3),
2230 (HexagonCONST32 tglobaladdr:$src1)),
2231 (i32 (M4_mpyri_addi tglobaladdr:$src1, IntRegs:$src2,
2234 // Rd=add(##,mpyi(Rs,Rt))
2235 def : Pat <(add (mul (i32 IntRegs:$src2), (i32 IntRegs:$src3)),
2236 (HexagonCONST32 tglobaladdr:$src1)),
2237 (i32 (M4_mpyrr_addi tglobaladdr:$src1, IntRegs:$src2,
2240 // Vector reduce multiply word by signed half (32x16)
2241 //Rdd=vrmpyweh(Rss,Rtt)[:<<1]
2242 let isCodeGenOnly = 0 in {
2243 def M4_vrmpyeh_s0 : T_M2_vmpy<"vrmpyweh", 0b010, 0b100, 0, 0, 0>;
2244 def M4_vrmpyeh_s1 : T_M2_vmpy<"vrmpyweh", 0b110, 0b100, 1, 0, 0>;
2247 //Rdd=vrmpywoh(Rss,Rtt)[:<<1]
2248 let isCodeGenOnly = 0 in {
2249 def M4_vrmpyoh_s0 : T_M2_vmpy<"vrmpywoh", 0b001, 0b010, 0, 0, 0>;
2250 def M4_vrmpyoh_s1 : T_M2_vmpy<"vrmpywoh", 0b101, 0b010, 1, 0, 0>;
2252 //Rdd+=vrmpyweh(Rss,Rtt)[:<<1]
2253 let isCodeGenOnly = 0 in {
2254 def M4_vrmpyeh_acc_s0: T_M2_vmpy_acc<"vrmpyweh", 0b001, 0b110, 0, 0>;
2255 def M4_vrmpyeh_acc_s1: T_M2_vmpy_acc<"vrmpyweh", 0b101, 0b110, 1, 0>;
2258 //Rdd=vrmpywoh(Rss,Rtt)[:<<1]
2259 let isCodeGenOnly = 0 in {
2260 def M4_vrmpyoh_acc_s0: T_M2_vmpy_acc<"vrmpywoh", 0b011, 0b110, 0, 0>;
2261 def M4_vrmpyoh_acc_s1: T_M2_vmpy_acc<"vrmpywoh", 0b111, 0b110, 1, 0>;
2264 // Vector multiply halfwords, signed by unsigned
2265 // Rdd=vmpyhsu(Rs,Rt)[:<<]:sat
2266 let isCodeGenOnly = 0 in {
2267 def M2_vmpy2su_s0 : T_XTYPE_mpy64 < "vmpyhsu", 0b000, 0b111, 1, 0, 0>;
2268 def M2_vmpy2su_s1 : T_XTYPE_mpy64 < "vmpyhsu", 0b100, 0b111, 1, 1, 0>;
2271 // Rxx+=vmpyhsu(Rs,Rt)[:<<1]:sat
2272 let isCodeGenOnly = 0 in {
2273 def M2_vmac2su_s0 : T_XTYPE_mpy64_acc < "vmpyhsu", "+", 0b011, 0b101, 1, 0, 0>;
2274 def M2_vmac2su_s1 : T_XTYPE_mpy64_acc < "vmpyhsu", "+", 0b111, 0b101, 1, 1, 0>;
2277 // Vector polynomial multiply halfwords
2278 // Rdd=vpmpyh(Rs,Rt)
2279 let isCodeGenOnly = 0 in
2280 def M4_vpmpyh : T_XTYPE_mpy64 < "vpmpyh", 0b110, 0b111, 0, 0, 0>;
2282 // Rxx^=vpmpyh(Rs,Rt)
2283 let isCodeGenOnly = 0 in
2284 def M4_vpmpyh_acc : T_XTYPE_mpy64_acc < "vpmpyh", "^", 0b101, 0b111, 0, 0, 0>;
2286 // Polynomial multiply words
2288 let isCodeGenOnly = 0 in
2289 def M4_pmpyw : T_XTYPE_mpy64 < "pmpyw", 0b010, 0b111, 0, 0, 0>;
2291 // Rxx^=pmpyw(Rs,Rt)
2292 let isCodeGenOnly = 0 in
2293 def M4_pmpyw_acc : T_XTYPE_mpy64_acc < "pmpyw", "^", 0b001, 0b111, 0, 0, 0>;
2295 //===----------------------------------------------------------------------===//
2297 //===----------------------------------------------------------------------===//
2300 //===----------------------------------------------------------------------===//
2302 //===----------------------------------------------------------------------===//
2303 // Shift by immediate and accumulate/logical.
2304 // Rx=add(#u8,asl(Rx,#U5)) Rx=add(#u8,lsr(Rx,#U5))
2305 // Rx=sub(#u8,asl(Rx,#U5)) Rx=sub(#u8,lsr(Rx,#U5))
2306 // Rx=and(#u8,asl(Rx,#U5)) Rx=and(#u8,lsr(Rx,#U5))
2307 // Rx=or(#u8,asl(Rx,#U5)) Rx=or(#u8,lsr(Rx,#U5))
2308 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8,
2309 hasNewValue = 1, opNewValue = 0, validSubTargets = HasV4SubT in
2310 class T_S4_ShiftOperate<string MnOp, string MnSh, SDNode Op, SDNode Sh,
2311 bit asl_lsr, bits<2> MajOp, InstrItinClass Itin>
2312 : MInst_acc<(outs IntRegs:$Rd), (ins u8Ext:$u8, IntRegs:$Rx, u5Imm:$U5),
2313 "$Rd = "#MnOp#"(#$u8, "#MnSh#"($Rx, #$U5))",
2314 [(set (i32 IntRegs:$Rd),
2315 (Op (Sh I32:$Rx, u5ImmPred:$U5), u8ExtPred:$u8))],
2316 "$Rd = $Rx", Itin> {
2323 let IClass = 0b1101;
2324 let Inst{27-24} = 0b1110;
2325 let Inst{23-21} = u8{7-5};
2326 let Inst{20-16} = Rd;
2327 let Inst{13} = u8{4};
2328 let Inst{12-8} = U5;
2329 let Inst{7-5} = u8{3-1};
2330 let Inst{4} = asl_lsr;
2331 let Inst{3} = u8{0};
2332 let Inst{2-1} = MajOp;
2335 multiclass T_ShiftOperate<string mnemonic, SDNode Op, bits<2> MajOp,
2336 InstrItinClass Itin> {
2337 def _asl_ri : T_S4_ShiftOperate<mnemonic, "asl", Op, shl, 0, MajOp, Itin>;
2338 def _lsr_ri : T_S4_ShiftOperate<mnemonic, "lsr", Op, srl, 1, MajOp, Itin>;
2341 let AddedComplexity = 200, isCodeGenOnly = 0 in {
2342 defm S4_addi : T_ShiftOperate<"add", add, 0b10, ALU64_tc_2_SLOT23>;
2343 defm S4_andi : T_ShiftOperate<"and", and, 0b00, ALU64_tc_2_SLOT23>;
2346 let AddedComplexity = 30, isCodeGenOnly = 0 in
2347 defm S4_ori : T_ShiftOperate<"or", or, 0b01, ALU64_tc_1_SLOT23>;
2349 let isCodeGenOnly = 0 in
2350 defm S4_subi : T_ShiftOperate<"sub", sub, 0b11, ALU64_tc_1_SLOT23>;
2352 // Vector conditional negate
2353 // Rdd=vcnegh(Rss,Rt)
2354 let Defs = [USR_OVF], Itinerary = S_3op_tc_2_SLOT23, isCodeGenOnly = 0 in
2355 def S2_vcnegh : T_S3op_shiftVect < "vcnegh", 0b11, 0b01>;
2357 // Rd=[cround|round](Rs,Rt)
2358 let hasNewValue = 1, Itinerary = S_3op_tc_2_SLOT23, isCodeGenOnly = 0 in {
2359 def A4_cround_rr : T_S3op_3 < "cround", IntRegs, 0b11, 0b00>;
2360 def A4_round_rr : T_S3op_3 < "round", IntRegs, 0b11, 0b10>;
2363 // Rd=round(Rs,Rt):sat
2364 let hasNewValue = 1, Defs = [USR_OVF], Itinerary = S_3op_tc_2_SLOT23,
2365 isCodeGenOnly = 0 in
2366 def A4_round_rr_sat : T_S3op_3 < "round", IntRegs, 0b11, 0b11, 1>;
2368 // Rd=[cmpyiwh|cmpyrwh](Rss,Rt):<<1:rnd:sat
2369 let Defs = [USR_OVF], Itinerary = S_3op_tc_3x_SLOT23, isCodeGenOnly = 0 in {
2370 def M4_cmpyi_wh : T_S3op_8<"cmpyiwh", 0b100, 1, 1, 1>;
2371 def M4_cmpyr_wh : T_S3op_8<"cmpyrwh", 0b110, 1, 1, 1>;
2374 // Rdd=[add|sub](Rss,Rtt,Px):carry
2375 let isPredicateLate = 1, hasSideEffects = 0 in
2376 class T_S3op_carry <string mnemonic, bits<3> MajOp>
2377 : SInst < (outs DoubleRegs:$Rdd, PredRegs:$Px),
2378 (ins DoubleRegs:$Rss, DoubleRegs:$Rtt, PredRegs:$Pu),
2379 "$Rdd = "#mnemonic#"($Rss, $Rtt, $Pu):carry",
2380 [], "$Px = $Pu", S_3op_tc_1_SLOT23 > {
2386 let IClass = 0b1100;
2388 let Inst{27-24} = 0b0010;
2389 let Inst{23-21} = MajOp;
2390 let Inst{20-16} = Rss;
2391 let Inst{12-8} = Rtt;
2393 let Inst{4-0} = Rdd;
2396 let isCodeGenOnly = 0 in {
2397 def A4_addp_c : T_S3op_carry < "add", 0b110 >;
2398 def A4_subp_c : T_S3op_carry < "sub", 0b111 >;
2401 let Itinerary = S_3op_tc_3_SLOT23, hasSideEffects = 0 in
2402 class T_S3op_6 <string mnemonic, bits<3> MinOp, bit isUnsigned>
2403 : SInst <(outs DoubleRegs:$Rxx),
2404 (ins DoubleRegs:$dst2, DoubleRegs:$Rss, IntRegs:$Ru),
2405 "$Rxx = "#mnemonic#"($Rss, $Ru)" ,
2406 [] , "$dst2 = $Rxx"> {
2411 let IClass = 0b1100;
2413 let Inst{27-21} = 0b1011001;
2414 let Inst{20-16} = Rss;
2415 let Inst{13} = isUnsigned;
2416 let Inst{12-8} = Rxx;
2417 let Inst{7-5} = MinOp;
2421 // Vector reduce maximum halfwords
2422 // Rxx=vrmax[u]h(Rss,Ru)
2423 let isCodeGenOnly = 0 in {
2424 def A4_vrmaxh : T_S3op_6 < "vrmaxh", 0b001, 0>;
2425 def A4_vrmaxuh : T_S3op_6 < "vrmaxuh", 0b001, 1>;
2427 // Vector reduce maximum words
2428 // Rxx=vrmax[u]w(Rss,Ru)
2429 let isCodeGenOnly = 0 in {
2430 def A4_vrmaxw : T_S3op_6 < "vrmaxw", 0b010, 0>;
2431 def A4_vrmaxuw : T_S3op_6 < "vrmaxuw", 0b010, 1>;
2433 // Vector reduce minimum halfwords
2434 // Rxx=vrmin[u]h(Rss,Ru)
2435 let isCodeGenOnly = 0 in {
2436 def A4_vrminh : T_S3op_6 < "vrminh", 0b101, 0>;
2437 def A4_vrminuh : T_S3op_6 < "vrminuh", 0b101, 1>;
2440 // Vector reduce minimum words
2441 // Rxx=vrmin[u]w(Rss,Ru)
2442 let isCodeGenOnly = 0 in {
2443 def A4_vrminw : T_S3op_6 < "vrminw", 0b110, 0>;
2444 def A4_vrminuw : T_S3op_6 < "vrminuw", 0b110, 1>;
2447 // Shift an immediate left by register amount.
2448 let hasNewValue = 1, hasSideEffects = 0, isCodeGenOnly = 0 in
2449 def S4_lsli: SInst <(outs IntRegs:$Rd), (ins s6Imm:$s6, IntRegs:$Rt),
2450 "$Rd = lsl(#$s6, $Rt)" ,
2451 [(set (i32 IntRegs:$Rd), (shl s6ImmPred:$s6,
2452 (i32 IntRegs:$Rt)))],
2453 "", S_3op_tc_1_SLOT23> {
2458 let IClass = 0b1100;
2460 let Inst{27-22} = 0b011010;
2461 let Inst{20-16} = s6{5-1};
2462 let Inst{12-8} = Rt;
2463 let Inst{7-6} = 0b11;
2465 let Inst{5} = s6{0};
2468 //===----------------------------------------------------------------------===//
2470 //===----------------------------------------------------------------------===//
2472 //===----------------------------------------------------------------------===//
2473 // MEMOP: Word, Half, Byte
2474 //===----------------------------------------------------------------------===//
2476 def MEMOPIMM : SDNodeXForm<imm, [{
2477 // Call the transformation function XformM5ToU5Imm to get the negative
2478 // immediate's positive counterpart.
2479 int32_t imm = N->getSExtValue();
2480 return XformM5ToU5Imm(imm);
2483 def MEMOPIMM_HALF : SDNodeXForm<imm, [{
2484 // -1 .. -31 represented as 65535..65515
2485 // assigning to a short restores our desired signed value.
2486 // Call the transformation function XformM5ToU5Imm to get the negative
2487 // immediate's positive counterpart.
2488 int16_t imm = N->getSExtValue();
2489 return XformM5ToU5Imm(imm);
2492 def MEMOPIMM_BYTE : SDNodeXForm<imm, [{
2493 // -1 .. -31 represented as 255..235
2494 // assigning to a char restores our desired signed value.
2495 // Call the transformation function XformM5ToU5Imm to get the negative
2496 // immediate's positive counterpart.
2497 int8_t imm = N->getSExtValue();
2498 return XformM5ToU5Imm(imm);
2501 def SETMEMIMM : SDNodeXForm<imm, [{
2502 // Return the bit position we will set [0-31].
2504 int32_t imm = N->getSExtValue();
2505 return XformMskToBitPosU5Imm(imm);
2508 def CLRMEMIMM : SDNodeXForm<imm, [{
2509 // Return the bit position we will clear [0-31].
2511 // we bit negate the value first
2512 int32_t imm = ~(N->getSExtValue());
2513 return XformMskToBitPosU5Imm(imm);
2516 def SETMEMIMM_SHORT : SDNodeXForm<imm, [{
2517 // Return the bit position we will set [0-15].
2519 int16_t imm = N->getSExtValue();
2520 return XformMskToBitPosU4Imm(imm);
2523 def CLRMEMIMM_SHORT : SDNodeXForm<imm, [{
2524 // Return the bit position we will clear [0-15].
2526 // we bit negate the value first
2527 int16_t imm = ~(N->getSExtValue());
2528 return XformMskToBitPosU4Imm(imm);
2531 def SETMEMIMM_BYTE : SDNodeXForm<imm, [{
2532 // Return the bit position we will set [0-7].
2534 int8_t imm = N->getSExtValue();
2535 return XformMskToBitPosU3Imm(imm);
2538 def CLRMEMIMM_BYTE : SDNodeXForm<imm, [{
2539 // Return the bit position we will clear [0-7].
2541 // we bit negate the value first
2542 int8_t imm = ~(N->getSExtValue());
2543 return XformMskToBitPosU3Imm(imm);
2546 //===----------------------------------------------------------------------===//
2547 // Template class for MemOp instructions with the register value.
2548 //===----------------------------------------------------------------------===//
2549 class MemOp_rr_base <string opc, bits<2> opcBits, Operand ImmOp,
2550 string memOp, bits<2> memOpBits> :
2552 (ins IntRegs:$base, ImmOp:$offset, IntRegs:$delta),
2553 opc#"($base+#$offset)"#memOp#"$delta",
2555 Requires<[UseMEMOP]> {
2560 bits<6> offsetBits; // memb - u6:0 , memh - u6:1, memw - u6:2
2562 let offsetBits = !if (!eq(opcBits, 0b00), offset{5-0},
2563 !if (!eq(opcBits, 0b01), offset{6-1},
2564 !if (!eq(opcBits, 0b10), offset{7-2},0)));
2566 let opExtentAlign = opcBits;
2567 let IClass = 0b0011;
2568 let Inst{27-24} = 0b1110;
2569 let Inst{22-21} = opcBits;
2570 let Inst{20-16} = base;
2572 let Inst{12-7} = offsetBits;
2573 let Inst{6-5} = memOpBits;
2574 let Inst{4-0} = delta;
2577 //===----------------------------------------------------------------------===//
2578 // Template class for MemOp instructions with the immediate value.
2579 //===----------------------------------------------------------------------===//
2580 class MemOp_ri_base <string opc, bits<2> opcBits, Operand ImmOp,
2581 string memOp, bits<2> memOpBits> :
2583 (ins IntRegs:$base, ImmOp:$offset, u5Imm:$delta),
2584 opc#"($base+#$offset)"#memOp#"#$delta"
2585 #!if(memOpBits{1},")", ""), // clrbit, setbit - include ')'
2587 Requires<[UseMEMOP]> {
2592 bits<6> offsetBits; // memb - u6:0 , memh - u6:1, memw - u6:2
2594 let offsetBits = !if (!eq(opcBits, 0b00), offset{5-0},
2595 !if (!eq(opcBits, 0b01), offset{6-1},
2596 !if (!eq(opcBits, 0b10), offset{7-2},0)));
2598 let opExtentAlign = opcBits;
2599 let IClass = 0b0011;
2600 let Inst{27-24} = 0b1111;
2601 let Inst{22-21} = opcBits;
2602 let Inst{20-16} = base;
2604 let Inst{12-7} = offsetBits;
2605 let Inst{6-5} = memOpBits;
2606 let Inst{4-0} = delta;
2609 // multiclass to define MemOp instructions with register operand.
2610 multiclass MemOp_rr<string opc, bits<2> opcBits, Operand ImmOp> {
2611 def L4_add#NAME : MemOp_rr_base <opc, opcBits, ImmOp, " += ", 0b00>; // add
2612 def L4_sub#NAME : MemOp_rr_base <opc, opcBits, ImmOp, " -= ", 0b01>; // sub
2613 def L4_and#NAME : MemOp_rr_base <opc, opcBits, ImmOp, " &= ", 0b10>; // and
2614 def L4_or#NAME : MemOp_rr_base <opc, opcBits, ImmOp, " |= ", 0b11>; // or
2617 // multiclass to define MemOp instructions with immediate Operand.
2618 multiclass MemOp_ri<string opc, bits<2> opcBits, Operand ImmOp> {
2619 def L4_iadd#NAME : MemOp_ri_base <opc, opcBits, ImmOp, " += ", 0b00 >;
2620 def L4_isub#NAME : MemOp_ri_base <opc, opcBits, ImmOp, " -= ", 0b01 >;
2621 def L4_iand#NAME : MemOp_ri_base<opc, opcBits, ImmOp, " = clrbit(", 0b10>;
2622 def L4_ior#NAME : MemOp_ri_base<opc, opcBits, ImmOp, " = setbit(", 0b11>;
2625 multiclass MemOp_base <string opc, bits<2> opcBits, Operand ImmOp> {
2626 defm _#NAME : MemOp_rr <opc, opcBits, ImmOp>;
2627 defm _#NAME : MemOp_ri <opc, opcBits, ImmOp>;
2630 // Define MemOp instructions.
2631 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0,
2632 validSubTargets =HasV4SubT in {
2633 let opExtentBits = 6, accessSize = ByteAccess, isCodeGenOnly = 0 in
2634 defm memopb_io : MemOp_base <"memb", 0b00, u6_0Ext>;
2636 let opExtentBits = 7, accessSize = HalfWordAccess, isCodeGenOnly = 0 in
2637 defm memoph_io : MemOp_base <"memh", 0b01, u6_1Ext>;
2639 let opExtentBits = 8, accessSize = WordAccess, isCodeGenOnly = 0 in
2640 defm memopw_io : MemOp_base <"memw", 0b10, u6_2Ext>;
2643 //===----------------------------------------------------------------------===//
2644 // Multiclass to define 'Def Pats' for ALU operations on the memory
2645 // Here value used for the ALU operation is an immediate value.
2646 // mem[bh](Rs+#0) += #U5
2647 // mem[bh](Rs+#u6) += #U5
2648 //===----------------------------------------------------------------------===//
2650 multiclass MemOpi_u5Pats <PatFrag ldOp, PatFrag stOp, PatLeaf ExtPred,
2651 InstHexagon MI, SDNode OpNode> {
2652 let AddedComplexity = 180 in
2653 def : Pat < (stOp (OpNode (ldOp IntRegs:$addr), u5ImmPred:$addend),
2655 (MI IntRegs:$addr, #0, u5ImmPred:$addend )>;
2657 let AddedComplexity = 190 in
2658 def : Pat <(stOp (OpNode (ldOp (add IntRegs:$base, ExtPred:$offset)),
2660 (add IntRegs:$base, ExtPred:$offset)),
2661 (MI IntRegs:$base, ExtPred:$offset, u5ImmPred:$addend)>;
2664 multiclass MemOpi_u5ALUOp<PatFrag ldOp, PatFrag stOp, PatLeaf ExtPred,
2665 InstHexagon addMI, InstHexagon subMI> {
2666 defm : MemOpi_u5Pats<ldOp, stOp, ExtPred, addMI, add>;
2667 defm : MemOpi_u5Pats<ldOp, stOp, ExtPred, subMI, sub>;
2670 multiclass MemOpi_u5ExtType<PatFrag ldOpByte, PatFrag ldOpHalf > {
2672 defm : MemOpi_u5ALUOp <ldOpHalf, truncstorei16, u6_1ExtPred,
2673 L4_iadd_memoph_io, L4_isub_memoph_io>;
2675 defm : MemOpi_u5ALUOp <ldOpByte, truncstorei8, u6ExtPred,
2676 L4_iadd_memopb_io, L4_isub_memopb_io>;
2679 let Predicates = [HasV4T, UseMEMOP] in {
2680 defm : MemOpi_u5ExtType<zextloadi8, zextloadi16>; // zero extend
2681 defm : MemOpi_u5ExtType<sextloadi8, sextloadi16>; // sign extend
2682 defm : MemOpi_u5ExtType<extloadi8, extloadi16>; // any extend
2685 defm : MemOpi_u5ALUOp <load, store, u6_2ExtPred, L4_iadd_memopw_io,
2689 //===----------------------------------------------------------------------===//
2690 // multiclass to define 'Def Pats' for ALU operations on the memory.
2691 // Here value used for the ALU operation is a negative value.
2692 // mem[bh](Rs+#0) += #m5
2693 // mem[bh](Rs+#u6) += #m5
2694 //===----------------------------------------------------------------------===//
2696 multiclass MemOpi_m5Pats <PatFrag ldOp, PatFrag stOp, PatLeaf extPred,
2697 PatLeaf immPred, ComplexPattern addrPred,
2698 SDNodeXForm xformFunc, InstHexagon MI> {
2699 let AddedComplexity = 190 in
2700 def : Pat <(stOp (add (ldOp IntRegs:$addr), immPred:$subend),
2702 (MI IntRegs:$addr, #0, (xformFunc immPred:$subend) )>;
2704 let AddedComplexity = 195 in
2705 def : Pat<(stOp (add (ldOp (add IntRegs:$base, extPred:$offset)),
2707 (add IntRegs:$base, extPred:$offset)),
2708 (MI IntRegs:$base, extPred:$offset, (xformFunc immPred:$subend))>;
2711 multiclass MemOpi_m5ExtType<PatFrag ldOpByte, PatFrag ldOpHalf > {
2713 defm : MemOpi_m5Pats <ldOpHalf, truncstorei16, u6_1ExtPred, m5HImmPred,
2714 ADDRriU6_1, MEMOPIMM_HALF, L4_isub_memoph_io>;
2716 defm : MemOpi_m5Pats <ldOpByte, truncstorei8, u6ExtPred, m5BImmPred,
2717 ADDRriU6_0, MEMOPIMM_BYTE, L4_isub_memopb_io>;
2720 let Predicates = [HasV4T, UseMEMOP] in {
2721 defm : MemOpi_m5ExtType<zextloadi8, zextloadi16>; // zero extend
2722 defm : MemOpi_m5ExtType<sextloadi8, sextloadi16>; // sign extend
2723 defm : MemOpi_m5ExtType<extloadi8, extloadi16>; // any extend
2726 defm : MemOpi_m5Pats <load, store, u6_2ExtPred, m5ImmPred,
2727 ADDRriU6_2, MEMOPIMM, L4_isub_memopw_io>;
2730 //===----------------------------------------------------------------------===//
2731 // Multiclass to define 'def Pats' for bit operations on the memory.
2732 // mem[bhw](Rs+#0) = [clrbit|setbit](#U5)
2733 // mem[bhw](Rs+#u6) = [clrbit|setbit](#U5)
2734 //===----------------------------------------------------------------------===//
2736 multiclass MemOpi_bitPats <PatFrag ldOp, PatFrag stOp, PatLeaf immPred,
2737 PatLeaf extPred, ComplexPattern addrPred,
2738 SDNodeXForm xformFunc, InstHexagon MI, SDNode OpNode> {
2740 // mem[bhw](Rs+#u6:[012]) = [clrbit|setbit](#U5)
2741 let AddedComplexity = 250 in
2742 def : Pat<(stOp (OpNode (ldOp (add IntRegs:$base, extPred:$offset)),
2744 (add IntRegs:$base, extPred:$offset)),
2745 (MI IntRegs:$base, extPred:$offset, (xformFunc immPred:$bitend))>;
2747 // mem[bhw](Rs+#0) = [clrbit|setbit](#U5)
2748 let AddedComplexity = 225 in
2749 def : Pat <(stOp (OpNode (ldOp (addrPred IntRegs:$addr, extPred:$offset)),
2751 (addrPred (i32 IntRegs:$addr), extPred:$offset)),
2752 (MI IntRegs:$addr, extPred:$offset, (xformFunc immPred:$bitend))>;
2755 multiclass MemOpi_bitExtType<PatFrag ldOpByte, PatFrag ldOpHalf > {
2757 defm : MemOpi_bitPats<ldOpByte, truncstorei8, Clr3ImmPred, u6ExtPred,
2758 ADDRriU6_0, CLRMEMIMM_BYTE, L4_iand_memopb_io, and>;
2760 defm : MemOpi_bitPats<ldOpByte, truncstorei8, Set3ImmPred, u6ExtPred,
2761 ADDRriU6_0, SETMEMIMM_BYTE, L4_ior_memopb_io, or>;
2762 // Half Word - clrbit
2763 defm : MemOpi_bitPats<ldOpHalf, truncstorei16, Clr4ImmPred, u6_1ExtPred,
2764 ADDRriU6_1, CLRMEMIMM_SHORT, L4_iand_memoph_io, and>;
2765 // Half Word - setbit
2766 defm : MemOpi_bitPats<ldOpHalf, truncstorei16, Set4ImmPred, u6_1ExtPred,
2767 ADDRriU6_1, SETMEMIMM_SHORT, L4_ior_memoph_io, or>;
2770 let Predicates = [HasV4T, UseMEMOP] in {
2771 // mem[bh](Rs+#0) = [clrbit|setbit](#U5)
2772 // mem[bh](Rs+#u6:[01]) = [clrbit|setbit](#U5)
2773 defm : MemOpi_bitExtType<zextloadi8, zextloadi16>; // zero extend
2774 defm : MemOpi_bitExtType<sextloadi8, sextloadi16>; // sign extend
2775 defm : MemOpi_bitExtType<extloadi8, extloadi16>; // any extend
2777 // memw(Rs+#0) = [clrbit|setbit](#U5)
2778 // memw(Rs+#u6:2) = [clrbit|setbit](#U5)
2779 defm : MemOpi_bitPats<load, store, Clr5ImmPred, u6_2ExtPred, ADDRriU6_2,
2780 CLRMEMIMM, L4_iand_memopw_io, and>;
2781 defm : MemOpi_bitPats<load, store, Set5ImmPred, u6_2ExtPred, ADDRriU6_2,
2782 SETMEMIMM, L4_ior_memopw_io, or>;
2785 //===----------------------------------------------------------------------===//
2786 // Multiclass to define 'def Pats' for ALU operations on the memory
2787 // where addend is a register.
2788 // mem[bhw](Rs+#0) [+-&|]= Rt
2789 // mem[bhw](Rs+#U6:[012]) [+-&|]= Rt
2790 //===----------------------------------------------------------------------===//
2792 multiclass MemOpr_Pats <PatFrag ldOp, PatFrag stOp, ComplexPattern addrPred,
2793 PatLeaf extPred, InstHexagon MI, SDNode OpNode> {
2794 let AddedComplexity = 141 in
2795 // mem[bhw](Rs+#0) [+-&|]= Rt
2796 def : Pat <(stOp (OpNode (ldOp (addrPred IntRegs:$addr, extPred:$offset)),
2797 (i32 IntRegs:$addend)),
2798 (addrPred (i32 IntRegs:$addr), extPred:$offset)),
2799 (MI IntRegs:$addr, extPred:$offset, (i32 IntRegs:$addend) )>;
2801 // mem[bhw](Rs+#U6:[012]) [+-&|]= Rt
2802 let AddedComplexity = 150 in
2803 def : Pat <(stOp (OpNode (ldOp (add IntRegs:$base, extPred:$offset)),
2804 (i32 IntRegs:$orend)),
2805 (add IntRegs:$base, extPred:$offset)),
2806 (MI IntRegs:$base, extPred:$offset, (i32 IntRegs:$orend) )>;
2809 multiclass MemOPr_ALUOp<PatFrag ldOp, PatFrag stOp,
2810 ComplexPattern addrPred, PatLeaf extPred,
2811 InstHexagon addMI, InstHexagon subMI,
2812 InstHexagon andMI, InstHexagon orMI > {
2814 defm : MemOpr_Pats <ldOp, stOp, addrPred, extPred, addMI, add>;
2815 defm : MemOpr_Pats <ldOp, stOp, addrPred, extPred, subMI, sub>;
2816 defm : MemOpr_Pats <ldOp, stOp, addrPred, extPred, andMI, and>;
2817 defm : MemOpr_Pats <ldOp, stOp, addrPred, extPred, orMI, or>;
2820 multiclass MemOPr_ExtType<PatFrag ldOpByte, PatFrag ldOpHalf > {
2822 defm : MemOPr_ALUOp <ldOpHalf, truncstorei16, ADDRriU6_1, u6_1ExtPred,
2823 L4_add_memoph_io, L4_sub_memoph_io,
2824 L4_and_memoph_io, L4_or_memoph_io>;
2826 defm : MemOPr_ALUOp <ldOpByte, truncstorei8, ADDRriU6_0, u6ExtPred,
2827 L4_add_memopb_io, L4_sub_memopb_io,
2828 L4_and_memopb_io, L4_or_memopb_io>;
2831 // Define 'def Pats' for MemOps with register addend.
2832 let Predicates = [HasV4T, UseMEMOP] in {
2834 defm : MemOPr_ExtType<zextloadi8, zextloadi16>; // zero extend
2835 defm : MemOPr_ExtType<sextloadi8, sextloadi16>; // sign extend
2836 defm : MemOPr_ExtType<extloadi8, extloadi16>; // any extend
2838 defm : MemOPr_ALUOp <load, store, ADDRriU6_2, u6_2ExtPred, L4_add_memopw_io,
2839 L4_sub_memopw_io, L4_and_memopw_io, L4_or_memopw_io >;
2842 //===----------------------------------------------------------------------===//
2844 //===----------------------------------------------------------------------===//
2846 // Hexagon V4 only supports these flavors of byte/half compare instructions:
2847 // EQ/GT/GTU. Other flavors like GE/GEU/LT/LTU/LE/LEU are not supported by
2848 // hardware. However, compiler can still implement these patterns through
2849 // appropriate patterns combinations based on current implemented patterns.
2850 // The implemented patterns are: EQ/GT/GTU.
2851 // Missing patterns are: GE/GEU/LT/LTU/LE/LEU.
2853 // Following instruction is not being extended as it results into the
2854 // incorrect code for negative numbers.
2855 // Pd=cmpb.eq(Rs,#u8)
2857 // p=!cmp.eq(r1,#s10)
2858 let isCodeGenOnly = 0 in {
2859 def C4_cmpneqi : T_CMP <"cmp.eq", 0b00, 1, s10Ext>;
2860 def C4_cmpltei : T_CMP <"cmp.gt", 0b01, 1, s10Ext>;
2861 def C4_cmplteui : T_CMP <"cmp.gtu", 0b10, 1, u9Ext>;
2864 def : T_CMP_pat <C4_cmpneqi, setne, s10ExtPred>;
2865 def : T_CMP_pat <C4_cmpltei, setle, s10ExtPred>;
2866 def : T_CMP_pat <C4_cmplteui, setule, u9ImmPred>;
2868 // rs <= rt -> !(rs > rt).
2870 def: Pat<(i1 (setle (i32 IntRegs:$src1), s10ExtPred:$src2)),
2871 (C2_not (C2_cmpgti IntRegs:$src1, s10ExtPred:$src2))>;
2872 // (C4_cmpltei IntRegs:$src1, s10ExtPred:$src2)>;
2874 // Map cmplt(Rs, Imm) -> !cmpgt(Rs, Imm-1).
2875 def: Pat<(i1 (setlt (i32 IntRegs:$src1), s8ExtPred:$src2)),
2876 (C4_cmpltei IntRegs:$src1, (DEC_CONST_SIGNED s8ExtPred:$src2))>;
2878 // rs != rt -> !(rs == rt).
2879 def: Pat<(i1 (setne (i32 IntRegs:$src1), s10ExtPred:$src2)),
2880 (C4_cmpneqi IntRegs:$src1, s10ExtPred:$src2)>;
2882 // SDNode for converting immediate C to C-1.
2883 def DEC_CONST_BYTE : SDNodeXForm<imm, [{
2884 // Return the byte immediate const-1 as an SDNode.
2885 int32_t imm = N->getSExtValue();
2886 return XformU7ToU7M1Imm(imm);
2890 // zext( seteq ( and(Rs, 255), u8))
2892 // Pd=cmpb.eq(Rs, #u8)
2893 // if (Pd.new) Rd=#1
2894 // if (!Pd.new) Rd=#0
2895 def : Pat <(i32 (zext (i1 (seteq (i32 (and (i32 IntRegs:$Rs), 255)),
2897 (i32 (TFR_condset_ii (i1 (A4_cmpbeqi (i32 IntRegs:$Rs),
2903 // zext( setne ( and(Rs, 255), u8))
2905 // Pd=cmpb.eq(Rs, #u8)
2906 // if (Pd.new) Rd=#0
2907 // if (!Pd.new) Rd=#1
2908 def : Pat <(i32 (zext (i1 (setne (i32 (and (i32 IntRegs:$Rs), 255)),
2910 (i32 (TFR_condset_ii (i1 (A4_cmpbeqi (i32 IntRegs:$Rs),
2916 // zext( seteq (Rs, and(Rt, 255)))
2918 // Pd=cmpb.eq(Rs, Rt)
2919 // if (Pd.new) Rd=#1
2920 // if (!Pd.new) Rd=#0
2921 def : Pat <(i32 (zext (i1 (seteq (i32 IntRegs:$Rt),
2922 (i32 (and (i32 IntRegs:$Rs), 255)))))),
2923 (i32 (TFR_condset_ii (i1 (A4_cmpbeq (i32 IntRegs:$Rs),
2924 (i32 IntRegs:$Rt))),
2929 // zext( setne (Rs, and(Rt, 255)))
2931 // Pd=cmpb.eq(Rs, Rt)
2932 // if (Pd.new) Rd=#0
2933 // if (!Pd.new) Rd=#1
2934 def : Pat <(i32 (zext (i1 (setne (i32 IntRegs:$Rt),
2935 (i32 (and (i32 IntRegs:$Rs), 255)))))),
2936 (i32 (TFR_condset_ii (i1 (A4_cmpbeq (i32 IntRegs:$Rs),
2937 (i32 IntRegs:$Rt))),
2942 // zext( setugt ( and(Rs, 255), u8))
2944 // Pd=cmpb.gtu(Rs, #u8)
2945 // if (Pd.new) Rd=#1
2946 // if (!Pd.new) Rd=#0
2947 def : Pat <(i32 (zext (i1 (setugt (i32 (and (i32 IntRegs:$Rs), 255)),
2949 (i32 (TFR_condset_ii (i1 (A4_cmpbgtui (i32 IntRegs:$Rs),
2955 // zext( setugt ( and(Rs, 254), u8))
2957 // Pd=cmpb.gtu(Rs, #u8)
2958 // if (Pd.new) Rd=#1
2959 // if (!Pd.new) Rd=#0
2960 def : Pat <(i32 (zext (i1 (setugt (i32 (and (i32 IntRegs:$Rs), 254)),
2962 (i32 (TFR_condset_ii (i1 (A4_cmpbgtui (i32 IntRegs:$Rs),
2968 // zext( setult ( Rs, Rt))
2970 // Pd=cmp.ltu(Rs, Rt)
2971 // if (Pd.new) Rd=#1
2972 // if (!Pd.new) Rd=#0
2973 // cmp.ltu(Rs, Rt) -> cmp.gtu(Rt, Rs)
2974 def : Pat <(i32 (zext (i1 (setult (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
2975 (i32 (TFR_condset_ii (i1 (C2_cmpgtu (i32 IntRegs:$Rt),
2976 (i32 IntRegs:$Rs))),
2981 // zext( setlt ( Rs, Rt))
2983 // Pd=cmp.lt(Rs, Rt)
2984 // if (Pd.new) Rd=#1
2985 // if (!Pd.new) Rd=#0
2986 // cmp.lt(Rs, Rt) -> cmp.gt(Rt, Rs)
2987 def : Pat <(i32 (zext (i1 (setlt (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
2988 (i32 (TFR_condset_ii (i1 (C2_cmpgt (i32 IntRegs:$Rt),
2989 (i32 IntRegs:$Rs))),
2994 // zext( setugt ( Rs, Rt))
2996 // Pd=cmp.gtu(Rs, Rt)
2997 // if (Pd.new) Rd=#1
2998 // if (!Pd.new) Rd=#0
2999 def : Pat <(i32 (zext (i1 (setugt (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
3000 (i32 (TFR_condset_ii (i1 (C2_cmpgtu (i32 IntRegs:$Rs),
3001 (i32 IntRegs:$Rt))),
3005 // This pattern interefers with coremark performance, not implementing at this
3008 // zext( setgt ( Rs, Rt))
3010 // Pd=cmp.gt(Rs, Rt)
3011 // if (Pd.new) Rd=#1
3012 // if (!Pd.new) Rd=#0
3015 // zext( setuge ( Rs, Rt))
3017 // Pd=cmp.ltu(Rs, Rt)
3018 // if (Pd.new) Rd=#0
3019 // if (!Pd.new) Rd=#1
3020 // cmp.ltu(Rs, Rt) -> cmp.gtu(Rt, Rs)
3021 def : Pat <(i32 (zext (i1 (setuge (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
3022 (i32 (TFR_condset_ii (i1 (C2_cmpgtu (i32 IntRegs:$Rt),
3023 (i32 IntRegs:$Rs))),
3028 // zext( setge ( Rs, Rt))
3030 // Pd=cmp.lt(Rs, Rt)
3031 // if (Pd.new) Rd=#0
3032 // if (!Pd.new) Rd=#1
3033 // cmp.lt(Rs, Rt) -> cmp.gt(Rt, Rs)
3034 def : Pat <(i32 (zext (i1 (setge (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
3035 (i32 (TFR_condset_ii (i1 (C2_cmpgt (i32 IntRegs:$Rt),
3036 (i32 IntRegs:$Rs))),
3041 // zext( setule ( Rs, Rt))
3043 // Pd=cmp.gtu(Rs, Rt)
3044 // if (Pd.new) Rd=#0
3045 // if (!Pd.new) Rd=#1
3046 def : Pat <(i32 (zext (i1 (setule (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
3047 (i32 (TFR_condset_ii (i1 (C2_cmpgtu (i32 IntRegs:$Rs),
3048 (i32 IntRegs:$Rt))),
3053 // zext( setle ( Rs, Rt))
3055 // Pd=cmp.gt(Rs, Rt)
3056 // if (Pd.new) Rd=#0
3057 // if (!Pd.new) Rd=#1
3058 def : Pat <(i32 (zext (i1 (setle (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
3059 (i32 (TFR_condset_ii (i1 (C2_cmpgt (i32 IntRegs:$Rs),
3060 (i32 IntRegs:$Rt))),
3065 // zext( setult ( and(Rs, 255), u8))
3066 // Use the isdigit transformation below
3068 // Generate code of the form 'mux_ii(cmpbgtu(Rdd, C-1),0,1)'
3069 // for C code of the form r = ((c>='0') & (c<='9')) ? 1 : 0;.
3070 // The isdigit transformation relies on two 'clever' aspects:
3071 // 1) The data type is unsigned which allows us to eliminate a zero test after
3072 // biasing the expression by 48. We are depending on the representation of
3073 // the unsigned types, and semantics.
3074 // 2) The front end has converted <= 9 into < 10 on entry to LLVM
3077 // retval = ((c>='0') & (c<='9')) ? 1 : 0;
3078 // The code is transformed upstream of llvm into
3079 // retval = (c-48) < 10 ? 1 : 0;
3080 let AddedComplexity = 139 in
3081 def : Pat <(i32 (zext (i1 (setult (i32 (and (i32 IntRegs:$src1), 255)),
3082 u7StrictPosImmPred:$src2)))),
3083 (i32 (C2_muxii (i1 (A4_cmpbgtui (i32 IntRegs:$src1),
3084 (DEC_CONST_BYTE u7StrictPosImmPred:$src2))),
3088 //===----------------------------------------------------------------------===//
3090 //===----------------------------------------------------------------------===//
3092 //===----------------------------------------------------------------------===//
3093 // Multiclass for DeallocReturn
3094 //===----------------------------------------------------------------------===//
3095 class L4_RETURN<string mnemonic, bit isNot, bit isPredNew, bit isTak>
3096 : LD0Inst<(outs), (ins PredRegs:$src),
3097 !if(isNot, "if (!$src", "if ($src")#
3098 !if(isPredNew, ".new) ", ") ")#mnemonic#
3099 !if(isPredNew, #!if(isTak,":t", ":nt"),""),
3100 [], "", LD_tc_3or4stall_SLOT0> {
3103 let BaseOpcode = "L4_RETURN";
3104 let isPredicatedFalse = isNot;
3105 let isPredicatedNew = isPredNew;
3106 let isTaken = isTak;
3107 let IClass = 0b1001;
3109 let Inst{27-16} = 0b011000011110;
3111 let Inst{13} = isNot;
3112 let Inst{12} = isTak;
3113 let Inst{11} = isPredNew;
3115 let Inst{9-8} = src;
3116 let Inst{4-0} = 0b11110;
3119 // Produce all predicated forms, p, !p, p.new, !p.new, :t, :nt
3120 multiclass L4_RETURN_PRED<string mnemonic, bit PredNot> {
3121 let isPredicated = 1 in {
3122 def _#NAME# : L4_RETURN <mnemonic, PredNot, 0, 1>;
3123 def _#NAME#new_pnt : L4_RETURN <mnemonic, PredNot, 1, 0>;
3124 def _#NAME#new_pt : L4_RETURN <mnemonic, PredNot, 1, 1>;
3128 multiclass LD_MISC_L4_RETURN<string mnemonic> {
3129 let isBarrier = 1, isPredicable = 1 in
3130 def NAME : LD0Inst <(outs), (ins), mnemonic, [], "",
3131 LD_tc_3or4stall_SLOT0> {
3132 let BaseOpcode = "L4_RETURN";
3133 let IClass = 0b1001;
3134 let Inst{27-16} = 0b011000011110;
3135 let Inst{13-10} = 0b0000;
3136 let Inst{4-0} = 0b11110;
3138 defm t : L4_RETURN_PRED<mnemonic, 0 >;
3139 defm f : L4_RETURN_PRED<mnemonic, 1 >;
3142 let isReturn = 1, isTerminator = 1,
3143 Defs = [R29, R30, R31, PC], Uses = [R30], hasSideEffects = 0,
3144 validSubTargets = HasV4SubT, isCodeGenOnly = 0 in
3145 defm L4_return: LD_MISC_L4_RETURN <"dealloc_return">, PredNewRel;
3147 // Restore registers and dealloc return function call.
3148 let isCall = 1, isBarrier = 1, isReturn = 1, isTerminator = 1,
3149 Defs = [R29, R30, R31, PC] in {
3150 let validSubTargets = HasV4SubT in
3151 def RESTORE_DEALLOC_RET_JMP_V4 : JInst<(outs),
3152 (ins calltarget:$dst),
3158 // Restore registers and dealloc frame before a tail call.
3159 let isCall = 1, isBarrier = 1,
3160 Defs = [R29, R30, R31, PC] in {
3161 let validSubTargets = HasV4SubT in
3162 def RESTORE_DEALLOC_BEFORE_TAILCALL_V4 : JInst<(outs),
3163 (ins calltarget:$dst),
3169 // Save registers function call.
3170 let isCall = 1, isBarrier = 1,
3171 Uses = [R29, R31] in {
3172 def SAVE_REGISTERS_CALL_V4 : JInst<(outs),
3173 (ins calltarget:$dst),
3174 "call $dst // Save_calle_saved_registers",
3179 //===----------------------------------------------------------------------===//
3180 // Template class for non predicated store instructions with
3181 // GP-Relative or absolute addressing.
3182 //===----------------------------------------------------------------------===//
3183 let hasSideEffects = 0, isPredicable = 1, isNVStorable = 1 in
3184 class T_StoreAbsGP <string mnemonic, RegisterClass RC, Operand ImmOp,
3185 bits<2>MajOp, Operand AddrOp, bit isAbs, bit isHalf>
3186 : STInst<(outs), (ins AddrOp:$addr, RC:$src),
3187 mnemonic # !if(isAbs, "(##", "(#")#"$addr) = $src"#!if(isHalf, ".h",""),
3188 [], "", V2LDST_tc_st_SLOT01> {
3191 bits<16> offsetBits;
3193 string ImmOpStr = !cast<string>(ImmOp);
3194 let offsetBits = !if (!eq(ImmOpStr, "u16_3Imm"), addr{18-3},
3195 !if (!eq(ImmOpStr, "u16_2Imm"), addr{17-2},
3196 !if (!eq(ImmOpStr, "u16_1Imm"), addr{16-1},
3197 /* u16_0Imm */ addr{15-0})));
3198 let IClass = 0b0100;
3200 let Inst{26-25} = offsetBits{15-14};
3202 let Inst{23-22} = MajOp;
3203 let Inst{21} = isHalf;
3204 let Inst{20-16} = offsetBits{13-9};
3205 let Inst{13} = offsetBits{8};
3206 let Inst{12-8} = src;
3207 let Inst{7-0} = offsetBits{7-0};
3210 //===----------------------------------------------------------------------===//
3211 // Template class for predicated store instructions with
3212 // GP-Relative or absolute addressing.
3213 //===----------------------------------------------------------------------===//
3214 let hasSideEffects = 0, isPredicated = 1, isNVStorable = 1, opExtentBits = 6,
3216 class T_StoreAbs_Pred <string mnemonic, RegisterClass RC, bits<2> MajOp,
3217 bit isHalf, bit isNot, bit isNew>
3218 : STInst<(outs), (ins PredRegs:$src1, u6Ext:$absaddr, RC: $src2),
3219 !if(isNot, "if (!$src1", "if ($src1")#!if(isNew, ".new) ",
3220 ") ")#mnemonic#"(#$absaddr) = $src2"#!if(isHalf, ".h",""),
3221 [], "", ST_tc_st_SLOT01>, AddrModeRel {
3226 let isPredicatedNew = isNew;
3227 let isPredicatedFalse = isNot;
3229 let IClass = 0b1010;
3231 let Inst{27-24} = 0b1111;
3232 let Inst{23-22} = MajOp;
3233 let Inst{21} = isHalf;
3234 let Inst{17-16} = absaddr{5-4};
3235 let Inst{13} = isNew;
3236 let Inst{12-8} = src2;
3238 let Inst{6-3} = absaddr{3-0};
3239 let Inst{2} = isNot;
3240 let Inst{1-0} = src1;
3243 //===----------------------------------------------------------------------===//
3244 // Template class for predicated store instructions with absolute addressing.
3245 //===----------------------------------------------------------------------===//
3246 class T_StoreAbs <string mnemonic, RegisterClass RC, Operand ImmOp,
3247 bits<2> MajOp, bit isHalf>
3248 : T_StoreAbsGP <mnemonic, RC, ImmOp, MajOp, u0AlwaysExt, 1, isHalf>,
3250 string ImmOpStr = !cast<string>(ImmOp);
3251 let opExtentBits = !if (!eq(ImmOpStr, "u16_3Imm"), 19,
3252 !if (!eq(ImmOpStr, "u16_2Imm"), 18,
3253 !if (!eq(ImmOpStr, "u16_1Imm"), 17,
3254 /* u16_0Imm */ 16)));
3256 let opExtentAlign = !if (!eq(ImmOpStr, "u16_3Imm"), 3,
3257 !if (!eq(ImmOpStr, "u16_2Imm"), 2,
3258 !if (!eq(ImmOpStr, "u16_1Imm"), 1,
3259 /* u16_0Imm */ 0)));
3262 //===----------------------------------------------------------------------===//
3263 // Multiclass for store instructions with absolute addressing.
3264 //===----------------------------------------------------------------------===//
3265 let validSubTargets = HasV4SubT, addrMode = Absolute, isExtended = 1 in
3266 multiclass ST_Abs<string mnemonic, string CextOp, RegisterClass RC,
3267 Operand ImmOp, bits<2> MajOp, bit isHalf = 0> {
3268 let CextOpcode = CextOp, BaseOpcode = CextOp#_abs in {
3269 let opExtendable = 0, isPredicable = 1 in
3270 def S2_#NAME#abs : T_StoreAbs <mnemonic, RC, ImmOp, MajOp, isHalf>;
3273 def S4_p#NAME#t_abs : T_StoreAbs_Pred<mnemonic, RC, MajOp, isHalf, 0, 0>;
3274 def S4_p#NAME#f_abs : T_StoreAbs_Pred<mnemonic, RC, MajOp, isHalf, 1, 0>;
3277 def S4_p#NAME#tnew_abs : T_StoreAbs_Pred<mnemonic, RC, MajOp, isHalf, 0, 1>;
3278 def S4_p#NAME#fnew_abs : T_StoreAbs_Pred<mnemonic, RC, MajOp, isHalf, 1, 1>;
3282 //===----------------------------------------------------------------------===//
3283 // Template class for non predicated new-value store instructions with
3284 // GP-Relative or absolute addressing.
3285 //===----------------------------------------------------------------------===//
3286 let hasSideEffects = 0, isPredicable = 1, mayStore = 1, isNVStore = 1,
3287 isNewValue = 1, opNewValue = 1 in
3288 class T_StoreAbsGP_NV <string mnemonic, Operand ImmOp, bits<2>MajOp, bit isAbs>
3289 : NVInst_V4<(outs), (ins u0AlwaysExt:$addr, IntRegs:$src),
3290 mnemonic # !if(isAbs, "(##", "(#")#"$addr) = $src.new",
3291 [], "", V2LDST_tc_st_SLOT0> {
3294 bits<16> offsetBits;
3296 string ImmOpStr = !cast<string>(ImmOp);
3297 let offsetBits = !if (!eq(ImmOpStr, "u16_3Imm"), addr{18-3},
3298 !if (!eq(ImmOpStr, "u16_2Imm"), addr{17-2},
3299 !if (!eq(ImmOpStr, "u16_1Imm"), addr{16-1},
3300 /* u16_0Imm */ addr{15-0})));
3301 let IClass = 0b0100;
3304 let Inst{26-25} = offsetBits{15-14};
3305 let Inst{24-21} = 0b0101;
3306 let Inst{20-16} = offsetBits{13-9};
3307 let Inst{13} = offsetBits{8};
3308 let Inst{12-11} = MajOp;
3309 let Inst{10-8} = src;
3310 let Inst{7-0} = offsetBits{7-0};
3313 //===----------------------------------------------------------------------===//
3314 // Template class for predicated new-value store instructions with
3315 // absolute addressing.
3316 //===----------------------------------------------------------------------===//
3317 let hasSideEffects = 0, isPredicated = 1, mayStore = 1, isNVStore = 1,
3318 isNewValue = 1, opNewValue = 2, opExtentBits = 6, opExtendable = 1 in
3319 class T_StoreAbs_NV_Pred <string mnemonic, bits<2> MajOp, bit isNot, bit isNew>
3320 : NVInst_V4<(outs), (ins PredRegs:$src1, u6Ext:$absaddr, IntRegs:$src2),
3321 !if(isNot, "if (!$src1", "if ($src1")#!if(isNew, ".new) ",
3322 ") ")#mnemonic#"(#$absaddr) = $src2.new",
3323 [], "", ST_tc_st_SLOT0>, AddrModeRel {
3328 let isPredicatedNew = isNew;
3329 let isPredicatedFalse = isNot;
3331 let IClass = 0b1010;
3333 let Inst{27-24} = 0b1111;
3334 let Inst{23-21} = 0b101;
3335 let Inst{17-16} = absaddr{5-4};
3336 let Inst{13} = isNew;
3337 let Inst{12-11} = MajOp;
3338 let Inst{10-8} = src2;
3340 let Inst{6-3} = absaddr{3-0};
3341 let Inst{2} = isNot;
3342 let Inst{1-0} = src1;
3345 //===----------------------------------------------------------------------===//
3346 // Template class for non-predicated new-value store instructions with
3347 // absolute addressing.
3348 //===----------------------------------------------------------------------===//
3349 class T_StoreAbs_NV <string mnemonic, Operand ImmOp, bits<2> MajOp>
3350 : T_StoreAbsGP_NV <mnemonic, ImmOp, MajOp, 1>, AddrModeRel {
3352 string ImmOpStr = !cast<string>(ImmOp);
3353 let opExtentBits = !if (!eq(ImmOpStr, "u16_3Imm"), 19,
3354 !if (!eq(ImmOpStr, "u16_2Imm"), 18,
3355 !if (!eq(ImmOpStr, "u16_1Imm"), 17,
3356 /* u16_0Imm */ 16)));
3358 let opExtentAlign = !if (!eq(ImmOpStr, "u16_3Imm"), 3,
3359 !if (!eq(ImmOpStr, "u16_2Imm"), 2,
3360 !if (!eq(ImmOpStr, "u16_1Imm"), 1,
3361 /* u16_0Imm */ 0)));
3364 //===----------------------------------------------------------------------===//
3365 // Multiclass for new-value store instructions with absolute addressing.
3366 //===----------------------------------------------------------------------===//
3367 let validSubTargets = HasV4SubT, addrMode = Absolute, isExtended = 1 in
3368 multiclass ST_Abs_NV <string mnemonic, string CextOp, Operand ImmOp,
3370 let CextOpcode = CextOp, BaseOpcode = CextOp#_abs in {
3371 let opExtendable = 0, isPredicable = 1 in
3372 def S2_#NAME#newabs : T_StoreAbs_NV <mnemonic, ImmOp, MajOp>;
3375 def S4_p#NAME#newt_abs : T_StoreAbs_NV_Pred <mnemonic, MajOp, 0, 0>;
3376 def S4_p#NAME#newf_abs : T_StoreAbs_NV_Pred <mnemonic, MajOp, 1, 0>;
3379 def S4_p#NAME#newtnew_abs : T_StoreAbs_NV_Pred <mnemonic, MajOp, 0, 1>;
3380 def S4_p#NAME#newfnew_abs : T_StoreAbs_NV_Pred <mnemonic, MajOp, 1, 1>;
3384 //===----------------------------------------------------------------------===//
3385 // Stores with absolute addressing
3386 //===----------------------------------------------------------------------===//
3387 let accessSize = ByteAccess, isCodeGenOnly = 0 in
3388 defm storerb : ST_Abs <"memb", "STrib", IntRegs, u16_0Imm, 0b00>,
3389 ST_Abs_NV <"memb", "STrib", u16_0Imm, 0b00>;
3391 let accessSize = HalfWordAccess, isCodeGenOnly = 0 in
3392 defm storerh : ST_Abs <"memh", "STrih", IntRegs, u16_1Imm, 0b01>,
3393 ST_Abs_NV <"memh", "STrih", u16_1Imm, 0b01>;
3395 let accessSize = WordAccess, isCodeGenOnly = 0 in
3396 defm storeri : ST_Abs <"memw", "STriw", IntRegs, u16_2Imm, 0b10>,
3397 ST_Abs_NV <"memw", "STriw", u16_2Imm, 0b10>;
3399 let isNVStorable = 0, accessSize = DoubleWordAccess, isCodeGenOnly = 0 in
3400 defm storerd : ST_Abs <"memd", "STrid", DoubleRegs, u16_3Imm, 0b11>;
3402 let isNVStorable = 0, accessSize = HalfWordAccess, isCodeGenOnly = 0 in
3403 defm storerf : ST_Abs <"memh", "STrif", IntRegs, u16_1Imm, 0b01, 1>;
3405 //===----------------------------------------------------------------------===//
3406 // GP-relative stores.
3407 // mem[bhwd](#global)=Rt
3408 // Once predicated, these instructions map to absolute addressing mode.
3409 // if ([!]Pv[.new]) mem[bhwd](##global)=Rt
3410 //===----------------------------------------------------------------------===//
3412 let validSubTargets = HasV4SubT in
3413 class T_StoreGP <string mnemonic, string BaseOp, RegisterClass RC,
3414 Operand ImmOp, bits<2> MajOp, bit isHalf = 0>
3415 : T_StoreAbsGP <mnemonic, RC, ImmOp, MajOp, globaladdress, 0, isHalf> {
3416 // Set BaseOpcode same as absolute addressing instructions so that
3417 // non-predicated GP-Rel instructions can have relate with predicated
3418 // Absolute instruction.
3419 let BaseOpcode = BaseOp#_abs;
3422 let validSubTargets = HasV4SubT in
3423 multiclass ST_GP <string mnemonic, string BaseOp, Operand ImmOp,
3424 bits<2> MajOp, bit isHalf = 0> {
3425 // Set BaseOpcode same as absolute addressing instructions so that
3426 // non-predicated GP-Rel instructions can have relate with predicated
3427 // Absolute instruction.
3428 let BaseOpcode = BaseOp#_abs in {
3429 def NAME#gp : T_StoreAbsGP <mnemonic, IntRegs, ImmOp, MajOp,
3430 globaladdress, 0, isHalf>;
3432 def NAME#newgp : T_StoreAbsGP_NV <mnemonic, ImmOp, MajOp, 0> ;
3436 let accessSize = ByteAccess in
3437 defm S2_storerb : ST_GP<"memb", "STrib", u16_0Imm, 0b00>, NewValueRel;
3439 let accessSize = HalfWordAccess in
3440 defm S2_storerh : ST_GP<"memh", "STrih", u16_1Imm, 0b01>, NewValueRel;
3442 let accessSize = WordAccess in
3443 defm S2_storeri : ST_GP<"memw", "STriw", u16_2Imm, 0b10>, NewValueRel;
3445 let isNVStorable = 0, accessSize = DoubleWordAccess in
3446 def S2_storerdgp : T_StoreGP <"memd", "STrid", DoubleRegs,
3447 u16_3Imm, 0b11>, PredNewRel;
3449 let isNVStorable = 0, accessSize = HalfWordAccess in
3450 def S2_storerfgp : T_StoreGP <"memh", "STrif", IntRegs,
3451 u16_1Imm, 0b01, 1>, PredNewRel;
3453 let Predicates = [HasV4T], AddedComplexity = 30 in {
3454 def : Pat<(truncstorei8 (i32 IntRegs:$src1),
3455 (HexagonCONST32 tglobaladdr:$absaddr)),
3456 (S2_storerbabs tglobaladdr: $absaddr, IntRegs: $src1)>;
3458 def : Pat<(truncstorei16 (i32 IntRegs:$src1),
3459 (HexagonCONST32 tglobaladdr:$absaddr)),
3460 (S2_storerhabs tglobaladdr: $absaddr, IntRegs: $src1)>;
3462 def : Pat<(store (i32 IntRegs:$src1), (HexagonCONST32 tglobaladdr:$absaddr)),
3463 (S2_storeriabs tglobaladdr: $absaddr, IntRegs: $src1)>;
3465 def : Pat<(store (i64 DoubleRegs:$src1),
3466 (HexagonCONST32 tglobaladdr:$absaddr)),
3467 (S2_storerdabs tglobaladdr: $absaddr, DoubleRegs: $src1)>;
3470 // 64 bit atomic store
3471 def : Pat <(atomic_store_64 (HexagonCONST32_GP tglobaladdr:$global),
3472 (i64 DoubleRegs:$src1)),
3473 (S2_storerdgp tglobaladdr:$global, (i64 DoubleRegs:$src1))>,
3476 // Map from store(globaladdress) -> memd(#foo)
3477 let AddedComplexity = 100 in
3478 def : Pat <(store (i64 DoubleRegs:$src1),
3479 (HexagonCONST32_GP tglobaladdr:$global)),
3480 (S2_storerdgp tglobaladdr:$global, (i64 DoubleRegs:$src1))>;
3482 // 8 bit atomic store
3483 def : Pat < (atomic_store_8 (HexagonCONST32_GP tglobaladdr:$global),
3484 (i32 IntRegs:$src1)),
3485 (S2_storerbgp tglobaladdr:$global, (i32 IntRegs:$src1))>;
3487 // Map from store(globaladdress) -> memb(#foo)
3488 let AddedComplexity = 100 in
3489 def : Pat<(truncstorei8 (i32 IntRegs:$src1),
3490 (HexagonCONST32_GP tglobaladdr:$global)),
3491 (S2_storerbgp tglobaladdr:$global, (i32 IntRegs:$src1))>;
3493 // Map from "i1 = constant<-1>; memw(CONST32(#foo)) = i1"
3494 // to "r0 = 1; memw(#foo) = r0"
3495 let AddedComplexity = 100 in
3496 def : Pat<(store (i1 -1), (HexagonCONST32_GP tglobaladdr:$global)),
3497 (S2_storerbgp tglobaladdr:$global, (A2_tfrsi 1))>;
3499 def : Pat<(atomic_store_16 (HexagonCONST32_GP tglobaladdr:$global),
3500 (i32 IntRegs:$src1)),
3501 (S2_storerhgp tglobaladdr:$global, (i32 IntRegs:$src1))>;
3503 // Map from store(globaladdress) -> memh(#foo)
3504 let AddedComplexity = 100 in
3505 def : Pat<(truncstorei16 (i32 IntRegs:$src1),
3506 (HexagonCONST32_GP tglobaladdr:$global)),
3507 (S2_storerhgp tglobaladdr:$global, (i32 IntRegs:$src1))>;
3509 // 32 bit atomic store
3510 def : Pat<(atomic_store_32 (HexagonCONST32_GP tglobaladdr:$global),
3511 (i32 IntRegs:$src1)),
3512 (S2_storerigp tglobaladdr:$global, (i32 IntRegs:$src1))>;
3514 // Map from store(globaladdress) -> memw(#foo)
3515 let AddedComplexity = 100 in
3516 def : Pat<(store (i32 IntRegs:$src1), (HexagonCONST32_GP tglobaladdr:$global)),
3517 (S2_storerigp tglobaladdr:$global, (i32 IntRegs:$src1))>;
3519 //===----------------------------------------------------------------------===//
3520 // Template class for non predicated load instructions with
3521 // absolute addressing mode.
3522 //===----------------------------------------------------------------------===//
3523 let isPredicable = 1, hasSideEffects = 0, validSubTargets = HasV4SubT in
3524 class T_LoadAbsGP <string mnemonic, RegisterClass RC, Operand ImmOp,
3525 bits<3> MajOp, Operand AddrOp, bit isAbs>
3526 : LDInst <(outs RC:$dst), (ins AddrOp:$addr),
3527 "$dst = "#mnemonic# !if(isAbs, "(##", "(#")#"$addr)",
3528 [], "", V2LDST_tc_ld_SLOT01> {
3531 bits<16> offsetBits;
3533 string ImmOpStr = !cast<string>(ImmOp);
3534 let offsetBits = !if (!eq(ImmOpStr, "u16_3Imm"), addr{18-3},
3535 !if (!eq(ImmOpStr, "u16_2Imm"), addr{17-2},
3536 !if (!eq(ImmOpStr, "u16_1Imm"), addr{16-1},
3537 /* u16_0Imm */ addr{15-0})));
3539 let IClass = 0b0100;
3542 let Inst{26-25} = offsetBits{15-14};
3544 let Inst{23-21} = MajOp;
3545 let Inst{20-16} = offsetBits{13-9};
3546 let Inst{13-5} = offsetBits{8-0};
3547 let Inst{4-0} = dst;
3550 class T_LoadAbs <string mnemonic, RegisterClass RC, Operand ImmOp,
3552 : T_LoadAbsGP <mnemonic, RC, ImmOp, MajOp, u0AlwaysExt, 1>, AddrModeRel {
3554 string ImmOpStr = !cast<string>(ImmOp);
3555 let opExtentBits = !if (!eq(ImmOpStr, "u16_3Imm"), 19,
3556 !if (!eq(ImmOpStr, "u16_2Imm"), 18,
3557 !if (!eq(ImmOpStr, "u16_1Imm"), 17,
3558 /* u16_0Imm */ 16)));
3560 let opExtentAlign = !if (!eq(ImmOpStr, "u16_3Imm"), 3,
3561 !if (!eq(ImmOpStr, "u16_2Imm"), 2,
3562 !if (!eq(ImmOpStr, "u16_1Imm"), 1,
3563 /* u16_0Imm */ 0)));
3565 //===----------------------------------------------------------------------===//
3566 // Template class for predicated load instructions with
3567 // absolute addressing mode.
3568 //===----------------------------------------------------------------------===//
3569 let isPredicated = 1, hasNewValue = 1, opExtentBits = 6, opExtendable = 2 in
3570 class T_LoadAbs_Pred <string mnemonic, RegisterClass RC, bits<3> MajOp,
3571 bit isPredNot, bit isPredNew>
3572 : LDInst <(outs RC:$dst), (ins PredRegs:$src1, u6Ext:$absaddr),
3573 !if(isPredNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
3574 ") ")#"$dst = "#mnemonic#"(#$absaddr)">, AddrModeRel {
3579 let isPredicatedNew = isPredNew;
3580 let isPredicatedFalse = isPredNot;
3582 let IClass = 0b1001;
3584 let Inst{27-24} = 0b1111;
3585 let Inst{23-21} = MajOp;
3586 let Inst{20-16} = absaddr{5-1};
3588 let Inst{12} = isPredNew;
3589 let Inst{11} = isPredNot;
3590 let Inst{10-9} = src1;
3591 let Inst{8} = absaddr{0};
3593 let Inst{4-0} = dst;
3596 //===----------------------------------------------------------------------===//
3597 // Multiclass for the load instructions with absolute addressing mode.
3598 //===----------------------------------------------------------------------===//
3599 multiclass LD_Abs_Pred<string mnemonic, RegisterClass RC, bits<3> MajOp,
3601 def _abs : T_LoadAbs_Pred <mnemonic, RC, MajOp, PredNot, 0>;
3603 def new_abs : T_LoadAbs_Pred <mnemonic, RC, MajOp, PredNot, 1>;
3606 let addrMode = Absolute, isExtended = 1 in
3607 multiclass LD_Abs<string mnemonic, string CextOp, RegisterClass RC,
3608 Operand ImmOp, bits<3> MajOp> {
3609 let CextOpcode = CextOp, BaseOpcode = CextOp#_abs in {
3610 let opExtendable = 1, isPredicable = 1 in
3611 def L4_#NAME#_abs: T_LoadAbs <mnemonic, RC, ImmOp, MajOp>;
3614 defm L4_p#NAME#t : LD_Abs_Pred<mnemonic, RC, MajOp, 0>;
3615 defm L4_p#NAME#f : LD_Abs_Pred<mnemonic, RC, MajOp, 1>;
3619 let accessSize = ByteAccess, hasNewValue = 1, isCodeGenOnly = 0 in {
3620 defm loadrb : LD_Abs<"memb", "LDrib", IntRegs, u16_0Imm, 0b000>;
3621 defm loadrub : LD_Abs<"memub", "LDriub", IntRegs, u16_0Imm, 0b001>;
3624 let accessSize = HalfWordAccess, hasNewValue = 1, isCodeGenOnly = 0 in {
3625 defm loadrh : LD_Abs<"memh", "LDrih", IntRegs, u16_1Imm, 0b010>;
3626 defm loadruh : LD_Abs<"memuh", "LDriuh", IntRegs, u16_1Imm, 0b011>;
3629 let accessSize = WordAccess, hasNewValue = 1, isCodeGenOnly = 0 in
3630 defm loadri : LD_Abs<"memw", "LDriw", IntRegs, u16_2Imm, 0b100>;
3632 let accessSize = DoubleWordAccess, isCodeGenOnly = 0 in
3633 defm loadrd : LD_Abs<"memd", "LDrid", DoubleRegs, u16_3Imm, 0b110>;
3635 //===----------------------------------------------------------------------===//
3636 // multiclass for load instructions with GP-relative addressing mode.
3637 // Rx=mem[bhwd](##global)
3638 // Once predicated, these instructions map to absolute addressing mode.
3639 // if ([!]Pv[.new]) Rx=mem[bhwd](##global)
3640 //===----------------------------------------------------------------------===//
3642 class T_LoadGP <string mnemonic, string BaseOp, RegisterClass RC, Operand ImmOp,
3644 : T_LoadAbsGP <mnemonic, RC, ImmOp, MajOp, globaladdress, 0>, PredNewRel {
3645 let BaseOpcode = BaseOp#_abs;
3648 let accessSize = ByteAccess, hasNewValue = 1 in {
3649 def L2_loadrbgp : T_LoadGP<"memb", "LDrib", IntRegs, u16_0Imm, 0b000>;
3650 def L2_loadrubgp : T_LoadGP<"memub", "LDriub", IntRegs, u16_0Imm, 0b001>;
3653 let accessSize = HalfWordAccess, hasNewValue = 1 in {
3654 def L2_loadrhgp : T_LoadGP<"memh", "LDrih", IntRegs, u16_1Imm, 0b010>;
3655 def L2_loadruhgp : T_LoadGP<"memuh", "LDriuh", IntRegs, u16_1Imm, 0b011>;
3658 let accessSize = WordAccess, hasNewValue = 1 in
3659 def L2_loadrigp : T_LoadGP<"memw", "LDriw", IntRegs, u16_2Imm, 0b100>;
3661 let accessSize = DoubleWordAccess in
3662 def L2_loadrdgp : T_LoadGP<"memd", "LDrid", DoubleRegs, u16_3Imm, 0b110>;
3664 let Predicates = [HasV4T], AddedComplexity = 30 in {
3665 def : Pat<(i32 (load (HexagonCONST32 tglobaladdr:$absaddr))),
3666 (L4_loadri_abs tglobaladdr: $absaddr)>;
3668 def : Pat<(i32 (sextloadi8 (HexagonCONST32 tglobaladdr:$absaddr))),
3669 (L4_loadrb_abs tglobaladdr:$absaddr)>;
3671 def : Pat<(i32 (zextloadi8 (HexagonCONST32 tglobaladdr:$absaddr))),
3672 (L4_loadrub_abs tglobaladdr:$absaddr)>;
3674 def : Pat<(i32 (sextloadi16 (HexagonCONST32 tglobaladdr:$absaddr))),
3675 (L4_loadrh_abs tglobaladdr:$absaddr)>;
3677 def : Pat<(i32 (zextloadi16 (HexagonCONST32 tglobaladdr:$absaddr))),
3678 (L4_loadruh_abs tglobaladdr:$absaddr)>;
3681 def : Pat <(atomic_load_64 (HexagonCONST32_GP tglobaladdr:$global)),
3682 (i64 (L2_loadrdgp tglobaladdr:$global))>;
3684 def : Pat <(atomic_load_32 (HexagonCONST32_GP tglobaladdr:$global)),
3685 (i32 (L2_loadrigp tglobaladdr:$global))>;
3687 def : Pat <(atomic_load_16 (HexagonCONST32_GP tglobaladdr:$global)),
3688 (i32 (L2_loadruhgp tglobaladdr:$global))>;
3690 def : Pat <(atomic_load_8 (HexagonCONST32_GP tglobaladdr:$global)),
3691 (i32 (L2_loadrubgp tglobaladdr:$global))>;
3693 // Map from load(globaladdress) -> memw(#foo + 0)
3694 let AddedComplexity = 100 in
3695 def : Pat <(i64 (load (HexagonCONST32_GP tglobaladdr:$global))),
3696 (i64 (L2_loadrdgp tglobaladdr:$global))>;
3698 // Map from Pd = load(globaladdress) -> Rd = memb(globaladdress), Pd = Rd
3699 let AddedComplexity = 100 in
3700 def : Pat <(i1 (load (HexagonCONST32_GP tglobaladdr:$global))),
3701 (i1 (C2_tfrrp (i32 (L2_loadrbgp tglobaladdr:$global))))>;
3703 // When the Interprocedural Global Variable optimizer realizes that a certain
3704 // global variable takes only two constant values, it shrinks the global to
3705 // a boolean. Catch those loads here in the following 3 patterns.
3706 let AddedComplexity = 100 in
3707 def : Pat <(i32 (extloadi1 (HexagonCONST32_GP tglobaladdr:$global))),
3708 (i32 (L2_loadrbgp tglobaladdr:$global))>;
3710 let AddedComplexity = 100 in
3711 def : Pat <(i32 (sextloadi1 (HexagonCONST32_GP tglobaladdr:$global))),
3712 (i32 (L2_loadrbgp tglobaladdr:$global))>;
3714 // Map from load(globaladdress) -> memb(#foo)
3715 let AddedComplexity = 100 in
3716 def : Pat <(i32 (extloadi8 (HexagonCONST32_GP tglobaladdr:$global))),
3717 (i32 (L2_loadrbgp tglobaladdr:$global))>;
3719 // Map from load(globaladdress) -> memb(#foo)
3720 let AddedComplexity = 100 in
3721 def : Pat <(i32 (sextloadi8 (HexagonCONST32_GP tglobaladdr:$global))),
3722 (i32 (L2_loadrbgp tglobaladdr:$global))>;
3724 let AddedComplexity = 100 in
3725 def : Pat <(i32 (zextloadi1 (HexagonCONST32_GP tglobaladdr:$global))),
3726 (i32 (L2_loadrubgp tglobaladdr:$global))>;
3728 // Map from load(globaladdress) -> memub(#foo)
3729 let AddedComplexity = 100 in
3730 def : Pat <(i32 (zextloadi8 (HexagonCONST32_GP tglobaladdr:$global))),
3731 (i32 (L2_loadrubgp tglobaladdr:$global))>;
3733 // Map from load(globaladdress) -> memh(#foo)
3734 let AddedComplexity = 100 in
3735 def : Pat <(i32 (extloadi16 (HexagonCONST32_GP tglobaladdr:$global))),
3736 (i32 (L2_loadrhgp tglobaladdr:$global))>;
3738 // Map from load(globaladdress) -> memh(#foo)
3739 let AddedComplexity = 100 in
3740 def : Pat <(i32 (sextloadi16 (HexagonCONST32_GP tglobaladdr:$global))),
3741 (i32 (L2_loadrhgp tglobaladdr:$global))>;
3743 // Map from load(globaladdress) -> memuh(#foo)
3744 let AddedComplexity = 100 in
3745 def : Pat <(i32 (zextloadi16 (HexagonCONST32_GP tglobaladdr:$global))),
3746 (i32 (L2_loadruhgp tglobaladdr:$global))>;
3748 // Map from load(globaladdress) -> memw(#foo)
3749 let AddedComplexity = 100 in
3750 def : Pat <(i32 (load (HexagonCONST32_GP tglobaladdr:$global))),
3751 (i32 (L2_loadrigp tglobaladdr:$global))>;
3754 // Transfer global address into a register
3755 let isExtended = 1, opExtendable = 1, AddedComplexity=50, isMoveImm = 1,
3756 isAsCheapAsAMove = 1, isReMaterializable = 1, validSubTargets = HasV4SubT in
3757 def TFRI_V4 : ALU32_ri<(outs IntRegs:$dst), (ins s16Ext:$src1),
3759 [(set IntRegs:$dst, (HexagonCONST32 tglobaladdr:$src1))]>,
3762 // Transfer a block address into a register
3763 def : Pat<(HexagonCONST32_GP tblockaddress:$src1),
3764 (TFRI_V4 tblockaddress:$src1)>,
3767 let isExtended = 1, opExtendable = 2, AddedComplexity=50,
3768 hasSideEffects = 0, isPredicated = 1, validSubTargets = HasV4SubT in
3769 def TFRI_cPt_V4 : ALU32_ri<(outs IntRegs:$dst),
3770 (ins PredRegs:$src1, s16Ext:$src2),
3771 "if($src1) $dst = #$src2",
3775 let isExtended = 1, opExtendable = 2, AddedComplexity=50, isPredicatedFalse = 1,
3776 hasSideEffects = 0, isPredicated = 1, validSubTargets = HasV4SubT in
3777 def TFRI_cNotPt_V4 : ALU32_ri<(outs IntRegs:$dst),
3778 (ins PredRegs:$src1, s16Ext:$src2),
3779 "if(!$src1) $dst = #$src2",
3783 let isExtended = 1, opExtendable = 2, AddedComplexity=50,
3784 hasSideEffects = 0, isPredicated = 1, validSubTargets = HasV4SubT in
3785 def TFRI_cdnPt_V4 : ALU32_ri<(outs IntRegs:$dst),
3786 (ins PredRegs:$src1, s16Ext:$src2),
3787 "if($src1.new) $dst = #$src2",
3791 let isExtended = 1, opExtendable = 2, AddedComplexity=50, isPredicatedFalse = 1,
3792 hasSideEffects = 0, isPredicated = 1, validSubTargets = HasV4SubT in
3793 def TFRI_cdnNotPt_V4 : ALU32_ri<(outs IntRegs:$dst),
3794 (ins PredRegs:$src1, s16Ext:$src2),
3795 "if(!$src1.new) $dst = #$src2",
3799 let AddedComplexity = 50, Predicates = [HasV4T] in
3800 def : Pat<(HexagonCONST32_GP tglobaladdr:$src1),
3801 (TFRI_V4 tglobaladdr:$src1)>,
3805 // Load - Indirect with long offset: These instructions take global address
3807 let isExtended = 1, opExtendable = 3, AddedComplexity = 40,
3808 validSubTargets = HasV4SubT in
3809 def LDrid_ind_lo_V4 : LDInst<(outs DoubleRegs:$dst),
3810 (ins IntRegs:$src1, u2Imm:$src2, globaladdressExt:$offset),
3811 "$dst=memd($src1<<#$src2+##$offset)",
3812 [(set (i64 DoubleRegs:$dst),
3813 (load (add (shl IntRegs:$src1, u2ImmPred:$src2),
3814 (HexagonCONST32 tglobaladdr:$offset))))]>,
3817 let AddedComplexity = 40 in
3818 multiclass LD_indirect_lo<string OpcStr, PatFrag OpNode> {
3819 let isExtended = 1, opExtendable = 3, validSubTargets = HasV4SubT in
3820 def _lo_V4 : LDInst<(outs IntRegs:$dst),
3821 (ins IntRegs:$src1, u2Imm:$src2, globaladdressExt:$offset),
3822 !strconcat("$dst = ",
3823 !strconcat(OpcStr, "($src1<<#$src2+##$offset)")),
3825 (i32 (OpNode (add (shl IntRegs:$src1, u2ImmPred:$src2),
3826 (HexagonCONST32 tglobaladdr:$offset)))))]>,
3830 defm LDrib_ind : LD_indirect_lo<"memb", sextloadi8>;
3831 defm LDriub_ind : LD_indirect_lo<"memub", zextloadi8>;
3832 defm LDriub_ind_anyext : LD_indirect_lo<"memub", extloadi8>;
3833 defm LDrih_ind : LD_indirect_lo<"memh", sextloadi16>;
3834 defm LDriuh_ind : LD_indirect_lo<"memuh", zextloadi16>;
3835 defm LDriuh_ind_anyext : LD_indirect_lo<"memuh", extloadi16>;
3836 defm LDriw_ind : LD_indirect_lo<"memw", load>;
3838 let AddedComplexity = 40 in
3839 def : Pat <(i32 (sextloadi8 (add IntRegs:$src1,
3840 (NumUsesBelowThresCONST32 tglobaladdr:$offset)))),
3841 (i32 (LDrib_ind_lo_V4 IntRegs:$src1, 0, tglobaladdr:$offset))>,
3844 let AddedComplexity = 40 in
3845 def : Pat <(i32 (zextloadi8 (add IntRegs:$src1,
3846 (NumUsesBelowThresCONST32 tglobaladdr:$offset)))),
3847 (i32 (LDriub_ind_lo_V4 IntRegs:$src1, 0, tglobaladdr:$offset))>,
3850 let Predicates = [HasV4T], AddedComplexity = 30 in {
3851 def : Pat<(truncstorei8 (i32 IntRegs:$src1), u0AlwaysExtPred:$src2),
3852 (S2_storerbabs u0AlwaysExtPred:$src2, IntRegs: $src1)>;
3854 def : Pat<(truncstorei16 (i32 IntRegs:$src1), u0AlwaysExtPred:$src2),
3855 (S2_storerhabs u0AlwaysExtPred:$src2, IntRegs: $src1)>;
3857 def : Pat<(store (i32 IntRegs:$src1), u0AlwaysExtPred:$src2),
3858 (S2_storeriabs u0AlwaysExtPred:$src2, IntRegs: $src1)>;
3861 let Predicates = [HasV4T], AddedComplexity = 30 in {
3862 def : Pat<(i32 (load u0AlwaysExtPred:$src)),
3863 (L4_loadri_abs u0AlwaysExtPred:$src)>;
3865 def : Pat<(i32 (sextloadi8 u0AlwaysExtPred:$src)),
3866 (L4_loadrb_abs u0AlwaysExtPred:$src)>;
3868 def : Pat<(i32 (zextloadi8 u0AlwaysExtPred:$src)),
3869 (L4_loadrub_abs u0AlwaysExtPred:$src)>;
3871 def : Pat<(i32 (sextloadi16 u0AlwaysExtPred:$src)),
3872 (L4_loadrh_abs u0AlwaysExtPred:$src)>;
3874 def : Pat<(i32 (zextloadi16 u0AlwaysExtPred:$src)),
3875 (L4_loadruh_abs u0AlwaysExtPred:$src)>;
3878 // Indexed store word - global address.
3879 // memw(Rs+#u6:2)=#S8
3880 let AddedComplexity = 10 in
3881 def STriw_offset_ext_V4 : STInst<(outs),
3882 (ins IntRegs:$src1, u6_2Imm:$src2, globaladdress:$src3),
3883 "memw($src1+#$src2) = ##$src3",
3884 [(store (HexagonCONST32 tglobaladdr:$src3),
3885 (add IntRegs:$src1, u6_2ImmPred:$src2))]>,
3888 def : Pat<(i64 (ctlz (i64 DoubleRegs:$src1))),
3889 (i64 (A4_combineir (i32 0), (i32 (S2_cl0p DoubleRegs:$src1))))>,
3892 def : Pat<(i64 (cttz (i64 DoubleRegs:$src1))),
3893 (i64 (A4_combineir (i32 0), (i32 (S2_ct0p DoubleRegs:$src1))))>,
3898 // We need a complexity of 120 here to override preceding handling of
3900 let Predicates = [HasV4T], AddedComplexity = 120 in {
3901 def: Pat <(i64 (extloadi8 (NumUsesBelowThresCONST32 tglobaladdr:$addr))),
3902 (i64 (A4_combineir 0, (L4_loadrb_abs tglobaladdr:$addr)))>;
3904 def: Pat <(i64 (zextloadi8 (NumUsesBelowThresCONST32 tglobaladdr:$addr))),
3905 (i64 (A4_combineir 0, (L4_loadrub_abs tglobaladdr:$addr)))>;
3907 def: Pat <(i64 (sextloadi8 (NumUsesBelowThresCONST32 tglobaladdr:$addr))),
3908 (i64 (A2_sxtw (L4_loadrb_abs tglobaladdr:$addr)))>;
3910 def: Pat <(i64 (extloadi8 FoldGlobalAddr:$addr)),
3911 (i64 (A4_combineir 0, (L4_loadrb_abs FoldGlobalAddr:$addr)))>;
3913 def: Pat <(i64 (zextloadi8 FoldGlobalAddr:$addr)),
3914 (i64 (A4_combineir 0, (L4_loadrub_abs FoldGlobalAddr:$addr)))>;
3916 def: Pat <(i64 (sextloadi8 FoldGlobalAddr:$addr)),
3917 (i64 (A2_sxtw (L4_loadrb_abs FoldGlobalAddr:$addr)))>;
3920 // We need a complexity of 120 here to override preceding handling of
3922 let AddedComplexity = 120 in {
3923 def: Pat <(i64 (extloadi16 (NumUsesBelowThresCONST32 tglobaladdr:$addr))),
3924 (i64 (A4_combineir 0, (L4_loadrh_abs tglobaladdr:$addr)))>,
3927 def: Pat <(i64 (zextloadi16 (NumUsesBelowThresCONST32 tglobaladdr:$addr))),
3928 (i64 (A4_combineir 0, (L4_loadruh_abs tglobaladdr:$addr)))>,
3931 def: Pat <(i64 (sextloadi16 (NumUsesBelowThresCONST32 tglobaladdr:$addr))),
3932 (i64 (A2_sxtw (L4_loadrh_abs tglobaladdr:$addr)))>,
3935 def: Pat <(i64 (extloadi16 FoldGlobalAddr:$addr)),
3936 (i64 (A4_combineir 0, (L4_loadrh_abs FoldGlobalAddr:$addr)))>,
3939 def: Pat <(i64 (zextloadi16 FoldGlobalAddr:$addr)),
3940 (i64 (A4_combineir 0, (L4_loadruh_abs FoldGlobalAddr:$addr)))>,
3943 def: Pat <(i64 (sextloadi16 FoldGlobalAddr:$addr)),
3944 (i64 (A2_sxtw (L4_loadrh_abs FoldGlobalAddr:$addr)))>,
3948 // We need a complexity of 120 here to override preceding handling of
3950 let AddedComplexity = 120 in {
3951 def: Pat <(i64 (extloadi32 (NumUsesBelowThresCONST32 tglobaladdr:$addr))),
3952 (i64 (A4_combineir 0, (L4_loadri_abs tglobaladdr:$addr)))>,
3955 def: Pat <(i64 (zextloadi32 (NumUsesBelowThresCONST32 tglobaladdr:$addr))),
3956 (i64 (A4_combineir 0, (L4_loadri_abs tglobaladdr:$addr)))>,
3959 def: Pat <(i64 (sextloadi32 (NumUsesBelowThresCONST32 tglobaladdr:$addr))),
3960 (i64 (A2_sxtw (L4_loadri_abs tglobaladdr:$addr)))>,
3963 def: Pat <(i64 (extloadi32 FoldGlobalAddr:$addr)),
3964 (i64 (A4_combineir 0, (L4_loadri_abs FoldGlobalAddr:$addr)))>,
3967 def: Pat <(i64 (zextloadi32 FoldGlobalAddr:$addr)),
3968 (i64 (A4_combineir 0, (L4_loadri_abs FoldGlobalAddr:$addr)))>,
3971 def: Pat <(i64 (sextloadi32 FoldGlobalAddr:$addr)),
3972 (i64 (A2_sxtw (L4_loadri_abs FoldGlobalAddr:$addr)))>,
3976 // Indexed store double word - global address.
3977 // memw(Rs+#u6:2)=#S8
3978 let AddedComplexity = 10 in
3979 def STrih_offset_ext_V4 : STInst<(outs),
3980 (ins IntRegs:$src1, u6_1Imm:$src2, globaladdress:$src3),
3981 "memh($src1+#$src2) = ##$src3",
3982 [(truncstorei16 (HexagonCONST32 tglobaladdr:$src3),
3983 (add IntRegs:$src1, u6_1ImmPred:$src2))]>,
3985 // Map from store(globaladdress + x) -> memd(#foo + x)
3986 let AddedComplexity = 100 in
3987 def : Pat<(store (i64 DoubleRegs:$src1),
3988 FoldGlobalAddrGP:$addr),
3989 (S2_storerdabs FoldGlobalAddrGP:$addr, (i64 DoubleRegs:$src1))>,
3992 def : Pat<(atomic_store_64 FoldGlobalAddrGP:$addr,
3993 (i64 DoubleRegs:$src1)),
3994 (S2_storerdabs FoldGlobalAddrGP:$addr, (i64 DoubleRegs:$src1))>,
3997 // Map from store(globaladdress + x) -> memb(#foo + x)
3998 let AddedComplexity = 100 in
3999 def : Pat<(truncstorei8 (i32 IntRegs:$src1), FoldGlobalAddrGP:$addr),
4000 (S2_storerbabs FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1))>,
4003 def : Pat<(atomic_store_8 FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1)),
4004 (S2_storerbabs FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1))>,
4007 // Map from store(globaladdress + x) -> memh(#foo + x)
4008 let AddedComplexity = 100 in
4009 def : Pat<(truncstorei16 (i32 IntRegs:$src1), FoldGlobalAddrGP:$addr),
4010 (S2_storerhabs FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1))>,
4013 def : Pat<(atomic_store_16 FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1)),
4014 (S2_storerhabs FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1))>,
4017 // Map from store(globaladdress + x) -> memw(#foo + x)
4018 let AddedComplexity = 100 in
4019 def : Pat<(store (i32 IntRegs:$src1), FoldGlobalAddrGP:$addr),
4020 (S2_storeriabs FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1))>,
4023 def : Pat<(atomic_store_32 FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1)),
4024 (S2_storeriabs FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1))>,
4027 // Map from load(globaladdress + x) -> memd(#foo + x)
4028 let AddedComplexity = 100 in
4029 def : Pat<(i64 (load FoldGlobalAddrGP:$addr)),
4030 (i64 (L4_loadrd_abs FoldGlobalAddrGP:$addr))>,
4033 def : Pat<(atomic_load_64 FoldGlobalAddrGP:$addr),
4034 (i64 (L4_loadrd_abs FoldGlobalAddrGP:$addr))>,
4037 // Map from load(globaladdress + x) -> memb(#foo + x)
4038 let AddedComplexity = 100 in
4039 def : Pat<(i32 (extloadi8 FoldGlobalAddrGP:$addr)),
4040 (i32 (L4_loadrb_abs FoldGlobalAddrGP:$addr))>,
4043 // Map from load(globaladdress + x) -> memb(#foo + x)
4044 let AddedComplexity = 100 in
4045 def : Pat<(i32 (sextloadi8 FoldGlobalAddrGP:$addr)),
4046 (i32 (L4_loadrb_abs FoldGlobalAddrGP:$addr))>,
4049 //let AddedComplexity = 100 in
4050 let AddedComplexity = 100 in
4051 def : Pat<(i32 (extloadi16 FoldGlobalAddrGP:$addr)),
4052 (i32 (L4_loadrh_abs FoldGlobalAddrGP:$addr))>,
4055 // Map from load(globaladdress + x) -> memh(#foo + x)
4056 let AddedComplexity = 100 in
4057 def : Pat<(i32 (sextloadi16 FoldGlobalAddrGP:$addr)),
4058 (i32 (L4_loadrh_abs FoldGlobalAddrGP:$addr))>,
4061 // Map from load(globaladdress + x) -> memuh(#foo + x)
4062 let AddedComplexity = 100 in
4063 def : Pat<(i32 (zextloadi16 FoldGlobalAddrGP:$addr)),
4064 (i32 (L4_loadruh_abs FoldGlobalAddrGP:$addr))>,
4067 def : Pat<(atomic_load_16 FoldGlobalAddrGP:$addr),
4068 (i32 (L4_loadruh_abs FoldGlobalAddrGP:$addr))>,
4071 // Map from load(globaladdress + x) -> memub(#foo + x)
4072 let AddedComplexity = 100 in
4073 def : Pat<(i32 (zextloadi8 FoldGlobalAddrGP:$addr)),
4074 (i32 (L4_loadrub_abs FoldGlobalAddrGP:$addr))>,
4077 def : Pat<(atomic_load_8 FoldGlobalAddrGP:$addr),
4078 (i32 (L4_loadrub_abs FoldGlobalAddrGP:$addr))>,
4081 // Map from load(globaladdress + x) -> memw(#foo + x)
4082 let AddedComplexity = 100 in
4083 def : Pat<(i32 (load FoldGlobalAddrGP:$addr)),
4084 (i32 (L4_loadri_abs FoldGlobalAddrGP:$addr))>,
4087 def : Pat<(atomic_load_32 FoldGlobalAddrGP:$addr),
4088 (i32 (L4_loadri_abs FoldGlobalAddrGP:$addr))>,
4091 //===----------------------------------------------------------------------===//
4092 // :raw for of boundscheck:hi:lo insns
4093 //===----------------------------------------------------------------------===//
4095 // A4_boundscheck_lo: Detect if a register is within bounds.
4096 let hasSideEffects = 0, isCodeGenOnly = 0 in
4097 def A4_boundscheck_lo: ALU64Inst <
4098 (outs PredRegs:$Pd),
4099 (ins DoubleRegs:$Rss, DoubleRegs:$Rtt),
4100 "$Pd = boundscheck($Rss, $Rtt):raw:lo"> {
4105 let IClass = 0b1101;
4107 let Inst{27-23} = 0b00100;
4109 let Inst{7-5} = 0b100;
4111 let Inst{20-16} = Rss;
4112 let Inst{12-8} = Rtt;
4115 // A4_boundscheck_hi: Detect if a register is within bounds.
4116 let hasSideEffects = 0, isCodeGenOnly = 0 in
4117 def A4_boundscheck_hi: ALU64Inst <
4118 (outs PredRegs:$Pd),
4119 (ins DoubleRegs:$Rss, DoubleRegs:$Rtt),
4120 "$Pd = boundscheck($Rss, $Rtt):raw:hi"> {
4125 let IClass = 0b1101;
4127 let Inst{27-23} = 0b00100;
4129 let Inst{7-5} = 0b101;
4131 let Inst{20-16} = Rss;
4132 let Inst{12-8} = Rtt;
4135 let hasSideEffects = 0 in
4136 def A4_boundscheck : MInst <
4137 (outs PredRegs:$Pd), (ins IntRegs:$Rs, DoubleRegs:$Rtt),
4138 "$Pd=boundscheck($Rs,$Rtt)">;
4140 // A4_tlbmatch: Detect if a VA/ASID matches a TLB entry.
4141 let isPredicateLate = 1, hasSideEffects = 0, isCodeGenOnly = 0 in
4142 def A4_tlbmatch : ALU64Inst<(outs PredRegs:$Pd),
4143 (ins DoubleRegs:$Rs, IntRegs:$Rt),
4144 "$Pd = tlbmatch($Rs, $Rt)",
4145 [], "", ALU64_tc_2early_SLOT23> {
4150 let IClass = 0b1101;
4151 let Inst{27-23} = 0b00100;
4152 let Inst{20-16} = Rs;
4154 let Inst{12-8} = Rt;
4155 let Inst{7-5} = 0b011;
4159 // We need custom lowering of ISD::PREFETCH into HexagonISD::DCFETCH
4160 // because the SDNode ISD::PREFETCH has properties MayLoad and MayStore.
4161 // We don't really want either one here.
4162 def SDTHexagonDCFETCH : SDTypeProfile<0, 2, [SDTCisPtrTy<0>,SDTCisInt<1>]>;
4163 def HexagonDCFETCH : SDNode<"HexagonISD::DCFETCH", SDTHexagonDCFETCH,
4166 // Use LD0Inst for dcfetch, but set "mayLoad" to 0 because this doesn't
4167 // really do a load.
4168 let hasSideEffects = 1, mayLoad = 0, isCodeGenOnly = 0 in
4169 def Y2_dcfetchbo : LD0Inst<(outs), (ins IntRegs:$Rs, u11_3Imm:$u11_3),
4170 "dcfetch($Rs + #$u11_3)",
4171 [(HexagonDCFETCH IntRegs:$Rs, u11_3ImmPred:$u11_3)],
4172 "", LD_tc_ld_SLOT0> {
4176 let IClass = 0b1001;
4177 let Inst{27-21} = 0b0100000;
4178 let Inst{20-16} = Rs;
4180 let Inst{10-0} = u11_3{13-3};
4183 //===----------------------------------------------------------------------===//
4184 // Compound instructions
4185 //===----------------------------------------------------------------------===//
4187 let isBranch = 1, hasSideEffects = 0, isExtentSigned = 1,
4188 isPredicated = 1, isPredicatedNew = 1, isExtendable = 1,
4189 opExtentBits = 11, opExtentAlign = 2, opExtendable = 1,
4190 isTerminator = 1, validSubTargets = HasV4SubT in
4191 class CJInst_tstbit_R0<string px, bit np, string tnt>
4192 : InstHexagon<(outs), (ins IntRegs:$Rs, brtarget:$r9_2),
4193 ""#px#" = tstbit($Rs, #0); if ("
4194 #!if(np, "!","")#""#px#".new) jump:"#tnt#" $r9_2",
4195 [], "", COMPOUND, TypeCOMPOUND> {
4200 let isPredicatedFalse = np;
4201 // tnt: Taken/Not Taken
4202 let isBrTaken = !if (!eq(tnt, "t"), "true", "false");
4203 let isTaken = !if (!eq(tnt, "t"), 1, 0);
4205 let IClass = 0b0001;
4206 let Inst{27-26} = 0b00;
4207 let Inst{25} = !if (!eq(px, "!p1"), 1,
4208 !if (!eq(px, "p1"), 1, 0));
4209 let Inst{24-23} = 0b11;
4211 let Inst{21-20} = r9_2{10-9};
4212 let Inst{19-16} = Rs;
4213 let Inst{13} = !if (!eq(tnt, "t"), 1, 0);
4214 let Inst{9-8} = 0b11;
4215 let Inst{7-1} = r9_2{8-2};
4218 let Defs = [PC, P0], Uses = [P0], isCodeGenOnly = 0 in {
4219 def J4_tstbit0_tp0_jump_nt : CJInst_tstbit_R0<"p0", 0, "nt">;
4220 def J4_tstbit0_tp0_jump_t : CJInst_tstbit_R0<"p0", 0, "t">;
4221 def J4_tstbit0_fp0_jump_nt : CJInst_tstbit_R0<"p0", 1, "nt">;
4222 def J4_tstbit0_fp0_jump_t : CJInst_tstbit_R0<"p0", 1, "t">;
4225 let Defs = [PC, P1], Uses = [P1], isCodeGenOnly = 0 in {
4226 def J4_tstbit0_tp1_jump_nt : CJInst_tstbit_R0<"p1", 0, "nt">;
4227 def J4_tstbit0_tp1_jump_t : CJInst_tstbit_R0<"p1", 0, "t">;
4228 def J4_tstbit0_fp1_jump_nt : CJInst_tstbit_R0<"p1", 1, "nt">;
4229 def J4_tstbit0_fp1_jump_t : CJInst_tstbit_R0<"p1", 1, "t">;
4233 let isBranch = 1, hasSideEffects = 0,
4234 isExtentSigned = 1, isPredicated = 1, isPredicatedNew = 1,
4235 isExtendable = 1, opExtentBits = 11, opExtentAlign = 2,
4236 opExtendable = 2, isTerminator = 1, validSubTargets = HasV4SubT in
4237 class CJInst_RR<string px, string op, bit np, string tnt>
4238 : InstHexagon<(outs), (ins IntRegs:$Rs, IntRegs:$Rt, brtarget:$r9_2),
4239 ""#px#" = cmp."#op#"($Rs, $Rt); if ("
4240 #!if(np, "!","")#""#px#".new) jump:"#tnt#" $r9_2",
4241 [], "", COMPOUND, TypeCOMPOUND> {
4247 let isPredicatedFalse = np;
4248 // tnt: Taken/Not Taken
4249 let isBrTaken = !if (!eq(tnt, "t"), "true", "false");
4250 let isTaken = !if (!eq(tnt, "t"), 1, 0);
4252 let IClass = 0b0001;
4253 let Inst{27-23} = !if (!eq(op, "eq"), 0b01000,
4254 !if (!eq(op, "gt"), 0b01001,
4255 !if (!eq(op, "gtu"), 0b01010, 0)));
4257 let Inst{21-20} = r9_2{10-9};
4258 let Inst{19-16} = Rs;
4259 let Inst{13} = !if (!eq(tnt, "t"), 1, 0);
4260 // px: Predicate reg 0/1
4261 let Inst{12} = !if (!eq(px, "!p1"), 1,
4262 !if (!eq(px, "p1"), 1, 0));
4263 let Inst{11-8} = Rt;
4264 let Inst{7-1} = r9_2{8-2};
4267 // P[10] taken/not taken.
4268 multiclass T_tnt_CJInst_RR<string op, bit np> {
4269 let Defs = [PC, P0], Uses = [P0] in {
4270 def NAME#p0_jump_nt : CJInst_RR<"p0", op, np, "nt">;
4271 def NAME#p0_jump_t : CJInst_RR<"p0", op, np, "t">;
4273 let Defs = [PC, P1], Uses = [P1] in {
4274 def NAME#p1_jump_nt : CJInst_RR<"p1", op, np, "nt">;
4275 def NAME#p1_jump_t : CJInst_RR<"p1", op, np, "t">;
4278 // Predicate / !Predicate
4279 multiclass T_pnp_CJInst_RR<string op>{
4280 defm J4_cmp#NAME#_t : T_tnt_CJInst_RR<op, 0>;
4281 defm J4_cmp#NAME#_f : T_tnt_CJInst_RR<op, 1>;
4283 // TypeCJ Instructions compare RR and jump
4284 let isCodeGenOnly = 0 in {
4285 defm eq : T_pnp_CJInst_RR<"eq">;
4286 defm gt : T_pnp_CJInst_RR<"gt">;
4287 defm gtu : T_pnp_CJInst_RR<"gtu">;
4290 let isBranch = 1, hasSideEffects = 0, isExtentSigned = 1,
4291 isPredicated = 1, isPredicatedNew = 1, isExtendable = 1, opExtentBits = 11,
4292 opExtentAlign = 2, opExtendable = 2, isTerminator = 1,
4293 validSubTargets = HasV4SubT in
4294 class CJInst_RU5<string px, string op, bit np, string tnt>
4295 : InstHexagon<(outs), (ins IntRegs:$Rs, u5Imm:$U5, brtarget:$r9_2),
4296 ""#px#" = cmp."#op#"($Rs, #$U5); if ("
4297 #!if(np, "!","")#""#px#".new) jump:"#tnt#" $r9_2",
4298 [], "", COMPOUND, TypeCOMPOUND> {
4304 let isPredicatedFalse = np;
4305 // tnt: Taken/Not Taken
4306 let isBrTaken = !if (!eq(tnt, "t"), "true", "false");
4307 let isTaken = !if (!eq(tnt, "t"), 1, 0);
4309 let IClass = 0b0001;
4310 let Inst{27-26} = 0b00;
4311 // px: Predicate reg 0/1
4312 let Inst{25} = !if (!eq(px, "!p1"), 1,
4313 !if (!eq(px, "p1"), 1, 0));
4314 let Inst{24-23} = !if (!eq(op, "eq"), 0b00,
4315 !if (!eq(op, "gt"), 0b01,
4316 !if (!eq(op, "gtu"), 0b10, 0)));
4318 let Inst{21-20} = r9_2{10-9};
4319 let Inst{19-16} = Rs;
4320 let Inst{13} = !if (!eq(tnt, "t"), 1, 0);
4321 let Inst{12-8} = U5;
4322 let Inst{7-1} = r9_2{8-2};
4324 // P[10] taken/not taken.
4325 multiclass T_tnt_CJInst_RU5<string op, bit np> {
4326 let Defs = [PC, P0], Uses = [P0] in {
4327 def NAME#p0_jump_nt : CJInst_RU5<"p0", op, np, "nt">;
4328 def NAME#p0_jump_t : CJInst_RU5<"p0", op, np, "t">;
4330 let Defs = [PC, P1], Uses = [P1] in {
4331 def NAME#p1_jump_nt : CJInst_RU5<"p1", op, np, "nt">;
4332 def NAME#p1_jump_t : CJInst_RU5<"p1", op, np, "t">;
4335 // Predicate / !Predicate
4336 multiclass T_pnp_CJInst_RU5<string op>{
4337 defm J4_cmp#NAME#i_t : T_tnt_CJInst_RU5<op, 0>;
4338 defm J4_cmp#NAME#i_f : T_tnt_CJInst_RU5<op, 1>;
4340 // TypeCJ Instructions compare RI and jump
4341 let isCodeGenOnly = 0 in {
4342 defm eq : T_pnp_CJInst_RU5<"eq">;
4343 defm gt : T_pnp_CJInst_RU5<"gt">;
4344 defm gtu : T_pnp_CJInst_RU5<"gtu">;
4347 let isBranch = 1, hasSideEffects = 0, isExtentSigned = 1,
4348 isPredicated = 1, isPredicatedFalse = 1, isPredicatedNew = 1,
4349 isExtendable = 1, opExtentBits = 11, opExtentAlign = 2, opExtendable = 1,
4350 isTerminator = 1, validSubTargets = HasV4SubT in
4351 class CJInst_Rn1<string px, string op, bit np, string tnt>
4352 : InstHexagon<(outs), (ins IntRegs:$Rs, brtarget:$r9_2),
4353 ""#px#" = cmp."#op#"($Rs,#-1); if ("
4354 #!if(np, "!","")#""#px#".new) jump:"#tnt#" $r9_2",
4355 [], "", COMPOUND, TypeCOMPOUND> {
4360 let isPredicatedFalse = np;
4361 // tnt: Taken/Not Taken
4362 let isBrTaken = !if (!eq(tnt, "t"), "true", "false");
4363 let isTaken = !if (!eq(tnt, "t"), 1, 0);
4365 let IClass = 0b0001;
4366 let Inst{27-26} = 0b00;
4367 let Inst{25} = !if (!eq(px, "!p1"), 1,
4368 !if (!eq(px, "p1"), 1, 0));
4370 let Inst{24-23} = 0b11;
4372 let Inst{21-20} = r9_2{10-9};
4373 let Inst{19-16} = Rs;
4374 let Inst{13} = !if (!eq(tnt, "t"), 1, 0);
4375 let Inst{9-8} = !if (!eq(op, "eq"), 0b00,
4376 !if (!eq(op, "gt"), 0b01, 0));
4377 let Inst{7-1} = r9_2{8-2};
4380 // P[10] taken/not taken.
4381 multiclass T_tnt_CJInst_Rn1<string op, bit np> {
4382 let Defs = [PC, P0], Uses = [P0] in {
4383 def NAME#p0_jump_nt : CJInst_Rn1<"p0", op, np, "nt">;
4384 def NAME#p0_jump_t : CJInst_Rn1<"p0", op, np, "t">;
4386 let Defs = [PC, P1], Uses = [P1] in {
4387 def NAME#p1_jump_nt : CJInst_Rn1<"p1", op, np, "nt">;
4388 def NAME#p1_jump_t : CJInst_Rn1<"p1", op, np, "t">;
4391 // Predicate / !Predicate
4392 multiclass T_pnp_CJInst_Rn1<string op>{
4393 defm J4_cmp#NAME#n1_t : T_tnt_CJInst_Rn1<op, 0>;
4394 defm J4_cmp#NAME#n1_f : T_tnt_CJInst_Rn1<op, 1>;
4396 // TypeCJ Instructions compare -1 and jump
4397 let isCodeGenOnly = 0 in {
4398 defm eq : T_pnp_CJInst_Rn1<"eq">;
4399 defm gt : T_pnp_CJInst_Rn1<"gt">;
4402 // J4_jumpseti: Direct unconditional jump and set register to immediate.
4403 let Defs = [PC], isBranch = 1, hasSideEffects = 0, hasNewValue = 1,
4404 isExtentSigned = 1, opNewValue = 0, isExtendable = 1, opExtentBits = 11,
4405 opExtentAlign = 2, opExtendable = 2, validSubTargets = HasV4SubT,
4406 isCodeGenOnly = 0 in
4407 def J4_jumpseti: CJInst <
4409 (ins u6Imm:$U6, brtarget:$r9_2),
4410 "$Rd = #$U6 ; jump $r9_2"> {
4415 let IClass = 0b0001;
4416 let Inst{27-24} = 0b0110;
4417 let Inst{21-20} = r9_2{10-9};
4418 let Inst{19-16} = Rd;
4419 let Inst{13-8} = U6;
4420 let Inst{7-1} = r9_2{8-2};
4423 // J4_jumpsetr: Direct unconditional jump and transfer register.
4424 let Defs = [PC], isBranch = 1, hasSideEffects = 0, hasNewValue = 1,
4425 isExtentSigned = 1, opNewValue = 0, isExtendable = 1, opExtentBits = 11,
4426 opExtentAlign = 2, opExtendable = 2, validSubTargets = HasV4SubT,
4427 isCodeGenOnly = 0 in
4428 def J4_jumpsetr: CJInst <
4430 (ins IntRegs:$Rs, brtarget:$r9_2),
4431 "$Rd = $Rs ; jump $r9_2"> {
4436 let IClass = 0b0001;
4437 let Inst{27-24} = 0b0111;
4438 let Inst{21-20} = r9_2{10-9};
4439 let Inst{11-8} = Rd;
4440 let Inst{19-16} = Rs;
4441 let Inst{7-1} = r9_2{8-2};