1 //=- HexagonInstrInfoV4.td - Target Desc. for Hexagon Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Hexagon V4 instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 let hasSideEffects = 0 in
15 class T_Immext<Operand ImmType>
16 : EXTENDERInst<(outs), (ins ImmType:$imm),
17 "immext(#$imm)", []> {
21 let Inst{27-16} = imm{31-20};
22 let Inst{13-0} = imm{19-6};
25 def A4_ext : T_Immext<u26_6Imm>;
26 let isCodeGenOnly = 1 in {
28 def A4_ext_b : T_Immext<brtarget>;
30 def A4_ext_c : T_Immext<calltarget>;
31 def A4_ext_g : T_Immext<globaladdress>;
34 // Fold (add (CONST32 tglobaladdr:$addr) <offset>) into a global address.
35 def FoldGlobalAddr : ComplexPattern<i32, 1, "foldGlobalAddress", [], []>;
37 // Fold (add (CONST32_GP tglobaladdr:$addr) <offset>) into a global address.
38 def FoldGlobalAddrGP : ComplexPattern<i32, 1, "foldGlobalAddressGP", [], []>;
40 def NumUsesBelowThresCONST32 : PatFrag<(ops node:$addr),
41 (HexagonCONST32 node:$addr), [{
42 return hasNumUsesBelowThresGA(N->getOperand(0).getNode());
45 // Hexagon V4 Architecture spec defines 8 instruction classes:
46 // LD ST ALU32 XTYPE J JR MEMOP NV CR SYSTEM(system is not implemented in the
50 // ========================================
51 // Loads (8/16/32/64 bit)
55 // ========================================
56 // Stores (8/16/32/64 bit)
59 // ALU32 Instructions:
60 // ========================================
61 // Arithmetic / Logical (32 bit)
64 // XTYPE Instructions (32/64 bit):
65 // ========================================
66 // Arithmetic, Logical, Bit Manipulation
67 // Multiply (Integer, Fractional, Complex)
68 // Permute / Vector Permute Operations
69 // Predicate Operations
70 // Shift / Shift with Add/Sub/Logical
72 // Vector Halfword (ALU, Shift, Multiply)
73 // Vector Word (ALU, Shift)
76 // ========================================
77 // Jump/Call PC-relative
80 // ========================================
83 // MEMOP Instructions:
84 // ========================================
85 // Operation on memory (8/16/32 bit)
88 // ========================================
93 // ========================================
94 // Control-Register Transfers
95 // Hardware Loop Setup
96 // Predicate Logicals & Reductions
98 // SYSTEM Instructions (not implemented in the compiler):
99 // ========================================
105 //===----------------------------------------------------------------------===//
107 //===----------------------------------------------------------------------===//
109 class T_ALU32_3op_not<string mnemonic, bits<3> MajOp, bits<3> MinOp,
111 : T_ALU32_3op<mnemonic, MajOp, MinOp, OpsRev, 0> {
112 let AsmString = "$Rd = "#mnemonic#"($Rs, ~$Rt)";
115 let BaseOpcode = "andn_rr", CextOpcode = "andn", isCodeGenOnly = 0 in
116 def A4_andn : T_ALU32_3op_not<"and", 0b001, 0b100, 1>;
117 let BaseOpcode = "orn_rr", CextOpcode = "orn", isCodeGenOnly = 0 in
118 def A4_orn : T_ALU32_3op_not<"or", 0b001, 0b101, 1>;
120 let CextOpcode = "rcmp.eq", isCodeGenOnly = 0 in
121 def A4_rcmpeq : T_ALU32_3op<"cmp.eq", 0b011, 0b010, 0, 1>;
122 let CextOpcode = "!rcmp.eq", isCodeGenOnly = 0 in
123 def A4_rcmpneq : T_ALU32_3op<"!cmp.eq", 0b011, 0b011, 0, 1>;
125 let isCodeGenOnly = 0 in {
126 def C4_cmpneq : T_ALU32_3op_cmp<"!cmp.eq", 0b00, 1, 1>;
127 def C4_cmplte : T_ALU32_3op_cmp<"!cmp.gt", 0b10, 1, 0>;
128 def C4_cmplteu : T_ALU32_3op_cmp<"!cmp.gtu", 0b11, 1, 0>;
131 // Pats for instruction selection.
133 // A class to embed the usual comparison patfrags within a zext to i32.
134 // The seteq/setne frags use "lhs" and "rhs" as operands, so use the same
135 // names, or else the frag's "body" won't match the operands.
136 class CmpInReg<PatFrag Op>
137 : PatFrag<(ops node:$lhs, node:$rhs),(i32 (zext (i1 Op.Fragment)))>;
139 def: T_cmp32_rr_pat<A4_rcmpeq, CmpInReg<seteq>, i32>;
140 def: T_cmp32_rr_pat<A4_rcmpneq, CmpInReg<setne>, i32>;
142 class T_CMP_rrbh<string mnemonic, bits<3> MinOp, bit IsComm>
143 : SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, IntRegs:$Rt),
144 "$Pd = "#mnemonic#"($Rs, $Rt)", [], "", S_3op_tc_2early_SLOT23>,
146 let validSubTargets = HasV4SubT;
147 let InputType = "reg";
148 let CextOpcode = mnemonic;
150 let isCommutable = IsComm;
151 let hasSideEffects = 0;
158 let Inst{27-21} = 0b0111110;
159 let Inst{20-16} = Rs;
161 let Inst{7-5} = MinOp;
165 let isCodeGenOnly = 0 in {
166 def A4_cmpbeq : T_CMP_rrbh<"cmpb.eq", 0b110, 1>;
167 def A4_cmpbgt : T_CMP_rrbh<"cmpb.gt", 0b010, 0>;
168 def A4_cmpbgtu : T_CMP_rrbh<"cmpb.gtu", 0b111, 0>;
169 def A4_cmpheq : T_CMP_rrbh<"cmph.eq", 0b011, 1>;
170 def A4_cmphgt : T_CMP_rrbh<"cmph.gt", 0b100, 0>;
171 def A4_cmphgtu : T_CMP_rrbh<"cmph.gtu", 0b101, 0>;
174 class T_CMP_ribh<string mnemonic, bits<2> MajOp, bit IsHalf, bit IsComm,
175 Operand ImmType, bit IsImmExt, bit IsImmSigned, int ImmBits>
176 : ALU64Inst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, ImmType:$Imm),
177 "$Pd = "#mnemonic#"($Rs, #$Imm)", [], "", ALU64_tc_2early_SLOT23>,
179 let validSubTargets = HasV4SubT;
180 let InputType = "imm";
181 let CextOpcode = mnemonic;
183 let isCommutable = IsComm;
184 let hasSideEffects = 0;
185 let isExtendable = IsImmExt;
186 let opExtendable = !if (IsImmExt, 2, 0);
187 let isExtentSigned = IsImmSigned;
188 let opExtentBits = ImmBits;
195 let Inst{27-24} = 0b1101;
196 let Inst{22-21} = MajOp;
197 let Inst{20-16} = Rs;
198 let Inst{12-5} = Imm;
200 let Inst{3} = IsHalf;
204 let isCodeGenOnly = 0 in {
205 def A4_cmpbeqi : T_CMP_ribh<"cmpb.eq", 0b00, 0, 1, u8Imm, 0, 0, 8>;
206 def A4_cmpbgti : T_CMP_ribh<"cmpb.gt", 0b01, 0, 0, s8Imm, 0, 1, 8>;
207 def A4_cmpbgtui : T_CMP_ribh<"cmpb.gtu", 0b10, 0, 0, u7Ext, 1, 0, 7>;
208 def A4_cmpheqi : T_CMP_ribh<"cmph.eq", 0b00, 1, 1, s8Ext, 1, 1, 8>;
209 def A4_cmphgti : T_CMP_ribh<"cmph.gt", 0b01, 1, 0, s8Ext, 1, 1, 8>;
210 def A4_cmphgtui : T_CMP_ribh<"cmph.gtu", 0b10, 1, 0, u7Ext, 1, 0, 7>;
212 class T_RCMP_EQ_ri<string mnemonic, bit IsNeg>
213 : ALU32_ri<(outs IntRegs:$Rd), (ins IntRegs:$Rs, s8Ext:$s8),
214 "$Rd = "#mnemonic#"($Rs, #$s8)", [], "", ALU32_2op_tc_1_SLOT0123>,
216 let validSubTargets = HasV4SubT;
217 let InputType = "imm";
218 let CextOpcode = !if (IsNeg, "!rcmp.eq", "rcmp.eq");
219 let isExtendable = 1;
220 let opExtendable = 2;
221 let isExtentSigned = 1;
222 let opExtentBits = 8;
230 let Inst{27-24} = 0b0011;
232 let Inst{21} = IsNeg;
233 let Inst{20-16} = Rs;
239 let isCodeGenOnly = 0 in {
240 def A4_rcmpeqi : T_RCMP_EQ_ri<"cmp.eq", 0>;
241 def A4_rcmpneqi : T_RCMP_EQ_ri<"!cmp.eq", 1>;
244 def: Pat<(i32 (zext (i1 (seteq (i32 IntRegs:$Rs), s8ExtPred:$s8)))),
245 (A4_rcmpeqi IntRegs:$Rs, s8ExtPred:$s8)>;
246 def: Pat<(i32 (zext (i1 (setne (i32 IntRegs:$Rs), s8ExtPred:$s8)))),
247 (A4_rcmpneqi IntRegs:$Rs, s8ExtPred:$s8)>;
249 // Preserve the S2_tstbit_r generation
250 def: Pat<(i32 (zext (i1 (setne (i32 (and (i32 (shl 1, (i32 IntRegs:$src2))),
251 (i32 IntRegs:$src1))), 0)))),
252 (C2_muxii (S2_tstbit_r IntRegs:$src1, IntRegs:$src2), 1, 0)>;
255 //===----------------------------------------------------------------------===//
257 //===----------------------------------------------------------------------===//
260 //===----------------------------------------------------------------------===//
262 //===----------------------------------------------------------------------===//
264 // Combine a word and an immediate into a register pair.
265 let hasSideEffects = 0, isExtentSigned = 1, isExtendable = 1,
267 class T_Combine1 <bits<2> MajOp, dag ins, string AsmStr>
268 : ALU32Inst <(outs DoubleRegs:$Rdd), ins, AsmStr> {
274 let Inst{27-24} = 0b0011;
275 let Inst{22-21} = MajOp;
276 let Inst{20-16} = Rs;
282 let opExtendable = 2, isCodeGenOnly = 0 in
283 def A4_combineri : T_Combine1<0b00, (ins IntRegs:$Rs, s8Ext:$s8),
284 "$Rdd = combine($Rs, #$s8)">;
286 let opExtendable = 1, isCodeGenOnly = 0 in
287 def A4_combineir : T_Combine1<0b01, (ins s8Ext:$s8, IntRegs:$Rs),
288 "$Rdd = combine(#$s8, $Rs)">;
290 def HexagonWrapperCombineRI_V4 :
291 SDNode<"HexagonISD::WrapperCombineRI_V4", SDTHexagonI64I32I32>;
292 def HexagonWrapperCombineIR_V4 :
293 SDNode<"HexagonISD::WrapperCombineIR_V4", SDTHexagonI64I32I32>;
295 def : Pat <(HexagonWrapperCombineRI_V4 IntRegs:$r, s8ExtPred:$i),
296 (A4_combineri IntRegs:$r, s8ExtPred:$i)>,
299 def : Pat <(HexagonWrapperCombineIR_V4 s8ExtPred:$i, IntRegs:$r),
300 (A4_combineir s8ExtPred:$i, IntRegs:$r)>,
303 // A4_combineii: Set two small immediates.
304 let hasSideEffects = 0, isExtendable = 1, opExtentBits = 6, opExtendable = 2 in
305 def A4_combineii: ALU32Inst<(outs DoubleRegs:$Rdd), (ins s8Imm:$s8, u6Ext:$U6),
306 "$Rdd = combine(#$s8, #$U6)"> {
312 let Inst{27-23} = 0b11001;
313 let Inst{20-16} = U6{5-1};
314 let Inst{13} = U6{0};
319 //===----------------------------------------------------------------------===//
321 //===----------------------------------------------------------------------===//
323 //===----------------------------------------------------------------------===//
325 //===----------------------------------------------------------------------===//
326 //===----------------------------------------------------------------------===//
327 // Template class for load instructions with Absolute set addressing mode.
328 //===----------------------------------------------------------------------===//
329 let isExtended = 1, opExtendable = 2, hasSideEffects = 0,
330 validSubTargets = HasV4SubT, addrMode = AbsoluteSet in
331 class T_LD_abs_set<string mnemonic, RegisterClass RC>:
332 LDInst2<(outs RC:$dst1, IntRegs:$dst2),
333 (ins u0AlwaysExt:$addr),
334 "$dst1 = "#mnemonic#"($dst2=##$addr)",
338 def LDrid_abs_set_V4 : T_LD_abs_set <"memd", DoubleRegs>;
339 def LDrib_abs_set_V4 : T_LD_abs_set <"memb", IntRegs>;
340 def LDriub_abs_set_V4 : T_LD_abs_set <"memub", IntRegs>;
341 def LDrih_abs_set_V4 : T_LD_abs_set <"memh", IntRegs>;
342 def LDriw_abs_set_V4 : T_LD_abs_set <"memw", IntRegs>;
343 def LDriuh_abs_set_V4 : T_LD_abs_set <"memuh", IntRegs>;
345 //===----------------------------------------------------------------------===//
346 // Template classes for the non-predicated load instructions with
347 // base + register offset addressing mode
348 //===----------------------------------------------------------------------===//
349 class T_load_rr <string mnemonic, RegisterClass RC, bits<3> MajOp>:
350 LDInst<(outs RC:$dst), (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$u2),
351 "$dst = "#mnemonic#"($src1 + $src2<<#$u2)",
352 [], "", V4LDST_tc_ld_SLOT01>, ImmRegShl, AddrModeRel {
360 let Inst{27-24} = 0b1010;
361 let Inst{23-21} = MajOp;
362 let Inst{20-16} = src1;
363 let Inst{12-8} = src2;
364 let Inst{13} = u2{1};
369 //===----------------------------------------------------------------------===//
370 // Template classes for the predicated load instructions with
371 // base + register offset addressing mode
372 //===----------------------------------------------------------------------===//
373 let isPredicated = 1 in
374 class T_pload_rr <string mnemonic, RegisterClass RC, bits<3> MajOp,
375 bit isNot, bit isPredNew>:
376 LDInst <(outs RC:$dst),
377 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$u2),
378 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
379 ") ")#"$dst = "#mnemonic#"($src2+$src3<<#$u2)",
380 [], "", V4LDST_tc_ld_SLOT01>, AddrModeRel {
387 let isPredicatedFalse = isNot;
388 let isPredicatedNew = isPredNew;
392 let Inst{27-26} = 0b00;
393 let Inst{25} = isPredNew;
394 let Inst{24} = isNot;
395 let Inst{23-21} = MajOp;
396 let Inst{20-16} = src2;
397 let Inst{12-8} = src3;
398 let Inst{13} = u2{1};
400 let Inst{6-5} = src1;
404 //===----------------------------------------------------------------------===//
405 // multiclass for load instructions with base + register offset
407 //===----------------------------------------------------------------------===//
408 let hasSideEffects = 0, addrMode = BaseRegOffset in
409 multiclass ld_idxd_shl <string mnemonic, string CextOp, RegisterClass RC,
411 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed_shl,
412 InputType = "reg" in {
413 let isPredicable = 1 in
414 def L4_#NAME#_rr : T_load_rr <mnemonic, RC, MajOp>;
417 def L4_p#NAME#t_rr : T_pload_rr <mnemonic, RC, MajOp, 0, 0>;
418 def L4_p#NAME#f_rr : T_pload_rr <mnemonic, RC, MajOp, 1, 0>;
421 def L4_p#NAME#tnew_rr : T_pload_rr <mnemonic, RC, MajOp, 0, 1>;
422 def L4_p#NAME#fnew_rr : T_pload_rr <mnemonic, RC, MajOp, 1, 1>;
426 let hasNewValue = 1, accessSize = ByteAccess, isCodeGenOnly = 0 in {
427 defm loadrb : ld_idxd_shl<"memb", "LDrib", IntRegs, 0b000>;
428 defm loadrub : ld_idxd_shl<"memub", "LDriub", IntRegs, 0b001>;
431 let hasNewValue = 1, accessSize = HalfWordAccess, isCodeGenOnly = 0 in {
432 defm loadrh : ld_idxd_shl<"memh", "LDrih", IntRegs, 0b010>;
433 defm loadruh : ld_idxd_shl<"memuh", "LDriuh", IntRegs, 0b011>;
436 let hasNewValue = 1, accessSize = WordAccess, isCodeGenOnly = 0 in
437 defm loadri : ld_idxd_shl<"memw", "LDriw", IntRegs, 0b100>;
439 let accessSize = DoubleWordAccess, isCodeGenOnly = 0 in
440 defm loadrd : ld_idxd_shl<"memd", "LDrid", DoubleRegs, 0b110>;
442 // 'def pats' for load instructions with base + register offset and non-zero
443 // immediate value. Immediate value is used to left-shift the second
445 let AddedComplexity = 40 in {
446 def : Pat <(i32 (sextloadi8 (add IntRegs:$src1,
447 (shl IntRegs:$src2, u2ImmPred:$offset)))),
448 (L4_loadrb_rr IntRegs:$src1,
449 IntRegs:$src2, u2ImmPred:$offset)>,
452 def : Pat <(i32 (zextloadi8 (add IntRegs:$src1,
453 (shl IntRegs:$src2, u2ImmPred:$offset)))),
454 (L4_loadrub_rr IntRegs:$src1,
455 IntRegs:$src2, u2ImmPred:$offset)>,
458 def : Pat <(i32 (extloadi8 (add IntRegs:$src1,
459 (shl IntRegs:$src2, u2ImmPred:$offset)))),
460 (L4_loadrub_rr IntRegs:$src1,
461 IntRegs:$src2, u2ImmPred:$offset)>,
464 def : Pat <(i32 (sextloadi16 (add IntRegs:$src1,
465 (shl IntRegs:$src2, u2ImmPred:$offset)))),
466 (L4_loadrh_rr IntRegs:$src1,
467 IntRegs:$src2, u2ImmPred:$offset)>,
470 def : Pat <(i32 (zextloadi16 (add IntRegs:$src1,
471 (shl IntRegs:$src2, u2ImmPred:$offset)))),
472 (L4_loadruh_rr IntRegs:$src1,
473 IntRegs:$src2, u2ImmPred:$offset)>,
476 def : Pat <(i32 (extloadi16 (add IntRegs:$src1,
477 (shl IntRegs:$src2, u2ImmPred:$offset)))),
478 (L4_loadruh_rr IntRegs:$src1,
479 IntRegs:$src2, u2ImmPred:$offset)>,
482 def : Pat <(i32 (load (add IntRegs:$src1,
483 (shl IntRegs:$src2, u2ImmPred:$offset)))),
484 (L4_loadri_rr IntRegs:$src1,
485 IntRegs:$src2, u2ImmPred:$offset)>,
488 def : Pat <(i64 (load (add IntRegs:$src1,
489 (shl IntRegs:$src2, u2ImmPred:$offset)))),
490 (L4_loadrd_rr IntRegs:$src1,
491 IntRegs:$src2, u2ImmPred:$offset)>,
496 // 'def pats' for load instruction base + register offset and
497 // zero immediate value.
498 let AddedComplexity = 10 in {
499 def : Pat <(i64 (load (add IntRegs:$src1, IntRegs:$src2))),
500 (L4_loadrd_rr IntRegs:$src1, IntRegs:$src2, 0)>,
503 def : Pat <(i32 (sextloadi8 (add IntRegs:$src1, IntRegs:$src2))),
504 (L4_loadrb_rr IntRegs:$src1, IntRegs:$src2, 0)>,
507 def : Pat <(i32 (zextloadi8 (add IntRegs:$src1, IntRegs:$src2))),
508 (L4_loadrub_rr IntRegs:$src1, IntRegs:$src2, 0)>,
511 def : Pat <(i32 (extloadi8 (add IntRegs:$src1, IntRegs:$src2))),
512 (L4_loadrub_rr IntRegs:$src1, IntRegs:$src2, 0)>,
515 def : Pat <(i32 (sextloadi16 (add IntRegs:$src1, IntRegs:$src2))),
516 (L4_loadrh_rr IntRegs:$src1, IntRegs:$src2, 0)>,
519 def : Pat <(i32 (zextloadi16 (add IntRegs:$src1, IntRegs:$src2))),
520 (L4_loadruh_rr IntRegs:$src1, IntRegs:$src2, 0)>,
523 def : Pat <(i32 (extloadi16 (add IntRegs:$src1, IntRegs:$src2))),
524 (L4_loadruh_rr IntRegs:$src1, IntRegs:$src2, 0)>,
527 def : Pat <(i32 (load (add IntRegs:$src1, IntRegs:$src2))),
528 (L4_loadri_rr IntRegs:$src1, IntRegs:$src2, 0)>,
533 def : Pat <(i64 (zext (i1 PredRegs:$src1))),
534 (i64 (A4_combineir 0, (C2_muxii (i1 PredRegs:$src1), 1, 0)))>,
538 def : Pat <(i64 (zext (i32 IntRegs:$src1))),
539 (i64 (A4_combineir 0, (i32 IntRegs:$src1)))>,
542 def: Pat <(i64 (zextloadi8 ADDRriS11_0:$src1)),
543 (i64 (A4_combineir 0, (L2_loadrub_io AddrFI:$src1, 0)))>,
546 let AddedComplexity = 20 in
547 def: Pat <(i64 (zextloadi8 (add (i32 IntRegs:$src1),
548 s11_0ExtPred:$offset))),
549 (i64 (A4_combineir 0, (L2_loadrub_io IntRegs:$src1,
550 s11_0ExtPred:$offset)))>,
554 def: Pat <(i64 (zextloadi1 ADDRriS11_0:$src1)),
555 (i64 (A4_combineir 0, (L2_loadrub_io AddrFI:$src1, 0)))>,
558 let AddedComplexity = 20 in
559 def: Pat <(i64 (zextloadi1 (add (i32 IntRegs:$src1),
560 s11_0ExtPred:$offset))),
561 (i64 (A4_combineir 0, (L2_loadrub_io IntRegs:$src1,
562 s11_0ExtPred:$offset)))>,
566 def: Pat <(i64 (zextloadi16 ADDRriS11_1:$src1)),
567 (i64 (A4_combineir 0, (L2_loadruh_io AddrFI:$src1, 0)))>,
570 let AddedComplexity = 20 in
571 def: Pat <(i64 (zextloadi16 (add (i32 IntRegs:$src1),
572 s11_1ExtPred:$offset))),
573 (i64 (A4_combineir 0, (L2_loadruh_io IntRegs:$src1,
574 s11_1ExtPred:$offset)))>,
578 def: Pat <(i64 (extloadi16 ADDRriS11_2:$src1)),
579 (i64 (A4_combineir 0, (L2_loadrh_io AddrFI:$src1, 0)))>,
582 let AddedComplexity = 20 in
583 def: Pat <(i64 (extloadi16 (add (i32 IntRegs:$src1),
584 s11_1ExtPred:$offset))),
585 (i64 (A4_combineir 0, (L2_loadrh_io IntRegs:$src1,
586 s11_1ExtPred:$offset)))>,
590 def: Pat <(i64 (zextloadi32 ADDRriS11_2:$src1)),
591 (i64 (A4_combineir 0, (L2_loadri_io AddrFI:$src1, 0)))>,
594 let AddedComplexity = 100 in
595 def: Pat <(i64 (zextloadi32 (i32 (add IntRegs:$src1, s11_2ExtPred:$offset)))),
596 (i64 (A4_combineir 0, (L2_loadri_io IntRegs:$src1,
597 s11_2ExtPred:$offset)))>,
601 def: Pat <(i64 (extloadi32 ADDRriS11_2:$src1)),
602 (i64 (A4_combineir 0, (L2_loadri_io AddrFI:$src1, 0)))>,
605 let AddedComplexity = 100 in
606 def: Pat <(i64 (extloadi32 (i32 (add IntRegs:$src1, s11_2ExtPred:$offset)))),
607 (i64 (A4_combineir 0, (L2_loadri_io IntRegs:$src1,
608 s11_2ExtPred:$offset)))>,
613 //===----------------------------------------------------------------------===//
615 //===----------------------------------------------------------------------===//
617 //===----------------------------------------------------------------------===//
619 //===----------------------------------------------------------------------===//
621 //===----------------------------------------------------------------------===//
622 // Template class for store instructions with Absolute set addressing mode.
623 //===----------------------------------------------------------------------===//
624 let isExtended = 1, opExtendable = 2, validSubTargets = HasV4SubT,
625 addrMode = AbsoluteSet in
626 class T_ST_abs_set<string mnemonic, RegisterClass RC>:
627 STInst2<(outs IntRegs:$dst1),
628 (ins RC:$src1, u0AlwaysExt:$src2),
629 mnemonic#"($dst1=##$src2) = $src1",
633 def STrid_abs_set_V4 : T_ST_abs_set <"memd", DoubleRegs>;
634 def STrib_abs_set_V4 : T_ST_abs_set <"memb", IntRegs>;
635 def STrih_abs_set_V4 : T_ST_abs_set <"memh", IntRegs>;
636 def STriw_abs_set_V4 : T_ST_abs_set <"memw", IntRegs>;
638 //===----------------------------------------------------------------------===//
639 // Template classes for the non-predicated store instructions with
640 // base + register offset addressing mode
641 //===----------------------------------------------------------------------===//
642 let isPredicable = 1 in
643 class T_store_rr <string mnemonic, RegisterClass RC, bits<3> MajOp, bit isH>
644 : STInst < (outs ), (ins IntRegs:$Rs, IntRegs:$Ru, u2Imm:$u2, RC:$Rt),
645 mnemonic#"($Rs + $Ru<<#$u2) = $Rt"#!if(isH, ".h",""),
646 [],"",V4LDST_tc_st_SLOT01>, ImmRegShl, AddrModeRel {
655 let Inst{27-24} = 0b1011;
656 let Inst{23-21} = MajOp;
657 let Inst{20-16} = Rs;
659 let Inst{13} = u2{1};
664 //===----------------------------------------------------------------------===//
665 // Template classes for the predicated store instructions with
666 // base + register offset addressing mode
667 //===----------------------------------------------------------------------===//
668 let isPredicated = 1 in
669 class T_pstore_rr <string mnemonic, RegisterClass RC, bits<3> MajOp,
670 bit isNot, bit isPredNew, bit isH>
672 (ins PredRegs:$Pv, IntRegs:$Rs, IntRegs:$Ru, u2Imm:$u2, RC:$Rt),
674 !if(isNot, "if (!$Pv", "if ($Pv")#!if(isPredNew, ".new) ",
675 ") ")#mnemonic#"($Rs+$Ru<<#$u2) = $Rt"#!if(isH, ".h",""),
676 [], "", V4LDST_tc_st_SLOT01> , AddrModeRel{
683 let isPredicatedFalse = isNot;
684 let isPredicatedNew = isPredNew;
688 let Inst{27-26} = 0b01;
689 let Inst{25} = isPredNew;
690 let Inst{24} = isNot;
691 let Inst{23-21} = MajOp;
692 let Inst{20-16} = Rs;
694 let Inst{13} = u2{1};
700 //===----------------------------------------------------------------------===//
701 // Template classes for the new-value store instructions with
702 // base + register offset addressing mode
703 //===----------------------------------------------------------------------===//
704 let isPredicable = 1, isNewValue = 1, opNewValue = 3 in
705 class T_store_new_rr <string mnemonic, bits<2> MajOp> :
706 NVInst < (outs ), (ins IntRegs:$Rs, IntRegs:$Ru, u2Imm:$u2, IntRegs:$Nt),
707 mnemonic#"($Rs + $Ru<<#$u2) = $Nt.new",
708 [],"",V4LDST_tc_st_SLOT0>, ImmRegShl, AddrModeRel {
717 let Inst{27-21} = 0b1011101;
718 let Inst{20-16} = Rs;
720 let Inst{13} = u2{1};
722 let Inst{4-3} = MajOp;
726 //===----------------------------------------------------------------------===//
727 // Template classes for the predicated new-value store instructions with
728 // base + register offset addressing mode
729 //===----------------------------------------------------------------------===//
730 let isPredicated = 1, isNewValue = 1, opNewValue = 4 in
731 class T_pstore_new_rr <string mnemonic, bits<2> MajOp, bit isNot, bit isPredNew>
733 (ins PredRegs:$Pv, IntRegs:$Rs, IntRegs:$Ru, u2Imm:$u2, IntRegs:$Nt),
734 !if(isNot, "if (!$Pv", "if ($Pv")#!if(isPredNew, ".new) ",
735 ") ")#mnemonic#"($Rs+$Ru<<#$u2) = $Nt.new",
736 [], "", V4LDST_tc_st_SLOT0>, AddrModeRel {
743 let isPredicatedFalse = isNot;
744 let isPredicatedNew = isPredNew;
747 let Inst{27-26} = 0b01;
748 let Inst{25} = isPredNew;
749 let Inst{24} = isNot;
750 let Inst{23-21} = 0b101;
751 let Inst{20-16} = Rs;
753 let Inst{13} = u2{1};
756 let Inst{4-3} = MajOp;
760 //===----------------------------------------------------------------------===//
761 // multiclass for store instructions with base + register offset addressing
763 //===----------------------------------------------------------------------===//
764 let isNVStorable = 1 in
765 multiclass ST_Idxd_shl<string mnemonic, string CextOp, RegisterClass RC,
766 bits<3> MajOp, bit isH = 0> {
767 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed_shl in {
768 def S4_#NAME#_rr : T_store_rr <mnemonic, RC, MajOp, isH>;
771 def S4_p#NAME#t_rr : T_pstore_rr <mnemonic, RC, MajOp, 0, 0, isH>;
772 def S4_p#NAME#f_rr : T_pstore_rr <mnemonic, RC, MajOp, 1, 0, isH>;
775 def S4_p#NAME#tnew_rr : T_pstore_rr <mnemonic, RC, MajOp, 0, 1, isH>;
776 def S4_p#NAME#fnew_rr : T_pstore_rr <mnemonic, RC, MajOp, 1, 1, isH>;
780 //===----------------------------------------------------------------------===//
781 // multiclass for new-value store instructions with base + register offset
783 //===----------------------------------------------------------------------===//
784 let mayStore = 1, isNVStore = 1 in
785 multiclass ST_Idxd_shl_nv <string mnemonic, string CextOp, RegisterClass RC,
787 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed_shl in {
788 def S4_#NAME#new_rr : T_store_new_rr<mnemonic, MajOp>;
791 def S4_p#NAME#newt_rr : T_pstore_new_rr <mnemonic, MajOp, 0, 0>;
792 def S4_p#NAME#newf_rr : T_pstore_new_rr <mnemonic, MajOp, 1, 0>;
795 def S4_p#NAME#newtnew_rr : T_pstore_new_rr <mnemonic, MajOp, 0, 1>;
796 def S4_p#NAME#newfnew_rr : T_pstore_new_rr <mnemonic, MajOp, 1, 1>;
800 let addrMode = BaseRegOffset, InputType = "reg", hasSideEffects = 0,
801 isCodeGenOnly = 0 in {
802 let accessSize = ByteAccess in
803 defm storerb: ST_Idxd_shl<"memb", "STrib", IntRegs, 0b000>,
804 ST_Idxd_shl_nv<"memb", "STrib", IntRegs, 0b00>;
806 let accessSize = HalfWordAccess in
807 defm storerh: ST_Idxd_shl<"memh", "STrih", IntRegs, 0b010>,
808 ST_Idxd_shl_nv<"memh", "STrih", IntRegs, 0b01>;
810 let accessSize = WordAccess in
811 defm storeri: ST_Idxd_shl<"memw", "STriw", IntRegs, 0b100>,
812 ST_Idxd_shl_nv<"memw", "STriw", IntRegs, 0b10>;
814 let isNVStorable = 0, accessSize = DoubleWordAccess in
815 defm storerd: ST_Idxd_shl<"memd", "STrid", DoubleRegs, 0b110>;
817 let isNVStorable = 0, accessSize = HalfWordAccess in
818 defm storerf: ST_Idxd_shl<"memh", "STrif", IntRegs, 0b011, 1>;
821 let Predicates = [HasV4T], AddedComplexity = 10 in {
822 def : Pat<(truncstorei8 (i32 IntRegs:$src4),
823 (add IntRegs:$src1, (shl IntRegs:$src2,
825 (S4_storerb_rr IntRegs:$src1, IntRegs:$src2,
826 u2ImmPred:$src3, IntRegs:$src4)>;
828 def : Pat<(truncstorei16 (i32 IntRegs:$src4),
829 (add IntRegs:$src1, (shl IntRegs:$src2,
831 (S4_storerh_rr IntRegs:$src1, IntRegs:$src2,
832 u2ImmPred:$src3, IntRegs:$src4)>;
834 def : Pat<(store (i32 IntRegs:$src4),
835 (add IntRegs:$src1, (shl IntRegs:$src2, u2ImmPred:$src3))),
836 (S4_storeri_rr IntRegs:$src1, IntRegs:$src2,
837 u2ImmPred:$src3, IntRegs:$src4)>;
839 def : Pat<(store (i64 DoubleRegs:$src4),
840 (add IntRegs:$src1, (shl IntRegs:$src2, u2ImmPred:$src3))),
841 (S4_storerd_rr IntRegs:$src1, IntRegs:$src2,
842 u2ImmPred:$src3, DoubleRegs:$src4)>;
845 let isExtended = 1, opExtendable = 2 in
846 class T_ST_LongOff <string mnemonic, PatFrag stOp, RegisterClass RC, ValueType VT> :
848 (ins IntRegs:$src1, u2Imm:$src2, u0AlwaysExt:$src3, RC:$src4),
849 mnemonic#"($src1<<#$src2+##$src3) = $src4",
850 [(stOp (VT RC:$src4),
851 (add (shl (i32 IntRegs:$src1), u2ImmPred:$src2),
852 u0AlwaysExtPred:$src3))]>,
855 let isExtended = 1, opExtendable = 2, mayStore = 1, isNVStore = 1 in
856 class T_ST_LongOff_nv <string mnemonic> :
858 (ins IntRegs:$src1, u2Imm:$src2, u0AlwaysExt:$src3, IntRegs:$src4),
859 mnemonic#"($src1<<#$src2+##$src3) = $src4.new",
863 multiclass ST_LongOff <string mnemonic, string BaseOp, PatFrag stOp> {
864 let BaseOpcode = BaseOp#"_shl" in {
865 let isNVStorable = 1 in
866 def NAME#_V4 : T_ST_LongOff<mnemonic, stOp, IntRegs, i32>;
868 def NAME#_nv_V4 : T_ST_LongOff_nv<mnemonic>;
872 let AddedComplexity = 10, validSubTargets = HasV4SubT in {
873 def STrid_shl_V4 : T_ST_LongOff<"memd", store, DoubleRegs, i64>;
874 defm STrib_shl : ST_LongOff <"memb", "STrib", truncstorei8>, NewValueRel;
875 defm STrih_shl : ST_LongOff <"memh", "Strih", truncstorei16>, NewValueRel;
876 defm STriw_shl : ST_LongOff <"memw", "STriw", store>, NewValueRel;
879 let AddedComplexity = 40 in
880 multiclass T_ST_LOff_Pats <InstHexagon I, RegisterClass RC, ValueType VT,
882 def : Pat<(stOp (VT RC:$src4),
883 (add (shl IntRegs:$src1, u2ImmPred:$src2),
884 (NumUsesBelowThresCONST32 tglobaladdr:$src3))),
885 (I IntRegs:$src1, u2ImmPred:$src2, tglobaladdr:$src3, RC:$src4)>;
887 def : Pat<(stOp (VT RC:$src4),
889 (NumUsesBelowThresCONST32 tglobaladdr:$src3))),
890 (I IntRegs:$src1, 0, tglobaladdr:$src3, RC:$src4)>;
893 defm : T_ST_LOff_Pats<STrid_shl_V4, DoubleRegs, i64, store>;
894 defm : T_ST_LOff_Pats<STriw_shl_V4, IntRegs, i32, store>;
895 defm : T_ST_LOff_Pats<STrib_shl_V4, IntRegs, i32, truncstorei8>;
896 defm : T_ST_LOff_Pats<STrih_shl_V4, IntRegs, i32, truncstorei16>;
898 // memd(Rx++#s4:3)=Rtt
899 // memd(Rx++#s4:3:circ(Mu))=Rtt
900 // memd(Rx++I:circ(Mu))=Rtt
902 // memd(Rx++Mu:brev)=Rtt
903 // memd(gp+#u16:3)=Rtt
905 // Store doubleword conditionally.
906 // if ([!]Pv[.new]) memd(#u6)=Rtt
907 // TODO: needs to be implemented.
909 //===----------------------------------------------------------------------===//
911 //===----------------------------------------------------------------------===//
912 let isPredicable = 1, isExtendable = 1, isExtentSigned = 1, opExtentBits = 8,
914 class T_StoreImm <string mnemonic, Operand OffsetOp, bits<2> MajOp >
915 : STInst <(outs ), (ins IntRegs:$Rs, OffsetOp:$offset, s8Ext:$S8),
916 mnemonic#"($Rs+#$offset)=#$S8",
917 [], "", V4LDST_tc_st_SLOT01>,
918 ImmRegRel, PredNewRel {
924 string OffsetOpStr = !cast<string>(OffsetOp);
925 let offsetBits = !if (!eq(OffsetOpStr, "u6_2Imm"), offset{7-2},
926 !if (!eq(OffsetOpStr, "u6_1Imm"), offset{6-1},
927 /* u6_0Imm */ offset{5-0}));
931 let Inst{27-25} = 0b110;
932 let Inst{22-21} = MajOp;
933 let Inst{20-16} = Rs;
934 let Inst{12-7} = offsetBits;
935 let Inst{13} = S8{7};
936 let Inst{6-0} = S8{6-0};
939 let isPredicated = 1, isExtendable = 1, isExtentSigned = 1, opExtentBits = 6,
941 class T_StoreImm_pred <string mnemonic, Operand OffsetOp, bits<2> MajOp,
942 bit isPredNot, bit isPredNew >
944 (ins PredRegs:$Pv, IntRegs:$Rs, OffsetOp:$offset, s6Ext:$S6),
945 !if(isPredNot, "if (!$Pv", "if ($Pv")#!if(isPredNew, ".new) ",
946 ") ")#mnemonic#"($Rs+#$offset)=#$S6",
947 [], "", V4LDST_tc_st_SLOT01>,
948 ImmRegRel, PredNewRel {
955 string OffsetOpStr = !cast<string>(OffsetOp);
956 let offsetBits = !if (!eq(OffsetOpStr, "u6_2Imm"), offset{7-2},
957 !if (!eq(OffsetOpStr, "u6_1Imm"), offset{6-1},
958 /* u6_0Imm */ offset{5-0}));
959 let isPredicatedNew = isPredNew;
960 let isPredicatedFalse = isPredNot;
964 let Inst{27-25} = 0b100;
965 let Inst{24} = isPredNew;
966 let Inst{23} = isPredNot;
967 let Inst{22-21} = MajOp;
968 let Inst{20-16} = Rs;
969 let Inst{13} = S6{5};
970 let Inst{12-7} = offsetBits;
972 let Inst{4-0} = S6{4-0};
976 //===----------------------------------------------------------------------===//
977 // multiclass for store instructions with base + immediate offset
978 // addressing mode and immediate stored value.
979 // mem[bhw](Rx++#s4:3)=#s8
980 // if ([!]Pv[.new]) mem[bhw](Rx++#s4:3)=#s6
981 //===----------------------------------------------------------------------===//
983 multiclass ST_Imm_Pred <string mnemonic, Operand OffsetOp, bits<2> MajOp,
985 def _io : T_StoreImm_pred <mnemonic, OffsetOp, MajOp, PredNot, 0>;
987 def new_io : T_StoreImm_pred <mnemonic, OffsetOp, MajOp, PredNot, 1>;
990 multiclass ST_Imm <string mnemonic, string CextOp, Operand OffsetOp,
992 let CextOpcode = CextOp, BaseOpcode = CextOp#_imm in {
993 def _io : T_StoreImm <mnemonic, OffsetOp, MajOp>;
995 defm t : ST_Imm_Pred <mnemonic, OffsetOp, MajOp, 0>;
996 defm f : ST_Imm_Pred <mnemonic, OffsetOp, MajOp, 1>;
1000 let hasSideEffects = 0, validSubTargets = HasV4SubT, addrMode = BaseImmOffset,
1001 InputType = "imm", isCodeGenOnly = 0 in {
1002 let accessSize = ByteAccess in
1003 defm S4_storeirb : ST_Imm<"memb", "STrib", u6_0Imm, 0b00>;
1005 let accessSize = HalfWordAccess in
1006 defm S4_storeirh : ST_Imm<"memh", "STrih", u6_1Imm, 0b01>;
1008 let accessSize = WordAccess in
1009 defm S4_storeiri : ST_Imm<"memw", "STriw", u6_2Imm, 0b10>;
1012 let Predicates = [HasV4T], AddedComplexity = 10 in {
1013 def: Pat<(truncstorei8 s8ExtPred:$src3, (add IntRegs:$src1, u6_0ImmPred:$src2)),
1014 (S4_storeirb_io IntRegs:$src1, u6_0ImmPred:$src2, s8ExtPred:$src3)>;
1016 def: Pat<(truncstorei16 s8ExtPred:$src3, (add IntRegs:$src1,
1017 u6_1ImmPred:$src2)),
1018 (S4_storeirh_io IntRegs:$src1, u6_1ImmPred:$src2, s8ExtPred:$src3)>;
1020 def: Pat<(store s8ExtPred:$src3, (add IntRegs:$src1, u6_2ImmPred:$src2)),
1021 (S4_storeiri_io IntRegs:$src1, u6_2ImmPred:$src2, s8ExtPred:$src3)>;
1024 let AddedComplexity = 6 in
1025 def : Pat <(truncstorei8 s8ExtPred:$src2, (i32 IntRegs:$src1)),
1026 (S4_storeirb_io IntRegs:$src1, 0, s8ExtPred:$src2)>,
1029 // memb(Rx++#s4:0:circ(Mu))=Rt
1030 // memb(Rx++I:circ(Mu))=Rt
1032 // memb(Rx++Mu:brev)=Rt
1033 // memb(gp+#u16:0)=Rt
1037 // TODO: needs to be implemented
1038 // memh(Re=#U6)=Rt.H
1039 // memh(Rs+#s11:1)=Rt.H
1040 let AddedComplexity = 6 in
1041 def : Pat <(truncstorei16 s8ExtPred:$src2, (i32 IntRegs:$src1)),
1042 (S4_storeirh_io IntRegs:$src1, 0, s8ExtPred:$src2)>,
1045 // memh(Rs+Ru<<#u2)=Rt.H
1046 // TODO: needs to be implemented.
1048 // memh(Ru<<#u2+#U6)=Rt.H
1049 // memh(Rx++#s4:1:circ(Mu))=Rt.H
1050 // memh(Rx++#s4:1:circ(Mu))=Rt
1051 // memh(Rx++I:circ(Mu))=Rt.H
1052 // memh(Rx++I:circ(Mu))=Rt
1053 // memh(Rx++Mu)=Rt.H
1055 // memh(Rx++Mu:brev)=Rt.H
1056 // memh(Rx++Mu:brev)=Rt
1057 // memh(gp+#u16:1)=Rt
1058 // if ([!]Pv[.new]) memh(#u6)=Rt.H
1059 // if ([!]Pv[.new]) memh(#u6)=Rt
1062 // if ([!]Pv[.new]) memh(Rs+#u6:1)=Rt.H
1063 // TODO: needs to be implemented.
1065 // if ([!]Pv[.new]) memh(Rx++#s4:1)=Rt.H
1066 // TODO: Needs to be implemented.
1070 // TODO: Needs to be implemented.
1073 let hasSideEffects = 0 in
1074 def STriw_pred_V4 : STInst2<(outs),
1075 (ins MEMri:$addr, PredRegs:$src1),
1076 "Error; should not emit",
1080 let AddedComplexity = 6 in
1081 def : Pat <(store s8ExtPred:$src2, (i32 IntRegs:$src1)),
1082 (S4_storeiri_io IntRegs:$src1, 0, s8ExtPred:$src2)>,
1085 // memw(Rx++#s4:2)=Rt
1086 // memw(Rx++#s4:2:circ(Mu))=Rt
1087 // memw(Rx++I:circ(Mu))=Rt
1089 // memw(Rx++Mu:brev)=Rt
1091 //===----------------------------------------------------------------------===
1093 //===----------------------------------------------------------------------===
1096 //===----------------------------------------------------------------------===//
1098 //===----------------------------------------------------------------------===//
1100 let opNewValue = 2, opExtendable = 1, isExtentSigned = 1, isPredicable = 1 in
1101 class T_store_io_nv <string mnemonic, RegisterClass RC,
1102 Operand ImmOp, bits<2>MajOp>
1103 : NVInst_V4 <(outs),
1104 (ins IntRegs:$src1, ImmOp:$src2, RC:$src3),
1105 mnemonic#"($src1+#$src2) = $src3.new",
1106 [],"",ST_tc_st_SLOT0> {
1108 bits<13> src2; // Actual address offset
1110 bits<11> offsetBits; // Represents offset encoding
1112 let opExtentBits = !if (!eq(mnemonic, "memb"), 11,
1113 !if (!eq(mnemonic, "memh"), 12,
1114 !if (!eq(mnemonic, "memw"), 13, 0)));
1116 let opExtentAlign = !if (!eq(mnemonic, "memb"), 0,
1117 !if (!eq(mnemonic, "memh"), 1,
1118 !if (!eq(mnemonic, "memw"), 2, 0)));
1120 let offsetBits = !if (!eq(mnemonic, "memb"), src2{10-0},
1121 !if (!eq(mnemonic, "memh"), src2{11-1},
1122 !if (!eq(mnemonic, "memw"), src2{12-2}, 0)));
1124 let IClass = 0b1010;
1127 let Inst{26-25} = offsetBits{10-9};
1128 let Inst{24-21} = 0b1101;
1129 let Inst{20-16} = src1;
1130 let Inst{13} = offsetBits{8};
1131 let Inst{12-11} = MajOp;
1132 let Inst{10-8} = src3;
1133 let Inst{7-0} = offsetBits{7-0};
1136 let opExtendable = 2, opNewValue = 3, isPredicated = 1 in
1137 class T_pstore_io_nv <string mnemonic, RegisterClass RC, Operand predImmOp,
1138 bits<2>MajOp, bit PredNot, bit isPredNew>
1139 : NVInst_V4 <(outs),
1140 (ins PredRegs:$src1, IntRegs:$src2, predImmOp:$src3, RC:$src4),
1141 !if(PredNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1142 ") ")#mnemonic#"($src2+#$src3) = $src4.new",
1143 [],"",V2LDST_tc_st_SLOT0> {
1148 bits<6> offsetBits; // Represents offset encoding
1150 let isPredicatedNew = isPredNew;
1151 let isPredicatedFalse = PredNot;
1152 let opExtentBits = !if (!eq(mnemonic, "memb"), 6,
1153 !if (!eq(mnemonic, "memh"), 7,
1154 !if (!eq(mnemonic, "memw"), 8, 0)));
1156 let opExtentAlign = !if (!eq(mnemonic, "memb"), 0,
1157 !if (!eq(mnemonic, "memh"), 1,
1158 !if (!eq(mnemonic, "memw"), 2, 0)));
1160 let offsetBits = !if (!eq(mnemonic, "memb"), src3{5-0},
1161 !if (!eq(mnemonic, "memh"), src3{6-1},
1162 !if (!eq(mnemonic, "memw"), src3{7-2}, 0)));
1164 let IClass = 0b0100;
1167 let Inst{26} = PredNot;
1168 let Inst{25} = isPredNew;
1169 let Inst{24-21} = 0b0101;
1170 let Inst{20-16} = src2;
1171 let Inst{13} = offsetBits{5};
1172 let Inst{12-11} = MajOp;
1173 let Inst{10-8} = src4;
1174 let Inst{7-3} = offsetBits{4-0};
1176 let Inst{1-0} = src1;
1179 // multiclass for new-value store instructions with base + immediate offset.
1181 let mayStore = 1, isNVStore = 1, isNewValue = 1, hasSideEffects = 0,
1183 multiclass ST_Idxd_nv<string mnemonic, string CextOp, RegisterClass RC,
1184 Operand ImmOp, Operand predImmOp, bits<2> MajOp> {
1186 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed in {
1187 def S2_#NAME#new_io : T_store_io_nv <mnemonic, RC, ImmOp, MajOp>;
1189 def S2_p#NAME#newt_io :T_pstore_io_nv <mnemonic, RC, predImmOp, MajOp, 0, 0>;
1190 def S2_p#NAME#newf_io :T_pstore_io_nv <mnemonic, RC, predImmOp, MajOp, 1, 0>;
1192 def S4_p#NAME#newtnew_io :T_pstore_io_nv <mnemonic, RC, predImmOp,
1194 def S4_p#NAME#newfnew_io :T_pstore_io_nv <mnemonic, RC, predImmOp,
1199 let addrMode = BaseImmOffset, InputType = "imm", isCodeGenOnly = 0 in {
1200 let accessSize = ByteAccess in
1201 defm storerb: ST_Idxd_nv<"memb", "STrib", IntRegs, s11_0Ext,
1202 u6_0Ext, 0b00>, AddrModeRel;
1204 let accessSize = HalfWordAccess, opExtentAlign = 1 in
1205 defm storerh: ST_Idxd_nv<"memh", "STrih", IntRegs, s11_1Ext,
1206 u6_1Ext, 0b01>, AddrModeRel;
1208 let accessSize = WordAccess, opExtentAlign = 2 in
1209 defm storeri: ST_Idxd_nv<"memw", "STriw", IntRegs, s11_2Ext,
1210 u6_2Ext, 0b10>, AddrModeRel;
1213 //===----------------------------------------------------------------------===//
1214 // Template class for non-predicated post increment .new stores
1215 // mem[bhwd](Rx++#s4:[0123])=Nt.new
1216 //===----------------------------------------------------------------------===//
1217 let isPredicable = 1, hasSideEffects = 0, validSubTargets = HasV4SubT,
1218 addrMode = PostInc, isNVStore = 1, isNewValue = 1, opNewValue = 3 in
1219 class T_StorePI_nv <string mnemonic, Operand ImmOp, bits<2> MajOp >
1220 : NVInstPI_V4 <(outs IntRegs:$_dst_),
1221 (ins IntRegs:$src1, ImmOp:$offset, IntRegs:$src2),
1222 mnemonic#"($src1++#$offset) = $src2.new",
1223 [], "$src1 = $_dst_">,
1230 string ImmOpStr = !cast<string>(ImmOp);
1231 let offsetBits = !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2},
1232 !if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1},
1233 /* s4_0Imm */ offset{3-0}));
1234 let IClass = 0b1010;
1236 let Inst{27-21} = 0b1011101;
1237 let Inst{20-16} = src1;
1239 let Inst{12-11} = MajOp;
1240 let Inst{10-8} = src2;
1242 let Inst{6-3} = offsetBits;
1246 //===----------------------------------------------------------------------===//
1247 // Template class for predicated post increment .new stores
1248 // if([!]Pv[.new]) mem[bhwd](Rx++#s4:[0123])=Nt.new
1249 //===----------------------------------------------------------------------===//
1250 let isPredicated = 1, hasSideEffects = 0, validSubTargets = HasV4SubT,
1251 addrMode = PostInc, isNVStore = 1, isNewValue = 1, opNewValue = 4 in
1252 class T_StorePI_nv_pred <string mnemonic, Operand ImmOp,
1253 bits<2> MajOp, bit isPredNot, bit isPredNew >
1254 : NVInstPI_V4 <(outs IntRegs:$_dst_),
1255 (ins PredRegs:$src1, IntRegs:$src2,
1256 ImmOp:$offset, IntRegs:$src3),
1257 !if(isPredNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1258 ") ")#mnemonic#"($src2++#$offset) = $src3.new",
1259 [], "$src2 = $_dst_">,
1267 string ImmOpStr = !cast<string>(ImmOp);
1268 let offsetBits = !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2},
1269 !if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1},
1270 /* s4_0Imm */ offset{3-0}));
1271 let isPredicatedNew = isPredNew;
1272 let isPredicatedFalse = isPredNot;
1274 let IClass = 0b1010;
1276 let Inst{27-21} = 0b1011101;
1277 let Inst{20-16} = src2;
1279 let Inst{12-11} = MajOp;
1280 let Inst{10-8} = src3;
1281 let Inst{7} = isPredNew;
1282 let Inst{6-3} = offsetBits;
1283 let Inst{2} = isPredNot;
1284 let Inst{1-0} = src1;
1287 multiclass ST_PostInc_Pred_nv<string mnemonic, Operand ImmOp,
1288 bits<2> MajOp, bit PredNot> {
1289 def _pi : T_StorePI_nv_pred <mnemonic, ImmOp, MajOp, PredNot, 0>;
1292 def new_pi : T_StorePI_nv_pred <mnemonic, ImmOp, MajOp, PredNot, 1>;
1295 multiclass ST_PostInc_nv<string mnemonic, string BaseOp, Operand ImmOp,
1297 let BaseOpcode = "POST_"#BaseOp in {
1298 def S2_#NAME#_pi : T_StorePI_nv <mnemonic, ImmOp, MajOp>;
1301 defm S2_p#NAME#t : ST_PostInc_Pred_nv <mnemonic, ImmOp, MajOp, 0>;
1302 defm S2_p#NAME#f : ST_PostInc_Pred_nv <mnemonic, ImmOp, MajOp, 1>;
1306 let accessSize = ByteAccess, isCodeGenOnly = 0 in
1307 defm storerbnew: ST_PostInc_nv <"memb", "STrib", s4_0Imm, 0b00>;
1309 let accessSize = HalfWordAccess, isCodeGenOnly = 0 in
1310 defm storerhnew: ST_PostInc_nv <"memh", "STrih", s4_1Imm, 0b01>;
1312 let accessSize = WordAccess, isCodeGenOnly = 0 in
1313 defm storerinew: ST_PostInc_nv <"memw", "STriw", s4_2Imm, 0b10>;
1315 // memb(Rx++#s4:0:circ(Mu))=Nt.new
1316 // memb(Rx++I:circ(Mu))=Nt.new
1317 // memb(Rx++Mu)=Nt.new
1318 // memb(Rx++Mu:brev)=Nt.new
1319 // memh(Rx++#s4:1:circ(Mu))=Nt.new
1320 // memh(Rx++I:circ(Mu))=Nt.new
1321 // memh(Rx++Mu)=Nt.new
1322 // memh(Rx++Mu:brev)=Nt.new
1324 // memw(Rx++#s4:2:circ(Mu))=Nt.new
1325 // memw(Rx++I:circ(Mu))=Nt.new
1326 // memw(Rx++Mu)=Nt.new
1327 // memw(Rx++Mu:brev)=Nt.new
1329 //===----------------------------------------------------------------------===//
1331 //===----------------------------------------------------------------------===//
1333 //===----------------------------------------------------------------------===//
1335 //===----------------------------------------------------------------------===//
1337 //===----------------------------------------------------------------------===//
1338 // multiclass/template class for the new-value compare jumps with the register
1340 //===----------------------------------------------------------------------===//
1342 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 11 in
1343 class NVJrr_template<string mnemonic, bits<3> majOp, bit NvOpNum,
1344 bit isNegCond, bit isTak>
1346 (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset),
1347 "if ("#!if(isNegCond, "!","")#mnemonic#
1348 "($src1"#!if(!eq(NvOpNum, 0),".new, ",", ")#
1349 "$src2"#!if(!eq(NvOpNum, 1),".new))","))")#" jump:"
1350 #!if(isTak, "t","nt")#" $offset",
1351 []>, Requires<[HasV4T]> {
1355 bits<3> Ns; // New-Value Operand
1356 bits<5> RegOp; // Non-New-Value Operand
1359 let isTaken = isTak;
1360 let isBrTaken = !if(isTaken, "true", "false");
1361 let isPredicatedFalse = isNegCond;
1363 let Ns = !if(!eq(NvOpNum, 0), src1{2-0}, src2{2-0});
1364 let RegOp = !if(!eq(NvOpNum, 0), src2, src1);
1366 let IClass = 0b0010;
1368 let Inst{25-23} = majOp;
1369 let Inst{22} = isNegCond;
1370 let Inst{18-16} = Ns;
1371 let Inst{13} = isTak;
1372 let Inst{12-8} = RegOp;
1373 let Inst{21-20} = offset{10-9};
1374 let Inst{7-1} = offset{8-2};
1378 multiclass NVJrr_cond<string mnemonic, bits<3> majOp, bit NvOpNum,
1380 // Branch not taken:
1381 def _nt_V4: NVJrr_template<mnemonic, majOp, NvOpNum, isNegCond, 0>;
1383 def _t_V4: NVJrr_template<mnemonic, majOp, NvOpNum, isNegCond, 1>;
1386 // NvOpNum = 0 -> First Operand is a new-value Register
1387 // NvOpNum = 1 -> Second Operand is a new-value Register
1389 multiclass NVJrr_base<string mnemonic, string BaseOp, bits<3> majOp,
1391 let BaseOpcode = BaseOp#_NVJ in {
1392 defm _t_Jumpnv : NVJrr_cond<mnemonic, majOp, NvOpNum, 0>; // True cond
1393 defm _f_Jumpnv : NVJrr_cond<mnemonic, majOp, NvOpNum, 1>; // False cond
1397 // if ([!]cmp.eq(Ns.new,Rt)) jump:[n]t #r9:2
1398 // if ([!]cmp.gt(Ns.new,Rt)) jump:[n]t #r9:2
1399 // if ([!]cmp.gtu(Ns.new,Rt)) jump:[n]t #r9:2
1400 // if ([!]cmp.gt(Rt,Ns.new)) jump:[n]t #r9:2
1401 // if ([!]cmp.gtu(Rt,Ns.new)) jump:[n]t #r9:2
1403 let isPredicated = 1, isBranch = 1, isNewValue = 1, isTerminator = 1,
1404 Defs = [PC], hasSideEffects = 0, validSubTargets = HasV4SubT in {
1405 defm CMPEQrr : NVJrr_base<"cmp.eq", "CMPEQ", 0b000, 0>, PredRel;
1406 defm CMPGTrr : NVJrr_base<"cmp.gt", "CMPGT", 0b001, 0>, PredRel;
1407 defm CMPGTUrr : NVJrr_base<"cmp.gtu", "CMPGTU", 0b010, 0>, PredRel;
1408 defm CMPLTrr : NVJrr_base<"cmp.gt", "CMPLT", 0b011, 1>, PredRel;
1409 defm CMPLTUrr : NVJrr_base<"cmp.gtu", "CMPLTU", 0b100, 1>, PredRel;
1412 //===----------------------------------------------------------------------===//
1413 // multiclass/template class for the new-value compare jumps instruction
1414 // with a register and an unsigned immediate (U5) operand.
1415 //===----------------------------------------------------------------------===//
1417 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 11 in
1418 class NVJri_template<string mnemonic, bits<3> majOp, bit isNegCond,
1421 (ins IntRegs:$src1, u5Imm:$src2, brtarget:$offset),
1422 "if ("#!if(isNegCond, "!","")#mnemonic#"($src1.new, #$src2)) jump:"
1423 #!if(isTak, "t","nt")#" $offset",
1424 []>, Requires<[HasV4T]> {
1426 let isTaken = isTak;
1427 let isPredicatedFalse = isNegCond;
1428 let isBrTaken = !if(isTaken, "true", "false");
1434 let IClass = 0b0010;
1436 let Inst{25-23} = majOp;
1437 let Inst{22} = isNegCond;
1438 let Inst{18-16} = src1;
1439 let Inst{13} = isTak;
1440 let Inst{12-8} = src2;
1441 let Inst{21-20} = offset{10-9};
1442 let Inst{7-1} = offset{8-2};
1445 multiclass NVJri_cond<string mnemonic, bits<3> majOp, bit isNegCond> {
1446 // Branch not taken:
1447 def _nt_V4: NVJri_template<mnemonic, majOp, isNegCond, 0>;
1449 def _t_V4: NVJri_template<mnemonic, majOp, isNegCond, 1>;
1452 multiclass NVJri_base<string mnemonic, string BaseOp, bits<3> majOp> {
1453 let BaseOpcode = BaseOp#_NVJri in {
1454 defm _t_Jumpnv : NVJri_cond<mnemonic, majOp, 0>; // True Cond
1455 defm _f_Jumpnv : NVJri_cond<mnemonic, majOp, 1>; // False cond
1459 // if ([!]cmp.eq(Ns.new,#U5)) jump:[n]t #r9:2
1460 // if ([!]cmp.gt(Ns.new,#U5)) jump:[n]t #r9:2
1461 // if ([!]cmp.gtu(Ns.new,#U5)) jump:[n]t #r9:2
1463 let isPredicated = 1, isBranch = 1, isNewValue = 1, isTerminator = 1,
1464 Defs = [PC], hasSideEffects = 0, validSubTargets = HasV4SubT in {
1465 defm CMPEQri : NVJri_base<"cmp.eq", "CMPEQ", 0b000>, PredRel;
1466 defm CMPGTri : NVJri_base<"cmp.gt", "CMPGT", 0b001>, PredRel;
1467 defm CMPGTUri : NVJri_base<"cmp.gtu", "CMPGTU", 0b010>, PredRel;
1470 //===----------------------------------------------------------------------===//
1471 // multiclass/template class for the new-value compare jumps instruction
1472 // with a register and an hardcoded 0/-1 immediate value.
1473 //===----------------------------------------------------------------------===//
1475 let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 11 in
1476 class NVJ_ConstImm_template<string mnemonic, bits<3> majOp, string ImmVal,
1477 bit isNegCond, bit isTak>
1479 (ins IntRegs:$src1, brtarget:$offset),
1480 "if ("#!if(isNegCond, "!","")#mnemonic
1481 #"($src1.new, #"#ImmVal#")) jump:"
1482 #!if(isTak, "t","nt")#" $offset",
1483 []>, Requires<[HasV4T]> {
1485 let isTaken = isTak;
1486 let isPredicatedFalse = isNegCond;
1487 let isBrTaken = !if(isTaken, "true", "false");
1491 let IClass = 0b0010;
1493 let Inst{25-23} = majOp;
1494 let Inst{22} = isNegCond;
1495 let Inst{18-16} = src1;
1496 let Inst{13} = isTak;
1497 let Inst{21-20} = offset{10-9};
1498 let Inst{7-1} = offset{8-2};
1501 multiclass NVJ_ConstImm_cond<string mnemonic, bits<3> majOp, string ImmVal,
1503 // Branch not taken:
1504 def _nt_V4: NVJ_ConstImm_template<mnemonic, majOp, ImmVal, isNegCond, 0>;
1506 def _t_V4: NVJ_ConstImm_template<mnemonic, majOp, ImmVal, isNegCond, 1>;
1509 multiclass NVJ_ConstImm_base<string mnemonic, string BaseOp, bits<3> majOp,
1511 let BaseOpcode = BaseOp#_NVJ_ConstImm in {
1512 defm _t_Jumpnv : NVJ_ConstImm_cond<mnemonic, majOp, ImmVal, 0>; // True cond
1513 defm _f_Jumpnv : NVJ_ConstImm_cond<mnemonic, majOp, ImmVal, 1>; // False Cond
1517 // if ([!]tstbit(Ns.new,#0)) jump:[n]t #r9:2
1518 // if ([!]cmp.eq(Ns.new,#-1)) jump:[n]t #r9:2
1519 // if ([!]cmp.gt(Ns.new,#-1)) jump:[n]t #r9:2
1521 let isPredicated = 1, isBranch = 1, isNewValue = 1, isTerminator=1,
1522 Defs = [PC], hasSideEffects = 0 in {
1523 defm TSTBIT0 : NVJ_ConstImm_base<"tstbit", "TSTBIT", 0b011, "0">, PredRel;
1524 defm CMPEQn1 : NVJ_ConstImm_base<"cmp.eq", "CMPEQ", 0b100, "-1">, PredRel;
1525 defm CMPGTn1 : NVJ_ConstImm_base<"cmp.gt", "CMPGT", 0b101, "-1">, PredRel;
1528 //===----------------------------------------------------------------------===//
1530 //===----------------------------------------------------------------------===//
1532 // Add and accumulate.
1533 // Rd=add(Rs,add(Ru,#s6))
1534 let isExtendable = 1, opExtendable = 3, isExtentSigned = 1, opExtentBits = 6,
1535 validSubTargets = HasV4SubT in
1536 def ADDr_ADDri_V4 : MInst<(outs IntRegs:$dst),
1537 (ins IntRegs:$src1, IntRegs:$src2, s6Ext:$src3),
1538 "$dst = add($src1, add($src2, #$src3))",
1539 [(set (i32 IntRegs:$dst),
1540 (add (i32 IntRegs:$src1), (add (i32 IntRegs:$src2),
1541 s6_16ExtPred:$src3)))]>,
1544 // Rd=add(Rs,sub(#s6,Ru))
1545 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 6,
1546 validSubTargets = HasV4SubT in
1547 def ADDr_SUBri_V4 : MInst<(outs IntRegs:$dst),
1548 (ins IntRegs:$src1, s6Ext:$src2, IntRegs:$src3),
1549 "$dst = add($src1, sub(#$src2, $src3))",
1550 [(set (i32 IntRegs:$dst),
1551 (add (i32 IntRegs:$src1), (sub s6_10ExtPred:$src2,
1552 (i32 IntRegs:$src3))))]>,
1555 // Generates the same instruction as ADDr_SUBri_V4 but matches different
1557 // Rd=add(Rs,sub(#s6,Ru))
1558 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 6,
1559 validSubTargets = HasV4SubT in
1560 def ADDri_SUBr_V4 : MInst<(outs IntRegs:$dst),
1561 (ins IntRegs:$src1, s6Ext:$src2, IntRegs:$src3),
1562 "$dst = add($src1, sub(#$src2, $src3))",
1563 [(set (i32 IntRegs:$dst),
1564 (sub (add (i32 IntRegs:$src1), s6_10ExtPred:$src2),
1565 (i32 IntRegs:$src3)))]>,
1569 // Add or subtract doublewords with carry.
1571 // Rdd=add(Rss,Rtt,Px):carry
1573 // Rdd=sub(Rss,Rtt,Px):carry
1576 // Logical doublewords.
1577 // Rdd=and(Rtt,~Rss)
1578 let validSubTargets = HasV4SubT in
1579 def ANDd_NOTd_V4 : MInst<(outs DoubleRegs:$dst),
1580 (ins DoubleRegs:$src1, DoubleRegs:$src2),
1581 "$dst = and($src1, ~$src2)",
1582 [(set (i64 DoubleRegs:$dst), (and (i64 DoubleRegs:$src1),
1583 (not (i64 DoubleRegs:$src2))))]>,
1587 let validSubTargets = HasV4SubT in
1588 def ORd_NOTd_V4 : MInst<(outs DoubleRegs:$dst),
1589 (ins DoubleRegs:$src1, DoubleRegs:$src2),
1590 "$dst = or($src1, ~$src2)",
1591 [(set (i64 DoubleRegs:$dst),
1592 (or (i64 DoubleRegs:$src1), (not (i64 DoubleRegs:$src2))))]>,
1596 // Logical-logical doublewords.
1597 // Rxx^=xor(Rss,Rtt)
1598 let validSubTargets = HasV4SubT in
1599 def XORd_XORdd: MInst_acc<(outs DoubleRegs:$dst),
1600 (ins DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),
1601 "$dst ^= xor($src2, $src3)",
1602 [(set (i64 DoubleRegs:$dst),
1603 (xor (i64 DoubleRegs:$src1), (xor (i64 DoubleRegs:$src2),
1604 (i64 DoubleRegs:$src3))))],
1609 // Logical-logical words.
1610 // Rx=or(Ru,and(Rx,#s10))
1611 let isExtendable = 1, opExtendable = 3, isExtentSigned = 1, opExtentBits = 10,
1612 validSubTargets = HasV4SubT in
1613 def ORr_ANDri_V4 : MInst_acc<(outs IntRegs:$dst),
1614 (ins IntRegs:$src1, IntRegs: $src2, s10Ext:$src3),
1615 "$dst = or($src1, and($src2, #$src3))",
1616 [(set (i32 IntRegs:$dst),
1617 (or (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
1618 s10ExtPred:$src3)))],
1622 // Rx[&|^]=and(Rs,Rt)
1624 let validSubTargets = HasV4SubT in
1625 def ANDr_ANDrr_V4 : MInst_acc<(outs IntRegs:$dst),
1626 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
1627 "$dst &= and($src2, $src3)",
1628 [(set (i32 IntRegs:$dst),
1629 (and (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
1630 (i32 IntRegs:$src3))))],
1635 let validSubTargets = HasV4SubT, CextOpcode = "ORr_ANDr", InputType = "reg" in
1636 def ORr_ANDrr_V4 : MInst_acc<(outs IntRegs:$dst),
1637 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
1638 "$dst |= and($src2, $src3)",
1639 [(set (i32 IntRegs:$dst),
1640 (or (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
1641 (i32 IntRegs:$src3))))],
1643 Requires<[HasV4T]>, ImmRegRel;
1646 let validSubTargets = HasV4SubT in
1647 def XORr_ANDrr_V4 : MInst_acc<(outs IntRegs:$dst),
1648 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
1649 "$dst ^= and($src2, $src3)",
1650 [(set (i32 IntRegs:$dst),
1651 (xor (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
1652 (i32 IntRegs:$src3))))],
1656 // Rx[&|^]=and(Rs,~Rt)
1658 let validSubTargets = HasV4SubT in
1659 def ANDr_ANDr_NOTr_V4 : MInst_acc<(outs IntRegs:$dst),
1660 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
1661 "$dst &= and($src2, ~$src3)",
1662 [(set (i32 IntRegs:$dst),
1663 (and (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
1664 (not (i32 IntRegs:$src3)))))],
1669 let validSubTargets = HasV4SubT in
1670 def ORr_ANDr_NOTr_V4 : MInst_acc<(outs IntRegs:$dst),
1671 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
1672 "$dst |= and($src2, ~$src3)",
1673 [(set (i32 IntRegs:$dst),
1674 (or (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
1675 (not (i32 IntRegs:$src3)))))],
1680 let validSubTargets = HasV4SubT in
1681 def XORr_ANDr_NOTr_V4 : MInst_acc<(outs IntRegs:$dst),
1682 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
1683 "$dst ^= and($src2, ~$src3)",
1684 [(set (i32 IntRegs:$dst),
1685 (xor (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
1686 (not (i32 IntRegs:$src3)))))],
1690 // Rx[&|^]=or(Rs,Rt)
1692 let validSubTargets = HasV4SubT in
1693 def ANDr_ORrr_V4 : MInst_acc<(outs IntRegs:$dst),
1694 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
1695 "$dst &= or($src2, $src3)",
1696 [(set (i32 IntRegs:$dst),
1697 (and (i32 IntRegs:$src1), (or (i32 IntRegs:$src2),
1698 (i32 IntRegs:$src3))))],
1703 let validSubTargets = HasV4SubT, CextOpcode = "ORr_ORr", InputType = "reg" in
1704 def ORr_ORrr_V4 : MInst_acc<(outs IntRegs:$dst),
1705 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
1706 "$dst |= or($src2, $src3)",
1707 [(set (i32 IntRegs:$dst),
1708 (or (i32 IntRegs:$src1), (or (i32 IntRegs:$src2),
1709 (i32 IntRegs:$src3))))],
1711 Requires<[HasV4T]>, ImmRegRel;
1714 let validSubTargets = HasV4SubT in
1715 def XORr_ORrr_V4 : MInst_acc<(outs IntRegs:$dst),
1716 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
1717 "$dst ^= or($src2, $src3)",
1718 [(set (i32 IntRegs:$dst),
1719 (xor (i32 IntRegs:$src1), (or (i32 IntRegs:$src2),
1720 (i32 IntRegs:$src3))))],
1724 // Rx[&|^]=xor(Rs,Rt)
1726 let validSubTargets = HasV4SubT in
1727 def ANDr_XORrr_V4 : MInst_acc<(outs IntRegs:$dst),
1728 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
1729 "$dst &= xor($src2, $src3)",
1730 [(set (i32 IntRegs:$dst),
1731 (and (i32 IntRegs:$src1), (xor (i32 IntRegs:$src2),
1732 (i32 IntRegs:$src3))))],
1737 let validSubTargets = HasV4SubT in
1738 def ORr_XORrr_V4 : MInst_acc<(outs IntRegs:$dst),
1739 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
1740 "$dst |= xor($src2, $src3)",
1741 [(set (i32 IntRegs:$dst),
1742 (and (i32 IntRegs:$src1), (xor (i32 IntRegs:$src2),
1743 (i32 IntRegs:$src3))))],
1748 let validSubTargets = HasV4SubT in
1749 def XORr_XORrr_V4 : MInst_acc<(outs IntRegs:$dst),
1750 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),
1751 "$dst ^= xor($src2, $src3)",
1752 [(set (i32 IntRegs:$dst),
1753 (and (i32 IntRegs:$src1), (xor (i32 IntRegs:$src2),
1754 (i32 IntRegs:$src3))))],
1759 let isExtendable = 1, opExtendable = 3, isExtentSigned = 1, opExtentBits = 10,
1760 validSubTargets = HasV4SubT, CextOpcode = "ORr_ANDr", InputType = "imm" in
1761 def ORr_ANDri2_V4 : MInst_acc<(outs IntRegs:$dst),
1762 (ins IntRegs:$src1, IntRegs: $src2, s10Ext:$src3),
1763 "$dst |= and($src2, #$src3)",
1764 [(set (i32 IntRegs:$dst),
1765 (or (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
1766 s10ExtPred:$src3)))],
1768 Requires<[HasV4T]>, ImmRegRel;
1771 let isExtendable = 1, opExtendable = 3, isExtentSigned = 1, opExtentBits = 10,
1772 validSubTargets = HasV4SubT, CextOpcode = "ORr_ORr", InputType = "imm" in
1773 def ORr_ORri_V4 : MInst_acc<(outs IntRegs:$dst),
1774 (ins IntRegs:$src1, IntRegs: $src2, s10Ext:$src3),
1775 "$dst |= or($src2, #$src3)",
1776 [(set (i32 IntRegs:$dst),
1777 (or (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),
1778 s10ExtPred:$src3)))],
1780 Requires<[HasV4T]>, ImmRegRel;
1784 // Rd=modwrap(Rs,Rt)
1786 // Rd=cround(Rs,#u5)
1788 // Rd=round(Rs,#u5)[:sat]
1789 // Rd=round(Rs,Rt)[:sat]
1790 // Vector reduce add unsigned halfwords
1791 // Rd=vraddh(Rss,Rtt)
1793 // Rdd=vaddb(Rss,Rtt)
1794 // Vector conditional negate
1795 // Rdd=vcnegh(Rss,Rt)
1796 // Rxx+=vrcnegh(Rss,Rt)
1797 // Vector maximum bytes
1798 // Rdd=vmaxb(Rtt,Rss)
1799 // Vector reduce maximum halfwords
1800 // Rxx=vrmaxh(Rss,Ru)
1801 // Rxx=vrmaxuh(Rss,Ru)
1802 // Vector reduce maximum words
1803 // Rxx=vrmaxuw(Rss,Ru)
1804 // Rxx=vrmaxw(Rss,Ru)
1805 // Vector minimum bytes
1806 // Rdd=vminb(Rtt,Rss)
1807 // Vector reduce minimum halfwords
1808 // Rxx=vrminh(Rss,Ru)
1809 // Rxx=vrminuh(Rss,Ru)
1810 // Vector reduce minimum words
1811 // Rxx=vrminuw(Rss,Ru)
1812 // Rxx=vrminw(Rss,Ru)
1813 // Vector subtract bytes
1814 // Rdd=vsubb(Rss,Rtt)
1816 //===----------------------------------------------------------------------===//
1818 //===----------------------------------------------------------------------===//
1821 //===----------------------------------------------------------------------===//
1823 //===----------------------------------------------------------------------===//
1825 // Multiply and user lower result.
1826 // Rd=add(#u6,mpyi(Rs,#U6))
1827 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 6,
1828 validSubTargets = HasV4SubT in
1829 def ADDi_MPYri_V4 : MInst<(outs IntRegs:$dst),
1830 (ins u6Ext:$src1, IntRegs:$src2, u6Imm:$src3),
1831 "$dst = add(#$src1, mpyi($src2, #$src3))",
1832 [(set (i32 IntRegs:$dst),
1833 (add (mul (i32 IntRegs:$src2), u6ImmPred:$src3),
1834 u6ExtPred:$src1))]>,
1837 // Rd=add(##,mpyi(Rs,#U6))
1838 def : Pat <(add (mul (i32 IntRegs:$src2), u6ImmPred:$src3),
1839 (HexagonCONST32 tglobaladdr:$src1)),
1840 (i32 (ADDi_MPYri_V4 tglobaladdr:$src1, IntRegs:$src2,
1843 // Rd=add(#u6,mpyi(Rs,Rt))
1844 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 6,
1845 validSubTargets = HasV4SubT, InputType = "imm", CextOpcode = "ADD_MPY" in
1846 def ADDi_MPYrr_V4 : MInst<(outs IntRegs:$dst),
1847 (ins u6Ext:$src1, IntRegs:$src2, IntRegs:$src3),
1848 "$dst = add(#$src1, mpyi($src2, $src3))",
1849 [(set (i32 IntRegs:$dst),
1850 (add (mul (i32 IntRegs:$src2), (i32 IntRegs:$src3)),
1851 u6ExtPred:$src1))]>,
1852 Requires<[HasV4T]>, ImmRegRel;
1854 // Rd=add(##,mpyi(Rs,Rt))
1855 def : Pat <(add (mul (i32 IntRegs:$src2), (i32 IntRegs:$src3)),
1856 (HexagonCONST32 tglobaladdr:$src1)),
1857 (i32 (ADDi_MPYrr_V4 tglobaladdr:$src1, IntRegs:$src2,
1860 // Rd=add(Ru,mpyi(#u6:2,Rs))
1861 let validSubTargets = HasV4SubT in
1862 def ADDr_MPYir_V4 : MInst<(outs IntRegs:$dst),
1863 (ins IntRegs:$src1, u6Imm:$src2, IntRegs:$src3),
1864 "$dst = add($src1, mpyi(#$src2, $src3))",
1865 [(set (i32 IntRegs:$dst),
1866 (add (i32 IntRegs:$src1), (mul (i32 IntRegs:$src3),
1867 u6_2ImmPred:$src2)))]>,
1870 // Rd=add(Ru,mpyi(Rs,#u6))
1871 let isExtendable = 1, opExtendable = 3, isExtentSigned = 0, opExtentBits = 6,
1872 validSubTargets = HasV4SubT, InputType = "imm", CextOpcode = "ADD_MPY" in
1873 def ADDr_MPYri_V4 : MInst<(outs IntRegs:$dst),
1874 (ins IntRegs:$src1, IntRegs:$src2, u6Ext:$src3),
1875 "$dst = add($src1, mpyi($src2, #$src3))",
1876 [(set (i32 IntRegs:$dst),
1877 (add (i32 IntRegs:$src1), (mul (i32 IntRegs:$src2),
1878 u6ExtPred:$src3)))]>,
1879 Requires<[HasV4T]>, ImmRegRel;
1881 // Rx=add(Ru,mpyi(Rx,Rs))
1882 let validSubTargets = HasV4SubT, InputType = "reg", CextOpcode = "ADD_MPY" in
1883 def ADDr_MPYrr_V4 : MInst_acc<(outs IntRegs:$dst),
1884 (ins IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
1885 "$dst = add($src1, mpyi($src2, $src3))",
1886 [(set (i32 IntRegs:$dst),
1887 (add (i32 IntRegs:$src1), (mul (i32 IntRegs:$src2),
1888 (i32 IntRegs:$src3))))],
1890 Requires<[HasV4T]>, ImmRegRel;
1893 // Polynomial multiply words
1895 // Rxx^=pmpyw(Rs,Rt)
1897 // Vector reduce multiply word by signed half (32x16)
1898 // Rdd=vrmpyweh(Rss,Rtt)[:<<1]
1899 // Rdd=vrmpywoh(Rss,Rtt)[:<<1]
1900 // Rxx+=vrmpyweh(Rss,Rtt)[:<<1]
1901 // Rxx+=vrmpywoh(Rss,Rtt)[:<<1]
1903 // Multiply and use upper result
1904 // Rd=mpy(Rs,Rt.H):<<1:sat
1905 // Rd=mpy(Rs,Rt.L):<<1:sat
1906 // Rd=mpy(Rs,Rt):<<1
1907 // Rd=mpy(Rs,Rt):<<1:sat
1909 // Rx+=mpy(Rs,Rt):<<1:sat
1910 // Rx-=mpy(Rs,Rt):<<1:sat
1912 // Vector multiply bytes
1913 // Rdd=vmpybsu(Rs,Rt)
1914 // Rdd=vmpybu(Rs,Rt)
1915 // Rxx+=vmpybsu(Rs,Rt)
1916 // Rxx+=vmpybu(Rs,Rt)
1918 // Vector polynomial multiply halfwords
1919 // Rdd=vpmpyh(Rs,Rt)
1920 // Rxx^=vpmpyh(Rs,Rt)
1922 //===----------------------------------------------------------------------===//
1924 //===----------------------------------------------------------------------===//
1927 //===----------------------------------------------------------------------===//
1929 //===----------------------------------------------------------------------===//
1931 // Shift by immediate and accumulate.
1932 // Rx=add(#u8,asl(Rx,#U5))
1933 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8,
1934 validSubTargets = HasV4SubT in
1935 def ADDi_ASLri_V4 : MInst_acc<(outs IntRegs:$dst),
1936 (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
1937 "$dst = add(#$src1, asl($src2, #$src3))",
1938 [(set (i32 IntRegs:$dst),
1939 (add (shl (i32 IntRegs:$src2), u5ImmPred:$src3),
1944 // Rx=add(#u8,lsr(Rx,#U5))
1945 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8,
1946 validSubTargets = HasV4SubT in
1947 def ADDi_LSRri_V4 : MInst_acc<(outs IntRegs:$dst),
1948 (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
1949 "$dst = add(#$src1, lsr($src2, #$src3))",
1950 [(set (i32 IntRegs:$dst),
1951 (add (srl (i32 IntRegs:$src2), u5ImmPred:$src3),
1956 // Rx=sub(#u8,asl(Rx,#U5))
1957 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8,
1958 validSubTargets = HasV4SubT in
1959 def SUBi_ASLri_V4 : MInst_acc<(outs IntRegs:$dst),
1960 (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
1961 "$dst = sub(#$src1, asl($src2, #$src3))",
1962 [(set (i32 IntRegs:$dst),
1963 (sub (shl (i32 IntRegs:$src2), u5ImmPred:$src3),
1968 // Rx=sub(#u8,lsr(Rx,#U5))
1969 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8,
1970 validSubTargets = HasV4SubT in
1971 def SUBi_LSRri_V4 : MInst_acc<(outs IntRegs:$dst),
1972 (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
1973 "$dst = sub(#$src1, lsr($src2, #$src3))",
1974 [(set (i32 IntRegs:$dst),
1975 (sub (srl (i32 IntRegs:$src2), u5ImmPred:$src3),
1981 //Shift by immediate and logical.
1982 //Rx=and(#u8,asl(Rx,#U5))
1983 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8,
1984 validSubTargets = HasV4SubT in
1985 def ANDi_ASLri_V4 : MInst_acc<(outs IntRegs:$dst),
1986 (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
1987 "$dst = and(#$src1, asl($src2, #$src3))",
1988 [(set (i32 IntRegs:$dst),
1989 (and (shl (i32 IntRegs:$src2), u5ImmPred:$src3),
1994 //Rx=and(#u8,lsr(Rx,#U5))
1995 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8,
1996 validSubTargets = HasV4SubT in
1997 def ANDi_LSRri_V4 : MInst_acc<(outs IntRegs:$dst),
1998 (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
1999 "$dst = and(#$src1, lsr($src2, #$src3))",
2000 [(set (i32 IntRegs:$dst),
2001 (and (srl (i32 IntRegs:$src2), u5ImmPred:$src3),
2006 //Rx=or(#u8,asl(Rx,#U5))
2007 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8,
2008 AddedComplexity = 30, validSubTargets = HasV4SubT in
2009 def ORi_ASLri_V4 : MInst_acc<(outs IntRegs:$dst),
2010 (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
2011 "$dst = or(#$src1, asl($src2, #$src3))",
2012 [(set (i32 IntRegs:$dst),
2013 (or (shl (i32 IntRegs:$src2), u5ImmPred:$src3),
2018 //Rx=or(#u8,lsr(Rx,#U5))
2019 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8,
2020 AddedComplexity = 30, validSubTargets = HasV4SubT in
2021 def ORi_LSRri_V4 : MInst_acc<(outs IntRegs:$dst),
2022 (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3),
2023 "$dst = or(#$src1, lsr($src2, #$src3))",
2024 [(set (i32 IntRegs:$dst),
2025 (or (srl (i32 IntRegs:$src2), u5ImmPred:$src3),
2031 //Shift by register.
2033 let validSubTargets = HasV4SubT in {
2034 def LSLi_V4 : MInst<(outs IntRegs:$dst), (ins s6Imm:$src1, IntRegs:$src2),
2035 "$dst = lsl(#$src1, $src2)",
2036 [(set (i32 IntRegs:$dst), (shl s6ImmPred:$src1,
2037 (i32 IntRegs:$src2)))]>,
2041 //Shift by register and logical.
2043 def ASLd_rr_xor_V4 : MInst_acc<(outs DoubleRegs:$dst),
2044 (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
2045 "$dst ^= asl($src2, $src3)",
2046 [(set (i64 DoubleRegs:$dst),
2047 (xor (i64 DoubleRegs:$src1), (shl (i64 DoubleRegs:$src2),
2048 (i32 IntRegs:$src3))))],
2053 def ASRd_rr_xor_V4 : MInst_acc<(outs DoubleRegs:$dst),
2054 (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
2055 "$dst ^= asr($src2, $src3)",
2056 [(set (i64 DoubleRegs:$dst),
2057 (xor (i64 DoubleRegs:$src1), (sra (i64 DoubleRegs:$src2),
2058 (i32 IntRegs:$src3))))],
2063 def LSLd_rr_xor_V4 : MInst_acc<(outs DoubleRegs:$dst),
2064 (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
2065 "$dst ^= lsl($src2, $src3)",
2066 [(set (i64 DoubleRegs:$dst), (xor (i64 DoubleRegs:$src1),
2067 (shl (i64 DoubleRegs:$src2),
2068 (i32 IntRegs:$src3))))],
2073 def LSRd_rr_xor_V4 : MInst_acc<(outs DoubleRegs:$dst),
2074 (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
2075 "$dst ^= lsr($src2, $src3)",
2076 [(set (i64 DoubleRegs:$dst),
2077 (xor (i64 DoubleRegs:$src1), (srl (i64 DoubleRegs:$src2),
2078 (i32 IntRegs:$src3))))],
2083 //===----------------------------------------------------------------------===//
2085 //===----------------------------------------------------------------------===//
2087 //===----------------------------------------------------------------------===//
2088 // MEMOP: Word, Half, Byte
2089 //===----------------------------------------------------------------------===//
2091 def MEMOPIMM : SDNodeXForm<imm, [{
2092 // Call the transformation function XformM5ToU5Imm to get the negative
2093 // immediate's positive counterpart.
2094 int32_t imm = N->getSExtValue();
2095 return XformM5ToU5Imm(imm);
2098 def MEMOPIMM_HALF : SDNodeXForm<imm, [{
2099 // -1 .. -31 represented as 65535..65515
2100 // assigning to a short restores our desired signed value.
2101 // Call the transformation function XformM5ToU5Imm to get the negative
2102 // immediate's positive counterpart.
2103 int16_t imm = N->getSExtValue();
2104 return XformM5ToU5Imm(imm);
2107 def MEMOPIMM_BYTE : SDNodeXForm<imm, [{
2108 // -1 .. -31 represented as 255..235
2109 // assigning to a char restores our desired signed value.
2110 // Call the transformation function XformM5ToU5Imm to get the negative
2111 // immediate's positive counterpart.
2112 int8_t imm = N->getSExtValue();
2113 return XformM5ToU5Imm(imm);
2116 def SETMEMIMM : SDNodeXForm<imm, [{
2117 // Return the bit position we will set [0-31].
2119 int32_t imm = N->getSExtValue();
2120 return XformMskToBitPosU5Imm(imm);
2123 def CLRMEMIMM : SDNodeXForm<imm, [{
2124 // Return the bit position we will clear [0-31].
2126 // we bit negate the value first
2127 int32_t imm = ~(N->getSExtValue());
2128 return XformMskToBitPosU5Imm(imm);
2131 def SETMEMIMM_SHORT : SDNodeXForm<imm, [{
2132 // Return the bit position we will set [0-15].
2134 int16_t imm = N->getSExtValue();
2135 return XformMskToBitPosU4Imm(imm);
2138 def CLRMEMIMM_SHORT : SDNodeXForm<imm, [{
2139 // Return the bit position we will clear [0-15].
2141 // we bit negate the value first
2142 int16_t imm = ~(N->getSExtValue());
2143 return XformMskToBitPosU4Imm(imm);
2146 def SETMEMIMM_BYTE : SDNodeXForm<imm, [{
2147 // Return the bit position we will set [0-7].
2149 int8_t imm = N->getSExtValue();
2150 return XformMskToBitPosU3Imm(imm);
2153 def CLRMEMIMM_BYTE : SDNodeXForm<imm, [{
2154 // Return the bit position we will clear [0-7].
2156 // we bit negate the value first
2157 int8_t imm = ~(N->getSExtValue());
2158 return XformMskToBitPosU3Imm(imm);
2161 //===----------------------------------------------------------------------===//
2162 // Template class for MemOp instructions with the register value.
2163 //===----------------------------------------------------------------------===//
2164 class MemOp_rr_base <string opc, bits<2> opcBits, Operand ImmOp,
2165 string memOp, bits<2> memOpBits> :
2167 (ins IntRegs:$base, ImmOp:$offset, IntRegs:$delta),
2168 opc#"($base+#$offset)"#memOp#"$delta",
2170 Requires<[HasV4T, UseMEMOP]> {
2175 bits<6> offsetBits; // memb - u6:0 , memh - u6:1, memw - u6:2
2177 let offsetBits = !if (!eq(opcBits, 0b00), offset{5-0},
2178 !if (!eq(opcBits, 0b01), offset{6-1},
2179 !if (!eq(opcBits, 0b10), offset{7-2},0)));
2181 let IClass = 0b0011;
2182 let Inst{27-24} = 0b1110;
2183 let Inst{22-21} = opcBits;
2184 let Inst{20-16} = base;
2186 let Inst{12-7} = offsetBits;
2187 let Inst{6-5} = memOpBits;
2188 let Inst{4-0} = delta;
2191 //===----------------------------------------------------------------------===//
2192 // Template class for MemOp instructions with the immediate value.
2193 //===----------------------------------------------------------------------===//
2194 class MemOp_ri_base <string opc, bits<2> opcBits, Operand ImmOp,
2195 string memOp, bits<2> memOpBits> :
2197 (ins IntRegs:$base, ImmOp:$offset, u5Imm:$delta),
2198 opc#"($base+#$offset)"#memOp#"#$delta"
2199 #!if(memOpBits{1},")", ""), // clrbit, setbit - include ')'
2201 Requires<[HasV4T, UseMEMOP]> {
2206 bits<6> offsetBits; // memb - u6:0 , memh - u6:1, memw - u6:2
2208 let offsetBits = !if (!eq(opcBits, 0b00), offset{5-0},
2209 !if (!eq(opcBits, 0b01), offset{6-1},
2210 !if (!eq(opcBits, 0b10), offset{7-2},0)));
2212 let IClass = 0b0011;
2213 let Inst{27-24} = 0b1111;
2214 let Inst{22-21} = opcBits;
2215 let Inst{20-16} = base;
2217 let Inst{12-7} = offsetBits;
2218 let Inst{6-5} = memOpBits;
2219 let Inst{4-0} = delta;
2222 // multiclass to define MemOp instructions with register operand.
2223 multiclass MemOp_rr<string opc, bits<2> opcBits, Operand ImmOp> {
2224 def _ADD#NAME#_V4 : MemOp_rr_base <opc, opcBits, ImmOp, " += ", 0b00>; // add
2225 def _SUB#NAME#_V4 : MemOp_rr_base <opc, opcBits, ImmOp, " -= ", 0b01>; // sub
2226 def _AND#NAME#_V4 : MemOp_rr_base <opc, opcBits, ImmOp, " &= ", 0b10>; // and
2227 def _OR#NAME#_V4 : MemOp_rr_base <opc, opcBits, ImmOp, " |= ", 0b11>; // or
2230 // multiclass to define MemOp instructions with immediate Operand.
2231 multiclass MemOp_ri<string opc, bits<2> opcBits, Operand ImmOp> {
2232 def _ADD#NAME#_V4 : MemOp_ri_base <opc, opcBits, ImmOp, " += ", 0b00 >;
2233 def _SUB#NAME#_V4 : MemOp_ri_base <opc, opcBits, ImmOp, " -= ", 0b01 >;
2234 def _CLRBIT#NAME#_V4 : MemOp_ri_base<opc, opcBits, ImmOp, " =clrbit(", 0b10>;
2235 def _SETBIT#NAME#_V4 : MemOp_ri_base<opc, opcBits, ImmOp, " =setbit(", 0b11>;
2238 multiclass MemOp_base <string opc, bits<2> opcBits, Operand ImmOp> {
2239 defm r : MemOp_rr <opc, opcBits, ImmOp>;
2240 defm i : MemOp_ri <opc, opcBits, ImmOp>;
2243 // Define MemOp instructions.
2244 let isExtendable = 1, opExtendable = 1, isExtentSigned = 0,
2245 validSubTargets =HasV4SubT in {
2246 let opExtentBits = 6, accessSize = ByteAccess in
2247 defm MemOPb : MemOp_base <"memb", 0b00, u6_0Ext>;
2249 let opExtentBits = 7, accessSize = HalfWordAccess in
2250 defm MemOPh : MemOp_base <"memh", 0b01, u6_1Ext>;
2252 let opExtentBits = 8, accessSize = WordAccess in
2253 defm MemOPw : MemOp_base <"memw", 0b10, u6_2Ext>;
2256 //===----------------------------------------------------------------------===//
2257 // Multiclass to define 'Def Pats' for ALU operations on the memory
2258 // Here value used for the ALU operation is an immediate value.
2259 // mem[bh](Rs+#0) += #U5
2260 // mem[bh](Rs+#u6) += #U5
2261 //===----------------------------------------------------------------------===//
2263 multiclass MemOpi_u5Pats <PatFrag ldOp, PatFrag stOp, PatLeaf ExtPred,
2264 InstHexagon MI, SDNode OpNode> {
2265 let AddedComplexity = 180 in
2266 def : Pat < (stOp (OpNode (ldOp IntRegs:$addr), u5ImmPred:$addend),
2268 (MI IntRegs:$addr, #0, u5ImmPred:$addend )>;
2270 let AddedComplexity = 190 in
2271 def : Pat <(stOp (OpNode (ldOp (add IntRegs:$base, ExtPred:$offset)),
2273 (add IntRegs:$base, ExtPred:$offset)),
2274 (MI IntRegs:$base, ExtPred:$offset, u5ImmPred:$addend)>;
2277 multiclass MemOpi_u5ALUOp<PatFrag ldOp, PatFrag stOp, PatLeaf ExtPred,
2278 InstHexagon addMI, InstHexagon subMI> {
2279 defm : MemOpi_u5Pats<ldOp, stOp, ExtPred, addMI, add>;
2280 defm : MemOpi_u5Pats<ldOp, stOp, ExtPred, subMI, sub>;
2283 multiclass MemOpi_u5ExtType<PatFrag ldOpByte, PatFrag ldOpHalf > {
2285 defm : MemOpi_u5ALUOp <ldOpHalf, truncstorei16, u6_1ExtPred,
2286 MemOPh_ADDi_V4, MemOPh_SUBi_V4>;
2288 defm : MemOpi_u5ALUOp <ldOpByte, truncstorei8, u6ExtPred,
2289 MemOPb_ADDi_V4, MemOPb_SUBi_V4>;
2292 let Predicates = [HasV4T, UseMEMOP] in {
2293 defm : MemOpi_u5ExtType<zextloadi8, zextloadi16>; // zero extend
2294 defm : MemOpi_u5ExtType<sextloadi8, sextloadi16>; // sign extend
2295 defm : MemOpi_u5ExtType<extloadi8, extloadi16>; // any extend
2298 defm : MemOpi_u5ALUOp <load, store, u6_2ExtPred, MemOPw_ADDi_V4,
2302 //===----------------------------------------------------------------------===//
2303 // multiclass to define 'Def Pats' for ALU operations on the memory.
2304 // Here value used for the ALU operation is a negative value.
2305 // mem[bh](Rs+#0) += #m5
2306 // mem[bh](Rs+#u6) += #m5
2307 //===----------------------------------------------------------------------===//
2309 multiclass MemOpi_m5Pats <PatFrag ldOp, PatFrag stOp, PatLeaf extPred,
2310 PatLeaf immPred, ComplexPattern addrPred,
2311 SDNodeXForm xformFunc, InstHexagon MI> {
2312 let AddedComplexity = 190 in
2313 def : Pat <(stOp (add (ldOp IntRegs:$addr), immPred:$subend),
2315 (MI IntRegs:$addr, #0, (xformFunc immPred:$subend) )>;
2317 let AddedComplexity = 195 in
2318 def : Pat<(stOp (add (ldOp (add IntRegs:$base, extPred:$offset)),
2320 (add IntRegs:$base, extPred:$offset)),
2321 (MI IntRegs:$base, extPred:$offset, (xformFunc immPred:$subend))>;
2324 multiclass MemOpi_m5ExtType<PatFrag ldOpByte, PatFrag ldOpHalf > {
2326 defm : MemOpi_m5Pats <ldOpHalf, truncstorei16, u6_1ExtPred, m5HImmPred,
2327 ADDRriU6_1, MEMOPIMM_HALF, MemOPh_SUBi_V4>;
2329 defm : MemOpi_m5Pats <ldOpByte, truncstorei8, u6ExtPred, m5BImmPred,
2330 ADDRriU6_0, MEMOPIMM_BYTE, MemOPb_SUBi_V4>;
2333 let Predicates = [HasV4T, UseMEMOP] in {
2334 defm : MemOpi_m5ExtType<zextloadi8, zextloadi16>; // zero extend
2335 defm : MemOpi_m5ExtType<sextloadi8, sextloadi16>; // sign extend
2336 defm : MemOpi_m5ExtType<extloadi8, extloadi16>; // any extend
2339 defm : MemOpi_m5Pats <load, store, u6_2ExtPred, m5ImmPred,
2340 ADDRriU6_2, MEMOPIMM, MemOPw_SUBi_V4>;
2343 //===----------------------------------------------------------------------===//
2344 // Multiclass to define 'def Pats' for bit operations on the memory.
2345 // mem[bhw](Rs+#0) = [clrbit|setbit](#U5)
2346 // mem[bhw](Rs+#u6) = [clrbit|setbit](#U5)
2347 //===----------------------------------------------------------------------===//
2349 multiclass MemOpi_bitPats <PatFrag ldOp, PatFrag stOp, PatLeaf immPred,
2350 PatLeaf extPred, ComplexPattern addrPred,
2351 SDNodeXForm xformFunc, InstHexagon MI, SDNode OpNode> {
2353 // mem[bhw](Rs+#u6:[012]) = [clrbit|setbit](#U5)
2354 let AddedComplexity = 250 in
2355 def : Pat<(stOp (OpNode (ldOp (add IntRegs:$base, extPred:$offset)),
2357 (add IntRegs:$base, extPred:$offset)),
2358 (MI IntRegs:$base, extPred:$offset, (xformFunc immPred:$bitend))>;
2360 // mem[bhw](Rs+#0) = [clrbit|setbit](#U5)
2361 let AddedComplexity = 225 in
2362 def : Pat <(stOp (OpNode (ldOp (addrPred IntRegs:$addr, extPred:$offset)),
2364 (addrPred (i32 IntRegs:$addr), extPred:$offset)),
2365 (MI IntRegs:$addr, extPred:$offset, (xformFunc immPred:$bitend))>;
2368 multiclass MemOpi_bitExtType<PatFrag ldOpByte, PatFrag ldOpHalf > {
2370 defm : MemOpi_bitPats<ldOpByte, truncstorei8, Clr3ImmPred, u6ExtPred,
2371 ADDRriU6_0, CLRMEMIMM_BYTE, MemOPb_CLRBITi_V4, and>;
2373 defm : MemOpi_bitPats<ldOpByte, truncstorei8, Set3ImmPred, u6ExtPred,
2374 ADDRriU6_0, SETMEMIMM_BYTE, MemOPb_SETBITi_V4, or>;
2375 // Half Word - clrbit
2376 defm : MemOpi_bitPats<ldOpHalf, truncstorei16, Clr4ImmPred, u6_1ExtPred,
2377 ADDRriU6_1, CLRMEMIMM_SHORT, MemOPh_CLRBITi_V4, and>;
2378 // Half Word - setbit
2379 defm : MemOpi_bitPats<ldOpHalf, truncstorei16, Set4ImmPred, u6_1ExtPred,
2380 ADDRriU6_1, SETMEMIMM_SHORT, MemOPh_SETBITi_V4, or>;
2383 let Predicates = [HasV4T, UseMEMOP] in {
2384 // mem[bh](Rs+#0) = [clrbit|setbit](#U5)
2385 // mem[bh](Rs+#u6:[01]) = [clrbit|setbit](#U5)
2386 defm : MemOpi_bitExtType<zextloadi8, zextloadi16>; // zero extend
2387 defm : MemOpi_bitExtType<sextloadi8, sextloadi16>; // sign extend
2388 defm : MemOpi_bitExtType<extloadi8, extloadi16>; // any extend
2390 // memw(Rs+#0) = [clrbit|setbit](#U5)
2391 // memw(Rs+#u6:2) = [clrbit|setbit](#U5)
2392 defm : MemOpi_bitPats<load, store, Clr5ImmPred, u6_2ExtPred, ADDRriU6_2,
2393 CLRMEMIMM, MemOPw_CLRBITi_V4, and>;
2394 defm : MemOpi_bitPats<load, store, Set5ImmPred, u6_2ExtPred, ADDRriU6_2,
2395 SETMEMIMM, MemOPw_SETBITi_V4, or>;
2398 //===----------------------------------------------------------------------===//
2399 // Multiclass to define 'def Pats' for ALU operations on the memory
2400 // where addend is a register.
2401 // mem[bhw](Rs+#0) [+-&|]= Rt
2402 // mem[bhw](Rs+#U6:[012]) [+-&|]= Rt
2403 //===----------------------------------------------------------------------===//
2405 multiclass MemOpr_Pats <PatFrag ldOp, PatFrag stOp, ComplexPattern addrPred,
2406 PatLeaf extPred, InstHexagon MI, SDNode OpNode> {
2407 let AddedComplexity = 141 in
2408 // mem[bhw](Rs+#0) [+-&|]= Rt
2409 def : Pat <(stOp (OpNode (ldOp (addrPred IntRegs:$addr, extPred:$offset)),
2410 (i32 IntRegs:$addend)),
2411 (addrPred (i32 IntRegs:$addr), extPred:$offset)),
2412 (MI IntRegs:$addr, extPred:$offset, (i32 IntRegs:$addend) )>;
2414 // mem[bhw](Rs+#U6:[012]) [+-&|]= Rt
2415 let AddedComplexity = 150 in
2416 def : Pat <(stOp (OpNode (ldOp (add IntRegs:$base, extPred:$offset)),
2417 (i32 IntRegs:$orend)),
2418 (add IntRegs:$base, extPred:$offset)),
2419 (MI IntRegs:$base, extPred:$offset, (i32 IntRegs:$orend) )>;
2422 multiclass MemOPr_ALUOp<PatFrag ldOp, PatFrag stOp,
2423 ComplexPattern addrPred, PatLeaf extPred,
2424 InstHexagon addMI, InstHexagon subMI,
2425 InstHexagon andMI, InstHexagon orMI > {
2427 defm : MemOpr_Pats <ldOp, stOp, addrPred, extPred, addMI, add>;
2428 defm : MemOpr_Pats <ldOp, stOp, addrPred, extPred, subMI, sub>;
2429 defm : MemOpr_Pats <ldOp, stOp, addrPred, extPred, andMI, and>;
2430 defm : MemOpr_Pats <ldOp, stOp, addrPred, extPred, orMI, or>;
2433 multiclass MemOPr_ExtType<PatFrag ldOpByte, PatFrag ldOpHalf > {
2435 defm : MemOPr_ALUOp <ldOpHalf, truncstorei16, ADDRriU6_1, u6_1ExtPred,
2436 MemOPh_ADDr_V4, MemOPh_SUBr_V4,
2437 MemOPh_ANDr_V4, MemOPh_ORr_V4>;
2439 defm : MemOPr_ALUOp <ldOpByte, truncstorei8, ADDRriU6_0, u6ExtPred,
2440 MemOPb_ADDr_V4, MemOPb_SUBr_V4,
2441 MemOPb_ANDr_V4, MemOPb_ORr_V4>;
2444 // Define 'def Pats' for MemOps with register addend.
2445 let Predicates = [HasV4T, UseMEMOP] in {
2447 defm : MemOPr_ExtType<zextloadi8, zextloadi16>; // zero extend
2448 defm : MemOPr_ExtType<sextloadi8, sextloadi16>; // sign extend
2449 defm : MemOPr_ExtType<extloadi8, extloadi16>; // any extend
2451 defm : MemOPr_ALUOp <load, store, ADDRriU6_2, u6_2ExtPred, MemOPw_ADDr_V4,
2452 MemOPw_SUBr_V4, MemOPw_ANDr_V4, MemOPw_ORr_V4 >;
2455 //===----------------------------------------------------------------------===//
2457 //===----------------------------------------------------------------------===//
2459 // Hexagon V4 only supports these flavors of byte/half compare instructions:
2460 // EQ/GT/GTU. Other flavors like GE/GEU/LT/LTU/LE/LEU are not supported by
2461 // hardware. However, compiler can still implement these patterns through
2462 // appropriate patterns combinations based on current implemented patterns.
2463 // The implemented patterns are: EQ/GT/GTU.
2464 // Missing patterns are: GE/GEU/LT/LTU/LE/LEU.
2466 // Following instruction is not being extended as it results into the
2467 // incorrect code for negative numbers.
2468 // Pd=cmpb.eq(Rs,#u8)
2470 let isCompare = 1, isExtendable = 1, opExtendable = 2, hasSideEffects = 0,
2471 validSubTargets = HasV4SubT in
2472 class CMP_NOT_REG_IMM<string OpName, bits<2> op, Operand ImmOp,
2474 : ALU32Inst <(outs PredRegs:$dst), (ins IntRegs:$src1, ImmOp:$src2),
2475 "$dst = !cmp."#OpName#"($src1, #$src2)",
2477 "", ALU32_2op_tc_2early_SLOT0123> {
2482 let IClass = 0b0111;
2483 let Inst{27-24} = 0b0101;
2484 let Inst{23-22} = op;
2485 let Inst{20-16} = src1;
2486 let Inst{21} = !if (!eq(OpName, "gtu"), 0b0, src2{9});
2487 let Inst{13-5} = src2{8-0};
2488 let Inst{4-2} = 0b100;
2489 let Inst{1-0} = dst;
2492 let opExtentBits = 10, isExtentSigned = 1 in {
2493 def C4_cmpneqi : CMP_NOT_REG_IMM <"eq", 0b00, s10Ext, [(set (i1 PredRegs:$dst),
2494 (setne (i32 IntRegs:$src1), s10ExtPred:$src2))]>;
2496 def C4_cmpltei : CMP_NOT_REG_IMM <"gt", 0b01, s10Ext, [(set (i1 PredRegs:$dst),
2497 (not (setgt (i32 IntRegs:$src1), s10ExtPred:$src2)))]>;
2500 let opExtentBits = 9 in
2501 def C4_cmplteui : CMP_NOT_REG_IMM <"gtu", 0b10, u9Ext, [(set (i1 PredRegs:$dst),
2502 (not (setugt (i32 IntRegs:$src1), u9ExtPred:$src2)))]>;
2507 let isCompare = 1, validSubTargets = HasV4SubT in
2508 def CMPnotEQ_rr : ALU32_rr<(outs PredRegs:$dst),
2509 (ins IntRegs:$src1, IntRegs:$src2),
2510 "$dst = !cmp.eq($src1, $src2)",
2511 [(set (i1 PredRegs:$dst),
2512 (setne (i32 IntRegs:$src1), (i32 IntRegs:$src2)))]>,
2516 let isCompare = 1, validSubTargets = HasV4SubT in
2517 def CMPnotGT_rr : ALU32_rr<(outs PredRegs:$dst),
2518 (ins IntRegs:$src1, IntRegs:$src2),
2519 "$dst = !cmp.gt($src1, $src2)",
2520 [(set (i1 PredRegs:$dst),
2521 (not (setgt (i32 IntRegs:$src1), (i32 IntRegs:$src2))))]>,
2525 // p=!cmp.gtu(r1,r2)
2526 let isCompare = 1, validSubTargets = HasV4SubT in
2527 def CMPnotGTU_rr : ALU32_rr<(outs PredRegs:$dst),
2528 (ins IntRegs:$src1, IntRegs:$src2),
2529 "$dst = !cmp.gtu($src1, $src2)",
2530 [(set (i1 PredRegs:$dst),
2531 (not (setugt (i32 IntRegs:$src1), (i32 IntRegs:$src2))))]>,
2534 let isCompare = 1, validSubTargets = HasV4SubT in
2535 def CMPbEQri_V4 : MInst<(outs PredRegs:$dst),
2536 (ins IntRegs:$src1, u8Imm:$src2),
2537 "$dst = cmpb.eq($src1, #$src2)",
2538 [(set (i1 PredRegs:$dst),
2539 (seteq (and (i32 IntRegs:$src1), 255), u8ImmPred:$src2))]>,
2542 def : Pat <(brcond (i1 (setne (and (i32 IntRegs:$src1), 255), u8ImmPred:$src2)),
2544 (J2_jumpf (CMPbEQri_V4 (i32 IntRegs:$src1), u8ImmPred:$src2),
2548 // Pd=cmpb.eq(Rs,Rt)
2549 let isCompare = 1, validSubTargets = HasV4SubT in
2550 def CMPbEQrr_ubub_V4 : MInst<(outs PredRegs:$dst),
2551 (ins IntRegs:$src1, IntRegs:$src2),
2552 "$dst = cmpb.eq($src1, $src2)",
2553 [(set (i1 PredRegs:$dst),
2554 (seteq (and (xor (i32 IntRegs:$src1),
2555 (i32 IntRegs:$src2)), 255), 0))]>,
2558 // Pd=cmpb.eq(Rs,Rt)
2559 let isCompare = 1, validSubTargets = HasV4SubT in
2560 def CMPbEQrr_sbsb_V4 : MInst<(outs PredRegs:$dst),
2561 (ins IntRegs:$src1, IntRegs:$src2),
2562 "$dst = cmpb.eq($src1, $src2)",
2563 [(set (i1 PredRegs:$dst),
2564 (seteq (shl (i32 IntRegs:$src1), (i32 24)),
2565 (shl (i32 IntRegs:$src2), (i32 24))))]>,
2568 // Pd=cmpb.gt(Rs,Rt)
2569 let isCompare = 1, validSubTargets = HasV4SubT in
2570 def CMPbGTrr_V4 : MInst<(outs PredRegs:$dst),
2571 (ins IntRegs:$src1, IntRegs:$src2),
2572 "$dst = cmpb.gt($src1, $src2)",
2573 [(set (i1 PredRegs:$dst),
2574 (setgt (shl (i32 IntRegs:$src1), (i32 24)),
2575 (shl (i32 IntRegs:$src2), (i32 24))))]>,
2578 // Pd=cmpb.gtu(Rs,#u7)
2579 let isExtendable = 1, opExtendable = 2, isExtentSigned = 0, opExtentBits = 7,
2580 isCompare = 1, validSubTargets = HasV4SubT, CextOpcode = "CMPbGTU", InputType = "imm" in
2581 def CMPbGTUri_V4 : MInst<(outs PredRegs:$dst),
2582 (ins IntRegs:$src1, u7Ext:$src2),
2583 "$dst = cmpb.gtu($src1, #$src2)",
2584 [(set (i1 PredRegs:$dst), (setugt (and (i32 IntRegs:$src1), 255),
2585 u7ExtPred:$src2))]>,
2586 Requires<[HasV4T]>, ImmRegRel;
2588 // SDNode for converting immediate C to C-1.
2589 def DEC_CONST_BYTE : SDNodeXForm<imm, [{
2590 // Return the byte immediate const-1 as an SDNode.
2591 int32_t imm = N->getSExtValue();
2592 return XformU7ToU7M1Imm(imm);
2596 // zext( seteq ( and(Rs, 255), u8))
2598 // Pd=cmpb.eq(Rs, #u8)
2599 // if (Pd.new) Rd=#1
2600 // if (!Pd.new) Rd=#0
2601 def : Pat <(i32 (zext (i1 (seteq (i32 (and (i32 IntRegs:$Rs), 255)),
2603 (i32 (TFR_condset_ii (i1 (CMPbEQri_V4 (i32 IntRegs:$Rs),
2609 // zext( setne ( and(Rs, 255), u8))
2611 // Pd=cmpb.eq(Rs, #u8)
2612 // if (Pd.new) Rd=#0
2613 // if (!Pd.new) Rd=#1
2614 def : Pat <(i32 (zext (i1 (setne (i32 (and (i32 IntRegs:$Rs), 255)),
2616 (i32 (TFR_condset_ii (i1 (CMPbEQri_V4 (i32 IntRegs:$Rs),
2622 // zext( seteq (Rs, and(Rt, 255)))
2624 // Pd=cmpb.eq(Rs, Rt)
2625 // if (Pd.new) Rd=#1
2626 // if (!Pd.new) Rd=#0
2627 def : Pat <(i32 (zext (i1 (seteq (i32 IntRegs:$Rt),
2628 (i32 (and (i32 IntRegs:$Rs), 255)))))),
2629 (i32 (TFR_condset_ii (i1 (CMPbEQrr_ubub_V4 (i32 IntRegs:$Rs),
2630 (i32 IntRegs:$Rt))),
2635 // zext( setne (Rs, and(Rt, 255)))
2637 // Pd=cmpb.eq(Rs, Rt)
2638 // if (Pd.new) Rd=#0
2639 // if (!Pd.new) Rd=#1
2640 def : Pat <(i32 (zext (i1 (setne (i32 IntRegs:$Rt),
2641 (i32 (and (i32 IntRegs:$Rs), 255)))))),
2642 (i32 (TFR_condset_ii (i1 (CMPbEQrr_ubub_V4 (i32 IntRegs:$Rs),
2643 (i32 IntRegs:$Rt))),
2648 // zext( setugt ( and(Rs, 255), u8))
2650 // Pd=cmpb.gtu(Rs, #u8)
2651 // if (Pd.new) Rd=#1
2652 // if (!Pd.new) Rd=#0
2653 def : Pat <(i32 (zext (i1 (setugt (i32 (and (i32 IntRegs:$Rs), 255)),
2655 (i32 (TFR_condset_ii (i1 (CMPbGTUri_V4 (i32 IntRegs:$Rs),
2661 // zext( setugt ( and(Rs, 254), u8))
2663 // Pd=cmpb.gtu(Rs, #u8)
2664 // if (Pd.new) Rd=#1
2665 // if (!Pd.new) Rd=#0
2666 def : Pat <(i32 (zext (i1 (setugt (i32 (and (i32 IntRegs:$Rs), 254)),
2668 (i32 (TFR_condset_ii (i1 (CMPbGTUri_V4 (i32 IntRegs:$Rs),
2674 // zext( setult ( Rs, Rt))
2676 // Pd=cmp.ltu(Rs, Rt)
2677 // if (Pd.new) Rd=#1
2678 // if (!Pd.new) Rd=#0
2679 // cmp.ltu(Rs, Rt) -> cmp.gtu(Rt, Rs)
2680 def : Pat <(i32 (zext (i1 (setult (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
2681 (i32 (TFR_condset_ii (i1 (C2_cmpgtu (i32 IntRegs:$Rt),
2682 (i32 IntRegs:$Rs))),
2687 // zext( setlt ( Rs, Rt))
2689 // Pd=cmp.lt(Rs, Rt)
2690 // if (Pd.new) Rd=#1
2691 // if (!Pd.new) Rd=#0
2692 // cmp.lt(Rs, Rt) -> cmp.gt(Rt, Rs)
2693 def : Pat <(i32 (zext (i1 (setlt (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
2694 (i32 (TFR_condset_ii (i1 (C2_cmpgt (i32 IntRegs:$Rt),
2695 (i32 IntRegs:$Rs))),
2700 // zext( setugt ( Rs, Rt))
2702 // Pd=cmp.gtu(Rs, Rt)
2703 // if (Pd.new) Rd=#1
2704 // if (!Pd.new) Rd=#0
2705 def : Pat <(i32 (zext (i1 (setugt (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
2706 (i32 (TFR_condset_ii (i1 (C2_cmpgtu (i32 IntRegs:$Rs),
2707 (i32 IntRegs:$Rt))),
2711 // This pattern interefers with coremark performance, not implementing at this
2714 // zext( setgt ( Rs, Rt))
2716 // Pd=cmp.gt(Rs, Rt)
2717 // if (Pd.new) Rd=#1
2718 // if (!Pd.new) Rd=#0
2721 // zext( setuge ( Rs, Rt))
2723 // Pd=cmp.ltu(Rs, Rt)
2724 // if (Pd.new) Rd=#0
2725 // if (!Pd.new) Rd=#1
2726 // cmp.ltu(Rs, Rt) -> cmp.gtu(Rt, Rs)
2727 def : Pat <(i32 (zext (i1 (setuge (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
2728 (i32 (TFR_condset_ii (i1 (C2_cmpgtu (i32 IntRegs:$Rt),
2729 (i32 IntRegs:$Rs))),
2734 // zext( setge ( Rs, Rt))
2736 // Pd=cmp.lt(Rs, Rt)
2737 // if (Pd.new) Rd=#0
2738 // if (!Pd.new) Rd=#1
2739 // cmp.lt(Rs, Rt) -> cmp.gt(Rt, Rs)
2740 def : Pat <(i32 (zext (i1 (setge (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
2741 (i32 (TFR_condset_ii (i1 (C2_cmpgt (i32 IntRegs:$Rt),
2742 (i32 IntRegs:$Rs))),
2747 // zext( setule ( Rs, Rt))
2749 // Pd=cmp.gtu(Rs, Rt)
2750 // if (Pd.new) Rd=#0
2751 // if (!Pd.new) Rd=#1
2752 def : Pat <(i32 (zext (i1 (setule (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
2753 (i32 (TFR_condset_ii (i1 (C2_cmpgtu (i32 IntRegs:$Rs),
2754 (i32 IntRegs:$Rt))),
2759 // zext( setle ( Rs, Rt))
2761 // Pd=cmp.gt(Rs, Rt)
2762 // if (Pd.new) Rd=#0
2763 // if (!Pd.new) Rd=#1
2764 def : Pat <(i32 (zext (i1 (setle (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
2765 (i32 (TFR_condset_ii (i1 (C2_cmpgt (i32 IntRegs:$Rs),
2766 (i32 IntRegs:$Rt))),
2771 // zext( setult ( and(Rs, 255), u8))
2772 // Use the isdigit transformation below
2774 // Generate code of the form 'mux_ii(cmpbgtu(Rdd, C-1),0,1)'
2775 // for C code of the form r = ((c>='0') & (c<='9')) ? 1 : 0;.
2776 // The isdigit transformation relies on two 'clever' aspects:
2777 // 1) The data type is unsigned which allows us to eliminate a zero test after
2778 // biasing the expression by 48. We are depending on the representation of
2779 // the unsigned types, and semantics.
2780 // 2) The front end has converted <= 9 into < 10 on entry to LLVM
2783 // retval = ((c>='0') & (c<='9')) ? 1 : 0;
2784 // The code is transformed upstream of llvm into
2785 // retval = (c-48) < 10 ? 1 : 0;
2786 let AddedComplexity = 139 in
2787 def : Pat <(i32 (zext (i1 (setult (i32 (and (i32 IntRegs:$src1), 255)),
2788 u7StrictPosImmPred:$src2)))),
2789 (i32 (C2_muxii (i1 (CMPbGTUri_V4 (i32 IntRegs:$src1),
2790 (DEC_CONST_BYTE u7StrictPosImmPred:$src2))),
2794 // Pd=cmpb.gtu(Rs,Rt)
2795 let isCompare = 1, validSubTargets = HasV4SubT, CextOpcode = "CMPbGTU",
2796 InputType = "reg" in
2797 def CMPbGTUrr_V4 : MInst<(outs PredRegs:$dst),
2798 (ins IntRegs:$src1, IntRegs:$src2),
2799 "$dst = cmpb.gtu($src1, $src2)",
2800 [(set (i1 PredRegs:$dst), (setugt (and (i32 IntRegs:$src1), 255),
2801 (and (i32 IntRegs:$src2), 255)))]>,
2802 Requires<[HasV4T]>, ImmRegRel;
2804 // Following instruction is not being extended as it results into the incorrect
2805 // code for negative numbers.
2807 // Signed half compare(.eq) ri.
2808 // Pd=cmph.eq(Rs,#s8)
2809 let isCompare = 1, validSubTargets = HasV4SubT in
2810 def CMPhEQri_V4 : MInst<(outs PredRegs:$dst),
2811 (ins IntRegs:$src1, s8Imm:$src2),
2812 "$dst = cmph.eq($src1, #$src2)",
2813 [(set (i1 PredRegs:$dst), (seteq (and (i32 IntRegs:$src1), 65535),
2814 s8ImmPred:$src2))]>,
2817 // Signed half compare(.eq) rr.
2818 // Case 1: xor + and, then compare:
2820 // r0=and(r0,#0xffff)
2822 // Pd=cmph.eq(Rs,Rt)
2823 let isCompare = 1, validSubTargets = HasV4SubT in
2824 def CMPhEQrr_xor_V4 : MInst<(outs PredRegs:$dst),
2825 (ins IntRegs:$src1, IntRegs:$src2),
2826 "$dst = cmph.eq($src1, $src2)",
2827 [(set (i1 PredRegs:$dst), (seteq (and (xor (i32 IntRegs:$src1),
2828 (i32 IntRegs:$src2)),
2832 // Signed half compare(.eq) rr.
2833 // Case 2: shift left 16 bits then compare:
2837 // Pd=cmph.eq(Rs,Rt)
2838 let isCompare = 1, validSubTargets = HasV4SubT in
2839 def CMPhEQrr_shl_V4 : MInst<(outs PredRegs:$dst),
2840 (ins IntRegs:$src1, IntRegs:$src2),
2841 "$dst = cmph.eq($src1, $src2)",
2842 [(set (i1 PredRegs:$dst),
2843 (seteq (shl (i32 IntRegs:$src1), (i32 16)),
2844 (shl (i32 IntRegs:$src2), (i32 16))))]>,
2847 /* Incorrect Pattern -- immediate should be right shifted before being
2848 used in the cmph.gt instruction.
2849 // Signed half compare(.gt) ri.
2850 // Pd=cmph.gt(Rs,#s8)
2852 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 8,
2853 isCompare = 1, validSubTargets = HasV4SubT in
2854 def CMPhGTri_V4 : MInst<(outs PredRegs:$dst),
2855 (ins IntRegs:$src1, s8Ext:$src2),
2856 "$dst = cmph.gt($src1, #$src2)",
2857 [(set (i1 PredRegs:$dst),
2858 (setgt (shl (i32 IntRegs:$src1), (i32 16)),
2859 s8ExtPred:$src2))]>,
2863 // Signed half compare(.gt) rr.
2864 // Pd=cmph.gt(Rs,Rt)
2865 let isCompare = 1, validSubTargets = HasV4SubT in
2866 def CMPhGTrr_shl_V4 : MInst<(outs PredRegs:$dst),
2867 (ins IntRegs:$src1, IntRegs:$src2),
2868 "$dst = cmph.gt($src1, $src2)",
2869 [(set (i1 PredRegs:$dst),
2870 (setgt (shl (i32 IntRegs:$src1), (i32 16)),
2871 (shl (i32 IntRegs:$src2), (i32 16))))]>,
2874 // Unsigned half compare rr (.gtu).
2875 // Pd=cmph.gtu(Rs,Rt)
2876 let isCompare = 1, validSubTargets = HasV4SubT, CextOpcode = "CMPhGTU",
2877 InputType = "reg" in
2878 def CMPhGTUrr_V4 : MInst<(outs PredRegs:$dst),
2879 (ins IntRegs:$src1, IntRegs:$src2),
2880 "$dst = cmph.gtu($src1, $src2)",
2881 [(set (i1 PredRegs:$dst),
2882 (setugt (and (i32 IntRegs:$src1), 65535),
2883 (and (i32 IntRegs:$src2), 65535)))]>,
2884 Requires<[HasV4T]>, ImmRegRel;
2886 // Unsigned half compare ri (.gtu).
2887 // Pd=cmph.gtu(Rs,#u7)
2888 let isExtendable = 1, opExtendable = 2, isExtentSigned = 0, opExtentBits = 7,
2889 isCompare = 1, validSubTargets = HasV4SubT, CextOpcode = "CMPhGTU",
2890 InputType = "imm" in
2891 def CMPhGTUri_V4 : MInst<(outs PredRegs:$dst),
2892 (ins IntRegs:$src1, u7Ext:$src2),
2893 "$dst = cmph.gtu($src1, #$src2)",
2894 [(set (i1 PredRegs:$dst), (setugt (and (i32 IntRegs:$src1), 65535),
2895 u7ExtPred:$src2))]>,
2896 Requires<[HasV4T]>, ImmRegRel;
2898 let validSubTargets = HasV4SubT in
2899 def NTSTBIT_rr : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2900 "$dst = !tstbit($src1, $src2)",
2901 [(set (i1 PredRegs:$dst),
2902 (seteq (and (shl 1, (i32 IntRegs:$src2)), (i32 IntRegs:$src1)), 0))]>,
2905 let validSubTargets = HasV4SubT in
2906 def NTSTBIT_ri : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
2907 "$dst = !tstbit($src1, $src2)",
2908 [(set (i1 PredRegs:$dst),
2909 (seteq (and (shl 1, u5ImmPred:$src2), (i32 IntRegs:$src1)), 0))]>,
2912 //===----------------------------------------------------------------------===//
2914 //===----------------------------------------------------------------------===//
2916 //Deallocate frame and return.
2918 let isReturn = 1, isTerminator = 1, isBarrier = 1, isPredicable = 1,
2919 Defs = [R29, R30, R31, PC], Uses = [R30], hasSideEffects = 0 in {
2920 let validSubTargets = HasV4SubT in
2921 def DEALLOC_RET_V4 : LD0Inst<(outs), (ins),
2927 // Restore registers and dealloc return function call.
2928 let isCall = 1, isBarrier = 1, isReturn = 1, isTerminator = 1,
2929 Defs = [R29, R30, R31, PC] in {
2930 let validSubTargets = HasV4SubT in
2931 def RESTORE_DEALLOC_RET_JMP_V4 : JInst<(outs),
2932 (ins calltarget:$dst),
2938 // Restore registers and dealloc frame before a tail call.
2939 let isCall = 1, isBarrier = 1,
2940 Defs = [R29, R30, R31, PC] in {
2941 let validSubTargets = HasV4SubT in
2942 def RESTORE_DEALLOC_BEFORE_TAILCALL_V4 : JInst<(outs),
2943 (ins calltarget:$dst),
2949 // Save registers function call.
2950 let isCall = 1, isBarrier = 1,
2951 Uses = [R29, R31] in {
2952 def SAVE_REGISTERS_CALL_V4 : JInst<(outs),
2953 (ins calltarget:$dst),
2954 "call $dst // Save_calle_saved_registers",
2959 // if (Ps) dealloc_return
2960 let isReturn = 1, isTerminator = 1,
2961 Defs = [R29, R30, R31, PC], Uses = [R30], hasSideEffects = 0,
2962 isPredicated = 1 in {
2963 let validSubTargets = HasV4SubT in
2964 def DEALLOC_RET_cPt_V4 : LD0Inst<(outs),
2965 (ins PredRegs:$src1),
2966 "if ($src1) dealloc_return",
2971 // if (!Ps) dealloc_return
2972 let isReturn = 1, isTerminator = 1,
2973 Defs = [R29, R30, R31, PC], Uses = [R30], hasSideEffects = 0,
2974 isPredicated = 1, isPredicatedFalse = 1 in {
2975 let validSubTargets = HasV4SubT in
2976 def DEALLOC_RET_cNotPt_V4 : LD0Inst<(outs), (ins PredRegs:$src1),
2977 "if (!$src1) dealloc_return",
2982 // if (Ps.new) dealloc_return:nt
2983 let isReturn = 1, isTerminator = 1,
2984 Defs = [R29, R30, R31, PC], Uses = [R30], hasSideEffects = 0,
2985 isPredicated = 1 in {
2986 let validSubTargets = HasV4SubT in
2987 def DEALLOC_RET_cdnPnt_V4 : LD0Inst<(outs), (ins PredRegs:$src1),
2988 "if ($src1.new) dealloc_return:nt",
2993 // if (!Ps.new) dealloc_return:nt
2994 let isReturn = 1, isTerminator = 1,
2995 Defs = [R29, R30, R31, PC], Uses = [R30], hasSideEffects = 0,
2996 isPredicated = 1, isPredicatedFalse = 1 in {
2997 let validSubTargets = HasV4SubT in
2998 def DEALLOC_RET_cNotdnPnt_V4 : LD0Inst<(outs), (ins PredRegs:$src1),
2999 "if (!$src1.new) dealloc_return:nt",
3004 // if (Ps.new) dealloc_return:t
3005 let isReturn = 1, isTerminator = 1,
3006 Defs = [R29, R30, R31, PC], Uses = [R30], hasSideEffects = 0,
3007 isPredicated = 1 in {
3008 let validSubTargets = HasV4SubT in
3009 def DEALLOC_RET_cdnPt_V4 : LD0Inst<(outs), (ins PredRegs:$src1),
3010 "if ($src1.new) dealloc_return:t",
3015 // if (!Ps.new) dealloc_return:nt
3016 let isReturn = 1, isTerminator = 1,
3017 Defs = [R29, R30, R31, PC], Uses = [R30], hasSideEffects = 0,
3018 isPredicated = 1, isPredicatedFalse = 1 in {
3019 let validSubTargets = HasV4SubT in
3020 def DEALLOC_RET_cNotdnPt_V4 : LD0Inst<(outs), (ins PredRegs:$src1),
3021 "if (!$src1.new) dealloc_return:t",
3026 // Load/Store with absolute addressing mode
3029 multiclass ST_Abs_Predbase<string mnemonic, RegisterClass RC, bit isNot,
3031 let isPredicatedNew = isPredNew in
3032 def NAME#_V4 : STInst2<(outs),
3033 (ins PredRegs:$src1, u0AlwaysExt:$absaddr, RC: $src2),
3034 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
3035 ") ")#mnemonic#"(##$absaddr) = $src2",
3040 multiclass ST_Abs_Pred<string mnemonic, RegisterClass RC, bit PredNot> {
3041 let isPredicatedFalse = PredNot in {
3042 defm _c#NAME : ST_Abs_Predbase<mnemonic, RC, PredNot, 0>;
3044 defm _cdn#NAME : ST_Abs_Predbase<mnemonic, RC, PredNot, 1>;
3048 let isNVStorable = 1, isExtended = 1, hasSideEffects = 0 in
3049 multiclass ST_Abs<string mnemonic, string CextOp, RegisterClass RC> {
3050 let CextOpcode = CextOp, BaseOpcode = CextOp#_abs in {
3051 let opExtendable = 0, isPredicable = 1 in
3052 def NAME#_V4 : STInst2<(outs),
3053 (ins u0AlwaysExt:$absaddr, RC:$src),
3054 mnemonic#"(##$absaddr) = $src",
3058 let opExtendable = 1, isPredicated = 1 in {
3059 defm Pt : ST_Abs_Pred<mnemonic, RC, 0>;
3060 defm NotPt : ST_Abs_Pred<mnemonic, RC, 1>;
3065 multiclass ST_Abs_Predbase_nv<string mnemonic, RegisterClass RC, bit isNot,
3067 let isPredicatedNew = isPredNew in
3068 def NAME#_nv_V4 : NVInst_V4<(outs),
3069 (ins PredRegs:$src1, u0AlwaysExt:$absaddr, RC: $src2),
3070 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
3071 ") ")#mnemonic#"(##$absaddr) = $src2.new",
3076 multiclass ST_Abs_Pred_nv<string mnemonic, RegisterClass RC, bit PredNot> {
3077 let isPredicatedFalse = PredNot in {
3078 defm _c#NAME : ST_Abs_Predbase_nv<mnemonic, RC, PredNot, 0>;
3080 defm _cdn#NAME : ST_Abs_Predbase_nv<mnemonic, RC, PredNot, 1>;
3084 let mayStore = 1, isNVStore = 1, isExtended = 1, hasSideEffects = 0 in
3085 multiclass ST_Abs_nv<string mnemonic, string CextOp, RegisterClass RC> {
3086 let CextOpcode = CextOp, BaseOpcode = CextOp#_abs in {
3087 let opExtendable = 0, isPredicable = 1 in
3088 def NAME#_nv_V4 : NVInst_V4<(outs),
3089 (ins u0AlwaysExt:$absaddr, RC:$src),
3090 mnemonic#"(##$absaddr) = $src.new",
3094 let opExtendable = 1, isPredicated = 1 in {
3095 defm Pt : ST_Abs_Pred_nv<mnemonic, RC, 0>;
3096 defm NotPt : ST_Abs_Pred_nv<mnemonic, RC, 1>;
3101 let addrMode = Absolute in {
3102 let accessSize = ByteAccess in
3103 defm STrib_abs : ST_Abs<"memb", "STrib", IntRegs>,
3104 ST_Abs_nv<"memb", "STrib", IntRegs>, AddrModeRel;
3106 let accessSize = HalfWordAccess in
3107 defm STrih_abs : ST_Abs<"memh", "STrih", IntRegs>,
3108 ST_Abs_nv<"memh", "STrih", IntRegs>, AddrModeRel;
3110 let accessSize = WordAccess in
3111 defm STriw_abs : ST_Abs<"memw", "STriw", IntRegs>,
3112 ST_Abs_nv<"memw", "STriw", IntRegs>, AddrModeRel;
3114 let accessSize = DoubleWordAccess, isNVStorable = 0 in
3115 defm STrid_abs : ST_Abs<"memd", "STrid", DoubleRegs>, AddrModeRel;
3118 let Predicates = [HasV4T], AddedComplexity = 30 in {
3119 def : Pat<(truncstorei8 (i32 IntRegs:$src1),
3120 (HexagonCONST32 tglobaladdr:$absaddr)),
3121 (STrib_abs_V4 tglobaladdr: $absaddr, IntRegs: $src1)>;
3123 def : Pat<(truncstorei16 (i32 IntRegs:$src1),
3124 (HexagonCONST32 tglobaladdr:$absaddr)),
3125 (STrih_abs_V4 tglobaladdr: $absaddr, IntRegs: $src1)>;
3127 def : Pat<(store (i32 IntRegs:$src1), (HexagonCONST32 tglobaladdr:$absaddr)),
3128 (STriw_abs_V4 tglobaladdr: $absaddr, IntRegs: $src1)>;
3130 def : Pat<(store (i64 DoubleRegs:$src1),
3131 (HexagonCONST32 tglobaladdr:$absaddr)),
3132 (STrid_abs_V4 tglobaladdr: $absaddr, DoubleRegs: $src1)>;
3135 //===----------------------------------------------------------------------===//
3136 // multiclass for store instructions with GP-relative addressing mode.
3137 // mem[bhwd](#global)=Rt
3138 // if ([!]Pv[.new]) mem[bhwd](##global) = Rt
3139 //===----------------------------------------------------------------------===//
3140 let mayStore = 1, isNVStorable = 1 in
3141 multiclass ST_GP<string mnemonic, string BaseOp, RegisterClass RC> {
3142 let BaseOpcode = BaseOp, isPredicable = 1 in
3143 def NAME#_V4 : STInst2<(outs),
3144 (ins globaladdress:$global, RC:$src),
3145 mnemonic#"(#$global) = $src",
3148 // When GP-relative instructions are predicated, their addressing mode is
3149 // changed to absolute and they are always constant extended.
3150 let BaseOpcode = BaseOp, isExtended = 1, opExtendable = 1,
3151 isPredicated = 1 in {
3152 defm Pt : ST_Abs_Pred <mnemonic, RC, 0>;
3153 defm NotPt : ST_Abs_Pred <mnemonic, RC, 1>;
3157 let mayStore = 1, isNVStore = 1 in
3158 multiclass ST_GP_nv<string mnemonic, string BaseOp, RegisterClass RC> {
3159 let BaseOpcode = BaseOp, isPredicable = 1 in
3160 def NAME#_nv_V4 : NVInst_V4<(outs),
3161 (ins u0AlwaysExt:$global, RC:$src),
3162 mnemonic#"(#$global) = $src.new",
3166 // When GP-relative instructions are predicated, their addressing mode is
3167 // changed to absolute and they are always constant extended.
3168 let BaseOpcode = BaseOp, isExtended = 1, opExtendable = 1,
3169 isPredicated = 1 in {
3170 defm Pt : ST_Abs_Pred_nv<mnemonic, RC, 0>;
3171 defm NotPt : ST_Abs_Pred_nv<mnemonic, RC, 1>;
3175 let validSubTargets = HasV4SubT, hasSideEffects = 0 in {
3176 let isNVStorable = 0 in
3177 defm STd_GP : ST_GP <"memd", "STd_GP", DoubleRegs>, PredNewRel;
3179 defm STb_GP : ST_GP<"memb", "STb_GP", IntRegs>,
3180 ST_GP_nv<"memb", "STb_GP", IntRegs>, NewValueRel;
3181 defm STh_GP : ST_GP<"memh", "STh_GP", IntRegs>,
3182 ST_GP_nv<"memh", "STh_GP", IntRegs>, NewValueRel;
3183 defm STw_GP : ST_GP<"memw", "STw_GP", IntRegs>,
3184 ST_GP_nv<"memw", "STw_GP", IntRegs>, NewValueRel;
3187 // 64 bit atomic store
3188 def : Pat <(atomic_store_64 (HexagonCONST32_GP tglobaladdr:$global),
3189 (i64 DoubleRegs:$src1)),
3190 (STd_GP_V4 tglobaladdr:$global, (i64 DoubleRegs:$src1))>,
3193 // Map from store(globaladdress) -> memd(#foo)
3194 let AddedComplexity = 100 in
3195 def : Pat <(store (i64 DoubleRegs:$src1),
3196 (HexagonCONST32_GP tglobaladdr:$global)),
3197 (STd_GP_V4 tglobaladdr:$global, (i64 DoubleRegs:$src1))>;
3199 // 8 bit atomic store
3200 def : Pat < (atomic_store_8 (HexagonCONST32_GP tglobaladdr:$global),
3201 (i32 IntRegs:$src1)),
3202 (STb_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>;
3204 // Map from store(globaladdress) -> memb(#foo)
3205 let AddedComplexity = 100 in
3206 def : Pat<(truncstorei8 (i32 IntRegs:$src1),
3207 (HexagonCONST32_GP tglobaladdr:$global)),
3208 (STb_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>;
3210 // Map from "i1 = constant<-1>; memw(CONST32(#foo)) = i1"
3211 // to "r0 = 1; memw(#foo) = r0"
3212 let AddedComplexity = 100 in
3213 def : Pat<(store (i1 -1), (HexagonCONST32_GP tglobaladdr:$global)),
3214 (STb_GP_V4 tglobaladdr:$global, (A2_tfrsi 1))>;
3216 def : Pat<(atomic_store_16 (HexagonCONST32_GP tglobaladdr:$global),
3217 (i32 IntRegs:$src1)),
3218 (STh_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>;
3220 // Map from store(globaladdress) -> memh(#foo)
3221 let AddedComplexity = 100 in
3222 def : Pat<(truncstorei16 (i32 IntRegs:$src1),
3223 (HexagonCONST32_GP tglobaladdr:$global)),
3224 (STh_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>;
3226 // 32 bit atomic store
3227 def : Pat<(atomic_store_32 (HexagonCONST32_GP tglobaladdr:$global),
3228 (i32 IntRegs:$src1)),
3229 (STw_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>;
3231 // Map from store(globaladdress) -> memw(#foo)
3232 let AddedComplexity = 100 in
3233 def : Pat<(store (i32 IntRegs:$src1), (HexagonCONST32_GP tglobaladdr:$global)),
3234 (STw_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>;
3236 //===----------------------------------------------------------------------===//
3237 // Multiclass for the load instructions with absolute addressing mode.
3238 //===----------------------------------------------------------------------===//
3239 multiclass LD_Abs_Predbase<string mnemonic, RegisterClass RC, bit isNot,
3241 let isPredicatedNew = isPredNew in
3242 def NAME : LDInst2<(outs RC:$dst),
3243 (ins PredRegs:$src1, u0AlwaysExt:$absaddr),
3244 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
3245 ") ")#"$dst = "#mnemonic#"(##$absaddr)",
3250 multiclass LD_Abs_Pred<string mnemonic, RegisterClass RC, bit PredNot> {
3251 let isPredicatedFalse = PredNot in {
3252 defm _c#NAME : LD_Abs_Predbase<mnemonic, RC, PredNot, 0>;
3254 defm _cdn#NAME : LD_Abs_Predbase<mnemonic, RC, PredNot, 1>;
3258 let isExtended = 1, hasSideEffects = 0 in
3259 multiclass LD_Abs<string mnemonic, string CextOp, RegisterClass RC> {
3260 let CextOpcode = CextOp, BaseOpcode = CextOp#_abs in {
3261 let opExtendable = 1, isPredicable = 1 in
3262 def NAME#_V4 : LDInst2<(outs RC:$dst),
3263 (ins u0AlwaysExt:$absaddr),
3264 "$dst = "#mnemonic#"(##$absaddr)",
3268 let opExtendable = 2, isPredicated = 1 in {
3269 defm Pt_V4 : LD_Abs_Pred<mnemonic, RC, 0>;
3270 defm NotPt_V4 : LD_Abs_Pred<mnemonic, RC, 1>;
3275 let addrMode = Absolute in {
3276 let accessSize = ByteAccess in {
3277 defm LDrib_abs : LD_Abs<"memb", "LDrib", IntRegs>, AddrModeRel;
3278 defm LDriub_abs : LD_Abs<"memub", "LDriub", IntRegs>, AddrModeRel;
3280 let accessSize = HalfWordAccess in {
3281 defm LDrih_abs : LD_Abs<"memh", "LDrih", IntRegs>, AddrModeRel;
3282 defm LDriuh_abs : LD_Abs<"memuh", "LDriuh", IntRegs>, AddrModeRel;
3284 let accessSize = WordAccess in
3285 defm LDriw_abs : LD_Abs<"memw", "LDriw", IntRegs>, AddrModeRel;
3287 let accessSize = DoubleWordAccess in
3288 defm LDrid_abs : LD_Abs<"memd", "LDrid", DoubleRegs>, AddrModeRel;
3291 let Predicates = [HasV4T], AddedComplexity = 30 in {
3292 def : Pat<(i32 (load (HexagonCONST32 tglobaladdr:$absaddr))),
3293 (LDriw_abs_V4 tglobaladdr: $absaddr)>;
3295 def : Pat<(i32 (sextloadi8 (HexagonCONST32 tglobaladdr:$absaddr))),
3296 (LDrib_abs_V4 tglobaladdr:$absaddr)>;
3298 def : Pat<(i32 (zextloadi8 (HexagonCONST32 tglobaladdr:$absaddr))),
3299 (LDriub_abs_V4 tglobaladdr:$absaddr)>;
3301 def : Pat<(i32 (sextloadi16 (HexagonCONST32 tglobaladdr:$absaddr))),
3302 (LDrih_abs_V4 tglobaladdr:$absaddr)>;
3304 def : Pat<(i32 (zextloadi16 (HexagonCONST32 tglobaladdr:$absaddr))),
3305 (LDriuh_abs_V4 tglobaladdr:$absaddr)>;
3308 //===----------------------------------------------------------------------===//
3309 // multiclass for load instructions with GP-relative addressing mode.
3310 // Rx=mem[bhwd](##global)
3311 // if ([!]Pv[.new]) Rx=mem[bhwd](##global)
3312 //===----------------------------------------------------------------------===//
3313 let hasSideEffects = 0, validSubTargets = HasV4SubT in
3314 multiclass LD_GP<string mnemonic, string BaseOp, RegisterClass RC> {
3315 let BaseOpcode = BaseOp in {
3316 let isPredicable = 1 in
3317 def NAME#_V4 : LDInst2<(outs RC:$dst),
3318 (ins globaladdress:$global),
3319 "$dst = "#mnemonic#"(#$global)",
3322 let isExtended = 1, opExtendable = 2, isPredicated = 1 in {
3323 defm Pt_V4 : LD_Abs_Pred<mnemonic, RC, 0>;
3324 defm NotPt_V4 : LD_Abs_Pred<mnemonic, RC, 1>;
3329 defm LDd_GP : LD_GP<"memd", "LDd_GP", DoubleRegs>, PredNewRel;
3330 defm LDb_GP : LD_GP<"memb", "LDb_GP", IntRegs>, PredNewRel;
3331 defm LDub_GP : LD_GP<"memub", "LDub_GP", IntRegs>, PredNewRel;
3332 defm LDh_GP : LD_GP<"memh", "LDh_GP", IntRegs>, PredNewRel;
3333 defm LDuh_GP : LD_GP<"memuh", "LDuh_GP", IntRegs>, PredNewRel;
3334 defm LDw_GP : LD_GP<"memw", "LDw_GP", IntRegs>, PredNewRel;
3336 def : Pat <(atomic_load_64 (HexagonCONST32_GP tglobaladdr:$global)),
3337 (i64 (LDd_GP_V4 tglobaladdr:$global))>;
3339 def : Pat <(atomic_load_32 (HexagonCONST32_GP tglobaladdr:$global)),
3340 (i32 (LDw_GP_V4 tglobaladdr:$global))>;
3342 def : Pat <(atomic_load_16 (HexagonCONST32_GP tglobaladdr:$global)),
3343 (i32 (LDuh_GP_V4 tglobaladdr:$global))>;
3345 def : Pat <(atomic_load_8 (HexagonCONST32_GP tglobaladdr:$global)),
3346 (i32 (LDub_GP_V4 tglobaladdr:$global))>;
3348 // Map from load(globaladdress) -> memw(#foo + 0)
3349 let AddedComplexity = 100 in
3350 def : Pat <(i64 (load (HexagonCONST32_GP tglobaladdr:$global))),
3351 (i64 (LDd_GP_V4 tglobaladdr:$global))>;
3353 // Map from Pd = load(globaladdress) -> Rd = memb(globaladdress), Pd = Rd
3354 let AddedComplexity = 100 in
3355 def : Pat <(i1 (load (HexagonCONST32_GP tglobaladdr:$global))),
3356 (i1 (C2_tfrrp (i32 (LDb_GP_V4 tglobaladdr:$global))))>;
3358 // When the Interprocedural Global Variable optimizer realizes that a certain
3359 // global variable takes only two constant values, it shrinks the global to
3360 // a boolean. Catch those loads here in the following 3 patterns.
3361 let AddedComplexity = 100 in
3362 def : Pat <(i32 (extloadi1 (HexagonCONST32_GP tglobaladdr:$global))),
3363 (i32 (LDb_GP_V4 tglobaladdr:$global))>;
3365 let AddedComplexity = 100 in
3366 def : Pat <(i32 (sextloadi1 (HexagonCONST32_GP tglobaladdr:$global))),
3367 (i32 (LDb_GP_V4 tglobaladdr:$global))>;
3369 // Map from load(globaladdress) -> memb(#foo)
3370 let AddedComplexity = 100 in
3371 def : Pat <(i32 (extloadi8 (HexagonCONST32_GP tglobaladdr:$global))),
3372 (i32 (LDb_GP_V4 tglobaladdr:$global))>;
3374 // Map from load(globaladdress) -> memb(#foo)
3375 let AddedComplexity = 100 in
3376 def : Pat <(i32 (sextloadi8 (HexagonCONST32_GP tglobaladdr:$global))),
3377 (i32 (LDb_GP_V4 tglobaladdr:$global))>;
3379 let AddedComplexity = 100 in
3380 def : Pat <(i32 (zextloadi1 (HexagonCONST32_GP tglobaladdr:$global))),
3381 (i32 (LDub_GP_V4 tglobaladdr:$global))>;
3383 // Map from load(globaladdress) -> memub(#foo)
3384 let AddedComplexity = 100 in
3385 def : Pat <(i32 (zextloadi8 (HexagonCONST32_GP tglobaladdr:$global))),
3386 (i32 (LDub_GP_V4 tglobaladdr:$global))>;
3388 // Map from load(globaladdress) -> memh(#foo)
3389 let AddedComplexity = 100 in
3390 def : Pat <(i32 (extloadi16 (HexagonCONST32_GP tglobaladdr:$global))),
3391 (i32 (LDh_GP_V4 tglobaladdr:$global))>;
3393 // Map from load(globaladdress) -> memh(#foo)
3394 let AddedComplexity = 100 in
3395 def : Pat <(i32 (sextloadi16 (HexagonCONST32_GP tglobaladdr:$global))),
3396 (i32 (LDh_GP_V4 tglobaladdr:$global))>;
3398 // Map from load(globaladdress) -> memuh(#foo)
3399 let AddedComplexity = 100 in
3400 def : Pat <(i32 (zextloadi16 (HexagonCONST32_GP tglobaladdr:$global))),
3401 (i32 (LDuh_GP_V4 tglobaladdr:$global))>;
3403 // Map from load(globaladdress) -> memw(#foo)
3404 let AddedComplexity = 100 in
3405 def : Pat <(i32 (load (HexagonCONST32_GP tglobaladdr:$global))),
3406 (i32 (LDw_GP_V4 tglobaladdr:$global))>;
3409 // Transfer global address into a register
3410 let isExtended = 1, opExtendable = 1, AddedComplexity=50, isMoveImm = 1,
3411 isAsCheapAsAMove = 1, isReMaterializable = 1, validSubTargets = HasV4SubT in
3412 def TFRI_V4 : ALU32_ri<(outs IntRegs:$dst), (ins s16Ext:$src1),
3414 [(set IntRegs:$dst, (HexagonCONST32 tglobaladdr:$src1))]>,
3417 // Transfer a block address into a register
3418 def : Pat<(HexagonCONST32_GP tblockaddress:$src1),
3419 (TFRI_V4 tblockaddress:$src1)>,
3422 let isExtended = 1, opExtendable = 2, AddedComplexity=50,
3423 hasSideEffects = 0, isPredicated = 1, validSubTargets = HasV4SubT in
3424 def TFRI_cPt_V4 : ALU32_ri<(outs IntRegs:$dst),
3425 (ins PredRegs:$src1, s16Ext:$src2),
3426 "if($src1) $dst = #$src2",
3430 let isExtended = 1, opExtendable = 2, AddedComplexity=50, isPredicatedFalse = 1,
3431 hasSideEffects = 0, isPredicated = 1, validSubTargets = HasV4SubT in
3432 def TFRI_cNotPt_V4 : ALU32_ri<(outs IntRegs:$dst),
3433 (ins PredRegs:$src1, s16Ext:$src2),
3434 "if(!$src1) $dst = #$src2",
3438 let isExtended = 1, opExtendable = 2, AddedComplexity=50,
3439 hasSideEffects = 0, isPredicated = 1, validSubTargets = HasV4SubT in
3440 def TFRI_cdnPt_V4 : ALU32_ri<(outs IntRegs:$dst),
3441 (ins PredRegs:$src1, s16Ext:$src2),
3442 "if($src1.new) $dst = #$src2",
3446 let isExtended = 1, opExtendable = 2, AddedComplexity=50, isPredicatedFalse = 1,
3447 hasSideEffects = 0, isPredicated = 1, validSubTargets = HasV4SubT in
3448 def TFRI_cdnNotPt_V4 : ALU32_ri<(outs IntRegs:$dst),
3449 (ins PredRegs:$src1, s16Ext:$src2),
3450 "if(!$src1.new) $dst = #$src2",
3454 let AddedComplexity = 50, Predicates = [HasV4T] in
3455 def : Pat<(HexagonCONST32_GP tglobaladdr:$src1),
3456 (TFRI_V4 tglobaladdr:$src1)>,
3460 // Load - Indirect with long offset: These instructions take global address
3462 let isExtended = 1, opExtendable = 3, AddedComplexity = 40,
3463 validSubTargets = HasV4SubT in
3464 def LDrid_ind_lo_V4 : LDInst<(outs DoubleRegs:$dst),
3465 (ins IntRegs:$src1, u2Imm:$src2, globaladdressExt:$offset),
3466 "$dst=memd($src1<<#$src2+##$offset)",
3467 [(set (i64 DoubleRegs:$dst),
3468 (load (add (shl IntRegs:$src1, u2ImmPred:$src2),
3469 (HexagonCONST32 tglobaladdr:$offset))))]>,
3472 let AddedComplexity = 40 in
3473 multiclass LD_indirect_lo<string OpcStr, PatFrag OpNode> {
3474 let isExtended = 1, opExtendable = 3, validSubTargets = HasV4SubT in
3475 def _lo_V4 : LDInst<(outs IntRegs:$dst),
3476 (ins IntRegs:$src1, u2Imm:$src2, globaladdressExt:$offset),
3477 !strconcat("$dst = ",
3478 !strconcat(OpcStr, "($src1<<#$src2+##$offset)")),
3480 (i32 (OpNode (add (shl IntRegs:$src1, u2ImmPred:$src2),
3481 (HexagonCONST32 tglobaladdr:$offset)))))]>,
3485 defm LDrib_ind : LD_indirect_lo<"memb", sextloadi8>;
3486 defm LDriub_ind : LD_indirect_lo<"memub", zextloadi8>;
3487 defm LDriub_ind_anyext : LD_indirect_lo<"memub", extloadi8>;
3488 defm LDrih_ind : LD_indirect_lo<"memh", sextloadi16>;
3489 defm LDriuh_ind : LD_indirect_lo<"memuh", zextloadi16>;
3490 defm LDriuh_ind_anyext : LD_indirect_lo<"memuh", extloadi16>;
3491 defm LDriw_ind : LD_indirect_lo<"memw", load>;
3493 let AddedComplexity = 40 in
3494 def : Pat <(i32 (sextloadi8 (add IntRegs:$src1,
3495 (NumUsesBelowThresCONST32 tglobaladdr:$offset)))),
3496 (i32 (LDrib_ind_lo_V4 IntRegs:$src1, 0, tglobaladdr:$offset))>,
3499 let AddedComplexity = 40 in
3500 def : Pat <(i32 (zextloadi8 (add IntRegs:$src1,
3501 (NumUsesBelowThresCONST32 tglobaladdr:$offset)))),
3502 (i32 (LDriub_ind_lo_V4 IntRegs:$src1, 0, tglobaladdr:$offset))>,
3505 let Predicates = [HasV4T], AddedComplexity = 30 in {
3506 def : Pat<(truncstorei8 (i32 IntRegs:$src1), u0AlwaysExtPred:$src2),
3507 (STrib_abs_V4 u0AlwaysExtPred:$src2, IntRegs: $src1)>;
3509 def : Pat<(truncstorei16 (i32 IntRegs:$src1), u0AlwaysExtPred:$src2),
3510 (STrih_abs_V4 u0AlwaysExtPred:$src2, IntRegs: $src1)>;
3512 def : Pat<(store (i32 IntRegs:$src1), u0AlwaysExtPred:$src2),
3513 (STriw_abs_V4 u0AlwaysExtPred:$src2, IntRegs: $src1)>;
3516 let Predicates = [HasV4T], AddedComplexity = 30 in {
3517 def : Pat<(i32 (load u0AlwaysExtPred:$src)),
3518 (LDriw_abs_V4 u0AlwaysExtPred:$src)>;
3520 def : Pat<(i32 (sextloadi8 u0AlwaysExtPred:$src)),
3521 (LDrib_abs_V4 u0AlwaysExtPred:$src)>;
3523 def : Pat<(i32 (zextloadi8 u0AlwaysExtPred:$src)),
3524 (LDriub_abs_V4 u0AlwaysExtPred:$src)>;
3526 def : Pat<(i32 (sextloadi16 u0AlwaysExtPred:$src)),
3527 (LDrih_abs_V4 u0AlwaysExtPred:$src)>;
3529 def : Pat<(i32 (zextloadi16 u0AlwaysExtPred:$src)),
3530 (LDriuh_abs_V4 u0AlwaysExtPred:$src)>;
3533 // Indexed store word - global address.
3534 // memw(Rs+#u6:2)=#S8
3535 let AddedComplexity = 10 in
3536 def STriw_offset_ext_V4 : STInst<(outs),
3537 (ins IntRegs:$src1, u6_2Imm:$src2, globaladdress:$src3),
3538 "memw($src1+#$src2) = ##$src3",
3539 [(store (HexagonCONST32 tglobaladdr:$src3),
3540 (add IntRegs:$src1, u6_2ImmPred:$src2))]>,
3543 def : Pat<(i64 (ctlz (i64 DoubleRegs:$src1))),
3544 (i64 (A4_combineir (i32 0), (i32 (CTLZ64_rr DoubleRegs:$src1))))>,
3547 def : Pat<(i64 (cttz (i64 DoubleRegs:$src1))),
3548 (i64 (A4_combineir (i32 0), (i32 (CTTZ64_rr DoubleRegs:$src1))))>,
3553 // We need a complexity of 120 here to override preceding handling of
3555 let Predicates = [HasV4T], AddedComplexity = 120 in {
3556 def: Pat <(i64 (extloadi8 (NumUsesBelowThresCONST32 tglobaladdr:$addr))),
3557 (i64 (A4_combineir 0, (LDrib_abs_V4 tglobaladdr:$addr)))>;
3559 def: Pat <(i64 (zextloadi8 (NumUsesBelowThresCONST32 tglobaladdr:$addr))),
3560 (i64 (A4_combineir 0, (LDriub_abs_V4 tglobaladdr:$addr)))>;
3562 def: Pat <(i64 (sextloadi8 (NumUsesBelowThresCONST32 tglobaladdr:$addr))),
3563 (i64 (A2_sxtw (LDrib_abs_V4 tglobaladdr:$addr)))>;
3565 def: Pat <(i64 (extloadi8 FoldGlobalAddr:$addr)),
3566 (i64 (A4_combineir 0, (LDrib_abs_V4 FoldGlobalAddr:$addr)))>;
3568 def: Pat <(i64 (zextloadi8 FoldGlobalAddr:$addr)),
3569 (i64 (A4_combineir 0, (LDriub_abs_V4 FoldGlobalAddr:$addr)))>;
3571 def: Pat <(i64 (sextloadi8 FoldGlobalAddr:$addr)),
3572 (i64 (A2_sxtw (LDrib_abs_V4 FoldGlobalAddr:$addr)))>;
3575 // We need a complexity of 120 here to override preceding handling of
3577 let AddedComplexity = 120 in {
3578 def: Pat <(i64 (extloadi16 (NumUsesBelowThresCONST32 tglobaladdr:$addr))),
3579 (i64 (A4_combineir 0, (LDrih_abs_V4 tglobaladdr:$addr)))>,
3582 def: Pat <(i64 (zextloadi16 (NumUsesBelowThresCONST32 tglobaladdr:$addr))),
3583 (i64 (A4_combineir 0, (LDriuh_abs_V4 tglobaladdr:$addr)))>,
3586 def: Pat <(i64 (sextloadi16 (NumUsesBelowThresCONST32 tglobaladdr:$addr))),
3587 (i64 (A2_sxtw (LDrih_abs_V4 tglobaladdr:$addr)))>,
3590 def: Pat <(i64 (extloadi16 FoldGlobalAddr:$addr)),
3591 (i64 (A4_combineir 0, (LDrih_abs_V4 FoldGlobalAddr:$addr)))>,
3594 def: Pat <(i64 (zextloadi16 FoldGlobalAddr:$addr)),
3595 (i64 (A4_combineir 0, (LDriuh_abs_V4 FoldGlobalAddr:$addr)))>,
3598 def: Pat <(i64 (sextloadi16 FoldGlobalAddr:$addr)),
3599 (i64 (A2_sxtw (LDrih_abs_V4 FoldGlobalAddr:$addr)))>,
3603 // We need a complexity of 120 here to override preceding handling of
3605 let AddedComplexity = 120 in {
3606 def: Pat <(i64 (extloadi32 (NumUsesBelowThresCONST32 tglobaladdr:$addr))),
3607 (i64 (A4_combineir 0, (LDriw_abs_V4 tglobaladdr:$addr)))>,
3610 def: Pat <(i64 (zextloadi32 (NumUsesBelowThresCONST32 tglobaladdr:$addr))),
3611 (i64 (A4_combineir 0, (LDriw_abs_V4 tglobaladdr:$addr)))>,
3614 def: Pat <(i64 (sextloadi32 (NumUsesBelowThresCONST32 tglobaladdr:$addr))),
3615 (i64 (A2_sxtw (LDriw_abs_V4 tglobaladdr:$addr)))>,
3618 def: Pat <(i64 (extloadi32 FoldGlobalAddr:$addr)),
3619 (i64 (A4_combineir 0, (LDriw_abs_V4 FoldGlobalAddr:$addr)))>,
3622 def: Pat <(i64 (zextloadi32 FoldGlobalAddr:$addr)),
3623 (i64 (A4_combineir 0, (LDriw_abs_V4 FoldGlobalAddr:$addr)))>,
3626 def: Pat <(i64 (sextloadi32 FoldGlobalAddr:$addr)),
3627 (i64 (A2_sxtw (LDriw_abs_V4 FoldGlobalAddr:$addr)))>,
3631 // Indexed store double word - global address.
3632 // memw(Rs+#u6:2)=#S8
3633 let AddedComplexity = 10 in
3634 def STrih_offset_ext_V4 : STInst<(outs),
3635 (ins IntRegs:$src1, u6_1Imm:$src2, globaladdress:$src3),
3636 "memh($src1+#$src2) = ##$src3",
3637 [(truncstorei16 (HexagonCONST32 tglobaladdr:$src3),
3638 (add IntRegs:$src1, u6_1ImmPred:$src2))]>,
3640 // Map from store(globaladdress + x) -> memd(#foo + x)
3641 let AddedComplexity = 100 in
3642 def : Pat<(store (i64 DoubleRegs:$src1),
3643 FoldGlobalAddrGP:$addr),
3644 (STrid_abs_V4 FoldGlobalAddrGP:$addr, (i64 DoubleRegs:$src1))>,
3647 def : Pat<(atomic_store_64 FoldGlobalAddrGP:$addr,
3648 (i64 DoubleRegs:$src1)),
3649 (STrid_abs_V4 FoldGlobalAddrGP:$addr, (i64 DoubleRegs:$src1))>,
3652 // Map from store(globaladdress + x) -> memb(#foo + x)
3653 let AddedComplexity = 100 in
3654 def : Pat<(truncstorei8 (i32 IntRegs:$src1), FoldGlobalAddrGP:$addr),
3655 (STrib_abs_V4 FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1))>,
3658 def : Pat<(atomic_store_8 FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1)),
3659 (STrib_abs_V4 FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1))>,
3662 // Map from store(globaladdress + x) -> memh(#foo + x)
3663 let AddedComplexity = 100 in
3664 def : Pat<(truncstorei16 (i32 IntRegs:$src1), FoldGlobalAddrGP:$addr),
3665 (STrih_abs_V4 FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1))>,
3668 def : Pat<(atomic_store_16 FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1)),
3669 (STrih_abs_V4 FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1))>,
3672 // Map from store(globaladdress + x) -> memw(#foo + x)
3673 let AddedComplexity = 100 in
3674 def : Pat<(store (i32 IntRegs:$src1), FoldGlobalAddrGP:$addr),
3675 (STriw_abs_V4 FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1))>,
3678 def : Pat<(atomic_store_32 FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1)),
3679 (STriw_abs_V4 FoldGlobalAddrGP:$addr, (i32 IntRegs:$src1))>,
3682 // Map from load(globaladdress + x) -> memd(#foo + x)
3683 let AddedComplexity = 100 in
3684 def : Pat<(i64 (load FoldGlobalAddrGP:$addr)),
3685 (i64 (LDrid_abs_V4 FoldGlobalAddrGP:$addr))>,
3688 def : Pat<(atomic_load_64 FoldGlobalAddrGP:$addr),
3689 (i64 (LDrid_abs_V4 FoldGlobalAddrGP:$addr))>,
3692 // Map from load(globaladdress + x) -> memb(#foo + x)
3693 let AddedComplexity = 100 in
3694 def : Pat<(i32 (extloadi8 FoldGlobalAddrGP:$addr)),
3695 (i32 (LDrib_abs_V4 FoldGlobalAddrGP:$addr))>,
3698 // Map from load(globaladdress + x) -> memb(#foo + x)
3699 let AddedComplexity = 100 in
3700 def : Pat<(i32 (sextloadi8 FoldGlobalAddrGP:$addr)),
3701 (i32 (LDrib_abs_V4 FoldGlobalAddrGP:$addr))>,
3704 //let AddedComplexity = 100 in
3705 let AddedComplexity = 100 in
3706 def : Pat<(i32 (extloadi16 FoldGlobalAddrGP:$addr)),
3707 (i32 (LDrih_abs_V4 FoldGlobalAddrGP:$addr))>,
3710 // Map from load(globaladdress + x) -> memh(#foo + x)
3711 let AddedComplexity = 100 in
3712 def : Pat<(i32 (sextloadi16 FoldGlobalAddrGP:$addr)),
3713 (i32 (LDrih_abs_V4 FoldGlobalAddrGP:$addr))>,
3716 // Map from load(globaladdress + x) -> memuh(#foo + x)
3717 let AddedComplexity = 100 in
3718 def : Pat<(i32 (zextloadi16 FoldGlobalAddrGP:$addr)),
3719 (i32 (LDriuh_abs_V4 FoldGlobalAddrGP:$addr))>,
3722 def : Pat<(atomic_load_16 FoldGlobalAddrGP:$addr),
3723 (i32 (LDriuh_abs_V4 FoldGlobalAddrGP:$addr))>,
3726 // Map from load(globaladdress + x) -> memub(#foo + x)
3727 let AddedComplexity = 100 in
3728 def : Pat<(i32 (zextloadi8 FoldGlobalAddrGP:$addr)),
3729 (i32 (LDriub_abs_V4 FoldGlobalAddrGP:$addr))>,
3732 def : Pat<(atomic_load_8 FoldGlobalAddrGP:$addr),
3733 (i32 (LDriub_abs_V4 FoldGlobalAddrGP:$addr))>,
3736 // Map from load(globaladdress + x) -> memw(#foo + x)
3737 let AddedComplexity = 100 in
3738 def : Pat<(i32 (load FoldGlobalAddrGP:$addr)),
3739 (i32 (LDriw_abs_V4 FoldGlobalAddrGP:$addr))>,
3742 def : Pat<(atomic_load_32 FoldGlobalAddrGP:$addr),
3743 (i32 (LDriw_abs_V4 FoldGlobalAddrGP:$addr))>,