1 //=- HexagonInstrInfoV3.td - Target Desc. for Hexagon Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Hexagon V3 instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 def callv3 : SDNode<"HexagonISD::CALLv3", SDT_SPCall,
15 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, SDNPVariadic]>;
17 def callv3nr : SDNode<"HexagonISD::CALLv3nr", SDT_SPCall,
18 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, SDNPVariadic]>;
20 //===----------------------------------------------------------------------===//
22 //===----------------------------------------------------------------------===//
24 let isCall = 1, hasSideEffects = 1, validSubTargets = HasV3SubT,
25 Defs = VolatileV3.Regs, isPredicable = 1,
26 isExtended = 0, isExtendable = 1, opExtendable = 0,
27 isExtentSigned = 1, opExtentBits = 24, opExtentAlign = 2 in
28 class T_Call<string ExtStr>
29 : JInst<(outs), (ins calltarget:$dst),
30 "call " # ExtStr # "$dst", [], "", J_tc_2early_SLOT23> {
31 let BaseOpcode = "call";
35 let Inst{27-25} = 0b101;
36 let Inst{24-16,13-1} = dst{23-2};
40 let isCall = 1, hasSideEffects = 1, validSubTargets = HasV3SubT,
41 Defs = VolatileV3.Regs, isPredicated = 1,
42 isExtended = 0, isExtendable = 1, opExtendable = 1,
43 isExtentSigned = 1, opExtentBits = 17, opExtentAlign = 2 in
44 class T_CallPred<bit IfTrue, string ExtStr>
45 : JInst<(outs), (ins PredRegs:$Pu, calltarget:$dst),
46 CondStr<"$Pu", IfTrue, 0>.S # "call " # ExtStr # "$dst",
47 [], "", J_tc_2early_SLOT23> {
48 let BaseOpcode = "call";
49 let isPredicatedFalse = !if(IfTrue,0,1);
54 let Inst{27-24} = 0b1101;
55 let Inst{23-22,20-16,13,7-1} = dst{16-2};
56 let Inst{21} = !if(IfTrue,0,1);
61 multiclass T_Calls<string ExtStr> {
62 def NAME : T_Call<ExtStr>;
63 def t : T_CallPred<1, ExtStr>;
64 def f : T_CallPred<0, ExtStr>;
67 let isCodeGenOnly = 0 in
68 defm J2_call: T_Calls<"">, PredRel;
70 //===----------------------------------------------------------------------===//
72 //===----------------------------------------------------------------------===//
75 //===----------------------------------------------------------------------===//
77 //===----------------------------------------------------------------------===//
78 // Call subroutine from register.
79 let isCall = 1, hasSideEffects = 0,
80 Defs = [D0, D1, D2, D3, D4, D5, D6, D7, R28, R31,
81 P0, P1, P2, P3, LC0, LC1, SA0, SA1] in {
82 def CALLRv3 : JRInst<(outs), (ins IntRegs:$dst),
84 []>, Requires<[HasV3TOnly]>;
87 //===----------------------------------------------------------------------===//
89 //===----------------------------------------------------------------------===//
91 //===----------------------------------------------------------------------===//
93 //===----------------------------------------------------------------------===//
95 let AddedComplexity = 200 in
96 def MAXw_dd : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
98 "$dst = max($src2, $src1)",
99 [(set (i64 DoubleRegs:$dst),
100 (i64 (select (i1 (setlt (i64 DoubleRegs:$src2),
101 (i64 DoubleRegs:$src1))),
102 (i64 DoubleRegs:$src1),
103 (i64 DoubleRegs:$src2))))]>,
106 let AddedComplexity = 200 in
107 def MINw_dd : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
109 "$dst = min($src2, $src1)",
110 [(set (i64 DoubleRegs:$dst),
111 (i64 (select (i1 (setgt (i64 DoubleRegs:$src2),
112 (i64 DoubleRegs:$src1))),
113 (i64 DoubleRegs:$src1),
114 (i64 DoubleRegs:$src2))))]>,
117 //===----------------------------------------------------------------------===//
119 //===----------------------------------------------------------------------===//
124 //def : Pat <(brcond (i1 (seteq (i32 IntRegs:$src1), 0)), bb:$offset),
125 // (JMP_RegEzt (i32 IntRegs:$src1), bb:$offset)>, Requires<[HasV3T]>;
127 //def : Pat <(brcond (i1 (setne (i32 IntRegs:$src1), 0)), bb:$offset),
128 // (JMP_RegNzt (i32 IntRegs:$src1), bb:$offset)>, Requires<[HasV3T]>;
130 //def : Pat <(brcond (i1 (setle (i32 IntRegs:$src1), 0)), bb:$offset),
131 // (JMP_RegLezt (i32 IntRegs:$src1), bb:$offset)>, Requires<[HasV3T]>;
133 //def : Pat <(brcond (i1 (setge (i32 IntRegs:$src1), 0)), bb:$offset),
134 // (JMP_RegGezt (i32 IntRegs:$src1), bb:$offset)>, Requires<[HasV3T]>;
136 //def : Pat <(brcond (i1 (setgt (i32 IntRegs:$src1), -1)), bb:$offset),
137 // (JMP_RegGezt (i32 IntRegs:$src1), bb:$offset)>, Requires<[HasV3T]>;
140 // Map call instruction
141 def : Pat<(call (i32 IntRegs:$dst)),
142 (J2_call (i32 IntRegs:$dst))>, Requires<[HasV3T]>;
143 def : Pat<(call tglobaladdr:$dst),
144 (J2_call tglobaladdr:$dst)>, Requires<[HasV3T]>;
145 def : Pat<(call texternalsym:$dst),
146 (J2_call texternalsym:$dst)>, Requires<[HasV3T]>;