1 //==- HexagonInstrInfo.td - Target Description for Hexagon -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Hexagon instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 include "HexagonInstrFormats.td"
15 include "HexagonOperands.td"
17 // Pattern fragment that combines the value type and the register class
18 // into a single parameter.
19 // The pat frags in the definitions below need to have a named register,
20 // otherwise i32 will be assumed regardless of the register class. The
21 // name of the register does not matter.
22 def I1 : PatLeaf<(i1 PredRegs:$R)>;
23 def I32 : PatLeaf<(i32 IntRegs:$R)>;
24 def I64 : PatLeaf<(i64 DoubleRegs:$R)>;
25 def F32 : PatLeaf<(f32 IntRegs:$R)>;
26 def F64 : PatLeaf<(f64 DoubleRegs:$R)>;
28 // Pattern fragments to extract the low and high subregisters from a
30 def LoReg: OutPatFrag<(ops node:$Rs),
31 (EXTRACT_SUBREG (i64 $Rs), subreg_loreg)>;
32 def HiReg: OutPatFrag<(ops node:$Rs),
33 (EXTRACT_SUBREG (i64 $Rs), subreg_hireg)>;
35 // SDNode for converting immediate C to C-1.
36 def DEC_CONST_SIGNED : SDNodeXForm<imm, [{
37 // Return the byte immediate const-1 as an SDNode.
38 int32_t imm = N->getSExtValue();
39 return XformSToSM1Imm(imm);
42 // SDNode for converting immediate C to C-2.
43 def DEC2_CONST_SIGNED : SDNodeXForm<imm, [{
44 // Return the byte immediate const-2 as an SDNode.
45 int32_t imm = N->getSExtValue();
46 return XformSToSM2Imm(imm);
49 // SDNode for converting immediate C to C-3.
50 def DEC3_CONST_SIGNED : SDNodeXForm<imm, [{
51 // Return the byte immediate const-3 as an SDNode.
52 int32_t imm = N->getSExtValue();
53 return XformSToSM3Imm(imm);
56 // SDNode for converting immediate C to C-1.
57 def DEC_CONST_UNSIGNED : SDNodeXForm<imm, [{
58 // Return the byte immediate const-1 as an SDNode.
59 uint32_t imm = N->getZExtValue();
60 return XformUToUM1Imm(imm);
63 //===----------------------------------------------------------------------===//
65 //===----------------------------------------------------------------------===//
67 //===----------------------------------------------------------------------===//
68 let hasSideEffects = 0, isCompare = 1, InputType = "imm", isExtendable = 1,
70 class T_CMP <string mnemonic, bits<2> MajOp, bit isNot, Operand ImmOp>
71 : ALU32Inst <(outs PredRegs:$dst),
72 (ins IntRegs:$src1, ImmOp:$src2),
73 "$dst = "#!if(isNot, "!","")#mnemonic#"($src1, #$src2)",
74 [], "",ALU32_2op_tc_2early_SLOT0123 >, ImmRegRel {
78 let CextOpcode = mnemonic;
79 let opExtentBits = !if(!eq(mnemonic, "cmp.gtu"), 9, 10);
80 let isExtentSigned = !if(!eq(mnemonic, "cmp.gtu"), 0, 1);
84 let Inst{27-24} = 0b0101;
85 let Inst{23-22} = MajOp;
86 let Inst{21} = !if(!eq(mnemonic, "cmp.gtu"), 0, src2{9});
87 let Inst{20-16} = src1;
88 let Inst{13-5} = src2{8-0};
94 def C2_cmpeqi : T_CMP <"cmp.eq", 0b00, 0, s10Ext>;
95 def C2_cmpgti : T_CMP <"cmp.gt", 0b01, 0, s10Ext>;
96 def C2_cmpgtui : T_CMP <"cmp.gtu", 0b10, 0, u9Ext>;
98 class T_CMP_pat <InstHexagon MI, PatFrag OpNode, PatLeaf ImmPred>
99 : Pat<(i1 (OpNode (i32 IntRegs:$src1), ImmPred:$src2)),
100 (MI IntRegs:$src1, ImmPred:$src2)>;
102 def : T_CMP_pat <C2_cmpeqi, seteq, s10ImmPred>;
103 def : T_CMP_pat <C2_cmpgti, setgt, s10ImmPred>;
104 def : T_CMP_pat <C2_cmpgtui, setugt, u9ImmPred>;
106 //===----------------------------------------------------------------------===//
108 //===----------------------------------------------------------------------===//
109 def SDTHexagonI64I32I32 : SDTypeProfile<1, 2,
110 [SDTCisVT<0, i64>, SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
112 def HexagonCOMBINE : SDNode<"HexagonISD::COMBINE", SDTHexagonI64I32I32>;
114 let hasSideEffects = 0, hasNewValue = 1, InputType = "reg" in
115 class T_ALU32_3op<string mnemonic, bits<3> MajOp, bits<3> MinOp, bit OpsRev,
117 : ALU32_rr<(outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt),
118 "$Rd = "#mnemonic#"($Rs, $Rt)",
119 [], "", ALU32_3op_tc_1_SLOT0123>, ImmRegRel, PredRel {
120 let isCommutable = IsComm;
121 let BaseOpcode = mnemonic#_rr;
122 let CextOpcode = mnemonic;
130 let Inst{26-24} = MajOp;
131 let Inst{23-21} = MinOp;
132 let Inst{20-16} = !if(OpsRev,Rt,Rs);
133 let Inst{12-8} = !if(OpsRev,Rs,Rt);
137 let hasSideEffects = 0, hasNewValue = 1 in
138 class T_ALU32_3op_pred<string mnemonic, bits<3> MajOp, bits<3> MinOp,
139 bit OpsRev, bit PredNot, bit PredNew>
140 : ALU32_rr<(outs IntRegs:$Rd), (ins PredRegs:$Pu, IntRegs:$Rs, IntRegs:$Rt),
141 "if ("#!if(PredNot,"!","")#"$Pu"#!if(PredNew,".new","")#") "#
142 "$Rd = "#mnemonic#"($Rs, $Rt)",
143 [], "", ALU32_3op_tc_1_SLOT0123>, ImmRegRel, PredNewRel {
144 let isPredicated = 1;
145 let isPredicatedFalse = PredNot;
146 let isPredicatedNew = PredNew;
147 let BaseOpcode = mnemonic#_rr;
148 let CextOpcode = mnemonic;
157 let Inst{26-24} = MajOp;
158 let Inst{23-21} = MinOp;
159 let Inst{20-16} = !if(OpsRev,Rt,Rs);
160 let Inst{13} = PredNew;
161 let Inst{12-8} = !if(OpsRev,Rs,Rt);
162 let Inst{7} = PredNot;
167 class T_ALU32_combineh<string Op1, string Op2, bits<3> MajOp, bits<3> MinOp,
169 : T_ALU32_3op<"", MajOp, MinOp, OpsRev, 0> {
170 let AsmString = "$Rd = combine($Rs"#Op1#", $Rt"#Op2#")";
173 let isCodeGenOnly = 0 in {
174 def A2_combine_hh : T_ALU32_combineh<".h", ".h", 0b011, 0b100, 1>;
175 def A2_combine_hl : T_ALU32_combineh<".h", ".l", 0b011, 0b101, 1>;
176 def A2_combine_lh : T_ALU32_combineh<".l", ".h", 0b011, 0b110, 1>;
177 def A2_combine_ll : T_ALU32_combineh<".l", ".l", 0b011, 0b111, 1>;
180 class T_ALU32_3op_sfx<string mnemonic, string suffix, bits<3> MajOp,
181 bits<3> MinOp, bit OpsRev, bit IsComm>
182 : T_ALU32_3op<"", MajOp, MinOp, OpsRev, IsComm> {
183 let AsmString = "$Rd = "#mnemonic#"($Rs, $Rt)"#suffix;
186 let Defs = [USR_OVF], Itinerary = ALU32_3op_tc_2_SLOT0123,
187 isCodeGenOnly = 0 in {
188 def A2_addsat : T_ALU32_3op_sfx<"add", ":sat", 0b110, 0b010, 0, 1>;
189 def A2_subsat : T_ALU32_3op_sfx<"sub", ":sat", 0b110, 0b110, 1, 0>;
192 multiclass T_ALU32_3op_p<string mnemonic, bits<3> MajOp, bits<3> MinOp,
194 def t : T_ALU32_3op_pred<mnemonic, MajOp, MinOp, OpsRev, 0, 0>;
195 def f : T_ALU32_3op_pred<mnemonic, MajOp, MinOp, OpsRev, 1, 0>;
196 def tnew : T_ALU32_3op_pred<mnemonic, MajOp, MinOp, OpsRev, 0, 1>;
197 def fnew : T_ALU32_3op_pred<mnemonic, MajOp, MinOp, OpsRev, 1, 1>;
200 multiclass T_ALU32_3op_A2<string mnemonic, bits<3> MajOp, bits<3> MinOp,
201 bit OpsRev, bit IsComm> {
202 let isPredicable = 1 in
203 def A2_#NAME : T_ALU32_3op <mnemonic, MajOp, MinOp, OpsRev, IsComm>;
204 defm A2_p#NAME : T_ALU32_3op_p<mnemonic, MajOp, MinOp, OpsRev>;
207 let isCodeGenOnly = 0 in {
208 defm add : T_ALU32_3op_A2<"add", 0b011, 0b000, 0, 1>;
209 defm and : T_ALU32_3op_A2<"and", 0b001, 0b000, 0, 1>;
210 defm or : T_ALU32_3op_A2<"or", 0b001, 0b001, 0, 1>;
211 defm sub : T_ALU32_3op_A2<"sub", 0b011, 0b001, 1, 0>;
212 defm xor : T_ALU32_3op_A2<"xor", 0b001, 0b011, 0, 1>;
215 // Pats for instruction selection.
216 class BinOp32_pat<SDNode Op, InstHexagon MI, ValueType ResT>
217 : Pat<(ResT (Op (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))),
218 (ResT (MI IntRegs:$Rs, IntRegs:$Rt))>;
220 def: BinOp32_pat<add, A2_add, i32>;
221 def: BinOp32_pat<and, A2_and, i32>;
222 def: BinOp32_pat<or, A2_or, i32>;
223 def: BinOp32_pat<sub, A2_sub, i32>;
224 def: BinOp32_pat<xor, A2_xor, i32>;
226 // A few special cases producing register pairs:
227 let OutOperandList = (outs DoubleRegs:$Rd), hasNewValue = 0,
228 isCodeGenOnly = 0 in {
229 def S2_packhl : T_ALU32_3op <"packhl", 0b101, 0b100, 0, 0>;
231 let isPredicable = 1 in
232 def A2_combinew : T_ALU32_3op <"combine", 0b101, 0b000, 0, 0>;
234 // Conditional combinew uses "newt/f" instead of "t/fnew".
235 def C2_ccombinewt : T_ALU32_3op_pred<"combine", 0b101, 0b000, 0, 0, 0>;
236 def C2_ccombinewf : T_ALU32_3op_pred<"combine", 0b101, 0b000, 0, 1, 0>;
237 def C2_ccombinewnewt : T_ALU32_3op_pred<"combine", 0b101, 0b000, 0, 0, 1>;
238 def C2_ccombinewnewf : T_ALU32_3op_pred<"combine", 0b101, 0b000, 0, 1, 1>;
241 let hasSideEffects = 0, hasNewValue = 1, isCompare = 1, InputType = "reg" in
242 class T_ALU32_3op_cmp<string mnemonic, bits<2> MinOp, bit IsNeg, bit IsComm>
243 : ALU32_rr<(outs PredRegs:$Pd), (ins IntRegs:$Rs, IntRegs:$Rt),
244 "$Pd = "#mnemonic#"($Rs, $Rt)",
245 [], "", ALU32_3op_tc_1_SLOT0123>, ImmRegRel {
246 let CextOpcode = mnemonic;
247 let isCommutable = IsComm;
253 let Inst{27-24} = 0b0010;
254 let Inst{22-21} = MinOp;
255 let Inst{20-16} = Rs;
258 let Inst{3-2} = 0b00;
262 let Itinerary = ALU32_3op_tc_2early_SLOT0123, isCodeGenOnly = 0 in {
263 def C2_cmpeq : T_ALU32_3op_cmp< "cmp.eq", 0b00, 0, 1>;
264 def C2_cmpgt : T_ALU32_3op_cmp< "cmp.gt", 0b10, 0, 0>;
265 def C2_cmpgtu : T_ALU32_3op_cmp< "cmp.gtu", 0b11, 0, 0>;
268 // Patfrag to convert the usual comparison patfrags (e.g. setlt) to ones
269 // that reverse the order of the operands.
270 class RevCmp<PatFrag F> : PatFrag<(ops node:$rhs, node:$lhs), F.Fragment>;
272 // Pats for compares. They use PatFrags as operands, not SDNodes,
273 // since seteq/setgt/etc. are defined as ParFrags.
274 class T_cmp32_rr_pat<InstHexagon MI, PatFrag Op, ValueType VT>
275 : Pat<(VT (Op (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))),
276 (VT (MI IntRegs:$Rs, IntRegs:$Rt))>;
278 def: T_cmp32_rr_pat<C2_cmpeq, seteq, i1>;
279 def: T_cmp32_rr_pat<C2_cmpgt, setgt, i1>;
280 def: T_cmp32_rr_pat<C2_cmpgtu, setugt, i1>;
282 def: T_cmp32_rr_pat<C2_cmpgt, RevCmp<setlt>, i1>;
283 def: T_cmp32_rr_pat<C2_cmpgtu, RevCmp<setult>, i1>;
285 let CextOpcode = "MUX", InputType = "reg", hasNewValue = 1,
287 def C2_mux: ALU32_rr<(outs IntRegs:$Rd),
288 (ins PredRegs:$Pu, IntRegs:$Rs, IntRegs:$Rt),
289 "$Rd = mux($Pu, $Rs, $Rt)", [], "", ALU32_3op_tc_1_SLOT0123>, ImmRegRel {
295 let CextOpcode = "mux";
296 let InputType = "reg";
297 let hasSideEffects = 0;
300 let Inst{27-24} = 0b0100;
301 let Inst{20-16} = Rs;
307 def: Pat<(i32 (select (i1 PredRegs:$Pu), (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))),
308 (C2_mux PredRegs:$Pu, IntRegs:$Rs, IntRegs:$Rt)>;
310 // Combines the two immediates into a double register.
311 // Increase complexity to make it greater than any complexity of a combine
312 // that involves a register.
314 let isReMaterializable = 1, isMoveImm = 1, isAsCheapAsAMove = 1,
315 isExtentSigned = 1, isExtendable = 1, opExtentBits = 8, opExtendable = 1,
316 AddedComplexity = 75, isCodeGenOnly = 0 in
317 def A2_combineii: ALU32Inst <(outs DoubleRegs:$Rdd), (ins s8Ext:$s8, s8Imm:$S8),
318 "$Rdd = combine(#$s8, #$S8)",
319 [(set (i64 DoubleRegs:$Rdd),
320 (i64 (HexagonCOMBINE(i32 s8ExtPred:$s8), (i32 s8ImmPred:$S8))))]> {
326 let Inst{27-23} = 0b11000;
327 let Inst{22-16} = S8{7-1};
328 let Inst{13} = S8{0};
333 //===----------------------------------------------------------------------===//
334 // Template class for predicated ADD of a reg and an Immediate value.
335 //===----------------------------------------------------------------------===//
336 let hasNewValue = 1 in
337 class T_Addri_Pred <bit PredNot, bit PredNew>
338 : ALU32_ri <(outs IntRegs:$Rd),
339 (ins PredRegs:$Pu, IntRegs:$Rs, s8Ext:$s8),
340 !if(PredNot, "if (!$Pu", "if ($Pu")#!if(PredNew,".new) $Rd = ",
341 ") $Rd = ")#"add($Rs, #$s8)"> {
347 let isPredicatedNew = PredNew;
350 let Inst{27-24} = 0b0100;
351 let Inst{23} = PredNot;
352 let Inst{22-21} = Pu;
353 let Inst{20-16} = Rs;
354 let Inst{13} = PredNew;
359 //===----------------------------------------------------------------------===//
360 // A2_addi: Add a signed immediate to a register.
361 //===----------------------------------------------------------------------===//
362 let hasNewValue = 1 in
363 class T_Addri <Operand immOp, list<dag> pattern = [] >
364 : ALU32_ri <(outs IntRegs:$Rd),
365 (ins IntRegs:$Rs, immOp:$s16),
366 "$Rd = add($Rs, #$s16)", pattern,
367 //[(set (i32 IntRegs:$Rd), (add (i32 IntRegs:$Rs), (s16ExtPred:$s16)))],
368 "", ALU32_ADDI_tc_1_SLOT0123> {
375 let Inst{27-21} = s16{15-9};
376 let Inst{20-16} = Rs;
377 let Inst{13-5} = s16{8-0};
381 //===----------------------------------------------------------------------===//
382 // Multiclass for ADD of a register and an immediate value.
383 //===----------------------------------------------------------------------===//
384 multiclass Addri_Pred<string mnemonic, bit PredNot> {
385 let isPredicatedFalse = PredNot in {
386 def _c#NAME : T_Addri_Pred<PredNot, 0>;
388 def _cdn#NAME : T_Addri_Pred<PredNot, 1>;
392 let isExtendable = 1, InputType = "imm" in
393 multiclass Addri_base<string mnemonic, SDNode OpNode> {
394 let CextOpcode = mnemonic, BaseOpcode = mnemonic#_ri in {
395 let opExtendable = 2, isExtentSigned = 1, opExtentBits = 16,
397 def NAME : T_Addri< s16Ext, // Rd=add(Rs,#s16)
398 [(set (i32 IntRegs:$Rd),
399 (add IntRegs:$Rs, s16ExtPred:$s16))]>;
401 let opExtendable = 3, isExtentSigned = 1, opExtentBits = 8,
402 hasSideEffects = 0, isPredicated = 1 in {
403 defm Pt : Addri_Pred<mnemonic, 0>;
404 defm NotPt : Addri_Pred<mnemonic, 1>;
409 let isCodeGenOnly = 0 in
410 defm ADD_ri : Addri_base<"add", add>, ImmRegRel, PredNewRel;
412 //===----------------------------------------------------------------------===//
413 // Template class used for the following ALU32 instructions.
416 //===----------------------------------------------------------------------===//
417 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 10,
418 InputType = "imm", hasNewValue = 1 in
419 class T_ALU32ri_logical <string mnemonic, SDNode OpNode, bits<2> MinOp>
420 : ALU32_ri <(outs IntRegs:$Rd),
421 (ins IntRegs:$Rs, s10Ext:$s10),
422 "$Rd = "#mnemonic#"($Rs, #$s10)" ,
423 [(set (i32 IntRegs:$Rd), (OpNode (i32 IntRegs:$Rs), s10ExtPred:$s10))]> {
427 let CextOpcode = mnemonic;
431 let Inst{27-24} = 0b0110;
432 let Inst{23-22} = MinOp;
433 let Inst{21} = s10{9};
434 let Inst{20-16} = Rs;
435 let Inst{13-5} = s10{8-0};
439 let isCodeGenOnly = 0 in {
440 def OR_ri : T_ALU32ri_logical<"or", or, 0b10>, ImmRegRel;
441 def AND_ri : T_ALU32ri_logical<"and", and, 0b00>, ImmRegRel;
444 // Subtract register from immediate
445 // Rd32=sub(#s10,Rs32)
446 let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 10,
447 CextOpcode = "sub", InputType = "imm", hasNewValue = 1, isCodeGenOnly = 0 in
448 def SUB_ri: ALU32_ri <(outs IntRegs:$Rd), (ins s10Ext:$s10, IntRegs:$Rs),
449 "$Rd = sub(#$s10, $Rs)" ,
450 [(set IntRegs:$Rd, (sub s10ExtPred:$s10, IntRegs:$Rs))] > ,
458 let Inst{27-22} = 0b011001;
459 let Inst{21} = s10{9};
460 let Inst{20-16} = Rs;
461 let Inst{13-5} = s10{8-0};
466 let hasSideEffects = 0, isCodeGenOnly = 0 in
467 def A2_nop: ALU32Inst <(outs), (ins), "nop" > {
469 let Inst{27-24} = 0b1111;
471 // Rd = not(Rs) gets mapped to Rd=sub(#-1, Rs).
472 def : Pat<(not (i32 IntRegs:$src1)),
473 (SUB_ri -1, (i32 IntRegs:$src1))>;
475 let hasSideEffects = 0, hasNewValue = 1 in
476 class T_tfr16<bit isHi>
477 : ALU32Inst <(outs IntRegs:$Rx), (ins IntRegs:$src1, u16Imm:$u16),
478 "$Rx"#!if(isHi, ".h", ".l")#" = #$u16",
479 [], "$src1 = $Rx" > {
484 let Inst{27-26} = 0b00;
485 let Inst{25-24} = !if(isHi, 0b10, 0b01);
486 let Inst{23-22} = u16{15-14};
488 let Inst{20-16} = Rx;
489 let Inst{13-0} = u16{13-0};
492 let isCodeGenOnly = 0 in {
493 def A2_tfril: T_tfr16<0>;
494 def A2_tfrih: T_tfr16<1>;
497 // Conditional transfer is an alias to conditional "Rd = add(Rs, #0)".
498 let isPredicated = 1, hasNewValue = 1, opNewValue = 0 in
499 class T_tfr_pred<bit isPredNot, bit isPredNew>
500 : ALU32Inst<(outs IntRegs:$dst),
501 (ins PredRegs:$src1, IntRegs:$src2),
502 "if ("#!if(isPredNot, "!", "")#
503 "$src1"#!if(isPredNew, ".new", "")#
509 let isPredicatedFalse = isPredNot;
510 let isPredicatedNew = isPredNew;
513 let Inst{27-24} = 0b0100;
514 let Inst{23} = isPredNot;
515 let Inst{13} = isPredNew;
518 let Inst{22-21} = src1;
519 let Inst{20-16} = src2;
522 let isPredicable = 1 in
523 class T_tfr : ALU32Inst<(outs IntRegs:$dst), (ins IntRegs:$src),
530 let Inst{27-21} = 0b0000011;
531 let Inst{20-16} = src;
536 let InputType = "reg", hasNewValue = 1, hasSideEffects = 0 in
537 multiclass tfr_base<string CextOp> {
538 let CextOpcode = CextOp, BaseOpcode = CextOp in {
542 def t : T_tfr_pred<0, 0>;
543 def f : T_tfr_pred<1, 0>;
545 def tnew : T_tfr_pred<0, 1>;
546 def fnew : T_tfr_pred<1, 1>;
550 // Assembler mapped to C2_ccombinew[t|f|newt|newf].
551 // Please don't add bits to this instruction as it'll be converted into
552 // 'combine' before object code emission.
553 let isPredicated = 1 in
554 class T_tfrp_pred<bit PredNot, bit PredNew>
555 : ALU32_rr <(outs DoubleRegs:$dst),
556 (ins PredRegs:$src1, DoubleRegs:$src2),
557 "if ("#!if(PredNot, "!", "")#"$src1"
558 #!if(PredNew, ".new", "")#") $dst = $src2" > {
559 let isPredicatedFalse = PredNot;
560 let isPredicatedNew = PredNew;
563 // Assembler mapped to A2_combinew.
564 // Please don't add bits to this instruction as it'll be converted into
565 // 'combine' before object code emission.
566 class T_tfrp : ALU32Inst <(outs DoubleRegs:$dst),
567 (ins DoubleRegs:$src),
570 let hasSideEffects = 0 in
571 multiclass TFR64_base<string BaseName> {
572 let BaseOpcode = BaseName in {
573 let isPredicable = 1 in
576 def t : T_tfrp_pred <0, 0>;
577 def f : T_tfrp_pred <1, 0>;
579 def tnew : T_tfrp_pred <0, 1>;
580 def fnew : T_tfrp_pred <1, 1>;
584 let InputType = "imm", isExtendable = 1, isExtentSigned = 1, opExtentBits = 12,
585 isMoveImm = 1, opExtendable = 2, BaseOpcode = "TFRI", CextOpcode = "TFR",
586 hasSideEffects = 0, isPredicated = 1, hasNewValue = 1 in
587 class T_TFRI_Pred<bit PredNot, bit PredNew>
588 : ALU32_ri<(outs IntRegs:$Rd), (ins PredRegs:$Pu, s12Ext:$s12),
589 "if ("#!if(PredNot,"!","")#"$Pu"#!if(PredNew,".new","")#") $Rd = #$s12",
590 [], "", ALU32_2op_tc_1_SLOT0123>, ImmRegRel, PredNewRel {
591 let isPredicatedFalse = PredNot;
592 let isPredicatedNew = PredNew;
599 let Inst{27-24} = 0b1110;
600 let Inst{23} = PredNot;
601 let Inst{22-21} = Pu;
603 let Inst{19-16,12-5} = s12;
604 let Inst{13} = PredNew;
608 let isCodeGenOnly = 0 in {
609 def C2_cmoveit : T_TFRI_Pred<0, 0>;
610 def C2_cmoveif : T_TFRI_Pred<1, 0>;
611 def C2_cmovenewit : T_TFRI_Pred<0, 1>;
612 def C2_cmovenewif : T_TFRI_Pred<1, 1>;
615 let InputType = "imm", isExtendable = 1, isExtentSigned = 1,
616 CextOpcode = "TFR", BaseOpcode = "TFRI", hasNewValue = 1, opNewValue = 0,
617 isAsCheapAsAMove = 1 , opExtendable = 1, opExtentBits = 16, isMoveImm = 1,
618 isPredicated = 0, isPredicable = 1, isReMaterializable = 1,
620 def A2_tfrsi : ALU32Inst<(outs IntRegs:$Rd), (ins s16Ext:$s16), "$Rd = #$s16",
621 [(set (i32 IntRegs:$Rd), s16ExtPred:$s16)], "", ALU32_2op_tc_1_SLOT0123>,
627 let Inst{27-24} = 0b1000;
628 let Inst{23-22,20-16,13-5} = s16;
632 let isCodeGenOnly = 0 in
633 defm A2_tfr : tfr_base<"TFR">, ImmRegRel, PredNewRel;
634 defm A2_tfrp : TFR64_base<"TFR64">, PredNewRel;
637 let isReMaterializable = 1, isMoveImm = 1, isAsCheapAsAMove = 1 in
638 def A2_tfrpi : ALU64_rr<(outs DoubleRegs:$dst), (ins s8Imm64:$src1),
640 [(set (i64 DoubleRegs:$dst), s8Imm64Pred:$src1)]>;
642 // TODO: see if this instruction can be deleted..
643 let isExtendable = 1, opExtendable = 1, opExtentBits = 6 in
644 def TFRI64_V4 : ALU64_rr<(outs DoubleRegs:$dst), (ins u6Ext:$src1),
647 //===----------------------------------------------------------------------===//
649 //===----------------------------------------------------------------------===//
652 //===----------------------------------------------------------------------===//
654 //===----------------------------------------------------------------------===//
655 // Scalar mux register immediate.
656 let hasSideEffects = 0, isExtentSigned = 1, CextOpcode = "MUX",
657 InputType = "imm", hasNewValue = 1, isExtendable = 1, opExtentBits = 8 in
658 class T_MUX1 <bit MajOp, dag ins, string AsmStr>
659 : ALU32Inst <(outs IntRegs:$Rd), ins, AsmStr>, ImmRegRel {
666 let Inst{27-24} = 0b0011;
667 let Inst{23} = MajOp;
668 let Inst{22-21} = Pu;
669 let Inst{20-16} = Rs;
675 let opExtendable = 2, isCodeGenOnly = 0 in
676 def C2_muxri : T_MUX1<0b1, (ins PredRegs:$Pu, s8Ext:$s8, IntRegs:$Rs),
677 "$Rd = mux($Pu, #$s8, $Rs)">;
679 let opExtendable = 3, isCodeGenOnly = 0 in
680 def C2_muxir : T_MUX1<0b0, (ins PredRegs:$Pu, IntRegs:$Rs, s8Ext:$s8),
681 "$Rd = mux($Pu, $Rs, #$s8)">;
683 def : Pat<(i32 (select I1:$Pu, s8ExtPred:$s8, I32:$Rs)),
684 (C2_muxri I1:$Pu, s8ExtPred:$s8, I32:$Rs)>;
686 def : Pat<(i32 (select I1:$Pu, I32:$Rs, s8ExtPred:$s8)),
687 (C2_muxir I1:$Pu, I32:$Rs, s8ExtPred:$s8)>;
689 // C2_muxii: Scalar mux immediates.
690 let isExtentSigned = 1, hasNewValue = 1, isExtendable = 1,
691 opExtentBits = 8, opExtendable = 2, isCodeGenOnly = 0 in
692 def C2_muxii: ALU32Inst <(outs IntRegs:$Rd),
693 (ins PredRegs:$Pu, s8Ext:$s8, s8Imm:$S8),
694 "$Rd = mux($Pu, #$s8, #$S8)" ,
695 [(set (i32 IntRegs:$Rd),
696 (i32 (select I1:$Pu, s8ExtPred:$s8, s8ImmPred:$S8)))] > {
704 let Inst{27-25} = 0b101;
705 let Inst{24-23} = Pu;
706 let Inst{22-16} = S8{7-1};
707 let Inst{13} = S8{0};
712 //===----------------------------------------------------------------------===//
713 // template class for non-predicated alu32_2op instructions
714 // - aslh, asrh, sxtb, sxth, zxth
715 //===----------------------------------------------------------------------===//
716 let hasNewValue = 1, opNewValue = 0 in
717 class T_ALU32_2op <string mnemonic, bits<3> minOp> :
718 ALU32Inst < (outs IntRegs:$Rd), (ins IntRegs:$Rs),
719 "$Rd = "#mnemonic#"($Rs)", [] > {
725 let Inst{27-24} = 0b0000;
726 let Inst{23-21} = minOp;
729 let Inst{20-16} = Rs;
732 //===----------------------------------------------------------------------===//
733 // template class for predicated alu32_2op instructions
734 // - aslh, asrh, sxtb, sxth, zxtb, zxth
735 //===----------------------------------------------------------------------===//
736 let hasSideEffects = 0, validSubTargets = HasV4SubT,
737 hasNewValue = 1, opNewValue = 0 in
738 class T_ALU32_2op_Pred <string mnemonic, bits<3> minOp, bit isPredNot,
740 ALU32Inst <(outs IntRegs:$Rd), (ins PredRegs:$Pu, IntRegs:$Rs),
741 !if(isPredNot, "if (!$Pu", "if ($Pu")
742 #!if(isPredNew, ".new) ",") ")#"$Rd = "#mnemonic#"($Rs)"> {
749 let Inst{27-24} = 0b0000;
750 let Inst{23-21} = minOp;
752 let Inst{11} = isPredNot;
753 let Inst{10} = isPredNew;
756 let Inst{20-16} = Rs;
759 multiclass ALU32_2op_Pred<string mnemonic, bits<3> minOp, bit PredNot> {
760 let isPredicatedFalse = PredNot in {
761 def NAME : T_ALU32_2op_Pred<mnemonic, minOp, PredNot, 0>;
764 let isPredicatedNew = 1 in
765 def NAME#new : T_ALU32_2op_Pred<mnemonic, minOp, PredNot, 1>;
769 multiclass ALU32_2op_base<string mnemonic, bits<3> minOp> {
770 let BaseOpcode = mnemonic in {
771 let isPredicable = 1, hasSideEffects = 0 in
772 def A2_#NAME : T_ALU32_2op<mnemonic, minOp>;
774 let validSubTargets = HasV4SubT, isPredicated = 1, hasSideEffects = 0 in {
775 defm A4_p#NAME#t : ALU32_2op_Pred<mnemonic, minOp, 0>;
776 defm A4_p#NAME#f : ALU32_2op_Pred<mnemonic, minOp, 1>;
781 let isCodeGenOnly = 0 in {
782 defm aslh : ALU32_2op_base<"aslh", 0b000>, PredNewRel;
783 defm asrh : ALU32_2op_base<"asrh", 0b001>, PredNewRel;
784 defm sxtb : ALU32_2op_base<"sxtb", 0b101>, PredNewRel;
785 defm sxth : ALU32_2op_base<"sxth", 0b111>, PredNewRel;
786 defm zxth : ALU32_2op_base<"zxth", 0b110>, PredNewRel;
789 // Rd=zxtb(Rs): assembler mapped to Rd=and(Rs,#255).
790 // Compiler would want to generate 'zxtb' instead of 'and' becuase 'zxtb' has
791 // predicated forms while 'and' doesn't. Since integrated assembler can't
792 // handle 'mapped' instructions, we need to encode 'zxtb' same as 'and' where
793 // immediate operand is set to '255'.
795 let hasNewValue = 1, opNewValue = 0 in
796 class T_ZXTB: ALU32Inst < (outs IntRegs:$Rd), (ins IntRegs:$Rs),
797 "$Rd = zxtb($Rs)", [] > { // Rd = and(Rs,255)
804 let Inst{27-22} = 0b011000;
806 let Inst{20-16} = Rs;
807 let Inst{21} = s10{9};
808 let Inst{13-5} = s10{8-0};
811 //Rd=zxtb(Rs): assembler mapped to "Rd=and(Rs,#255)
812 multiclass ZXTB_base <string mnemonic, bits<3> minOp> {
813 let BaseOpcode = mnemonic in {
814 let isPredicable = 1, hasSideEffects = 0 in
815 def A2_#NAME : T_ZXTB;
817 let validSubTargets = HasV4SubT, isPredicated = 1, hasSideEffects = 0 in {
818 defm A4_p#NAME#t : ALU32_2op_Pred<mnemonic, minOp, 0>;
819 defm A4_p#NAME#f : ALU32_2op_Pred<mnemonic, minOp, 1>;
824 let isCodeGenOnly=0 in
825 defm zxtb : ZXTB_base<"zxtb",0b100>, PredNewRel;
827 def: Pat<(shl I32:$src1, (i32 16)), (A2_aslh I32:$src1)>;
828 def: Pat<(sra I32:$src1, (i32 16)), (A2_asrh I32:$src1)>;
829 def: Pat<(sext_inreg I32:$src1, i8), (A2_sxtb I32:$src1)>;
830 def: Pat<(sext_inreg I32:$src1, i16), (A2_sxth I32:$src1)>;
832 //===----------------------------------------------------------------------===//
834 //===----------------------------------------------------------------------===//
837 //===----------------------------------------------------------------------===//
839 //===----------------------------------------------------------------------===//
841 //===----------------------------------------------------------------------===//
843 //===----------------------------------------------------------------------===//
846 //===----------------------------------------------------------------------===//
848 //===----------------------------------------------------------------------===//// Add.
849 //===----------------------------------------------------------------------===//
851 // Add/Subtract halfword
852 // Rd=add(Rt.L,Rs.[HL])[:sat]
853 // Rd=sub(Rt.L,Rs.[HL])[:sat]
854 // Rd=add(Rt.[LH],Rs.[HL])[:sat][:<16]
855 // Rd=sub(Rt.[LH],Rs.[HL])[:sat][:<16]
856 //===----------------------------------------------------------------------===//
858 let hasNewValue = 1, opNewValue = 0 in
859 class T_XTYPE_ADD_SUB <bits<2> LHbits, bit isSat, bit hasShift, bit isSub>
860 : ALU64Inst <(outs IntRegs:$Rd), (ins IntRegs:$Rt, IntRegs:$Rs),
861 "$Rd = "#!if(isSub,"sub","add")#"($Rt."
862 #!if(hasShift, !if(LHbits{1},"h","l"),"l") #", $Rs."
863 #!if(hasShift, !if(LHbits{0},"h)","l)"), !if(LHbits{1},"h)","l)"))
864 #!if(isSat,":sat","")
865 #!if(hasShift,":<<16",""), [], "", ALU64_tc_1_SLOT23> {
871 let Inst{27-23} = 0b01010;
872 let Inst{22} = hasShift;
873 let Inst{21} = isSub;
875 let Inst{6-5} = LHbits;
878 let Inst{20-16} = Rs;
881 //Rd=sub(Rt.L,Rs.[LH])
882 let isCodeGenOnly = 0 in {
883 def A2_subh_l16_ll : T_XTYPE_ADD_SUB <0b00, 0, 0, 1>;
884 def A2_subh_l16_hl : T_XTYPE_ADD_SUB <0b10, 0, 0, 1>;
887 let isCodeGenOnly = 0 in {
888 //Rd=add(Rt.L,Rs.[LH])
889 def A2_addh_l16_ll : T_XTYPE_ADD_SUB <0b00, 0, 0, 0>;
890 def A2_addh_l16_hl : T_XTYPE_ADD_SUB <0b10, 0, 0, 0>;
893 let Itinerary = ALU64_tc_2_SLOT23, Defs = [USR_OVF], isCodeGenOnly = 0 in {
894 //Rd=sub(Rt.L,Rs.[LH]):sat
895 def A2_subh_l16_sat_ll : T_XTYPE_ADD_SUB <0b00, 1, 0, 1>;
896 def A2_subh_l16_sat_hl : T_XTYPE_ADD_SUB <0b10, 1, 0, 1>;
898 //Rd=add(Rt.L,Rs.[LH]):sat
899 def A2_addh_l16_sat_ll : T_XTYPE_ADD_SUB <0b00, 1, 0, 0>;
900 def A2_addh_l16_sat_hl : T_XTYPE_ADD_SUB <0b10, 1, 0, 0>;
903 //Rd=sub(Rt.[LH],Rs.[LH]):<<16
904 let isCodeGenOnly = 0 in {
905 def A2_subh_h16_ll : T_XTYPE_ADD_SUB <0b00, 0, 1, 1>;
906 def A2_subh_h16_lh : T_XTYPE_ADD_SUB <0b01, 0, 1, 1>;
907 def A2_subh_h16_hl : T_XTYPE_ADD_SUB <0b10, 0, 1, 1>;
908 def A2_subh_h16_hh : T_XTYPE_ADD_SUB <0b11, 0, 1, 1>;
911 //Rd=add(Rt.[LH],Rs.[LH]):<<16
912 let isCodeGenOnly = 0 in {
913 def A2_addh_h16_ll : T_XTYPE_ADD_SUB <0b00, 0, 1, 0>;
914 def A2_addh_h16_lh : T_XTYPE_ADD_SUB <0b01, 0, 1, 0>;
915 def A2_addh_h16_hl : T_XTYPE_ADD_SUB <0b10, 0, 1, 0>;
916 def A2_addh_h16_hh : T_XTYPE_ADD_SUB <0b11, 0, 1, 0>;
919 let Itinerary = ALU64_tc_2_SLOT23, Defs = [USR_OVF], isCodeGenOnly = 0 in {
920 //Rd=sub(Rt.[LH],Rs.[LH]):sat:<<16
921 def A2_subh_h16_sat_ll : T_XTYPE_ADD_SUB <0b00, 1, 1, 1>;
922 def A2_subh_h16_sat_lh : T_XTYPE_ADD_SUB <0b01, 1, 1, 1>;
923 def A2_subh_h16_sat_hl : T_XTYPE_ADD_SUB <0b10, 1, 1, 1>;
924 def A2_subh_h16_sat_hh : T_XTYPE_ADD_SUB <0b11, 1, 1, 1>;
926 //Rd=add(Rt.[LH],Rs.[LH]):sat:<<16
927 def A2_addh_h16_sat_ll : T_XTYPE_ADD_SUB <0b00, 1, 1, 0>;
928 def A2_addh_h16_sat_lh : T_XTYPE_ADD_SUB <0b01, 1, 1, 0>;
929 def A2_addh_h16_sat_hl : T_XTYPE_ADD_SUB <0b10, 1, 1, 0>;
930 def A2_addh_h16_sat_hh : T_XTYPE_ADD_SUB <0b11, 1, 1, 0>;
934 def: Pat<(sext_inreg (add I32:$src1, I32:$src2), i16),
935 (A2_addh_l16_ll I32:$src1, I32:$src2)>;
937 def: Pat<(sra (add (shl I32:$src1, (i32 16)), I32:$src2), (i32 16)),
938 (A2_addh_l16_hl I32:$src1, I32:$src2)>;
940 def: Pat<(shl (add I32:$src1, I32:$src2), (i32 16)),
941 (A2_addh_h16_ll I32:$src1, I32:$src2)>;
943 // Subtract halfword.
944 def: Pat<(sext_inreg (sub I32:$src1, I32:$src2), i16),
945 (A2_subh_l16_ll I32:$src1, I32:$src2)>;
947 def: Pat<(shl (sub I32:$src1, I32:$src2), (i32 16)),
948 (A2_subh_h16_ll I32:$src1, I32:$src2)>;
950 let hasSideEffects = 0, hasNewValue = 1, isCodeGenOnly = 0 in
951 def S2_parityp: ALU64Inst<(outs IntRegs:$Rd),
952 (ins DoubleRegs:$Rs, DoubleRegs:$Rt),
953 "$Rd = parity($Rs, $Rt)", [], "", ALU64_tc_2_SLOT23> {
959 let Inst{27-24} = 0b0000;
960 let Inst{20-16} = Rs;
965 let hasNewValue = 1, opNewValue = 0, hasSideEffects = 0 in
966 class T_XTYPE_MIN_MAX < bit isMax, bit isUnsigned >
967 : ALU64Inst < (outs IntRegs:$Rd), (ins IntRegs:$Rt, IntRegs:$Rs),
968 "$Rd = "#!if(isMax,"max","min")#!if(isUnsigned,"u","")
969 #"($Rt, $Rs)", [], "", ALU64_tc_2_SLOT23> {
976 let Inst{27-23} = 0b01011;
977 let Inst{22-21} = !if(isMax, 0b10, 0b01);
978 let Inst{7} = isUnsigned;
980 let Inst{12-8} = !if(isMax, Rs, Rt);
981 let Inst{20-16} = !if(isMax, Rt, Rs);
984 let isCodeGenOnly = 0 in {
985 def A2_min : T_XTYPE_MIN_MAX < 0, 0 >;
986 def A2_minu : T_XTYPE_MIN_MAX < 0, 1 >;
987 def A2_max : T_XTYPE_MIN_MAX < 1, 0 >;
988 def A2_maxu : T_XTYPE_MIN_MAX < 1, 1 >;
991 // Here, depending on the operand being selected, we'll either generate a
992 // min or max instruction.
994 // (a>b)?a:b --> max(a,b) => Here check performed is '>' and the value selected
995 // is the larger of two. So, the corresponding HexagonInst is passed in 'Inst'.
996 // (a>b)?b:a --> min(a,b) => Here check performed is '>' but the smaller value
997 // is selected and the corresponding HexagonInst is passed in 'SwapInst'.
999 multiclass T_MinMax_pats <PatFrag Op, RegisterClass RC, ValueType VT,
1000 InstHexagon Inst, InstHexagon SwapInst> {
1001 def: Pat<(select (i1 (Op (VT RC:$src1), (VT RC:$src2))),
1002 (VT RC:$src1), (VT RC:$src2)),
1003 (Inst RC:$src1, RC:$src2)>;
1004 def: Pat<(select (i1 (Op (VT RC:$src1), (VT RC:$src2))),
1005 (VT RC:$src2), (VT RC:$src1)),
1006 (SwapInst RC:$src1, RC:$src2)>;
1010 multiclass MinMax_pats <PatFrag Op, InstHexagon Inst, InstHexagon SwapInst> {
1011 defm: T_MinMax_pats<Op, IntRegs, i32, Inst, SwapInst>;
1013 def: Pat<(sext_inreg (i32 (select (i1 (Op (i32 PositiveHalfWord:$src1),
1014 (i32 PositiveHalfWord:$src2))),
1015 (i32 PositiveHalfWord:$src1),
1016 (i32 PositiveHalfWord:$src2))), i16),
1017 (Inst IntRegs:$src1, IntRegs:$src2)>;
1019 def: Pat<(sext_inreg (i32 (select (i1 (Op (i32 PositiveHalfWord:$src1),
1020 (i32 PositiveHalfWord:$src2))),
1021 (i32 PositiveHalfWord:$src2),
1022 (i32 PositiveHalfWord:$src1))), i16),
1023 (SwapInst IntRegs:$src1, IntRegs:$src2)>;
1026 let AddedComplexity = 200 in {
1027 defm: MinMax_pats<setge, A2_max, A2_min>;
1028 defm: MinMax_pats<setgt, A2_max, A2_min>;
1029 defm: MinMax_pats<setle, A2_min, A2_max>;
1030 defm: MinMax_pats<setlt, A2_min, A2_max>;
1031 defm: MinMax_pats<setuge, A2_maxu, A2_minu>;
1032 defm: MinMax_pats<setugt, A2_maxu, A2_minu>;
1033 defm: MinMax_pats<setule, A2_minu, A2_maxu>;
1034 defm: MinMax_pats<setult, A2_minu, A2_maxu>;
1037 class T_cmp64_rr<string mnemonic, bits<3> MinOp, bit IsComm>
1038 : ALU64_rr<(outs PredRegs:$Pd), (ins DoubleRegs:$Rs, DoubleRegs:$Rt),
1039 "$Pd = "#mnemonic#"($Rs, $Rt)", [], "", ALU64_tc_2early_SLOT23> {
1041 let isCommutable = IsComm;
1042 let hasSideEffects = 0;
1048 let IClass = 0b1101;
1049 let Inst{27-21} = 0b0010100;
1050 let Inst{20-16} = Rs;
1051 let Inst{12-8} = Rt;
1052 let Inst{7-5} = MinOp;
1056 let isCodeGenOnly = 0 in {
1057 def C2_cmpeqp : T_cmp64_rr<"cmp.eq", 0b000, 1>;
1058 def C2_cmpgtp : T_cmp64_rr<"cmp.gt", 0b010, 0>;
1059 def C2_cmpgtup : T_cmp64_rr<"cmp.gtu", 0b100, 0>;
1062 class T_cmp64_rr_pat<InstHexagon MI, PatFrag CmpOp>
1063 : Pat<(i1 (CmpOp (i64 DoubleRegs:$Rs), (i64 DoubleRegs:$Rt))),
1064 (i1 (MI DoubleRegs:$Rs, DoubleRegs:$Rt))>;
1066 def: T_cmp64_rr_pat<C2_cmpeqp, seteq>;
1067 def: T_cmp64_rr_pat<C2_cmpgtp, setgt>;
1068 def: T_cmp64_rr_pat<C2_cmpgtup, setugt>;
1069 def: T_cmp64_rr_pat<C2_cmpgtp, RevCmp<setlt>>;
1070 def: T_cmp64_rr_pat<C2_cmpgtup, RevCmp<setult>>;
1072 let isCodeGenOnly = 0 in
1073 def C2_vmux : ALU64_rr<(outs DoubleRegs:$Rd),
1074 (ins PredRegs:$Pu, DoubleRegs:$Rs, DoubleRegs:$Rt),
1075 "$Rd = vmux($Pu, $Rs, $Rt)", [], "", ALU64_tc_1_SLOT23> {
1076 let hasSideEffects = 0;
1083 let IClass = 0b1101;
1084 let Inst{27-24} = 0b0001;
1085 let Inst{20-16} = Rs;
1086 let Inst{12-8} = Rt;
1091 class T_ALU64_rr<string mnemonic, string suffix, bits<4> RegType,
1092 bits<3> MajOp, bits<3> MinOp, bit OpsRev, bit IsComm,
1094 : ALU64_rr<(outs DoubleRegs:$Rd), (ins DoubleRegs:$Rs, DoubleRegs:$Rt),
1095 "$Rd = " #mnemonic# "($Rs, " #Op2Pfx# "$Rt)" #suffix, [],
1096 "", ALU64_tc_1_SLOT23> {
1097 let hasSideEffects = 0;
1098 let isCommutable = IsComm;
1104 let IClass = 0b1101;
1105 let Inst{27-24} = RegType;
1106 let Inst{23-21} = MajOp;
1107 let Inst{20-16} = !if (OpsRev,Rt,Rs);
1108 let Inst{12-8} = !if (OpsRev,Rs,Rt);
1109 let Inst{7-5} = MinOp;
1113 class T_ALU64_arith<string mnemonic, bits<3> MajOp, bits<3> MinOp, bit IsSat,
1114 bit OpsRev, bit IsComm>
1115 : T_ALU64_rr<mnemonic, !if(IsSat,":sat",""), 0b0011, MajOp, MinOp, OpsRev,
1118 let isCodeGenOnly = 0 in {
1119 def A2_addp : T_ALU64_arith<"add", 0b000, 0b111, 0, 0, 1>;
1120 def A2_subp : T_ALU64_arith<"sub", 0b001, 0b111, 0, 1, 0>;
1123 def: Pat<(i64 (add I64:$Rs, I64:$Rt)), (A2_addp I64:$Rs, I64:$Rt)>;
1124 def: Pat<(i64 (sub I64:$Rs, I64:$Rt)), (A2_subp I64:$Rs, I64:$Rt)>;
1126 class T_ALU64_logical<string mnemonic, bits<3> MinOp, bit OpsRev, bit IsComm,
1128 : T_ALU64_rr<mnemonic, "", 0b0011, 0b111, MinOp, OpsRev, IsComm,
1131 let isCodeGenOnly = 0 in {
1132 def A2_andp : T_ALU64_logical<"and", 0b000, 0, 1, 0>;
1133 def A2_orp : T_ALU64_logical<"or", 0b010, 0, 1, 0>;
1134 def A2_xorp : T_ALU64_logical<"xor", 0b100, 0, 1, 0>;
1137 def: Pat<(i64 (and I64:$Rs, I64:$Rt)), (A2_andp I64:$Rs, I64:$Rt)>;
1138 def: Pat<(i64 (or I64:$Rs, I64:$Rt)), (A2_orp I64:$Rs, I64:$Rt)>;
1139 def: Pat<(i64 (xor I64:$Rs, I64:$Rt)), (A2_xorp I64:$Rs, I64:$Rt)>;
1141 //===----------------------------------------------------------------------===//
1143 //===----------------------------------------------------------------------===//
1145 //===----------------------------------------------------------------------===//
1147 //===----------------------------------------------------------------------===//
1149 //===----------------------------------------------------------------------===//
1151 //===----------------------------------------------------------------------===//
1153 //===----------------------------------------------------------------------===//
1155 //===----------------------------------------------------------------------===//
1157 //===----------------------------------------------------------------------===//
1159 //===----------------------------------------------------------------------===//
1161 //===----------------------------------------------------------------------===//
1163 //===----------------------------------------------------------------------===//
1164 // Logical reductions on predicates.
1166 // Looping instructions.
1168 // Pipelined looping instructions.
1170 // Logical operations on predicates.
1171 let hasSideEffects = 0 in
1172 class T_LOGICAL_1OP<string MnOp, bits<2> OpBits>
1173 : CRInst<(outs PredRegs:$Pd), (ins PredRegs:$Ps),
1174 "$Pd = " # MnOp # "($Ps)", [], "", CR_tc_2early_SLOT23> {
1178 let IClass = 0b0110;
1179 let Inst{27-23} = 0b10111;
1180 let Inst{22-21} = OpBits;
1182 let Inst{17-16} = Ps;
1187 let isCodeGenOnly = 0 in {
1188 def C2_any8 : T_LOGICAL_1OP<"any8", 0b00>;
1189 def C2_all8 : T_LOGICAL_1OP<"all8", 0b01>;
1190 def C2_not : T_LOGICAL_1OP<"not", 0b10>;
1193 def: Pat<(i1 (not (i1 PredRegs:$Ps))),
1194 (C2_not PredRegs:$Ps)>;
1196 let hasSideEffects = 0 in
1197 class T_LOGICAL_2OP<string MnOp, bits<3> OpBits, bit IsNeg, bit Rev>
1198 : CRInst<(outs PredRegs:$Pd), (ins PredRegs:$Ps, PredRegs:$Pt),
1199 "$Pd = " # MnOp # "($Ps, " # !if (IsNeg,"!","") # "$Pt)",
1200 [], "", CR_tc_2early_SLOT23> {
1205 let IClass = 0b0110;
1206 let Inst{27-24} = 0b1011;
1207 let Inst{23-21} = OpBits;
1209 let Inst{17-16} = !if(Rev,Pt,Ps); // Rs and Rt are reversed for some
1210 let Inst{13} = 0b0; // instructions.
1211 let Inst{9-8} = !if(Rev,Ps,Pt);
1215 let isCodeGenOnly = 0 in {
1216 def C2_and : T_LOGICAL_2OP<"and", 0b000, 0, 1>;
1217 def C2_or : T_LOGICAL_2OP<"or", 0b001, 0, 1>;
1218 def C2_xor : T_LOGICAL_2OP<"xor", 0b010, 0, 0>;
1219 def C2_andn : T_LOGICAL_2OP<"and", 0b011, 1, 1>;
1220 def C2_orn : T_LOGICAL_2OP<"or", 0b111, 1, 1>;
1223 def: Pat<(i1 (and I1:$Ps, I1:$Pt)), (C2_and I1:$Ps, I1:$Pt)>;
1224 def: Pat<(i1 (or I1:$Ps, I1:$Pt)), (C2_or I1:$Ps, I1:$Pt)>;
1225 def: Pat<(i1 (xor I1:$Ps, I1:$Pt)), (C2_xor I1:$Ps, I1:$Pt)>;
1226 def: Pat<(i1 (and I1:$Ps, (not I1:$Pt))), (C2_andn I1:$Ps, I1:$Pt)>;
1227 def: Pat<(i1 (or I1:$Ps, (not I1:$Pt))), (C2_orn I1:$Ps, I1:$Pt)>;
1229 let hasSideEffects = 0, hasNewValue = 1, isCodeGenOnly = 0 in
1230 def C2_vitpack : SInst<(outs IntRegs:$Rd), (ins PredRegs:$Ps, PredRegs:$Pt),
1231 "$Rd = vitpack($Ps, $Pt)", [], "", S_2op_tc_1_SLOT23> {
1236 let IClass = 0b1000;
1237 let Inst{27-24} = 0b1001;
1238 let Inst{22-21} = 0b00;
1239 let Inst{17-16} = Ps;
1244 let hasSideEffects = 0, isCodeGenOnly = 0 in
1245 def C2_mask : SInst<(outs DoubleRegs:$Rd), (ins PredRegs:$Pt),
1246 "$Rd = mask($Pt)", [], "", S_2op_tc_1_SLOT23> {
1250 let IClass = 0b1000;
1251 let Inst{27-24} = 0b0110;
1256 // User control register transfer.
1257 //===----------------------------------------------------------------------===//
1259 //===----------------------------------------------------------------------===//
1261 //===----------------------------------------------------------------------===//
1263 //===----------------------------------------------------------------------===//
1265 def retflag : SDNode<"HexagonISD::RET_FLAG", SDTNone,
1266 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
1267 def eh_return: SDNode<"HexagonISD::EH_RETURN", SDTNone, [SDNPHasChain]>;
1269 def SDHexagonBR_JT: SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
1270 def HexagonBR_JT: SDNode<"HexagonISD::BR_JT", SDHexagonBR_JT, [SDNPHasChain]>;
1272 class CondStr<string CReg, bit True, bit New> {
1273 string S = "if (" # !if(True,"","!") # CReg # !if(New,".new","") # ") ";
1275 class JumpOpcStr<string Mnemonic, bit New, bit Taken> {
1276 string S = Mnemonic # !if(New, !if(Taken,":t",":nt"), "");
1279 let isBranch = 1, isBarrier = 1, Defs = [PC], hasSideEffects = 0,
1281 isExtendable = 1, opExtendable = 0, isExtentSigned = 1,
1282 opExtentBits = 24, opExtentAlign = 2, InputType = "imm" in
1283 class T_JMP<string ExtStr>
1284 : JInst<(outs), (ins brtarget:$dst),
1285 "jump " # ExtStr # "$dst",
1286 [], "", J_tc_2early_SLOT23> {
1288 let IClass = 0b0101;
1290 let Inst{27-25} = 0b100;
1291 let Inst{24-16} = dst{23-15};
1292 let Inst{13-1} = dst{14-2};
1295 let isBranch = 1, Defs = [PC], hasSideEffects = 0, isPredicated = 1,
1296 isExtendable = 1, opExtendable = 1, isExtentSigned = 1,
1297 opExtentBits = 17, opExtentAlign = 2, InputType = "imm" in
1298 class T_JMP_c<bit PredNot, bit isPredNew, bit isTak, string ExtStr>
1299 : JInst<(outs), (ins PredRegs:$src, brtarget:$dst),
1300 CondStr<"$src", !if(PredNot,0,1), isPredNew>.S #
1301 JumpOpcStr<"jump", isPredNew, isTak>.S # " " #
1303 [], "", J_tc_2early_SLOT23>, ImmRegRel {
1304 let isTaken = isTak;
1305 let isPredicatedFalse = PredNot;
1306 let isPredicatedNew = isPredNew;
1310 let IClass = 0b0101;
1312 let Inst{27-24} = 0b1100;
1313 let Inst{21} = PredNot;
1314 let Inst{12} = !if(isPredNew, isTak, zero);
1315 let Inst{11} = isPredNew;
1316 let Inst{9-8} = src;
1317 let Inst{23-22} = dst{16-15};
1318 let Inst{20-16} = dst{14-10};
1319 let Inst{13} = dst{9};
1320 let Inst{7-1} = dst{8-2};
1323 multiclass JMP_Pred<bit PredNot, string ExtStr> {
1324 def NAME : T_JMP_c<PredNot, 0, 0, ExtStr>;
1326 def NAME#newpt : T_JMP_c<PredNot, 1, 1, ExtStr>; // taken
1327 def NAME#new : T_JMP_c<PredNot, 1, 0, ExtStr>; // not taken
1330 multiclass JMP_base<string BaseOp, string ExtStr> {
1331 let BaseOpcode = BaseOp in {
1332 def NAME : T_JMP<ExtStr>;
1333 defm t : JMP_Pred<0, ExtStr>;
1334 defm f : JMP_Pred<1, ExtStr>;
1338 // Jumps to address stored in a register, JUMPR_MISC
1339 // if ([[!]P[.new]]) jumpr[:t/nt] Rs
1340 let isBranch = 1, isIndirectBranch = 1, isBarrier = 1, Defs = [PC],
1341 isPredicable = 1, hasSideEffects = 0, InputType = "reg" in
1343 : JRInst<(outs), (ins IntRegs:$dst),
1344 "jumpr $dst", [], "", J_tc_2early_SLOT2> {
1347 let IClass = 0b0101;
1348 let Inst{27-21} = 0b0010100;
1349 let Inst{20-16} = dst;
1352 let isBranch = 1, isIndirectBranch = 1, Defs = [PC], isPredicated = 1,
1353 hasSideEffects = 0, InputType = "reg" in
1354 class T_JMPr_c <bit PredNot, bit isPredNew, bit isTak>
1355 : JRInst <(outs), (ins PredRegs:$src, IntRegs:$dst),
1356 CondStr<"$src", !if(PredNot,0,1), isPredNew>.S #
1357 JumpOpcStr<"jumpr", isPredNew, isTak>.S # " $dst", [],
1358 "", J_tc_2early_SLOT2> {
1360 let isTaken = isTak;
1361 let isPredicatedFalse = PredNot;
1362 let isPredicatedNew = isPredNew;
1366 let IClass = 0b0101;
1368 let Inst{27-22} = 0b001101;
1369 let Inst{21} = PredNot;
1370 let Inst{20-16} = dst;
1371 let Inst{12} = !if(isPredNew, isTak, zero);
1372 let Inst{11} = isPredNew;
1373 let Inst{9-8} = src;
1376 multiclass JMPR_Pred<bit PredNot> {
1377 def NAME: T_JMPr_c<PredNot, 0, 0>;
1379 def NAME#newpt : T_JMPr_c<PredNot, 1, 1>; // taken
1380 def NAME#new : T_JMPr_c<PredNot, 1, 0>; // not taken
1383 multiclass JMPR_base<string BaseOp> {
1384 let BaseOpcode = BaseOp in {
1386 defm t : JMPR_Pred<0>;
1387 defm f : JMPR_Pred<1>;
1391 let isCall = 1, hasSideEffects = 1 in
1392 class JUMPR_MISC_CALLR<bit isPred, bit isPredNot,
1393 dag InputDag = (ins IntRegs:$Rs)>
1394 : JRInst<(outs), InputDag,
1395 !if(isPred, !if(isPredNot, "if (!$Pu) callr $Rs",
1396 "if ($Pu) callr $Rs"),
1398 [], "", J_tc_2early_SLOT2> {
1401 let isPredicated = isPred;
1402 let isPredicatedFalse = isPredNot;
1404 let IClass = 0b0101;
1405 let Inst{27-25} = 0b000;
1406 let Inst{24-23} = !if (isPred, 0b10, 0b01);
1408 let Inst{21} = isPredNot;
1409 let Inst{9-8} = !if (isPred, Pu, 0b00);
1410 let Inst{20-16} = Rs;
1414 let Defs = VolatileV3.Regs, isCodeGenOnly = 0 in {
1415 def J2_callrt : JUMPR_MISC_CALLR<1, 0, (ins PredRegs:$Pu, IntRegs:$Rs)>;
1416 def J2_callrf : JUMPR_MISC_CALLR<1, 1, (ins PredRegs:$Pu, IntRegs:$Rs)>;
1419 let isTerminator = 1, hasSideEffects = 0, isCodeGenOnly = 0 in {
1420 defm J2_jump : JMP_base<"JMP", "">, PredNewRel;
1422 // Deal with explicit assembly
1423 // - never extened a jump #, always extend a jump ##
1424 let isAsmParserOnly = 1 in {
1425 defm J2_jump_ext : JMP_base<"JMP", "##">;
1426 defm J2_jump_noext : JMP_base<"JMP", "#">;
1429 defm J2_jumpr : JMPR_base<"JMPr">, PredNewRel;
1431 let isReturn = 1, isCodeGenOnly = 1 in
1432 defm JMPret : JMPR_base<"JMPret">, PredNewRel;
1435 def: Pat<(br bb:$dst),
1436 (J2_jump brtarget:$dst)>;
1438 (JMPret (i32 R31))>;
1439 def: Pat<(brcond (i1 PredRegs:$src1), bb:$offset),
1440 (J2_jumpt PredRegs:$src1, bb:$offset)>;
1442 // A return through builtin_eh_return.
1443 let isReturn = 1, isTerminator = 1, isBarrier = 1, hasSideEffects = 0,
1444 isCodeGenOnly = 1, Defs = [PC], Uses = [R28], isPredicable = 0 in
1445 def EH_RETURN_JMPR : T_JMPr;
1447 def: Pat<(eh_return),
1448 (EH_RETURN_JMPR (i32 R31))>;
1449 def: Pat<(HexagonBR_JT (i32 IntRegs:$dst)),
1450 (J2_jumpr IntRegs:$dst)>;
1451 def: Pat<(brind (i32 IntRegs:$dst)),
1452 (J2_jumpr IntRegs:$dst)>;
1454 //===----------------------------------------------------------------------===//
1456 //===----------------------------------------------------------------------===//
1458 //===----------------------------------------------------------------------===//
1460 //===----------------------------------------------------------------------===//
1461 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, AddedComplexity = 20 in
1462 class T_load_io <string mnemonic, RegisterClass RC, bits<4> MajOp,
1464 : LDInst<(outs RC:$dst), (ins IntRegs:$src1, ImmOp:$offset),
1465 "$dst = "#mnemonic#"($src1 + #$offset)", []>, AddrModeRel {
1470 bits<11> offsetBits;
1472 string ImmOpStr = !cast<string>(ImmOp);
1473 let offsetBits = !if (!eq(ImmOpStr, "s11_3Ext"), offset{13-3},
1474 !if (!eq(ImmOpStr, "s11_2Ext"), offset{12-2},
1475 !if (!eq(ImmOpStr, "s11_1Ext"), offset{11-1},
1476 /* s11_0Ext */ offset{10-0})));
1477 let opExtentBits = !if (!eq(ImmOpStr, "s11_3Ext"), 14,
1478 !if (!eq(ImmOpStr, "s11_2Ext"), 13,
1479 !if (!eq(ImmOpStr, "s11_1Ext"), 12,
1480 /* s11_0Ext */ 11)));
1481 let hasNewValue = !if (!eq(ImmOpStr, "s11_3Ext"), 0, 1);
1483 let IClass = 0b1001;
1486 let Inst{26-25} = offsetBits{10-9};
1487 let Inst{24-21} = MajOp;
1488 let Inst{20-16} = src1;
1489 let Inst{13-5} = offsetBits{8-0};
1490 let Inst{4-0} = dst;
1493 let opExtendable = 3, isExtentSigned = 0, isPredicated = 1 in
1494 class T_pload_io <string mnemonic, RegisterClass RC, bits<4>MajOp,
1495 Operand ImmOp, bit isNot, bit isPredNew>
1496 : LDInst<(outs RC:$dst),
1497 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset),
1498 "if ("#!if(isNot, "!$src1", "$src1")
1499 #!if(isPredNew, ".new", "")
1500 #") $dst = "#mnemonic#"($src2 + #$offset)",
1501 [],"", V2LDST_tc_ld_SLOT01> , AddrModeRel {
1507 string ImmOpStr = !cast<string>(ImmOp);
1509 let offsetBits = !if (!eq(ImmOpStr, "u6_3Ext"), offset{8-3},
1510 !if (!eq(ImmOpStr, "u6_2Ext"), offset{7-2},
1511 !if (!eq(ImmOpStr, "u6_1Ext"), offset{6-1},
1512 /* u6_0Ext */ offset{5-0})));
1513 let opExtentBits = !if (!eq(ImmOpStr, "u6_3Ext"), 9,
1514 !if (!eq(ImmOpStr, "u6_2Ext"), 8,
1515 !if (!eq(ImmOpStr, "u6_1Ext"), 7,
1517 let hasNewValue = !if (!eq(ImmOpStr, "u6_3Ext"), 0, 1);
1518 let isPredicatedNew = isPredNew;
1519 let isPredicatedFalse = isNot;
1521 let IClass = 0b0100;
1525 let Inst{26} = isNot;
1526 let Inst{25} = isPredNew;
1527 let Inst{24-21} = MajOp;
1528 let Inst{20-16} = src2;
1530 let Inst{12-11} = src1;
1531 let Inst{10-5} = offsetBits;
1532 let Inst{4-0} = dst;
1535 let isExtendable = 1, hasSideEffects = 0, addrMode = BaseImmOffset in
1536 multiclass LD_Idxd<string mnemonic, string CextOp, RegisterClass RC,
1537 Operand ImmOp, Operand predImmOp, bits<4>MajOp> {
1538 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed in {
1539 let isPredicable = 1 in
1540 def L2_#NAME#_io : T_load_io <mnemonic, RC, MajOp, ImmOp>;
1543 def L2_p#NAME#t_io : T_pload_io <mnemonic, RC, MajOp, predImmOp, 0, 0>;
1544 def L2_p#NAME#f_io : T_pload_io <mnemonic, RC, MajOp, predImmOp, 1, 0>;
1547 def L2_p#NAME#tnew_io : T_pload_io <mnemonic, RC, MajOp, predImmOp, 0, 1>;
1548 def L2_p#NAME#fnew_io : T_pload_io <mnemonic, RC, MajOp, predImmOp, 1, 1>;
1552 let accessSize = ByteAccess, isCodeGenOnly = 0 in {
1553 defm loadrb: LD_Idxd <"memb", "LDrib", IntRegs, s11_0Ext, u6_0Ext, 0b1000>;
1554 defm loadrub: LD_Idxd <"memub", "LDriub", IntRegs, s11_0Ext, u6_0Ext, 0b1001>;
1557 let accessSize = HalfWordAccess, opExtentAlign = 1, isCodeGenOnly = 0 in {
1558 defm loadrh: LD_Idxd <"memh", "LDrih", IntRegs, s11_1Ext, u6_1Ext, 0b1010>;
1559 defm loadruh: LD_Idxd <"memuh", "LDriuh", IntRegs, s11_1Ext, u6_1Ext, 0b1011>;
1562 let accessSize = WordAccess, opExtentAlign = 2, isCodeGenOnly = 0 in
1563 defm loadri: LD_Idxd <"memw", "LDriw", IntRegs, s11_2Ext, u6_2Ext, 0b1100>;
1565 let accessSize = DoubleWordAccess, opExtentAlign = 3, isCodeGenOnly = 0 in
1566 defm loadrd: LD_Idxd <"memd", "LDrid", DoubleRegs, s11_3Ext, u6_3Ext, 0b1110>;
1568 // Patterns to select load-indexed (i.e. load from base+offset).
1569 multiclass Loadx_pat<PatFrag Load, ValueType VT, PatLeaf ImmPred,
1571 def: Pat<(VT (Load AddrFI:$fi)), (VT (MI AddrFI:$fi, 0))>;
1572 def: Pat<(VT (Load (add (i32 IntRegs:$Rs), ImmPred:$Off))),
1573 (VT (MI IntRegs:$Rs, imm:$Off))>;
1574 def: Pat<(VT (Load (i32 IntRegs:$Rs))), (VT (MI IntRegs:$Rs, 0))>;
1577 let AddedComplexity = 20 in {
1578 defm: Loadx_pat<load, i32, s11_2ExtPred, L2_loadri_io>;
1579 defm: Loadx_pat<load, i64, s11_3ExtPred, L2_loadrd_io>;
1580 defm: Loadx_pat<atomic_load_8 , i32, s11_0ExtPred, L2_loadrub_io>;
1581 defm: Loadx_pat<atomic_load_16, i32, s11_1ExtPred, L2_loadruh_io>;
1582 defm: Loadx_pat<atomic_load_32, i32, s11_2ExtPred, L2_loadri_io>;
1583 defm: Loadx_pat<atomic_load_64, i64, s11_3ExtPred, L2_loadrd_io>;
1585 defm: Loadx_pat<extloadi1, i32, s11_0ExtPred, L2_loadrub_io>;
1586 defm: Loadx_pat<extloadi8, i32, s11_0ExtPred, L2_loadrub_io>;
1587 defm: Loadx_pat<extloadi16, i32, s11_1ExtPred, L2_loadruh_io>;
1588 defm: Loadx_pat<sextloadi8, i32, s11_0ExtPred, L2_loadrb_io>;
1589 defm: Loadx_pat<sextloadi16, i32, s11_1ExtPred, L2_loadrh_io>;
1590 defm: Loadx_pat<zextloadi1, i32, s11_0ExtPred, L2_loadrub_io>;
1591 defm: Loadx_pat<zextloadi8, i32, s11_0ExtPred, L2_loadrub_io>;
1592 defm: Loadx_pat<zextloadi16, i32, s11_1ExtPred, L2_loadruh_io>;
1596 // Sign-extending loads of i1 need to replicate the lowest bit throughout
1597 // the 32-bit value. Since the loaded value can only be 0 or 1, 0-v should
1599 let AddedComplexity = 20 in
1600 def: Pat<(i32 (sextloadi1 (i32 IntRegs:$Rs))),
1601 (SUB_ri 0, (L2_loadrub_io IntRegs:$Rs, 0))>;
1603 //===----------------------------------------------------------------------===//
1604 // Post increment load
1605 //===----------------------------------------------------------------------===//
1606 //===----------------------------------------------------------------------===//
1607 // Template class for non-predicated post increment loads with immediate offset.
1608 //===----------------------------------------------------------------------===//
1609 let hasSideEffects = 0, addrMode = PostInc in
1610 class T_load_pi <string mnemonic, RegisterClass RC, Operand ImmOp,
1612 : LDInstPI <(outs RC:$dst, IntRegs:$dst2),
1613 (ins IntRegs:$src1, ImmOp:$offset),
1614 "$dst = "#mnemonic#"($src1++#$offset)" ,
1623 string ImmOpStr = !cast<string>(ImmOp);
1624 let offsetBits = !if (!eq(ImmOpStr, "s4_3Imm"), offset{6-3},
1625 !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2},
1626 !if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1},
1627 /* s4_0Imm */ offset{3-0})));
1628 let hasNewValue = !if (!eq(ImmOpStr, "s4_3Imm"), 0, 1);
1630 let IClass = 0b1001;
1632 let Inst{27-25} = 0b101;
1633 let Inst{24-21} = MajOp;
1634 let Inst{20-16} = src1;
1635 let Inst{13-12} = 0b00;
1636 let Inst{8-5} = offsetBits;
1637 let Inst{4-0} = dst;
1640 //===----------------------------------------------------------------------===//
1641 // Template class for predicated post increment loads with immediate offset.
1642 //===----------------------------------------------------------------------===//
1643 let isPredicated = 1, hasSideEffects = 0, addrMode = PostInc in
1644 class T_pload_pi <string mnemonic, RegisterClass RC, Operand ImmOp,
1645 bits<4> MajOp, bit isPredNot, bit isPredNew >
1646 : LDInst <(outs RC:$dst, IntRegs:$dst2),
1647 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset),
1648 !if(isPredNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1649 ") ")#"$dst = "#mnemonic#"($src2++#$offset)",
1659 let isPredicatedNew = isPredNew;
1660 let isPredicatedFalse = isPredNot;
1662 string ImmOpStr = !cast<string>(ImmOp);
1663 let offsetBits = !if (!eq(ImmOpStr, "s4_3Imm"), offset{6-3},
1664 !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2},
1665 !if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1},
1666 /* s4_0Imm */ offset{3-0})));
1667 let hasNewValue = !if (!eq(ImmOpStr, "s4_3Imm"), 0, 1);
1669 let IClass = 0b1001;
1671 let Inst{27-25} = 0b101;
1672 let Inst{24-21} = MajOp;
1673 let Inst{20-16} = src2;
1675 let Inst{12} = isPredNew;
1676 let Inst{11} = isPredNot;
1677 let Inst{10-9} = src1;
1678 let Inst{8-5} = offsetBits;
1679 let Inst{4-0} = dst;
1682 //===----------------------------------------------------------------------===//
1683 // Multiclass for post increment loads with immediate offset.
1684 //===----------------------------------------------------------------------===//
1686 multiclass LD_PostInc <string mnemonic, string BaseOp, RegisterClass RC,
1687 Operand ImmOp, bits<4> MajOp> {
1688 let BaseOpcode = "POST_"#BaseOp in {
1689 let isPredicable = 1 in
1690 def L2_#NAME#_pi : T_load_pi < mnemonic, RC, ImmOp, MajOp>;
1693 def L2_p#NAME#t_pi : T_pload_pi < mnemonic, RC, ImmOp, MajOp, 0, 0>;
1694 def L2_p#NAME#f_pi : T_pload_pi < mnemonic, RC, ImmOp, MajOp, 1, 0>;
1697 def L2_p#NAME#tnew_pi : T_pload_pi < mnemonic, RC, ImmOp, MajOp, 0, 1>;
1698 def L2_p#NAME#fnew_pi : T_pload_pi < mnemonic, RC, ImmOp, MajOp, 1, 1>;
1702 // post increment byte loads with immediate offset
1703 let accessSize = ByteAccess, isCodeGenOnly = 0 in {
1704 defm loadrb : LD_PostInc <"memb", "LDrib", IntRegs, s4_0Imm, 0b1000>;
1705 defm loadrub : LD_PostInc <"memub", "LDriub", IntRegs, s4_0Imm, 0b1001>;
1708 // post increment halfword loads with immediate offset
1709 let accessSize = HalfWordAccess, opExtentAlign = 1, isCodeGenOnly = 0 in {
1710 defm loadrh : LD_PostInc <"memh", "LDrih", IntRegs, s4_1Imm, 0b1010>;
1711 defm loadruh : LD_PostInc <"memuh", "LDriuh", IntRegs, s4_1Imm, 0b1011>;
1714 // post increment word loads with immediate offset
1715 let accessSize = WordAccess, opExtentAlign = 2, isCodeGenOnly = 0 in
1716 defm loadri : LD_PostInc <"memw", "LDriw", IntRegs, s4_2Imm, 0b1100>;
1718 // post increment doubleword loads with immediate offset
1719 let accessSize = DoubleWordAccess, opExtentAlign = 3, isCodeGenOnly = 0 in
1720 defm loadrd : LD_PostInc <"memd", "LDrid", DoubleRegs, s4_3Imm, 0b1110>;
1722 //===----------------------------------------------------------------------===//
1723 // Template class for post increment loads with register offset.
1724 //===----------------------------------------------------------------------===//
1725 let hasSideEffects = 0, addrMode = PostInc in
1726 class T_load_pr <string mnemonic, RegisterClass RC, bits<4> MajOp,
1727 MemAccessSize AccessSz>
1728 : LDInstPI <(outs RC:$dst, IntRegs:$_dst_),
1729 (ins IntRegs:$src1, ModRegs:$src2),
1730 "$dst = "#mnemonic#"($src1++$src2)" ,
1731 [], "$src1 = $_dst_" > {
1736 let accessSize = AccessSz;
1737 let IClass = 0b1001;
1739 let Inst{27-25} = 0b110;
1740 let Inst{24-21} = MajOp;
1741 let Inst{20-16} = src1;
1742 let Inst{13} = src2;
1745 let Inst{4-0} = dst;
1748 let hasNewValue = 1, isCodeGenOnly = 0 in {
1749 def L2_loadrb_pr : T_load_pr <"memb", IntRegs, 0b1000, ByteAccess>;
1750 def L2_loadrub_pr : T_load_pr <"memub", IntRegs, 0b1001, ByteAccess>;
1751 def L2_loadrh_pr : T_load_pr <"memh", IntRegs, 0b1010, HalfWordAccess>;
1752 def L2_loadruh_pr : T_load_pr <"memuh", IntRegs, 0b1011, HalfWordAccess>;
1753 def L2_loadri_pr : T_load_pr <"memw", IntRegs, 0b1100, WordAccess>;
1756 let isCodeGenOnly = 0 in
1757 def L2_loadrd_pr : T_load_pr <"memd", DoubleRegs, 0b1110, DoubleWordAccess>;
1760 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 13,
1761 isPseudo = 1, Defs = [R10,R11,D5], hasSideEffects = 0 in
1762 def LDriw_pred : LDInst2<(outs PredRegs:$dst),
1764 "Error; should not emit",
1767 let Defs = [R29, R30, R31], Uses = [R30], hasSideEffects = 0, isCodeGenOnly = 0 in
1768 def L2_deallocframe : LDInst<(outs), (ins),
1771 let IClass = 0b1001;
1773 let Inst{27-16} = 0b000000011110;
1775 let Inst{4-0} = 0b11110;
1778 // Load / Post increment circular addressing mode.
1779 let Uses = [CS], hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in
1780 class T_load_pcr<string mnemonic, RegisterClass RC, bits<4> MajOp>
1781 : LDInst <(outs RC:$dst, IntRegs:$_dst_),
1782 (ins IntRegs:$Rz, ModRegs:$Mu),
1783 "$dst = "#mnemonic#"($Rz ++ I:circ($Mu))", [],
1789 let IClass = 0b1001;
1791 let Inst{27-25} = 0b100;
1792 let Inst{24-21} = MajOp;
1793 let Inst{20-16} = Rz;
1798 let Inst{4-0} = dst;
1801 let accessSize = ByteAccess, isCodeGenOnly = 0 in {
1802 def L2_loadrb_pcr : T_load_pcr <"memb", IntRegs, 0b1000>;
1803 def L2_loadrub_pcr : T_load_pcr <"memub", IntRegs, 0b1001>;
1806 let accessSize = HalfWordAccess, isCodeGenOnly = 0 in {
1807 def L2_loadrh_pcr : T_load_pcr <"memh", IntRegs, 0b1010>;
1808 def L2_loadruh_pcr : T_load_pcr <"memuh", IntRegs, 0b1011>;
1811 let accessSize = WordAccess, isCodeGenOnly = 0 in {
1812 def L2_loadri_pcr : T_load_pcr <"memw", IntRegs, 0b1100>;
1815 let accessSize = DoubleWordAccess, isCodeGenOnly = 0 in
1816 def L2_loadrd_pcr : T_load_pcr <"memd", DoubleRegs, 0b1110>;
1818 //===----------------------------------------------------------------------===//
1819 // Circular loads with immediate offset.
1820 //===----------------------------------------------------------------------===//
1821 let Uses = [CS], mayLoad = 1, hasSideEffects = 0, hasNewValue = 1 in
1822 class T_load_pci <string mnemonic, RegisterClass RC,
1823 Operand ImmOp, bits<4> MajOp>
1824 : LDInstPI<(outs RC:$dst, IntRegs:$_dst_),
1825 (ins IntRegs:$Rz, ImmOp:$offset, ModRegs:$Mu),
1826 "$dst = "#mnemonic#"($Rz ++ #$offset:circ($Mu))", [],
1834 string ImmOpStr = !cast<string>(ImmOp);
1835 let offsetBits = !if (!eq(ImmOpStr, "s4_3Imm"), offset{6-3},
1836 !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2},
1837 !if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1},
1838 /* s4_0Imm */ offset{3-0})));
1839 let IClass = 0b1001;
1840 let Inst{27-25} = 0b100;
1841 let Inst{24-21} = MajOp;
1842 let Inst{20-16} = Rz;
1846 let Inst{8-5} = offsetBits;
1847 let Inst{4-0} = dst;
1850 // Byte variants of circ load
1851 let accessSize = ByteAccess, isCodeGenOnly = 0 in {
1852 def L2_loadrb_pci : T_load_pci <"memb", IntRegs, s4_0Imm, 0b1000>;
1853 def L2_loadrub_pci : T_load_pci <"memub", IntRegs, s4_0Imm, 0b1001>;
1856 // Half word variants of circ load
1857 let accessSize = HalfWordAccess, isCodeGenOnly = 0 in {
1858 def L2_loadrh_pci : T_load_pci <"memh", IntRegs, s4_1Imm, 0b1010>;
1859 def L2_loadruh_pci : T_load_pci <"memuh", IntRegs, s4_1Imm, 0b1011>;
1862 // Word variants of circ load
1863 let accessSize = WordAccess, isCodeGenOnly = 0 in
1864 def L2_loadri_pci : T_load_pci <"memw", IntRegs, s4_2Imm, 0b1100>;
1866 let accessSize = DoubleWordAccess, hasNewValue = 0, isCodeGenOnly = 0 in
1867 def L2_loadrd_pci : T_load_pci <"memd", DoubleRegs, s4_3Imm, 0b1110>;
1869 // L[24]_load[wd]_locked: Load word/double with lock.
1871 class T_load_locked <string mnemonic, RegisterClass RC>
1872 : LD0Inst <(outs RC:$dst),
1874 "$dst = "#mnemonic#"($src)"> {
1877 let IClass = 0b1001;
1878 let Inst{27-21} = 0b0010000;
1879 let Inst{20-16} = src;
1880 let Inst{13-12} = !if (!eq(mnemonic, "memd_locked"), 0b01, 0b00);
1881 let Inst{4-0} = dst;
1883 let hasNewValue = 1, accessSize = WordAccess, opNewValue = 0, isCodeGenOnly = 0 in
1884 def L2_loadw_locked : T_load_locked <"memw_locked", IntRegs>;
1885 let accessSize = DoubleWordAccess, isCodeGenOnly = 0 in
1886 def L4_loadd_locked : T_load_locked <"memd_locked", DoubleRegs>;
1887 //===----------------------------------------------------------------------===//
1888 // Bit-reversed loads with auto-increment register
1889 //===----------------------------------------------------------------------===//
1890 let hasSideEffects = 0 in
1891 class T_load_pbr<string mnemonic, RegisterClass RC,
1892 MemAccessSize addrSize, bits<4> majOp>
1894 <(outs RC:$dst, IntRegs:$_dst_),
1895 (ins IntRegs:$Rz, ModRegs:$Mu),
1896 "$dst = "#mnemonic#"($Rz ++ $Mu:brev)" ,
1897 [] , "$Rz = $_dst_" > {
1899 let accessSize = addrSize;
1905 let IClass = 0b1001;
1907 let Inst{27-25} = 0b111;
1908 let Inst{24-21} = majOp;
1909 let Inst{20-16} = Rz;
1913 let Inst{4-0} = dst;
1916 let hasNewValue =1, opNewValue = 0, isCodeGenOnly = 0 in {
1917 def L2_loadrb_pbr : T_load_pbr <"memb", IntRegs, ByteAccess, 0b1000>;
1918 def L2_loadrub_pbr : T_load_pbr <"memub", IntRegs, ByteAccess, 0b1001>;
1919 def L2_loadrh_pbr : T_load_pbr <"memh", IntRegs, HalfWordAccess, 0b1010>;
1920 def L2_loadruh_pbr : T_load_pbr <"memuh", IntRegs, HalfWordAccess, 0b1011>;
1921 def L2_loadri_pbr : T_load_pbr <"memw", IntRegs, WordAccess, 0b1100>;
1924 let isCodeGenOnly = 0 in
1925 def L2_loadrd_pbr : T_load_pbr <"memd", DoubleRegs, DoubleWordAccess, 0b1110>;
1927 //===----------------------------------------------------------------------===//
1929 //===----------------------------------------------------------------------===//
1931 //===----------------------------------------------------------------------===//
1933 //===----------------------------------------------------------------------===//
1934 //===----------------------------------------------------------------------===//
1936 //===----------------------------------------------------------------------===//
1938 //===----------------------------------------------------------------------===//
1940 //===----------------------------------------------------------------------===//
1941 //===----------------------------------------------------------------------===//
1943 //===----------------------------------------------------------------------===//
1945 //===----------------------------------------------------------------------===//
1947 //===----------------------------------------------------------------------===//
1949 //===----------------------------------------------------------------------===//
1951 // MPYS / Multipy signed/unsigned halfwords
1952 //Rd=mpy[u](Rs.[H|L],Rt.[H|L])[:<<1][:rnd][:sat]
1953 //===----------------------------------------------------------------------===//
1955 let hasNewValue = 1, opNewValue = 0 in
1956 class T_M2_mpy < bits<2> LHbits, bit isSat, bit isRnd,
1957 bit hasShift, bit isUnsigned>
1958 : MInst < (outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt),
1959 "$Rd = "#!if(isUnsigned,"mpyu","mpy")#"($Rs."#!if(LHbits{1},"h","l")
1960 #", $Rt."#!if(LHbits{0},"h)","l)")
1961 #!if(hasShift,":<<1","")
1962 #!if(isRnd,":rnd","")
1963 #!if(isSat,":sat",""),
1964 [], "", M_tc_3x_SLOT23 > {
1969 let IClass = 0b1110;
1971 let Inst{27-24} = 0b1100;
1972 let Inst{23} = hasShift;
1973 let Inst{22} = isUnsigned;
1974 let Inst{21} = isRnd;
1975 let Inst{7} = isSat;
1976 let Inst{6-5} = LHbits;
1978 let Inst{20-16} = Rs;
1979 let Inst{12-8} = Rt;
1982 //Rd=mpy(Rs.[H|L],Rt.[H|L])[:<<1]
1983 let isCodeGenOnly = 0 in {
1984 def M2_mpy_ll_s1: T_M2_mpy<0b00, 0, 0, 1, 0>;
1985 def M2_mpy_ll_s0: T_M2_mpy<0b00, 0, 0, 0, 0>;
1986 def M2_mpy_lh_s1: T_M2_mpy<0b01, 0, 0, 1, 0>;
1987 def M2_mpy_lh_s0: T_M2_mpy<0b01, 0, 0, 0, 0>;
1988 def M2_mpy_hl_s1: T_M2_mpy<0b10, 0, 0, 1, 0>;
1989 def M2_mpy_hl_s0: T_M2_mpy<0b10, 0, 0, 0, 0>;
1990 def M2_mpy_hh_s1: T_M2_mpy<0b11, 0, 0, 1, 0>;
1991 def M2_mpy_hh_s0: T_M2_mpy<0b11, 0, 0, 0, 0>;
1994 //Rd=mpyu(Rs.[H|L],Rt.[H|L])[:<<1]
1995 let isCodeGenOnly = 0 in {
1996 def M2_mpyu_ll_s1: T_M2_mpy<0b00, 0, 0, 1, 1>;
1997 def M2_mpyu_ll_s0: T_M2_mpy<0b00, 0, 0, 0, 1>;
1998 def M2_mpyu_lh_s1: T_M2_mpy<0b01, 0, 0, 1, 1>;
1999 def M2_mpyu_lh_s0: T_M2_mpy<0b01, 0, 0, 0, 1>;
2000 def M2_mpyu_hl_s1: T_M2_mpy<0b10, 0, 0, 1, 1>;
2001 def M2_mpyu_hl_s0: T_M2_mpy<0b10, 0, 0, 0, 1>;
2002 def M2_mpyu_hh_s1: T_M2_mpy<0b11, 0, 0, 1, 1>;
2003 def M2_mpyu_hh_s0: T_M2_mpy<0b11, 0, 0, 0, 1>;
2006 //Rd=mpy(Rs.[H|L],Rt.[H|L])[:<<1]:rnd
2007 let isCodeGenOnly = 0 in {
2008 def M2_mpy_rnd_ll_s1: T_M2_mpy <0b00, 0, 1, 1, 0>;
2009 def M2_mpy_rnd_ll_s0: T_M2_mpy <0b00, 0, 1, 0, 0>;
2010 def M2_mpy_rnd_lh_s1: T_M2_mpy <0b01, 0, 1, 1, 0>;
2011 def M2_mpy_rnd_lh_s0: T_M2_mpy <0b01, 0, 1, 0, 0>;
2012 def M2_mpy_rnd_hl_s1: T_M2_mpy <0b10, 0, 1, 1, 0>;
2013 def M2_mpy_rnd_hl_s0: T_M2_mpy <0b10, 0, 1, 0, 0>;
2014 def M2_mpy_rnd_hh_s1: T_M2_mpy <0b11, 0, 1, 1, 0>;
2015 def M2_mpy_rnd_hh_s0: T_M2_mpy <0b11, 0, 1, 0, 0>;
2018 //Rd=mpy(Rs.[H|L],Rt.[H|L])[:<<1][:sat]
2019 //Rd=mpy(Rs.[H|L],Rt.[H|L])[:<<1][:rnd][:sat]
2020 let Defs = [USR_OVF], isCodeGenOnly = 0 in {
2021 def M2_mpy_sat_ll_s1: T_M2_mpy <0b00, 1, 0, 1, 0>;
2022 def M2_mpy_sat_ll_s0: T_M2_mpy <0b00, 1, 0, 0, 0>;
2023 def M2_mpy_sat_lh_s1: T_M2_mpy <0b01, 1, 0, 1, 0>;
2024 def M2_mpy_sat_lh_s0: T_M2_mpy <0b01, 1, 0, 0, 0>;
2025 def M2_mpy_sat_hl_s1: T_M2_mpy <0b10, 1, 0, 1, 0>;
2026 def M2_mpy_sat_hl_s0: T_M2_mpy <0b10, 1, 0, 0, 0>;
2027 def M2_mpy_sat_hh_s1: T_M2_mpy <0b11, 1, 0, 1, 0>;
2028 def M2_mpy_sat_hh_s0: T_M2_mpy <0b11, 1, 0, 0, 0>;
2030 def M2_mpy_sat_rnd_ll_s1: T_M2_mpy <0b00, 1, 1, 1, 0>;
2031 def M2_mpy_sat_rnd_ll_s0: T_M2_mpy <0b00, 1, 1, 0, 0>;
2032 def M2_mpy_sat_rnd_lh_s1: T_M2_mpy <0b01, 1, 1, 1, 0>;
2033 def M2_mpy_sat_rnd_lh_s0: T_M2_mpy <0b01, 1, 1, 0, 0>;
2034 def M2_mpy_sat_rnd_hl_s1: T_M2_mpy <0b10, 1, 1, 1, 0>;
2035 def M2_mpy_sat_rnd_hl_s0: T_M2_mpy <0b10, 1, 1, 0, 0>;
2036 def M2_mpy_sat_rnd_hh_s1: T_M2_mpy <0b11, 1, 1, 1, 0>;
2037 def M2_mpy_sat_rnd_hh_s0: T_M2_mpy <0b11, 1, 1, 0, 0>;
2040 //===----------------------------------------------------------------------===//
2042 // MPYS / Multipy signed/unsigned halfwords and add/subtract the
2043 // result from the accumulator.
2044 //Rx [-+]= mpy[u](Rs.[H|L],Rt.[H|L])[:<<1][:sat]
2045 //===----------------------------------------------------------------------===//
2047 let hasNewValue = 1, opNewValue = 0 in
2048 class T_M2_mpy_acc < bits<2> LHbits, bit isSat, bit isNac,
2049 bit hasShift, bit isUnsigned >
2050 : MInst_acc<(outs IntRegs:$Rx), (ins IntRegs:$dst2, IntRegs:$Rs, IntRegs:$Rt),
2051 "$Rx "#!if(isNac,"-= ","+= ")#!if(isUnsigned,"mpyu","mpy")
2052 #"($Rs."#!if(LHbits{1},"h","l")
2053 #", $Rt."#!if(LHbits{0},"h)","l)")
2054 #!if(hasShift,":<<1","")
2055 #!if(isSat,":sat",""),
2056 [], "$dst2 = $Rx", M_tc_3x_SLOT23 > {
2061 let IClass = 0b1110;
2062 let Inst{27-24} = 0b1110;
2063 let Inst{23} = hasShift;
2064 let Inst{22} = isUnsigned;
2065 let Inst{21} = isNac;
2066 let Inst{7} = isSat;
2067 let Inst{6-5} = LHbits;
2069 let Inst{20-16} = Rs;
2070 let Inst{12-8} = Rt;
2073 //Rx += mpy(Rs.[H|L],Rt.[H|L])[:<<1]
2074 let isCodeGenOnly = 0 in {
2075 def M2_mpy_acc_ll_s1: T_M2_mpy_acc <0b00, 0, 0, 1, 0>;
2076 def M2_mpy_acc_ll_s0: T_M2_mpy_acc <0b00, 0, 0, 0, 0>;
2077 def M2_mpy_acc_lh_s1: T_M2_mpy_acc <0b01, 0, 0, 1, 0>;
2078 def M2_mpy_acc_lh_s0: T_M2_mpy_acc <0b01, 0, 0, 0, 0>;
2079 def M2_mpy_acc_hl_s1: T_M2_mpy_acc <0b10, 0, 0, 1, 0>;
2080 def M2_mpy_acc_hl_s0: T_M2_mpy_acc <0b10, 0, 0, 0, 0>;
2081 def M2_mpy_acc_hh_s1: T_M2_mpy_acc <0b11, 0, 0, 1, 0>;
2082 def M2_mpy_acc_hh_s0: T_M2_mpy_acc <0b11, 0, 0, 0, 0>;
2085 //Rx += mpyu(Rs.[H|L],Rt.[H|L])[:<<1]
2086 let isCodeGenOnly = 0 in {
2087 def M2_mpyu_acc_ll_s1: T_M2_mpy_acc <0b00, 0, 0, 1, 1>;
2088 def M2_mpyu_acc_ll_s0: T_M2_mpy_acc <0b00, 0, 0, 0, 1>;
2089 def M2_mpyu_acc_lh_s1: T_M2_mpy_acc <0b01, 0, 0, 1, 1>;
2090 def M2_mpyu_acc_lh_s0: T_M2_mpy_acc <0b01, 0, 0, 0, 1>;
2091 def M2_mpyu_acc_hl_s1: T_M2_mpy_acc <0b10, 0, 0, 1, 1>;
2092 def M2_mpyu_acc_hl_s0: T_M2_mpy_acc <0b10, 0, 0, 0, 1>;
2093 def M2_mpyu_acc_hh_s1: T_M2_mpy_acc <0b11, 0, 0, 1, 1>;
2094 def M2_mpyu_acc_hh_s0: T_M2_mpy_acc <0b11, 0, 0, 0, 1>;
2097 //Rx -= mpy(Rs.[H|L],Rt.[H|L])[:<<1]
2098 let isCodeGenOnly = 0 in {
2099 def M2_mpy_nac_ll_s1: T_M2_mpy_acc <0b00, 0, 1, 1, 0>;
2100 def M2_mpy_nac_ll_s0: T_M2_mpy_acc <0b00, 0, 1, 0, 0>;
2101 def M2_mpy_nac_lh_s1: T_M2_mpy_acc <0b01, 0, 1, 1, 0>;
2102 def M2_mpy_nac_lh_s0: T_M2_mpy_acc <0b01, 0, 1, 0, 0>;
2103 def M2_mpy_nac_hl_s1: T_M2_mpy_acc <0b10, 0, 1, 1, 0>;
2104 def M2_mpy_nac_hl_s0: T_M2_mpy_acc <0b10, 0, 1, 0, 0>;
2105 def M2_mpy_nac_hh_s1: T_M2_mpy_acc <0b11, 0, 1, 1, 0>;
2106 def M2_mpy_nac_hh_s0: T_M2_mpy_acc <0b11, 0, 1, 0, 0>;
2109 //Rx -= mpyu(Rs.[H|L],Rt.[H|L])[:<<1]
2110 let isCodeGenOnly = 0 in {
2111 def M2_mpyu_nac_ll_s1: T_M2_mpy_acc <0b00, 0, 1, 1, 1>;
2112 def M2_mpyu_nac_ll_s0: T_M2_mpy_acc <0b00, 0, 1, 0, 1>;
2113 def M2_mpyu_nac_lh_s1: T_M2_mpy_acc <0b01, 0, 1, 1, 1>;
2114 def M2_mpyu_nac_lh_s0: T_M2_mpy_acc <0b01, 0, 1, 0, 1>;
2115 def M2_mpyu_nac_hl_s1: T_M2_mpy_acc <0b10, 0, 1, 1, 1>;
2116 def M2_mpyu_nac_hl_s0: T_M2_mpy_acc <0b10, 0, 1, 0, 1>;
2117 def M2_mpyu_nac_hh_s1: T_M2_mpy_acc <0b11, 0, 1, 1, 1>;
2118 def M2_mpyu_nac_hh_s0: T_M2_mpy_acc <0b11, 0, 1, 0, 1>;
2121 //Rx += mpy(Rs.[H|L],Rt.[H|L])[:<<1]:sat
2122 let isCodeGenOnly = 0 in {
2123 def M2_mpy_acc_sat_ll_s1: T_M2_mpy_acc <0b00, 1, 0, 1, 0>;
2124 def M2_mpy_acc_sat_ll_s0: T_M2_mpy_acc <0b00, 1, 0, 0, 0>;
2125 def M2_mpy_acc_sat_lh_s1: T_M2_mpy_acc <0b01, 1, 0, 1, 0>;
2126 def M2_mpy_acc_sat_lh_s0: T_M2_mpy_acc <0b01, 1, 0, 0, 0>;
2127 def M2_mpy_acc_sat_hl_s1: T_M2_mpy_acc <0b10, 1, 0, 1, 0>;
2128 def M2_mpy_acc_sat_hl_s0: T_M2_mpy_acc <0b10, 1, 0, 0, 0>;
2129 def M2_mpy_acc_sat_hh_s1: T_M2_mpy_acc <0b11, 1, 0, 1, 0>;
2130 def M2_mpy_acc_sat_hh_s0: T_M2_mpy_acc <0b11, 1, 0, 0, 0>;
2133 //Rx -= mpy(Rs.[H|L],Rt.[H|L])[:<<1]:sat
2134 let isCodeGenOnly = 0 in {
2135 def M2_mpy_nac_sat_ll_s1: T_M2_mpy_acc <0b00, 1, 1, 1, 0>;
2136 def M2_mpy_nac_sat_ll_s0: T_M2_mpy_acc <0b00, 1, 1, 0, 0>;
2137 def M2_mpy_nac_sat_lh_s1: T_M2_mpy_acc <0b01, 1, 1, 1, 0>;
2138 def M2_mpy_nac_sat_lh_s0: T_M2_mpy_acc <0b01, 1, 1, 0, 0>;
2139 def M2_mpy_nac_sat_hl_s1: T_M2_mpy_acc <0b10, 1, 1, 1, 0>;
2140 def M2_mpy_nac_sat_hl_s0: T_M2_mpy_acc <0b10, 1, 1, 0, 0>;
2141 def M2_mpy_nac_sat_hh_s1: T_M2_mpy_acc <0b11, 1, 1, 1, 0>;
2142 def M2_mpy_nac_sat_hh_s0: T_M2_mpy_acc <0b11, 1, 1, 0, 0>;
2145 //===----------------------------------------------------------------------===//
2147 // MPYS / Multipy signed/unsigned halfwords and add/subtract the
2148 // result from the 64-bit destination register.
2149 //Rxx [-+]= mpy[u](Rs.[H|L],Rt.[H|L])[:<<1][:sat]
2150 //===----------------------------------------------------------------------===//
2152 class T_M2_mpyd_acc < bits<2> LHbits, bit isNac, bit hasShift, bit isUnsigned>
2153 : MInst_acc<(outs DoubleRegs:$Rxx),
2154 (ins DoubleRegs:$dst2, IntRegs:$Rs, IntRegs:$Rt),
2155 "$Rxx "#!if(isNac,"-= ","+= ")#!if(isUnsigned,"mpyu","mpy")
2156 #"($Rs."#!if(LHbits{1},"h","l")
2157 #", $Rt."#!if(LHbits{0},"h)","l)")
2158 #!if(hasShift,":<<1",""),
2159 [], "$dst2 = $Rxx", M_tc_3x_SLOT23 > {
2164 let IClass = 0b1110;
2166 let Inst{27-24} = 0b0110;
2167 let Inst{23} = hasShift;
2168 let Inst{22} = isUnsigned;
2169 let Inst{21} = isNac;
2171 let Inst{6-5} = LHbits;
2172 let Inst{4-0} = Rxx;
2173 let Inst{20-16} = Rs;
2174 let Inst{12-8} = Rt;
2177 let isCodeGenOnly = 0 in {
2178 def M2_mpyd_acc_hh_s0: T_M2_mpyd_acc <0b11, 0, 0, 0>;
2179 def M2_mpyd_acc_hl_s0: T_M2_mpyd_acc <0b10, 0, 0, 0>;
2180 def M2_mpyd_acc_lh_s0: T_M2_mpyd_acc <0b01, 0, 0, 0>;
2181 def M2_mpyd_acc_ll_s0: T_M2_mpyd_acc <0b00, 0, 0, 0>;
2183 def M2_mpyd_acc_hh_s1: T_M2_mpyd_acc <0b11, 0, 1, 0>;
2184 def M2_mpyd_acc_hl_s1: T_M2_mpyd_acc <0b10, 0, 1, 0>;
2185 def M2_mpyd_acc_lh_s1: T_M2_mpyd_acc <0b01, 0, 1, 0>;
2186 def M2_mpyd_acc_ll_s1: T_M2_mpyd_acc <0b00, 0, 1, 0>;
2188 def M2_mpyd_nac_hh_s0: T_M2_mpyd_acc <0b11, 1, 0, 0>;
2189 def M2_mpyd_nac_hl_s0: T_M2_mpyd_acc <0b10, 1, 0, 0>;
2190 def M2_mpyd_nac_lh_s0: T_M2_mpyd_acc <0b01, 1, 0, 0>;
2191 def M2_mpyd_nac_ll_s0: T_M2_mpyd_acc <0b00, 1, 0, 0>;
2193 def M2_mpyd_nac_hh_s1: T_M2_mpyd_acc <0b11, 1, 1, 0>;
2194 def M2_mpyd_nac_hl_s1: T_M2_mpyd_acc <0b10, 1, 1, 0>;
2195 def M2_mpyd_nac_lh_s1: T_M2_mpyd_acc <0b01, 1, 1, 0>;
2196 def M2_mpyd_nac_ll_s1: T_M2_mpyd_acc <0b00, 1, 1, 0>;
2198 def M2_mpyud_acc_hh_s0: T_M2_mpyd_acc <0b11, 0, 0, 1>;
2199 def M2_mpyud_acc_hl_s0: T_M2_mpyd_acc <0b10, 0, 0, 1>;
2200 def M2_mpyud_acc_lh_s0: T_M2_mpyd_acc <0b01, 0, 0, 1>;
2201 def M2_mpyud_acc_ll_s0: T_M2_mpyd_acc <0b00, 0, 0, 1>;
2203 def M2_mpyud_acc_hh_s1: T_M2_mpyd_acc <0b11, 0, 1, 1>;
2204 def M2_mpyud_acc_hl_s1: T_M2_mpyd_acc <0b10, 0, 1, 1>;
2205 def M2_mpyud_acc_lh_s1: T_M2_mpyd_acc <0b01, 0, 1, 1>;
2206 def M2_mpyud_acc_ll_s1: T_M2_mpyd_acc <0b00, 0, 1, 1>;
2208 def M2_mpyud_nac_hh_s0: T_M2_mpyd_acc <0b11, 1, 0, 1>;
2209 def M2_mpyud_nac_hl_s0: T_M2_mpyd_acc <0b10, 1, 0, 1>;
2210 def M2_mpyud_nac_lh_s0: T_M2_mpyd_acc <0b01, 1, 0, 1>;
2211 def M2_mpyud_nac_ll_s0: T_M2_mpyd_acc <0b00, 1, 0, 1>;
2213 def M2_mpyud_nac_hh_s1: T_M2_mpyd_acc <0b11, 1, 1, 1>;
2214 def M2_mpyud_nac_hl_s1: T_M2_mpyd_acc <0b10, 1, 1, 1>;
2215 def M2_mpyud_nac_lh_s1: T_M2_mpyd_acc <0b01, 1, 1, 1>;
2216 def M2_mpyud_nac_ll_s1: T_M2_mpyd_acc <0b00, 1, 1, 1>;
2219 let hasNewValue = 1, opNewValue = 0 in
2220 class T_MType_mpy <string mnemonic, bits<4> RegTyBits, RegisterClass RC,
2221 bits<3> MajOp, bits<3> MinOp, bit isSat = 0, bit isRnd = 0,
2222 string op2Suffix = "", bit isRaw = 0, bit isHi = 0 >
2223 : MInst <(outs IntRegs:$dst), (ins RC:$src1, RC:$src2),
2225 #"($src1, $src2"#op2Suffix#")"
2226 #!if(MajOp{2}, ":<<1", "")
2227 #!if(isRnd, ":rnd", "")
2228 #!if(isSat, ":sat", "")
2229 #!if(isRaw, !if(isHi, ":raw:hi", ":raw:lo"), ""), [] > {
2234 let IClass = 0b1110;
2236 let Inst{27-24} = RegTyBits;
2237 let Inst{23-21} = MajOp;
2238 let Inst{20-16} = src1;
2240 let Inst{12-8} = src2;
2241 let Inst{7-5} = MinOp;
2242 let Inst{4-0} = dst;
2245 class T_MType_dd <string mnemonic, bits<3> MajOp, bits<3> MinOp,
2246 bit isSat = 0, bit isRnd = 0 >
2247 : T_MType_mpy <mnemonic, 0b1001, DoubleRegs, MajOp, MinOp, isSat, isRnd>;
2249 class T_MType_rr1 <string mnemonic, bits<3> MajOp, bits<3> MinOp,
2250 bit isSat = 0, bit isRnd = 0 >
2251 : T_MType_mpy<mnemonic, 0b1101, IntRegs, MajOp, MinOp, isSat, isRnd>;
2253 class T_MType_rr2 <string mnemonic, bits<3> MajOp, bits<3> MinOp,
2254 bit isSat = 0, bit isRnd = 0, string op2str = "" >
2255 : T_MType_mpy<mnemonic, 0b1101, IntRegs, MajOp, MinOp, isSat, isRnd, op2str>;
2257 let CextOpcode = "mpyi", InputType = "reg", isCodeGenOnly = 0 in
2258 def M2_mpyi : T_MType_rr1 <"mpyi", 0b000, 0b000>, ImmRegRel;
2260 let isCodeGenOnly = 0 in {
2261 def M2_mpy_up : T_MType_rr1 <"mpy", 0b000, 0b001>;
2262 def M2_mpyu_up : T_MType_rr1 <"mpyu", 0b010, 0b001>;
2265 let isCodeGenOnly = 0 in
2266 def M2_dpmpyss_rnd_s0 : T_MType_rr1 <"mpy", 0b001, 0b001, 0, 1>;
2268 let isCodeGenOnly = 0 in {
2269 def M2_hmmpyh_rs1 : T_MType_rr2 <"mpy", 0b101, 0b100, 1, 1, ".h">;
2270 def M2_hmmpyl_rs1 : T_MType_rr2 <"mpy", 0b111, 0b100, 1, 1, ".l">;
2274 let isCodeGenOnly = 0 in {
2275 def M2_mpysu_up : T_MType_rr1 <"mpysu", 0b011, 0b001, 0>;
2276 def M2_mpy_up_s1 : T_MType_rr1 <"mpy", 0b101, 0b010, 0>;
2277 def M2_mpy_up_s1_sat : T_MType_rr1 <"mpy", 0b111, 0b000, 1>;
2279 def M2_hmmpyh_s1 : T_MType_rr2 <"mpy", 0b101, 0b000, 1, 0, ".h">;
2280 def M2_hmmpyl_s1 : T_MType_rr2 <"mpy", 0b101, 0b001, 1, 0, ".l">;
2283 def: Pat<(i32 (mul I32:$src1, I32:$src2)), (M2_mpyi I32:$src1, I32:$src2)>;
2284 def: Pat<(i32 (mulhs I32:$src1, I32:$src2)), (M2_mpy_up I32:$src1, I32:$src2)>;
2285 def: Pat<(i32 (mulhu I32:$src1, I32:$src2)), (M2_mpyu_up I32:$src1, I32:$src2)>;
2287 let hasNewValue = 1, opNewValue = 0 in
2288 class T_MType_mpy_ri <bit isNeg, Operand ImmOp, list<dag> pattern>
2289 : MInst < (outs IntRegs:$Rd), (ins IntRegs:$Rs, ImmOp:$u8),
2290 "$Rd ="#!if(isNeg, "- ", "+ ")#"mpyi($Rs, #$u8)" ,
2291 pattern, "", M_tc_3x_SLOT23> {
2296 let IClass = 0b1110;
2298 let Inst{27-24} = 0b0000;
2299 let Inst{23} = isNeg;
2302 let Inst{20-16} = Rs;
2303 let Inst{12-5} = u8;
2306 let isExtendable = 1, opExtentBits = 8, opExtendable = 2, isCodeGenOnly = 0 in
2307 def M2_mpysip : T_MType_mpy_ri <0, u8Ext,
2308 [(set (i32 IntRegs:$Rd), (mul IntRegs:$Rs, u8ExtPred:$u8))]>;
2310 let isCodeGenOnly = 0 in
2311 def M2_mpysin : T_MType_mpy_ri <1, u8Imm,
2312 [(set (i32 IntRegs:$Rd), (ineg (mul IntRegs:$Rs,
2315 // Assember mapped to M2_mpyi
2316 let isAsmParserOnly = 1 in
2317 def M2_mpyui : MInst<(outs IntRegs:$dst),
2318 (ins IntRegs:$src1, IntRegs:$src2),
2319 "$dst = mpyui($src1, $src2)">;
2322 // s9 is NOT the same as m9 - but it works.. so far.
2323 // Assembler maps to either Rd=+mpyi(Rs,#u8) or Rd=-mpyi(Rs,#u8)
2324 // depending on the value of m9. See Arch Spec.
2325 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 9,
2326 CextOpcode = "mpyi", InputType = "imm", hasNewValue = 1 in
2327 def M2_mpysmi : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, s9Ext:$src2),
2328 "$dst = mpyi($src1, #$src2)",
2329 [(set (i32 IntRegs:$dst), (mul (i32 IntRegs:$src1),
2330 s9ExtPred:$src2))]>, ImmRegRel;
2332 let hasNewValue = 1, isExtendable = 1, opExtentBits = 8, opExtendable = 3,
2333 InputType = "imm" in
2334 class T_MType_acc_ri <string mnemonic, bits<3> MajOp, Operand ImmOp,
2335 list<dag> pattern = []>
2336 : MInst < (outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2, ImmOp:$src3),
2337 "$dst "#mnemonic#"($src2, #$src3)",
2338 pattern, "$src1 = $dst", M_tc_2_SLOT23> {
2343 let IClass = 0b1110;
2345 let Inst{27-26} = 0b00;
2346 let Inst{25-23} = MajOp;
2347 let Inst{20-16} = src2;
2349 let Inst{12-5} = src3;
2350 let Inst{4-0} = dst;
2353 let InputType = "reg", hasNewValue = 1 in
2354 class T_MType_acc_rr <string mnemonic, bits<3> MajOp, bits<3> MinOp,
2355 bit isSwap = 0, list<dag> pattern = [], bit hasNot = 0,
2356 bit isSat = 0, bit isShift = 0>
2357 : MInst < (outs IntRegs:$dst),
2358 (ins IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
2359 "$dst "#mnemonic#"($src2, "#!if(hasNot, "~$src3)","$src3)")
2360 #!if(isShift, ":<<1", "")
2361 #!if(isSat, ":sat", ""),
2362 pattern, "$src1 = $dst", M_tc_2_SLOT23 > {
2367 let IClass = 0b1110;
2369 let Inst{27-24} = 0b1111;
2370 let Inst{23-21} = MajOp;
2371 let Inst{20-16} = !if(isSwap, src3, src2);
2373 let Inst{12-8} = !if(isSwap, src2, src3);
2374 let Inst{7-5} = MinOp;
2375 let Inst{4-0} = dst;
2378 let CextOpcode = "MPYI_acc", Itinerary = M_tc_3x_SLOT23, isCodeGenOnly = 0 in {
2379 def M2_macsip : T_MType_acc_ri <"+= mpyi", 0b010, u8Ext,
2380 [(set (i32 IntRegs:$dst),
2381 (add (mul IntRegs:$src2, u8ExtPred:$src3),
2382 IntRegs:$src1))]>, ImmRegRel;
2384 def M2_maci : T_MType_acc_rr <"+= mpyi", 0b000, 0b000, 0,
2385 [(set (i32 IntRegs:$dst),
2386 (add (mul IntRegs:$src2, IntRegs:$src3),
2387 IntRegs:$src1))]>, ImmRegRel;
2390 let CextOpcode = "ADD_acc", isCodeGenOnly = 0 in {
2391 let isExtentSigned = 1 in
2392 def M2_accii : T_MType_acc_ri <"+= add", 0b100, s8Ext,
2393 [(set (i32 IntRegs:$dst),
2394 (add (add (i32 IntRegs:$src2), s8_16ExtPred:$src3),
2395 (i32 IntRegs:$src1)))]>, ImmRegRel;
2397 def M2_acci : T_MType_acc_rr <"+= add", 0b000, 0b001, 0,
2398 [(set (i32 IntRegs:$dst),
2399 (add (add (i32 IntRegs:$src2), (i32 IntRegs:$src3)),
2400 (i32 IntRegs:$src1)))]>, ImmRegRel;
2403 let CextOpcode = "SUB_acc", isCodeGenOnly = 0 in {
2404 let isExtentSigned = 1 in
2405 def M2_naccii : T_MType_acc_ri <"-= add", 0b101, s8Ext>, ImmRegRel;
2407 def M2_nacci : T_MType_acc_rr <"-= add", 0b100, 0b001, 0>, ImmRegRel;
2410 let Itinerary = M_tc_3x_SLOT23, isCodeGenOnly = 0 in
2411 def M2_macsin : T_MType_acc_ri <"-= mpyi", 0b011, u8Ext>;
2413 let isCodeGenOnly = 0 in {
2414 def M2_xor_xacc : T_MType_acc_rr < "^= xor", 0b100, 0b011, 0>;
2415 def M2_subacc : T_MType_acc_rr <"+= sub", 0b000, 0b011, 1>;
2418 class T_MType_acc_pat1 <InstHexagon MI, SDNode firstOp, SDNode secOp,
2420 : Pat <(secOp IntRegs:$src1, (firstOp IntRegs:$src2, ImmPred:$src3)),
2421 (MI IntRegs:$src1, IntRegs:$src2, ImmPred:$src3)>;
2423 class T_MType_acc_pat2 <InstHexagon MI, SDNode firstOp, SDNode secOp>
2424 : Pat <(i32 (secOp IntRegs:$src1, (firstOp IntRegs:$src2, IntRegs:$src3))),
2425 (MI IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
2427 def : T_MType_acc_pat2 <M2_xor_xacc, xor, xor>;
2428 def : T_MType_acc_pat1 <M2_macsin, mul, sub, u8ExtPred>;
2430 def : T_MType_acc_pat1 <M2_naccii, add, sub, s8_16ExtPred>;
2431 def : T_MType_acc_pat2 <M2_nacci, add, sub>;
2432 //===----------------------------------------------------------------------===//
2433 // Template Class -- Multiply signed/unsigned halfwords with and without
2434 // saturation and rounding
2435 //===----------------------------------------------------------------------===//
2436 class T_M2_mpyd < bits<2> LHbits, bit isRnd, bit hasShift, bit isUnsigned >
2437 : MInst < (outs DoubleRegs:$Rdd), (ins IntRegs:$Rs, IntRegs:$Rt),
2438 "$Rdd = "#!if(isUnsigned,"mpyu","mpy")#"($Rs."#!if(LHbits{1},"h","l")
2439 #", $Rt."#!if(LHbits{0},"h)","l)")
2440 #!if(hasShift,":<<1","")
2441 #!if(isRnd,":rnd",""),
2447 let IClass = 0b1110;
2449 let Inst{27-24} = 0b0100;
2450 let Inst{23} = hasShift;
2451 let Inst{22} = isUnsigned;
2452 let Inst{21} = isRnd;
2453 let Inst{6-5} = LHbits;
2454 let Inst{4-0} = Rdd;
2455 let Inst{20-16} = Rs;
2456 let Inst{12-8} = Rt;
2459 let isCodeGenOnly = 0 in {
2460 def M2_mpyd_hh_s0: T_M2_mpyd<0b11, 0, 0, 0>;
2461 def M2_mpyd_hl_s0: T_M2_mpyd<0b10, 0, 0, 0>;
2462 def M2_mpyd_lh_s0: T_M2_mpyd<0b01, 0, 0, 0>;
2463 def M2_mpyd_ll_s0: T_M2_mpyd<0b00, 0, 0, 0>;
2465 def M2_mpyd_hh_s1: T_M2_mpyd<0b11, 0, 1, 0>;
2466 def M2_mpyd_hl_s1: T_M2_mpyd<0b10, 0, 1, 0>;
2467 def M2_mpyd_lh_s1: T_M2_mpyd<0b01, 0, 1, 0>;
2468 def M2_mpyd_ll_s1: T_M2_mpyd<0b00, 0, 1, 0>;
2470 def M2_mpyd_rnd_hh_s0: T_M2_mpyd<0b11, 1, 0, 0>;
2471 def M2_mpyd_rnd_hl_s0: T_M2_mpyd<0b10, 1, 0, 0>;
2472 def M2_mpyd_rnd_lh_s0: T_M2_mpyd<0b01, 1, 0, 0>;
2473 def M2_mpyd_rnd_ll_s0: T_M2_mpyd<0b00, 1, 0, 0>;
2475 def M2_mpyd_rnd_hh_s1: T_M2_mpyd<0b11, 1, 1, 0>;
2476 def M2_mpyd_rnd_hl_s1: T_M2_mpyd<0b10, 1, 1, 0>;
2477 def M2_mpyd_rnd_lh_s1: T_M2_mpyd<0b01, 1, 1, 0>;
2478 def M2_mpyd_rnd_ll_s1: T_M2_mpyd<0b00, 1, 1, 0>;
2480 //Rdd=mpyu(Rs.[HL],Rt.[HL])[:<<1]
2481 def M2_mpyud_hh_s0: T_M2_mpyd<0b11, 0, 0, 1>;
2482 def M2_mpyud_hl_s0: T_M2_mpyd<0b10, 0, 0, 1>;
2483 def M2_mpyud_lh_s0: T_M2_mpyd<0b01, 0, 0, 1>;
2484 def M2_mpyud_ll_s0: T_M2_mpyd<0b00, 0, 0, 1>;
2486 def M2_mpyud_hh_s1: T_M2_mpyd<0b11, 0, 1, 1>;
2487 def M2_mpyud_hl_s1: T_M2_mpyd<0b10, 0, 1, 1>;
2488 def M2_mpyud_lh_s1: T_M2_mpyd<0b01, 0, 1, 1>;
2489 def M2_mpyud_ll_s1: T_M2_mpyd<0b00, 0, 1, 1>;
2491 //===----------------------------------------------------------------------===//
2492 // Template Class for xtype mpy:
2495 // multiply 32X32 and use full result
2496 //===----------------------------------------------------------------------===//
2497 let hasSideEffects = 0 in
2498 class T_XTYPE_mpy64 <string mnemonic, bits<3> MajOp, bits<3> MinOp,
2499 bit isSat, bit hasShift, bit isConj>
2500 : MInst <(outs DoubleRegs:$Rdd),
2501 (ins IntRegs:$Rs, IntRegs:$Rt),
2502 "$Rdd = "#mnemonic#"($Rs, $Rt"#!if(isConj,"*)",")")
2503 #!if(hasShift,":<<1","")
2504 #!if(isSat,":sat",""),
2510 let IClass = 0b1110;
2512 let Inst{27-24} = 0b0101;
2513 let Inst{23-21} = MajOp;
2514 let Inst{20-16} = Rs;
2515 let Inst{12-8} = Rt;
2516 let Inst{7-5} = MinOp;
2517 let Inst{4-0} = Rdd;
2520 //===----------------------------------------------------------------------===//
2521 // Template Class for xtype mpy with accumulation into 64-bit:
2524 // multiply 32X32 and use full result
2525 //===----------------------------------------------------------------------===//
2526 class T_XTYPE_mpy64_acc <string op1, string op2, bits<3> MajOp, bits<3> MinOp,
2527 bit isSat, bit hasShift, bit isConj>
2528 : MInst <(outs DoubleRegs:$Rxx),
2529 (ins DoubleRegs:$dst2, IntRegs:$Rs, IntRegs:$Rt),
2530 "$Rxx "#op2#"= "#op1#"($Rs, $Rt"#!if(isConj,"*)",")")
2531 #!if(hasShift,":<<1","")
2532 #!if(isSat,":sat",""),
2534 [] , "$dst2 = $Rxx" > {
2539 let IClass = 0b1110;
2541 let Inst{27-24} = 0b0111;
2542 let Inst{23-21} = MajOp;
2543 let Inst{20-16} = Rs;
2544 let Inst{12-8} = Rt;
2545 let Inst{7-5} = MinOp;
2546 let Inst{4-0} = Rxx;
2549 // MPY - Multiply and use full result
2550 // Rdd = mpy[u](Rs,Rt)
2551 let isCodeGenOnly = 0 in {
2552 def M2_dpmpyss_s0 : T_XTYPE_mpy64 < "mpy", 0b000, 0b000, 0, 0, 0>;
2553 def M2_dpmpyuu_s0 : T_XTYPE_mpy64 < "mpyu", 0b010, 0b000, 0, 0, 0>;
2555 // Rxx[+-]= mpy[u](Rs,Rt)
2556 def M2_dpmpyss_acc_s0 : T_XTYPE_mpy64_acc < "mpy", "+", 0b000, 0b000, 0, 0, 0>;
2557 def M2_dpmpyss_nac_s0 : T_XTYPE_mpy64_acc < "mpy", "-", 0b001, 0b000, 0, 0, 0>;
2558 def M2_dpmpyuu_acc_s0 : T_XTYPE_mpy64_acc < "mpyu", "+", 0b010, 0b000, 0, 0, 0>;
2559 def M2_dpmpyuu_nac_s0 : T_XTYPE_mpy64_acc < "mpyu", "-", 0b011, 0b000, 0, 0, 0>;
2562 def: Pat<(i64 (mul (i64 (anyext (i32 IntRegs:$src1))),
2563 (i64 (anyext (i32 IntRegs:$src2))))),
2564 (M2_dpmpyuu_s0 IntRegs:$src1, IntRegs:$src2)>;
2566 def: Pat<(i64 (mul (i64 (sext (i32 IntRegs:$src1))),
2567 (i64 (sext (i32 IntRegs:$src2))))),
2568 (M2_dpmpyss_s0 IntRegs:$src1, IntRegs:$src2)>;
2570 def: Pat<(i64 (mul (is_sext_i32:$src1),
2571 (is_sext_i32:$src2))),
2572 (M2_dpmpyss_s0 (LoReg DoubleRegs:$src1), (LoReg DoubleRegs:$src2))>;
2574 // Multiply and accumulate, use full result.
2575 // Rxx[+-]=mpy(Rs,Rt)
2577 def: Pat<(i64 (add (i64 DoubleRegs:$src1),
2578 (mul (i64 (sext (i32 IntRegs:$src2))),
2579 (i64 (sext (i32 IntRegs:$src3)))))),
2580 (M2_dpmpyss_acc_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
2582 def: Pat<(i64 (sub (i64 DoubleRegs:$src1),
2583 (mul (i64 (sext (i32 IntRegs:$src2))),
2584 (i64 (sext (i32 IntRegs:$src3)))))),
2585 (M2_dpmpyss_nac_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
2587 def: Pat<(i64 (add (i64 DoubleRegs:$src1),
2588 (mul (i64 (anyext (i32 IntRegs:$src2))),
2589 (i64 (anyext (i32 IntRegs:$src3)))))),
2590 (M2_dpmpyuu_acc_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
2592 def: Pat<(i64 (add (i64 DoubleRegs:$src1),
2593 (mul (i64 (zext (i32 IntRegs:$src2))),
2594 (i64 (zext (i32 IntRegs:$src3)))))),
2595 (M2_dpmpyuu_acc_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
2597 def: Pat<(i64 (sub (i64 DoubleRegs:$src1),
2598 (mul (i64 (anyext (i32 IntRegs:$src2))),
2599 (i64 (anyext (i32 IntRegs:$src3)))))),
2600 (M2_dpmpyuu_nac_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
2602 def: Pat<(i64 (sub (i64 DoubleRegs:$src1),
2603 (mul (i64 (zext (i32 IntRegs:$src2))),
2604 (i64 (zext (i32 IntRegs:$src3)))))),
2605 (M2_dpmpyuu_nac_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
2607 //===----------------------------------------------------------------------===//
2609 //===----------------------------------------------------------------------===//
2611 //===----------------------------------------------------------------------===//
2613 //===----------------------------------------------------------------------===//
2614 //===----------------------------------------------------------------------===//
2616 //===----------------------------------------------------------------------===//
2618 //===----------------------------------------------------------------------===//
2620 //===----------------------------------------------------------------------===//
2621 //===----------------------------------------------------------------------===//
2623 //===----------------------------------------------------------------------===//
2625 //===----------------------------------------------------------------------===//
2627 //===----------------------------------------------------------------------===//
2628 //===----------------------------------------------------------------------===//
2630 //===----------------------------------------------------------------------===//
2632 //===----------------------------------------------------------------------===//
2634 //===----------------------------------------------------------------------===//
2636 // Store doubleword.
2637 //===----------------------------------------------------------------------===//
2638 // Template class for non-predicated post increment stores with immediate offset
2639 //===----------------------------------------------------------------------===//
2640 let isPredicable = 1, hasSideEffects = 0, addrMode = PostInc in
2641 class T_store_pi <string mnemonic, RegisterClass RC, Operand ImmOp,
2642 bits<4> MajOp, bit isHalf >
2643 : STInst <(outs IntRegs:$_dst_),
2644 (ins IntRegs:$src1, ImmOp:$offset, RC:$src2),
2645 mnemonic#"($src1++#$offset) = $src2"#!if(isHalf, ".h", ""),
2646 [], "$src1 = $_dst_" >,
2653 string ImmOpStr = !cast<string>(ImmOp);
2654 let offsetBits = !if (!eq(ImmOpStr, "s4_3Imm"), offset{6-3},
2655 !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2},
2656 !if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1},
2657 /* s4_0Imm */ offset{3-0})));
2658 let isNVStorable = !if (!eq(ImmOpStr, "s4_3Imm"), 0, 1);
2660 let IClass = 0b1010;
2662 let Inst{27-25} = 0b101;
2663 let Inst{24-21} = MajOp;
2664 let Inst{20-16} = src1;
2666 let Inst{12-8} = src2;
2668 let Inst{6-3} = offsetBits;
2672 //===----------------------------------------------------------------------===//
2673 // Template class for predicated post increment stores with immediate offset
2674 //===----------------------------------------------------------------------===//
2675 let isPredicated = 1, hasSideEffects = 0, addrMode = PostInc in
2676 class T_pstore_pi <string mnemonic, RegisterClass RC, Operand ImmOp,
2677 bits<4> MajOp, bit isHalf, bit isPredNot, bit isPredNew >
2678 : STInst <(outs IntRegs:$_dst_),
2679 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset, RC:$src3),
2680 !if(isPredNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
2681 ") ")#mnemonic#"($src2++#$offset) = $src3"#!if(isHalf, ".h", ""),
2682 [], "$src2 = $_dst_" >,
2690 string ImmOpStr = !cast<string>(ImmOp);
2691 let offsetBits = !if (!eq(ImmOpStr, "s4_3Imm"), offset{6-3},
2692 !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2},
2693 !if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1},
2694 /* s4_0Imm */ offset{3-0})));
2696 let isNVStorable = !if (!eq(ImmOpStr, "s4_3Imm"), 0, 1);
2697 let isPredicatedNew = isPredNew;
2698 let isPredicatedFalse = isPredNot;
2700 let IClass = 0b1010;
2702 let Inst{27-25} = 0b101;
2703 let Inst{24-21} = MajOp;
2704 let Inst{20-16} = src2;
2706 let Inst{12-8} = src3;
2707 let Inst{7} = isPredNew;
2708 let Inst{6-3} = offsetBits;
2709 let Inst{2} = isPredNot;
2710 let Inst{1-0} = src1;
2713 multiclass ST_PostInc<string mnemonic, string BaseOp, RegisterClass RC,
2714 Operand ImmOp, bits<4> MajOp, bit isHalf = 0 > {
2716 let BaseOpcode = "POST_"#BaseOp in {
2717 def S2_#NAME#_pi : T_store_pi <mnemonic, RC, ImmOp, MajOp, isHalf>;
2720 def S2_p#NAME#t_pi : T_pstore_pi <mnemonic, RC, ImmOp, MajOp, isHalf, 0, 0>;
2721 def S2_p#NAME#f_pi : T_pstore_pi <mnemonic, RC, ImmOp, MajOp, isHalf, 1, 0>;
2724 def S2_p#NAME#tnew_pi : T_pstore_pi <mnemonic, RC, ImmOp, MajOp,
2726 def S2_p#NAME#fnew_pi : T_pstore_pi <mnemonic, RC, ImmOp, MajOp,
2731 let accessSize = ByteAccess, isCodeGenOnly = 0 in
2732 defm storerb: ST_PostInc <"memb", "STrib", IntRegs, s4_0Imm, 0b1000>;
2734 let accessSize = HalfWordAccess, isCodeGenOnly = 0 in
2735 defm storerh: ST_PostInc <"memh", "STrih", IntRegs, s4_1Imm, 0b1010>;
2737 let accessSize = WordAccess, isCodeGenOnly = 0 in
2738 defm storeri: ST_PostInc <"memw", "STriw", IntRegs, s4_2Imm, 0b1100>;
2740 let accessSize = DoubleWordAccess, isCodeGenOnly = 0 in
2741 defm storerd: ST_PostInc <"memd", "STrid", DoubleRegs, s4_3Imm, 0b1110>;
2743 let accessSize = HalfWordAccess, isNVStorable = 0, isCodeGenOnly = 0 in
2744 defm storerf: ST_PostInc <"memh", "STrih_H", IntRegs, s4_1Imm, 0b1011, 1>;
2746 // Patterns for generating stores, where the address takes different forms:
2749 // - simple (base address without offset).
2750 // These would usually be used together (via Storex_pat defined below), but
2751 // in some cases one may want to apply different properties (such as
2752 // AddedComplexity) to the individual patterns.
2753 class Storex_fi_pat<PatFrag Store, PatFrag Value, InstHexagon MI>
2754 : Pat<(Store Value:$Rs, AddrFI:$fi), (MI AddrFI:$fi, 0, Value:$Rs)>;
2755 class Storex_add_pat<PatFrag Store, PatFrag Value, PatFrag ImmPred,
2757 : Pat<(Store Value:$Rt, (add (i32 IntRegs:$Rs), ImmPred:$Off)),
2758 (MI IntRegs:$Rs, imm:$Off, Value:$Rt)>;
2760 multiclass Storex_pat<PatFrag Store, PatFrag Value, PatLeaf ImmPred,
2762 def: Storex_fi_pat <Store, Value, MI>;
2763 def: Storex_add_pat <Store, Value, ImmPred, MI>;
2766 def : Pat<(post_truncsti8 (i32 IntRegs:$src1), IntRegs:$src2,
2767 s4_3ImmPred:$offset),
2768 (S2_storerb_pi IntRegs:$src2, s4_0ImmPred:$offset, IntRegs:$src1)>;
2770 def : Pat<(post_truncsti16 (i32 IntRegs:$src1), IntRegs:$src2,
2771 s4_3ImmPred:$offset),
2772 (S2_storerh_pi IntRegs:$src2, s4_1ImmPred:$offset, IntRegs:$src1)>;
2774 def : Pat<(post_store (i32 IntRegs:$src1), IntRegs:$src2, s4_2ImmPred:$offset),
2775 (S2_storeri_pi IntRegs:$src2, s4_1ImmPred:$offset, IntRegs:$src1)>;
2777 def : Pat<(post_store (i64 DoubleRegs:$src1), IntRegs:$src2,
2778 s4_3ImmPred:$offset),
2779 (S2_storerd_pi IntRegs:$src2, s4_3ImmPred:$offset, DoubleRegs:$src1)>;
2781 //===----------------------------------------------------------------------===//
2782 // Template class for post increment stores with register offset.
2783 //===----------------------------------------------------------------------===//
2784 let isNVStorable = 1 in
2785 class T_store_pr <string mnemonic, RegisterClass RC, bits<3> MajOp,
2786 MemAccessSize AccessSz, bit isHalf = 0>
2787 : STInst <(outs IntRegs:$_dst_),
2788 (ins IntRegs:$src1, ModRegs:$src2, RC:$src3),
2789 mnemonic#"($src1++$src2) = $src3"#!if(isHalf, ".h", ""),
2790 [], "$src1 = $_dst_" > {
2794 let accessSize = AccessSz;
2796 let IClass = 0b1010;
2798 let Inst{27-24} = 0b1101;
2799 let Inst{23-21} = MajOp;
2800 let Inst{20-16} = src1;
2801 let Inst{13} = src2;
2802 let Inst{12-8} = src3;
2806 let isCodeGenOnly = 0 in {
2807 def S2_storerb_pr : T_store_pr<"memb", IntRegs, 0b000, ByteAccess>;
2808 def S2_storerh_pr : T_store_pr<"memh", IntRegs, 0b010, HalfWordAccess>;
2809 def S2_storeri_pr : T_store_pr<"memw", IntRegs, 0b100, WordAccess>;
2810 def S2_storerd_pr : T_store_pr<"memd", DoubleRegs, 0b110, DoubleWordAccess>;
2812 def S2_storerf_pr : T_store_pr<"memh", IntRegs, 0b011, HalfWordAccess, 1>;
2814 let opExtendable = 1, isExtentSigned = 1, isPredicable = 1 in
2815 class T_store_io <string mnemonic, RegisterClass RC, Operand ImmOp,
2816 bits<3>MajOp, bit isH = 0>
2818 (ins IntRegs:$src1, ImmOp:$src2, RC:$src3),
2819 mnemonic#"($src1+#$src2) = $src3"#!if(isH,".h","")>,
2820 AddrModeRel, ImmRegRel {
2822 bits<14> src2; // Actual address offset
2824 bits<11> offsetBits; // Represents offset encoding
2826 string ImmOpStr = !cast<string>(ImmOp);
2828 let opExtentBits = !if (!eq(ImmOpStr, "s11_3Ext"), 14,
2829 !if (!eq(ImmOpStr, "s11_2Ext"), 13,
2830 !if (!eq(ImmOpStr, "s11_1Ext"), 12,
2831 /* s11_0Ext */ 11)));
2832 let offsetBits = !if (!eq(ImmOpStr, "s11_3Ext"), src2{13-3},
2833 !if (!eq(ImmOpStr, "s11_2Ext"), src2{12-2},
2834 !if (!eq(ImmOpStr, "s11_1Ext"), src2{11-1},
2835 /* s11_0Ext */ src2{10-0})));
2836 let IClass = 0b1010;
2839 let Inst{26-25} = offsetBits{10-9};
2841 let Inst{23-21} = MajOp;
2842 let Inst{20-16} = src1;
2843 let Inst{13} = offsetBits{8};
2844 let Inst{12-8} = src3;
2845 let Inst{7-0} = offsetBits{7-0};
2848 let opExtendable = 2, isPredicated = 1 in
2849 class T_pstore_io <string mnemonic, RegisterClass RC, Operand ImmOp,
2850 bits<3>MajOp, bit PredNot, bit isPredNew, bit isH = 0>
2852 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$src3, RC:$src4),
2853 !if(PredNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
2854 ") ")#mnemonic#"($src2+#$src3) = $src4"#!if(isH,".h",""),
2855 [],"",V2LDST_tc_st_SLOT01 >,
2856 AddrModeRel, ImmRegRel {
2859 bits<9> src3; // Actual address offset
2861 bits<6> offsetBits; // Represents offset encoding
2863 let isPredicatedNew = isPredNew;
2864 let isPredicatedFalse = PredNot;
2866 string ImmOpStr = !cast<string>(ImmOp);
2867 let opExtentBits = !if (!eq(ImmOpStr, "u6_3Ext"), 9,
2868 !if (!eq(ImmOpStr, "u6_2Ext"), 8,
2869 !if (!eq(ImmOpStr, "u6_1Ext"), 7,
2871 let offsetBits = !if (!eq(ImmOpStr, "u6_3Ext"), src3{8-3},
2872 !if (!eq(ImmOpStr, "u6_2Ext"), src3{7-2},
2873 !if (!eq(ImmOpStr, "u6_1Ext"), src3{6-1},
2874 /* u6_0Ext */ src3{5-0})));
2875 let IClass = 0b0100;
2878 let Inst{26} = PredNot;
2879 let Inst{25} = isPredNew;
2881 let Inst{23-21} = MajOp;
2882 let Inst{20-16} = src2;
2883 let Inst{13} = offsetBits{5};
2884 let Inst{12-8} = src4;
2885 let Inst{7-3} = offsetBits{4-0};
2886 let Inst{1-0} = src1;
2889 let isExtendable = 1, isNVStorable = 1, hasSideEffects = 0 in
2890 multiclass ST_Idxd<string mnemonic, string CextOp, RegisterClass RC,
2891 Operand ImmOp, Operand predImmOp, bits<3> MajOp, bit isH = 0> {
2892 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed in {
2893 def S2_#NAME#_io : T_store_io <mnemonic, RC, ImmOp, MajOp, isH>;
2896 def S2_p#NAME#t_io : T_pstore_io<mnemonic, RC, predImmOp, MajOp, 0, 0, isH>;
2897 def S2_p#NAME#f_io : T_pstore_io<mnemonic, RC, predImmOp, MajOp, 1, 0, isH>;
2900 def S4_p#NAME#tnew_io : T_pstore_io <mnemonic, RC, predImmOp,
2902 def S4_p#NAME#fnew_io : T_pstore_io <mnemonic, RC, predImmOp,
2907 let addrMode = BaseImmOffset, InputType = "imm", isCodeGenOnly = 0 in {
2908 let accessSize = ByteAccess in
2909 defm storerb: ST_Idxd < "memb", "STrib", IntRegs, s11_0Ext, u6_0Ext, 0b000>;
2911 let accessSize = HalfWordAccess, opExtentAlign = 1 in
2912 defm storerh: ST_Idxd < "memh", "STrih", IntRegs, s11_1Ext, u6_1Ext, 0b010>;
2914 let accessSize = WordAccess, opExtentAlign = 2 in
2915 defm storeri: ST_Idxd < "memw", "STriw", IntRegs, s11_2Ext, u6_2Ext, 0b100>;
2917 let accessSize = DoubleWordAccess, isNVStorable = 0, opExtentAlign = 3 in
2918 defm storerd: ST_Idxd < "memd", "STrid", DoubleRegs, s11_3Ext,
2921 let accessSize = HalfWordAccess, opExtentAlign = 1 in
2922 defm storerf: ST_Idxd < "memh", "STrif", IntRegs, s11_1Ext,
2926 class Storex_simple_pat<PatFrag Store, PatFrag Value, InstHexagon MI>
2927 : Pat<(Store Value:$Rt, (i32 IntRegs:$Rs)),
2928 (MI IntRegs:$Rs, 0, Value:$Rt)>;
2930 // Regular stores in the DAG have two operands: value and address.
2931 // Atomic stores also have two, but they are reversed: address, value.
2932 // To use atomic stores with the patterns, they need to have their operands
2933 // swapped. This relies on the knowledge that the F.Fragment uses names
2935 class SwapSt<PatFrag F>
2936 : PatFrag<(ops node:$val, node:$ptr), F.Fragment>;
2938 def: Storex_simple_pat<SwapSt<atomic_store_8>, I32, S2_storerb_io>;
2939 def: Storex_simple_pat<SwapSt<atomic_store_16>, I32, S2_storerh_io>;
2940 def: Storex_simple_pat<SwapSt<atomic_store_32>, I32, S2_storeri_io>;
2941 def: Storex_simple_pat<SwapSt<atomic_store_64>, I64, S2_storerd_io>;
2943 def : Pat<(truncstorei8 (i32 IntRegs:$src1), ADDRriS11_0:$addr),
2944 (S2_storerb_io AddrFI:$addr, 0, (i32 IntRegs:$src1))>;
2946 def : Pat<(truncstorei16 (i32 IntRegs:$src1), ADDRriS11_1:$addr),
2947 (S2_storerh_io AddrFI:$addr, 0, (i32 IntRegs:$src1))>;
2949 def : Pat<(store (i32 IntRegs:$src1), ADDRriS11_2:$addr),
2950 (S2_storeri_io AddrFI:$addr, 0, (i32 IntRegs:$src1))>;
2952 def : Pat<(store (i64 DoubleRegs:$src1), ADDRriS11_3:$addr),
2953 (S2_storerd_io AddrFI:$addr, 0, (i64 DoubleRegs:$src1))>;
2956 let AddedComplexity = 10 in {
2957 def : Pat<(truncstorei8 (i32 IntRegs:$src1), (add IntRegs:$src2,
2958 s11_0ExtPred:$offset)),
2959 (S2_storerb_io IntRegs:$src2, s11_0ImmPred:$offset,
2960 (i32 IntRegs:$src1))>;
2962 def : Pat<(truncstorei16 (i32 IntRegs:$src1), (add IntRegs:$src2,
2963 s11_1ExtPred:$offset)),
2964 (S2_storerh_io IntRegs:$src2, s11_1ImmPred:$offset,
2965 (i32 IntRegs:$src1))>;
2967 def : Pat<(store (i32 IntRegs:$src1), (add IntRegs:$src2,
2968 s11_2ExtPred:$offset)),
2969 (S2_storeri_io IntRegs:$src2, s11_2ImmPred:$offset,
2970 (i32 IntRegs:$src1))>;
2972 def : Pat<(store (i64 DoubleRegs:$src1), (add IntRegs:$src2,
2973 s11_3ExtPred:$offset)),
2974 (S2_storerd_io IntRegs:$src2, s11_3ImmPred:$offset,
2975 (i64 DoubleRegs:$src1))>;
2978 // memh(Rx++#s4:1)=Rt.H
2981 let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 13,
2982 isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 0 in
2983 def STriw_pred : STInst<(outs),
2984 (ins IntRegs:$addr, s11_2Ext:$off, PredRegs:$src1),
2985 ".error \"should not emit\"", []>;
2987 // S2_allocframe: Allocate stack frame.
2988 let Defs = [R29, R30], Uses = [R29, R31, R30],
2989 hasSideEffects = 0, accessSize = DoubleWordAccess, isCodeGenOnly = 0 in
2990 def S2_allocframe: ST0Inst <
2991 (outs), (ins u11_3Imm:$u11_3),
2992 "allocframe(#$u11_3)" > {
2995 let IClass = 0b1010;
2996 let Inst{27-16} = 0b000010011101;
2997 let Inst{13-11} = 0b000;
2998 let Inst{10-0} = u11_3{13-3};
3001 // S2_storer[bhwdf]_pci: Store byte/half/word/double.
3002 // S2_storer[bhwdf]_pci -> S2_storerbnew_pci
3003 let Uses = [CS], isNVStorable = 1 in
3004 class T_store_pci <string mnemonic, RegisterClass RC,
3005 Operand Imm, bits<4>MajOp,
3006 MemAccessSize AlignSize, string RegSrc = "Rt">
3007 : STInst <(outs IntRegs:$_dst_),
3008 (ins IntRegs:$Rz, Imm:$offset, ModRegs:$Mu, RC:$Rt),
3009 #mnemonic#"($Rz ++ #$offset:circ($Mu)) = $"#RegSrc#"",
3016 let accessSize = AlignSize;
3018 let IClass = 0b1010;
3019 let Inst{27-25} = 0b100;
3020 let Inst{24-21} = MajOp;
3021 let Inst{20-16} = Rz;
3023 let Inst{12-8} = Rt;
3026 !if (!eq(!cast<string>(AlignSize), "DoubleWordAccess"), offset{6-3},
3027 !if (!eq(!cast<string>(AlignSize), "WordAccess"), offset{5-2},
3028 !if (!eq(!cast<string>(AlignSize), "HalfWordAccess"), offset{4-1},
3029 /* ByteAccess */ offset{3-0})));
3033 let isCodeGenOnly = 0 in {
3034 def S2_storerb_pci : T_store_pci<"memb", IntRegs, s4_0Imm, 0b1000,
3036 def S2_storerh_pci : T_store_pci<"memh", IntRegs, s4_1Imm, 0b1010,
3038 def S2_storerf_pci : T_store_pci<"memh", IntRegs, s4_1Imm, 0b1011,
3039 HalfWordAccess, "Rt.h">;
3040 def S2_storeri_pci : T_store_pci<"memw", IntRegs, s4_2Imm, 0b1100,
3042 def S2_storerd_pci : T_store_pci<"memd", DoubleRegs, s4_3Imm, 0b1110,
3046 let Uses = [CS], isNewValue = 1, mayStore = 1, isNVStore = 1, opNewValue = 4 in
3047 class T_storenew_pci <string mnemonic, Operand Imm,
3048 bits<2>MajOp, MemAccessSize AlignSize>
3049 : NVInst < (outs IntRegs:$_dst_),
3050 (ins IntRegs:$Rz, Imm:$offset, ModRegs:$Mu, IntRegs:$Nt),
3051 #mnemonic#"($Rz ++ #$offset:circ($Mu)) = $Nt.new",
3059 let accessSize = AlignSize;
3061 let IClass = 0b1010;
3062 let Inst{27-21} = 0b1001101;
3063 let Inst{20-16} = Rz;
3065 let Inst{12-11} = MajOp;
3066 let Inst{10-8} = Nt;
3069 !if (!eq(!cast<string>(AlignSize), "WordAccess"), offset{5-2},
3070 !if (!eq(!cast<string>(AlignSize), "HalfWordAccess"), offset{4-1},
3071 /* ByteAccess */ offset{3-0}));
3074 let isCodeGenOnly = 0 in {
3075 def S2_storerbnew_pci : T_storenew_pci <"memb", s4_0Imm, 0b00, ByteAccess>;
3076 def S2_storerhnew_pci : T_storenew_pci <"memh", s4_1Imm, 0b01, HalfWordAccess>;
3077 def S2_storerinew_pci : T_storenew_pci <"memw", s4_2Imm, 0b10, WordAccess>;
3080 //===----------------------------------------------------------------------===//
3081 // Circular stores with auto-increment register
3082 //===----------------------------------------------------------------------===//
3083 let Uses = [CS], isNVStorable = 1, isCodeGenOnly = 0 in
3084 class T_store_pcr <string mnemonic, RegisterClass RC, bits<4>MajOp,
3085 MemAccessSize AlignSize, string RegSrc = "Rt">
3086 : STInst <(outs IntRegs:$_dst_),
3087 (ins IntRegs:$Rz, ModRegs:$Mu, RC:$Rt),
3088 #mnemonic#"($Rz ++ I:circ($Mu)) = $"#RegSrc#"",
3095 let accessSize = AlignSize;
3097 let IClass = 0b1010;
3098 let Inst{27-25} = 0b100;
3099 let Inst{24-21} = MajOp;
3100 let Inst{20-16} = Rz;
3102 let Inst{12-8} = Rt;
3107 let isCodeGenOnly = 0 in {
3108 def S2_storerb_pcr : T_store_pcr<"memb", IntRegs, 0b1000, ByteAccess>;
3109 def S2_storerh_pcr : T_store_pcr<"memh", IntRegs, 0b1010, HalfWordAccess>;
3110 def S2_storeri_pcr : T_store_pcr<"memw", IntRegs, 0b1100, WordAccess>;
3111 def S2_storerd_pcr : T_store_pcr<"memd", DoubleRegs, 0b1110, DoubleWordAccess>;
3112 def S2_storerf_pcr : T_store_pcr<"memh", IntRegs, 0b1011,
3113 HalfWordAccess, "Rt.h">;
3116 //===----------------------------------------------------------------------===//
3117 // Circular .new stores with auto-increment register
3118 //===----------------------------------------------------------------------===//
3119 let Uses = [CS], isNewValue = 1, mayStore = 1, isNVStore = 1, opNewValue = 3 in
3120 class T_storenew_pcr <string mnemonic, bits<2>MajOp,
3121 MemAccessSize AlignSize>
3122 : NVInst <(outs IntRegs:$_dst_),
3123 (ins IntRegs:$Rz, ModRegs:$Mu, IntRegs:$Nt),
3124 #mnemonic#"($Rz ++ I:circ($Mu)) = $Nt.new" ,
3131 let accessSize = AlignSize;
3133 let IClass = 0b1010;
3134 let Inst{27-21} = 0b1001101;
3135 let Inst{20-16} = Rz;
3137 let Inst{12-11} = MajOp;
3138 let Inst{10-8} = Nt;
3143 let isCodeGenOnly = 0 in {
3144 def S2_storerbnew_pcr : T_storenew_pcr <"memb", 0b00, ByteAccess>;
3145 def S2_storerhnew_pcr : T_storenew_pcr <"memh", 0b01, HalfWordAccess>;
3146 def S2_storerinew_pcr : T_storenew_pcr <"memw", 0b10, WordAccess>;
3149 //===----------------------------------------------------------------------===//
3150 // Bit-reversed stores with auto-increment register
3151 //===----------------------------------------------------------------------===//
3152 let hasSideEffects = 0 in
3153 class T_store_pbr<string mnemonic, RegisterClass RC,
3154 MemAccessSize addrSize, bits<3> majOp,
3157 <(outs IntRegs:$_dst_),
3158 (ins IntRegs:$Rz, ModRegs:$Mu, RC:$src),
3159 #mnemonic#"($Rz ++ $Mu:brev) = $src"#!if (!eq(isHalf, 1), ".h", ""),
3160 [], "$Rz = $_dst_" > {
3162 let accessSize = addrSize;
3168 let IClass = 0b1010;
3170 let Inst{27-24} = 0b1111;
3171 let Inst{23-21} = majOp;
3173 let Inst{20-16} = Rz;
3175 let Inst{12-8} = src;
3178 let isNVStorable = 1, isCodeGenOnly = 0 in {
3179 let BaseOpcode = "S2_storerb_pbr" in
3180 def S2_storerb_pbr : T_store_pbr<"memb", IntRegs, ByteAccess,
3181 0b000>, NewValueRel;
3182 let BaseOpcode = "S2_storerh_pbr" in
3183 def S2_storerh_pbr : T_store_pbr<"memh", IntRegs, HalfWordAccess,
3184 0b010>, NewValueRel;
3185 let BaseOpcode = "S2_storeri_pbr" in
3186 def S2_storeri_pbr : T_store_pbr<"memw", IntRegs, WordAccess,
3187 0b100>, NewValueRel;
3189 let isCodeGenOnly = 0 in {
3190 def S2_storerf_pbr : T_store_pbr<"memh", IntRegs, HalfWordAccess, 0b011, 1>;
3191 def S2_storerd_pbr : T_store_pbr<"memd", DoubleRegs, DoubleWordAccess, 0b110>;
3194 //===----------------------------------------------------------------------===//
3195 // Bit-reversed .new stores with auto-increment register
3196 //===----------------------------------------------------------------------===//
3197 let isNewValue = 1, mayStore = 1, isNVStore = 1, opNewValue = 3,
3198 hasSideEffects = 0 in
3199 class T_storenew_pbr<string mnemonic, MemAccessSize addrSize, bits<2> majOp>
3200 : NVInst <(outs IntRegs:$_dst_),
3201 (ins IntRegs:$Rz, ModRegs:$Mu, IntRegs:$Nt),
3202 #mnemonic#"($Rz ++ $Mu:brev) = $Nt.new", [],
3203 "$Rz = $_dst_">, NewValueRel {
3204 let accessSize = addrSize;
3209 let IClass = 0b1010;
3211 let Inst{27-21} = 0b1111101;
3212 let Inst{12-11} = majOp;
3214 let Inst{20-16} = Rz;
3216 let Inst{10-8} = Nt;
3219 let BaseOpcode = "S2_storerb_pbr", isCodeGenOnly = 0 in
3220 def S2_storerbnew_pbr : T_storenew_pbr<"memb", ByteAccess, 0b00>;
3222 let BaseOpcode = "S2_storerh_pbr", isCodeGenOnly = 0 in
3223 def S2_storerhnew_pbr : T_storenew_pbr<"memh", HalfWordAccess, 0b01>;
3225 let BaseOpcode = "S2_storeri_pbr", isCodeGenOnly = 0 in
3226 def S2_storerinew_pbr : T_storenew_pbr<"memw", WordAccess, 0b10>;
3228 //===----------------------------------------------------------------------===//
3230 //===----------------------------------------------------------------------===//
3232 //===----------------------------------------------------------------------===//
3234 //===----------------------------------------------------------------------===//
3236 def NOT_rr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1),
3237 "$dst = not($src1)",
3238 [(set (i64 DoubleRegs:$dst), (not (i64 DoubleRegs:$src1)))]>;
3241 //===----------------------------------------------------------------------===//
3243 //===----------------------------------------------------------------------===//
3245 let hasSideEffects = 0 in
3246 class T_S2op_1 <string mnemonic, bits<4> RegTyBits, RegisterClass RCOut,
3247 RegisterClass RCIn, bits<2> MajOp, bits<3> MinOp, bit isSat>
3248 : SInst <(outs RCOut:$dst), (ins RCIn:$src),
3249 "$dst = "#mnemonic#"($src)"#!if(isSat, ":sat", ""),
3250 [], "", S_2op_tc_1_SLOT23 > {
3254 let IClass = 0b1000;
3256 let Inst{27-24} = RegTyBits;
3257 let Inst{23-22} = MajOp;
3259 let Inst{20-16} = src;
3260 let Inst{7-5} = MinOp;
3261 let Inst{4-0} = dst;
3264 class T_S2op_1_di <string mnemonic, bits<2> MajOp, bits<3> MinOp>
3265 : T_S2op_1 <mnemonic, 0b0100, DoubleRegs, IntRegs, MajOp, MinOp, 0>;
3267 let hasNewValue = 1 in
3268 class T_S2op_1_id <string mnemonic, bits<2> MajOp, bits<3> MinOp, bit isSat = 0>
3269 : T_S2op_1 <mnemonic, 0b1000, IntRegs, DoubleRegs, MajOp, MinOp, isSat>;
3271 let hasNewValue = 1 in
3272 class T_S2op_1_ii <string mnemonic, bits<2> MajOp, bits<3> MinOp, bit isSat = 0>
3273 : T_S2op_1 <mnemonic, 0b1100, IntRegs, IntRegs, MajOp, MinOp, isSat>;
3275 // Sign extend word to doubleword
3276 let isCodeGenOnly = 0 in
3277 def A2_sxtw : T_S2op_1_di <"sxtw", 0b01, 0b000>;
3279 def: Pat <(i64 (sext I32:$src)), (A2_sxtw I32:$src)>;
3281 // Swizzle the bytes of a word
3282 let isCodeGenOnly = 0 in
3283 def A2_swiz : T_S2op_1_ii <"swiz", 0b10, 0b111>;
3286 let Defs = [USR_OVF], isCodeGenOnly = 0 in {
3287 def A2_sat : T_S2op_1_id <"sat", 0b11, 0b000>;
3288 def A2_satb : T_S2op_1_ii <"satb", 0b11, 0b111>;
3289 def A2_satub : T_S2op_1_ii <"satub", 0b11, 0b110>;
3290 def A2_sath : T_S2op_1_ii <"sath", 0b11, 0b100>;
3291 def A2_satuh : T_S2op_1_ii <"satuh", 0b11, 0b101>;
3292 def A2_roundsat : T_S2op_1_id <"round", 0b11, 0b001, 0b1>;
3295 let Itinerary = S_2op_tc_2_SLOT23, isCodeGenOnly = 0 in {
3297 def S2_brev : T_S2op_1_ii <"brev", 0b01, 0b110>;
3299 // Absolute value word
3300 def A2_abs : T_S2op_1_ii <"abs", 0b10, 0b100>;
3302 let Defs = [USR_OVF] in
3303 def A2_abssat : T_S2op_1_ii <"abs", 0b10, 0b101, 1>;
3305 // Negate with saturation
3306 let Defs = [USR_OVF] in
3307 def A2_negsat : T_S2op_1_ii <"neg", 0b10, 0b110, 1>;
3310 def: Pat<(i32 (select (i1 (setlt (i32 IntRegs:$src), 0)),
3311 (i32 (sub 0, (i32 IntRegs:$src))),
3312 (i32 IntRegs:$src))),
3313 (A2_abs IntRegs:$src)>;
3315 let AddedComplexity = 50 in
3316 def: Pat<(i32 (xor (add (sra (i32 IntRegs:$src), (i32 31)),
3317 (i32 IntRegs:$src)),
3318 (sra (i32 IntRegs:$src), (i32 31)))),
3319 (A2_abs IntRegs:$src)>;
3321 class T_S2op_2 <string mnemonic, bits<4> RegTyBits, RegisterClass RCOut,
3322 RegisterClass RCIn, bits<3> MajOp, bits<3> MinOp,
3323 bit isSat, bit isRnd, list<dag> pattern = []>
3324 : SInst <(outs RCOut:$dst),
3325 (ins RCIn:$src, u5Imm:$u5),
3326 "$dst = "#mnemonic#"($src, #$u5)"#!if(isSat, ":sat", "")
3327 #!if(isRnd, ":rnd", ""),
3328 pattern, "", S_2op_tc_2_SLOT23> {
3333 let IClass = 0b1000;
3335 let Inst{27-24} = RegTyBits;
3336 let Inst{23-21} = MajOp;
3337 let Inst{20-16} = src;
3339 let Inst{12-8} = u5;
3340 let Inst{7-5} = MinOp;
3341 let Inst{4-0} = dst;
3344 class T_S2op_2_di <string mnemonic, bits<3> MajOp, bits<3> MinOp>
3345 : T_S2op_2 <mnemonic, 0b1000, DoubleRegs, IntRegs, MajOp, MinOp, 0, 0>;
3347 let hasNewValue = 1 in
3348 class T_S2op_2_id <string mnemonic, bits<3> MajOp, bits<3> MinOp>
3349 : T_S2op_2 <mnemonic, 0b1000, IntRegs, DoubleRegs, MajOp, MinOp, 0, 0>;
3351 let hasNewValue = 1 in
3352 class T_S2op_2_ii <string mnemonic, bits<3> MajOp, bits<3> MinOp,
3353 bit isSat = 0, bit isRnd = 0, list<dag> pattern = []>
3354 : T_S2op_2 <mnemonic, 0b1100, IntRegs, IntRegs, MajOp, MinOp,
3355 isSat, isRnd, pattern>;
3357 class T_S2op_shift <string mnemonic, bits<3> MajOp, bits<3> MinOp, SDNode OpNd>
3358 : T_S2op_2_ii <mnemonic, MajOp, MinOp, 0, 0,
3359 [(set (i32 IntRegs:$dst), (OpNd (i32 IntRegs:$src),
3360 (u5ImmPred:$u5)))]>;
3362 // Arithmetic/logical shift right/left by immediate
3363 let Itinerary = S_2op_tc_1_SLOT23, isCodeGenOnly = 0 in {
3364 def S2_asr_i_r : T_S2op_shift <"asr", 0b000, 0b000, sra>;
3365 def S2_lsr_i_r : T_S2op_shift <"lsr", 0b000, 0b001, srl>;
3366 def S2_asl_i_r : T_S2op_shift <"asl", 0b000, 0b010, shl>;
3369 // Shift left by immediate with saturation
3370 let Defs = [USR_OVF], isCodeGenOnly = 0 in
3371 def S2_asl_i_r_sat : T_S2op_2_ii <"asl", 0b010, 0b010, 1>;
3373 // Shift right with round
3374 let isCodeGenOnly = 0 in
3375 def S2_asr_i_r_rnd : T_S2op_2_ii <"asr", 0b010, 0b000, 0, 1>;
3377 def S2_asr_i_r_rnd_goodsyntax
3378 : SInst <(outs IntRegs:$dst), (ins IntRegs:$src, u5Imm:$u5),
3379 "$dst = asrrnd($src, #$u5)",
3380 [], "", S_2op_tc_1_SLOT23>;
3382 def: Pat<(i32 (sra (i32 (add (i32 (sra I32:$src1, u5ImmPred:$src2)),
3385 (S2_asr_i_r_rnd IntRegs:$src1, u5ImmPred:$src2)>;
3387 class T_S2op_3<string opc, bits<2>MajOp, bits<3>minOp, bits<1> sat = 0>
3388 : SInst<(outs DoubleRegs:$Rdd), (ins DoubleRegs:$Rss),
3389 "$Rdd = "#opc#"($Rss)"#!if(!eq(sat, 1),":sat","")> {
3392 let IClass = 0b1000;
3393 let Inst{27-24} = 0;
3394 let Inst{23-22} = MajOp;
3395 let Inst{20-16} = Rss;
3396 let Inst{7-5} = minOp;
3397 let Inst{4-0} = Rdd;
3400 let isCodeGenOnly = 0 in {
3401 def A2_absp : T_S2op_3 <"abs", 0b10, 0b110>;
3402 def A2_negp : T_S2op_3 <"neg", 0b10, 0b101>;
3403 def A2_notp : T_S2op_3 <"not", 0b10, 0b100>;
3406 // Innterleave/deinterleave
3407 let isCodeGenOnly = 0 in {
3408 def S2_interleave : T_S2op_3 <"interleave", 0b11, 0b101>;
3409 def S2_deinterleave : T_S2op_3 <"deinterleave", 0b11, 0b100>;
3412 //===----------------------------------------------------------------------===//
3414 //===----------------------------------------------------------------------===//
3417 let hasSideEffects = 0, hasNewValue = 1 in
3418 class T_COUNT_LEADING<string MnOp, bits<3> MajOp, bits<3> MinOp, bit Is32,
3420 : SInst<Out, Inp, "$Rd = "#MnOp#"($Rs)", [], "", S_2op_tc_1_SLOT23> {
3423 let IClass = 0b1000;
3425 let Inst{26} = Is32;
3426 let Inst{25-24} = 0b00;
3427 let Inst{23-21} = MajOp;
3428 let Inst{20-16} = Rs;
3429 let Inst{7-5} = MinOp;
3433 class T_COUNT_LEADING_32<string MnOp, bits<3> MajOp, bits<3> MinOp>
3434 : T_COUNT_LEADING<MnOp, MajOp, MinOp, 0b1,
3435 (outs IntRegs:$Rd), (ins IntRegs:$Rs)>;
3437 class T_COUNT_LEADING_64<string MnOp, bits<3> MajOp, bits<3> MinOp>
3438 : T_COUNT_LEADING<MnOp, MajOp, MinOp, 0b0,
3439 (outs IntRegs:$Rd), (ins DoubleRegs:$Rs)>;
3441 let isCodeGenOnly = 0 in {
3442 def S2_cl0 : T_COUNT_LEADING_32<"cl0", 0b000, 0b101>;
3443 def S2_cl1 : T_COUNT_LEADING_32<"cl1", 0b000, 0b110>;
3444 def S2_ct0 : T_COUNT_LEADING_32<"ct0", 0b010, 0b100>;
3445 def S2_ct1 : T_COUNT_LEADING_32<"ct1", 0b010, 0b101>;
3446 def S2_cl0p : T_COUNT_LEADING_64<"cl0", 0b010, 0b010>;
3447 def S2_cl1p : T_COUNT_LEADING_64<"cl1", 0b010, 0b100>;
3448 def S2_clb : T_COUNT_LEADING_32<"clb", 0b000, 0b100>;
3449 def S2_clbp : T_COUNT_LEADING_64<"clb", 0b010, 0b000>;
3450 def S2_clbnorm : T_COUNT_LEADING_32<"normamt", 0b000, 0b111>;
3453 def: Pat<(i32 (ctlz I32:$Rs)), (S2_cl0 I32:$Rs)>;
3454 def: Pat<(i32 (ctlz (not I32:$Rs))), (S2_cl1 I32:$Rs)>;
3455 def: Pat<(i32 (cttz I32:$Rs)), (S2_ct0 I32:$Rs)>;
3456 def: Pat<(i32 (cttz (not I32:$Rs))), (S2_ct1 I32:$Rs)>;
3457 def: Pat<(i32 (trunc (ctlz I64:$Rss))), (S2_cl0p I64:$Rss)>;
3458 def: Pat<(i32 (trunc (ctlz (not I64:$Rss)))), (S2_cl1p I64:$Rss)>;
3460 // Bit set/clear/toggle
3462 let hasSideEffects = 0, hasNewValue = 1 in
3463 class T_SCT_BIT_IMM<string MnOp, bits<3> MinOp>
3464 : SInst<(outs IntRegs:$Rd), (ins IntRegs:$Rs, u5Imm:$u5),
3465 "$Rd = "#MnOp#"($Rs, #$u5)", [], "", S_2op_tc_1_SLOT23> {
3469 let IClass = 0b1000;
3470 let Inst{27-21} = 0b1100110;
3471 let Inst{20-16} = Rs;
3473 let Inst{12-8} = u5;
3474 let Inst{7-5} = MinOp;
3478 let hasSideEffects = 0, hasNewValue = 1 in
3479 class T_SCT_BIT_REG<string MnOp, bits<2> MinOp>
3480 : SInst<(outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt),
3481 "$Rd = "#MnOp#"($Rs, $Rt)", [], "", S_3op_tc_1_SLOT23> {
3485 let IClass = 0b1100;
3486 let Inst{27-22} = 0b011010;
3487 let Inst{20-16} = Rs;
3488 let Inst{12-8} = Rt;
3489 let Inst{7-6} = MinOp;
3493 let isCodeGenOnly = 0 in {
3494 def S2_clrbit_i : T_SCT_BIT_IMM<"clrbit", 0b001>;
3495 def S2_setbit_i : T_SCT_BIT_IMM<"setbit", 0b000>;
3496 def S2_togglebit_i : T_SCT_BIT_IMM<"togglebit", 0b010>;
3497 def S2_clrbit_r : T_SCT_BIT_REG<"clrbit", 0b01>;
3498 def S2_setbit_r : T_SCT_BIT_REG<"setbit", 0b00>;
3499 def S2_togglebit_r : T_SCT_BIT_REG<"togglebit", 0b10>;
3502 def: Pat<(i32 (and (i32 IntRegs:$Rs), (not (shl 1, u5ImmPred:$u5)))),
3503 (S2_clrbit_i IntRegs:$Rs, u5ImmPred:$u5)>;
3504 def: Pat<(i32 (or (i32 IntRegs:$Rs), (shl 1, u5ImmPred:$u5))),
3505 (S2_setbit_i IntRegs:$Rs, u5ImmPred:$u5)>;
3506 def: Pat<(i32 (xor (i32 IntRegs:$Rs), (shl 1, u5ImmPred:$u5))),
3507 (S2_togglebit_i IntRegs:$Rs, u5ImmPred:$u5)>;
3508 def: Pat<(i32 (and (i32 IntRegs:$Rs), (not (shl 1, (i32 IntRegs:$Rt))))),
3509 (S2_clrbit_r IntRegs:$Rs, IntRegs:$Rt)>;
3510 def: Pat<(i32 (or (i32 IntRegs:$Rs), (shl 1, (i32 IntRegs:$Rt)))),
3511 (S2_setbit_r IntRegs:$Rs, IntRegs:$Rt)>;
3512 def: Pat<(i32 (xor (i32 IntRegs:$Rs), (shl 1, (i32 IntRegs:$Rt)))),
3513 (S2_togglebit_r IntRegs:$Rs, IntRegs:$Rt)>;
3517 let hasSideEffects = 0 in
3518 class T_TEST_BIT_IMM<string MnOp, bits<3> MajOp>
3519 : SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, u5Imm:$u5),
3520 "$Pd = "#MnOp#"($Rs, #$u5)",
3521 [], "", S_2op_tc_2early_SLOT23> {
3525 let IClass = 0b1000;
3526 let Inst{27-24} = 0b0101;
3527 let Inst{23-21} = MajOp;
3528 let Inst{20-16} = Rs;
3530 let Inst{12-8} = u5;
3534 let hasSideEffects = 0 in
3535 class T_TEST_BIT_REG<string MnOp, bit IsNeg>
3536 : SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, IntRegs:$Rt),
3537 "$Pd = "#MnOp#"($Rs, $Rt)",
3538 [], "", S_3op_tc_2early_SLOT23> {
3542 let IClass = 0b1100;
3543 let Inst{27-22} = 0b011100;
3544 let Inst{21} = IsNeg;
3545 let Inst{20-16} = Rs;
3546 let Inst{12-8} = Rt;
3550 let isCodeGenOnly = 0 in {
3551 def S2_tstbit_i : T_TEST_BIT_IMM<"tstbit", 0b000>;
3552 def S2_tstbit_r : T_TEST_BIT_REG<"tstbit", 0>;
3555 let AddedComplexity = 20 in { // Complexity greater than cmp reg-imm.
3556 def: Pat<(i1 (setne (and (shl 1, u5ImmPred:$u5), (i32 IntRegs:$Rs)), 0)),
3557 (S2_tstbit_i IntRegs:$Rs, u5ImmPred:$u5)>;
3558 def: Pat<(i1 (setne (and (shl 1, (i32 IntRegs:$Rt)), (i32 IntRegs:$Rs)), 0)),
3559 (S2_tstbit_r IntRegs:$Rs, IntRegs:$Rt)>;
3560 def: Pat<(i1 (trunc (i32 IntRegs:$Rs))),
3561 (S2_tstbit_i IntRegs:$Rs, 0)>;
3562 def: Pat<(i1 (trunc (i64 DoubleRegs:$Rs))),
3563 (S2_tstbit_i (LoReg DoubleRegs:$Rs), 0)>;
3565 let hasSideEffects = 0 in
3566 class T_TEST_BITS_IMM<string MnOp, bits<2> MajOp, bit IsNeg>
3567 : SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, u6Imm:$u6),
3568 "$Pd = "#MnOp#"($Rs, #$u6)",
3569 [], "", S_2op_tc_2early_SLOT23> {
3573 let IClass = 0b1000;
3574 let Inst{27-24} = 0b0101;
3575 let Inst{23-22} = MajOp;
3576 let Inst{21} = IsNeg;
3577 let Inst{20-16} = Rs;
3578 let Inst{13-8} = u6;
3582 let hasSideEffects = 0 in
3583 class T_TEST_BITS_REG<string MnOp, bits<2> MajOp, bit IsNeg>
3584 : SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, IntRegs:$Rt),
3585 "$Pd = "#MnOp#"($Rs, $Rt)",
3586 [], "", S_3op_tc_2early_SLOT23> {
3590 let IClass = 0b1100;
3591 let Inst{27-24} = 0b0111;
3592 let Inst{23-22} = MajOp;
3593 let Inst{21} = IsNeg;
3594 let Inst{20-16} = Rs;
3595 let Inst{12-8} = Rt;
3599 let isCodeGenOnly = 0 in {
3600 def C2_bitsclri : T_TEST_BITS_IMM<"bitsclr", 0b10, 0>;
3601 def C2_bitsclr : T_TEST_BITS_REG<"bitsclr", 0b10, 0>;
3602 def C2_bitsset : T_TEST_BITS_REG<"bitsset", 0b01, 0>;
3605 let AddedComplexity = 20 in { // Complexity greater than compare reg-imm.
3606 def: Pat<(i1 (seteq (and (i32 IntRegs:$Rs), u6ImmPred:$u6), 0)),
3607 (C2_bitsclri IntRegs:$Rs, u6ImmPred:$u6)>;
3608 def: Pat<(i1 (seteq (and (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)), 0)),
3609 (C2_bitsclr IntRegs:$Rs, IntRegs:$Rt)>;
3612 let AddedComplexity = 10 in // Complexity greater than compare reg-reg.
3613 def: Pat<(i1 (seteq (and (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)), IntRegs:$Rt)),
3614 (C2_bitsset IntRegs:$Rs, IntRegs:$Rt)>;
3616 //===----------------------------------------------------------------------===//
3618 //===----------------------------------------------------------------------===//
3620 //===----------------------------------------------------------------------===//
3622 //===----------------------------------------------------------------------===//
3623 //===----------------------------------------------------------------------===//
3625 //===----------------------------------------------------------------------===//
3627 //===----------------------------------------------------------------------===//
3629 //===----------------------------------------------------------------------===//
3631 //===----------------------------------------------------------------------===//
3633 //===----------------------------------------------------------------------===//
3635 //===----------------------------------------------------------------------===//
3637 //===----------------------------------------------------------------------===//
3639 // Predicate transfer.
3640 let hasSideEffects = 0, hasNewValue = 1, isCodeGenOnly = 0 in
3641 def C2_tfrpr : SInst<(outs IntRegs:$Rd), (ins PredRegs:$Ps),
3642 "$Rd = $Ps", [], "", S_2op_tc_1_SLOT23> {
3646 let IClass = 0b1000;
3647 let Inst{27-24} = 0b1001;
3649 let Inst{17-16} = Ps;
3653 // Transfer general register to predicate.
3654 let hasSideEffects = 0, isCodeGenOnly = 0 in
3655 def C2_tfrrp: SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs),
3656 "$Pd = $Rs", [], "", S_2op_tc_2early_SLOT23> {
3660 let IClass = 0b1000;
3661 let Inst{27-21} = 0b0101010;
3662 let Inst{20-16} = Rs;
3667 //===----------------------------------------------------------------------===//
3669 //===----------------------------------------------------------------------===//
3671 //===----------------------------------------------------------------------===//
3673 //===----------------------------------------------------------------------===//
3674 class S_2OpInstImm<string Mnemonic, bits<3>MajOp, bits<3>MinOp,
3675 Operand Imm, list<dag> pattern = [], bit isRnd = 0>
3676 : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, Imm:$src2),
3677 "$dst = "#Mnemonic#"($src1, #$src2)"#!if(isRnd, ":rnd", ""),
3681 let IClass = 0b1000;
3682 let Inst{27-24} = 0;
3683 let Inst{23-21} = MajOp;
3684 let Inst{20-16} = src1;
3685 let Inst{7-5} = MinOp;
3686 let Inst{4-0} = dst;
3689 class S_2OpInstImmI6<string Mnemonic, SDNode OpNode, bits<3>MinOp>
3690 : S_2OpInstImm<Mnemonic, 0b000, MinOp, u6Imm,
3691 [(set (i64 DoubleRegs:$dst), (OpNode (i64 DoubleRegs:$src1),
3692 u6ImmPred:$src2))]> {
3694 let Inst{13-8} = src2;
3697 // Shift by immediate.
3698 let isCodeGenOnly = 0 in {
3699 def S2_asr_i_p : S_2OpInstImmI6<"asr", sra, 0b000>;
3700 def S2_asl_i_p : S_2OpInstImmI6<"asl", shl, 0b010>;
3701 def S2_lsr_i_p : S_2OpInstImmI6<"lsr", srl, 0b001>;
3704 // Shift left by small amount and add.
3705 let AddedComplexity = 100, hasNewValue = 1, hasSideEffects = 0,
3706 isCodeGenOnly = 0 in
3707 def S2_addasl_rrri: SInst <(outs IntRegs:$Rd),
3708 (ins IntRegs:$Rt, IntRegs:$Rs, u3Imm:$u3),
3709 "$Rd = addasl($Rt, $Rs, #$u3)" ,
3710 [(set (i32 IntRegs:$Rd), (add (i32 IntRegs:$Rt),
3711 (shl (i32 IntRegs:$Rs), u3ImmPred:$u3)))],
3712 "", S_3op_tc_2_SLOT23> {
3718 let IClass = 0b1100;
3720 let Inst{27-21} = 0b0100000;
3721 let Inst{20-16} = Rs;
3723 let Inst{12-8} = Rt;
3728 //===----------------------------------------------------------------------===//
3730 //===----------------------------------------------------------------------===//
3732 //===----------------------------------------------------------------------===//
3734 //===----------------------------------------------------------------------===//
3735 //===----------------------------------------------------------------------===//
3737 //===----------------------------------------------------------------------===//
3739 //===----------------------------------------------------------------------===//
3741 //===----------------------------------------------------------------------===//
3742 //===----------------------------------------------------------------------===//
3744 //===----------------------------------------------------------------------===//
3746 //===----------------------------------------------------------------------===//
3748 //===----------------------------------------------------------------------===//
3750 //===----------------------------------------------------------------------===//
3752 //===----------------------------------------------------------------------===//
3753 def HexagonBARRIER: SDNode<"HexagonISD::BARRIER", SDTNone, [SDNPHasChain]>;
3755 let hasSideEffects = 1, isSoloAX = 1, isCodeGenOnly = 0 in
3756 def BARRIER : SYSInst<(outs), (ins),
3758 [(HexagonBARRIER)],"",ST_tc_st_SLOT0> {
3759 let Inst{31-28} = 0b1010;
3760 let Inst{27-21} = 0b1000000;
3763 //===----------------------------------------------------------------------===//
3765 //===----------------------------------------------------------------------===//
3766 //===----------------------------------------------------------------------===//
3768 //===----------------------------------------------------------------------===//
3770 let isExtendable = 1, isExtentSigned = 1, opExtentBits = 9, opExtentAlign = 2,
3771 opExtendable = 0, hasSideEffects = 0 in
3772 class LOOP_iBase<string mnemonic, Operand brOp, bit mustExtend = 0>
3773 : CRInst<(outs), (ins brOp:$offset, u10Imm:$src2),
3774 #mnemonic#"($offset, #$src2)",
3775 [], "" , CR_tc_3x_SLOT3> {
3779 let IClass = 0b0110;
3781 let Inst{27-22} = 0b100100;
3782 let Inst{21} = !if (!eq(mnemonic, "loop0"), 0b0, 0b1);
3783 let Inst{20-16} = src2{9-5};
3784 let Inst{12-8} = offset{8-4};
3785 let Inst{7-5} = src2{4-2};
3786 let Inst{4-3} = offset{3-2};
3787 let Inst{1-0} = src2{1-0};
3790 let isExtendable = 1, isExtentSigned = 1, opExtentBits = 9, opExtentAlign = 2,
3791 opExtendable = 0, hasSideEffects = 0 in
3792 class LOOP_rBase<string mnemonic, Operand brOp, bit mustExtend = 0>
3793 : CRInst<(outs), (ins brOp:$offset, IntRegs:$src2),
3794 #mnemonic#"($offset, $src2)",
3795 [], "" ,CR_tc_3x_SLOT3> {
3799 let IClass = 0b0110;
3801 let Inst{27-22} = 0b000000;
3802 let Inst{21} = !if (!eq(mnemonic, "loop0"), 0b0, 0b1);
3803 let Inst{20-16} = src2;
3804 let Inst{12-8} = offset{8-4};
3805 let Inst{4-3} = offset{3-2};
3808 multiclass LOOP_ri<string mnemonic> {
3809 def i : LOOP_iBase<mnemonic, brtarget>;
3810 def r : LOOP_rBase<mnemonic, brtarget>;
3814 let Defs = [SA0, LC0, USR], isCodeGenOnly = 0 in
3815 defm J2_loop0 : LOOP_ri<"loop0">;
3817 // Interestingly only loop0's appear to set usr.lpcfg
3818 let Defs = [SA1, LC1], isCodeGenOnly = 0 in
3819 defm J2_loop1 : LOOP_ri<"loop1">;
3821 let isBranch = 1, isTerminator = 1, hasSideEffects = 0,
3822 Defs = [PC, LC0], Uses = [SA0, LC0] in {
3823 def ENDLOOP0 : Endloop<(outs), (ins brtarget:$offset),
3828 let isBranch = 1, isTerminator = 1, hasSideEffects = 0,
3829 Defs = [PC, LC1], Uses = [SA1, LC1] in {
3830 def ENDLOOP1 : Endloop<(outs), (ins brtarget:$offset),
3835 // Pipelined loop instructions, sp[123]loop0
3836 let Defs = [LC0, SA0, P3, USR], hasSideEffects = 0,
3837 isExtentSigned = 1, isExtendable = 1, opExtentBits = 9, opExtentAlign = 2,
3838 opExtendable = 0, isPredicateLate = 1 in
3839 class SPLOOP_iBase<string SP, bits<2> op>
3840 : CRInst <(outs), (ins brtarget:$r7_2, u10Imm:$U10),
3841 "p3 = sp"#SP#"loop0($r7_2, #$U10)" > {
3845 let IClass = 0b0110;
3847 let Inst{22-21} = op;
3848 let Inst{27-23} = 0b10011;
3849 let Inst{20-16} = U10{9-5};
3850 let Inst{12-8} = r7_2{8-4};
3851 let Inst{7-5} = U10{4-2};
3852 let Inst{4-3} = r7_2{3-2};
3853 let Inst{1-0} = U10{1-0};
3856 let Defs = [LC0, SA0, P3, USR], hasSideEffects = 0,
3857 isExtentSigned = 1, isExtendable = 1, opExtentBits = 9, opExtentAlign = 2,
3858 opExtendable = 0, isPredicateLate = 1 in
3859 class SPLOOP_rBase<string SP, bits<2> op>
3860 : CRInst <(outs), (ins brtarget:$r7_2, IntRegs:$Rs),
3861 "p3 = sp"#SP#"loop0($r7_2, $Rs)" > {
3865 let IClass = 0b0110;
3867 let Inst{22-21} = op;
3868 let Inst{27-23} = 0b00001;
3869 let Inst{20-16} = Rs;
3870 let Inst{12-8} = r7_2{8-4};
3871 let Inst{4-3} = r7_2{3-2};
3874 multiclass SPLOOP_ri<string mnemonic, bits<2> op> {
3875 def i : SPLOOP_iBase<mnemonic, op>;
3876 def r : SPLOOP_rBase<mnemonic, op>;
3879 let isCodeGenOnly = 0 in {
3880 defm J2_ploop1s : SPLOOP_ri<"1", 0b01>;
3881 defm J2_ploop2s : SPLOOP_ri<"2", 0b10>;
3882 defm J2_ploop3s : SPLOOP_ri<"3", 0b11>;
3885 // Transfer to/from Control/GPR Guest/GPR
3886 let hasSideEffects = 0 in
3887 class TFR_CR_RS_base<RegisterClass CTRC, RegisterClass RC, bit isDouble>
3888 : CRInst <(outs CTRC:$dst), (ins RC:$src),
3889 "$dst = $src", [], "", CR_tc_3x_SLOT3> {
3893 let IClass = 0b0110;
3895 let Inst{27-25} = 0b001;
3896 let Inst{24} = isDouble;
3897 let Inst{23-21} = 0b001;
3898 let Inst{20-16} = src;
3899 let Inst{4-0} = dst;
3901 let isCodeGenOnly = 0 in
3902 def A2_tfrrcr : TFR_CR_RS_base<CtrRegs, IntRegs, 0b0>;
3903 def : InstAlias<"m0 = $Rs", (A2_tfrrcr C6, IntRegs:$Rs)>;
3904 def : InstAlias<"m1 = $Rs", (A2_tfrrcr C7, IntRegs:$Rs)>;
3906 let hasSideEffects = 0 in
3907 class TFR_RD_CR_base<RegisterClass RC, RegisterClass CTRC, bit isSingle>
3908 : CRInst <(outs RC:$dst), (ins CTRC:$src),
3909 "$dst = $src", [], "", CR_tc_3x_SLOT3> {
3913 let IClass = 0b0110;
3915 let Inst{27-26} = 0b10;
3916 let Inst{25} = isSingle;
3917 let Inst{24-21} = 0b0000;
3918 let Inst{20-16} = src;
3919 let Inst{4-0} = dst;
3922 let hasNewValue = 1, opNewValue = 0, isCodeGenOnly = 0 in
3923 def A2_tfrcrr : TFR_RD_CR_base<IntRegs, CtrRegs, 1>;
3924 def : InstAlias<"$Rd = m0", (A2_tfrcrr IntRegs:$Rd, C6)>;
3925 def : InstAlias<"$Rd = m1", (A2_tfrcrr IntRegs:$Rd, C7)>;
3927 // Y4_trace: Send value to etm trace.
3928 let isSoloAX = 1, hasSideEffects = 0, isCodeGenOnly = 0 in
3929 def Y4_trace: CRInst <(outs), (ins IntRegs:$Rs),
3933 let IClass = 0b0110;
3934 let Inst{27-21} = 0b0010010;
3935 let Inst{20-16} = Rs;
3938 let AddedComplexity = 100, isPredicated = 1 in
3939 def TFR_condset_ri : ALU32_rr<(outs IntRegs:$dst),
3940 (ins PredRegs:$src1, IntRegs:$src2, s12Imm:$src3),
3941 "Error; should not emit",
3942 [(set (i32 IntRegs:$dst),
3943 (i32 (select (i1 PredRegs:$src1), (i32 IntRegs:$src2),
3944 s12ImmPred:$src3)))]>;
3946 let AddedComplexity = 100, isPredicated = 1 in
3947 def TFR_condset_ir : ALU32_rr<(outs IntRegs:$dst),
3948 (ins PredRegs:$src1, s12Imm:$src2, IntRegs:$src3),
3949 "Error; should not emit",
3950 [(set (i32 IntRegs:$dst),
3951 (i32 (select (i1 PredRegs:$src1), s12ImmPred:$src2,
3952 (i32 IntRegs:$src3))))]>;
3954 let AddedComplexity = 100, isPredicated = 1 in
3955 def TFR_condset_ii : ALU32_rr<(outs IntRegs:$dst),
3956 (ins PredRegs:$src1, s12Imm:$src2, s12Imm:$src3),
3957 "Error; should not emit",
3958 [(set (i32 IntRegs:$dst),
3959 (i32 (select (i1 PredRegs:$src1), s12ImmPred:$src2,
3960 s12ImmPred:$src3)))]>;
3962 // Generate frameindex addresses.
3963 let isReMaterializable = 1 in
3964 def TFR_FI : ALU32_ri<(outs IntRegs:$dst), (ins FrameIndex:$src1),
3965 "$dst = add($src1)",
3966 [(set (i32 IntRegs:$dst), ADDRri:$src1)]>;
3968 // Support for generating global address.
3969 // Taken from X86InstrInfo.td.
3970 def SDTHexagonCONST32 : SDTypeProfile<1, 1, [SDTCisVT<0, i32>,
3973 def HexagonCONST32 : SDNode<"HexagonISD::CONST32", SDTHexagonCONST32>;
3974 def HexagonCONST32_GP : SDNode<"HexagonISD::CONST32_GP", SDTHexagonCONST32>;
3976 // HI/LO Instructions
3977 let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0 in
3978 def LO : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$global),
3979 "$dst.l = #LO($global)",
3982 let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0 in
3983 def HI : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$global),
3984 "$dst.h = #HI($global)",
3987 let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0 in
3988 def LOi : ALU32_ri<(outs IntRegs:$dst), (ins i32imm:$imm_value),
3989 "$dst.l = #LO($imm_value)",
3993 let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0 in
3994 def HIi : ALU32_ri<(outs IntRegs:$dst), (ins i32imm:$imm_value),
3995 "$dst.h = #HI($imm_value)",
3998 let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0 in
3999 def LO_jt : ALU32_ri<(outs IntRegs:$dst), (ins jumptablebase:$jt),
4000 "$dst.l = #LO($jt)",
4003 let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0 in
4004 def HI_jt : ALU32_ri<(outs IntRegs:$dst), (ins jumptablebase:$jt),
4005 "$dst.h = #HI($jt)",
4009 let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0 in
4010 def LO_label : ALU32_ri<(outs IntRegs:$dst), (ins bblabel:$label),
4011 "$dst.l = #LO($label)",
4014 let isReMaterializable = 1, isMoveImm = 1 , hasSideEffects = 0 in
4015 def HI_label : ALU32_ri<(outs IntRegs:$dst), (ins bblabel:$label),
4016 "$dst.h = #HI($label)",
4019 // This pattern is incorrect. When we add small data, we should change
4020 // this pattern to use memw(#foo).
4021 // This is for sdata.
4022 let isMoveImm = 1 in
4023 def CONST32 : LDInst<(outs IntRegs:$dst), (ins globaladdress:$global),
4024 "$dst = CONST32(#$global)",
4025 [(set (i32 IntRegs:$dst),
4026 (load (HexagonCONST32 tglobaltlsaddr:$global)))]>;
4028 // This is for non-sdata.
4029 let isReMaterializable = 1, isMoveImm = 1 in
4030 def CONST32_set : LDInst2<(outs IntRegs:$dst), (ins globaladdress:$global),
4031 "$dst = CONST32(#$global)",
4032 [(set (i32 IntRegs:$dst),
4033 (HexagonCONST32 tglobaladdr:$global))]>;
4035 let isReMaterializable = 1, isMoveImm = 1 in
4036 def CONST32_set_jt : LDInst2<(outs IntRegs:$dst), (ins jumptablebase:$jt),
4037 "$dst = CONST32(#$jt)",
4038 [(set (i32 IntRegs:$dst),
4039 (HexagonCONST32 tjumptable:$jt))]>;
4041 let isReMaterializable = 1, isMoveImm = 1 in
4042 def CONST32GP_set : LDInst2<(outs IntRegs:$dst), (ins globaladdress:$global),
4043 "$dst = CONST32(#$global)",
4044 [(set (i32 IntRegs:$dst),
4045 (HexagonCONST32_GP tglobaladdr:$global))]>;
4047 let isReMaterializable = 1, isMoveImm = 1 in
4048 def CONST32_Int_Real : LDInst2<(outs IntRegs:$dst), (ins i32imm:$global),
4049 "$dst = CONST32(#$global)",
4050 [(set (i32 IntRegs:$dst), imm:$global) ]>;
4052 // Map BlockAddress lowering to CONST32_Int_Real
4053 def : Pat<(HexagonCONST32_GP tblockaddress:$addr),
4054 (CONST32_Int_Real tblockaddress:$addr)>;
4056 let isReMaterializable = 1, isMoveImm = 1 in
4057 def CONST32_Label : LDInst2<(outs IntRegs:$dst), (ins bblabel:$label),
4058 "$dst = CONST32($label)",
4059 [(set (i32 IntRegs:$dst), (HexagonCONST32 bbl:$label))]>;
4061 let isReMaterializable = 1, isMoveImm = 1 in
4062 def CONST64_Int_Real : LDInst2<(outs DoubleRegs:$dst), (ins i64imm:$global),
4063 "$dst = CONST64(#$global)",
4064 [(set (i64 DoubleRegs:$dst), imm:$global) ]>;
4066 def TFR_PdFalse : SInst<(outs PredRegs:$dst), (ins),
4067 "$dst = xor($dst, $dst)",
4068 [(set (i1 PredRegs:$dst), 0)]>;
4070 // Pseudo instructions.
4071 def SDT_SPCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
4072 def SDT_SPCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
4073 SDTCisVT<1, i32> ]>;
4075 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeqStart,
4076 [SDNPHasChain, SDNPOutGlue]>;
4077 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeqEnd,
4078 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
4080 def SDT_SPCall : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
4082 // For tailcalls a HexagonTCRet SDNode has 3 SDNode Properties - a chain,
4083 // Optional Flag and Variable Arguments.
4084 // Its 1 Operand has pointer type.
4085 def HexagonTCRet : SDNode<"HexagonISD::TC_RETURN", SDT_SPCall,
4086 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
4088 let Defs = [R29, R30], Uses = [R31, R30, R29] in {
4089 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
4090 "Should never be emitted",
4091 [(callseq_start timm:$amt)]>;
4094 let Defs = [R29, R30, R31], Uses = [R29] in {
4095 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
4096 "Should never be emitted",
4097 [(callseq_end timm:$amt1, timm:$amt2)]>;
4100 let isCall = 1, hasSideEffects = 0,
4101 Defs = [D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10,
4102 R22, R23, R28, R31, P0, P1, P2, P3, LC0, LC1, SA0, SA1] in {
4103 def CALL : JInst<(outs), (ins calltarget:$dst),
4107 // Call subroutine indirectly.
4108 let Defs = VolatileV3.Regs, isCodeGenOnly = 0 in
4109 def J2_callr : JUMPR_MISC_CALLR<0, 1>;
4111 // Indirect tail-call.
4112 let isCodeGenOnly = 1, isCall = 1, isReturn = 1 in
4113 def TCRETURNR : T_JMPr;
4115 // Direct tail-calls.
4116 let isCall = 1, isReturn = 1, isBarrier = 1, isPredicable = 0,
4117 isTerminator = 1, isCodeGenOnly = 1 in {
4118 def TCRETURNtg : JInst<(outs), (ins calltarget:$dst), "jump $dst",
4119 [], "", J_tc_2early_SLOT23>;
4120 def TCRETURNtext : JInst<(outs), (ins calltarget:$dst), "jump $dst",
4121 [], "", J_tc_2early_SLOT23>;
4125 def : Pat<(HexagonTCRet tglobaladdr:$dst),
4126 (TCRETURNtg tglobaladdr:$dst)>;
4127 def : Pat<(HexagonTCRet texternalsym:$dst),
4128 (TCRETURNtext texternalsym:$dst)>;
4129 def : Pat<(HexagonTCRet (i32 IntRegs:$dst)),
4130 (TCRETURNR (i32 IntRegs:$dst))>;
4132 // Map from r0 = and(r1, 65535) to r0 = zxth(r1)
4133 def : Pat <(and (i32 IntRegs:$src1), 65535),
4134 (A2_zxth (i32 IntRegs:$src1))>;
4136 // Map from r0 = and(r1, 255) to r0 = zxtb(r1).
4137 def : Pat <(and (i32 IntRegs:$src1), 255),
4138 (A2_zxtb (i32 IntRegs:$src1))>;
4140 // Map Add(p1, true) to p1 = not(p1).
4141 // Add(p1, false) should never be produced,
4142 // if it does, it got to be mapped to NOOP.
4143 def : Pat <(add (i1 PredRegs:$src1), -1),
4144 (C2_not (i1 PredRegs:$src1))>;
4146 // Map from p0 = pnot(p0); r0 = mux(p0, #i, #j) => r0 = mux(p0, #j, #i).
4147 def : Pat <(select (not (i1 PredRegs:$src1)), s8ImmPred:$src2, s8ImmPred:$src3),
4148 (i32 (TFR_condset_ii (i1 PredRegs:$src1), s8ImmPred:$src3,
4151 // Map from p0 = pnot(p0); r0 = select(p0, #i, r1)
4152 // => r0 = TFR_condset_ri(p0, r1, #i)
4153 def : Pat <(select (not (i1 PredRegs:$src1)), s12ImmPred:$src2,
4154 (i32 IntRegs:$src3)),
4155 (i32 (TFR_condset_ri (i1 PredRegs:$src1), (i32 IntRegs:$src3),
4156 s12ImmPred:$src2))>;
4158 // Map from p0 = pnot(p0); r0 = mux(p0, r1, #i)
4159 // => r0 = TFR_condset_ir(p0, #i, r1)
4160 def : Pat <(select (not (i1 PredRegs:$src1)), IntRegs:$src2, s12ImmPred:$src3),
4161 (i32 (TFR_condset_ir (i1 PredRegs:$src1), s12ImmPred:$src3,
4162 (i32 IntRegs:$src2)))>;
4164 // Map from p0 = pnot(p0); if (p0) jump => if (!p0) jump.
4165 def : Pat <(brcond (not (i1 PredRegs:$src1)), bb:$offset),
4166 (J2_jumpf (i1 PredRegs:$src1), bb:$offset)>;
4168 // Map from p2 = pnot(p2); p1 = and(p0, p2) => p1 = and(p0, !p2).
4169 def : Pat <(and (i1 PredRegs:$src1), (not (i1 PredRegs:$src2))),
4170 (i1 (C2_andn (i1 PredRegs:$src1), (i1 PredRegs:$src2)))>;
4173 let AddedComplexity = 100 in
4174 def : Pat <(i64 (zextloadi1 (HexagonCONST32 tglobaladdr:$global))),
4175 (i64 (A2_combinew (A2_tfrsi 0),
4176 (L2_loadrub_io (CONST32_set tglobaladdr:$global), 0)))>,
4179 // Map from i1 loads to 32 bits. This assumes that the i1* is byte aligned.
4180 let AddedComplexity = 10 in
4181 def : Pat <(i32 (zextloadi1 ADDRriS11_0:$addr)),
4182 (i32 (A2_and (i32 (L2_loadrb_io AddrFI:$addr, 0)), (A2_tfrsi 0x1)))>;
4184 // Map from Rdd = sign_extend_inreg(Rss, i32) -> Rdd = A2_sxtw(Rss.lo).
4185 def : Pat <(i64 (sext_inreg (i64 DoubleRegs:$src1), i32)),
4186 (i64 (A2_sxtw (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_loreg))))>;
4188 // Map from Rdd = sign_extend_inreg(Rss, i16) -> Rdd = A2_sxtw(SXTH(Rss.lo)).
4189 def : Pat <(i64 (sext_inreg (i64 DoubleRegs:$src1), i16)),
4190 (i64 (A2_sxtw (i32 (A2_sxth (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
4191 subreg_loreg))))))>;
4193 // Map from Rdd = sign_extend_inreg(Rss, i8) -> Rdd = A2_sxtw(SXTB(Rss.lo)).
4194 def : Pat <(i64 (sext_inreg (i64 DoubleRegs:$src1), i8)),
4195 (i64 (A2_sxtw (i32 (A2_sxtb (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
4196 subreg_loreg))))))>;
4198 // We want to prevent emitting pnot's as much as possible.
4199 // Map brcond with an unsupported setcc to a J2_jumpf.
4200 def : Pat <(brcond (i1 (setne (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
4202 (J2_jumpf (C2_cmpeq (i32 IntRegs:$src1), (i32 IntRegs:$src2)),
4205 def : Pat <(brcond (i1 (setne (i32 IntRegs:$src1), s10ImmPred:$src2)),
4207 (J2_jumpf (C2_cmpeqi (i32 IntRegs:$src1), s10ImmPred:$src2), bb:$offset)>;
4209 def : Pat <(brcond (i1 (setne (i1 PredRegs:$src1), (i1 -1))), bb:$offset),
4210 (J2_jumpf (i1 PredRegs:$src1), bb:$offset)>;
4212 def : Pat <(brcond (i1 (setne (i1 PredRegs:$src1), (i1 0))), bb:$offset),
4213 (J2_jumpt (i1 PredRegs:$src1), bb:$offset)>;
4215 // cmp.lt(Rs, Imm) -> !cmp.ge(Rs, Imm) -> !cmp.gt(Rs, Imm-1)
4216 def : Pat <(brcond (i1 (setlt (i32 IntRegs:$src1), s8ImmPred:$src2)),
4218 (J2_jumpf (C2_cmpgti (i32 IntRegs:$src1),
4219 (DEC_CONST_SIGNED s8ImmPred:$src2)), bb:$offset)>;
4221 // cmp.lt(r0, r1) -> cmp.gt(r1, r0)
4222 def : Pat <(brcond (i1 (setlt (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
4224 (J2_jumpt (C2_cmpgt (i32 IntRegs:$src2), (i32 IntRegs:$src1)), bb:$offset)>;
4226 def : Pat <(brcond (i1 (setuge (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
4228 (J2_jumpf (C2_cmpgtup (i64 DoubleRegs:$src2), (i64 DoubleRegs:$src1)),
4231 def : Pat <(brcond (i1 (setule (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
4233 (J2_jumpf (C2_cmpgtu (i32 IntRegs:$src1), (i32 IntRegs:$src2)),
4236 def : Pat <(brcond (i1 (setule (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
4238 (J2_jumpf (C2_cmpgtup (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2)),
4241 // Map from a 64-bit select to an emulated 64-bit mux.
4242 // Hexagon does not support 64-bit MUXes; so emulate with combines.
4243 def : Pat <(select (i1 PredRegs:$src1), (i64 DoubleRegs:$src2),
4244 (i64 DoubleRegs:$src3)),
4245 (i64 (A2_combinew (i32 (C2_mux (i1 PredRegs:$src1),
4246 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
4248 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src3),
4250 (i32 (C2_mux (i1 PredRegs:$src1),
4251 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
4253 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src3),
4254 subreg_loreg))))))>;
4256 // Map from a 1-bit select to logical ops.
4257 // From LegalizeDAG.cpp: (B1 ? B2 : B3) <=> (B1 & B2)|(!B1&B3).
4258 def : Pat <(select (i1 PredRegs:$src1), (i1 PredRegs:$src2),
4259 (i1 PredRegs:$src3)),
4260 (C2_or (C2_and (i1 PredRegs:$src1), (i1 PredRegs:$src2)),
4261 (C2_and (C2_not (i1 PredRegs:$src1)), (i1 PredRegs:$src3)))>;
4263 // Map Pd = load(addr) -> Rs = load(addr); Pd = Rs.
4264 def : Pat<(i1 (load ADDRriS11_2:$addr)),
4265 (i1 (C2_tfrrp (i32 (L2_loadrb_io AddrFI:$addr, 0))))>;
4267 // Map for truncating from 64 immediates to 32 bit immediates.
4268 def : Pat<(i32 (trunc (i64 DoubleRegs:$src))),
4269 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src), subreg_loreg))>;
4271 // Map for truncating from i64 immediates to i1 bit immediates.
4272 def : Pat<(i1 (trunc (i64 DoubleRegs:$src))),
4273 (i1 (C2_tfrrp (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
4276 // Map memb(Rs) = Rdd -> memb(Rs) = Rt.
4277 def : Pat<(truncstorei8 (i64 DoubleRegs:$src), ADDRriS11_0:$addr),
4278 (S2_storerb_io AddrFI:$addr, 0, (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
4281 // Map memh(Rs) = Rdd -> memh(Rs) = Rt.
4282 def : Pat<(truncstorei16 (i64 DoubleRegs:$src), ADDRriS11_0:$addr),
4283 (S2_storerh_io AddrFI:$addr, 0, (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
4285 // Map memw(Rs) = Rdd -> memw(Rs) = Rt
4286 def : Pat<(truncstorei32 (i64 DoubleRegs:$src), ADDRriS11_0:$addr),
4287 (S2_storeri_io AddrFI:$addr, 0, (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
4290 // Map memw(Rs) = Rdd -> memw(Rs) = Rt.
4291 def : Pat<(truncstorei32 (i64 DoubleRegs:$src), ADDRriS11_0:$addr),
4292 (S2_storeri_io AddrFI:$addr, 0, (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
4295 // Map from i1 = constant<-1>; memw(addr) = i1 -> r0 = 1; memw(addr) = r0.
4296 def : Pat<(store (i1 -1), ADDRriS11_2:$addr),
4297 (S2_storerb_io AddrFI:$addr, 0, (A2_tfrsi 1))>;
4300 // Map from i1 = constant<-1>; store i1 -> r0 = 1; store r0.
4301 def : Pat<(store (i1 -1), ADDRriS11_2:$addr),
4302 (S2_storerb_io AddrFI:$addr, 0, (A2_tfrsi 1))>;
4304 // Map from memb(Rs) = Pd -> Rt = mux(Pd, #0, #1); store Rt.
4305 def : Pat<(store (i1 PredRegs:$src1), ADDRriS11_2:$addr),
4306 (S2_storerb_io AddrFI:$addr, 0, (i32 (C2_muxii (i1 PredRegs:$src1), 1, 0)) )>;
4308 // Map Rdd = anyext(Rs) -> Rdd = A2_sxtw(Rs).
4309 // Hexagon_TODO: We can probably use combine but that will cost 2 instructions.
4310 // Better way to do this?
4311 def : Pat<(i64 (anyext (i32 IntRegs:$src1))),
4312 (i64 (A2_sxtw (i32 IntRegs:$src1)))>;
4314 // Map cmple -> cmpgt.
4315 // rs <= rt -> !(rs > rt).
4316 def : Pat<(i1 (setle (i32 IntRegs:$src1), s10ExtPred:$src2)),
4317 (i1 (C2_not (C2_cmpgti (i32 IntRegs:$src1), s10ExtPred:$src2)))>;
4319 // rs <= rt -> !(rs > rt).
4320 def : Pat<(i1 (setle (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
4321 (i1 (C2_not (C2_cmpgt (i32 IntRegs:$src1), (i32 IntRegs:$src2))))>;
4323 // Rss <= Rtt -> !(Rss > Rtt).
4324 def : Pat<(i1 (setle (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
4325 (i1 (C2_not (C2_cmpgtp (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))))>;
4327 // Map cmpne -> cmpeq.
4328 // Hexagon_TODO: We should improve on this.
4329 // rs != rt -> !(rs == rt).
4330 def : Pat <(i1 (setne (i32 IntRegs:$src1), s10ExtPred:$src2)),
4331 (i1 (C2_not(i1 (C2_cmpeqi (i32 IntRegs:$src1), s10ExtPred:$src2))))>;
4333 // Map cmpne(Rs) -> !cmpeqe(Rs).
4334 // rs != rt -> !(rs == rt).
4335 def : Pat <(i1 (setne (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
4336 (i1 (C2_not (i1 (C2_cmpeq (i32 IntRegs:$src1), (i32 IntRegs:$src2)))))>;
4338 // Convert setne back to xor for hexagon since we compute w/ pred registers.
4339 def : Pat <(i1 (setne (i1 PredRegs:$src1), (i1 PredRegs:$src2))),
4340 (i1 (C2_xor (i1 PredRegs:$src1), (i1 PredRegs:$src2)))>;
4342 // Map cmpne(Rss) -> !cmpew(Rss).
4343 // rs != rt -> !(rs == rt).
4344 def : Pat <(i1 (setne (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
4345 (i1 (C2_not (i1 (C2_cmpeqp (i64 DoubleRegs:$src1),
4346 (i64 DoubleRegs:$src2)))))>;
4348 // Map cmpge(Rs, Rt) -> !(cmpgt(Rs, Rt).
4349 // rs >= rt -> !(rt > rs).
4350 def : Pat <(i1 (setge (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
4351 (i1 (C2_not (i1 (C2_cmpgt (i32 IntRegs:$src2), (i32 IntRegs:$src1)))))>;
4353 // cmpge(Rs, Imm) -> cmpgt(Rs, Imm-1)
4354 def : Pat <(i1 (setge (i32 IntRegs:$src1), s8ExtPred:$src2)),
4355 (i1 (C2_cmpgti (i32 IntRegs:$src1), (DEC_CONST_SIGNED s8ExtPred:$src2)))>;
4357 // Map cmpge(Rss, Rtt) -> !cmpgt(Rtt, Rss).
4358 // rss >= rtt -> !(rtt > rss).
4359 def : Pat <(i1 (setge (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
4360 (i1 (C2_not (i1 (C2_cmpgtp (i64 DoubleRegs:$src2),
4361 (i64 DoubleRegs:$src1)))))>;
4363 // Map cmplt(Rs, Imm) -> !cmpge(Rs, Imm).
4364 // !cmpge(Rs, Imm) -> !cmpgt(Rs, Imm-1).
4365 // rs < rt -> !(rs >= rt).
4366 def : Pat <(i1 (setlt (i32 IntRegs:$src1), s8ExtPred:$src2)),
4367 (i1 (C2_not (C2_cmpgti (i32 IntRegs:$src1), (DEC_CONST_SIGNED s8ExtPred:$src2))))>;
4369 // Map cmplt(Rs, Rt) -> cmpgt(Rt, Rs).
4370 // rs < rt -> rt > rs.
4371 // We can let assembler map it, or we can do in the compiler itself.
4372 def : Pat <(i1 (setlt (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
4373 (i1 (C2_cmpgt (i32 IntRegs:$src2), (i32 IntRegs:$src1)))>;
4375 // Map cmplt(Rss, Rtt) -> cmpgt(Rtt, Rss).
4376 // rss < rtt -> (rtt > rss).
4377 def : Pat <(i1 (setlt (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
4378 (i1 (C2_cmpgtp (i64 DoubleRegs:$src2), (i64 DoubleRegs:$src1)))>;
4380 // Map from cmpltu(Rs, Rd) -> cmpgtu(Rd, Rs)
4381 // rs < rt -> rt > rs.
4382 // We can let assembler map it, or we can do in the compiler itself.
4383 def : Pat <(i1 (setult (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
4384 (i1 (C2_cmpgtu (i32 IntRegs:$src2), (i32 IntRegs:$src1)))>;
4386 // Map from cmpltu(Rss, Rdd) -> cmpgtu(Rdd, Rss).
4387 // rs < rt -> rt > rs.
4388 def : Pat <(i1 (setult (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
4389 (i1 (C2_cmpgtup (i64 DoubleRegs:$src2), (i64 DoubleRegs:$src1)))>;
4391 // Generate cmpgeu(Rs, #0) -> cmpeq(Rs, Rs)
4392 def : Pat <(i1 (setuge (i32 IntRegs:$src1), 0)),
4393 (i1 (C2_cmpeq (i32 IntRegs:$src1), (i32 IntRegs:$src1)))>;
4395 // Generate cmpgeu(Rs, #u8) -> cmpgtu(Rs, #u8 -1)
4396 def : Pat <(i1 (setuge (i32 IntRegs:$src1), u8ExtPred:$src2)),
4397 (i1 (C2_cmpgtui (i32 IntRegs:$src1), (DEC_CONST_UNSIGNED u8ExtPred:$src2)))>;
4399 // Generate cmpgtu(Rs, #u9)
4400 def : Pat <(i1 (setugt (i32 IntRegs:$src1), u9ExtPred:$src2)),
4401 (i1 (C2_cmpgtui (i32 IntRegs:$src1), u9ExtPred:$src2))>;
4403 // Map from Rs >= Rt -> !(Rt > Rs).
4404 // rs >= rt -> !(rt > rs).
4405 def : Pat <(i1 (setuge (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
4406 (i1 (C2_not (C2_cmpgtu (i32 IntRegs:$src2), (i32 IntRegs:$src1))))>;
4408 // Map from Rs >= Rt -> !(Rt > Rs).
4409 // rs >= rt -> !(rt > rs).
4410 def : Pat <(i1 (setuge (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
4411 (i1 (C2_not (C2_cmpgtup (i64 DoubleRegs:$src2), (i64 DoubleRegs:$src1))))>;
4413 // Map from cmpleu(Rs, Rt) -> !cmpgtu(Rs, Rt).
4414 // Map from (Rs <= Rt) -> !(Rs > Rt).
4415 def : Pat <(i1 (setule (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
4416 (i1 (C2_not (C2_cmpgtu (i32 IntRegs:$src1), (i32 IntRegs:$src2))))>;
4418 // Map from cmpleu(Rss, Rtt) -> !cmpgtu(Rss, Rtt-1).
4419 // Map from (Rs <= Rt) -> !(Rs > Rt).
4420 def : Pat <(i1 (setule (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
4421 (i1 (C2_not (C2_cmpgtup (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))))>;
4425 def : Pat <(i32 (sext (i1 PredRegs:$src1))),
4426 (i32 (C2_muxii (i1 PredRegs:$src1), -1, 0))>;
4429 def : Pat <(i64 (sext (i1 PredRegs:$src1))),
4430 (i64 (A2_combinew (A2_tfrsi -1), (C2_muxii (i1 PredRegs:$src1), -1, 0)))>;
4432 // Convert sign-extended load back to load and sign extend.
4434 def: Pat <(i64 (sextloadi8 ADDRriS11_0:$src1)),
4435 (i64 (A2_sxtw (L2_loadrb_io AddrFI:$src1, 0)))>;
4437 // Convert any-extended load back to load and sign extend.
4439 def: Pat <(i64 (extloadi8 ADDRriS11_0:$src1)),
4440 (i64 (A2_sxtw (L2_loadrb_io AddrFI:$src1, 0)))>;
4442 // Convert sign-extended load back to load and sign extend.
4444 def: Pat <(i64 (sextloadi16 ADDRriS11_1:$src1)),
4445 (i64 (A2_sxtw (L2_loadrh_io AddrFI:$src1, 0)))>;
4447 // Convert sign-extended load back to load and sign extend.
4449 def: Pat <(i64 (sextloadi32 ADDRriS11_2:$src1)),
4450 (i64 (A2_sxtw (L2_loadri_io AddrFI:$src1, 0)))>;
4455 def : Pat <(i32 (zext (i1 PredRegs:$src1))),
4456 (i32 (C2_muxii (i1 PredRegs:$src1), 1, 0))>;
4459 def : Pat <(i64 (zext (i1 PredRegs:$src1))),
4460 (i64 (A2_combinew (A2_tfrsi 0), (C2_muxii (i1 PredRegs:$src1), 1, 0)))>,
4464 def : Pat <(i64 (zext (i32 IntRegs:$src1))),
4465 (i64 (A2_combinew (A2_tfrsi 0), (i32 IntRegs:$src1)))>,
4469 def: Pat <(i64 (zextloadi8 ADDRriS11_0:$src1)),
4470 (i64 (A2_combinew (A2_tfrsi 0), (L2_loadrub_io AddrFI:$src1, 0)))>,
4473 let AddedComplexity = 20 in
4474 def: Pat <(i64 (zextloadi8 (add (i32 IntRegs:$src1),
4475 s11_0ExtPred:$offset))),
4476 (i64 (A2_combinew (A2_tfrsi 0), (L2_loadrub_io IntRegs:$src1,
4477 s11_0ExtPred:$offset)))>,
4481 def: Pat <(i64 (zextloadi1 ADDRriS11_0:$src1)),
4482 (i64 (A2_combinew (A2_tfrsi 0), (L2_loadrub_io AddrFI:$src1, 0)))>,
4485 let AddedComplexity = 20 in
4486 def: Pat <(i64 (zextloadi1 (add (i32 IntRegs:$src1),
4487 s11_0ExtPred:$offset))),
4488 (i64 (A2_combinew (A2_tfrsi 0), (L2_loadrub_io IntRegs:$src1,
4489 s11_0ExtPred:$offset)))>,
4493 def: Pat <(i64 (zextloadi16 ADDRriS11_1:$src1)),
4494 (i64 (A2_combinew (A2_tfrsi 0), (L2_loadruh_io AddrFI:$src1, 0)))>,
4497 let AddedComplexity = 20 in
4498 def: Pat <(i64 (zextloadi16 (add (i32 IntRegs:$src1),
4499 s11_1ExtPred:$offset))),
4500 (i64 (A2_combinew (A2_tfrsi 0), (L2_loadruh_io IntRegs:$src1,
4501 s11_1ExtPred:$offset)))>,
4505 def: Pat <(i64 (zextloadi32 ADDRriS11_2:$src1)),
4506 (i64 (A2_combinew (A2_tfrsi 0), (L2_loadri_io AddrFI:$src1, 0)))>,
4509 let AddedComplexity = 100 in
4510 def: Pat <(i64 (zextloadi32 (i32 (add IntRegs:$src1, s11_2ExtPred:$offset)))),
4511 (i64 (A2_combinew (A2_tfrsi 0), (L2_loadri_io IntRegs:$src1,
4512 s11_2ExtPred:$offset)))>,
4515 let AddedComplexity = 10 in
4516 def: Pat <(i32 (zextloadi1 ADDRriS11_0:$src1)),
4517 (i32 (L2_loadri_io AddrFI:$src1, 0))>;
4519 // Map from Rs = Pd to Pd = mux(Pd, #1, #0)
4520 def : Pat <(i32 (zext (i1 PredRegs:$src1))),
4521 (i32 (C2_muxii (i1 PredRegs:$src1), 1, 0))>;
4523 // Map from Rs = Pd to Pd = mux(Pd, #1, #0)
4524 def : Pat <(i32 (anyext (i1 PredRegs:$src1))),
4525 (i32 (C2_muxii (i1 PredRegs:$src1), 1, 0))>;
4527 // Map from Rss = Pd to Rdd = A2_sxtw (mux(Pd, #1, #0))
4528 def : Pat <(i64 (anyext (i1 PredRegs:$src1))),
4529 (i64 (A2_sxtw (i32 (C2_muxii (i1 PredRegs:$src1), 1, 0))))>;
4532 let AddedComplexity = 100 in
4533 def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh),
4535 (i64 (zextloadi32 (i32 (add IntRegs:$src2,
4536 s11_2ExtPred:$offset2)))))),
4537 (i64 (A2_combinew (EXTRACT_SUBREG (i64 DoubleRegs:$srcHigh), subreg_loreg),
4538 (L2_loadri_io IntRegs:$src2,
4539 s11_2ExtPred:$offset2)))>;
4541 def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh),
4543 (i64 (zextloadi32 ADDRriS11_2:$srcLow)))),
4544 (i64 (A2_combinew (EXTRACT_SUBREG (i64 DoubleRegs:$srcHigh), subreg_loreg),
4545 (L2_loadri_io AddrFI:$srcLow, 0)))>;
4547 def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh),
4549 (i64 (zext (i32 IntRegs:$srcLow))))),
4550 (i64 (A2_combinew (EXTRACT_SUBREG (i64 DoubleRegs:$srcHigh), subreg_loreg),
4553 let AddedComplexity = 100 in
4554 def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh),
4556 (i64 (zextloadi32 (i32 (add IntRegs:$src2,
4557 s11_2ExtPred:$offset2)))))),
4558 (i64 (A2_combinew (EXTRACT_SUBREG (i64 DoubleRegs:$srcHigh), subreg_loreg),
4559 (L2_loadri_io IntRegs:$src2,
4560 s11_2ExtPred:$offset2)))>;
4562 def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh),
4564 (i64 (zextloadi32 ADDRriS11_2:$srcLow)))),
4565 (i64 (A2_combinew (EXTRACT_SUBREG (i64 DoubleRegs:$srcHigh), subreg_loreg),
4566 (L2_loadri_io AddrFI:$srcLow, 0)))>;
4568 def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh),
4570 (i64 (zext (i32 IntRegs:$srcLow))))),
4571 (i64 (A2_combinew (EXTRACT_SUBREG (i64 DoubleRegs:$srcHigh), subreg_loreg),
4574 // Any extended 64-bit load.
4575 // anyext i32 -> i64
4576 def: Pat <(i64 (extloadi32 ADDRriS11_2:$src1)),
4577 (i64 (A2_combinew (A2_tfrsi 0), (L2_loadri_io AddrFI:$src1, 0)))>,
4580 // When there is an offset we should prefer the pattern below over the pattern above.
4581 // The complexity of the above is 13 (gleaned from HexagonGenDAGIsel.inc)
4582 // So this complexity below is comfortably higher to allow for choosing the below.
4583 // If this is not done then we generate addresses such as
4584 // ********************************************
4585 // r1 = add (r0, #4)
4586 // r1 = memw(r1 + #0)
4588 // r1 = memw(r0 + #4)
4589 // ********************************************
4590 let AddedComplexity = 100 in
4591 def: Pat <(i64 (extloadi32 (i32 (add IntRegs:$src1, s11_2ExtPred:$offset)))),
4592 (i64 (A2_combinew (A2_tfrsi 0), (L2_loadri_io IntRegs:$src1,
4593 s11_2ExtPred:$offset)))>,
4596 // anyext i16 -> i64.
4597 def: Pat <(i64 (extloadi16 ADDRriS11_2:$src1)),
4598 (i64 (A2_combinew (A2_tfrsi 0), (L2_loadrh_io AddrFI:$src1, 0)))>,
4601 let AddedComplexity = 20 in
4602 def: Pat <(i64 (extloadi16 (add (i32 IntRegs:$src1),
4603 s11_1ExtPred:$offset))),
4604 (i64 (A2_combinew (A2_tfrsi 0), (L2_loadrh_io IntRegs:$src1,
4605 s11_1ExtPred:$offset)))>,
4608 // Map from Rdd = zxtw(Rs) -> Rdd = combine(0, Rs).
4609 def : Pat<(i64 (zext (i32 IntRegs:$src1))),
4610 (i64 (A2_combinew (A2_tfrsi 0), (i32 IntRegs:$src1)))>,
4613 // Multiply 64-bit unsigned and use upper result.
4614 def : Pat <(mulhu (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2)),
4629 (A2_combinew (A2_tfrsi 0),
4636 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
4638 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
4639 subreg_loreg)))), 32)),
4641 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg)),
4642 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_loreg)))),
4643 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_loreg)),
4644 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg)))),
4645 32)), subreg_loreg)))),
4646 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg)),
4647 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg))))>;
4649 // Multiply 64-bit signed and use upper result.
4650 def : Pat <(mulhs (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2)),
4654 (A2_combinew (A2_tfrsi 0),
4664 (A2_combinew (A2_tfrsi 0),
4671 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
4673 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
4674 subreg_loreg)))), 32)),
4676 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg)),
4677 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_loreg)))),
4678 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_loreg)),
4679 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg)))),
4680 32)), subreg_loreg)))),
4681 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg)),
4682 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg))))>;
4684 // Hexagon specific ISD nodes.
4685 //def SDTHexagonADJDYNALLOC : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>]>;
4686 def SDTHexagonADJDYNALLOC : SDTypeProfile<1, 2,
4687 [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
4688 def Hexagon_ADJDYNALLOC : SDNode<"HexagonISD::ADJDYNALLOC",
4689 SDTHexagonADJDYNALLOC>;
4690 // Needed to tag these instructions for stack layout.
4691 let usesCustomInserter = 1 in
4692 def ADJDYNALLOC : ALU32_ri<(outs IntRegs:$dst), (ins IntRegs:$src1,
4694 "$dst = add($src1, #$src2)",
4695 [(set (i32 IntRegs:$dst),
4696 (Hexagon_ADJDYNALLOC (i32 IntRegs:$src1),
4697 s16ImmPred:$src2))]>;
4699 def SDTHexagonARGEXTEND : SDTypeProfile<1, 1, [SDTCisVT<0, i32>]>;
4700 def Hexagon_ARGEXTEND : SDNode<"HexagonISD::ARGEXTEND", SDTHexagonARGEXTEND>;
4701 def ARGEXTEND : ALU32_rr <(outs IntRegs:$dst), (ins IntRegs:$src1),
4703 [(set (i32 IntRegs:$dst),
4704 (Hexagon_ARGEXTEND (i32 IntRegs:$src1)))]>;
4706 let AddedComplexity = 100 in
4707 def : Pat<(i32 (sext_inreg (Hexagon_ARGEXTEND (i32 IntRegs:$src1)), i16)),
4708 (COPY (i32 IntRegs:$src1))>;
4710 def HexagonWrapperJT: SDNode<"HexagonISD::WrapperJT", SDTIntUnaryOp>;
4712 def : Pat<(HexagonWrapperJT tjumptable:$dst),
4713 (i32 (CONST32_set_jt tjumptable:$dst))>;
4717 //===----------------------------------------------------------------------===//
4719 // Shift by immediate/register and accumulate/logical
4720 //===----------------------------------------------------------------------===//
4722 // Rx[+-&|]=asr(Rs,#u5)
4723 // Rx[+-&|^]=lsr(Rs,#u5)
4724 // Rx[+-&|^]=asl(Rs,#u5)
4726 let hasNewValue = 1, opNewValue = 0 in
4727 class T_shift_imm_acc_r <string opc1, string opc2, SDNode OpNode1,
4728 SDNode OpNode2, bits<3> majOp, bits<2> minOp>
4729 : SInst_acc<(outs IntRegs:$Rx),
4730 (ins IntRegs:$src1, IntRegs:$Rs, u5Imm:$u5),
4731 "$Rx "#opc2#opc1#"($Rs, #$u5)",
4732 [(set (i32 IntRegs:$Rx),
4733 (OpNode2 (i32 IntRegs:$src1),
4734 (OpNode1 (i32 IntRegs:$Rs), u5ImmPred:$u5)))],
4735 "$src1 = $Rx", S_2op_tc_2_SLOT23> {
4740 let IClass = 0b1000;
4742 let Inst{27-24} = 0b1110;
4743 let Inst{23-22} = majOp{2-1};
4745 let Inst{7} = majOp{0};
4746 let Inst{6-5} = minOp;
4748 let Inst{20-16} = Rs;
4749 let Inst{12-8} = u5;
4752 // Rx[+-&|]=asr(Rs,Rt)
4753 // Rx[+-&|^]=lsr(Rs,Rt)
4754 // Rx[+-&|^]=asl(Rs,Rt)
4756 let hasNewValue = 1, opNewValue = 0 in
4757 class T_shift_reg_acc_r <string opc1, string opc2, SDNode OpNode1,
4758 SDNode OpNode2, bits<2> majOp, bits<2> minOp>
4759 : SInst_acc<(outs IntRegs:$Rx),
4760 (ins IntRegs:$src1, IntRegs:$Rs, IntRegs:$Rt),
4761 "$Rx "#opc2#opc1#"($Rs, $Rt)",
4762 [(set (i32 IntRegs:$Rx),
4763 (OpNode2 (i32 IntRegs:$src1),
4764 (OpNode1 (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))],
4765 "$src1 = $Rx", S_3op_tc_2_SLOT23 > {
4770 let IClass = 0b1100;
4772 let Inst{27-24} = 0b1100;
4773 let Inst{23-22} = majOp;
4774 let Inst{7-6} = minOp;
4776 let Inst{20-16} = Rs;
4777 let Inst{12-8} = Rt;
4780 // Rxx[+-&|]=asr(Rss,#u6)
4781 // Rxx[+-&|^]=lsr(Rss,#u6)
4782 // Rxx[+-&|^]=asl(Rss,#u6)
4784 class T_shift_imm_acc_p <string opc1, string opc2, SDNode OpNode1,
4785 SDNode OpNode2, bits<3> majOp, bits<2> minOp>
4786 : SInst_acc<(outs DoubleRegs:$Rxx),
4787 (ins DoubleRegs:$src1, DoubleRegs:$Rss, u6Imm:$u6),
4788 "$Rxx "#opc2#opc1#"($Rss, #$u6)",
4789 [(set (i64 DoubleRegs:$Rxx),
4790 (OpNode2 (i64 DoubleRegs:$src1),
4791 (OpNode1 (i64 DoubleRegs:$Rss), u6ImmPred:$u6)))],
4792 "$src1 = $Rxx", S_2op_tc_2_SLOT23> {
4797 let IClass = 0b1000;
4799 let Inst{27-24} = 0b0010;
4800 let Inst{23-22} = majOp{2-1};
4801 let Inst{7} = majOp{0};
4802 let Inst{6-5} = minOp;
4803 let Inst{4-0} = Rxx;
4804 let Inst{20-16} = Rss;
4805 let Inst{13-8} = u6;
4809 // Rxx[+-&|]=asr(Rss,Rt)
4810 // Rxx[+-&|^]=lsr(Rss,Rt)
4811 // Rxx[+-&|^]=asl(Rss,Rt)
4812 // Rxx[+-&|^]=lsl(Rss,Rt)
4814 class T_shift_reg_acc_p <string opc1, string opc2, SDNode OpNode1,
4815 SDNode OpNode2, bits<3> majOp, bits<2> minOp>
4816 : SInst_acc<(outs DoubleRegs:$Rxx),
4817 (ins DoubleRegs:$src1, DoubleRegs:$Rss, IntRegs:$Rt),
4818 "$Rxx "#opc2#opc1#"($Rss, $Rt)",
4819 [(set (i64 DoubleRegs:$Rxx),
4820 (OpNode2 (i64 DoubleRegs:$src1),
4821 (OpNode1 (i64 DoubleRegs:$Rss), (i32 IntRegs:$Rt))))],
4822 "$src1 = $Rxx", S_3op_tc_2_SLOT23> {
4827 let IClass = 0b1100;
4829 let Inst{27-24} = 0b1011;
4830 let Inst{23-21} = majOp;
4831 let Inst{20-16} = Rss;
4832 let Inst{12-8} = Rt;
4833 let Inst{7-6} = minOp;
4834 let Inst{4-0} = Rxx;
4837 //===----------------------------------------------------------------------===//
4838 // Multi-class for the shift instructions with logical/arithmetic operators.
4839 //===----------------------------------------------------------------------===//
4841 multiclass xtype_imm_base<string OpcStr1, string OpcStr2, SDNode OpNode1,
4842 SDNode OpNode2, bits<3> majOp, bits<2> minOp > {
4843 def _i_r#NAME : T_shift_imm_acc_r< OpcStr1, OpcStr2, OpNode1,
4844 OpNode2, majOp, minOp >;
4845 def _i_p#NAME : T_shift_imm_acc_p< OpcStr1, OpcStr2, OpNode1,
4846 OpNode2, majOp, minOp >;
4849 multiclass xtype_imm_acc<string opc1, SDNode OpNode, bits<2>minOp> {
4850 let AddedComplexity = 100 in
4851 defm _acc : xtype_imm_base< opc1, "+= ", OpNode, add, 0b001, minOp>;
4853 defm _nac : xtype_imm_base< opc1, "-= ", OpNode, sub, 0b000, minOp>;
4854 defm _and : xtype_imm_base< opc1, "&= ", OpNode, and, 0b010, minOp>;
4855 defm _or : xtype_imm_base< opc1, "|= ", OpNode, or, 0b011, minOp>;
4858 multiclass xtype_xor_imm_acc<string opc1, SDNode OpNode, bits<2>minOp> {
4859 let AddedComplexity = 100 in
4860 defm _xacc : xtype_imm_base< opc1, "^= ", OpNode, xor, 0b100, minOp>;
4863 let isCodeGenOnly = 0 in {
4864 defm S2_asr : xtype_imm_acc<"asr", sra, 0b00>;
4866 defm S2_lsr : xtype_imm_acc<"lsr", srl, 0b01>,
4867 xtype_xor_imm_acc<"lsr", srl, 0b01>;
4869 defm S2_asl : xtype_imm_acc<"asl", shl, 0b10>,
4870 xtype_xor_imm_acc<"asl", shl, 0b10>;
4873 multiclass xtype_reg_acc_r<string opc1, SDNode OpNode, bits<2>minOp> {
4874 let AddedComplexity = 100 in
4875 def _acc : T_shift_reg_acc_r <opc1, "+= ", OpNode, add, 0b11, minOp>;
4877 def _nac : T_shift_reg_acc_r <opc1, "-= ", OpNode, sub, 0b10, minOp>;
4878 def _and : T_shift_reg_acc_r <opc1, "&= ", OpNode, and, 0b01, minOp>;
4879 def _or : T_shift_reg_acc_r <opc1, "|= ", OpNode, or, 0b00, minOp>;
4882 multiclass xtype_reg_acc_p<string opc1, SDNode OpNode, bits<2>minOp> {
4883 let AddedComplexity = 100 in
4884 def _acc : T_shift_reg_acc_p <opc1, "+= ", OpNode, add, 0b110, minOp>;
4886 def _nac : T_shift_reg_acc_p <opc1, "-= ", OpNode, sub, 0b100, minOp>;
4887 def _and : T_shift_reg_acc_p <opc1, "&= ", OpNode, and, 0b010, minOp>;
4888 def _or : T_shift_reg_acc_p <opc1, "|= ", OpNode, or, 0b000, minOp>;
4889 def _xor : T_shift_reg_acc_p <opc1, "^= ", OpNode, xor, 0b011, minOp>;
4892 multiclass xtype_reg_acc<string OpcStr, SDNode OpNode, bits<2> minOp > {
4893 defm _r_r : xtype_reg_acc_r <OpcStr, OpNode, minOp>;
4894 defm _r_p : xtype_reg_acc_p <OpcStr, OpNode, minOp>;
4897 let isCodeGenOnly = 0 in {
4898 defm S2_asl : xtype_reg_acc<"asl", shl, 0b10>;
4899 defm S2_asr : xtype_reg_acc<"asr", sra, 0b00>;
4900 defm S2_lsr : xtype_reg_acc<"lsr", srl, 0b01>;
4901 defm S2_lsl : xtype_reg_acc<"lsl", shl, 0b11>;
4904 //===----------------------------------------------------------------------===//
4905 let hasSideEffects = 0 in
4906 class T_S3op_1 <string mnemonic, RegisterClass RC, bits<2> MajOp, bits<3> MinOp,
4907 bit SwapOps, bit isSat = 0, bit isRnd = 0, bit hasShift = 0>
4908 : SInst <(outs RC:$dst),
4909 (ins DoubleRegs:$src1, DoubleRegs:$src2),
4910 "$dst = "#mnemonic#"($src1, $src2)"#!if(isRnd, ":rnd", "")
4911 #!if(hasShift,":>>1","")
4912 #!if(isSat, ":sat", ""),
4913 [], "", S_3op_tc_2_SLOT23 > {
4918 let IClass = 0b1100;
4920 let Inst{27-24} = 0b0001;
4921 let Inst{23-22} = MajOp;
4922 let Inst{20-16} = !if (SwapOps, src2, src1);
4923 let Inst{12-8} = !if (SwapOps, src1, src2);
4924 let Inst{7-5} = MinOp;
4925 let Inst{4-0} = dst;
4928 class T_S3op_64 <string mnemonic, bits<2> MajOp, bits<3> MinOp, bit SwapOps,
4929 bit isSat = 0, bit isRnd = 0, bit hasShift = 0 >
4930 : T_S3op_1 <mnemonic, DoubleRegs, MajOp, MinOp, SwapOps,
4931 isSat, isRnd, hasShift>;
4933 let isCodeGenOnly = 0 in
4934 def S2_lfsp : T_S3op_64 < "lfs", 0b10, 0b110, 0>;
4936 let hasSideEffects = 0 in
4937 class T_S3op_2 <string mnemonic, bits<3> MajOp, bit SwapOps>
4938 : SInst < (outs DoubleRegs:$Rdd),
4939 (ins DoubleRegs:$Rss, DoubleRegs:$Rtt, PredRegs:$Pu),
4940 "$Rdd = "#mnemonic#"($Rss, $Rtt, $Pu)",
4941 [], "", S_3op_tc_1_SLOT23 > {
4947 let IClass = 0b1100;
4949 let Inst{27-24} = 0b0010;
4950 let Inst{23-21} = MajOp;
4951 let Inst{20-16} = !if (SwapOps, Rtt, Rss);
4952 let Inst{12-8} = !if (SwapOps, Rss, Rtt);
4954 let Inst{4-0} = Rdd;
4957 let isCodeGenOnly = 0 in {
4958 def S2_valignrb : T_S3op_2 < "valignb", 0b000, 1>;
4959 def S2_vsplicerb : T_S3op_2 < "vspliceb", 0b100, 0>;
4962 //===----------------------------------------------------------------------===//
4963 // Template class used by vector shift, vector rotate, vector neg,
4964 // 32-bit shift, 64-bit shifts, etc.
4965 //===----------------------------------------------------------------------===//
4967 let hasSideEffects = 0 in
4968 class T_S3op_3 <string mnemonic, RegisterClass RC, bits<2> MajOp,
4969 bits<2> MinOp, bit isSat = 0, list<dag> pattern = [] >
4970 : SInst <(outs RC:$dst),
4971 (ins RC:$src1, IntRegs:$src2),
4972 "$dst = "#mnemonic#"($src1, $src2)"#!if(isSat, ":sat", ""),
4973 pattern, "", S_3op_tc_1_SLOT23> {
4978 let IClass = 0b1100;
4980 let Inst{27-24} = !if(!eq(!cast<string>(RC), "IntRegs"), 0b0110, 0b0011);
4981 let Inst{23-22} = MajOp;
4982 let Inst{20-16} = src1;
4983 let Inst{12-8} = src2;
4984 let Inst{7-6} = MinOp;
4985 let Inst{4-0} = dst;
4988 let hasNewValue = 1 in
4989 class T_S3op_shift32 <string mnemonic, SDNode OpNode, bits<2> MinOp>
4990 : T_S3op_3 <mnemonic, IntRegs, 0b01, MinOp, 0,
4991 [(set (i32 IntRegs:$dst), (OpNode (i32 IntRegs:$src1),
4992 (i32 IntRegs:$src2)))]>;
4994 let hasNewValue = 1, Itinerary = S_3op_tc_2_SLOT23 in
4995 class T_S3op_shift32_Sat <string mnemonic, bits<2> MinOp>
4996 : T_S3op_3 <mnemonic, IntRegs, 0b00, MinOp, 1, []>;
4999 class T_S3op_shift64 <string mnemonic, SDNode OpNode, bits<2> MinOp>
5000 : T_S3op_3 <mnemonic, DoubleRegs, 0b10, MinOp, 0,
5001 [(set (i64 DoubleRegs:$dst), (OpNode (i64 DoubleRegs:$src1),
5002 (i32 IntRegs:$src2)))]>;
5005 class T_S3op_shiftVect <string mnemonic, bits<2> MajOp, bits<2> MinOp>
5006 : T_S3op_3 <mnemonic, DoubleRegs, MajOp, MinOp, 0, []>;
5009 // Shift by register
5010 // Rdd=[asr|lsr|asl|lsl](Rss,Rt)
5012 let isCodeGenOnly = 0 in {
5013 def S2_asr_r_p : T_S3op_shift64 < "asr", sra, 0b00>;
5014 def S2_lsr_r_p : T_S3op_shift64 < "lsr", srl, 0b01>;
5015 def S2_asl_r_p : T_S3op_shift64 < "asl", shl, 0b10>;
5016 def S2_lsl_r_p : T_S3op_shift64 < "lsl", shl, 0b11>;
5019 // Rd=[asr|lsr|asl|lsl](Rs,Rt)
5021 let isCodeGenOnly = 0 in {
5022 def S2_asr_r_r : T_S3op_shift32<"asr", sra, 0b00>;
5023 def S2_lsr_r_r : T_S3op_shift32<"lsr", srl, 0b01>;
5024 def S2_asl_r_r : T_S3op_shift32<"asl", shl, 0b10>;
5025 def S2_lsl_r_r : T_S3op_shift32<"lsl", shl, 0b11>;
5028 // Shift by register with saturation
5029 // Rd=asr(Rs,Rt):sat
5030 // Rd=asl(Rs,Rt):sat
5032 let Defs = [USR_OVF], isCodeGenOnly = 0 in {
5033 def S2_asr_r_r_sat : T_S3op_shift32_Sat<"asr", 0b00>;
5034 def S2_asl_r_r_sat : T_S3op_shift32_Sat<"asl", 0b10>;
5037 //===----------------------------------------------------------------------===//
5038 // Template class for 'insert bitfield' instructions
5039 //===----------------------------------------------------------------------===//
5040 let hasSideEffects = 0 in
5041 class T_S3op_insert <string mnemonic, RegisterClass RC>
5042 : SInst <(outs RC:$dst),
5043 (ins RC:$src1, RC:$src2, DoubleRegs:$src3),
5044 "$dst = "#mnemonic#"($src2, $src3)" ,
5045 [], "$src1 = $dst", S_3op_tc_1_SLOT23 > {
5050 let IClass = 0b1100;
5052 let Inst{27-26} = 0b10;
5053 let Inst{25-24} = !if(!eq(!cast<string>(RC), "IntRegs"), 0b00, 0b10);
5055 let Inst{20-16} = src2;
5056 let Inst{12-8} = src3;
5057 let Inst{4-0} = dst;
5060 let hasSideEffects = 0 in
5061 class T_S2op_insert <bits<4> RegTyBits, RegisterClass RC, Operand ImmOp>
5062 : SInst <(outs RC:$dst), (ins RC:$dst2, RC:$src1, ImmOp:$src2, ImmOp:$src3),
5063 "$dst = insert($src1, #$src2, #$src3)",
5064 [], "$dst2 = $dst", S_2op_tc_2_SLOT23> {
5071 string ImmOpStr = !cast<string>(ImmOp);
5073 let bit23 = !if (!eq(ImmOpStr, "u6Imm"), src3{5}, 0);
5074 let bit13 = !if (!eq(ImmOpStr, "u6Imm"), src2{5}, 0);
5076 let IClass = 0b1000;
5078 let Inst{27-24} = RegTyBits;
5079 let Inst{23} = bit23;
5080 let Inst{22-21} = src3{4-3};
5081 let Inst{20-16} = src1;
5082 let Inst{13} = bit13;
5083 let Inst{12-8} = src2{4-0};
5084 let Inst{7-5} = src3{2-0};
5085 let Inst{4-0} = dst;
5088 // Rx=insert(Rs,Rtt)
5089 // Rx=insert(Rs,#u5,#U5)
5090 let hasNewValue = 1, isCodeGenOnly = 0 in {
5091 def S2_insert_rp : T_S3op_insert <"insert", IntRegs>;
5092 def S2_insert : T_S2op_insert <0b1111, IntRegs, u5Imm>;
5095 // Rxx=insert(Rss,Rtt)
5096 // Rxx=insert(Rss,#u6,#U6)
5097 let isCodeGenOnly = 0 in {
5098 def S2_insertp_rp : T_S3op_insert<"insert", DoubleRegs>;
5099 def S2_insertp : T_S2op_insert <0b0011, DoubleRegs, u6Imm>;
5102 //===----------------------------------------------------------------------===//
5103 // Template class for 'extract bitfield' instructions
5104 //===----------------------------------------------------------------------===//
5105 let hasNewValue = 1, hasSideEffects = 0 in
5106 class T_S3op_extract <string mnemonic, bits<2> MinOp>
5107 : SInst <(outs IntRegs:$Rd), (ins IntRegs:$Rs, DoubleRegs:$Rtt),
5108 "$Rd = "#mnemonic#"($Rs, $Rtt)",
5109 [], "", S_3op_tc_2_SLOT23 > {
5114 let IClass = 0b1100;
5116 let Inst{27-22} = 0b100100;
5117 let Inst{20-16} = Rs;
5118 let Inst{12-8} = Rtt;
5119 let Inst{7-6} = MinOp;
5123 let hasSideEffects = 0 in
5124 class T_S2op_extract <string mnemonic, bits<4> RegTyBits,
5125 RegisterClass RC, Operand ImmOp>
5126 : SInst <(outs RC:$dst), (ins RC:$src1, ImmOp:$src2, ImmOp:$src3),
5127 "$dst = "#mnemonic#"($src1, #$src2, #$src3)",
5128 [], "", S_2op_tc_2_SLOT23> {
5135 string ImmOpStr = !cast<string>(ImmOp);
5137 let bit23 = !if (!eq(ImmOpStr, "u6Imm"), src3{5},
5138 !if (!eq(mnemonic, "extractu"), 0, 1));
5140 let bit13 = !if (!eq(ImmOpStr, "u6Imm"), src2{5}, 0);
5142 let IClass = 0b1000;
5144 let Inst{27-24} = RegTyBits;
5145 let Inst{23} = bit23;
5146 let Inst{22-21} = src3{4-3};
5147 let Inst{20-16} = src1;
5148 let Inst{13} = bit13;
5149 let Inst{12-8} = src2{4-0};
5150 let Inst{7-5} = src3{2-0};
5151 let Inst{4-0} = dst;
5156 // Rdd=extractu(Rss,Rtt)
5157 // Rdd=extractu(Rss,#u6,#U6)
5158 let isCodeGenOnly = 0 in {
5159 def S2_extractup_rp : T_S3op_64 < "extractu", 0b00, 0b000, 0>;
5160 def S2_extractup : T_S2op_extract <"extractu", 0b0001, DoubleRegs, u6Imm>;
5163 // Rd=extractu(Rs,Rtt)
5164 // Rd=extractu(Rs,#u5,#U5)
5165 let hasNewValue = 1, isCodeGenOnly = 0 in {
5166 def S2_extractu_rp : T_S3op_extract<"extractu", 0b00>;
5167 def S2_extractu : T_S2op_extract <"extractu", 0b1101, IntRegs, u5Imm>;
5170 //===----------------------------------------------------------------------===//
5171 // :raw for of tableindx[bdhw] insns
5172 //===----------------------------------------------------------------------===//
5174 let hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in
5175 class tableidxRaw<string OpStr, bits<2>MinOp>
5176 : SInst <(outs IntRegs:$Rx),
5177 (ins IntRegs:$_dst_, IntRegs:$Rs, u4Imm:$u4, s6Imm:$S6),
5178 "$Rx = "#OpStr#"($Rs, #$u4, #$S6):raw",
5179 [], "$Rx = $_dst_" > {
5185 let IClass = 0b1000;
5187 let Inst{27-24} = 0b0111;
5188 let Inst{23-22} = MinOp;
5189 let Inst{21} = u4{3};
5190 let Inst{20-16} = Rs;
5191 let Inst{13-8} = S6;
5192 let Inst{7-5} = u4{2-0};
5196 let isCodeGenOnly = 0 in {
5197 def S2_tableidxb : tableidxRaw<"tableidxb", 0b00>;
5198 def S2_tableidxh : tableidxRaw<"tableidxh", 0b01>;
5199 def S2_tableidxw : tableidxRaw<"tableidxw", 0b10>;
5200 def S2_tableidxd : tableidxRaw<"tableidxd", 0b11>;
5203 // Change the sign of the immediate for Rd=-mpyi(Rs,#u8)
5204 def : Pat <(mul (i32 IntRegs:$src1), (ineg n8ImmPred:$src2)),
5205 (i32 (M2_mpysin (i32 IntRegs:$src1), u8ImmPred:$src2))>;
5207 //===----------------------------------------------------------------------===//
5208 // V3 Instructions +
5209 //===----------------------------------------------------------------------===//
5211 include "HexagonInstrInfoV3.td"
5213 //===----------------------------------------------------------------------===//
5214 // V3 Instructions -
5215 //===----------------------------------------------------------------------===//
5217 //===----------------------------------------------------------------------===//
5218 // V4 Instructions +
5219 //===----------------------------------------------------------------------===//
5221 include "HexagonInstrInfoV4.td"
5223 //===----------------------------------------------------------------------===//
5224 // V4 Instructions -
5225 //===----------------------------------------------------------------------===//
5227 //===----------------------------------------------------------------------===//
5228 // V5 Instructions +
5229 //===----------------------------------------------------------------------===//
5231 include "HexagonInstrInfoV5.td"
5233 //===----------------------------------------------------------------------===//
5234 // V5 Instructions -
5235 //===----------------------------------------------------------------------===//