1 //==- HexagonInstrInfo.td - Target Description for Hexagon -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Hexagon instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 include "HexagonInstrFormats.td"
15 include "HexagonOperands.td"
17 // Pattern fragment that combines the value type and the register class
18 // into a single parameter.
19 // The pat frags in the definitions below need to have a named register,
20 // otherwise i32 will be assumed regardless of the register class. The
21 // name of the register does not matter.
22 def I1 : PatLeaf<(i1 PredRegs:$R)>;
23 def I32 : PatLeaf<(i32 IntRegs:$R)>;
24 def I64 : PatLeaf<(i64 DoubleRegs:$R)>;
25 def F32 : PatLeaf<(f32 IntRegs:$R)>;
26 def F64 : PatLeaf<(f64 DoubleRegs:$R)>;
28 // Pattern fragments to extract the low and high subregisters from a
30 def LoReg: OutPatFrag<(ops node:$Rs),
31 (EXTRACT_SUBREG (i64 $Rs), subreg_loreg)>;
33 //===----------------------------------------------------------------------===//
35 //===----------------------------------------------------------------------===//
37 //===----------------------------------------------------------------------===//
38 let hasSideEffects = 0, isCompare = 1, InputType = "imm", isExtendable = 1,
40 class T_CMP <string mnemonic, bits<2> MajOp, bit isNot, Operand ImmOp>
41 : ALU32Inst <(outs PredRegs:$dst),
42 (ins IntRegs:$src1, ImmOp:$src2),
43 "$dst = "#!if(isNot, "!","")#mnemonic#"($src1, #$src2)",
44 [], "",ALU32_2op_tc_2early_SLOT0123 >, ImmRegRel {
48 let CextOpcode = mnemonic;
49 let opExtentBits = !if(!eq(mnemonic, "cmp.gtu"), 9, 10);
50 let isExtentSigned = !if(!eq(mnemonic, "cmp.gtu"), 0, 1);
54 let Inst{27-24} = 0b0101;
55 let Inst{23-22} = MajOp;
56 let Inst{21} = !if(!eq(mnemonic, "cmp.gtu"), 0, src2{9});
57 let Inst{20-16} = src1;
58 let Inst{13-5} = src2{8-0};
64 def C2_cmpeqi : T_CMP <"cmp.eq", 0b00, 0, s10Ext>;
65 def C2_cmpgti : T_CMP <"cmp.gt", 0b01, 0, s10Ext>;
66 def C2_cmpgtui : T_CMP <"cmp.gtu", 0b10, 0, u9Ext>;
68 class T_CMP_pat <InstHexagon MI, PatFrag OpNode, PatLeaf ImmPred>
69 : Pat<(i1 (OpNode (i32 IntRegs:$src1), ImmPred:$src2)),
70 (MI IntRegs:$src1, ImmPred:$src2)>;
72 def : T_CMP_pat <C2_cmpeqi, seteq, s10ImmPred>;
73 def : T_CMP_pat <C2_cmpgti, setgt, s10ImmPred>;
74 def : T_CMP_pat <C2_cmpgtui, setugt, u9ImmPred>;
76 //===----------------------------------------------------------------------===//
78 //===----------------------------------------------------------------------===//
79 def SDTHexagonI64I32I32 : SDTypeProfile<1, 2,
80 [SDTCisVT<0, i64>, SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
82 def HexagonCOMBINE : SDNode<"HexagonISD::COMBINE", SDTHexagonI64I32I32>;
84 let hasSideEffects = 0, hasNewValue = 1, InputType = "reg" in
85 class T_ALU32_3op<string mnemonic, bits<3> MajOp, bits<3> MinOp, bit OpsRev,
87 : ALU32_rr<(outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt),
88 "$Rd = "#mnemonic#"($Rs, $Rt)",
89 [], "", ALU32_3op_tc_1_SLOT0123>, ImmRegRel, PredRel {
90 let isCommutable = IsComm;
91 let BaseOpcode = mnemonic#_rr;
92 let CextOpcode = mnemonic;
100 let Inst{26-24} = MajOp;
101 let Inst{23-21} = MinOp;
102 let Inst{20-16} = !if(OpsRev,Rt,Rs);
103 let Inst{12-8} = !if(OpsRev,Rs,Rt);
107 let hasSideEffects = 0, hasNewValue = 1 in
108 class T_ALU32_3op_pred<string mnemonic, bits<3> MajOp, bits<3> MinOp,
109 bit OpsRev, bit PredNot, bit PredNew>
110 : ALU32_rr<(outs IntRegs:$Rd), (ins PredRegs:$Pu, IntRegs:$Rs, IntRegs:$Rt),
111 "if ("#!if(PredNot,"!","")#"$Pu"#!if(PredNew,".new","")#") "#
112 "$Rd = "#mnemonic#"($Rs, $Rt)",
113 [], "", ALU32_3op_tc_1_SLOT0123>, ImmRegRel, PredNewRel {
114 let isPredicated = 1;
115 let isPredicatedFalse = PredNot;
116 let isPredicatedNew = PredNew;
117 let BaseOpcode = mnemonic#_rr;
118 let CextOpcode = mnemonic;
127 let Inst{26-24} = MajOp;
128 let Inst{23-21} = MinOp;
129 let Inst{20-16} = !if(OpsRev,Rt,Rs);
130 let Inst{13} = PredNew;
131 let Inst{12-8} = !if(OpsRev,Rs,Rt);
132 let Inst{7} = PredNot;
137 class T_ALU32_combineh<string Op1, string Op2, bits<3> MajOp, bits<3> MinOp,
139 : T_ALU32_3op<"", MajOp, MinOp, OpsRev, 0> {
140 let AsmString = "$Rd = combine($Rs"#Op1#", $Rt"#Op2#")";
143 let isCodeGenOnly = 0 in {
144 def A2_combine_hh : T_ALU32_combineh<".h", ".h", 0b011, 0b100, 1>;
145 def A2_combine_hl : T_ALU32_combineh<".h", ".l", 0b011, 0b101, 1>;
146 def A2_combine_lh : T_ALU32_combineh<".l", ".h", 0b011, 0b110, 1>;
147 def A2_combine_ll : T_ALU32_combineh<".l", ".l", 0b011, 0b111, 1>;
150 class T_ALU32_3op_sfx<string mnemonic, string suffix, bits<3> MajOp,
151 bits<3> MinOp, bit OpsRev, bit IsComm>
152 : T_ALU32_3op<"", MajOp, MinOp, OpsRev, IsComm> {
153 let AsmString = "$Rd = "#mnemonic#"($Rs, $Rt)"#suffix;
156 let Defs = [USR_OVF], Itinerary = ALU32_3op_tc_2_SLOT0123,
157 isCodeGenOnly = 0 in {
158 def A2_addsat : T_ALU32_3op_sfx<"add", ":sat", 0b110, 0b010, 0, 1>;
159 def A2_subsat : T_ALU32_3op_sfx<"sub", ":sat", 0b110, 0b110, 1, 0>;
162 multiclass T_ALU32_3op_p<string mnemonic, bits<3> MajOp, bits<3> MinOp,
164 def t : T_ALU32_3op_pred<mnemonic, MajOp, MinOp, OpsRev, 0, 0>;
165 def f : T_ALU32_3op_pred<mnemonic, MajOp, MinOp, OpsRev, 1, 0>;
166 def tnew : T_ALU32_3op_pred<mnemonic, MajOp, MinOp, OpsRev, 0, 1>;
167 def fnew : T_ALU32_3op_pred<mnemonic, MajOp, MinOp, OpsRev, 1, 1>;
170 multiclass T_ALU32_3op_A2<string mnemonic, bits<3> MajOp, bits<3> MinOp,
171 bit OpsRev, bit IsComm> {
172 let isPredicable = 1 in
173 def A2_#NAME : T_ALU32_3op <mnemonic, MajOp, MinOp, OpsRev, IsComm>;
174 defm A2_p#NAME : T_ALU32_3op_p<mnemonic, MajOp, MinOp, OpsRev>;
177 let isCodeGenOnly = 0 in {
178 defm add : T_ALU32_3op_A2<"add", 0b011, 0b000, 0, 1>;
179 defm and : T_ALU32_3op_A2<"and", 0b001, 0b000, 0, 1>;
180 defm or : T_ALU32_3op_A2<"or", 0b001, 0b001, 0, 1>;
181 defm sub : T_ALU32_3op_A2<"sub", 0b011, 0b001, 1, 0>;
182 defm xor : T_ALU32_3op_A2<"xor", 0b001, 0b011, 0, 1>;
185 // Pats for instruction selection.
186 class BinOp32_pat<SDNode Op, InstHexagon MI, ValueType ResT>
187 : Pat<(ResT (Op (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))),
188 (ResT (MI IntRegs:$Rs, IntRegs:$Rt))>;
190 def: BinOp32_pat<add, A2_add, i32>;
191 def: BinOp32_pat<and, A2_and, i32>;
192 def: BinOp32_pat<or, A2_or, i32>;
193 def: BinOp32_pat<sub, A2_sub, i32>;
194 def: BinOp32_pat<xor, A2_xor, i32>;
196 // A few special cases producing register pairs:
197 let OutOperandList = (outs DoubleRegs:$Rd), hasNewValue = 0,
198 isCodeGenOnly = 0 in {
199 def S2_packhl : T_ALU32_3op <"packhl", 0b101, 0b100, 0, 0>;
201 let isPredicable = 1 in
202 def A2_combinew : T_ALU32_3op <"combine", 0b101, 0b000, 0, 0>;
204 // Conditional combinew uses "newt/f" instead of "t/fnew".
205 def C2_ccombinewt : T_ALU32_3op_pred<"combine", 0b101, 0b000, 0, 0, 0>;
206 def C2_ccombinewf : T_ALU32_3op_pred<"combine", 0b101, 0b000, 0, 1, 0>;
207 def C2_ccombinewnewt : T_ALU32_3op_pred<"combine", 0b101, 0b000, 0, 0, 1>;
208 def C2_ccombinewnewf : T_ALU32_3op_pred<"combine", 0b101, 0b000, 0, 1, 1>;
211 let hasSideEffects = 0, hasNewValue = 1, isCompare = 1, InputType = "reg" in
212 class T_ALU32_3op_cmp<string mnemonic, bits<2> MinOp, bit IsNeg, bit IsComm>
213 : ALU32_rr<(outs PredRegs:$Pd), (ins IntRegs:$Rs, IntRegs:$Rt),
214 "$Pd = "#mnemonic#"($Rs, $Rt)",
215 [], "", ALU32_3op_tc_1_SLOT0123>, ImmRegRel {
216 let CextOpcode = mnemonic;
217 let isCommutable = IsComm;
223 let Inst{27-24} = 0b0010;
224 let Inst{22-21} = MinOp;
225 let Inst{20-16} = Rs;
228 let Inst{3-2} = 0b00;
232 let Itinerary = ALU32_3op_tc_2early_SLOT0123, isCodeGenOnly = 0 in {
233 def C2_cmpeq : T_ALU32_3op_cmp< "cmp.eq", 0b00, 0, 1>;
234 def C2_cmpgt : T_ALU32_3op_cmp< "cmp.gt", 0b10, 0, 0>;
235 def C2_cmpgtu : T_ALU32_3op_cmp< "cmp.gtu", 0b11, 0, 0>;
238 // Patfrag to convert the usual comparison patfrags (e.g. setlt) to ones
239 // that reverse the order of the operands.
240 class RevCmp<PatFrag F> : PatFrag<(ops node:$rhs, node:$lhs), F.Fragment>;
242 // Pats for compares. They use PatFrags as operands, not SDNodes,
243 // since seteq/setgt/etc. are defined as ParFrags.
244 class T_cmp32_rr_pat<InstHexagon MI, PatFrag Op, ValueType VT>
245 : Pat<(VT (Op (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))),
246 (VT (MI IntRegs:$Rs, IntRegs:$Rt))>;
248 def: T_cmp32_rr_pat<C2_cmpeq, seteq, i1>;
249 def: T_cmp32_rr_pat<C2_cmpgt, setgt, i1>;
250 def: T_cmp32_rr_pat<C2_cmpgtu, setugt, i1>;
252 def: T_cmp32_rr_pat<C2_cmpgt, RevCmp<setlt>, i1>;
253 def: T_cmp32_rr_pat<C2_cmpgtu, RevCmp<setult>, i1>;
255 let CextOpcode = "MUX", InputType = "reg", hasNewValue = 1,
257 def C2_mux: ALU32_rr<(outs IntRegs:$Rd),
258 (ins PredRegs:$Pu, IntRegs:$Rs, IntRegs:$Rt),
259 "$Rd = mux($Pu, $Rs, $Rt)", [], "", ALU32_3op_tc_1_SLOT0123>, ImmRegRel {
265 let CextOpcode = "mux";
266 let InputType = "reg";
267 let hasSideEffects = 0;
270 let Inst{27-24} = 0b0100;
271 let Inst{20-16} = Rs;
277 def: Pat<(i32 (select (i1 PredRegs:$Pu), (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))),
278 (C2_mux PredRegs:$Pu, IntRegs:$Rs, IntRegs:$Rt)>;
280 // Combines the two immediates into a double register.
281 // Increase complexity to make it greater than any complexity of a combine
282 // that involves a register.
284 let isReMaterializable = 1, isMoveImm = 1, isAsCheapAsAMove = 1,
285 isExtentSigned = 1, isExtendable = 1, opExtentBits = 8, opExtendable = 1,
286 AddedComplexity = 75, isCodeGenOnly = 0 in
287 def A2_combineii: ALU32Inst <(outs DoubleRegs:$Rdd), (ins s8Ext:$s8, s8Imm:$S8),
288 "$Rdd = combine(#$s8, #$S8)",
289 [(set (i64 DoubleRegs:$Rdd),
290 (i64 (HexagonCOMBINE(i32 s8ExtPred:$s8), (i32 s8ImmPred:$S8))))]> {
296 let Inst{27-23} = 0b11000;
297 let Inst{22-16} = S8{7-1};
298 let Inst{13} = S8{0};
303 //===----------------------------------------------------------------------===//
304 // Template class for predicated ADD of a reg and an Immediate value.
305 //===----------------------------------------------------------------------===//
306 let hasNewValue = 1 in
307 class T_Addri_Pred <bit PredNot, bit PredNew>
308 : ALU32_ri <(outs IntRegs:$Rd),
309 (ins PredRegs:$Pu, IntRegs:$Rs, s8Ext:$s8),
310 !if(PredNot, "if (!$Pu", "if ($Pu")#!if(PredNew,".new) $Rd = ",
311 ") $Rd = ")#"add($Rs, #$s8)"> {
317 let isPredicatedNew = PredNew;
320 let Inst{27-24} = 0b0100;
321 let Inst{23} = PredNot;
322 let Inst{22-21} = Pu;
323 let Inst{20-16} = Rs;
324 let Inst{13} = PredNew;
329 //===----------------------------------------------------------------------===//
330 // A2_addi: Add a signed immediate to a register.
331 //===----------------------------------------------------------------------===//
332 let hasNewValue = 1 in
333 class T_Addri <Operand immOp, list<dag> pattern = [] >
334 : ALU32_ri <(outs IntRegs:$Rd),
335 (ins IntRegs:$Rs, immOp:$s16),
336 "$Rd = add($Rs, #$s16)", pattern,
337 //[(set (i32 IntRegs:$Rd), (add (i32 IntRegs:$Rs), (s16ExtPred:$s16)))],
338 "", ALU32_ADDI_tc_1_SLOT0123> {
345 let Inst{27-21} = s16{15-9};
346 let Inst{20-16} = Rs;
347 let Inst{13-5} = s16{8-0};
351 //===----------------------------------------------------------------------===//
352 // Multiclass for ADD of a register and an immediate value.
353 //===----------------------------------------------------------------------===//
354 multiclass Addri_Pred<string mnemonic, bit PredNot> {
355 let isPredicatedFalse = PredNot in {
356 def _c#NAME : T_Addri_Pred<PredNot, 0>;
358 def _cdn#NAME : T_Addri_Pred<PredNot, 1>;
362 let isExtendable = 1, InputType = "imm" in
363 multiclass Addri_base<string mnemonic, SDNode OpNode> {
364 let CextOpcode = mnemonic, BaseOpcode = mnemonic#_ri in {
365 let opExtendable = 2, isExtentSigned = 1, opExtentBits = 16,
367 def NAME : T_Addri< s16Ext, // Rd=add(Rs,#s16)
368 [(set (i32 IntRegs:$Rd),
369 (add IntRegs:$Rs, s16ExtPred:$s16))]>;
371 let opExtendable = 3, isExtentSigned = 1, opExtentBits = 8,
372 hasSideEffects = 0, isPredicated = 1 in {
373 defm Pt : Addri_Pred<mnemonic, 0>;
374 defm NotPt : Addri_Pred<mnemonic, 1>;
379 let isCodeGenOnly = 0 in
380 defm ADD_ri : Addri_base<"add", add>, ImmRegRel, PredNewRel;
382 //===----------------------------------------------------------------------===//
383 // Template class used for the following ALU32 instructions.
386 //===----------------------------------------------------------------------===//
387 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 10,
388 InputType = "imm", hasNewValue = 1 in
389 class T_ALU32ri_logical <string mnemonic, SDNode OpNode, bits<2> MinOp>
390 : ALU32_ri <(outs IntRegs:$Rd),
391 (ins IntRegs:$Rs, s10Ext:$s10),
392 "$Rd = "#mnemonic#"($Rs, #$s10)" ,
393 [(set (i32 IntRegs:$Rd), (OpNode (i32 IntRegs:$Rs), s10ExtPred:$s10))]> {
397 let CextOpcode = mnemonic;
401 let Inst{27-24} = 0b0110;
402 let Inst{23-22} = MinOp;
403 let Inst{21} = s10{9};
404 let Inst{20-16} = Rs;
405 let Inst{13-5} = s10{8-0};
409 let isCodeGenOnly = 0 in {
410 def OR_ri : T_ALU32ri_logical<"or", or, 0b10>, ImmRegRel;
411 def AND_ri : T_ALU32ri_logical<"and", and, 0b00>, ImmRegRel;
414 // Subtract register from immediate
415 // Rd32=sub(#s10,Rs32)
416 let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 10,
417 CextOpcode = "sub", InputType = "imm", hasNewValue = 1, isCodeGenOnly = 0 in
418 def SUB_ri: ALU32_ri <(outs IntRegs:$Rd), (ins s10Ext:$s10, IntRegs:$Rs),
419 "$Rd = sub(#$s10, $Rs)" ,
420 [(set IntRegs:$Rd, (sub s10ExtPred:$s10, IntRegs:$Rs))] > ,
428 let Inst{27-22} = 0b011001;
429 let Inst{21} = s10{9};
430 let Inst{20-16} = Rs;
431 let Inst{13-5} = s10{8-0};
436 let hasSideEffects = 0, isCodeGenOnly = 0 in
437 def A2_nop: ALU32Inst <(outs), (ins), "nop" > {
439 let Inst{27-24} = 0b1111;
441 // Rd = not(Rs) gets mapped to Rd=sub(#-1, Rs).
442 def : Pat<(not (i32 IntRegs:$src1)),
443 (SUB_ri -1, (i32 IntRegs:$src1))>;
445 let hasSideEffects = 0, hasNewValue = 1 in
446 class T_tfr16<bit isHi>
447 : ALU32Inst <(outs IntRegs:$Rx), (ins IntRegs:$src1, u16Imm:$u16),
448 "$Rx"#!if(isHi, ".h", ".l")#" = #$u16",
449 [], "$src1 = $Rx" > {
454 let Inst{27-26} = 0b00;
455 let Inst{25-24} = !if(isHi, 0b10, 0b01);
456 let Inst{23-22} = u16{15-14};
458 let Inst{20-16} = Rx;
459 let Inst{13-0} = u16{13-0};
462 let isCodeGenOnly = 0 in {
463 def A2_tfril: T_tfr16<0>;
464 def A2_tfrih: T_tfr16<1>;
467 // Conditional transfer is an alias to conditional "Rd = add(Rs, #0)".
468 let isPredicated = 1, hasNewValue = 1, opNewValue = 0 in
469 class T_tfr_pred<bit isPredNot, bit isPredNew>
470 : ALU32Inst<(outs IntRegs:$dst),
471 (ins PredRegs:$src1, IntRegs:$src2),
472 "if ("#!if(isPredNot, "!", "")#
473 "$src1"#!if(isPredNew, ".new", "")#
479 let isPredicatedFalse = isPredNot;
480 let isPredicatedNew = isPredNew;
483 let Inst{27-24} = 0b0100;
484 let Inst{23} = isPredNot;
485 let Inst{13} = isPredNew;
488 let Inst{22-21} = src1;
489 let Inst{20-16} = src2;
492 let isPredicable = 1 in
493 class T_tfr : ALU32Inst<(outs IntRegs:$dst), (ins IntRegs:$src),
500 let Inst{27-21} = 0b0000011;
501 let Inst{20-16} = src;
506 let InputType = "reg", hasNewValue = 1, hasSideEffects = 0 in
507 multiclass tfr_base<string CextOp> {
508 let CextOpcode = CextOp, BaseOpcode = CextOp in {
512 def t : T_tfr_pred<0, 0>;
513 def f : T_tfr_pred<1, 0>;
515 def tnew : T_tfr_pred<0, 1>;
516 def fnew : T_tfr_pred<1, 1>;
520 // Assembler mapped to C2_ccombinew[t|f|newt|newf].
521 // Please don't add bits to this instruction as it'll be converted into
522 // 'combine' before object code emission.
523 let isPredicated = 1 in
524 class T_tfrp_pred<bit PredNot, bit PredNew>
525 : ALU32_rr <(outs DoubleRegs:$dst),
526 (ins PredRegs:$src1, DoubleRegs:$src2),
527 "if ("#!if(PredNot, "!", "")#"$src1"
528 #!if(PredNew, ".new", "")#") $dst = $src2" > {
529 let isPredicatedFalse = PredNot;
530 let isPredicatedNew = PredNew;
533 // Assembler mapped to A2_combinew.
534 // Please don't add bits to this instruction as it'll be converted into
535 // 'combine' before object code emission.
536 class T_tfrp : ALU32Inst <(outs DoubleRegs:$dst),
537 (ins DoubleRegs:$src),
540 let hasSideEffects = 0 in
541 multiclass TFR64_base<string BaseName> {
542 let BaseOpcode = BaseName in {
543 let isPredicable = 1 in
546 def t : T_tfrp_pred <0, 0>;
547 def f : T_tfrp_pred <1, 0>;
549 def tnew : T_tfrp_pred <0, 1>;
550 def fnew : T_tfrp_pred <1, 1>;
554 let InputType = "imm", isExtendable = 1, isExtentSigned = 1, opExtentBits = 12,
555 isMoveImm = 1, opExtendable = 2, BaseOpcode = "TFRI", CextOpcode = "TFR",
556 hasSideEffects = 0, isPredicated = 1, hasNewValue = 1 in
557 class T_TFRI_Pred<bit PredNot, bit PredNew>
558 : ALU32_ri<(outs IntRegs:$Rd), (ins PredRegs:$Pu, s12Ext:$s12),
559 "if ("#!if(PredNot,"!","")#"$Pu"#!if(PredNew,".new","")#") $Rd = #$s12",
560 [], "", ALU32_2op_tc_1_SLOT0123>, ImmRegRel, PredNewRel {
561 let isPredicatedFalse = PredNot;
562 let isPredicatedNew = PredNew;
569 let Inst{27-24} = 0b1110;
570 let Inst{23} = PredNot;
571 let Inst{22-21} = Pu;
573 let Inst{19-16,12-5} = s12;
574 let Inst{13} = PredNew;
578 let isCodeGenOnly = 0 in {
579 def C2_cmoveit : T_TFRI_Pred<0, 0>;
580 def C2_cmoveif : T_TFRI_Pred<1, 0>;
581 def C2_cmovenewit : T_TFRI_Pred<0, 1>;
582 def C2_cmovenewif : T_TFRI_Pred<1, 1>;
585 let InputType = "imm", isExtendable = 1, isExtentSigned = 1,
586 CextOpcode = "TFR", BaseOpcode = "TFRI", hasNewValue = 1, opNewValue = 0,
587 isAsCheapAsAMove = 1 , opExtendable = 1, opExtentBits = 16, isMoveImm = 1,
588 isPredicated = 0, isPredicable = 1, isReMaterializable = 1,
590 def A2_tfrsi : ALU32Inst<(outs IntRegs:$Rd), (ins s16Ext:$s16), "$Rd = #$s16",
591 [(set (i32 IntRegs:$Rd), s16ExtPred:$s16)], "", ALU32_2op_tc_1_SLOT0123>,
597 let Inst{27-24} = 0b1000;
598 let Inst{23-22,20-16,13-5} = s16;
602 let isCodeGenOnly = 0 in
603 defm A2_tfr : tfr_base<"TFR">, ImmRegRel, PredNewRel;
604 defm A2_tfrp : TFR64_base<"TFR64">, PredNewRel;
607 let isReMaterializable = 1, isMoveImm = 1, isAsCheapAsAMove = 1 in
608 def A2_tfrpi : ALU64_rr<(outs DoubleRegs:$dst), (ins s8Imm64:$src1),
610 [(set (i64 DoubleRegs:$dst), s8Imm64Pred:$src1)]>;
612 // TODO: see if this instruction can be deleted..
613 let isExtendable = 1, opExtendable = 1, opExtentBits = 6 in
614 def TFRI64_V4 : ALU64_rr<(outs DoubleRegs:$dst), (ins u6Ext:$src1),
617 // Transfer control register.
618 let hasSideEffects = 0 in
619 def TFCR : CRInst<(outs CRRegs:$dst), (ins IntRegs:$src1),
622 //===----------------------------------------------------------------------===//
624 //===----------------------------------------------------------------------===//
627 //===----------------------------------------------------------------------===//
629 //===----------------------------------------------------------------------===//
630 // Scalar mux register immediate.
631 let hasSideEffects = 0, isExtentSigned = 1, CextOpcode = "MUX",
632 InputType = "imm", hasNewValue = 1, isExtendable = 1, opExtentBits = 8 in
633 class T_MUX1 <bit MajOp, dag ins, string AsmStr>
634 : ALU32Inst <(outs IntRegs:$Rd), ins, AsmStr>, ImmRegRel {
641 let Inst{27-24} = 0b0011;
642 let Inst{23} = MajOp;
643 let Inst{22-21} = Pu;
644 let Inst{20-16} = Rs;
650 let opExtendable = 2, isCodeGenOnly = 0 in
651 def C2_muxri : T_MUX1<0b1, (ins PredRegs:$Pu, s8Ext:$s8, IntRegs:$Rs),
652 "$Rd = mux($Pu, #$s8, $Rs)">;
654 let opExtendable = 3, isCodeGenOnly = 0 in
655 def C2_muxir : T_MUX1<0b0, (ins PredRegs:$Pu, IntRegs:$Rs, s8Ext:$s8),
656 "$Rd = mux($Pu, $Rs, #$s8)">;
658 def : Pat<(i32 (select I1:$Pu, s8ExtPred:$s8, I32:$Rs)),
659 (C2_muxri I1:$Pu, s8ExtPred:$s8, I32:$Rs)>;
661 def : Pat<(i32 (select I1:$Pu, I32:$Rs, s8ExtPred:$s8)),
662 (C2_muxir I1:$Pu, I32:$Rs, s8ExtPred:$s8)>;
664 // C2_muxii: Scalar mux immediates.
665 let isExtentSigned = 1, hasNewValue = 1, isExtendable = 1,
666 opExtentBits = 8, opExtendable = 2, isCodeGenOnly = 0 in
667 def C2_muxii: ALU32Inst <(outs IntRegs:$Rd),
668 (ins PredRegs:$Pu, s8Ext:$s8, s8Imm:$S8),
669 "$Rd = mux($Pu, #$s8, #$S8)" ,
670 [(set (i32 IntRegs:$Rd),
671 (i32 (select I1:$Pu, s8ExtPred:$s8, s8ImmPred:$S8)))] > {
679 let Inst{27-25} = 0b101;
680 let Inst{24-23} = Pu;
681 let Inst{22-16} = S8{7-1};
682 let Inst{13} = S8{0};
687 //===----------------------------------------------------------------------===//
688 // template class for non-predicated alu32_2op instructions
689 // - aslh, asrh, sxtb, sxth, zxth
690 //===----------------------------------------------------------------------===//
691 let hasNewValue = 1, opNewValue = 0 in
692 class T_ALU32_2op <string mnemonic, bits<3> minOp> :
693 ALU32Inst < (outs IntRegs:$Rd), (ins IntRegs:$Rs),
694 "$Rd = "#mnemonic#"($Rs)", [] > {
700 let Inst{27-24} = 0b0000;
701 let Inst{23-21} = minOp;
704 let Inst{20-16} = Rs;
707 //===----------------------------------------------------------------------===//
708 // template class for predicated alu32_2op instructions
709 // - aslh, asrh, sxtb, sxth, zxtb, zxth
710 //===----------------------------------------------------------------------===//
711 let hasSideEffects = 0, validSubTargets = HasV4SubT,
712 hasNewValue = 1, opNewValue = 0 in
713 class T_ALU32_2op_Pred <string mnemonic, bits<3> minOp, bit isPredNot,
715 ALU32Inst <(outs IntRegs:$Rd), (ins PredRegs:$Pu, IntRegs:$Rs),
716 !if(isPredNot, "if (!$Pu", "if ($Pu")
717 #!if(isPredNew, ".new) ",") ")#"$Rd = "#mnemonic#"($Rs)"> {
724 let Inst{27-24} = 0b0000;
725 let Inst{23-21} = minOp;
727 let Inst{11} = isPredNot;
728 let Inst{10} = isPredNew;
731 let Inst{20-16} = Rs;
734 multiclass ALU32_2op_Pred<string mnemonic, bits<3> minOp, bit PredNot> {
735 let isPredicatedFalse = PredNot in {
736 def NAME : T_ALU32_2op_Pred<mnemonic, minOp, PredNot, 0>;
739 let isPredicatedNew = 1 in
740 def NAME#new : T_ALU32_2op_Pred<mnemonic, minOp, PredNot, 1>;
744 multiclass ALU32_2op_base<string mnemonic, bits<3> minOp> {
745 let BaseOpcode = mnemonic in {
746 let isPredicable = 1, hasSideEffects = 0 in
747 def A2_#NAME : T_ALU32_2op<mnemonic, minOp>;
749 let validSubTargets = HasV4SubT, isPredicated = 1, hasSideEffects = 0 in {
750 defm A4_p#NAME#t : ALU32_2op_Pred<mnemonic, minOp, 0>;
751 defm A4_p#NAME#f : ALU32_2op_Pred<mnemonic, minOp, 1>;
756 let isCodeGenOnly = 0 in {
757 defm aslh : ALU32_2op_base<"aslh", 0b000>, PredNewRel;
758 defm asrh : ALU32_2op_base<"asrh", 0b001>, PredNewRel;
759 defm sxtb : ALU32_2op_base<"sxtb", 0b101>, PredNewRel;
760 defm sxth : ALU32_2op_base<"sxth", 0b111>, PredNewRel;
761 defm zxth : ALU32_2op_base<"zxth", 0b110>, PredNewRel;
764 // Rd=zxtb(Rs): assembler mapped to Rd=and(Rs,#255).
765 // Compiler would want to generate 'zxtb' instead of 'and' becuase 'zxtb' has
766 // predicated forms while 'and' doesn't. Since integrated assembler can't
767 // handle 'mapped' instructions, we need to encode 'zxtb' same as 'and' where
768 // immediate operand is set to '255'.
770 let hasNewValue = 1, opNewValue = 0 in
771 class T_ZXTB: ALU32Inst < (outs IntRegs:$Rd), (ins IntRegs:$Rs),
772 "$Rd = zxtb($Rs)", [] > { // Rd = and(Rs,255)
779 let Inst{27-22} = 0b011000;
781 let Inst{20-16} = Rs;
782 let Inst{21} = s10{9};
783 let Inst{13-5} = s10{8-0};
786 //Rd=zxtb(Rs): assembler mapped to "Rd=and(Rs,#255)
787 multiclass ZXTB_base <string mnemonic, bits<3> minOp> {
788 let BaseOpcode = mnemonic in {
789 let isPredicable = 1, hasSideEffects = 0 in
790 def A2_#NAME : T_ZXTB;
792 let validSubTargets = HasV4SubT, isPredicated = 1, hasSideEffects = 0 in {
793 defm A4_p#NAME#t : ALU32_2op_Pred<mnemonic, minOp, 0>;
794 defm A4_p#NAME#f : ALU32_2op_Pred<mnemonic, minOp, 1>;
799 let isCodeGenOnly=0 in
800 defm zxtb : ZXTB_base<"zxtb",0b100>, PredNewRel;
802 def: Pat<(shl I32:$src1, (i32 16)), (A2_aslh I32:$src1)>;
803 def: Pat<(sra I32:$src1, (i32 16)), (A2_asrh I32:$src1)>;
804 def: Pat<(sext_inreg I32:$src1, i8), (A2_sxtb I32:$src1)>;
805 def: Pat<(sext_inreg I32:$src1, i16), (A2_sxth I32:$src1)>;
808 def VMUX_prr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins PredRegs:$src1,
811 "$dst = vmux($src1, $src2, $src3)",
815 //===----------------------------------------------------------------------===//
817 //===----------------------------------------------------------------------===//
820 //===----------------------------------------------------------------------===//
822 //===----------------------------------------------------------------------===//
824 // SDNode for converting immediate C to C-1.
825 def DEC_CONST_SIGNED : SDNodeXForm<imm, [{
826 // Return the byte immediate const-1 as an SDNode.
827 int32_t imm = N->getSExtValue();
828 return XformSToSM1Imm(imm);
831 // SDNode for converting immediate C to C-1.
832 def DEC_CONST_UNSIGNED : SDNodeXForm<imm, [{
833 // Return the byte immediate const-1 as an SDNode.
834 uint32_t imm = N->getZExtValue();
835 return XformUToUM1Imm(imm);
838 def CTLZ_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1),
840 [(set (i32 IntRegs:$dst), (ctlz (i32 IntRegs:$src1)))]>;
842 def CTTZ_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1),
844 [(set (i32 IntRegs:$dst), (cttz (i32 IntRegs:$src1)))]>;
846 def CTLZ64_rr : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1),
848 [(set (i32 IntRegs:$dst), (i32 (trunc (ctlz (i64 DoubleRegs:$src1)))))]>;
850 def CTTZ64_rr : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1),
852 [(set (i32 IntRegs:$dst), (i32 (trunc (cttz (i64 DoubleRegs:$src1)))))]>;
854 def TSTBIT_rr : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
855 "$dst = tstbit($src1, $src2)",
856 [(set (i1 PredRegs:$dst),
857 (setne (and (shl 1, (i32 IntRegs:$src2)), (i32 IntRegs:$src1)), 0))]>;
859 //===----------------------------------------------------------------------===//
861 //===----------------------------------------------------------------------===//
864 //===----------------------------------------------------------------------===//
866 //===----------------------------------------------------------------------===//// Add.
867 //===----------------------------------------------------------------------===//
869 // Add/Subtract halfword
870 // Rd=add(Rt.L,Rs.[HL])[:sat]
871 // Rd=sub(Rt.L,Rs.[HL])[:sat]
872 // Rd=add(Rt.[LH],Rs.[HL])[:sat][:<16]
873 // Rd=sub(Rt.[LH],Rs.[HL])[:sat][:<16]
874 //===----------------------------------------------------------------------===//
876 let hasNewValue = 1, opNewValue = 0 in
877 class T_XTYPE_ADD_SUB <bits<2> LHbits, bit isSat, bit hasShift, bit isSub>
878 : ALU64Inst <(outs IntRegs:$Rd), (ins IntRegs:$Rt, IntRegs:$Rs),
879 "$Rd = "#!if(isSub,"sub","add")#"($Rt."
880 #!if(hasShift, !if(LHbits{1},"h","l"),"l") #", $Rs."
881 #!if(hasShift, !if(LHbits{0},"h)","l)"), !if(LHbits{1},"h)","l)"))
882 #!if(isSat,":sat","")
883 #!if(hasShift,":<<16",""), [], "", ALU64_tc_1_SLOT23> {
889 let Inst{27-23} = 0b01010;
890 let Inst{22} = hasShift;
891 let Inst{21} = isSub;
893 let Inst{6-5} = LHbits;
896 let Inst{20-16} = Rs;
899 //Rd=sub(Rt.L,Rs.[LH])
900 let isCodeGenOnly = 0 in {
901 def A2_subh_l16_ll : T_XTYPE_ADD_SUB <0b00, 0, 0, 1>;
902 def A2_subh_l16_hl : T_XTYPE_ADD_SUB <0b10, 0, 0, 1>;
905 let isCodeGenOnly = 0 in {
906 //Rd=add(Rt.L,Rs.[LH])
907 def A2_addh_l16_ll : T_XTYPE_ADD_SUB <0b00, 0, 0, 0>;
908 def A2_addh_l16_hl : T_XTYPE_ADD_SUB <0b10, 0, 0, 0>;
911 let Itinerary = ALU64_tc_2_SLOT23, Defs = [USR_OVF], isCodeGenOnly = 0 in {
912 //Rd=sub(Rt.L,Rs.[LH]):sat
913 def A2_subh_l16_sat_ll : T_XTYPE_ADD_SUB <0b00, 1, 0, 1>;
914 def A2_subh_l16_sat_hl : T_XTYPE_ADD_SUB <0b10, 1, 0, 1>;
916 //Rd=add(Rt.L,Rs.[LH]):sat
917 def A2_addh_l16_sat_ll : T_XTYPE_ADD_SUB <0b00, 1, 0, 0>;
918 def A2_addh_l16_sat_hl : T_XTYPE_ADD_SUB <0b10, 1, 0, 0>;
921 //Rd=sub(Rt.[LH],Rs.[LH]):<<16
922 let isCodeGenOnly = 0 in {
923 def A2_subh_h16_ll : T_XTYPE_ADD_SUB <0b00, 0, 1, 1>;
924 def A2_subh_h16_lh : T_XTYPE_ADD_SUB <0b01, 0, 1, 1>;
925 def A2_subh_h16_hl : T_XTYPE_ADD_SUB <0b10, 0, 1, 1>;
926 def A2_subh_h16_hh : T_XTYPE_ADD_SUB <0b11, 0, 1, 1>;
929 //Rd=add(Rt.[LH],Rs.[LH]):<<16
930 let isCodeGenOnly = 0 in {
931 def A2_addh_h16_ll : T_XTYPE_ADD_SUB <0b00, 0, 1, 0>;
932 def A2_addh_h16_lh : T_XTYPE_ADD_SUB <0b01, 0, 1, 0>;
933 def A2_addh_h16_hl : T_XTYPE_ADD_SUB <0b10, 0, 1, 0>;
934 def A2_addh_h16_hh : T_XTYPE_ADD_SUB <0b11, 0, 1, 0>;
937 let Itinerary = ALU64_tc_2_SLOT23, Defs = [USR_OVF], isCodeGenOnly = 0 in {
938 //Rd=sub(Rt.[LH],Rs.[LH]):sat:<<16
939 def A2_subh_h16_sat_ll : T_XTYPE_ADD_SUB <0b00, 1, 1, 1>;
940 def A2_subh_h16_sat_lh : T_XTYPE_ADD_SUB <0b01, 1, 1, 1>;
941 def A2_subh_h16_sat_hl : T_XTYPE_ADD_SUB <0b10, 1, 1, 1>;
942 def A2_subh_h16_sat_hh : T_XTYPE_ADD_SUB <0b11, 1, 1, 1>;
944 //Rd=add(Rt.[LH],Rs.[LH]):sat:<<16
945 def A2_addh_h16_sat_ll : T_XTYPE_ADD_SUB <0b00, 1, 1, 0>;
946 def A2_addh_h16_sat_lh : T_XTYPE_ADD_SUB <0b01, 1, 1, 0>;
947 def A2_addh_h16_sat_hl : T_XTYPE_ADD_SUB <0b10, 1, 1, 0>;
948 def A2_addh_h16_sat_hh : T_XTYPE_ADD_SUB <0b11, 1, 1, 0>;
952 def: Pat<(sext_inreg (add I32:$src1, I32:$src2), i16),
953 (A2_addh_l16_ll I32:$src1, I32:$src2)>;
955 def: Pat<(sra (add (shl I32:$src1, (i32 16)), I32:$src2), (i32 16)),
956 (A2_addh_l16_hl I32:$src1, I32:$src2)>;
958 def: Pat<(shl (add I32:$src1, I32:$src2), (i32 16)),
959 (A2_addh_h16_ll I32:$src1, I32:$src2)>;
961 // Subtract halfword.
962 def: Pat<(sext_inreg (sub I32:$src1, I32:$src2), i16),
963 (A2_subh_l16_ll I32:$src1, I32:$src2)>;
965 def: Pat<(shl (sub I32:$src1, I32:$src2), (i32 16)),
966 (A2_subh_h16_ll I32:$src1, I32:$src2)>;
968 let hasSideEffects = 0, hasNewValue = 1, isCodeGenOnly = 0 in
969 def S2_parityp: ALU64Inst<(outs IntRegs:$Rd),
970 (ins DoubleRegs:$Rs, DoubleRegs:$Rt),
971 "$Rd = parity($Rs, $Rt)", [], "", ALU64_tc_2_SLOT23> {
977 let Inst{27-24} = 0b0000;
978 let Inst{20-16} = Rs;
983 let hasNewValue = 1, opNewValue = 0, hasSideEffects = 0 in
984 class T_XTYPE_MIN_MAX < bit isMax, bit isUnsigned >
985 : ALU64Inst < (outs IntRegs:$Rd), (ins IntRegs:$Rt, IntRegs:$Rs),
986 "$Rd = "#!if(isMax,"max","min")#!if(isUnsigned,"u","")
987 #"($Rt, $Rs)", [], "", ALU64_tc_2_SLOT23> {
994 let Inst{27-23} = 0b01011;
995 let Inst{22-21} = !if(isMax, 0b10, 0b01);
996 let Inst{7} = isUnsigned;
998 let Inst{12-8} = !if(isMax, Rs, Rt);
999 let Inst{20-16} = !if(isMax, Rt, Rs);
1002 let isCodeGenOnly = 0 in {
1003 def A2_min : T_XTYPE_MIN_MAX < 0, 0 >;
1004 def A2_minu : T_XTYPE_MIN_MAX < 0, 1 >;
1005 def A2_max : T_XTYPE_MIN_MAX < 1, 0 >;
1006 def A2_maxu : T_XTYPE_MIN_MAX < 1, 1 >;
1009 // Here, depending on the operand being selected, we'll either generate a
1010 // min or max instruction.
1012 // (a>b)?a:b --> max(a,b) => Here check performed is '>' and the value selected
1013 // is the larger of two. So, the corresponding HexagonInst is passed in 'Inst'.
1014 // (a>b)?b:a --> min(a,b) => Here check performed is '>' but the smaller value
1015 // is selected and the corresponding HexagonInst is passed in 'SwapInst'.
1017 multiclass T_MinMax_pats <PatFrag Op, RegisterClass RC, ValueType VT,
1018 InstHexagon Inst, InstHexagon SwapInst> {
1019 def: Pat<(select (i1 (Op (VT RC:$src1), (VT RC:$src2))),
1020 (VT RC:$src1), (VT RC:$src2)),
1021 (Inst RC:$src1, RC:$src2)>;
1022 def: Pat<(select (i1 (Op (VT RC:$src1), (VT RC:$src2))),
1023 (VT RC:$src2), (VT RC:$src1)),
1024 (SwapInst RC:$src1, RC:$src2)>;
1028 multiclass MinMax_pats <PatFrag Op, InstHexagon Inst, InstHexagon SwapInst> {
1029 defm: T_MinMax_pats<Op, IntRegs, i32, Inst, SwapInst>;
1031 def: Pat<(sext_inreg (i32 (select (i1 (Op (i32 PositiveHalfWord:$src1),
1032 (i32 PositiveHalfWord:$src2))),
1033 (i32 PositiveHalfWord:$src1),
1034 (i32 PositiveHalfWord:$src2))), i16),
1035 (Inst IntRegs:$src1, IntRegs:$src2)>;
1037 def: Pat<(sext_inreg (i32 (select (i1 (Op (i32 PositiveHalfWord:$src1),
1038 (i32 PositiveHalfWord:$src2))),
1039 (i32 PositiveHalfWord:$src2),
1040 (i32 PositiveHalfWord:$src1))), i16),
1041 (SwapInst IntRegs:$src1, IntRegs:$src2)>;
1044 let AddedComplexity = 200 in {
1045 defm: MinMax_pats<setge, A2_max, A2_min>;
1046 defm: MinMax_pats<setgt, A2_max, A2_min>;
1047 defm: MinMax_pats<setle, A2_min, A2_max>;
1048 defm: MinMax_pats<setlt, A2_min, A2_max>;
1049 defm: MinMax_pats<setuge, A2_maxu, A2_minu>;
1050 defm: MinMax_pats<setugt, A2_maxu, A2_minu>;
1051 defm: MinMax_pats<setule, A2_minu, A2_maxu>;
1052 defm: MinMax_pats<setult, A2_minu, A2_maxu>;
1055 class T_cmp64_rr<string mnemonic, bits<3> MinOp, bit IsComm>
1056 : ALU64_rr<(outs PredRegs:$Pd), (ins DoubleRegs:$Rs, DoubleRegs:$Rt),
1057 "$Pd = "#mnemonic#"($Rs, $Rt)", [], "", ALU64_tc_2early_SLOT23> {
1059 let isCommutable = IsComm;
1060 let hasSideEffects = 0;
1066 let IClass = 0b1101;
1067 let Inst{27-21} = 0b0010100;
1068 let Inst{20-16} = Rs;
1069 let Inst{12-8} = Rt;
1070 let Inst{7-5} = MinOp;
1074 let isCodeGenOnly = 0 in {
1075 def C2_cmpeqp : T_cmp64_rr<"cmp.eq", 0b000, 1>;
1076 def C2_cmpgtp : T_cmp64_rr<"cmp.gt", 0b010, 0>;
1077 def C2_cmpgtup : T_cmp64_rr<"cmp.gtu", 0b100, 0>;
1080 class T_cmp64_rr_pat<InstHexagon MI, PatFrag CmpOp>
1081 : Pat<(i1 (CmpOp (i64 DoubleRegs:$Rs), (i64 DoubleRegs:$Rt))),
1082 (i1 (MI DoubleRegs:$Rs, DoubleRegs:$Rt))>;
1084 def: T_cmp64_rr_pat<C2_cmpeqp, seteq>;
1085 def: T_cmp64_rr_pat<C2_cmpgtp, setgt>;
1086 def: T_cmp64_rr_pat<C2_cmpgtup, setugt>;
1087 def: T_cmp64_rr_pat<C2_cmpgtp, RevCmp<setlt>>;
1088 def: T_cmp64_rr_pat<C2_cmpgtup, RevCmp<setult>>;
1090 class T_ALU64_rr<string mnemonic, string suffix, bits<4> RegType,
1091 bits<3> MajOp, bits<3> MinOp, bit OpsRev, bit IsComm,
1093 : ALU64_rr<(outs DoubleRegs:$Rd), (ins DoubleRegs:$Rs, DoubleRegs:$Rt),
1094 "$Rd = " #mnemonic# "($Rs, " #Op2Pfx# "$Rt)" #suffix, [],
1095 "", ALU64_tc_1_SLOT23> {
1096 let hasSideEffects = 0;
1097 let isCommutable = IsComm;
1103 let IClass = 0b1101;
1104 let Inst{27-24} = RegType;
1105 let Inst{23-21} = MajOp;
1106 let Inst{20-16} = !if (OpsRev,Rt,Rs);
1107 let Inst{12-8} = !if (OpsRev,Rs,Rt);
1108 let Inst{7-5} = MinOp;
1112 class T_ALU64_arith<string mnemonic, bits<3> MajOp, bits<3> MinOp, bit IsSat,
1113 bit OpsRev, bit IsComm>
1114 : T_ALU64_rr<mnemonic, !if(IsSat,":sat",""), 0b0011, MajOp, MinOp, OpsRev,
1117 let isCodeGenOnly = 0 in {
1118 def A2_addp : T_ALU64_arith<"add", 0b000, 0b111, 0, 0, 1>;
1119 def A2_subp : T_ALU64_arith<"sub", 0b001, 0b111, 0, 1, 0>;
1122 def: Pat<(i64 (add I64:$Rs, I64:$Rt)), (A2_addp I64:$Rs, I64:$Rt)>;
1123 def: Pat<(i64 (sub I64:$Rs, I64:$Rt)), (A2_subp I64:$Rs, I64:$Rt)>;
1125 class T_ALU64_logical<string mnemonic, bits<3> MinOp, bit OpsRev, bit IsComm,
1127 : T_ALU64_rr<mnemonic, "", 0b0011, 0b111, MinOp, OpsRev, IsComm,
1130 let isCodeGenOnly = 0 in {
1131 def A2_andp : T_ALU64_logical<"and", 0b000, 0, 1, 0>;
1132 def A2_orp : T_ALU64_logical<"or", 0b010, 0, 1, 0>;
1133 def A2_xorp : T_ALU64_logical<"xor", 0b100, 0, 1, 0>;
1136 def: Pat<(i64 (and I64:$Rs, I64:$Rt)), (A2_andp I64:$Rs, I64:$Rt)>;
1137 def: Pat<(i64 (or I64:$Rs, I64:$Rt)), (A2_orp I64:$Rs, I64:$Rt)>;
1138 def: Pat<(i64 (xor I64:$Rs, I64:$Rt)), (A2_xorp I64:$Rs, I64:$Rt)>;
1140 //===----------------------------------------------------------------------===//
1142 //===----------------------------------------------------------------------===//
1144 //===----------------------------------------------------------------------===//
1146 //===----------------------------------------------------------------------===//
1148 //===----------------------------------------------------------------------===//
1150 //===----------------------------------------------------------------------===//
1152 //===----------------------------------------------------------------------===//
1154 //===----------------------------------------------------------------------===//
1156 //===----------------------------------------------------------------------===//
1158 //===----------------------------------------------------------------------===//
1160 //===----------------------------------------------------------------------===//
1162 //===----------------------------------------------------------------------===//
1163 // Logical reductions on predicates.
1165 // Looping instructions.
1167 // Pipelined looping instructions.
1169 // Logical operations on predicates.
1170 let hasSideEffects = 0 in
1171 class T_LOGICAL_1OP<string MnOp, bits<2> OpBits>
1172 : CRInst<(outs PredRegs:$Pd), (ins PredRegs:$Ps),
1173 "$Pd = " # MnOp # "($Ps)", [], "", CR_tc_2early_SLOT23> {
1177 let IClass = 0b0110;
1178 let Inst{27-23} = 0b10111;
1179 let Inst{22-21} = OpBits;
1181 let Inst{17-16} = Ps;
1186 let isCodeGenOnly = 0 in {
1187 def C2_any8 : T_LOGICAL_1OP<"any8", 0b00>;
1188 def C2_all8 : T_LOGICAL_1OP<"all8", 0b01>;
1189 def C2_not : T_LOGICAL_1OP<"not", 0b10>;
1192 def: Pat<(i1 (not (i1 PredRegs:$Ps))),
1193 (C2_not PredRegs:$Ps)>;
1195 let hasSideEffects = 0 in
1196 class T_LOGICAL_2OP<string MnOp, bits<3> OpBits, bit IsNeg, bit Rev>
1197 : CRInst<(outs PredRegs:$Pd), (ins PredRegs:$Ps, PredRegs:$Pt),
1198 "$Pd = " # MnOp # "($Ps, " # !if (IsNeg,"!","") # "$Pt)",
1199 [], "", CR_tc_2early_SLOT23> {
1204 let IClass = 0b0110;
1205 let Inst{27-24} = 0b1011;
1206 let Inst{23-21} = OpBits;
1208 let Inst{17-16} = !if(Rev,Pt,Ps); // Rs and Rt are reversed for some
1209 let Inst{13} = 0b0; // instructions.
1210 let Inst{9-8} = !if(Rev,Ps,Pt);
1214 let isCodeGenOnly = 0 in {
1215 def C2_and : T_LOGICAL_2OP<"and", 0b000, 0, 1>;
1216 def C2_or : T_LOGICAL_2OP<"or", 0b001, 0, 1>;
1217 def C2_xor : T_LOGICAL_2OP<"xor", 0b010, 0, 0>;
1218 def C2_andn : T_LOGICAL_2OP<"and", 0b011, 1, 1>;
1219 def C2_orn : T_LOGICAL_2OP<"or", 0b111, 1, 1>;
1222 def: Pat<(i1 (and I1:$Ps, I1:$Pt)), (C2_and I1:$Ps, I1:$Pt)>;
1223 def: Pat<(i1 (or I1:$Ps, I1:$Pt)), (C2_or I1:$Ps, I1:$Pt)>;
1224 def: Pat<(i1 (xor I1:$Ps, I1:$Pt)), (C2_xor I1:$Ps, I1:$Pt)>;
1225 def: Pat<(i1 (and I1:$Ps, (not I1:$Pt))), (C2_andn I1:$Ps, I1:$Pt)>;
1226 def: Pat<(i1 (or I1:$Ps, (not I1:$Pt))), (C2_orn I1:$Ps, I1:$Pt)>;
1228 let hasSideEffects = 0, hasNewValue = 1, isCodeGenOnly = 0 in
1229 def C2_vitpack : SInst<(outs IntRegs:$Rd), (ins PredRegs:$Ps, PredRegs:$Pt),
1230 "$Rd = vitpack($Ps, $Pt)", [], "", S_2op_tc_1_SLOT23> {
1235 let IClass = 0b1000;
1236 let Inst{27-24} = 0b1001;
1237 let Inst{22-21} = 0b00;
1238 let Inst{17-16} = Ps;
1243 let hasSideEffects = 0, isCodeGenOnly = 0 in
1244 def C2_mask : SInst<(outs DoubleRegs:$Rd), (ins PredRegs:$Pt),
1245 "$Rd = mask($Pt)", [], "", S_2op_tc_1_SLOT23> {
1249 let IClass = 0b1000;
1250 let Inst{27-24} = 0b0110;
1255 def VALIGN_rrp : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
1258 "$dst = valignb($src1, $src2, $src3)",
1261 def VSPLICE_rrp : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
1264 "$dst = vspliceb($src1, $src2, $src3)",
1267 // User control register transfer.
1268 //===----------------------------------------------------------------------===//
1270 //===----------------------------------------------------------------------===//
1272 //===----------------------------------------------------------------------===//
1274 //===----------------------------------------------------------------------===//
1276 def retflag : SDNode<"HexagonISD::RET_FLAG", SDTNone,
1277 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
1278 def eh_return: SDNode<"HexagonISD::EH_RETURN", SDTNone, [SDNPHasChain]>;
1280 def SDHexagonBR_JT: SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
1281 def HexagonBR_JT: SDNode<"HexagonISD::BR_JT", SDHexagonBR_JT, [SDNPHasChain]>;
1283 class CondStr<string CReg, bit True, bit New> {
1284 string S = "if (" # !if(True,"","!") # CReg # !if(New,".new","") # ") ";
1286 class JumpOpcStr<string Mnemonic, bit New, bit Taken> {
1287 string S = Mnemonic # !if(New, !if(Taken,":t",":nt"), "");
1290 let isBranch = 1, isBarrier = 1, Defs = [PC], hasSideEffects = 0,
1292 isExtendable = 1, opExtendable = 0, isExtentSigned = 1,
1293 opExtentBits = 24, opExtentAlign = 2, InputType = "imm" in
1294 class T_JMP<string ExtStr>
1295 : JInst<(outs), (ins brtarget:$dst),
1296 "jump " # ExtStr # "$dst",
1297 [], "", J_tc_2early_SLOT23> {
1299 let IClass = 0b0101;
1301 let Inst{27-25} = 0b100;
1302 let Inst{24-16} = dst{23-15};
1303 let Inst{13-1} = dst{14-2};
1306 let isBranch = 1, Defs = [PC], hasSideEffects = 0, isPredicated = 1,
1307 isExtendable = 1, opExtendable = 1, isExtentSigned = 1,
1308 opExtentBits = 17, opExtentAlign = 2, InputType = "imm" in
1309 class T_JMP_c<bit PredNot, bit isPredNew, bit isTak, string ExtStr>
1310 : JInst<(outs), (ins PredRegs:$src, brtarget:$dst),
1311 CondStr<"$src", !if(PredNot,0,1), isPredNew>.S #
1312 JumpOpcStr<"jump", isPredNew, isTak>.S # " " #
1314 [], "", J_tc_2early_SLOT23>, ImmRegRel {
1315 let isTaken = isTak;
1316 let isPredicatedFalse = PredNot;
1317 let isPredicatedNew = isPredNew;
1321 let IClass = 0b0101;
1323 let Inst{27-24} = 0b1100;
1324 let Inst{21} = PredNot;
1325 let Inst{12} = !if(isPredNew, isTak, zero);
1326 let Inst{11} = isPredNew;
1327 let Inst{9-8} = src;
1328 let Inst{23-22} = dst{16-15};
1329 let Inst{20-16} = dst{14-10};
1330 let Inst{13} = dst{9};
1331 let Inst{7-1} = dst{8-2};
1334 multiclass JMP_Pred<bit PredNot, string ExtStr> {
1335 def NAME : T_JMP_c<PredNot, 0, 0, ExtStr>;
1337 def NAME#newpt : T_JMP_c<PredNot, 1, 1, ExtStr>; // taken
1338 def NAME#new : T_JMP_c<PredNot, 1, 0, ExtStr>; // not taken
1341 multiclass JMP_base<string BaseOp, string ExtStr> {
1342 let BaseOpcode = BaseOp in {
1343 def NAME : T_JMP<ExtStr>;
1344 defm t : JMP_Pred<0, ExtStr>;
1345 defm f : JMP_Pred<1, ExtStr>;
1349 // Jumps to address stored in a register, JUMPR_MISC
1350 // if ([[!]P[.new]]) jumpr[:t/nt] Rs
1351 let isBranch = 1, isIndirectBranch = 1, isBarrier = 1, Defs = [PC],
1352 isPredicable = 1, hasSideEffects = 0, InputType = "reg" in
1354 : JRInst<(outs), (ins IntRegs:$dst),
1355 "jumpr $dst", [], "", J_tc_2early_SLOT2> {
1358 let IClass = 0b0101;
1359 let Inst{27-21} = 0b0010100;
1360 let Inst{20-16} = dst;
1363 let isBranch = 1, isIndirectBranch = 1, Defs = [PC], isPredicated = 1,
1364 hasSideEffects = 0, InputType = "reg" in
1365 class T_JMPr_c <bit PredNot, bit isPredNew, bit isTak>
1366 : JRInst <(outs), (ins PredRegs:$src, IntRegs:$dst),
1367 CondStr<"$src", !if(PredNot,0,1), isPredNew>.S #
1368 JumpOpcStr<"jumpr", isPredNew, isTak>.S # " $dst", [],
1369 "", J_tc_2early_SLOT2> {
1371 let isTaken = isTak;
1372 let isPredicatedFalse = PredNot;
1373 let isPredicatedNew = isPredNew;
1377 let IClass = 0b0101;
1379 let Inst{27-22} = 0b001101;
1380 let Inst{21} = PredNot;
1381 let Inst{20-16} = dst;
1382 let Inst{12} = !if(isPredNew, isTak, zero);
1383 let Inst{11} = isPredNew;
1384 let Inst{9-8} = src;
1387 multiclass JMPR_Pred<bit PredNot> {
1388 def NAME: T_JMPr_c<PredNot, 0, 0>;
1390 def NAME#newpt : T_JMPr_c<PredNot, 1, 1>; // taken
1391 def NAME#new : T_JMPr_c<PredNot, 1, 0>; // not taken
1394 multiclass JMPR_base<string BaseOp> {
1395 let BaseOpcode = BaseOp in {
1397 defm t : JMPR_Pred<0>;
1398 defm f : JMPR_Pred<1>;
1402 let isCall = 1, hasSideEffects = 1 in
1403 class JUMPR_MISC_CALLR<bit isPred, bit isPredNot,
1404 dag InputDag = (ins IntRegs:$Rs)>
1405 : JRInst<(outs), InputDag,
1406 !if(isPred, !if(isPredNot, "if (!$Pu) callr $Rs",
1407 "if ($Pu) callr $Rs"),
1409 [], "", J_tc_2early_SLOT2> {
1412 let isPredicated = isPred;
1413 let isPredicatedFalse = isPredNot;
1415 let IClass = 0b0101;
1416 let Inst{27-25} = 0b000;
1417 let Inst{24-23} = !if (isPred, 0b10, 0b01);
1419 let Inst{21} = isPredNot;
1420 let Inst{9-8} = !if (isPred, Pu, 0b00);
1421 let Inst{20-16} = Rs;
1425 let Defs = VolatileV3.Regs, isCodeGenOnly = 0 in {
1426 def J2_callrt : JUMPR_MISC_CALLR<1, 0, (ins PredRegs:$Pu, IntRegs:$Rs)>;
1427 def J2_callrf : JUMPR_MISC_CALLR<1, 1, (ins PredRegs:$Pu, IntRegs:$Rs)>;
1430 let isTerminator = 1, hasSideEffects = 0, isCodeGenOnly = 0 in {
1431 defm J2_jump : JMP_base<"JMP", "">, PredNewRel;
1433 // Deal with explicit assembly
1434 // - never extened a jump #, always extend a jump ##
1435 let isAsmParserOnly = 1 in {
1436 defm J2_jump_ext : JMP_base<"JMP", "##">;
1437 defm J2_jump_noext : JMP_base<"JMP", "#">;
1440 defm J2_jumpr : JMPR_base<"JMPr">, PredNewRel;
1442 let isReturn = 1, isCodeGenOnly = 1 in
1443 defm JMPret : JMPR_base<"JMPret">, PredNewRel;
1446 def: Pat<(br bb:$dst),
1447 (J2_jump brtarget:$dst)>;
1449 (JMPret (i32 R31))>;
1450 def: Pat<(brcond (i1 PredRegs:$src1), bb:$offset),
1451 (J2_jumpt PredRegs:$src1, bb:$offset)>;
1453 // A return through builtin_eh_return.
1454 let isReturn = 1, isTerminator = 1, isBarrier = 1, hasSideEffects = 0,
1455 isCodeGenOnly = 1, Defs = [PC], Uses = [R28], isPredicable = 0 in
1456 def EH_RETURN_JMPR : T_JMPr;
1458 def: Pat<(eh_return),
1459 (EH_RETURN_JMPR (i32 R31))>;
1460 def: Pat<(HexagonBR_JT (i32 IntRegs:$dst)),
1461 (J2_jumpr IntRegs:$dst)>;
1462 def: Pat<(brind (i32 IntRegs:$dst)),
1463 (J2_jumpr IntRegs:$dst)>;
1465 //===----------------------------------------------------------------------===//
1467 //===----------------------------------------------------------------------===//
1469 //===----------------------------------------------------------------------===//
1471 //===----------------------------------------------------------------------===//
1473 // Load -- MEMri operand
1474 multiclass LD_MEMri_Pbase<string mnemonic, RegisterClass RC,
1475 bit isNot, bit isPredNew> {
1476 let isPredicatedNew = isPredNew in
1477 def NAME : LDInst2<(outs RC:$dst),
1478 (ins PredRegs:$src1, MEMri:$addr),
1479 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1480 ") ")#"$dst = "#mnemonic#"($addr)",
1484 multiclass LD_MEMri_Pred<string mnemonic, RegisterClass RC, bit PredNot> {
1485 let isPredicatedFalse = PredNot in {
1486 defm _c#NAME : LD_MEMri_Pbase<mnemonic, RC, PredNot, 0>;
1488 defm _cdn#NAME : LD_MEMri_Pbase<mnemonic, RC, PredNot, 1>;
1492 let isExtendable = 1, hasSideEffects = 0 in
1493 multiclass LD_MEMri<string mnemonic, string CextOp, RegisterClass RC,
1494 bits<5> ImmBits, bits<5> PredImmBits> {
1496 let CextOpcode = CextOp, BaseOpcode = CextOp in {
1497 let opExtendable = 2, isExtentSigned = 1, opExtentBits = ImmBits,
1499 def NAME : LDInst2<(outs RC:$dst), (ins MEMri:$addr),
1500 "$dst = "#mnemonic#"($addr)",
1503 let opExtendable = 3, isExtentSigned = 0, opExtentBits = PredImmBits,
1504 isPredicated = 1 in {
1505 defm Pt : LD_MEMri_Pred<mnemonic, RC, 0 >;
1506 defm NotPt : LD_MEMri_Pred<mnemonic, RC, 1 >;
1511 let addrMode = BaseImmOffset, isMEMri = "true" in {
1512 let accessSize = ByteAccess in {
1513 defm LDrib: LD_MEMri < "memb", "LDrib", IntRegs, 11, 6>, AddrModeRel;
1514 defm LDriub: LD_MEMri < "memub" , "LDriub", IntRegs, 11, 6>, AddrModeRel;
1517 let accessSize = HalfWordAccess in {
1518 defm LDrih: LD_MEMri < "memh", "LDrih", IntRegs, 12, 7>, AddrModeRel;
1519 defm LDriuh: LD_MEMri < "memuh", "LDriuh", IntRegs, 12, 7>, AddrModeRel;
1522 let accessSize = WordAccess in
1523 defm LDriw: LD_MEMri < "memw", "LDriw", IntRegs, 13, 8>, AddrModeRel;
1525 let accessSize = DoubleWordAccess in
1526 defm LDrid: LD_MEMri < "memd", "LDrid", DoubleRegs, 14, 9>, AddrModeRel;
1529 def : Pat < (i32 (sextloadi8 ADDRriS11_0:$addr)),
1530 (LDrib ADDRriS11_0:$addr) >;
1532 def : Pat < (i32 (zextloadi8 ADDRriS11_0:$addr)),
1533 (LDriub ADDRriS11_0:$addr) >;
1535 def : Pat < (i32 (sextloadi16 ADDRriS11_1:$addr)),
1536 (LDrih ADDRriS11_1:$addr) >;
1538 def : Pat < (i32 (zextloadi16 ADDRriS11_1:$addr)),
1539 (LDriuh ADDRriS11_1:$addr) >;
1541 def : Pat < (i32 (load ADDRriS11_2:$addr)),
1542 (LDriw ADDRriS11_2:$addr) >;
1544 def : Pat < (i64 (load ADDRriS11_3:$addr)),
1545 (LDrid ADDRriS11_3:$addr) >;
1548 // Load - Base with Immediate offset addressing mode
1549 multiclass LD_Idxd_Pbase2<string mnemonic, RegisterClass RC, Operand predImmOp,
1550 bit isNot, bit isPredNew> {
1551 let isPredicatedNew = isPredNew in
1552 def NAME : LDInst2<(outs RC:$dst),
1553 (ins PredRegs:$src1, IntRegs:$src2, predImmOp:$src3),
1554 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1555 ") ")#"$dst = "#mnemonic#"($src2+#$src3)",
1559 multiclass LD_Idxd_Pred2<string mnemonic, RegisterClass RC, Operand predImmOp,
1561 let isPredicatedFalse = PredNot in {
1562 defm _c#NAME : LD_Idxd_Pbase2<mnemonic, RC, predImmOp, PredNot, 0>;
1564 defm _cdn#NAME : LD_Idxd_Pbase2<mnemonic, RC, predImmOp, PredNot, 1>;
1568 let isExtendable = 1, hasSideEffects = 0 in
1569 multiclass LD_Idxd2<string mnemonic, string CextOp, RegisterClass RC,
1570 Operand ImmOp, Operand predImmOp, bits<5> ImmBits,
1571 bits<5> PredImmBits> {
1573 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed in {
1574 let opExtendable = 2, isExtentSigned = 1, opExtentBits = ImmBits,
1575 isPredicable = 1, AddedComplexity = 20 in
1576 def NAME : LDInst2<(outs RC:$dst), (ins IntRegs:$src1, ImmOp:$offset),
1577 "$dst = "#mnemonic#"($src1+#$offset)",
1580 let opExtendable = 3, isExtentSigned = 0, opExtentBits = PredImmBits,
1581 isPredicated = 1 in {
1582 defm Pt : LD_Idxd_Pred2<mnemonic, RC, predImmOp, 0 >;
1583 defm NotPt : LD_Idxd_Pred2<mnemonic, RC, predImmOp, 1 >;
1588 let addrMode = BaseImmOffset in {
1589 let accessSize = ByteAccess in {
1590 defm LDrib_indexed: LD_Idxd2 <"memb", "LDrib", IntRegs, s11_0Ext, u6_0Ext,
1591 11, 6>, AddrModeRel;
1592 defm LDriub_indexed: LD_Idxd2 <"memub" , "LDriub", IntRegs, s11_0Ext, u6_0Ext,
1593 11, 6>, AddrModeRel;
1595 let accessSize = HalfWordAccess in {
1596 defm LDrih_indexed: LD_Idxd2 <"memh", "LDrih", IntRegs, s11_1Ext, u6_1Ext,
1597 12, 7>, AddrModeRel;
1598 defm LDriuh_indexed: LD_Idxd2 <"memuh", "LDriuh", IntRegs, s11_1Ext, u6_1Ext,
1599 12, 7>, AddrModeRel;
1601 let accessSize = WordAccess in
1602 defm LDriw_indexed: LD_Idxd2 <"memw", "LDriw", IntRegs, s11_2Ext, u6_2Ext,
1603 13, 8>, AddrModeRel;
1605 let accessSize = DoubleWordAccess in
1606 defm LDrid_indexed: LD_Idxd2 <"memd", "LDrid", DoubleRegs, s11_3Ext, u6_3Ext,
1607 14, 9>, AddrModeRel;
1610 let AddedComplexity = 20 in {
1611 def : Pat < (i32 (sextloadi8 (add IntRegs:$src1, s11_0ExtPred:$offset))),
1612 (LDrib_indexed IntRegs:$src1, s11_0ExtPred:$offset) >;
1614 def : Pat < (i32 (zextloadi8 (add IntRegs:$src1, s11_0ExtPred:$offset))),
1615 (LDriub_indexed IntRegs:$src1, s11_0ExtPred:$offset) >;
1617 def : Pat < (i32 (sextloadi16 (add IntRegs:$src1, s11_1ExtPred:$offset))),
1618 (LDrih_indexed IntRegs:$src1, s11_1ExtPred:$offset) >;
1620 def : Pat < (i32 (zextloadi16 (add IntRegs:$src1, s11_1ExtPred:$offset))),
1621 (LDriuh_indexed IntRegs:$src1, s11_1ExtPred:$offset) >;
1623 def : Pat < (i32 (load (add IntRegs:$src1, s11_2ExtPred:$offset))),
1624 (LDriw_indexed IntRegs:$src1, s11_2ExtPred:$offset) >;
1626 def : Pat < (i64 (load (add IntRegs:$src1, s11_3ExtPred:$offset))),
1627 (LDrid_indexed IntRegs:$src1, s11_3ExtPred:$offset) >;
1630 //===----------------------------------------------------------------------===//
1631 // Post increment load
1632 //===----------------------------------------------------------------------===//
1634 multiclass LD_PostInc_Pbase<string mnemonic, RegisterClass RC, Operand ImmOp,
1635 bit isNot, bit isPredNew> {
1636 let isPredicatedNew = isPredNew in
1637 def NAME : LDInst2PI<(outs RC:$dst, IntRegs:$dst2),
1638 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset),
1639 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1640 ") ")#"$dst = "#mnemonic#"($src2++#$offset)",
1645 multiclass LD_PostInc_Pred<string mnemonic, RegisterClass RC,
1646 Operand ImmOp, bit PredNot> {
1647 let isPredicatedFalse = PredNot in {
1648 defm _c#NAME : LD_PostInc_Pbase<mnemonic, RC, ImmOp, PredNot, 0>;
1650 let Predicates = [HasV4T], validSubTargets = HasV4SubT in
1651 defm _cdn#NAME#_V4 : LD_PostInc_Pbase<mnemonic, RC, ImmOp, PredNot, 1>;
1655 multiclass LD_PostInc<string mnemonic, string BaseOp, RegisterClass RC,
1658 let BaseOpcode = "POST_"#BaseOp in {
1659 let isPredicable = 1 in
1660 def NAME : LDInst2PI<(outs RC:$dst, IntRegs:$dst2),
1661 (ins IntRegs:$src1, ImmOp:$offset),
1662 "$dst = "#mnemonic#"($src1++#$offset)",
1666 let isPredicated = 1 in {
1667 defm Pt : LD_PostInc_Pred<mnemonic, RC, ImmOp, 0 >;
1668 defm NotPt : LD_PostInc_Pred<mnemonic, RC, ImmOp, 1 >;
1673 let hasCtrlDep = 1, hasSideEffects = 0, addrMode = PostInc in {
1674 defm POST_LDrib : LD_PostInc<"memb", "LDrib", IntRegs, s4_0Imm>,
1676 defm POST_LDriub : LD_PostInc<"memub", "LDriub", IntRegs, s4_0Imm>,
1678 defm POST_LDrih : LD_PostInc<"memh", "LDrih", IntRegs, s4_1Imm>,
1680 defm POST_LDriuh : LD_PostInc<"memuh", "LDriuh", IntRegs, s4_1Imm>,
1682 defm POST_LDriw : LD_PostInc<"memw", "LDriw", IntRegs, s4_2Imm>,
1684 defm POST_LDrid : LD_PostInc<"memd", "LDrid", DoubleRegs, s4_3Imm>,
1688 def : Pat< (i32 (extloadi1 ADDRriS11_0:$addr)),
1689 (i32 (LDrib ADDRriS11_0:$addr)) >;
1691 // Load byte any-extend.
1692 def : Pat < (i32 (extloadi8 ADDRriS11_0:$addr)),
1693 (i32 (LDrib ADDRriS11_0:$addr)) >;
1695 // Indexed load byte any-extend.
1696 let AddedComplexity = 20 in
1697 def : Pat < (i32 (extloadi8 (add IntRegs:$src1, s11_0ImmPred:$offset))),
1698 (i32 (LDrib_indexed IntRegs:$src1, s11_0ImmPred:$offset)) >;
1700 def : Pat < (i32 (extloadi16 ADDRriS11_1:$addr)),
1701 (i32 (LDrih ADDRriS11_1:$addr))>;
1703 let AddedComplexity = 20 in
1704 def : Pat < (i32 (extloadi16 (add IntRegs:$src1, s11_1ImmPred:$offset))),
1705 (i32 (LDrih_indexed IntRegs:$src1, s11_1ImmPred:$offset)) >;
1707 let AddedComplexity = 10 in
1708 def : Pat < (i32 (zextloadi1 ADDRriS11_0:$addr)),
1709 (i32 (LDriub ADDRriS11_0:$addr))>;
1711 let AddedComplexity = 20 in
1712 def : Pat < (i32 (zextloadi1 (add IntRegs:$src1, s11_0ImmPred:$offset))),
1713 (i32 (LDriub_indexed IntRegs:$src1, s11_0ImmPred:$offset))>;
1716 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 13,
1717 isPseudo = 1, Defs = [R10,R11,D5], hasSideEffects = 0 in
1718 def LDriw_pred : LDInst2<(outs PredRegs:$dst),
1720 "Error; should not emit",
1723 // Deallocate stack frame.
1724 let Defs = [R29, R30, R31], Uses = [R29], hasSideEffects = 0 in {
1725 def DEALLOCFRAME : LDInst2<(outs), (ins),
1730 // Load and unpack bytes to halfwords.
1731 //===----------------------------------------------------------------------===//
1733 //===----------------------------------------------------------------------===//
1735 //===----------------------------------------------------------------------===//
1737 //===----------------------------------------------------------------------===//
1738 //===----------------------------------------------------------------------===//
1740 //===----------------------------------------------------------------------===//
1742 //===----------------------------------------------------------------------===//
1744 //===----------------------------------------------------------------------===//
1745 //===----------------------------------------------------------------------===//
1747 //===----------------------------------------------------------------------===//
1749 //===----------------------------------------------------------------------===//
1751 //===----------------------------------------------------------------------===//
1753 //===----------------------------------------------------------------------===//
1755 // MPYS / Multipy signed/unsigned halfwords
1756 //Rd=mpy[u](Rs.[H|L],Rt.[H|L])[:<<1][:rnd][:sat]
1757 //===----------------------------------------------------------------------===//
1759 let hasNewValue = 1, opNewValue = 0 in
1760 class T_M2_mpy < bits<2> LHbits, bit isSat, bit isRnd,
1761 bit hasShift, bit isUnsigned>
1762 : MInst < (outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt),
1763 "$Rd = "#!if(isUnsigned,"mpyu","mpy")#"($Rs."#!if(LHbits{1},"h","l")
1764 #", $Rt."#!if(LHbits{0},"h)","l)")
1765 #!if(hasShift,":<<1","")
1766 #!if(isRnd,":rnd","")
1767 #!if(isSat,":sat",""),
1768 [], "", M_tc_3x_SLOT23 > {
1773 let IClass = 0b1110;
1775 let Inst{27-24} = 0b1100;
1776 let Inst{23} = hasShift;
1777 let Inst{22} = isUnsigned;
1778 let Inst{21} = isRnd;
1779 let Inst{7} = isSat;
1780 let Inst{6-5} = LHbits;
1782 let Inst{20-16} = Rs;
1783 let Inst{12-8} = Rt;
1786 //Rd=mpy(Rs.[H|L],Rt.[H|L])[:<<1]
1787 let isCodeGenOnly = 0 in {
1788 def M2_mpy_ll_s1: T_M2_mpy<0b00, 0, 0, 1, 0>;
1789 def M2_mpy_ll_s0: T_M2_mpy<0b00, 0, 0, 0, 0>;
1790 def M2_mpy_lh_s1: T_M2_mpy<0b01, 0, 0, 1, 0>;
1791 def M2_mpy_lh_s0: T_M2_mpy<0b01, 0, 0, 0, 0>;
1792 def M2_mpy_hl_s1: T_M2_mpy<0b10, 0, 0, 1, 0>;
1793 def M2_mpy_hl_s0: T_M2_mpy<0b10, 0, 0, 0, 0>;
1794 def M2_mpy_hh_s1: T_M2_mpy<0b11, 0, 0, 1, 0>;
1795 def M2_mpy_hh_s0: T_M2_mpy<0b11, 0, 0, 0, 0>;
1798 //Rd=mpyu(Rs.[H|L],Rt.[H|L])[:<<1]
1799 let isCodeGenOnly = 0 in {
1800 def M2_mpyu_ll_s1: T_M2_mpy<0b00, 0, 0, 1, 1>;
1801 def M2_mpyu_ll_s0: T_M2_mpy<0b00, 0, 0, 0, 1>;
1802 def M2_mpyu_lh_s1: T_M2_mpy<0b01, 0, 0, 1, 1>;
1803 def M2_mpyu_lh_s0: T_M2_mpy<0b01, 0, 0, 0, 1>;
1804 def M2_mpyu_hl_s1: T_M2_mpy<0b10, 0, 0, 1, 1>;
1805 def M2_mpyu_hl_s0: T_M2_mpy<0b10, 0, 0, 0, 1>;
1806 def M2_mpyu_hh_s1: T_M2_mpy<0b11, 0, 0, 1, 1>;
1807 def M2_mpyu_hh_s0: T_M2_mpy<0b11, 0, 0, 0, 1>;
1810 //Rd=mpy(Rs.[H|L],Rt.[H|L])[:<<1]:rnd
1811 let isCodeGenOnly = 0 in {
1812 def M2_mpy_rnd_ll_s1: T_M2_mpy <0b00, 0, 1, 1, 0>;
1813 def M2_mpy_rnd_ll_s0: T_M2_mpy <0b00, 0, 1, 0, 0>;
1814 def M2_mpy_rnd_lh_s1: T_M2_mpy <0b01, 0, 1, 1, 0>;
1815 def M2_mpy_rnd_lh_s0: T_M2_mpy <0b01, 0, 1, 0, 0>;
1816 def M2_mpy_rnd_hl_s1: T_M2_mpy <0b10, 0, 1, 1, 0>;
1817 def M2_mpy_rnd_hl_s0: T_M2_mpy <0b10, 0, 1, 0, 0>;
1818 def M2_mpy_rnd_hh_s1: T_M2_mpy <0b11, 0, 1, 1, 0>;
1819 def M2_mpy_rnd_hh_s0: T_M2_mpy <0b11, 0, 1, 0, 0>;
1822 //Rd=mpy(Rs.[H|L],Rt.[H|L])[:<<1][:sat]
1823 //Rd=mpy(Rs.[H|L],Rt.[H|L])[:<<1][:rnd][:sat]
1824 let Defs = [USR_OVF], isCodeGenOnly = 0 in {
1825 def M2_mpy_sat_ll_s1: T_M2_mpy <0b00, 1, 0, 1, 0>;
1826 def M2_mpy_sat_ll_s0: T_M2_mpy <0b00, 1, 0, 0, 0>;
1827 def M2_mpy_sat_lh_s1: T_M2_mpy <0b01, 1, 0, 1, 0>;
1828 def M2_mpy_sat_lh_s0: T_M2_mpy <0b01, 1, 0, 0, 0>;
1829 def M2_mpy_sat_hl_s1: T_M2_mpy <0b10, 1, 0, 1, 0>;
1830 def M2_mpy_sat_hl_s0: T_M2_mpy <0b10, 1, 0, 0, 0>;
1831 def M2_mpy_sat_hh_s1: T_M2_mpy <0b11, 1, 0, 1, 0>;
1832 def M2_mpy_sat_hh_s0: T_M2_mpy <0b11, 1, 0, 0, 0>;
1834 def M2_mpy_sat_rnd_ll_s1: T_M2_mpy <0b00, 1, 1, 1, 0>;
1835 def M2_mpy_sat_rnd_ll_s0: T_M2_mpy <0b00, 1, 1, 0, 0>;
1836 def M2_mpy_sat_rnd_lh_s1: T_M2_mpy <0b01, 1, 1, 1, 0>;
1837 def M2_mpy_sat_rnd_lh_s0: T_M2_mpy <0b01, 1, 1, 0, 0>;
1838 def M2_mpy_sat_rnd_hl_s1: T_M2_mpy <0b10, 1, 1, 1, 0>;
1839 def M2_mpy_sat_rnd_hl_s0: T_M2_mpy <0b10, 1, 1, 0, 0>;
1840 def M2_mpy_sat_rnd_hh_s1: T_M2_mpy <0b11, 1, 1, 1, 0>;
1841 def M2_mpy_sat_rnd_hh_s0: T_M2_mpy <0b11, 1, 1, 0, 0>;
1844 //===----------------------------------------------------------------------===//
1846 // MPYS / Multipy signed/unsigned halfwords and add/subtract the
1847 // result from the accumulator.
1848 //Rx [-+]= mpy[u](Rs.[H|L],Rt.[H|L])[:<<1][:sat]
1849 //===----------------------------------------------------------------------===//
1851 let hasNewValue = 1, opNewValue = 0 in
1852 class T_M2_mpy_acc < bits<2> LHbits, bit isSat, bit isNac,
1853 bit hasShift, bit isUnsigned >
1854 : MInst_acc<(outs IntRegs:$Rx), (ins IntRegs:$dst2, IntRegs:$Rs, IntRegs:$Rt),
1855 "$Rx "#!if(isNac,"-= ","+= ")#!if(isUnsigned,"mpyu","mpy")
1856 #"($Rs."#!if(LHbits{1},"h","l")
1857 #", $Rt."#!if(LHbits{0},"h)","l)")
1858 #!if(hasShift,":<<1","")
1859 #!if(isSat,":sat",""),
1860 [], "$dst2 = $Rx", M_tc_3x_SLOT23 > {
1865 let IClass = 0b1110;
1866 let Inst{27-24} = 0b1110;
1867 let Inst{23} = hasShift;
1868 let Inst{22} = isUnsigned;
1869 let Inst{21} = isNac;
1870 let Inst{7} = isSat;
1871 let Inst{6-5} = LHbits;
1873 let Inst{20-16} = Rs;
1874 let Inst{12-8} = Rt;
1877 //Rx += mpy(Rs.[H|L],Rt.[H|L])[:<<1]
1878 let isCodeGenOnly = 0 in {
1879 def M2_mpy_acc_ll_s1: T_M2_mpy_acc <0b00, 0, 0, 1, 0>;
1880 def M2_mpy_acc_ll_s0: T_M2_mpy_acc <0b00, 0, 0, 0, 0>;
1881 def M2_mpy_acc_lh_s1: T_M2_mpy_acc <0b01, 0, 0, 1, 0>;
1882 def M2_mpy_acc_lh_s0: T_M2_mpy_acc <0b01, 0, 0, 0, 0>;
1883 def M2_mpy_acc_hl_s1: T_M2_mpy_acc <0b10, 0, 0, 1, 0>;
1884 def M2_mpy_acc_hl_s0: T_M2_mpy_acc <0b10, 0, 0, 0, 0>;
1885 def M2_mpy_acc_hh_s1: T_M2_mpy_acc <0b11, 0, 0, 1, 0>;
1886 def M2_mpy_acc_hh_s0: T_M2_mpy_acc <0b11, 0, 0, 0, 0>;
1889 //Rx += mpyu(Rs.[H|L],Rt.[H|L])[:<<1]
1890 let isCodeGenOnly = 0 in {
1891 def M2_mpyu_acc_ll_s1: T_M2_mpy_acc <0b00, 0, 0, 1, 1>;
1892 def M2_mpyu_acc_ll_s0: T_M2_mpy_acc <0b00, 0, 0, 0, 1>;
1893 def M2_mpyu_acc_lh_s1: T_M2_mpy_acc <0b01, 0, 0, 1, 1>;
1894 def M2_mpyu_acc_lh_s0: T_M2_mpy_acc <0b01, 0, 0, 0, 1>;
1895 def M2_mpyu_acc_hl_s1: T_M2_mpy_acc <0b10, 0, 0, 1, 1>;
1896 def M2_mpyu_acc_hl_s0: T_M2_mpy_acc <0b10, 0, 0, 0, 1>;
1897 def M2_mpyu_acc_hh_s1: T_M2_mpy_acc <0b11, 0, 0, 1, 1>;
1898 def M2_mpyu_acc_hh_s0: T_M2_mpy_acc <0b11, 0, 0, 0, 1>;
1901 //Rx -= mpy(Rs.[H|L],Rt.[H|L])[:<<1]
1902 let isCodeGenOnly = 0 in {
1903 def M2_mpy_nac_ll_s1: T_M2_mpy_acc <0b00, 0, 1, 1, 0>;
1904 def M2_mpy_nac_ll_s0: T_M2_mpy_acc <0b00, 0, 1, 0, 0>;
1905 def M2_mpy_nac_lh_s1: T_M2_mpy_acc <0b01, 0, 1, 1, 0>;
1906 def M2_mpy_nac_lh_s0: T_M2_mpy_acc <0b01, 0, 1, 0, 0>;
1907 def M2_mpy_nac_hl_s1: T_M2_mpy_acc <0b10, 0, 1, 1, 0>;
1908 def M2_mpy_nac_hl_s0: T_M2_mpy_acc <0b10, 0, 1, 0, 0>;
1909 def M2_mpy_nac_hh_s1: T_M2_mpy_acc <0b11, 0, 1, 1, 0>;
1910 def M2_mpy_nac_hh_s0: T_M2_mpy_acc <0b11, 0, 1, 0, 0>;
1913 //Rx -= mpyu(Rs.[H|L],Rt.[H|L])[:<<1]
1914 let isCodeGenOnly = 0 in {
1915 def M2_mpyu_nac_ll_s1: T_M2_mpy_acc <0b00, 0, 1, 1, 1>;
1916 def M2_mpyu_nac_ll_s0: T_M2_mpy_acc <0b00, 0, 1, 0, 1>;
1917 def M2_mpyu_nac_lh_s1: T_M2_mpy_acc <0b01, 0, 1, 1, 1>;
1918 def M2_mpyu_nac_lh_s0: T_M2_mpy_acc <0b01, 0, 1, 0, 1>;
1919 def M2_mpyu_nac_hl_s1: T_M2_mpy_acc <0b10, 0, 1, 1, 1>;
1920 def M2_mpyu_nac_hl_s0: T_M2_mpy_acc <0b10, 0, 1, 0, 1>;
1921 def M2_mpyu_nac_hh_s1: T_M2_mpy_acc <0b11, 0, 1, 1, 1>;
1922 def M2_mpyu_nac_hh_s0: T_M2_mpy_acc <0b11, 0, 1, 0, 1>;
1925 //Rx += mpy(Rs.[H|L],Rt.[H|L])[:<<1]:sat
1926 let isCodeGenOnly = 0 in {
1927 def M2_mpy_acc_sat_ll_s1: T_M2_mpy_acc <0b00, 1, 0, 1, 0>;
1928 def M2_mpy_acc_sat_ll_s0: T_M2_mpy_acc <0b00, 1, 0, 0, 0>;
1929 def M2_mpy_acc_sat_lh_s1: T_M2_mpy_acc <0b01, 1, 0, 1, 0>;
1930 def M2_mpy_acc_sat_lh_s0: T_M2_mpy_acc <0b01, 1, 0, 0, 0>;
1931 def M2_mpy_acc_sat_hl_s1: T_M2_mpy_acc <0b10, 1, 0, 1, 0>;
1932 def M2_mpy_acc_sat_hl_s0: T_M2_mpy_acc <0b10, 1, 0, 0, 0>;
1933 def M2_mpy_acc_sat_hh_s1: T_M2_mpy_acc <0b11, 1, 0, 1, 0>;
1934 def M2_mpy_acc_sat_hh_s0: T_M2_mpy_acc <0b11, 1, 0, 0, 0>;
1937 //Rx -= mpy(Rs.[H|L],Rt.[H|L])[:<<1]:sat
1938 let isCodeGenOnly = 0 in {
1939 def M2_mpy_nac_sat_ll_s1: T_M2_mpy_acc <0b00, 1, 1, 1, 0>;
1940 def M2_mpy_nac_sat_ll_s0: T_M2_mpy_acc <0b00, 1, 1, 0, 0>;
1941 def M2_mpy_nac_sat_lh_s1: T_M2_mpy_acc <0b01, 1, 1, 1, 0>;
1942 def M2_mpy_nac_sat_lh_s0: T_M2_mpy_acc <0b01, 1, 1, 0, 0>;
1943 def M2_mpy_nac_sat_hl_s1: T_M2_mpy_acc <0b10, 1, 1, 1, 0>;
1944 def M2_mpy_nac_sat_hl_s0: T_M2_mpy_acc <0b10, 1, 1, 0, 0>;
1945 def M2_mpy_nac_sat_hh_s1: T_M2_mpy_acc <0b11, 1, 1, 1, 0>;
1946 def M2_mpy_nac_sat_hh_s0: T_M2_mpy_acc <0b11, 1, 1, 0, 0>;
1949 //===----------------------------------------------------------------------===//
1951 // MPYS / Multipy signed/unsigned halfwords and add/subtract the
1952 // result from the 64-bit destination register.
1953 //Rxx [-+]= mpy[u](Rs.[H|L],Rt.[H|L])[:<<1][:sat]
1954 //===----------------------------------------------------------------------===//
1956 class T_M2_mpyd_acc < bits<2> LHbits, bit isNac, bit hasShift, bit isUnsigned>
1957 : MInst_acc<(outs DoubleRegs:$Rxx),
1958 (ins DoubleRegs:$dst2, IntRegs:$Rs, IntRegs:$Rt),
1959 "$Rxx "#!if(isNac,"-= ","+= ")#!if(isUnsigned,"mpyu","mpy")
1960 #"($Rs."#!if(LHbits{1},"h","l")
1961 #", $Rt."#!if(LHbits{0},"h)","l)")
1962 #!if(hasShift,":<<1",""),
1963 [], "$dst2 = $Rxx", M_tc_3x_SLOT23 > {
1968 let IClass = 0b1110;
1970 let Inst{27-24} = 0b0110;
1971 let Inst{23} = hasShift;
1972 let Inst{22} = isUnsigned;
1973 let Inst{21} = isNac;
1975 let Inst{6-5} = LHbits;
1976 let Inst{4-0} = Rxx;
1977 let Inst{20-16} = Rs;
1978 let Inst{12-8} = Rt;
1981 let isCodeGenOnly = 0 in {
1982 def M2_mpyd_acc_hh_s0: T_M2_mpyd_acc <0b11, 0, 0, 0>;
1983 def M2_mpyd_acc_hl_s0: T_M2_mpyd_acc <0b10, 0, 0, 0>;
1984 def M2_mpyd_acc_lh_s0: T_M2_mpyd_acc <0b01, 0, 0, 0>;
1985 def M2_mpyd_acc_ll_s0: T_M2_mpyd_acc <0b00, 0, 0, 0>;
1987 def M2_mpyd_acc_hh_s1: T_M2_mpyd_acc <0b11, 0, 1, 0>;
1988 def M2_mpyd_acc_hl_s1: T_M2_mpyd_acc <0b10, 0, 1, 0>;
1989 def M2_mpyd_acc_lh_s1: T_M2_mpyd_acc <0b01, 0, 1, 0>;
1990 def M2_mpyd_acc_ll_s1: T_M2_mpyd_acc <0b00, 0, 1, 0>;
1992 def M2_mpyd_nac_hh_s0: T_M2_mpyd_acc <0b11, 1, 0, 0>;
1993 def M2_mpyd_nac_hl_s0: T_M2_mpyd_acc <0b10, 1, 0, 0>;
1994 def M2_mpyd_nac_lh_s0: T_M2_mpyd_acc <0b01, 1, 0, 0>;
1995 def M2_mpyd_nac_ll_s0: T_M2_mpyd_acc <0b00, 1, 0, 0>;
1997 def M2_mpyd_nac_hh_s1: T_M2_mpyd_acc <0b11, 1, 1, 0>;
1998 def M2_mpyd_nac_hl_s1: T_M2_mpyd_acc <0b10, 1, 1, 0>;
1999 def M2_mpyd_nac_lh_s1: T_M2_mpyd_acc <0b01, 1, 1, 0>;
2000 def M2_mpyd_nac_ll_s1: T_M2_mpyd_acc <0b00, 1, 1, 0>;
2002 def M2_mpyud_acc_hh_s0: T_M2_mpyd_acc <0b11, 0, 0, 1>;
2003 def M2_mpyud_acc_hl_s0: T_M2_mpyd_acc <0b10, 0, 0, 1>;
2004 def M2_mpyud_acc_lh_s0: T_M2_mpyd_acc <0b01, 0, 0, 1>;
2005 def M2_mpyud_acc_ll_s0: T_M2_mpyd_acc <0b00, 0, 0, 1>;
2007 def M2_mpyud_acc_hh_s1: T_M2_mpyd_acc <0b11, 0, 1, 1>;
2008 def M2_mpyud_acc_hl_s1: T_M2_mpyd_acc <0b10, 0, 1, 1>;
2009 def M2_mpyud_acc_lh_s1: T_M2_mpyd_acc <0b01, 0, 1, 1>;
2010 def M2_mpyud_acc_ll_s1: T_M2_mpyd_acc <0b00, 0, 1, 1>;
2012 def M2_mpyud_nac_hh_s0: T_M2_mpyd_acc <0b11, 1, 0, 1>;
2013 def M2_mpyud_nac_hl_s0: T_M2_mpyd_acc <0b10, 1, 0, 1>;
2014 def M2_mpyud_nac_lh_s0: T_M2_mpyd_acc <0b01, 1, 0, 1>;
2015 def M2_mpyud_nac_ll_s0: T_M2_mpyd_acc <0b00, 1, 0, 1>;
2017 def M2_mpyud_nac_hh_s1: T_M2_mpyd_acc <0b11, 1, 1, 1>;
2018 def M2_mpyud_nac_hl_s1: T_M2_mpyd_acc <0b10, 1, 1, 1>;
2019 def M2_mpyud_nac_lh_s1: T_M2_mpyd_acc <0b01, 1, 1, 1>;
2020 def M2_mpyud_nac_ll_s1: T_M2_mpyd_acc <0b00, 1, 1, 1>;
2023 let hasNewValue = 1, opNewValue = 0 in
2024 class T_MType_mpy <string mnemonic, bits<4> RegTyBits, RegisterClass RC,
2025 bits<3> MajOp, bits<3> MinOp, bit isSat = 0, bit isRnd = 0,
2026 string op2Suffix = "", bit isRaw = 0, bit isHi = 0 >
2027 : MInst <(outs IntRegs:$dst), (ins RC:$src1, RC:$src2),
2029 #"($src1, $src2"#op2Suffix#")"
2030 #!if(MajOp{2}, ":<<1", "")
2031 #!if(isRnd, ":rnd", "")
2032 #!if(isSat, ":sat", "")
2033 #!if(isRaw, !if(isHi, ":raw:hi", ":raw:lo"), ""), [] > {
2038 let IClass = 0b1110;
2040 let Inst{27-24} = RegTyBits;
2041 let Inst{23-21} = MajOp;
2042 let Inst{20-16} = src1;
2044 let Inst{12-8} = src2;
2045 let Inst{7-5} = MinOp;
2046 let Inst{4-0} = dst;
2049 class T_MType_dd <string mnemonic, bits<3> MajOp, bits<3> MinOp,
2050 bit isSat = 0, bit isRnd = 0 >
2051 : T_MType_mpy <mnemonic, 0b1001, DoubleRegs, MajOp, MinOp, isSat, isRnd>;
2053 class T_MType_rr1 <string mnemonic, bits<3> MajOp, bits<3> MinOp,
2054 bit isSat = 0, bit isRnd = 0 >
2055 : T_MType_mpy<mnemonic, 0b1101, IntRegs, MajOp, MinOp, isSat, isRnd>;
2057 class T_MType_rr2 <string mnemonic, bits<3> MajOp, bits<3> MinOp,
2058 bit isSat = 0, bit isRnd = 0, string op2str = "" >
2059 : T_MType_mpy<mnemonic, 0b1101, IntRegs, MajOp, MinOp, isSat, isRnd, op2str>;
2061 let CextOpcode = "mpyi", InputType = "reg", isCodeGenOnly = 0 in
2062 def M2_mpyi : T_MType_rr1 <"mpyi", 0b000, 0b000>, ImmRegRel;
2064 let isCodeGenOnly = 0 in {
2065 def M2_mpy_up : T_MType_rr1 <"mpy", 0b000, 0b001>;
2066 def M2_mpyu_up : T_MType_rr1 <"mpyu", 0b010, 0b001>;
2069 let isCodeGenOnly = 0 in
2070 def M2_dpmpyss_rnd_s0 : T_MType_rr1 <"mpy", 0b001, 0b001, 0, 1>;
2072 let isCodeGenOnly = 0 in {
2073 def M2_hmmpyh_rs1 : T_MType_rr2 <"mpy", 0b101, 0b100, 1, 1, ".h">;
2074 def M2_hmmpyl_rs1 : T_MType_rr2 <"mpy", 0b111, 0b100, 1, 1, ".l">;
2078 let isCodeGenOnly = 0 in {
2079 def M2_mpysu_up : T_MType_rr1 <"mpysu", 0b011, 0b001, 0>;
2080 def M2_mpy_up_s1_sat : T_MType_rr1 <"mpy", 0b111, 0b000, 1>;
2082 def M2_hmmpyh_s1 : T_MType_rr2 <"mpy", 0b101, 0b000, 1, 0, ".h">;
2083 def M2_hmmpyl_s1 : T_MType_rr2 <"mpy", 0b101, 0b001, 1, 0, ".l">;
2086 def: Pat<(i32 (mul I32:$src1, I32:$src2)), (M2_mpyi I32:$src1, I32:$src2)>;
2087 def: Pat<(i32 (mulhs I32:$src1, I32:$src2)), (M2_mpy_up I32:$src1, I32:$src2)>;
2088 def: Pat<(i32 (mulhu I32:$src1, I32:$src2)), (M2_mpyu_up I32:$src1, I32:$src2)>;
2090 let hasNewValue = 1, opNewValue = 0 in
2091 class T_MType_mpy_ri <bit isNeg, Operand ImmOp, list<dag> pattern>
2092 : MInst < (outs IntRegs:$Rd), (ins IntRegs:$Rs, ImmOp:$u8),
2093 "$Rd ="#!if(isNeg, "- ", "+ ")#"mpyi($Rs, #$u8)" ,
2094 pattern, "", M_tc_3x_SLOT23> {
2099 let IClass = 0b1110;
2101 let Inst{27-24} = 0b0000;
2102 let Inst{23} = isNeg;
2105 let Inst{20-16} = Rs;
2106 let Inst{12-5} = u8;
2109 let isExtendable = 1, opExtentBits = 8, opExtendable = 2, isCodeGenOnly = 0 in
2110 def M2_mpysip : T_MType_mpy_ri <0, u8Ext,
2111 [(set (i32 IntRegs:$Rd), (mul IntRegs:$Rs, u8ExtPred:$u8))]>;
2113 let isCodeGenOnly = 0 in
2114 def M2_mpysin : T_MType_mpy_ri <1, u8Imm,
2115 [(set (i32 IntRegs:$Rd), (ineg (mul IntRegs:$Rs,
2118 // Assember mapped to M2_mpyi
2119 let isAsmParserOnly = 1 in
2120 def M2_mpyui : MInst<(outs IntRegs:$dst),
2121 (ins IntRegs:$src1, IntRegs:$src2),
2122 "$dst = mpyui($src1, $src2)">;
2125 // s9 is NOT the same as m9 - but it works.. so far.
2126 // Assembler maps to either Rd=+mpyi(Rs,#u8) or Rd=-mpyi(Rs,#u8)
2127 // depending on the value of m9. See Arch Spec.
2128 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 9,
2129 CextOpcode = "mpyi", InputType = "imm", hasNewValue = 1 in
2130 def M2_mpysmi : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, s9Ext:$src2),
2131 "$dst = mpyi($src1, #$src2)",
2132 [(set (i32 IntRegs:$dst), (mul (i32 IntRegs:$src1),
2133 s9ExtPred:$src2))]>, ImmRegRel;
2135 let hasNewValue = 1, isExtendable = 1, opExtentBits = 8, opExtendable = 3,
2136 InputType = "imm" in
2137 class T_MType_acc_ri <string mnemonic, bits<3> MajOp, Operand ImmOp,
2138 list<dag> pattern = []>
2139 : MInst < (outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2, ImmOp:$src3),
2140 "$dst "#mnemonic#"($src2, #$src3)",
2141 pattern, "$src1 = $dst", M_tc_2_SLOT23> {
2146 let IClass = 0b1110;
2148 let Inst{27-26} = 0b00;
2149 let Inst{25-23} = MajOp;
2150 let Inst{20-16} = src2;
2152 let Inst{12-5} = src3;
2153 let Inst{4-0} = dst;
2156 let InputType = "reg", hasNewValue = 1 in
2157 class T_MType_acc_rr <string mnemonic, bits<3> MajOp, bits<3> MinOp,
2158 bit isSwap = 0, list<dag> pattern = [], bit hasNot = 0,
2159 bit isSat = 0, bit isShift = 0>
2160 : MInst < (outs IntRegs:$dst),
2161 (ins IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
2162 "$dst "#mnemonic#"($src2, "#!if(hasNot, "~$src3)","$src3)")
2163 #!if(isShift, ":<<1", "")
2164 #!if(isSat, ":sat", ""),
2165 pattern, "$src1 = $dst", M_tc_2_SLOT23 > {
2170 let IClass = 0b1110;
2172 let Inst{27-24} = 0b1111;
2173 let Inst{23-21} = MajOp;
2174 let Inst{20-16} = !if(isSwap, src3, src2);
2176 let Inst{12-8} = !if(isSwap, src2, src3);
2177 let Inst{7-5} = MinOp;
2178 let Inst{4-0} = dst;
2181 let CextOpcode = "MPYI_acc", Itinerary = M_tc_3x_SLOT23, isCodeGenOnly = 0 in {
2182 def M2_macsip : T_MType_acc_ri <"+= mpyi", 0b010, u8Ext,
2183 [(set (i32 IntRegs:$dst),
2184 (add (mul IntRegs:$src2, u8ExtPred:$src3),
2185 IntRegs:$src1))]>, ImmRegRel;
2187 def M2_maci : T_MType_acc_rr <"+= mpyi", 0b000, 0b000, 0,
2188 [(set (i32 IntRegs:$dst),
2189 (add (mul IntRegs:$src2, IntRegs:$src3),
2190 IntRegs:$src1))]>, ImmRegRel;
2193 let CextOpcode = "ADD_acc", isCodeGenOnly = 0 in {
2194 let isExtentSigned = 1 in
2195 def M2_accii : T_MType_acc_ri <"+= add", 0b100, s8Ext,
2196 [(set (i32 IntRegs:$dst),
2197 (add (add (i32 IntRegs:$src2), s8_16ExtPred:$src3),
2198 (i32 IntRegs:$src1)))]>, ImmRegRel;
2200 def M2_acci : T_MType_acc_rr <"+= add", 0b000, 0b001, 0,
2201 [(set (i32 IntRegs:$dst),
2202 (add (add (i32 IntRegs:$src2), (i32 IntRegs:$src3)),
2203 (i32 IntRegs:$src1)))]>, ImmRegRel;
2206 let CextOpcode = "SUB_acc", isCodeGenOnly = 0 in {
2207 let isExtentSigned = 1 in
2208 def M2_naccii : T_MType_acc_ri <"-= add", 0b101, s8Ext>, ImmRegRel;
2210 def M2_nacci : T_MType_acc_rr <"-= add", 0b100, 0b001, 0>, ImmRegRel;
2213 let Itinerary = M_tc_3x_SLOT23, isCodeGenOnly = 0 in
2214 def M2_macsin : T_MType_acc_ri <"-= mpyi", 0b011, u8Ext>;
2216 let isCodeGenOnly = 0 in {
2217 def M2_xor_xacc : T_MType_acc_rr < "^= xor", 0b100, 0b011, 0>;
2218 def M2_subacc : T_MType_acc_rr <"+= sub", 0b000, 0b011, 1>;
2221 class T_MType_acc_pat1 <InstHexagon MI, SDNode firstOp, SDNode secOp,
2223 : Pat <(secOp IntRegs:$src1, (firstOp IntRegs:$src2, ImmPred:$src3)),
2224 (MI IntRegs:$src1, IntRegs:$src2, ImmPred:$src3)>;
2226 class T_MType_acc_pat2 <InstHexagon MI, SDNode firstOp, SDNode secOp>
2227 : Pat <(i32 (secOp IntRegs:$src1, (firstOp IntRegs:$src2, IntRegs:$src3))),
2228 (MI IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
2230 def : T_MType_acc_pat2 <M2_xor_xacc, xor, xor>;
2231 def : T_MType_acc_pat1 <M2_macsin, mul, sub, u8ExtPred>;
2233 def : T_MType_acc_pat1 <M2_naccii, add, sub, s8_16ExtPred>;
2234 def : T_MType_acc_pat2 <M2_nacci, add, sub>;
2235 //===----------------------------------------------------------------------===//
2236 // Template Class -- Multiply signed/unsigned halfwords with and without
2237 // saturation and rounding
2238 //===----------------------------------------------------------------------===//
2239 class T_M2_mpyd < bits<2> LHbits, bit isRnd, bit hasShift, bit isUnsigned >
2240 : MInst < (outs DoubleRegs:$Rdd), (ins IntRegs:$Rs, IntRegs:$Rt),
2241 "$Rdd = "#!if(isUnsigned,"mpyu","mpy")#"($Rs."#!if(LHbits{1},"h","l")
2242 #", $Rt."#!if(LHbits{0},"h)","l)")
2243 #!if(hasShift,":<<1","")
2244 #!if(isRnd,":rnd",""),
2250 let IClass = 0b1110;
2252 let Inst{27-24} = 0b0100;
2253 let Inst{23} = hasShift;
2254 let Inst{22} = isUnsigned;
2255 let Inst{21} = isRnd;
2256 let Inst{6-5} = LHbits;
2257 let Inst{4-0} = Rdd;
2258 let Inst{20-16} = Rs;
2259 let Inst{12-8} = Rt;
2262 let isCodeGenOnly = 0 in {
2263 def M2_mpyd_hh_s0: T_M2_mpyd<0b11, 0, 0, 0>;
2264 def M2_mpyd_hl_s0: T_M2_mpyd<0b10, 0, 0, 0>;
2265 def M2_mpyd_lh_s0: T_M2_mpyd<0b01, 0, 0, 0>;
2266 def M2_mpyd_ll_s0: T_M2_mpyd<0b00, 0, 0, 0>;
2268 def M2_mpyd_hh_s1: T_M2_mpyd<0b11, 0, 1, 0>;
2269 def M2_mpyd_hl_s1: T_M2_mpyd<0b10, 0, 1, 0>;
2270 def M2_mpyd_lh_s1: T_M2_mpyd<0b01, 0, 1, 0>;
2271 def M2_mpyd_ll_s1: T_M2_mpyd<0b00, 0, 1, 0>;
2273 def M2_mpyd_rnd_hh_s0: T_M2_mpyd<0b11, 1, 0, 0>;
2274 def M2_mpyd_rnd_hl_s0: T_M2_mpyd<0b10, 1, 0, 0>;
2275 def M2_mpyd_rnd_lh_s0: T_M2_mpyd<0b01, 1, 0, 0>;
2276 def M2_mpyd_rnd_ll_s0: T_M2_mpyd<0b00, 1, 0, 0>;
2278 def M2_mpyd_rnd_hh_s1: T_M2_mpyd<0b11, 1, 1, 0>;
2279 def M2_mpyd_rnd_hl_s1: T_M2_mpyd<0b10, 1, 1, 0>;
2280 def M2_mpyd_rnd_lh_s1: T_M2_mpyd<0b01, 1, 1, 0>;
2281 def M2_mpyd_rnd_ll_s1: T_M2_mpyd<0b00, 1, 1, 0>;
2283 //Rdd=mpyu(Rs.[HL],Rt.[HL])[:<<1]
2284 def M2_mpyud_hh_s0: T_M2_mpyd<0b11, 0, 0, 1>;
2285 def M2_mpyud_hl_s0: T_M2_mpyd<0b10, 0, 0, 1>;
2286 def M2_mpyud_lh_s0: T_M2_mpyd<0b01, 0, 0, 1>;
2287 def M2_mpyud_ll_s0: T_M2_mpyd<0b00, 0, 0, 1>;
2289 def M2_mpyud_hh_s1: T_M2_mpyd<0b11, 0, 1, 1>;
2290 def M2_mpyud_hl_s1: T_M2_mpyd<0b10, 0, 1, 1>;
2291 def M2_mpyud_lh_s1: T_M2_mpyd<0b01, 0, 1, 1>;
2292 def M2_mpyud_ll_s1: T_M2_mpyd<0b00, 0, 1, 1>;
2294 //===----------------------------------------------------------------------===//
2295 // Template Class for xtype mpy:
2298 // multiply 32X32 and use full result
2299 //===----------------------------------------------------------------------===//
2300 let hasSideEffects = 0 in
2301 class T_XTYPE_mpy64 <string mnemonic, bits<3> MajOp, bits<3> MinOp,
2302 bit isSat, bit hasShift, bit isConj>
2303 : MInst <(outs DoubleRegs:$Rdd),
2304 (ins IntRegs:$Rs, IntRegs:$Rt),
2305 "$Rdd = "#mnemonic#"($Rs, $Rt"#!if(isConj,"*)",")")
2306 #!if(hasShift,":<<1","")
2307 #!if(isSat,":sat",""),
2313 let IClass = 0b1110;
2315 let Inst{27-24} = 0b0101;
2316 let Inst{23-21} = MajOp;
2317 let Inst{20-16} = Rs;
2318 let Inst{12-8} = Rt;
2319 let Inst{7-5} = MinOp;
2320 let Inst{4-0} = Rdd;
2323 //===----------------------------------------------------------------------===//
2324 // Template Class for xtype mpy with accumulation into 64-bit:
2327 // multiply 32X32 and use full result
2328 //===----------------------------------------------------------------------===//
2329 class T_XTYPE_mpy64_acc <string op1, string op2, bits<3> MajOp, bits<3> MinOp,
2330 bit isSat, bit hasShift, bit isConj>
2331 : MInst <(outs DoubleRegs:$Rxx),
2332 (ins DoubleRegs:$dst2, IntRegs:$Rs, IntRegs:$Rt),
2333 "$Rxx "#op2#"= "#op1#"($Rs, $Rt"#!if(isConj,"*)",")")
2334 #!if(hasShift,":<<1","")
2335 #!if(isSat,":sat",""),
2337 [] , "$dst2 = $Rxx" > {
2342 let IClass = 0b1110;
2344 let Inst{27-24} = 0b0111;
2345 let Inst{23-21} = MajOp;
2346 let Inst{20-16} = Rs;
2347 let Inst{12-8} = Rt;
2348 let Inst{7-5} = MinOp;
2349 let Inst{4-0} = Rxx;
2352 // MPY - Multiply and use full result
2353 // Rdd = mpy[u](Rs,Rt)
2354 let isCodeGenOnly = 0 in {
2355 def M2_dpmpyss_s0 : T_XTYPE_mpy64 < "mpy", 0b000, 0b000, 0, 0, 0>;
2356 def M2_dpmpyuu_s0 : T_XTYPE_mpy64 < "mpyu", 0b010, 0b000, 0, 0, 0>;
2358 // Rxx[+-]= mpy[u](Rs,Rt)
2359 def M2_dpmpyss_acc_s0 : T_XTYPE_mpy64_acc < "mpy", "+", 0b000, 0b000, 0, 0, 0>;
2360 def M2_dpmpyss_nac_s0 : T_XTYPE_mpy64_acc < "mpy", "-", 0b001, 0b000, 0, 0, 0>;
2361 def M2_dpmpyuu_acc_s0 : T_XTYPE_mpy64_acc < "mpyu", "+", 0b010, 0b000, 0, 0, 0>;
2362 def M2_dpmpyuu_nac_s0 : T_XTYPE_mpy64_acc < "mpyu", "-", 0b011, 0b000, 0, 0, 0>;
2365 def: Pat<(i64 (mul (i64 (anyext (i32 IntRegs:$src1))),
2366 (i64 (anyext (i32 IntRegs:$src2))))),
2367 (M2_dpmpyuu_s0 IntRegs:$src1, IntRegs:$src2)>;
2369 def: Pat<(i64 (mul (i64 (sext (i32 IntRegs:$src1))),
2370 (i64 (sext (i32 IntRegs:$src2))))),
2371 (M2_dpmpyss_s0 IntRegs:$src1, IntRegs:$src2)>;
2373 def: Pat<(i64 (mul (is_sext_i32:$src1),
2374 (is_sext_i32:$src2))),
2375 (M2_dpmpyss_s0 (LoReg DoubleRegs:$src1), (LoReg DoubleRegs:$src2))>;
2377 // Multiply and accumulate, use full result.
2378 // Rxx[+-]=mpy(Rs,Rt)
2380 def: Pat<(i64 (add (i64 DoubleRegs:$src1),
2381 (mul (i64 (sext (i32 IntRegs:$src2))),
2382 (i64 (sext (i32 IntRegs:$src3)))))),
2383 (M2_dpmpyss_acc_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
2385 def: Pat<(i64 (sub (i64 DoubleRegs:$src1),
2386 (mul (i64 (sext (i32 IntRegs:$src2))),
2387 (i64 (sext (i32 IntRegs:$src3)))))),
2388 (M2_dpmpyss_nac_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
2390 def: Pat<(i64 (add (i64 DoubleRegs:$src1),
2391 (mul (i64 (anyext (i32 IntRegs:$src2))),
2392 (i64 (anyext (i32 IntRegs:$src3)))))),
2393 (M2_dpmpyuu_acc_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
2395 def: Pat<(i64 (add (i64 DoubleRegs:$src1),
2396 (mul (i64 (zext (i32 IntRegs:$src2))),
2397 (i64 (zext (i32 IntRegs:$src3)))))),
2398 (M2_dpmpyuu_acc_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
2400 def: Pat<(i64 (sub (i64 DoubleRegs:$src1),
2401 (mul (i64 (anyext (i32 IntRegs:$src2))),
2402 (i64 (anyext (i32 IntRegs:$src3)))))),
2403 (M2_dpmpyuu_nac_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
2405 def: Pat<(i64 (sub (i64 DoubleRegs:$src1),
2406 (mul (i64 (zext (i32 IntRegs:$src2))),
2407 (i64 (zext (i32 IntRegs:$src3)))))),
2408 (M2_dpmpyuu_nac_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
2410 //===----------------------------------------------------------------------===//
2412 //===----------------------------------------------------------------------===//
2414 //===----------------------------------------------------------------------===//
2416 //===----------------------------------------------------------------------===//
2417 //===----------------------------------------------------------------------===//
2419 //===----------------------------------------------------------------------===//
2421 //===----------------------------------------------------------------------===//
2423 //===----------------------------------------------------------------------===//
2424 //===----------------------------------------------------------------------===//
2426 //===----------------------------------------------------------------------===//
2428 //===----------------------------------------------------------------------===//
2430 //===----------------------------------------------------------------------===//
2431 //===----------------------------------------------------------------------===//
2433 //===----------------------------------------------------------------------===//
2435 //===----------------------------------------------------------------------===//
2437 //===----------------------------------------------------------------------===//
2439 // Store doubleword.
2441 //===----------------------------------------------------------------------===//
2442 // Post increment store
2443 //===----------------------------------------------------------------------===//
2445 multiclass ST_PostInc_Pbase<string mnemonic, RegisterClass RC, Operand ImmOp,
2446 bit isNot, bit isPredNew> {
2447 let isPredicatedNew = isPredNew in
2448 def NAME : STInst2PI<(outs IntRegs:$dst),
2449 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset, RC:$src3),
2450 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
2451 ") ")#mnemonic#"($src2++#$offset) = $src3",
2456 multiclass ST_PostInc_Pred<string mnemonic, RegisterClass RC,
2457 Operand ImmOp, bit PredNot> {
2458 let isPredicatedFalse = PredNot in {
2459 defm _c#NAME : ST_PostInc_Pbase<mnemonic, RC, ImmOp, PredNot, 0>;
2461 let Predicates = [HasV4T], validSubTargets = HasV4SubT in
2462 defm _cdn#NAME#_V4 : ST_PostInc_Pbase<mnemonic, RC, ImmOp, PredNot, 1>;
2466 let hasCtrlDep = 1, isNVStorable = 1, hasSideEffects = 0 in
2467 multiclass ST_PostInc<string mnemonic, string BaseOp, RegisterClass RC,
2470 let hasCtrlDep = 1, BaseOpcode = "POST_"#BaseOp in {
2471 let isPredicable = 1 in
2472 def NAME : STInst2PI<(outs IntRegs:$dst),
2473 (ins IntRegs:$src1, ImmOp:$offset, RC:$src2),
2474 mnemonic#"($src1++#$offset) = $src2",
2478 let isPredicated = 1 in {
2479 defm Pt : ST_PostInc_Pred<mnemonic, RC, ImmOp, 0 >;
2480 defm NotPt : ST_PostInc_Pred<mnemonic, RC, ImmOp, 1 >;
2485 defm POST_STbri: ST_PostInc <"memb", "STrib", IntRegs, s4_0Imm>, AddrModeRel;
2486 defm POST_SThri: ST_PostInc <"memh", "STrih", IntRegs, s4_1Imm>, AddrModeRel;
2487 defm POST_STwri: ST_PostInc <"memw", "STriw", IntRegs, s4_2Imm>, AddrModeRel;
2489 let isNVStorable = 0 in
2490 defm POST_STdri: ST_PostInc <"memd", "STrid", DoubleRegs, s4_3Imm>, AddrModeRel;
2492 def : Pat<(post_truncsti8 (i32 IntRegs:$src1), IntRegs:$src2,
2493 s4_3ImmPred:$offset),
2494 (POST_STbri IntRegs:$src2, s4_0ImmPred:$offset, IntRegs:$src1)>;
2496 def : Pat<(post_truncsti16 (i32 IntRegs:$src1), IntRegs:$src2,
2497 s4_3ImmPred:$offset),
2498 (POST_SThri IntRegs:$src2, s4_1ImmPred:$offset, IntRegs:$src1)>;
2500 def : Pat<(post_store (i32 IntRegs:$src1), IntRegs:$src2, s4_2ImmPred:$offset),
2501 (POST_STwri IntRegs:$src2, s4_1ImmPred:$offset, IntRegs:$src1)>;
2503 def : Pat<(post_store (i64 DoubleRegs:$src1), IntRegs:$src2,
2504 s4_3ImmPred:$offset),
2505 (POST_STdri IntRegs:$src2, s4_3ImmPred:$offset, DoubleRegs:$src1)>;
2507 //===----------------------------------------------------------------------===//
2508 // multiclass for the store instructions with MEMri operand.
2509 //===----------------------------------------------------------------------===//
2510 multiclass ST_MEMri_Pbase<string mnemonic, RegisterClass RC, bit isNot,
2512 let isPredicatedNew = isPredNew in
2513 def NAME : STInst2<(outs),
2514 (ins PredRegs:$src1, MEMri:$addr, RC: $src2),
2515 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
2516 ") ")#mnemonic#"($addr) = $src2",
2520 multiclass ST_MEMri_Pred<string mnemonic, RegisterClass RC, bit PredNot> {
2521 let isPredicatedFalse = PredNot in {
2522 defm _c#NAME : ST_MEMri_Pbase<mnemonic, RC, PredNot, 0>;
2525 let validSubTargets = HasV4SubT, Predicates = [HasV4T] in
2526 defm _cdn#NAME#_V4 : ST_MEMri_Pbase<mnemonic, RC, PredNot, 1>;
2530 let isExtendable = 1, isNVStorable = 1, hasSideEffects = 0 in
2531 multiclass ST_MEMri<string mnemonic, string CextOp, RegisterClass RC,
2532 bits<5> ImmBits, bits<5> PredImmBits> {
2534 let CextOpcode = CextOp, BaseOpcode = CextOp in {
2535 let opExtendable = 1, isExtentSigned = 1, opExtentBits = ImmBits,
2537 def NAME : STInst2<(outs),
2538 (ins MEMri:$addr, RC:$src),
2539 mnemonic#"($addr) = $src",
2542 let opExtendable = 2, isExtentSigned = 0, opExtentBits = PredImmBits,
2543 isPredicated = 1 in {
2544 defm Pt : ST_MEMri_Pred<mnemonic, RC, 0>;
2545 defm NotPt : ST_MEMri_Pred<mnemonic, RC, 1>;
2550 let addrMode = BaseImmOffset, isMEMri = "true" in {
2551 let accessSize = ByteAccess in
2552 defm STrib: ST_MEMri < "memb", "STrib", IntRegs, 11, 6>, AddrModeRel;
2554 let accessSize = HalfWordAccess in
2555 defm STrih: ST_MEMri < "memh", "STrih", IntRegs, 12, 7>, AddrModeRel;
2557 let accessSize = WordAccess in
2558 defm STriw: ST_MEMri < "memw", "STriw", IntRegs, 13, 8>, AddrModeRel;
2560 let accessSize = DoubleWordAccess, isNVStorable = 0 in
2561 defm STrid: ST_MEMri < "memd", "STrid", DoubleRegs, 14, 9>, AddrModeRel;
2564 def : Pat<(truncstorei8 (i32 IntRegs:$src1), ADDRriS11_0:$addr),
2565 (STrib ADDRriS11_0:$addr, (i32 IntRegs:$src1))>;
2567 def : Pat<(truncstorei16 (i32 IntRegs:$src1), ADDRriS11_1:$addr),
2568 (STrih ADDRriS11_1:$addr, (i32 IntRegs:$src1))>;
2570 def : Pat<(store (i32 IntRegs:$src1), ADDRriS11_2:$addr),
2571 (STriw ADDRriS11_2:$addr, (i32 IntRegs:$src1))>;
2573 def : Pat<(store (i64 DoubleRegs:$src1), ADDRriS11_3:$addr),
2574 (STrid ADDRriS11_3:$addr, (i64 DoubleRegs:$src1))>;
2577 //===----------------------------------------------------------------------===//
2578 // multiclass for the store instructions with base+immediate offset
2580 //===----------------------------------------------------------------------===//
2581 multiclass ST_Idxd_Pbase<string mnemonic, RegisterClass RC, Operand predImmOp,
2582 bit isNot, bit isPredNew> {
2583 let isPredicatedNew = isPredNew in
2584 def NAME : STInst2<(outs),
2585 (ins PredRegs:$src1, IntRegs:$src2, predImmOp:$src3, RC: $src4),
2586 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
2587 ") ")#mnemonic#"($src2+#$src3) = $src4",
2591 multiclass ST_Idxd_Pred<string mnemonic, RegisterClass RC, Operand predImmOp,
2593 let isPredicatedFalse = PredNot, isPredicated = 1 in {
2594 defm _c#NAME : ST_Idxd_Pbase<mnemonic, RC, predImmOp, PredNot, 0>;
2597 let validSubTargets = HasV4SubT, Predicates = [HasV4T] in
2598 defm _cdn#NAME#_V4 : ST_Idxd_Pbase<mnemonic, RC, predImmOp, PredNot, 1>;
2602 let isExtendable = 1, isNVStorable = 1, hasSideEffects = 0 in
2603 multiclass ST_Idxd<string mnemonic, string CextOp, RegisterClass RC,
2604 Operand ImmOp, Operand predImmOp, bits<5> ImmBits,
2605 bits<5> PredImmBits> {
2607 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed in {
2608 let opExtendable = 1, isExtentSigned = 1, opExtentBits = ImmBits,
2610 def NAME : STInst2<(outs),
2611 (ins IntRegs:$src1, ImmOp:$src2, RC:$src3),
2612 mnemonic#"($src1+#$src2) = $src3",
2615 let opExtendable = 2, isExtentSigned = 0, opExtentBits = PredImmBits in {
2616 defm Pt : ST_Idxd_Pred<mnemonic, RC, predImmOp, 0>;
2617 defm NotPt : ST_Idxd_Pred<mnemonic, RC, predImmOp, 1>;
2622 let addrMode = BaseImmOffset, InputType = "reg" in {
2623 let accessSize = ByteAccess in
2624 defm STrib_indexed: ST_Idxd < "memb", "STrib", IntRegs, s11_0Ext,
2625 u6_0Ext, 11, 6>, AddrModeRel, ImmRegRel;
2627 let accessSize = HalfWordAccess in
2628 defm STrih_indexed: ST_Idxd < "memh", "STrih", IntRegs, s11_1Ext,
2629 u6_1Ext, 12, 7>, AddrModeRel, ImmRegRel;
2631 let accessSize = WordAccess in
2632 defm STriw_indexed: ST_Idxd < "memw", "STriw", IntRegs, s11_2Ext,
2633 u6_2Ext, 13, 8>, AddrModeRel, ImmRegRel;
2635 let accessSize = DoubleWordAccess, isNVStorable = 0 in
2636 defm STrid_indexed: ST_Idxd < "memd", "STrid", DoubleRegs, s11_3Ext,
2637 u6_3Ext, 14, 9>, AddrModeRel;
2640 let AddedComplexity = 10 in {
2641 def : Pat<(truncstorei8 (i32 IntRegs:$src1), (add IntRegs:$src2,
2642 s11_0ExtPred:$offset)),
2643 (STrib_indexed IntRegs:$src2, s11_0ImmPred:$offset,
2644 (i32 IntRegs:$src1))>;
2646 def : Pat<(truncstorei16 (i32 IntRegs:$src1), (add IntRegs:$src2,
2647 s11_1ExtPred:$offset)),
2648 (STrih_indexed IntRegs:$src2, s11_1ImmPred:$offset,
2649 (i32 IntRegs:$src1))>;
2651 def : Pat<(store (i32 IntRegs:$src1), (add IntRegs:$src2,
2652 s11_2ExtPred:$offset)),
2653 (STriw_indexed IntRegs:$src2, s11_2ImmPred:$offset,
2654 (i32 IntRegs:$src1))>;
2656 def : Pat<(store (i64 DoubleRegs:$src1), (add IntRegs:$src2,
2657 s11_3ExtPred:$offset)),
2658 (STrid_indexed IntRegs:$src2, s11_3ImmPred:$offset,
2659 (i64 DoubleRegs:$src1))>;
2662 // memh(Rx++#s4:1)=Rt.H
2666 let Defs = [R10,R11,D5], hasSideEffects = 0 in
2667 def STriw_pred : STInst2<(outs),
2668 (ins MEMri:$addr, PredRegs:$src1),
2669 "Error; should not emit",
2672 // Allocate stack frame.
2673 let Defs = [R29, R30], Uses = [R31, R30], hasSideEffects = 0 in {
2674 def ALLOCFRAME : STInst2<(outs),
2676 "allocframe(#$amt)",
2679 //===----------------------------------------------------------------------===//
2681 //===----------------------------------------------------------------------===//
2683 //===----------------------------------------------------------------------===//
2685 //===----------------------------------------------------------------------===//
2687 def NOT_rr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1),
2688 "$dst = not($src1)",
2689 [(set (i64 DoubleRegs:$dst), (not (i64 DoubleRegs:$src1)))]>;
2692 //===----------------------------------------------------------------------===//
2694 //===----------------------------------------------------------------------===//
2696 let hasSideEffects = 0 in
2697 class T_S2op_1 <string mnemonic, bits<4> RegTyBits, RegisterClass RCOut,
2698 RegisterClass RCIn, bits<2> MajOp, bits<3> MinOp, bit isSat>
2699 : SInst <(outs RCOut:$dst), (ins RCIn:$src),
2700 "$dst = "#mnemonic#"($src)"#!if(isSat, ":sat", ""),
2701 [], "", S_2op_tc_1_SLOT23 > {
2705 let IClass = 0b1000;
2707 let Inst{27-24} = RegTyBits;
2708 let Inst{23-22} = MajOp;
2710 let Inst{20-16} = src;
2711 let Inst{7-5} = MinOp;
2712 let Inst{4-0} = dst;
2715 class T_S2op_1_di <string mnemonic, bits<2> MajOp, bits<3> MinOp>
2716 : T_S2op_1 <mnemonic, 0b0100, DoubleRegs, IntRegs, MajOp, MinOp, 0>;
2718 let hasNewValue = 1 in
2719 class T_S2op_1_id <string mnemonic, bits<2> MajOp, bits<3> MinOp, bit isSat = 0>
2720 : T_S2op_1 <mnemonic, 0b1000, IntRegs, DoubleRegs, MajOp, MinOp, isSat>;
2722 let hasNewValue = 1 in
2723 class T_S2op_1_ii <string mnemonic, bits<2> MajOp, bits<3> MinOp, bit isSat = 0>
2724 : T_S2op_1 <mnemonic, 0b1100, IntRegs, IntRegs, MajOp, MinOp, isSat>;
2726 // Sign extend word to doubleword
2727 let isCodeGenOnly = 0 in
2728 def A2_sxtw : T_S2op_1_di <"sxtw", 0b01, 0b000>;
2730 def: Pat <(i64 (sext I32:$src)), (A2_sxtw I32:$src)>;
2732 // Swizzle the bytes of a word
2733 let isCodeGenOnly = 0 in
2734 def A2_swiz : T_S2op_1_ii <"swiz", 0b10, 0b111>;
2737 let Defs = [USR_OVF], isCodeGenOnly = 0 in {
2738 def A2_sat : T_S2op_1_id <"sat", 0b11, 0b000>;
2739 def A2_satb : T_S2op_1_ii <"satb", 0b11, 0b111>;
2740 def A2_satub : T_S2op_1_ii <"satub", 0b11, 0b110>;
2741 def A2_sath : T_S2op_1_ii <"sath", 0b11, 0b100>;
2742 def A2_satuh : T_S2op_1_ii <"satuh", 0b11, 0b101>;
2745 let Itinerary = S_2op_tc_2_SLOT23, isCodeGenOnly = 0 in {
2746 // Absolute value word
2747 def A2_abs : T_S2op_1_ii <"abs", 0b10, 0b100>;
2749 let Defs = [USR_OVF] in
2750 def A2_abssat : T_S2op_1_ii <"abs", 0b10, 0b101, 1>;
2752 // Negate with saturation
2753 let Defs = [USR_OVF] in
2754 def A2_negsat : T_S2op_1_ii <"neg", 0b10, 0b110, 1>;
2757 def: Pat<(i32 (select (i1 (setlt (i32 IntRegs:$src), 0)),
2758 (i32 (sub 0, (i32 IntRegs:$src))),
2759 (i32 IntRegs:$src))),
2760 (A2_abs IntRegs:$src)>;
2762 let AddedComplexity = 50 in
2763 def: Pat<(i32 (xor (add (sra (i32 IntRegs:$src), (i32 31)),
2764 (i32 IntRegs:$src)),
2765 (sra (i32 IntRegs:$src), (i32 31)))),
2766 (A2_abs IntRegs:$src)>;
2768 class T_S2op_2 <string mnemonic, bits<4> RegTyBits, RegisterClass RCOut,
2769 RegisterClass RCIn, bits<3> MajOp, bits<3> MinOp,
2770 bit isSat, bit isRnd, list<dag> pattern = []>
2771 : SInst <(outs RCOut:$dst),
2772 (ins RCIn:$src, u5Imm:$u5),
2773 "$dst = "#mnemonic#"($src, #$u5)"#!if(isSat, ":sat", "")
2774 #!if(isRnd, ":rnd", ""),
2775 pattern, "", S_2op_tc_2_SLOT23> {
2780 let IClass = 0b1000;
2782 let Inst{27-24} = RegTyBits;
2783 let Inst{23-21} = MajOp;
2784 let Inst{20-16} = src;
2786 let Inst{12-8} = u5;
2787 let Inst{7-5} = MinOp;
2788 let Inst{4-0} = dst;
2791 let hasNewValue = 1 in
2792 class T_S2op_2_ii <string mnemonic, bits<3> MajOp, bits<3> MinOp,
2793 bit isSat = 0, bit isRnd = 0, list<dag> pattern = []>
2794 : T_S2op_2 <mnemonic, 0b1100, IntRegs, IntRegs, MajOp, MinOp,
2795 isSat, isRnd, pattern>;
2797 class T_S2op_shift <string mnemonic, bits<3> MajOp, bits<3> MinOp, SDNode OpNd>
2798 : T_S2op_2_ii <mnemonic, MajOp, MinOp, 0, 0,
2799 [(set (i32 IntRegs:$dst), (OpNd (i32 IntRegs:$src),
2800 (u5ImmPred:$u5)))]>;
2802 // Arithmetic/logical shift right/left by immediate
2803 let Itinerary = S_2op_tc_1_SLOT23, isCodeGenOnly = 0 in {
2804 def S2_asr_i_r : T_S2op_shift <"asr", 0b000, 0b000, sra>;
2805 def S2_lsr_i_r : T_S2op_shift <"lsr", 0b000, 0b001, srl>;
2806 def S2_asl_i_r : T_S2op_shift <"asl", 0b000, 0b010, shl>;
2809 // Shift left by immediate with saturation
2810 let Defs = [USR_OVF], isCodeGenOnly = 0 in
2811 def S2_asl_i_r_sat : T_S2op_2_ii <"asl", 0b010, 0b010, 1>;
2813 // Shift right with round
2814 let isCodeGenOnly = 0 in
2815 def S2_asr_i_r_rnd : T_S2op_2_ii <"asr", 0b010, 0b000, 0, 1>;
2817 def: Pat<(i32 (sra (i32 (add (i32 (sra I32:$src1, u5ImmPred:$src2)),
2820 (S2_asr_i_r_rnd IntRegs:$src1, u5ImmPred:$src2)>;
2822 class T_S2op_3<string opc, bits<2>MajOp, bits<3>minOp, bits<1> sat = 0>
2823 : SInst<(outs DoubleRegs:$Rdd), (ins DoubleRegs:$Rss),
2824 "$Rdd = "#opc#"($Rss)"#!if(!eq(sat, 1),":sat","")> {
2827 let IClass = 0b1000;
2828 let Inst{27-24} = 0;
2829 let Inst{23-22} = MajOp;
2830 let Inst{20-16} = Rss;
2831 let Inst{7-5} = minOp;
2832 let Inst{4-0} = Rdd;
2835 let isCodeGenOnly = 0 in {
2836 def A2_absp : T_S2op_3 <"abs", 0b10, 0b110>;
2837 def A2_negp : T_S2op_3 <"neg", 0b10, 0b101>;
2838 def A2_notp : T_S2op_3 <"not", 0b10, 0b100>;
2841 // Innterleave/deinterleave
2842 let isCodeGenOnly = 0 in {
2843 def S2_interleave : T_S2op_3 <"interleave", 0b11, 0b101>;
2844 def S2_deinterleave : T_S2op_3 <"deinterleave", 0b11, 0b100>;
2847 //===----------------------------------------------------------------------===//
2849 //===----------------------------------------------------------------------===//
2852 def CLRBIT : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
2853 "$dst = clrbit($src1, #$src2)",
2854 [(set (i32 IntRegs:$dst), (and (i32 IntRegs:$src1),
2856 (shl 1, u5ImmPred:$src2))))]>;
2858 def CLRBIT_31 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
2859 "$dst = clrbit($src1, #$src2)",
2862 // Map from r0 = and(r1, 2147483647) to r0 = clrbit(r1, #31).
2863 def : Pat <(and (i32 IntRegs:$src1), 2147483647),
2864 (CLRBIT_31 (i32 IntRegs:$src1), 31)>;
2867 def SETBIT : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
2868 "$dst = setbit($src1, #$src2)",
2869 [(set (i32 IntRegs:$dst), (or (i32 IntRegs:$src1),
2870 (shl 1, u5ImmPred:$src2)))]>;
2872 // Map from r0 = or(r1, -2147483648) to r0 = setbit(r1, #31).
2873 def SETBIT_31 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
2874 "$dst = setbit($src1, #$src2)",
2877 def : Pat <(or (i32 IntRegs:$src1), -2147483648),
2878 (SETBIT_31 (i32 IntRegs:$src1), 31)>;
2881 def TOGBIT : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
2882 "$dst = setbit($src1, #$src2)",
2883 [(set (i32 IntRegs:$dst), (xor (i32 IntRegs:$src1),
2884 (shl 1, u5ImmPred:$src2)))]>;
2886 // Map from r0 = xor(r1, -2147483648) to r0 = togglebit(r1, #31).
2887 def TOGBIT_31 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
2888 "$dst = togglebit($src1, #$src2)",
2891 def : Pat <(xor (i32 IntRegs:$src1), -2147483648),
2892 (TOGBIT_31 (i32 IntRegs:$src1), 31)>;
2894 //===----------------------------------------------------------------------===//
2896 //===----------------------------------------------------------------------===//
2898 //===----------------------------------------------------------------------===//
2900 //===----------------------------------------------------------------------===//
2902 // Predicate transfer.
2903 let hasSideEffects = 0, hasNewValue = 1, isCodeGenOnly = 0 in
2904 def C2_tfrpr : SInst<(outs IntRegs:$Rd), (ins PredRegs:$Ps),
2905 "$Rd = $Ps", [], "", S_2op_tc_1_SLOT23> {
2909 let IClass = 0b1000;
2910 let Inst{27-24} = 0b1001;
2912 let Inst{17-16} = Ps;
2916 // Transfer general register to predicate.
2917 let hasSideEffects = 0, isCodeGenOnly = 0 in
2918 def C2_tfrrp: SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs),
2919 "$Pd = $Rs", [], "", S_2op_tc_2early_SLOT23> {
2923 let IClass = 0b1000;
2924 let Inst{27-21} = 0b0101010;
2925 let Inst{20-16} = Rs;
2929 let hasSideEffects = 0 in
2930 class T_TEST_BIT_IMM<string MnOp, bits<3> MajOp>
2931 : SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, u5Imm:$u5),
2932 "$Pd = "#MnOp#"($Rs, #$u5)",
2933 [], "", S_2op_tc_2early_SLOT23> {
2937 let IClass = 0b1000;
2938 let Inst{27-24} = 0b0101;
2939 let Inst{23-21} = MajOp;
2940 let Inst{20-16} = Rs;
2942 let Inst{12-8} = u5;
2946 def S2_tstbit_i : T_TEST_BIT_IMM<"tstbit", 0b000>;
2948 let AddedComplexity = 20 in { // Complexity greater than cmp reg-imm.
2949 def: Pat<(i1 (trunc (i32 IntRegs:$Rs))),
2950 (S2_tstbit_i IntRegs:$Rs, 0)>;
2954 //===----------------------------------------------------------------------===//
2956 //===----------------------------------------------------------------------===//
2958 //===----------------------------------------------------------------------===//
2960 //===----------------------------------------------------------------------===//
2961 // Shift by immediate.
2962 def ASR_ri : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
2963 "$dst = asr($src1, #$src2)",
2964 [(set (i32 IntRegs:$dst), (sra (i32 IntRegs:$src1),
2965 u5ImmPred:$src2))]>;
2967 def ASRd_ri : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u6Imm:$src2),
2968 "$dst = asr($src1, #$src2)",
2969 [(set (i64 DoubleRegs:$dst), (sra (i64 DoubleRegs:$src1),
2970 u6ImmPred:$src2))]>;
2972 def ASL : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
2973 "$dst = asl($src1, #$src2)",
2974 [(set (i32 IntRegs:$dst), (shl (i32 IntRegs:$src1),
2975 u5ImmPred:$src2))]>;
2977 def ASLd_ri : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u6Imm:$src2),
2978 "$dst = asl($src1, #$src2)",
2979 [(set (i64 DoubleRegs:$dst), (shl (i64 DoubleRegs:$src1),
2980 u6ImmPred:$src2))]>;
2982 def LSR_ri : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
2983 "$dst = lsr($src1, #$src2)",
2984 [(set (i32 IntRegs:$dst), (srl (i32 IntRegs:$src1),
2985 u5ImmPred:$src2))]>;
2987 def LSRd_ri : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u6Imm:$src2),
2988 "$dst = lsr($src1, #$src2)",
2989 [(set (i64 DoubleRegs:$dst), (srl (i64 DoubleRegs:$src1),
2990 u6ImmPred:$src2))]>;
2992 // Shift by immediate and add.
2993 let AddedComplexity = 100 in
2994 def ADDASL : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2,
2996 "$dst = addasl($src1, $src2, #$src3)",
2997 [(set (i32 IntRegs:$dst), (add (i32 IntRegs:$src1),
2998 (shl (i32 IntRegs:$src2),
2999 u3ImmPred:$src3)))]>;
3001 // Shift by register.
3002 def ASL_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
3003 "$dst = asl($src1, $src2)",
3004 [(set (i32 IntRegs:$dst), (shl (i32 IntRegs:$src1),
3005 (i32 IntRegs:$src2)))]>;
3007 def ASR_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
3008 "$dst = asr($src1, $src2)",
3009 [(set (i32 IntRegs:$dst), (sra (i32 IntRegs:$src1),
3010 (i32 IntRegs:$src2)))]>;
3012 def LSL_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
3013 "$dst = lsl($src1, $src2)",
3014 [(set (i32 IntRegs:$dst), (shl (i32 IntRegs:$src1),
3015 (i32 IntRegs:$src2)))]>;
3017 def LSR_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
3018 "$dst = lsr($src1, $src2)",
3019 [(set (i32 IntRegs:$dst), (srl (i32 IntRegs:$src1),
3020 (i32 IntRegs:$src2)))]>;
3022 def ASLd : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
3023 "$dst = asl($src1, $src2)",
3024 [(set (i64 DoubleRegs:$dst), (shl (i64 DoubleRegs:$src1),
3025 (i32 IntRegs:$src2)))]>;
3027 def LSLd : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
3028 "$dst = lsl($src1, $src2)",
3029 [(set (i64 DoubleRegs:$dst), (shl (i64 DoubleRegs:$src1),
3030 (i32 IntRegs:$src2)))]>;
3032 def ASRd_rr : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
3034 "$dst = asr($src1, $src2)",
3035 [(set (i64 DoubleRegs:$dst), (sra (i64 DoubleRegs:$src1),
3036 (i32 IntRegs:$src2)))]>;
3038 def LSRd_rr : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
3040 "$dst = lsr($src1, $src2)",
3041 [(set (i64 DoubleRegs:$dst), (srl (i64 DoubleRegs:$src1),
3042 (i32 IntRegs:$src2)))]>;
3044 //===----------------------------------------------------------------------===//
3046 //===----------------------------------------------------------------------===//
3048 //===----------------------------------------------------------------------===//
3050 //===----------------------------------------------------------------------===//
3051 //===----------------------------------------------------------------------===//
3053 //===----------------------------------------------------------------------===//
3055 //===----------------------------------------------------------------------===//
3057 //===----------------------------------------------------------------------===//
3058 //===----------------------------------------------------------------------===//
3060 //===----------------------------------------------------------------------===//
3062 //===----------------------------------------------------------------------===//
3064 //===----------------------------------------------------------------------===//
3066 //===----------------------------------------------------------------------===//
3068 //===----------------------------------------------------------------------===//
3069 def SDHexagonBARRIER: SDTypeProfile<0, 0, []>;
3070 def HexagonBARRIER: SDNode<"HexagonISD::BARRIER", SDHexagonBARRIER,
3073 let hasSideEffects = 1, isSolo = 1 in
3074 def BARRIER : SYSInst<(outs), (ins),
3076 [(HexagonBARRIER)]>;
3078 //===----------------------------------------------------------------------===//
3080 //===----------------------------------------------------------------------===//
3082 // TFRI64 - assembly mapped.
3083 let isReMaterializable = 1 in
3084 def TFRI64 : ALU64_rr<(outs DoubleRegs:$dst), (ins s8Imm64:$src1),
3086 [(set (i64 DoubleRegs:$dst), s8Imm64Pred:$src1)]>;
3088 let AddedComplexity = 100, isPredicated = 1 in
3089 def TFR_condset_ri : ALU32_rr<(outs IntRegs:$dst),
3090 (ins PredRegs:$src1, IntRegs:$src2, s12Imm:$src3),
3091 "Error; should not emit",
3092 [(set (i32 IntRegs:$dst),
3093 (i32 (select (i1 PredRegs:$src1), (i32 IntRegs:$src2),
3094 s12ImmPred:$src3)))]>;
3096 let AddedComplexity = 100, isPredicated = 1 in
3097 def TFR_condset_ir : ALU32_rr<(outs IntRegs:$dst),
3098 (ins PredRegs:$src1, s12Imm:$src2, IntRegs:$src3),
3099 "Error; should not emit",
3100 [(set (i32 IntRegs:$dst),
3101 (i32 (select (i1 PredRegs:$src1), s12ImmPred:$src2,
3102 (i32 IntRegs:$src3))))]>;
3104 let AddedComplexity = 100, isPredicated = 1 in
3105 def TFR_condset_ii : ALU32_rr<(outs IntRegs:$dst),
3106 (ins PredRegs:$src1, s12Imm:$src2, s12Imm:$src3),
3107 "Error; should not emit",
3108 [(set (i32 IntRegs:$dst),
3109 (i32 (select (i1 PredRegs:$src1), s12ImmPred:$src2,
3110 s12ImmPred:$src3)))]>;
3112 // Generate frameindex addresses.
3113 let isReMaterializable = 1 in
3114 def TFR_FI : ALU32_ri<(outs IntRegs:$dst), (ins FrameIndex:$src1),
3115 "$dst = add($src1)",
3116 [(set (i32 IntRegs:$dst), ADDRri:$src1)]>;
3121 let hasSideEffects = 0, Defs = [SA0, LC0] in {
3122 def LOOP0_i : CRInst<(outs), (ins brtarget:$offset, u10Imm:$src2),
3123 "loop0($offset, #$src2)",
3127 let hasSideEffects = 0, Defs = [SA0, LC0] in {
3128 def LOOP0_r : CRInst<(outs), (ins brtarget:$offset, IntRegs:$src2),
3129 "loop0($offset, $src2)",
3133 let isBranch = 1, isTerminator = 1, hasSideEffects = 0,
3134 Defs = [PC, LC0], Uses = [SA0, LC0] in {
3135 def ENDLOOP0 : Endloop<(outs), (ins brtarget:$offset),
3140 // Support for generating global address.
3141 // Taken from X86InstrInfo.td.
3142 def SDTHexagonCONST32 : SDTypeProfile<1, 1, [
3146 def HexagonCONST32 : SDNode<"HexagonISD::CONST32", SDTHexagonCONST32>;
3147 def HexagonCONST32_GP : SDNode<"HexagonISD::CONST32_GP", SDTHexagonCONST32>;
3149 // HI/LO Instructions
3150 let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0 in
3151 def LO : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$global),
3152 "$dst.l = #LO($global)",
3155 let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0 in
3156 def HI : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$global),
3157 "$dst.h = #HI($global)",
3160 let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0 in
3161 def LOi : ALU32_ri<(outs IntRegs:$dst), (ins i32imm:$imm_value),
3162 "$dst.l = #LO($imm_value)",
3166 let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0 in
3167 def HIi : ALU32_ri<(outs IntRegs:$dst), (ins i32imm:$imm_value),
3168 "$dst.h = #HI($imm_value)",
3171 let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0 in
3172 def LO_jt : ALU32_ri<(outs IntRegs:$dst), (ins jumptablebase:$jt),
3173 "$dst.l = #LO($jt)",
3176 let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0 in
3177 def HI_jt : ALU32_ri<(outs IntRegs:$dst), (ins jumptablebase:$jt),
3178 "$dst.h = #HI($jt)",
3182 let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0 in
3183 def LO_label : ALU32_ri<(outs IntRegs:$dst), (ins bblabel:$label),
3184 "$dst.l = #LO($label)",
3187 let isReMaterializable = 1, isMoveImm = 1 , hasSideEffects = 0 in
3188 def HI_label : ALU32_ri<(outs IntRegs:$dst), (ins bblabel:$label),
3189 "$dst.h = #HI($label)",
3192 // This pattern is incorrect. When we add small data, we should change
3193 // this pattern to use memw(#foo).
3194 // This is for sdata.
3195 let isMoveImm = 1 in
3196 def CONST32 : LDInst<(outs IntRegs:$dst), (ins globaladdress:$global),
3197 "$dst = CONST32(#$global)",
3198 [(set (i32 IntRegs:$dst),
3199 (load (HexagonCONST32 tglobaltlsaddr:$global)))]>;
3201 // This is for non-sdata.
3202 let isReMaterializable = 1, isMoveImm = 1 in
3203 def CONST32_set : LDInst2<(outs IntRegs:$dst), (ins globaladdress:$global),
3204 "$dst = CONST32(#$global)",
3205 [(set (i32 IntRegs:$dst),
3206 (HexagonCONST32 tglobaladdr:$global))]>;
3208 let isReMaterializable = 1, isMoveImm = 1 in
3209 def CONST32_set_jt : LDInst2<(outs IntRegs:$dst), (ins jumptablebase:$jt),
3210 "$dst = CONST32(#$jt)",
3211 [(set (i32 IntRegs:$dst),
3212 (HexagonCONST32 tjumptable:$jt))]>;
3214 let isReMaterializable = 1, isMoveImm = 1 in
3215 def CONST32GP_set : LDInst2<(outs IntRegs:$dst), (ins globaladdress:$global),
3216 "$dst = CONST32(#$global)",
3217 [(set (i32 IntRegs:$dst),
3218 (HexagonCONST32_GP tglobaladdr:$global))]>;
3220 let isReMaterializable = 1, isMoveImm = 1 in
3221 def CONST32_Int_Real : LDInst2<(outs IntRegs:$dst), (ins i32imm:$global),
3222 "$dst = CONST32(#$global)",
3223 [(set (i32 IntRegs:$dst), imm:$global) ]>;
3225 // Map BlockAddress lowering to CONST32_Int_Real
3226 def : Pat<(HexagonCONST32_GP tblockaddress:$addr),
3227 (CONST32_Int_Real tblockaddress:$addr)>;
3229 let isReMaterializable = 1, isMoveImm = 1 in
3230 def CONST32_Label : LDInst2<(outs IntRegs:$dst), (ins bblabel:$label),
3231 "$dst = CONST32($label)",
3232 [(set (i32 IntRegs:$dst), (HexagonCONST32 bbl:$label))]>;
3234 let isReMaterializable = 1, isMoveImm = 1 in
3235 def CONST64_Int_Real : LDInst2<(outs DoubleRegs:$dst), (ins i64imm:$global),
3236 "$dst = CONST64(#$global)",
3237 [(set (i64 DoubleRegs:$dst), imm:$global) ]>;
3239 def TFR_PdFalse : SInst<(outs PredRegs:$dst), (ins),
3240 "$dst = xor($dst, $dst)",
3241 [(set (i1 PredRegs:$dst), 0)]>;
3243 def MPY_trsext : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
3244 "$dst = mpy($src1, $src2)",
3245 [(set (i32 IntRegs:$dst),
3246 (trunc (i64 (srl (i64 (mul (i64 (sext (i32 IntRegs:$src1))),
3247 (i64 (sext (i32 IntRegs:$src2))))),
3250 // Pseudo instructions.
3251 def SDT_SPCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
3253 def SDT_SPCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
3254 SDTCisVT<1, i32> ]>;
3256 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeqEnd,
3257 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
3259 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeqStart,
3260 [SDNPHasChain, SDNPOutGlue]>;
3262 def SDT_SPCall : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
3264 def call : SDNode<"HexagonISD::CALL", SDT_SPCall,
3265 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, SDNPVariadic]>;
3267 // For tailcalls a HexagonTCRet SDNode has 3 SDNode Properties - a chain,
3268 // Optional Flag and Variable Arguments.
3269 // Its 1 Operand has pointer type.
3270 def HexagonTCRet : SDNode<"HexagonISD::TC_RETURN", SDT_SPCall,
3271 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
3273 let Defs = [R29, R30], Uses = [R31, R30, R29] in {
3274 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
3275 "Should never be emitted",
3276 [(callseq_start timm:$amt)]>;
3279 let Defs = [R29, R30, R31], Uses = [R29] in {
3280 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
3281 "Should never be emitted",
3282 [(callseq_end timm:$amt1, timm:$amt2)]>;
3285 let isCall = 1, hasSideEffects = 0,
3286 Defs = [D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10,
3287 R22, R23, R28, R31, P0, P1, P2, P3, LC0, LC1, SA0, SA1] in {
3288 def CALL : JInst<(outs), (ins calltarget:$dst),
3292 // Call subroutine indirectly.
3293 let Defs = VolatileV3.Regs, isCodeGenOnly = 0 in
3294 def J2_callr : JUMPR_MISC_CALLR<0, 1>;
3296 // Indirect tail-call.
3297 let isCodeGenOnly = 1, isCall = 1, isReturn = 1 in
3298 def TCRETURNR : T_JMPr;
3300 // Direct tail-calls.
3301 let isCall = 1, isReturn = 1, isBarrier = 1, isPredicable = 0,
3302 isTerminator = 1, isCodeGenOnly = 1 in {
3303 def TCRETURNtg : JInst<(outs), (ins calltarget:$dst), "jump $dst",
3304 [], "", J_tc_2early_SLOT23>;
3305 def TCRETURNtext : JInst<(outs), (ins calltarget:$dst), "jump $dst",
3306 [], "", J_tc_2early_SLOT23>;
3309 // Map call instruction.
3310 def : Pat<(call (i32 IntRegs:$dst)),
3311 (J2_callr (i32 IntRegs:$dst))>, Requires<[HasV2TOnly]>;
3312 def : Pat<(call tglobaladdr:$dst),
3313 (CALL tglobaladdr:$dst)>, Requires<[HasV2TOnly]>;
3314 def : Pat<(call texternalsym:$dst),
3315 (CALL texternalsym:$dst)>, Requires<[HasV2TOnly]>;
3317 def : Pat<(HexagonTCRet tglobaladdr:$dst),
3318 (TCRETURNtg tglobaladdr:$dst)>;
3319 def : Pat<(HexagonTCRet texternalsym:$dst),
3320 (TCRETURNtext texternalsym:$dst)>;
3321 def : Pat<(HexagonTCRet (i32 IntRegs:$dst)),
3322 (TCRETURNR (i32 IntRegs:$dst))>;
3324 // Atomic load and store support
3325 // 8 bit atomic load
3326 def : Pat<(atomic_load_8 ADDRriS11_0:$src1),
3327 (i32 (LDriub ADDRriS11_0:$src1))>;
3329 def : Pat<(atomic_load_8 (add (i32 IntRegs:$src1), s11_0ImmPred:$offset)),
3330 (i32 (LDriub_indexed (i32 IntRegs:$src1), s11_0ImmPred:$offset))>;
3332 // 16 bit atomic load
3333 def : Pat<(atomic_load_16 ADDRriS11_1:$src1),
3334 (i32 (LDriuh ADDRriS11_1:$src1))>;
3336 def : Pat<(atomic_load_16 (add (i32 IntRegs:$src1), s11_1ImmPred:$offset)),
3337 (i32 (LDriuh_indexed (i32 IntRegs:$src1), s11_1ImmPred:$offset))>;
3339 def : Pat<(atomic_load_32 ADDRriS11_2:$src1),
3340 (i32 (LDriw ADDRriS11_2:$src1))>;
3342 def : Pat<(atomic_load_32 (add (i32 IntRegs:$src1), s11_2ImmPred:$offset)),
3343 (i32 (LDriw_indexed (i32 IntRegs:$src1), s11_2ImmPred:$offset))>;
3345 // 64 bit atomic load
3346 def : Pat<(atomic_load_64 ADDRriS11_3:$src1),
3347 (i64 (LDrid ADDRriS11_3:$src1))>;
3349 def : Pat<(atomic_load_64 (add (i32 IntRegs:$src1), s11_3ImmPred:$offset)),
3350 (i64 (LDrid_indexed (i32 IntRegs:$src1), s11_3ImmPred:$offset))>;
3353 def : Pat<(atomic_store_8 ADDRriS11_0:$src2, (i32 IntRegs:$src1)),
3354 (STrib ADDRriS11_0:$src2, (i32 IntRegs:$src1))>;
3356 def : Pat<(atomic_store_8 (add (i32 IntRegs:$src2), s11_0ImmPred:$offset),
3357 (i32 IntRegs:$src1)),
3358 (STrib_indexed (i32 IntRegs:$src2), s11_0ImmPred:$offset,
3359 (i32 IntRegs:$src1))>;
3362 def : Pat<(atomic_store_16 ADDRriS11_1:$src2, (i32 IntRegs:$src1)),
3363 (STrih ADDRriS11_1:$src2, (i32 IntRegs:$src1))>;
3365 def : Pat<(atomic_store_16 (i32 IntRegs:$src1),
3366 (add (i32 IntRegs:$src2), s11_1ImmPred:$offset)),
3367 (STrih_indexed (i32 IntRegs:$src2), s11_1ImmPred:$offset,
3368 (i32 IntRegs:$src1))>;
3370 def : Pat<(atomic_store_32 ADDRriS11_2:$src2, (i32 IntRegs:$src1)),
3371 (STriw ADDRriS11_2:$src2, (i32 IntRegs:$src1))>;
3373 def : Pat<(atomic_store_32 (add (i32 IntRegs:$src2), s11_2ImmPred:$offset),
3374 (i32 IntRegs:$src1)),
3375 (STriw_indexed (i32 IntRegs:$src2), s11_2ImmPred:$offset,
3376 (i32 IntRegs:$src1))>;
3381 def : Pat<(atomic_store_64 ADDRriS11_3:$src2, (i64 DoubleRegs:$src1)),
3382 (STrid ADDRriS11_3:$src2, (i64 DoubleRegs:$src1))>;
3384 def : Pat<(atomic_store_64 (add (i32 IntRegs:$src2), s11_3ImmPred:$offset),
3385 (i64 DoubleRegs:$src1)),
3386 (STrid_indexed (i32 IntRegs:$src2), s11_3ImmPred:$offset,
3387 (i64 DoubleRegs:$src1))>;
3389 // Map from r0 = and(r1, 65535) to r0 = zxth(r1)
3390 def : Pat <(and (i32 IntRegs:$src1), 65535),
3391 (A2_zxth (i32 IntRegs:$src1))>;
3393 // Map from r0 = and(r1, 255) to r0 = zxtb(r1).
3394 def : Pat <(and (i32 IntRegs:$src1), 255),
3395 (A2_zxtb (i32 IntRegs:$src1))>;
3397 // Map Add(p1, true) to p1 = not(p1).
3398 // Add(p1, false) should never be produced,
3399 // if it does, it got to be mapped to NOOP.
3400 def : Pat <(add (i1 PredRegs:$src1), -1),
3401 (C2_not (i1 PredRegs:$src1))>;
3403 // Map from p0 = pnot(p0); r0 = mux(p0, #i, #j) => r0 = mux(p0, #j, #i).
3404 def : Pat <(select (not (i1 PredRegs:$src1)), s8ImmPred:$src2, s8ImmPred:$src3),
3405 (i32 (TFR_condset_ii (i1 PredRegs:$src1), s8ImmPred:$src3,
3408 // Map from p0 = pnot(p0); r0 = select(p0, #i, r1)
3409 // => r0 = TFR_condset_ri(p0, r1, #i)
3410 def : Pat <(select (not (i1 PredRegs:$src1)), s12ImmPred:$src2,
3411 (i32 IntRegs:$src3)),
3412 (i32 (TFR_condset_ri (i1 PredRegs:$src1), (i32 IntRegs:$src3),
3413 s12ImmPred:$src2))>;
3415 // Map from p0 = pnot(p0); r0 = mux(p0, r1, #i)
3416 // => r0 = TFR_condset_ir(p0, #i, r1)
3417 def : Pat <(select (not (i1 PredRegs:$src1)), IntRegs:$src2, s12ImmPred:$src3),
3418 (i32 (TFR_condset_ir (i1 PredRegs:$src1), s12ImmPred:$src3,
3419 (i32 IntRegs:$src2)))>;
3421 // Map from p0 = pnot(p0); if (p0) jump => if (!p0) jump.
3422 def : Pat <(brcond (not (i1 PredRegs:$src1)), bb:$offset),
3423 (J2_jumpf (i1 PredRegs:$src1), bb:$offset)>;
3425 // Map from p2 = pnot(p2); p1 = and(p0, p2) => p1 = and(p0, !p2).
3426 def : Pat <(and (i1 PredRegs:$src1), (not (i1 PredRegs:$src2))),
3427 (i1 (C2_andn (i1 PredRegs:$src1), (i1 PredRegs:$src2)))>;
3430 let AddedComplexity = 100 in
3431 def : Pat <(i64 (zextloadi1 (HexagonCONST32 tglobaladdr:$global))),
3432 (i64 (A2_combinew (A2_tfrsi 0),
3433 (LDriub_indexed (CONST32_set tglobaladdr:$global), 0)))>,
3436 // Map from i1 loads to 32 bits. This assumes that the i1* is byte aligned.
3437 let AddedComplexity = 10 in
3438 def : Pat <(i32 (zextloadi1 ADDRriS11_0:$addr)),
3439 (i32 (A2_and (i32 (LDrib ADDRriS11_0:$addr)), (A2_tfrsi 0x1)))>;
3441 // Map from Rdd = sign_extend_inreg(Rss, i32) -> Rdd = A2_sxtw(Rss.lo).
3442 def : Pat <(i64 (sext_inreg (i64 DoubleRegs:$src1), i32)),
3443 (i64 (A2_sxtw (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_loreg))))>;
3445 // Map from Rdd = sign_extend_inreg(Rss, i16) -> Rdd = A2_sxtw(SXTH(Rss.lo)).
3446 def : Pat <(i64 (sext_inreg (i64 DoubleRegs:$src1), i16)),
3447 (i64 (A2_sxtw (i32 (A2_sxth (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
3448 subreg_loreg))))))>;
3450 // Map from Rdd = sign_extend_inreg(Rss, i8) -> Rdd = A2_sxtw(SXTB(Rss.lo)).
3451 def : Pat <(i64 (sext_inreg (i64 DoubleRegs:$src1), i8)),
3452 (i64 (A2_sxtw (i32 (A2_sxtb (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
3453 subreg_loreg))))))>;
3455 // We want to prevent emitting pnot's as much as possible.
3456 // Map brcond with an unsupported setcc to a J2_jumpf.
3457 def : Pat <(brcond (i1 (setne (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
3459 (J2_jumpf (C2_cmpeq (i32 IntRegs:$src1), (i32 IntRegs:$src2)),
3462 def : Pat <(brcond (i1 (setne (i32 IntRegs:$src1), s10ImmPred:$src2)),
3464 (J2_jumpf (C2_cmpeqi (i32 IntRegs:$src1), s10ImmPred:$src2), bb:$offset)>;
3466 def : Pat <(brcond (i1 (setne (i1 PredRegs:$src1), (i1 -1))), bb:$offset),
3467 (J2_jumpf (i1 PredRegs:$src1), bb:$offset)>;
3469 def : Pat <(brcond (i1 (setne (i1 PredRegs:$src1), (i1 0))), bb:$offset),
3470 (J2_jumpt (i1 PredRegs:$src1), bb:$offset)>;
3472 // cmp.lt(Rs, Imm) -> !cmp.ge(Rs, Imm) -> !cmp.gt(Rs, Imm-1)
3473 def : Pat <(brcond (i1 (setlt (i32 IntRegs:$src1), s8ImmPred:$src2)),
3475 (J2_jumpf (C2_cmpgti (i32 IntRegs:$src1),
3476 (DEC_CONST_SIGNED s8ImmPred:$src2)), bb:$offset)>;
3478 // cmp.lt(r0, r1) -> cmp.gt(r1, r0)
3479 def : Pat <(brcond (i1 (setlt (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
3481 (J2_jumpt (C2_cmpgt (i32 IntRegs:$src2), (i32 IntRegs:$src1)), bb:$offset)>;
3483 def : Pat <(brcond (i1 (setuge (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
3485 (J2_jumpf (C2_cmpgtup (i64 DoubleRegs:$src2), (i64 DoubleRegs:$src1)),
3488 def : Pat <(brcond (i1 (setule (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
3490 (J2_jumpf (C2_cmpgtu (i32 IntRegs:$src1), (i32 IntRegs:$src2)),
3493 def : Pat <(brcond (i1 (setule (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
3495 (J2_jumpf (C2_cmpgtup (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2)),
3498 // Map from a 64-bit select to an emulated 64-bit mux.
3499 // Hexagon does not support 64-bit MUXes; so emulate with combines.
3500 def : Pat <(select (i1 PredRegs:$src1), (i64 DoubleRegs:$src2),
3501 (i64 DoubleRegs:$src3)),
3502 (i64 (A2_combinew (i32 (C2_mux (i1 PredRegs:$src1),
3503 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
3505 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src3),
3507 (i32 (C2_mux (i1 PredRegs:$src1),
3508 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
3510 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src3),
3511 subreg_loreg))))))>;
3513 // Map from a 1-bit select to logical ops.
3514 // From LegalizeDAG.cpp: (B1 ? B2 : B3) <=> (B1 & B2)|(!B1&B3).
3515 def : Pat <(select (i1 PredRegs:$src1), (i1 PredRegs:$src2),
3516 (i1 PredRegs:$src3)),
3517 (C2_or (C2_and (i1 PredRegs:$src1), (i1 PredRegs:$src2)),
3518 (C2_and (C2_not (i1 PredRegs:$src1)), (i1 PredRegs:$src3)))>;
3520 // Map Pd = load(addr) -> Rs = load(addr); Pd = Rs.
3521 def : Pat<(i1 (load ADDRriS11_2:$addr)),
3522 (i1 (C2_tfrrp (i32 (LDrib ADDRriS11_2:$addr))))>;
3524 // Map for truncating from 64 immediates to 32 bit immediates.
3525 def : Pat<(i32 (trunc (i64 DoubleRegs:$src))),
3526 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src), subreg_loreg))>;
3528 // Map for truncating from i64 immediates to i1 bit immediates.
3529 def : Pat<(i1 (trunc (i64 DoubleRegs:$src))),
3530 (i1 (C2_tfrrp (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
3533 // Map memb(Rs) = Rdd -> memb(Rs) = Rt.
3534 def : Pat<(truncstorei8 (i64 DoubleRegs:$src), ADDRriS11_0:$addr),
3535 (STrib ADDRriS11_0:$addr, (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
3538 // Map memh(Rs) = Rdd -> memh(Rs) = Rt.
3539 def : Pat<(truncstorei16 (i64 DoubleRegs:$src), ADDRriS11_0:$addr),
3540 (STrih ADDRriS11_0:$addr, (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
3542 // Map memw(Rs) = Rdd -> memw(Rs) = Rt
3543 def : Pat<(truncstorei32 (i64 DoubleRegs:$src), ADDRriS11_0:$addr),
3544 (STriw ADDRriS11_0:$addr, (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
3547 // Map memw(Rs) = Rdd -> memw(Rs) = Rt.
3548 def : Pat<(truncstorei32 (i64 DoubleRegs:$src), ADDRriS11_0:$addr),
3549 (STriw ADDRriS11_0:$addr, (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
3552 // Map from i1 = constant<-1>; memw(addr) = i1 -> r0 = 1; memw(addr) = r0.
3553 def : Pat<(store (i1 -1), ADDRriS11_2:$addr),
3554 (STrib ADDRriS11_2:$addr, (A2_tfrsi 1))>;
3557 // Map from i1 = constant<-1>; store i1 -> r0 = 1; store r0.
3558 def : Pat<(store (i1 -1), ADDRriS11_2:$addr),
3559 (STrib ADDRriS11_2:$addr, (A2_tfrsi 1))>;
3561 // Map from memb(Rs) = Pd -> Rt = mux(Pd, #0, #1); store Rt.
3562 def : Pat<(store (i1 PredRegs:$src1), ADDRriS11_2:$addr),
3563 (STrib ADDRriS11_2:$addr, (i32 (C2_muxii (i1 PredRegs:$src1), 1, 0)) )>;
3565 // Map Rdd = anyext(Rs) -> Rdd = A2_sxtw(Rs).
3566 // Hexagon_TODO: We can probably use combine but that will cost 2 instructions.
3567 // Better way to do this?
3568 def : Pat<(i64 (anyext (i32 IntRegs:$src1))),
3569 (i64 (A2_sxtw (i32 IntRegs:$src1)))>;
3571 // Map cmple -> cmpgt.
3572 // rs <= rt -> !(rs > rt).
3573 def : Pat<(i1 (setle (i32 IntRegs:$src1), s10ExtPred:$src2)),
3574 (i1 (C2_not (C2_cmpgti (i32 IntRegs:$src1), s10ExtPred:$src2)))>;
3576 // rs <= rt -> !(rs > rt).
3577 def : Pat<(i1 (setle (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
3578 (i1 (C2_not (C2_cmpgt (i32 IntRegs:$src1), (i32 IntRegs:$src2))))>;
3580 // Rss <= Rtt -> !(Rss > Rtt).
3581 def : Pat<(i1 (setle (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
3582 (i1 (C2_not (C2_cmpgtp (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))))>;
3584 // Map cmpne -> cmpeq.
3585 // Hexagon_TODO: We should improve on this.
3586 // rs != rt -> !(rs == rt).
3587 def : Pat <(i1 (setne (i32 IntRegs:$src1), s10ExtPred:$src2)),
3588 (i1 (C2_not(i1 (C2_cmpeqi (i32 IntRegs:$src1), s10ExtPred:$src2))))>;
3590 // Map cmpne(Rs) -> !cmpeqe(Rs).
3591 // rs != rt -> !(rs == rt).
3592 def : Pat <(i1 (setne (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
3593 (i1 (C2_not (i1 (C2_cmpeq (i32 IntRegs:$src1), (i32 IntRegs:$src2)))))>;
3595 // Convert setne back to xor for hexagon since we compute w/ pred registers.
3596 def : Pat <(i1 (setne (i1 PredRegs:$src1), (i1 PredRegs:$src2))),
3597 (i1 (C2_xor (i1 PredRegs:$src1), (i1 PredRegs:$src2)))>;
3599 // Map cmpne(Rss) -> !cmpew(Rss).
3600 // rs != rt -> !(rs == rt).
3601 def : Pat <(i1 (setne (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
3602 (i1 (C2_not (i1 (C2_cmpeqp (i64 DoubleRegs:$src1),
3603 (i64 DoubleRegs:$src2)))))>;
3605 // Map cmpge(Rs, Rt) -> !(cmpgt(Rs, Rt).
3606 // rs >= rt -> !(rt > rs).
3607 def : Pat <(i1 (setge (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
3608 (i1 (C2_not (i1 (C2_cmpgt (i32 IntRegs:$src2), (i32 IntRegs:$src1)))))>;
3610 // cmpge(Rs, Imm) -> cmpgt(Rs, Imm-1)
3611 def : Pat <(i1 (setge (i32 IntRegs:$src1), s8ExtPred:$src2)),
3612 (i1 (C2_cmpgti (i32 IntRegs:$src1), (DEC_CONST_SIGNED s8ExtPred:$src2)))>;
3614 // Map cmpge(Rss, Rtt) -> !cmpgt(Rtt, Rss).
3615 // rss >= rtt -> !(rtt > rss).
3616 def : Pat <(i1 (setge (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
3617 (i1 (C2_not (i1 (C2_cmpgtp (i64 DoubleRegs:$src2),
3618 (i64 DoubleRegs:$src1)))))>;
3620 // Map cmplt(Rs, Imm) -> !cmpge(Rs, Imm).
3621 // !cmpge(Rs, Imm) -> !cmpgt(Rs, Imm-1).
3622 // rs < rt -> !(rs >= rt).
3623 def : Pat <(i1 (setlt (i32 IntRegs:$src1), s8ExtPred:$src2)),
3624 (i1 (C2_not (C2_cmpgti (i32 IntRegs:$src1), (DEC_CONST_SIGNED s8ExtPred:$src2))))>;
3626 // Map cmplt(Rs, Rt) -> cmpgt(Rt, Rs).
3627 // rs < rt -> rt > rs.
3628 // We can let assembler map it, or we can do in the compiler itself.
3629 def : Pat <(i1 (setlt (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
3630 (i1 (C2_cmpgt (i32 IntRegs:$src2), (i32 IntRegs:$src1)))>;
3632 // Map cmplt(Rss, Rtt) -> cmpgt(Rtt, Rss).
3633 // rss < rtt -> (rtt > rss).
3634 def : Pat <(i1 (setlt (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
3635 (i1 (C2_cmpgtp (i64 DoubleRegs:$src2), (i64 DoubleRegs:$src1)))>;
3637 // Map from cmpltu(Rs, Rd) -> cmpgtu(Rd, Rs)
3638 // rs < rt -> rt > rs.
3639 // We can let assembler map it, or we can do in the compiler itself.
3640 def : Pat <(i1 (setult (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
3641 (i1 (C2_cmpgtu (i32 IntRegs:$src2), (i32 IntRegs:$src1)))>;
3643 // Map from cmpltu(Rss, Rdd) -> cmpgtu(Rdd, Rss).
3644 // rs < rt -> rt > rs.
3645 def : Pat <(i1 (setult (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
3646 (i1 (C2_cmpgtup (i64 DoubleRegs:$src2), (i64 DoubleRegs:$src1)))>;
3648 // Generate cmpgeu(Rs, #0) -> cmpeq(Rs, Rs)
3649 def : Pat <(i1 (setuge (i32 IntRegs:$src1), 0)),
3650 (i1 (C2_cmpeq (i32 IntRegs:$src1), (i32 IntRegs:$src1)))>;
3652 // Generate cmpgeu(Rs, #u8) -> cmpgtu(Rs, #u8 -1)
3653 def : Pat <(i1 (setuge (i32 IntRegs:$src1), u8ExtPred:$src2)),
3654 (i1 (C2_cmpgtui (i32 IntRegs:$src1), (DEC_CONST_UNSIGNED u8ExtPred:$src2)))>;
3656 // Generate cmpgtu(Rs, #u9)
3657 def : Pat <(i1 (setugt (i32 IntRegs:$src1), u9ExtPred:$src2)),
3658 (i1 (C2_cmpgtui (i32 IntRegs:$src1), u9ExtPred:$src2))>;
3660 // Map from Rs >= Rt -> !(Rt > Rs).
3661 // rs >= rt -> !(rt > rs).
3662 def : Pat <(i1 (setuge (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
3663 (i1 (C2_not (C2_cmpgtu (i32 IntRegs:$src2), (i32 IntRegs:$src1))))>;
3665 // Map from Rs >= Rt -> !(Rt > Rs).
3666 // rs >= rt -> !(rt > rs).
3667 def : Pat <(i1 (setuge (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
3668 (i1 (C2_not (C2_cmpgtup (i64 DoubleRegs:$src2), (i64 DoubleRegs:$src1))))>;
3670 // Map from cmpleu(Rs, Rt) -> !cmpgtu(Rs, Rt).
3671 // Map from (Rs <= Rt) -> !(Rs > Rt).
3672 def : Pat <(i1 (setule (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
3673 (i1 (C2_not (C2_cmpgtu (i32 IntRegs:$src1), (i32 IntRegs:$src2))))>;
3675 // Map from cmpleu(Rss, Rtt) -> !cmpgtu(Rss, Rtt-1).
3676 // Map from (Rs <= Rt) -> !(Rs > Rt).
3677 def : Pat <(i1 (setule (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
3678 (i1 (C2_not (C2_cmpgtup (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))))>;
3682 def : Pat <(i32 (sext (i1 PredRegs:$src1))),
3683 (i32 (C2_muxii (i1 PredRegs:$src1), -1, 0))>;
3686 def : Pat <(i64 (sext (i1 PredRegs:$src1))),
3687 (i64 (A2_combinew (A2_tfrsi -1), (C2_muxii (i1 PredRegs:$src1), -1, 0)))>;
3689 // Convert sign-extended load back to load and sign extend.
3691 def: Pat <(i64 (sextloadi8 ADDRriS11_0:$src1)),
3692 (i64 (A2_sxtw (LDrib ADDRriS11_0:$src1)))>;
3694 // Convert any-extended load back to load and sign extend.
3696 def: Pat <(i64 (extloadi8 ADDRriS11_0:$src1)),
3697 (i64 (A2_sxtw (LDrib ADDRriS11_0:$src1)))>;
3699 // Convert sign-extended load back to load and sign extend.
3701 def: Pat <(i64 (sextloadi16 ADDRriS11_1:$src1)),
3702 (i64 (A2_sxtw (LDrih ADDRriS11_1:$src1)))>;
3704 // Convert sign-extended load back to load and sign extend.
3706 def: Pat <(i64 (sextloadi32 ADDRriS11_2:$src1)),
3707 (i64 (A2_sxtw (LDriw ADDRriS11_2:$src1)))>;
3712 def : Pat <(i32 (zext (i1 PredRegs:$src1))),
3713 (i32 (C2_muxii (i1 PredRegs:$src1), 1, 0))>;
3716 def : Pat <(i64 (zext (i1 PredRegs:$src1))),
3717 (i64 (A2_combinew (A2_tfrsi 0), (C2_muxii (i1 PredRegs:$src1), 1, 0)))>,
3721 def : Pat <(i64 (zext (i32 IntRegs:$src1))),
3722 (i64 (A2_combinew (A2_tfrsi 0), (i32 IntRegs:$src1)))>,
3726 def: Pat <(i64 (zextloadi8 ADDRriS11_0:$src1)),
3727 (i64 (A2_combinew (A2_tfrsi 0), (LDriub ADDRriS11_0:$src1)))>,
3730 let AddedComplexity = 20 in
3731 def: Pat <(i64 (zextloadi8 (add (i32 IntRegs:$src1),
3732 s11_0ExtPred:$offset))),
3733 (i64 (A2_combinew (A2_tfrsi 0), (LDriub_indexed IntRegs:$src1,
3734 s11_0ExtPred:$offset)))>,
3738 def: Pat <(i64 (zextloadi1 ADDRriS11_0:$src1)),
3739 (i64 (A2_combinew (A2_tfrsi 0), (LDriub ADDRriS11_0:$src1)))>,
3742 let AddedComplexity = 20 in
3743 def: Pat <(i64 (zextloadi1 (add (i32 IntRegs:$src1),
3744 s11_0ExtPred:$offset))),
3745 (i64 (A2_combinew (A2_tfrsi 0), (LDriub_indexed IntRegs:$src1,
3746 s11_0ExtPred:$offset)))>,
3750 def: Pat <(i64 (zextloadi16 ADDRriS11_1:$src1)),
3751 (i64 (A2_combinew (A2_tfrsi 0), (LDriuh ADDRriS11_1:$src1)))>,
3754 let AddedComplexity = 20 in
3755 def: Pat <(i64 (zextloadi16 (add (i32 IntRegs:$src1),
3756 s11_1ExtPred:$offset))),
3757 (i64 (A2_combinew (A2_tfrsi 0), (LDriuh_indexed IntRegs:$src1,
3758 s11_1ExtPred:$offset)))>,
3762 def: Pat <(i64 (zextloadi32 ADDRriS11_2:$src1)),
3763 (i64 (A2_combinew (A2_tfrsi 0), (LDriw ADDRriS11_2:$src1)))>,
3766 let AddedComplexity = 100 in
3767 def: Pat <(i64 (zextloadi32 (i32 (add IntRegs:$src1, s11_2ExtPred:$offset)))),
3768 (i64 (A2_combinew (A2_tfrsi 0), (LDriw_indexed IntRegs:$src1,
3769 s11_2ExtPred:$offset)))>,
3772 let AddedComplexity = 10 in
3773 def: Pat <(i32 (zextloadi1 ADDRriS11_0:$src1)),
3774 (i32 (LDriw ADDRriS11_0:$src1))>;
3776 // Map from Rs = Pd to Pd = mux(Pd, #1, #0)
3777 def : Pat <(i32 (zext (i1 PredRegs:$src1))),
3778 (i32 (C2_muxii (i1 PredRegs:$src1), 1, 0))>;
3780 // Map from Rs = Pd to Pd = mux(Pd, #1, #0)
3781 def : Pat <(i32 (anyext (i1 PredRegs:$src1))),
3782 (i32 (C2_muxii (i1 PredRegs:$src1), 1, 0))>;
3784 // Map from Rss = Pd to Rdd = A2_sxtw (mux(Pd, #1, #0))
3785 def : Pat <(i64 (anyext (i1 PredRegs:$src1))),
3786 (i64 (A2_sxtw (i32 (C2_muxii (i1 PredRegs:$src1), 1, 0))))>;
3789 let AddedComplexity = 100 in
3790 def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh),
3792 (i64 (zextloadi32 (i32 (add IntRegs:$src2,
3793 s11_2ExtPred:$offset2)))))),
3794 (i64 (A2_combinew (EXTRACT_SUBREG (i64 DoubleRegs:$srcHigh), subreg_loreg),
3795 (LDriw_indexed IntRegs:$src2,
3796 s11_2ExtPred:$offset2)))>;
3798 def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh),
3800 (i64 (zextloadi32 ADDRriS11_2:$srcLow)))),
3801 (i64 (A2_combinew (EXTRACT_SUBREG (i64 DoubleRegs:$srcHigh), subreg_loreg),
3802 (LDriw ADDRriS11_2:$srcLow)))>;
3804 def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh),
3806 (i64 (zext (i32 IntRegs:$srcLow))))),
3807 (i64 (A2_combinew (EXTRACT_SUBREG (i64 DoubleRegs:$srcHigh), subreg_loreg),
3810 let AddedComplexity = 100 in
3811 def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh),
3813 (i64 (zextloadi32 (i32 (add IntRegs:$src2,
3814 s11_2ExtPred:$offset2)))))),
3815 (i64 (A2_combinew (EXTRACT_SUBREG (i64 DoubleRegs:$srcHigh), subreg_loreg),
3816 (LDriw_indexed IntRegs:$src2,
3817 s11_2ExtPred:$offset2)))>;
3819 def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh),
3821 (i64 (zextloadi32 ADDRriS11_2:$srcLow)))),
3822 (i64 (A2_combinew (EXTRACT_SUBREG (i64 DoubleRegs:$srcHigh), subreg_loreg),
3823 (LDriw ADDRriS11_2:$srcLow)))>;
3825 def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh),
3827 (i64 (zext (i32 IntRegs:$srcLow))))),
3828 (i64 (A2_combinew (EXTRACT_SUBREG (i64 DoubleRegs:$srcHigh), subreg_loreg),
3831 // Any extended 64-bit load.
3832 // anyext i32 -> i64
3833 def: Pat <(i64 (extloadi32 ADDRriS11_2:$src1)),
3834 (i64 (A2_combinew (A2_tfrsi 0), (LDriw ADDRriS11_2:$src1)))>,
3837 // When there is an offset we should prefer the pattern below over the pattern above.
3838 // The complexity of the above is 13 (gleaned from HexagonGenDAGIsel.inc)
3839 // So this complexity below is comfortably higher to allow for choosing the below.
3840 // If this is not done then we generate addresses such as
3841 // ********************************************
3842 // r1 = add (r0, #4)
3843 // r1 = memw(r1 + #0)
3845 // r1 = memw(r0 + #4)
3846 // ********************************************
3847 let AddedComplexity = 100 in
3848 def: Pat <(i64 (extloadi32 (i32 (add IntRegs:$src1, s11_2ExtPred:$offset)))),
3849 (i64 (A2_combinew (A2_tfrsi 0), (LDriw_indexed IntRegs:$src1,
3850 s11_2ExtPred:$offset)))>,
3853 // anyext i16 -> i64.
3854 def: Pat <(i64 (extloadi16 ADDRriS11_2:$src1)),
3855 (i64 (A2_combinew (A2_tfrsi 0), (LDrih ADDRriS11_2:$src1)))>,
3858 let AddedComplexity = 20 in
3859 def: Pat <(i64 (extloadi16 (add (i32 IntRegs:$src1),
3860 s11_1ExtPred:$offset))),
3861 (i64 (A2_combinew (A2_tfrsi 0), (LDrih_indexed IntRegs:$src1,
3862 s11_1ExtPred:$offset)))>,
3865 // Map from Rdd = zxtw(Rs) -> Rdd = combine(0, Rs).
3866 def : Pat<(i64 (zext (i32 IntRegs:$src1))),
3867 (i64 (A2_combinew (A2_tfrsi 0), (i32 IntRegs:$src1)))>,
3870 // Multiply 64-bit unsigned and use upper result.
3871 def : Pat <(mulhu (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2)),
3886 (A2_combinew (A2_tfrsi 0),
3893 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
3895 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
3896 subreg_loreg)))), 32)),
3898 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg)),
3899 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_loreg)))),
3900 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_loreg)),
3901 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg)))),
3902 32)), subreg_loreg)))),
3903 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg)),
3904 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg))))>;
3906 // Multiply 64-bit signed and use upper result.
3907 def : Pat <(mulhs (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2)),
3911 (A2_combinew (A2_tfrsi 0),
3921 (A2_combinew (A2_tfrsi 0),
3928 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
3930 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
3931 subreg_loreg)))), 32)),
3933 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg)),
3934 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_loreg)))),
3935 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_loreg)),
3936 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg)))),
3937 32)), subreg_loreg)))),
3938 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg)),
3939 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg))))>;
3941 // Hexagon specific ISD nodes.
3942 //def SDTHexagonADJDYNALLOC : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>]>;
3943 def SDTHexagonADJDYNALLOC : SDTypeProfile<1, 2,
3944 [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
3945 def Hexagon_ADJDYNALLOC : SDNode<"HexagonISD::ADJDYNALLOC",
3946 SDTHexagonADJDYNALLOC>;
3947 // Needed to tag these instructions for stack layout.
3948 let usesCustomInserter = 1 in
3949 def ADJDYNALLOC : ALU32_ri<(outs IntRegs:$dst), (ins IntRegs:$src1,
3951 "$dst = add($src1, #$src2)",
3952 [(set (i32 IntRegs:$dst),
3953 (Hexagon_ADJDYNALLOC (i32 IntRegs:$src1),
3954 s16ImmPred:$src2))]>;
3956 def SDTHexagonARGEXTEND : SDTypeProfile<1, 1, [SDTCisVT<0, i32>]>;
3957 def Hexagon_ARGEXTEND : SDNode<"HexagonISD::ARGEXTEND", SDTHexagonARGEXTEND>;
3958 def ARGEXTEND : ALU32_rr <(outs IntRegs:$dst), (ins IntRegs:$src1),
3960 [(set (i32 IntRegs:$dst),
3961 (Hexagon_ARGEXTEND (i32 IntRegs:$src1)))]>;
3963 let AddedComplexity = 100 in
3964 def : Pat<(i32 (sext_inreg (Hexagon_ARGEXTEND (i32 IntRegs:$src1)), i16)),
3965 (COPY (i32 IntRegs:$src1))>;
3967 def HexagonWrapperJT: SDNode<"HexagonISD::WrapperJT", SDTIntUnaryOp>;
3969 def : Pat<(HexagonWrapperJT tjumptable:$dst),
3970 (i32 (CONST32_set_jt tjumptable:$dst))>;
3974 // Multi-class for logical operators :
3975 // Shift by immediate/register and accumulate/logical
3976 multiclass xtype_imm<string OpcStr, SDNode OpNode1, SDNode OpNode2> {
3977 def _ri : SInst_acc<(outs IntRegs:$dst),
3978 (ins IntRegs:$src1, IntRegs:$src2, u5Imm:$src3),
3979 !strconcat("$dst ", !strconcat(OpcStr, "($src2, #$src3)")),
3980 [(set (i32 IntRegs:$dst),
3981 (OpNode2 (i32 IntRegs:$src1),
3982 (OpNode1 (i32 IntRegs:$src2),
3983 u5ImmPred:$src3)))],
3986 def d_ri : SInst_acc<(outs DoubleRegs:$dst),
3987 (ins DoubleRegs:$src1, DoubleRegs:$src2, u6Imm:$src3),
3988 !strconcat("$dst ", !strconcat(OpcStr, "($src2, #$src3)")),
3989 [(set (i64 DoubleRegs:$dst), (OpNode2 (i64 DoubleRegs:$src1),
3990 (OpNode1 (i64 DoubleRegs:$src2), u6ImmPred:$src3)))],
3994 // Multi-class for logical operators :
3995 // Shift by register and accumulate/logical (32/64 bits)
3996 multiclass xtype_reg<string OpcStr, SDNode OpNode1, SDNode OpNode2> {
3997 def _rr : SInst_acc<(outs IntRegs:$dst),
3998 (ins IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
3999 !strconcat("$dst ", !strconcat(OpcStr, "($src2, $src3)")),
4000 [(set (i32 IntRegs:$dst),
4001 (OpNode2 (i32 IntRegs:$src1),
4002 (OpNode1 (i32 IntRegs:$src2),
4003 (i32 IntRegs:$src3))))],
4006 def d_rr : SInst_acc<(outs DoubleRegs:$dst),
4007 (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
4008 !strconcat("$dst ", !strconcat(OpcStr, "($src2, $src3)")),
4009 [(set (i64 DoubleRegs:$dst),
4010 (OpNode2 (i64 DoubleRegs:$src1),
4011 (OpNode1 (i64 DoubleRegs:$src2),
4012 (i32 IntRegs:$src3))))],
4017 multiclass basic_xtype_imm<string OpcStr, SDNode OpNode> {
4018 let AddedComplexity = 100 in
4019 defm _ADD : xtype_imm< !strconcat("+= ", OpcStr), OpNode, add>;
4020 defm _SUB : xtype_imm< !strconcat("-= ", OpcStr), OpNode, sub>;
4021 defm _AND : xtype_imm< !strconcat("&= ", OpcStr), OpNode, and>;
4022 defm _OR : xtype_imm< !strconcat("|= ", OpcStr), OpNode, or>;
4025 multiclass basic_xtype_reg<string OpcStr, SDNode OpNode> {
4026 let AddedComplexity = 100 in
4027 defm _ADD : xtype_reg< !strconcat("+= ", OpcStr), OpNode, add>;
4028 defm _SUB : xtype_reg< !strconcat("-= ", OpcStr), OpNode, sub>;
4029 defm _AND : xtype_reg< !strconcat("&= ", OpcStr), OpNode, and>;
4030 defm _OR : xtype_reg< !strconcat("|= ", OpcStr), OpNode, or>;
4033 multiclass xtype_xor_imm<string OpcStr, SDNode OpNode> {
4034 let AddedComplexity = 100 in
4035 defm _XOR : xtype_imm< !strconcat("^= ", OpcStr), OpNode, xor>;
4038 defm ASL : basic_xtype_imm<"asl", shl>, basic_xtype_reg<"asl", shl>,
4039 xtype_xor_imm<"asl", shl>;
4041 defm LSR : basic_xtype_imm<"lsr", srl>, basic_xtype_reg<"lsr", srl>,
4042 xtype_xor_imm<"lsr", srl>;
4044 defm ASR : basic_xtype_imm<"asr", sra>, basic_xtype_reg<"asr", sra>;
4045 defm LSL : basic_xtype_reg<"lsl", shl>;
4047 // Change the sign of the immediate for Rd=-mpyi(Rs,#u8)
4048 def : Pat <(mul (i32 IntRegs:$src1), (ineg n8ImmPred:$src2)),
4049 (i32 (M2_mpysin (i32 IntRegs:$src1), u8ImmPred:$src2))>;
4051 //===----------------------------------------------------------------------===//
4052 // V3 Instructions +
4053 //===----------------------------------------------------------------------===//
4055 include "HexagonInstrInfoV3.td"
4057 //===----------------------------------------------------------------------===//
4058 // V3 Instructions -
4059 //===----------------------------------------------------------------------===//
4061 //===----------------------------------------------------------------------===//
4062 // V4 Instructions +
4063 //===----------------------------------------------------------------------===//
4065 include "HexagonInstrInfoV4.td"
4067 //===----------------------------------------------------------------------===//
4068 // V4 Instructions -
4069 //===----------------------------------------------------------------------===//
4071 //===----------------------------------------------------------------------===//
4072 // V5 Instructions +
4073 //===----------------------------------------------------------------------===//
4075 include "HexagonInstrInfoV5.td"
4077 //===----------------------------------------------------------------------===//
4078 // V5 Instructions -
4079 //===----------------------------------------------------------------------===//