1 //==- HexagonInstrInfo.td - Target Description for Hexagon -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Hexagon instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 include "HexagonInstrFormats.td"
15 include "HexagonOperands.td"
17 // Pattern fragment that combines the value type and the register class
18 // into a single parameter.
19 // The pat frags in the definitions below need to have a named register,
20 // otherwise i32 will be assumed regardless of the register class. The
21 // name of the register does not matter.
22 def I1 : PatLeaf<(i1 PredRegs:$R)>;
23 def I32 : PatLeaf<(i32 IntRegs:$R)>;
24 def I64 : PatLeaf<(i64 DoubleRegs:$R)>;
25 def F32 : PatLeaf<(f32 IntRegs:$R)>;
26 def F64 : PatLeaf<(f64 DoubleRegs:$R)>;
28 // Pattern fragments to extract the low and high subregisters from a
30 def LoReg: OutPatFrag<(ops node:$Rs),
31 (EXTRACT_SUBREG (i64 $Rs), subreg_loreg)>;
32 def HiReg: OutPatFrag<(ops node:$Rs),
33 (EXTRACT_SUBREG (i64 $Rs), subreg_hireg)>;
35 // SDNode for converting immediate C to C-1.
36 def DEC_CONST_SIGNED : SDNodeXForm<imm, [{
37 // Return the byte immediate const-1 as an SDNode.
38 int32_t imm = N->getSExtValue();
39 return XformSToSM1Imm(imm);
42 // SDNode for converting immediate C to C-2.
43 def DEC2_CONST_SIGNED : SDNodeXForm<imm, [{
44 // Return the byte immediate const-2 as an SDNode.
45 int32_t imm = N->getSExtValue();
46 return XformSToSM2Imm(imm);
49 // SDNode for converting immediate C to C-3.
50 def DEC3_CONST_SIGNED : SDNodeXForm<imm, [{
51 // Return the byte immediate const-3 as an SDNode.
52 int32_t imm = N->getSExtValue();
53 return XformSToSM3Imm(imm);
56 // SDNode for converting immediate C to C-1.
57 def DEC_CONST_UNSIGNED : SDNodeXForm<imm, [{
58 // Return the byte immediate const-1 as an SDNode.
59 uint32_t imm = N->getZExtValue();
60 return XformUToUM1Imm(imm);
63 //===----------------------------------------------------------------------===//
65 //===----------------------------------------------------------------------===//
67 //===----------------------------------------------------------------------===//
68 let hasSideEffects = 0, isCompare = 1, InputType = "imm", isExtendable = 1,
70 class T_CMP <string mnemonic, bits<2> MajOp, bit isNot, Operand ImmOp>
71 : ALU32Inst <(outs PredRegs:$dst),
72 (ins IntRegs:$src1, ImmOp:$src2),
73 "$dst = "#!if(isNot, "!","")#mnemonic#"($src1, #$src2)",
74 [], "",ALU32_2op_tc_2early_SLOT0123 >, ImmRegRel {
78 let CextOpcode = mnemonic;
79 let opExtentBits = !if(!eq(mnemonic, "cmp.gtu"), 9, 10);
80 let isExtentSigned = !if(!eq(mnemonic, "cmp.gtu"), 0, 1);
84 let Inst{27-24} = 0b0101;
85 let Inst{23-22} = MajOp;
86 let Inst{21} = !if(!eq(mnemonic, "cmp.gtu"), 0, src2{9});
87 let Inst{20-16} = src1;
88 let Inst{13-5} = src2{8-0};
94 let isCodeGenOnly = 0 in {
95 def C2_cmpeqi : T_CMP <"cmp.eq", 0b00, 0, s10Ext>;
96 def C2_cmpgti : T_CMP <"cmp.gt", 0b01, 0, s10Ext>;
97 def C2_cmpgtui : T_CMP <"cmp.gtu", 0b10, 0, u9Ext>;
100 class T_CMP_pat <InstHexagon MI, PatFrag OpNode, PatLeaf ImmPred>
101 : Pat<(i1 (OpNode (i32 IntRegs:$src1), ImmPred:$src2)),
102 (MI IntRegs:$src1, ImmPred:$src2)>;
104 def : T_CMP_pat <C2_cmpeqi, seteq, s10ImmPred>;
105 def : T_CMP_pat <C2_cmpgti, setgt, s10ImmPred>;
106 def : T_CMP_pat <C2_cmpgtui, setugt, u9ImmPred>;
108 //===----------------------------------------------------------------------===//
110 //===----------------------------------------------------------------------===//
111 def SDTHexagonI64I32I32 : SDTypeProfile<1, 2,
112 [SDTCisVT<0, i64>, SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
114 def HexagonCOMBINE : SDNode<"HexagonISD::COMBINE", SDTHexagonI64I32I32>;
116 let hasSideEffects = 0, hasNewValue = 1, InputType = "reg" in
117 class T_ALU32_3op<string mnemonic, bits<3> MajOp, bits<3> MinOp, bit OpsRev,
119 : ALU32_rr<(outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt),
120 "$Rd = "#mnemonic#"($Rs, $Rt)",
121 [], "", ALU32_3op_tc_1_SLOT0123>, ImmRegRel, PredRel {
122 let isCommutable = IsComm;
123 let BaseOpcode = mnemonic#_rr;
124 let CextOpcode = mnemonic;
132 let Inst{26-24} = MajOp;
133 let Inst{23-21} = MinOp;
134 let Inst{20-16} = !if(OpsRev,Rt,Rs);
135 let Inst{12-8} = !if(OpsRev,Rs,Rt);
139 let hasSideEffects = 0, hasNewValue = 1 in
140 class T_ALU32_3op_pred<string mnemonic, bits<3> MajOp, bits<3> MinOp,
141 bit OpsRev, bit PredNot, bit PredNew>
142 : ALU32_rr<(outs IntRegs:$Rd), (ins PredRegs:$Pu, IntRegs:$Rs, IntRegs:$Rt),
143 "if ("#!if(PredNot,"!","")#"$Pu"#!if(PredNew,".new","")#") "#
144 "$Rd = "#mnemonic#"($Rs, $Rt)",
145 [], "", ALU32_3op_tc_1_SLOT0123>, ImmRegRel, PredNewRel {
146 let isPredicated = 1;
147 let isPredicatedFalse = PredNot;
148 let isPredicatedNew = PredNew;
149 let BaseOpcode = mnemonic#_rr;
150 let CextOpcode = mnemonic;
159 let Inst{26-24} = MajOp;
160 let Inst{23-21} = MinOp;
161 let Inst{20-16} = !if(OpsRev,Rt,Rs);
162 let Inst{13} = PredNew;
163 let Inst{12-8} = !if(OpsRev,Rs,Rt);
164 let Inst{7} = PredNot;
169 class T_ALU32_combineh<string Op1, string Op2, bits<3> MajOp, bits<3> MinOp,
171 : T_ALU32_3op<"", MajOp, MinOp, OpsRev, 0> {
172 let AsmString = "$Rd = combine($Rs"#Op1#", $Rt"#Op2#")";
175 let isCodeGenOnly = 0 in {
176 def A2_combine_hh : T_ALU32_combineh<".h", ".h", 0b011, 0b100, 1>;
177 def A2_combine_hl : T_ALU32_combineh<".h", ".l", 0b011, 0b101, 1>;
178 def A2_combine_lh : T_ALU32_combineh<".l", ".h", 0b011, 0b110, 1>;
179 def A2_combine_ll : T_ALU32_combineh<".l", ".l", 0b011, 0b111, 1>;
182 class T_ALU32_3op_sfx<string mnemonic, string suffix, bits<3> MajOp,
183 bits<3> MinOp, bit OpsRev, bit IsComm>
184 : T_ALU32_3op<"", MajOp, MinOp, OpsRev, IsComm> {
185 let AsmString = "$Rd = "#mnemonic#"($Rs, $Rt)"#suffix;
188 let isCodeGenOnly = 0 in {
189 def A2_svaddh : T_ALU32_3op<"vaddh", 0b110, 0b000, 0, 1>;
190 def A2_svsubh : T_ALU32_3op<"vsubh", 0b110, 0b100, 1, 0>;
193 let Defs = [USR_OVF], Itinerary = ALU32_3op_tc_2_SLOT0123,
194 isCodeGenOnly = 0 in {
195 def A2_svaddhs : T_ALU32_3op_sfx<"vaddh", ":sat", 0b110, 0b001, 0, 1>;
196 def A2_addsat : T_ALU32_3op_sfx<"add", ":sat", 0b110, 0b010, 0, 1>;
197 def A2_svadduhs : T_ALU32_3op_sfx<"vadduh", ":sat", 0b110, 0b011, 0, 1>;
198 def A2_svsubhs : T_ALU32_3op_sfx<"vsubh", ":sat", 0b110, 0b101, 1, 0>;
199 def A2_subsat : T_ALU32_3op_sfx<"sub", ":sat", 0b110, 0b110, 1, 0>;
200 def A2_svsubuhs : T_ALU32_3op_sfx<"vsubuh", ":sat", 0b110, 0b111, 1, 0>;
203 let Itinerary = ALU32_3op_tc_2_SLOT0123, isCodeGenOnly = 0 in
204 def A2_svavghs : T_ALU32_3op_sfx<"vavgh", ":rnd", 0b111, 0b001, 0, 1>;
206 let isCodeGenOnly = 0 in {
207 def A2_svavgh : T_ALU32_3op<"vavgh", 0b111, 0b000, 0, 1>;
208 def A2_svnavgh : T_ALU32_3op<"vnavgh", 0b111, 0b011, 1, 0>;
211 multiclass T_ALU32_3op_p<string mnemonic, bits<3> MajOp, bits<3> MinOp,
213 def t : T_ALU32_3op_pred<mnemonic, MajOp, MinOp, OpsRev, 0, 0>;
214 def f : T_ALU32_3op_pred<mnemonic, MajOp, MinOp, OpsRev, 1, 0>;
215 def tnew : T_ALU32_3op_pred<mnemonic, MajOp, MinOp, OpsRev, 0, 1>;
216 def fnew : T_ALU32_3op_pred<mnemonic, MajOp, MinOp, OpsRev, 1, 1>;
219 multiclass T_ALU32_3op_A2<string mnemonic, bits<3> MajOp, bits<3> MinOp,
220 bit OpsRev, bit IsComm> {
221 let isPredicable = 1 in
222 def A2_#NAME : T_ALU32_3op <mnemonic, MajOp, MinOp, OpsRev, IsComm>;
223 defm A2_p#NAME : T_ALU32_3op_p<mnemonic, MajOp, MinOp, OpsRev>;
226 let isCodeGenOnly = 0 in {
227 defm add : T_ALU32_3op_A2<"add", 0b011, 0b000, 0, 1>;
228 defm and : T_ALU32_3op_A2<"and", 0b001, 0b000, 0, 1>;
229 defm or : T_ALU32_3op_A2<"or", 0b001, 0b001, 0, 1>;
230 defm sub : T_ALU32_3op_A2<"sub", 0b011, 0b001, 1, 0>;
231 defm xor : T_ALU32_3op_A2<"xor", 0b001, 0b011, 0, 1>;
234 // Pats for instruction selection.
235 class BinOp32_pat<SDNode Op, InstHexagon MI, ValueType ResT>
236 : Pat<(ResT (Op (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))),
237 (ResT (MI IntRegs:$Rs, IntRegs:$Rt))>;
239 def: BinOp32_pat<add, A2_add, i32>;
240 def: BinOp32_pat<and, A2_and, i32>;
241 def: BinOp32_pat<or, A2_or, i32>;
242 def: BinOp32_pat<sub, A2_sub, i32>;
243 def: BinOp32_pat<xor, A2_xor, i32>;
245 // A few special cases producing register pairs:
246 let OutOperandList = (outs DoubleRegs:$Rd), hasNewValue = 0,
247 isCodeGenOnly = 0 in {
248 def S2_packhl : T_ALU32_3op <"packhl", 0b101, 0b100, 0, 0>;
250 let isPredicable = 1 in
251 def A2_combinew : T_ALU32_3op <"combine", 0b101, 0b000, 0, 0>;
253 // Conditional combinew uses "newt/f" instead of "t/fnew".
254 def C2_ccombinewt : T_ALU32_3op_pred<"combine", 0b101, 0b000, 0, 0, 0>;
255 def C2_ccombinewf : T_ALU32_3op_pred<"combine", 0b101, 0b000, 0, 1, 0>;
256 def C2_ccombinewnewt : T_ALU32_3op_pred<"combine", 0b101, 0b000, 0, 0, 1>;
257 def C2_ccombinewnewf : T_ALU32_3op_pred<"combine", 0b101, 0b000, 0, 1, 1>;
260 let hasSideEffects = 0, hasNewValue = 1, isCompare = 1, InputType = "reg" in
261 class T_ALU32_3op_cmp<string mnemonic, bits<2> MinOp, bit IsNeg, bit IsComm>
262 : ALU32_rr<(outs PredRegs:$Pd), (ins IntRegs:$Rs, IntRegs:$Rt),
263 "$Pd = "#mnemonic#"($Rs, $Rt)",
264 [], "", ALU32_3op_tc_1_SLOT0123>, ImmRegRel {
265 let CextOpcode = mnemonic;
266 let isCommutable = IsComm;
272 let Inst{27-24} = 0b0010;
273 let Inst{22-21} = MinOp;
274 let Inst{20-16} = Rs;
277 let Inst{3-2} = 0b00;
281 let Itinerary = ALU32_3op_tc_2early_SLOT0123, isCodeGenOnly = 0 in {
282 def C2_cmpeq : T_ALU32_3op_cmp< "cmp.eq", 0b00, 0, 1>;
283 def C2_cmpgt : T_ALU32_3op_cmp< "cmp.gt", 0b10, 0, 0>;
284 def C2_cmpgtu : T_ALU32_3op_cmp< "cmp.gtu", 0b11, 0, 0>;
287 // Patfrag to convert the usual comparison patfrags (e.g. setlt) to ones
288 // that reverse the order of the operands.
289 class RevCmp<PatFrag F> : PatFrag<(ops node:$rhs, node:$lhs), F.Fragment>;
291 // Pats for compares. They use PatFrags as operands, not SDNodes,
292 // since seteq/setgt/etc. are defined as ParFrags.
293 class T_cmp32_rr_pat<InstHexagon MI, PatFrag Op, ValueType VT>
294 : Pat<(VT (Op (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))),
295 (VT (MI IntRegs:$Rs, IntRegs:$Rt))>;
297 def: T_cmp32_rr_pat<C2_cmpeq, seteq, i1>;
298 def: T_cmp32_rr_pat<C2_cmpgt, setgt, i1>;
299 def: T_cmp32_rr_pat<C2_cmpgtu, setugt, i1>;
301 def: T_cmp32_rr_pat<C2_cmpgt, RevCmp<setlt>, i1>;
302 def: T_cmp32_rr_pat<C2_cmpgtu, RevCmp<setult>, i1>;
304 let CextOpcode = "MUX", InputType = "reg", hasNewValue = 1,
306 def C2_mux: ALU32_rr<(outs IntRegs:$Rd),
307 (ins PredRegs:$Pu, IntRegs:$Rs, IntRegs:$Rt),
308 "$Rd = mux($Pu, $Rs, $Rt)", [], "", ALU32_3op_tc_1_SLOT0123>, ImmRegRel {
314 let CextOpcode = "mux";
315 let InputType = "reg";
316 let hasSideEffects = 0;
319 let Inst{27-24} = 0b0100;
320 let Inst{20-16} = Rs;
326 def: Pat<(i32 (select (i1 PredRegs:$Pu), (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))),
327 (C2_mux PredRegs:$Pu, IntRegs:$Rs, IntRegs:$Rt)>;
329 // Combines the two immediates into a double register.
330 // Increase complexity to make it greater than any complexity of a combine
331 // that involves a register.
333 let isReMaterializable = 1, isMoveImm = 1, isAsCheapAsAMove = 1,
334 isExtentSigned = 1, isExtendable = 1, opExtentBits = 8, opExtendable = 1,
335 AddedComplexity = 75, isCodeGenOnly = 0 in
336 def A2_combineii: ALU32Inst <(outs DoubleRegs:$Rdd), (ins s8Ext:$s8, s8Imm:$S8),
337 "$Rdd = combine(#$s8, #$S8)",
338 [(set (i64 DoubleRegs:$Rdd),
339 (i64 (HexagonCOMBINE(i32 s8ExtPred:$s8), (i32 s8ImmPred:$S8))))]> {
345 let Inst{27-23} = 0b11000;
346 let Inst{22-16} = S8{7-1};
347 let Inst{13} = S8{0};
352 //===----------------------------------------------------------------------===//
353 // Template class for predicated ADD of a reg and an Immediate value.
354 //===----------------------------------------------------------------------===//
355 let hasNewValue = 1, hasSideEffects = 0 in
356 class T_Addri_Pred <bit PredNot, bit PredNew>
357 : ALU32_ri <(outs IntRegs:$Rd),
358 (ins PredRegs:$Pu, IntRegs:$Rs, s8Ext:$s8),
359 !if(PredNot, "if (!$Pu", "if ($Pu")#!if(PredNew,".new) $Rd = ",
360 ") $Rd = ")#"add($Rs, #$s8)"> {
366 let isPredicatedNew = PredNew;
369 let Inst{27-24} = 0b0100;
370 let Inst{23} = PredNot;
371 let Inst{22-21} = Pu;
372 let Inst{20-16} = Rs;
373 let Inst{13} = PredNew;
378 //===----------------------------------------------------------------------===//
379 // A2_addi: Add a signed immediate to a register.
380 //===----------------------------------------------------------------------===//
381 let hasNewValue = 1, hasSideEffects = 0 in
382 class T_Addri <Operand immOp, list<dag> pattern = [] >
383 : ALU32_ri <(outs IntRegs:$Rd),
384 (ins IntRegs:$Rs, immOp:$s16),
385 "$Rd = add($Rs, #$s16)", pattern,
386 //[(set (i32 IntRegs:$Rd), (add (i32 IntRegs:$Rs), (s16ExtPred:$s16)))],
387 "", ALU32_ADDI_tc_1_SLOT0123> {
394 let Inst{27-21} = s16{15-9};
395 let Inst{20-16} = Rs;
396 let Inst{13-5} = s16{8-0};
400 //===----------------------------------------------------------------------===//
401 // Multiclass for ADD of a register and an immediate value.
402 //===----------------------------------------------------------------------===//
403 multiclass Addri_Pred<string mnemonic, bit PredNot> {
404 let isPredicatedFalse = PredNot in {
405 def _c#NAME : T_Addri_Pred<PredNot, 0>;
407 def _cdn#NAME : T_Addri_Pred<PredNot, 1>;
411 let isExtendable = 1, InputType = "imm" in
412 multiclass Addri_base<string mnemonic, SDNode OpNode> {
413 let CextOpcode = mnemonic, BaseOpcode = mnemonic#_ri in {
414 let opExtendable = 2, isExtentSigned = 1, opExtentBits = 16,
416 def NAME : T_Addri< s16Ext, // Rd=add(Rs,#s16)
417 [(set (i32 IntRegs:$Rd),
418 (add IntRegs:$Rs, s16ExtPred:$s16))]>;
420 let opExtendable = 3, isExtentSigned = 1, opExtentBits = 8,
421 hasSideEffects = 0, isPredicated = 1 in {
422 defm Pt : Addri_Pred<mnemonic, 0>;
423 defm NotPt : Addri_Pred<mnemonic, 1>;
428 let isCodeGenOnly = 0 in
429 defm ADD_ri : Addri_base<"add", add>, ImmRegRel, PredNewRel;
431 //===----------------------------------------------------------------------===//
432 // Template class used for the following ALU32 instructions.
435 //===----------------------------------------------------------------------===//
436 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 10,
437 InputType = "imm", hasNewValue = 1 in
438 class T_ALU32ri_logical <string mnemonic, SDNode OpNode, bits<2> MinOp>
439 : ALU32_ri <(outs IntRegs:$Rd),
440 (ins IntRegs:$Rs, s10Ext:$s10),
441 "$Rd = "#mnemonic#"($Rs, #$s10)" ,
442 [(set (i32 IntRegs:$Rd), (OpNode (i32 IntRegs:$Rs), s10ExtPred:$s10))]> {
446 let CextOpcode = mnemonic;
450 let Inst{27-24} = 0b0110;
451 let Inst{23-22} = MinOp;
452 let Inst{21} = s10{9};
453 let Inst{20-16} = Rs;
454 let Inst{13-5} = s10{8-0};
458 let isCodeGenOnly = 0 in {
459 def OR_ri : T_ALU32ri_logical<"or", or, 0b10>, ImmRegRel;
460 def AND_ri : T_ALU32ri_logical<"and", and, 0b00>, ImmRegRel;
463 // Subtract register from immediate
464 // Rd32=sub(#s10,Rs32)
465 let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 10,
466 CextOpcode = "sub", InputType = "imm", hasNewValue = 1, isCodeGenOnly = 0 in
467 def SUB_ri: ALU32_ri <(outs IntRegs:$Rd), (ins s10Ext:$s10, IntRegs:$Rs),
468 "$Rd = sub(#$s10, $Rs)" ,
469 [(set IntRegs:$Rd, (sub s10ExtPred:$s10, IntRegs:$Rs))] > ,
477 let Inst{27-22} = 0b011001;
478 let Inst{21} = s10{9};
479 let Inst{20-16} = Rs;
480 let Inst{13-5} = s10{8-0};
485 let hasSideEffects = 0, isCodeGenOnly = 0 in
486 def A2_nop: ALU32Inst <(outs), (ins), "nop" > {
488 let Inst{27-24} = 0b1111;
490 // Rd = not(Rs) gets mapped to Rd=sub(#-1, Rs).
491 def : Pat<(not (i32 IntRegs:$src1)),
492 (SUB_ri -1, (i32 IntRegs:$src1))>;
494 let hasSideEffects = 0, hasNewValue = 1 in
495 class T_tfr16<bit isHi>
496 : ALU32Inst <(outs IntRegs:$Rx), (ins IntRegs:$src1, u16Imm:$u16),
497 "$Rx"#!if(isHi, ".h", ".l")#" = #$u16",
498 [], "$src1 = $Rx" > {
503 let Inst{27-26} = 0b00;
504 let Inst{25-24} = !if(isHi, 0b10, 0b01);
505 let Inst{23-22} = u16{15-14};
507 let Inst{20-16} = Rx;
508 let Inst{13-0} = u16{13-0};
511 let isCodeGenOnly = 0 in {
512 def A2_tfril: T_tfr16<0>;
513 def A2_tfrih: T_tfr16<1>;
516 // Conditional transfer is an alias to conditional "Rd = add(Rs, #0)".
517 let isPredicated = 1, hasNewValue = 1, opNewValue = 0 in
518 class T_tfr_pred<bit isPredNot, bit isPredNew>
519 : ALU32Inst<(outs IntRegs:$dst),
520 (ins PredRegs:$src1, IntRegs:$src2),
521 "if ("#!if(isPredNot, "!", "")#
522 "$src1"#!if(isPredNew, ".new", "")#
528 let isPredicatedFalse = isPredNot;
529 let isPredicatedNew = isPredNew;
532 let Inst{27-24} = 0b0100;
533 let Inst{23} = isPredNot;
534 let Inst{13} = isPredNew;
537 let Inst{22-21} = src1;
538 let Inst{20-16} = src2;
541 let isPredicable = 1 in
542 class T_tfr : ALU32Inst<(outs IntRegs:$dst), (ins IntRegs:$src),
549 let Inst{27-21} = 0b0000011;
550 let Inst{20-16} = src;
555 let InputType = "reg", hasNewValue = 1, hasSideEffects = 0 in
556 multiclass tfr_base<string CextOp> {
557 let CextOpcode = CextOp, BaseOpcode = CextOp in {
561 def t : T_tfr_pred<0, 0>;
562 def f : T_tfr_pred<1, 0>;
564 def tnew : T_tfr_pred<0, 1>;
565 def fnew : T_tfr_pred<1, 1>;
569 // Assembler mapped to C2_ccombinew[t|f|newt|newf].
570 // Please don't add bits to this instruction as it'll be converted into
571 // 'combine' before object code emission.
572 let isPredicated = 1 in
573 class T_tfrp_pred<bit PredNot, bit PredNew>
574 : ALU32_rr <(outs DoubleRegs:$dst),
575 (ins PredRegs:$src1, DoubleRegs:$src2),
576 "if ("#!if(PredNot, "!", "")#"$src1"
577 #!if(PredNew, ".new", "")#") $dst = $src2" > {
578 let isPredicatedFalse = PredNot;
579 let isPredicatedNew = PredNew;
582 // Assembler mapped to A2_combinew.
583 // Please don't add bits to this instruction as it'll be converted into
584 // 'combine' before object code emission.
585 class T_tfrp : ALU32Inst <(outs DoubleRegs:$dst),
586 (ins DoubleRegs:$src),
589 let hasSideEffects = 0 in
590 multiclass TFR64_base<string BaseName> {
591 let BaseOpcode = BaseName in {
592 let isPredicable = 1 in
595 def t : T_tfrp_pred <0, 0>;
596 def f : T_tfrp_pred <1, 0>;
598 def tnew : T_tfrp_pred <0, 1>;
599 def fnew : T_tfrp_pred <1, 1>;
603 let InputType = "imm", isExtendable = 1, isExtentSigned = 1, opExtentBits = 12,
604 isMoveImm = 1, opExtendable = 2, BaseOpcode = "TFRI", CextOpcode = "TFR",
605 hasSideEffects = 0, isPredicated = 1, hasNewValue = 1 in
606 class T_TFRI_Pred<bit PredNot, bit PredNew>
607 : ALU32_ri<(outs IntRegs:$Rd), (ins PredRegs:$Pu, s12Ext:$s12),
608 "if ("#!if(PredNot,"!","")#"$Pu"#!if(PredNew,".new","")#") $Rd = #$s12",
609 [], "", ALU32_2op_tc_1_SLOT0123>, ImmRegRel, PredNewRel {
610 let isPredicatedFalse = PredNot;
611 let isPredicatedNew = PredNew;
618 let Inst{27-24} = 0b1110;
619 let Inst{23} = PredNot;
620 let Inst{22-21} = Pu;
622 let Inst{19-16,12-5} = s12;
623 let Inst{13} = PredNew;
627 let isCodeGenOnly = 0 in {
628 def C2_cmoveit : T_TFRI_Pred<0, 0>;
629 def C2_cmoveif : T_TFRI_Pred<1, 0>;
630 def C2_cmovenewit : T_TFRI_Pred<0, 1>;
631 def C2_cmovenewif : T_TFRI_Pred<1, 1>;
634 let InputType = "imm", isExtendable = 1, isExtentSigned = 1,
635 CextOpcode = "TFR", BaseOpcode = "TFRI", hasNewValue = 1, opNewValue = 0,
636 isAsCheapAsAMove = 1 , opExtendable = 1, opExtentBits = 16, isMoveImm = 1,
637 isPredicated = 0, isPredicable = 1, isReMaterializable = 1,
639 def A2_tfrsi : ALU32Inst<(outs IntRegs:$Rd), (ins s16Ext:$s16), "$Rd = #$s16",
640 [(set (i32 IntRegs:$Rd), s16ExtPred:$s16)], "", ALU32_2op_tc_1_SLOT0123>,
646 let Inst{27-24} = 0b1000;
647 let Inst{23-22,20-16,13-5} = s16;
651 let isCodeGenOnly = 0 in
652 defm A2_tfr : tfr_base<"TFR">, ImmRegRel, PredNewRel;
653 defm A2_tfrp : TFR64_base<"TFR64">, PredNewRel;
656 let isReMaterializable = 1, isMoveImm = 1, isAsCheapAsAMove = 1 in
657 def A2_tfrpi : ALU64_rr<(outs DoubleRegs:$dst), (ins s8Imm64:$src1),
659 [(set (i64 DoubleRegs:$dst), s8Imm64Pred:$src1)]>;
661 // TODO: see if this instruction can be deleted..
662 let isExtendable = 1, opExtendable = 1, opExtentBits = 6 in
663 def TFRI64_V4 : ALU64_rr<(outs DoubleRegs:$dst), (ins u6Ext:$src1),
666 //===----------------------------------------------------------------------===//
668 //===----------------------------------------------------------------------===//
671 //===----------------------------------------------------------------------===//
673 //===----------------------------------------------------------------------===//
674 // Scalar mux register immediate.
675 let hasSideEffects = 0, isExtentSigned = 1, CextOpcode = "MUX",
676 InputType = "imm", hasNewValue = 1, isExtendable = 1, opExtentBits = 8 in
677 class T_MUX1 <bit MajOp, dag ins, string AsmStr>
678 : ALU32Inst <(outs IntRegs:$Rd), ins, AsmStr>, ImmRegRel {
685 let Inst{27-24} = 0b0011;
686 let Inst{23} = MajOp;
687 let Inst{22-21} = Pu;
688 let Inst{20-16} = Rs;
694 let opExtendable = 2, isCodeGenOnly = 0 in
695 def C2_muxri : T_MUX1<0b1, (ins PredRegs:$Pu, s8Ext:$s8, IntRegs:$Rs),
696 "$Rd = mux($Pu, #$s8, $Rs)">;
698 let opExtendable = 3, isCodeGenOnly = 0 in
699 def C2_muxir : T_MUX1<0b0, (ins PredRegs:$Pu, IntRegs:$Rs, s8Ext:$s8),
700 "$Rd = mux($Pu, $Rs, #$s8)">;
702 def : Pat<(i32 (select I1:$Pu, s8ExtPred:$s8, I32:$Rs)),
703 (C2_muxri I1:$Pu, s8ExtPred:$s8, I32:$Rs)>;
705 def : Pat<(i32 (select I1:$Pu, I32:$Rs, s8ExtPred:$s8)),
706 (C2_muxir I1:$Pu, I32:$Rs, s8ExtPred:$s8)>;
708 // C2_muxii: Scalar mux immediates.
709 let isExtentSigned = 1, hasNewValue = 1, isExtendable = 1,
710 opExtentBits = 8, opExtendable = 2, isCodeGenOnly = 0 in
711 def C2_muxii: ALU32Inst <(outs IntRegs:$Rd),
712 (ins PredRegs:$Pu, s8Ext:$s8, s8Imm:$S8),
713 "$Rd = mux($Pu, #$s8, #$S8)" ,
714 [(set (i32 IntRegs:$Rd),
715 (i32 (select I1:$Pu, s8ExtPred:$s8, s8ImmPred:$S8)))] > {
723 let Inst{27-25} = 0b101;
724 let Inst{24-23} = Pu;
725 let Inst{22-16} = S8{7-1};
726 let Inst{13} = S8{0};
731 //===----------------------------------------------------------------------===//
732 // template class for non-predicated alu32_2op instructions
733 // - aslh, asrh, sxtb, sxth, zxth
734 //===----------------------------------------------------------------------===//
735 let hasNewValue = 1, opNewValue = 0 in
736 class T_ALU32_2op <string mnemonic, bits<3> minOp> :
737 ALU32Inst < (outs IntRegs:$Rd), (ins IntRegs:$Rs),
738 "$Rd = "#mnemonic#"($Rs)", [] > {
744 let Inst{27-24} = 0b0000;
745 let Inst{23-21} = minOp;
748 let Inst{20-16} = Rs;
751 //===----------------------------------------------------------------------===//
752 // template class for predicated alu32_2op instructions
753 // - aslh, asrh, sxtb, sxth, zxtb, zxth
754 //===----------------------------------------------------------------------===//
755 let hasSideEffects = 0, validSubTargets = HasV4SubT,
756 hasNewValue = 1, opNewValue = 0 in
757 class T_ALU32_2op_Pred <string mnemonic, bits<3> minOp, bit isPredNot,
759 ALU32Inst <(outs IntRegs:$Rd), (ins PredRegs:$Pu, IntRegs:$Rs),
760 !if(isPredNot, "if (!$Pu", "if ($Pu")
761 #!if(isPredNew, ".new) ",") ")#"$Rd = "#mnemonic#"($Rs)"> {
768 let Inst{27-24} = 0b0000;
769 let Inst{23-21} = minOp;
771 let Inst{11} = isPredNot;
772 let Inst{10} = isPredNew;
775 let Inst{20-16} = Rs;
778 multiclass ALU32_2op_Pred<string mnemonic, bits<3> minOp, bit PredNot> {
779 let isPredicatedFalse = PredNot in {
780 def NAME : T_ALU32_2op_Pred<mnemonic, minOp, PredNot, 0>;
783 let isPredicatedNew = 1 in
784 def NAME#new : T_ALU32_2op_Pred<mnemonic, minOp, PredNot, 1>;
788 multiclass ALU32_2op_base<string mnemonic, bits<3> minOp> {
789 let BaseOpcode = mnemonic in {
790 let isPredicable = 1, hasSideEffects = 0 in
791 def A2_#NAME : T_ALU32_2op<mnemonic, minOp>;
793 let validSubTargets = HasV4SubT, isPredicated = 1, hasSideEffects = 0 in {
794 defm A4_p#NAME#t : ALU32_2op_Pred<mnemonic, minOp, 0>;
795 defm A4_p#NAME#f : ALU32_2op_Pred<mnemonic, minOp, 1>;
800 let isCodeGenOnly = 0 in {
801 defm aslh : ALU32_2op_base<"aslh", 0b000>, PredNewRel;
802 defm asrh : ALU32_2op_base<"asrh", 0b001>, PredNewRel;
803 defm sxtb : ALU32_2op_base<"sxtb", 0b101>, PredNewRel;
804 defm sxth : ALU32_2op_base<"sxth", 0b111>, PredNewRel;
805 defm zxth : ALU32_2op_base<"zxth", 0b110>, PredNewRel;
808 // Rd=zxtb(Rs): assembler mapped to Rd=and(Rs,#255).
809 // Compiler would want to generate 'zxtb' instead of 'and' becuase 'zxtb' has
810 // predicated forms while 'and' doesn't. Since integrated assembler can't
811 // handle 'mapped' instructions, we need to encode 'zxtb' same as 'and' where
812 // immediate operand is set to '255'.
814 let hasNewValue = 1, opNewValue = 0 in
815 class T_ZXTB: ALU32Inst < (outs IntRegs:$Rd), (ins IntRegs:$Rs),
816 "$Rd = zxtb($Rs)", [] > { // Rd = and(Rs,255)
823 let Inst{27-22} = 0b011000;
825 let Inst{20-16} = Rs;
826 let Inst{21} = s10{9};
827 let Inst{13-5} = s10{8-0};
830 //Rd=zxtb(Rs): assembler mapped to "Rd=and(Rs,#255)
831 multiclass ZXTB_base <string mnemonic, bits<3> minOp> {
832 let BaseOpcode = mnemonic in {
833 let isPredicable = 1, hasSideEffects = 0 in
834 def A2_#NAME : T_ZXTB;
836 let validSubTargets = HasV4SubT, isPredicated = 1, hasSideEffects = 0 in {
837 defm A4_p#NAME#t : ALU32_2op_Pred<mnemonic, minOp, 0>;
838 defm A4_p#NAME#f : ALU32_2op_Pred<mnemonic, minOp, 1>;
843 let isCodeGenOnly=0 in
844 defm zxtb : ZXTB_base<"zxtb",0b100>, PredNewRel;
846 def: Pat<(shl I32:$src1, (i32 16)), (A2_aslh I32:$src1)>;
847 def: Pat<(sra I32:$src1, (i32 16)), (A2_asrh I32:$src1)>;
848 def: Pat<(sext_inreg I32:$src1, i8), (A2_sxtb I32:$src1)>;
849 def: Pat<(sext_inreg I32:$src1, i16), (A2_sxth I32:$src1)>;
851 //===----------------------------------------------------------------------===//
852 // Template class for vector add and avg
853 //===----------------------------------------------------------------------===//
855 class T_VectALU_64 <string opc, bits<3> majOp, bits<3> minOp,
856 bit isSat, bit isRnd, bit isCrnd, bit SwapOps >
857 : ALU64_rr < (outs DoubleRegs:$Rdd),
858 (ins DoubleRegs:$Rss, DoubleRegs:$Rtt),
859 "$Rdd = "#opc#"($Rss, $Rtt)"#!if(isRnd, ":rnd", "")
860 #!if(isCrnd,":crnd","")
861 #!if(isSat, ":sat", ""),
862 [], "", ALU64_tc_2_SLOT23 > {
869 let Inst{27-24} = 0b0011;
870 let Inst{23-21} = majOp;
871 let Inst{20-16} = !if (SwapOps, Rtt, Rss);
872 let Inst{12-8} = !if (SwapOps, Rss, Rtt);
873 let Inst{7-5} = minOp;
877 // ALU64 - Vector add
878 // Rdd=vadd[u][bhw](Rss,Rtt)
879 let Itinerary = ALU64_tc_1_SLOT23 in {
880 def A2_vaddub : T_VectALU_64 < "vaddub", 0b000, 0b000, 0, 0, 0, 0>;
881 def A2_vaddh : T_VectALU_64 < "vaddh", 0b000, 0b010, 0, 0, 0, 0>;
882 def A2_vaddw : T_VectALU_64 < "vaddw", 0b000, 0b101, 0, 0, 0, 0>;
885 // Rdd=vadd[u][bhw](Rss,Rtt):sat
886 let Defs = [USR_OVF] in {
887 def A2_vaddubs : T_VectALU_64 < "vaddub", 0b000, 0b001, 1, 0, 0, 0>;
888 def A2_vaddhs : T_VectALU_64 < "vaddh", 0b000, 0b011, 1, 0, 0, 0>;
889 def A2_vadduhs : T_VectALU_64 < "vadduh", 0b000, 0b100, 1, 0, 0, 0>;
890 def A2_vaddws : T_VectALU_64 < "vaddw", 0b000, 0b110, 1, 0, 0, 0>;
893 // ALU64 - Vector average
894 // Rdd=vavg[u][bhw](Rss,Rtt)
895 let Itinerary = ALU64_tc_1_SLOT23 in {
896 def A2_vavgub : T_VectALU_64 < "vavgub", 0b010, 0b000, 0, 0, 0, 0>;
897 def A2_vavgh : T_VectALU_64 < "vavgh", 0b010, 0b010, 0, 0, 0, 0>;
898 def A2_vavguh : T_VectALU_64 < "vavguh", 0b010, 0b101, 0, 0, 0, 0>;
899 def A2_vavgw : T_VectALU_64 < "vavgw", 0b011, 0b000, 0, 0, 0, 0>;
900 def A2_vavguw : T_VectALU_64 < "vavguw", 0b011, 0b011, 0, 0, 0, 0>;
903 // Rdd=vavg[u][bhw](Rss,Rtt)[:rnd|:crnd]
904 def A2_vavgubr : T_VectALU_64 < "vavgub", 0b010, 0b001, 0, 1, 0, 0>;
905 def A2_vavghr : T_VectALU_64 < "vavgh", 0b010, 0b011, 0, 1, 0, 0>;
906 def A2_vavghcr : T_VectALU_64 < "vavgh", 0b010, 0b100, 0, 0, 1, 0>;
907 def A2_vavguhr : T_VectALU_64 < "vavguh", 0b010, 0b110, 0, 1, 0, 0>;
909 def A2_vavgwr : T_VectALU_64 < "vavgw", 0b011, 0b001, 0, 1, 0, 0>;
910 def A2_vavgwcr : T_VectALU_64 < "vavgw", 0b011, 0b010, 0, 0, 1, 0>;
911 def A2_vavguwr : T_VectALU_64 < "vavguw", 0b011, 0b100, 0, 1, 0, 0>;
913 // Rdd=vnavg[bh](Rss,Rtt)
914 let Itinerary = ALU64_tc_1_SLOT23 in {
915 def A2_vnavgh : T_VectALU_64 < "vnavgh", 0b100, 0b000, 0, 0, 0, 1>;
916 def A2_vnavgw : T_VectALU_64 < "vnavgw", 0b100, 0b011, 0, 0, 0, 1>;
919 // Rdd=vnavg[bh](Rss,Rtt)[:rnd|:crnd]:sat
920 let Defs = [USR_OVF] in {
921 def A2_vnavghr : T_VectALU_64 < "vnavgh", 0b100, 0b001, 1, 1, 0, 1>;
922 def A2_vnavghcr : T_VectALU_64 < "vnavgh", 0b100, 0b010, 1, 0, 1, 1>;
923 def A2_vnavgwr : T_VectALU_64 < "vnavgw", 0b100, 0b100, 1, 1, 0, 1>;
924 def A2_vnavgwcr : T_VectALU_64 < "vnavgw", 0b100, 0b110, 1, 0, 1, 1>;
927 // Rdd=vsub[u][bh](Rss,Rtt)
928 let Itinerary = ALU64_tc_1_SLOT23 in {
929 def A2_vsubub : T_VectALU_64 < "vsubub", 0b001, 0b000, 0, 0, 0, 1>;
930 def A2_vsubh : T_VectALU_64 < "vsubh", 0b001, 0b010, 0, 0, 0, 1>;
931 def A2_vsubw : T_VectALU_64 < "vsubw", 0b001, 0b101, 0, 0, 0, 1>;
934 // Rdd=vsub[u][bh](Rss,Rtt):sat
935 let Defs = [USR_OVF] in {
936 def A2_vsububs : T_VectALU_64 < "vsubub", 0b001, 0b001, 1, 0, 0, 1>;
937 def A2_vsubhs : T_VectALU_64 < "vsubh", 0b001, 0b011, 1, 0, 0, 1>;
938 def A2_vsubuhs : T_VectALU_64 < "vsubuh", 0b001, 0b100, 1, 0, 0, 1>;
939 def A2_vsubws : T_VectALU_64 < "vsubw", 0b001, 0b110, 1, 0, 0, 1>;
942 // Rdd=vmax[u][bhw](Rss,Rtt)
943 def A2_vmaxb : T_VectALU_64 < "vmaxb", 0b110, 0b110, 0, 0, 0, 1>;
944 def A2_vmaxub : T_VectALU_64 < "vmaxub", 0b110, 0b000, 0, 0, 0, 1>;
945 def A2_vmaxh : T_VectALU_64 < "vmaxh", 0b110, 0b001, 0, 0, 0, 1>;
946 def A2_vmaxuh : T_VectALU_64 < "vmaxuh", 0b110, 0b010, 0, 0, 0, 1>;
947 def A2_vmaxw : T_VectALU_64 < "vmaxw", 0b110, 0b011, 0, 0, 0, 1>;
948 def A2_vmaxuw : T_VectALU_64 < "vmaxuw", 0b101, 0b101, 0, 0, 0, 1>;
950 // Rdd=vmin[u][bhw](Rss,Rtt)
951 def A2_vminb : T_VectALU_64 < "vminb", 0b110, 0b111, 0, 0, 0, 1>;
952 def A2_vminub : T_VectALU_64 < "vminub", 0b101, 0b000, 0, 0, 0, 1>;
953 def A2_vminh : T_VectALU_64 < "vminh", 0b101, 0b001, 0, 0, 0, 1>;
954 def A2_vminuh : T_VectALU_64 < "vminuh", 0b101, 0b010, 0, 0, 0, 1>;
955 def A2_vminw : T_VectALU_64 < "vminw", 0b101, 0b011, 0, 0, 0, 1>;
956 def A2_vminuw : T_VectALU_64 < "vminuw", 0b101, 0b100, 0, 0, 0, 1>;
958 //===----------------------------------------------------------------------===//
959 // Template class for vector compare
960 //===----------------------------------------------------------------------===//
961 let hasSideEffects = 0 in
962 class T_vcmp <string Str, bits<4> minOp>
963 : ALU64_rr <(outs PredRegs:$Pd),
964 (ins DoubleRegs:$Rss, DoubleRegs:$Rtt),
965 "$Pd = "#Str#"($Rss, $Rtt)", [],
966 "", ALU64_tc_2early_SLOT23> {
973 let Inst{27-23} = 0b00100;
974 let Inst{13} = minOp{3};
975 let Inst{7-5} = minOp{2-0};
977 let Inst{20-16} = Rss;
978 let Inst{12-8} = Rtt;
981 class T_vcmp_pat<InstHexagon MI, PatFrag Op, ValueType T>
982 : Pat<(i1 (Op (T DoubleRegs:$Rss), (T DoubleRegs:$Rtt))),
983 (i1 (MI DoubleRegs:$Rss, DoubleRegs:$Rtt))>;
985 // Vector compare bytes
986 def A2_vcmpbeq : T_vcmp <"vcmpb.eq", 0b0110>;
987 def A2_vcmpbgtu : T_vcmp <"vcmpb.gtu", 0b0111>;
989 // Vector compare halfwords
990 def A2_vcmpheq : T_vcmp <"vcmph.eq", 0b0011>;
991 def A2_vcmphgt : T_vcmp <"vcmph.gt", 0b0100>;
992 def A2_vcmphgtu : T_vcmp <"vcmph.gtu", 0b0101>;
994 // Vector compare words
995 def A2_vcmpweq : T_vcmp <"vcmpw.eq", 0b0000>;
996 def A2_vcmpwgt : T_vcmp <"vcmpw.gt", 0b0001>;
997 def A2_vcmpwgtu : T_vcmp <"vcmpw.gtu", 0b0010>;
999 def: T_vcmp_pat<A2_vcmpbeq, seteq, v8i8>;
1000 def: T_vcmp_pat<A2_vcmpbgtu, setugt, v8i8>;
1001 def: T_vcmp_pat<A2_vcmpheq, seteq, v4i16>;
1002 def: T_vcmp_pat<A2_vcmphgt, setgt, v4i16>;
1003 def: T_vcmp_pat<A2_vcmphgtu, setugt, v4i16>;
1004 def: T_vcmp_pat<A2_vcmpweq, seteq, v2i32>;
1005 def: T_vcmp_pat<A2_vcmpwgt, setgt, v2i32>;
1006 def: T_vcmp_pat<A2_vcmpwgtu, setugt, v2i32>;
1008 //===----------------------------------------------------------------------===//
1010 //===----------------------------------------------------------------------===//
1013 //===----------------------------------------------------------------------===//
1015 //===----------------------------------------------------------------------===//
1017 //===----------------------------------------------------------------------===//
1019 //===----------------------------------------------------------------------===//
1022 //===----------------------------------------------------------------------===//
1024 //===----------------------------------------------------------------------===//// Add.
1025 //===----------------------------------------------------------------------===//
1027 // Add/Subtract halfword
1028 // Rd=add(Rt.L,Rs.[HL])[:sat]
1029 // Rd=sub(Rt.L,Rs.[HL])[:sat]
1030 // Rd=add(Rt.[LH],Rs.[HL])[:sat][:<16]
1031 // Rd=sub(Rt.[LH],Rs.[HL])[:sat][:<16]
1032 //===----------------------------------------------------------------------===//
1034 let hasNewValue = 1, opNewValue = 0 in
1035 class T_XTYPE_ADD_SUB <bits<2> LHbits, bit isSat, bit hasShift, bit isSub>
1036 : ALU64Inst <(outs IntRegs:$Rd), (ins IntRegs:$Rt, IntRegs:$Rs),
1037 "$Rd = "#!if(isSub,"sub","add")#"($Rt."
1038 #!if(hasShift, !if(LHbits{1},"h","l"),"l") #", $Rs."
1039 #!if(hasShift, !if(LHbits{0},"h)","l)"), !if(LHbits{1},"h)","l)"))
1040 #!if(isSat,":sat","")
1041 #!if(hasShift,":<<16",""), [], "", ALU64_tc_1_SLOT23> {
1045 let IClass = 0b1101;
1047 let Inst{27-23} = 0b01010;
1048 let Inst{22} = hasShift;
1049 let Inst{21} = isSub;
1050 let Inst{7} = isSat;
1051 let Inst{6-5} = LHbits;
1053 let Inst{12-8} = Rt;
1054 let Inst{20-16} = Rs;
1057 //Rd=sub(Rt.L,Rs.[LH])
1058 let isCodeGenOnly = 0 in {
1059 def A2_subh_l16_ll : T_XTYPE_ADD_SUB <0b00, 0, 0, 1>;
1060 def A2_subh_l16_hl : T_XTYPE_ADD_SUB <0b10, 0, 0, 1>;
1063 let isCodeGenOnly = 0 in {
1064 //Rd=add(Rt.L,Rs.[LH])
1065 def A2_addh_l16_ll : T_XTYPE_ADD_SUB <0b00, 0, 0, 0>;
1066 def A2_addh_l16_hl : T_XTYPE_ADD_SUB <0b10, 0, 0, 0>;
1069 let Itinerary = ALU64_tc_2_SLOT23, Defs = [USR_OVF], isCodeGenOnly = 0 in {
1070 //Rd=sub(Rt.L,Rs.[LH]):sat
1071 def A2_subh_l16_sat_ll : T_XTYPE_ADD_SUB <0b00, 1, 0, 1>;
1072 def A2_subh_l16_sat_hl : T_XTYPE_ADD_SUB <0b10, 1, 0, 1>;
1074 //Rd=add(Rt.L,Rs.[LH]):sat
1075 def A2_addh_l16_sat_ll : T_XTYPE_ADD_SUB <0b00, 1, 0, 0>;
1076 def A2_addh_l16_sat_hl : T_XTYPE_ADD_SUB <0b10, 1, 0, 0>;
1079 //Rd=sub(Rt.[LH],Rs.[LH]):<<16
1080 let isCodeGenOnly = 0 in {
1081 def A2_subh_h16_ll : T_XTYPE_ADD_SUB <0b00, 0, 1, 1>;
1082 def A2_subh_h16_lh : T_XTYPE_ADD_SUB <0b01, 0, 1, 1>;
1083 def A2_subh_h16_hl : T_XTYPE_ADD_SUB <0b10, 0, 1, 1>;
1084 def A2_subh_h16_hh : T_XTYPE_ADD_SUB <0b11, 0, 1, 1>;
1087 //Rd=add(Rt.[LH],Rs.[LH]):<<16
1088 let isCodeGenOnly = 0 in {
1089 def A2_addh_h16_ll : T_XTYPE_ADD_SUB <0b00, 0, 1, 0>;
1090 def A2_addh_h16_lh : T_XTYPE_ADD_SUB <0b01, 0, 1, 0>;
1091 def A2_addh_h16_hl : T_XTYPE_ADD_SUB <0b10, 0, 1, 0>;
1092 def A2_addh_h16_hh : T_XTYPE_ADD_SUB <0b11, 0, 1, 0>;
1095 let Itinerary = ALU64_tc_2_SLOT23, Defs = [USR_OVF], isCodeGenOnly = 0 in {
1096 //Rd=sub(Rt.[LH],Rs.[LH]):sat:<<16
1097 def A2_subh_h16_sat_ll : T_XTYPE_ADD_SUB <0b00, 1, 1, 1>;
1098 def A2_subh_h16_sat_lh : T_XTYPE_ADD_SUB <0b01, 1, 1, 1>;
1099 def A2_subh_h16_sat_hl : T_XTYPE_ADD_SUB <0b10, 1, 1, 1>;
1100 def A2_subh_h16_sat_hh : T_XTYPE_ADD_SUB <0b11, 1, 1, 1>;
1102 //Rd=add(Rt.[LH],Rs.[LH]):sat:<<16
1103 def A2_addh_h16_sat_ll : T_XTYPE_ADD_SUB <0b00, 1, 1, 0>;
1104 def A2_addh_h16_sat_lh : T_XTYPE_ADD_SUB <0b01, 1, 1, 0>;
1105 def A2_addh_h16_sat_hl : T_XTYPE_ADD_SUB <0b10, 1, 1, 0>;
1106 def A2_addh_h16_sat_hh : T_XTYPE_ADD_SUB <0b11, 1, 1, 0>;
1110 def: Pat<(sext_inreg (add I32:$src1, I32:$src2), i16),
1111 (A2_addh_l16_ll I32:$src1, I32:$src2)>;
1113 def: Pat<(sra (add (shl I32:$src1, (i32 16)), I32:$src2), (i32 16)),
1114 (A2_addh_l16_hl I32:$src1, I32:$src2)>;
1116 def: Pat<(shl (add I32:$src1, I32:$src2), (i32 16)),
1117 (A2_addh_h16_ll I32:$src1, I32:$src2)>;
1119 // Subtract halfword.
1120 def: Pat<(sext_inreg (sub I32:$src1, I32:$src2), i16),
1121 (A2_subh_l16_ll I32:$src1, I32:$src2)>;
1123 def: Pat<(shl (sub I32:$src1, I32:$src2), (i32 16)),
1124 (A2_subh_h16_ll I32:$src1, I32:$src2)>;
1126 let hasSideEffects = 0, hasNewValue = 1, isCodeGenOnly = 0 in
1127 def S2_parityp: ALU64Inst<(outs IntRegs:$Rd),
1128 (ins DoubleRegs:$Rs, DoubleRegs:$Rt),
1129 "$Rd = parity($Rs, $Rt)", [], "", ALU64_tc_2_SLOT23> {
1134 let IClass = 0b1101;
1135 let Inst{27-24} = 0b0000;
1136 let Inst{20-16} = Rs;
1137 let Inst{12-8} = Rt;
1141 let hasNewValue = 1, opNewValue = 0, hasSideEffects = 0 in
1142 class T_XTYPE_MIN_MAX < bit isMax, bit isUnsigned >
1143 : ALU64Inst < (outs IntRegs:$Rd), (ins IntRegs:$Rt, IntRegs:$Rs),
1144 "$Rd = "#!if(isMax,"max","min")#!if(isUnsigned,"u","")
1145 #"($Rt, $Rs)", [], "", ALU64_tc_2_SLOT23> {
1150 let IClass = 0b1101;
1152 let Inst{27-23} = 0b01011;
1153 let Inst{22-21} = !if(isMax, 0b10, 0b01);
1154 let Inst{7} = isUnsigned;
1156 let Inst{12-8} = !if(isMax, Rs, Rt);
1157 let Inst{20-16} = !if(isMax, Rt, Rs);
1160 let isCodeGenOnly = 0 in {
1161 def A2_min : T_XTYPE_MIN_MAX < 0, 0 >;
1162 def A2_minu : T_XTYPE_MIN_MAX < 0, 1 >;
1163 def A2_max : T_XTYPE_MIN_MAX < 1, 0 >;
1164 def A2_maxu : T_XTYPE_MIN_MAX < 1, 1 >;
1167 // Here, depending on the operand being selected, we'll either generate a
1168 // min or max instruction.
1170 // (a>b)?a:b --> max(a,b) => Here check performed is '>' and the value selected
1171 // is the larger of two. So, the corresponding HexagonInst is passed in 'Inst'.
1172 // (a>b)?b:a --> min(a,b) => Here check performed is '>' but the smaller value
1173 // is selected and the corresponding HexagonInst is passed in 'SwapInst'.
1175 multiclass T_MinMax_pats <PatFrag Op, RegisterClass RC, ValueType VT,
1176 InstHexagon Inst, InstHexagon SwapInst> {
1177 def: Pat<(select (i1 (Op (VT RC:$src1), (VT RC:$src2))),
1178 (VT RC:$src1), (VT RC:$src2)),
1179 (Inst RC:$src1, RC:$src2)>;
1180 def: Pat<(select (i1 (Op (VT RC:$src1), (VT RC:$src2))),
1181 (VT RC:$src2), (VT RC:$src1)),
1182 (SwapInst RC:$src1, RC:$src2)>;
1186 multiclass MinMax_pats <PatFrag Op, InstHexagon Inst, InstHexagon SwapInst> {
1187 defm: T_MinMax_pats<Op, IntRegs, i32, Inst, SwapInst>;
1189 def: Pat<(sext_inreg (i32 (select (i1 (Op (i32 PositiveHalfWord:$src1),
1190 (i32 PositiveHalfWord:$src2))),
1191 (i32 PositiveHalfWord:$src1),
1192 (i32 PositiveHalfWord:$src2))), i16),
1193 (Inst IntRegs:$src1, IntRegs:$src2)>;
1195 def: Pat<(sext_inreg (i32 (select (i1 (Op (i32 PositiveHalfWord:$src1),
1196 (i32 PositiveHalfWord:$src2))),
1197 (i32 PositiveHalfWord:$src2),
1198 (i32 PositiveHalfWord:$src1))), i16),
1199 (SwapInst IntRegs:$src1, IntRegs:$src2)>;
1202 let AddedComplexity = 200 in {
1203 defm: MinMax_pats<setge, A2_max, A2_min>;
1204 defm: MinMax_pats<setgt, A2_max, A2_min>;
1205 defm: MinMax_pats<setle, A2_min, A2_max>;
1206 defm: MinMax_pats<setlt, A2_min, A2_max>;
1207 defm: MinMax_pats<setuge, A2_maxu, A2_minu>;
1208 defm: MinMax_pats<setugt, A2_maxu, A2_minu>;
1209 defm: MinMax_pats<setule, A2_minu, A2_maxu>;
1210 defm: MinMax_pats<setult, A2_minu, A2_maxu>;
1213 class T_cmp64_rr<string mnemonic, bits<3> MinOp, bit IsComm>
1214 : ALU64_rr<(outs PredRegs:$Pd), (ins DoubleRegs:$Rs, DoubleRegs:$Rt),
1215 "$Pd = "#mnemonic#"($Rs, $Rt)", [], "", ALU64_tc_2early_SLOT23> {
1217 let isCommutable = IsComm;
1218 let hasSideEffects = 0;
1224 let IClass = 0b1101;
1225 let Inst{27-21} = 0b0010100;
1226 let Inst{20-16} = Rs;
1227 let Inst{12-8} = Rt;
1228 let Inst{7-5} = MinOp;
1232 let isCodeGenOnly = 0 in {
1233 def C2_cmpeqp : T_cmp64_rr<"cmp.eq", 0b000, 1>;
1234 def C2_cmpgtp : T_cmp64_rr<"cmp.gt", 0b010, 0>;
1235 def C2_cmpgtup : T_cmp64_rr<"cmp.gtu", 0b100, 0>;
1238 class T_cmp64_rr_pat<InstHexagon MI, PatFrag CmpOp>
1239 : Pat<(i1 (CmpOp (i64 DoubleRegs:$Rs), (i64 DoubleRegs:$Rt))),
1240 (i1 (MI DoubleRegs:$Rs, DoubleRegs:$Rt))>;
1242 def: T_cmp64_rr_pat<C2_cmpeqp, seteq>;
1243 def: T_cmp64_rr_pat<C2_cmpgtp, setgt>;
1244 def: T_cmp64_rr_pat<C2_cmpgtup, setugt>;
1245 def: T_cmp64_rr_pat<C2_cmpgtp, RevCmp<setlt>>;
1246 def: T_cmp64_rr_pat<C2_cmpgtup, RevCmp<setult>>;
1248 let isCodeGenOnly = 0 in
1249 def C2_vmux : ALU64_rr<(outs DoubleRegs:$Rd),
1250 (ins PredRegs:$Pu, DoubleRegs:$Rs, DoubleRegs:$Rt),
1251 "$Rd = vmux($Pu, $Rs, $Rt)", [], "", ALU64_tc_1_SLOT23> {
1252 let hasSideEffects = 0;
1259 let IClass = 0b1101;
1260 let Inst{27-24} = 0b0001;
1261 let Inst{20-16} = Rs;
1262 let Inst{12-8} = Rt;
1267 class T_ALU64_rr<string mnemonic, string suffix, bits<4> RegType,
1268 bits<3> MajOp, bits<3> MinOp, bit OpsRev, bit IsComm,
1270 : ALU64_rr<(outs DoubleRegs:$Rd), (ins DoubleRegs:$Rs, DoubleRegs:$Rt),
1271 "$Rd = " #mnemonic# "($Rs, " #Op2Pfx# "$Rt)" #suffix, [],
1272 "", ALU64_tc_1_SLOT23> {
1273 let hasSideEffects = 0;
1274 let isCommutable = IsComm;
1280 let IClass = 0b1101;
1281 let Inst{27-24} = RegType;
1282 let Inst{23-21} = MajOp;
1283 let Inst{20-16} = !if (OpsRev,Rt,Rs);
1284 let Inst{12-8} = !if (OpsRev,Rs,Rt);
1285 let Inst{7-5} = MinOp;
1289 class T_ALU64_arith<string mnemonic, bits<3> MajOp, bits<3> MinOp, bit IsSat,
1290 bit OpsRev, bit IsComm>
1291 : T_ALU64_rr<mnemonic, !if(IsSat,":sat",""), 0b0011, MajOp, MinOp, OpsRev,
1294 let isCodeGenOnly = 0 in {
1295 def A2_addp : T_ALU64_arith<"add", 0b000, 0b111, 0, 0, 1>;
1296 def A2_subp : T_ALU64_arith<"sub", 0b001, 0b111, 0, 1, 0>;
1299 def: Pat<(i64 (add I64:$Rs, I64:$Rt)), (A2_addp I64:$Rs, I64:$Rt)>;
1300 def: Pat<(i64 (sub I64:$Rs, I64:$Rt)), (A2_subp I64:$Rs, I64:$Rt)>;
1302 class T_ALU64_logical<string mnemonic, bits<3> MinOp, bit OpsRev, bit IsComm,
1304 : T_ALU64_rr<mnemonic, "", 0b0011, 0b111, MinOp, OpsRev, IsComm,
1307 let isCodeGenOnly = 0 in {
1308 def A2_andp : T_ALU64_logical<"and", 0b000, 0, 1, 0>;
1309 def A2_orp : T_ALU64_logical<"or", 0b010, 0, 1, 0>;
1310 def A2_xorp : T_ALU64_logical<"xor", 0b100, 0, 1, 0>;
1313 def: Pat<(i64 (and I64:$Rs, I64:$Rt)), (A2_andp I64:$Rs, I64:$Rt)>;
1314 def: Pat<(i64 (or I64:$Rs, I64:$Rt)), (A2_orp I64:$Rs, I64:$Rt)>;
1315 def: Pat<(i64 (xor I64:$Rs, I64:$Rt)), (A2_xorp I64:$Rs, I64:$Rt)>;
1317 //===----------------------------------------------------------------------===//
1319 //===----------------------------------------------------------------------===//
1321 //===----------------------------------------------------------------------===//
1323 //===----------------------------------------------------------------------===//
1325 //===----------------------------------------------------------------------===//
1327 //===----------------------------------------------------------------------===//
1329 //===----------------------------------------------------------------------===//
1331 //===----------------------------------------------------------------------===//
1333 //===----------------------------------------------------------------------===//
1335 //===----------------------------------------------------------------------===//
1337 //===----------------------------------------------------------------------===//
1339 //===----------------------------------------------------------------------===//
1340 // Logical reductions on predicates.
1342 // Looping instructions.
1344 // Pipelined looping instructions.
1346 // Logical operations on predicates.
1347 let hasSideEffects = 0 in
1348 class T_LOGICAL_1OP<string MnOp, bits<2> OpBits>
1349 : CRInst<(outs PredRegs:$Pd), (ins PredRegs:$Ps),
1350 "$Pd = " # MnOp # "($Ps)", [], "", CR_tc_2early_SLOT23> {
1354 let IClass = 0b0110;
1355 let Inst{27-23} = 0b10111;
1356 let Inst{22-21} = OpBits;
1358 let Inst{17-16} = Ps;
1363 let isCodeGenOnly = 0 in {
1364 def C2_any8 : T_LOGICAL_1OP<"any8", 0b00>;
1365 def C2_all8 : T_LOGICAL_1OP<"all8", 0b01>;
1366 def C2_not : T_LOGICAL_1OP<"not", 0b10>;
1369 def: Pat<(i1 (not (i1 PredRegs:$Ps))),
1370 (C2_not PredRegs:$Ps)>;
1372 let hasSideEffects = 0 in
1373 class T_LOGICAL_2OP<string MnOp, bits<3> OpBits, bit IsNeg, bit Rev>
1374 : CRInst<(outs PredRegs:$Pd), (ins PredRegs:$Ps, PredRegs:$Pt),
1375 "$Pd = " # MnOp # "($Ps, " # !if (IsNeg,"!","") # "$Pt)",
1376 [], "", CR_tc_2early_SLOT23> {
1381 let IClass = 0b0110;
1382 let Inst{27-24} = 0b1011;
1383 let Inst{23-21} = OpBits;
1385 let Inst{17-16} = !if(Rev,Pt,Ps); // Rs and Rt are reversed for some
1386 let Inst{13} = 0b0; // instructions.
1387 let Inst{9-8} = !if(Rev,Ps,Pt);
1391 let isCodeGenOnly = 0 in {
1392 def C2_and : T_LOGICAL_2OP<"and", 0b000, 0, 1>;
1393 def C2_or : T_LOGICAL_2OP<"or", 0b001, 0, 1>;
1394 def C2_xor : T_LOGICAL_2OP<"xor", 0b010, 0, 0>;
1395 def C2_andn : T_LOGICAL_2OP<"and", 0b011, 1, 1>;
1396 def C2_orn : T_LOGICAL_2OP<"or", 0b111, 1, 1>;
1399 def: Pat<(i1 (and I1:$Ps, I1:$Pt)), (C2_and I1:$Ps, I1:$Pt)>;
1400 def: Pat<(i1 (or I1:$Ps, I1:$Pt)), (C2_or I1:$Ps, I1:$Pt)>;
1401 def: Pat<(i1 (xor I1:$Ps, I1:$Pt)), (C2_xor I1:$Ps, I1:$Pt)>;
1402 def: Pat<(i1 (and I1:$Ps, (not I1:$Pt))), (C2_andn I1:$Ps, I1:$Pt)>;
1403 def: Pat<(i1 (or I1:$Ps, (not I1:$Pt))), (C2_orn I1:$Ps, I1:$Pt)>;
1405 let hasSideEffects = 0, hasNewValue = 1, isCodeGenOnly = 0 in
1406 def C2_vitpack : SInst<(outs IntRegs:$Rd), (ins PredRegs:$Ps, PredRegs:$Pt),
1407 "$Rd = vitpack($Ps, $Pt)", [], "", S_2op_tc_1_SLOT23> {
1412 let IClass = 0b1000;
1413 let Inst{27-24} = 0b1001;
1414 let Inst{22-21} = 0b00;
1415 let Inst{17-16} = Ps;
1420 let hasSideEffects = 0, isCodeGenOnly = 0 in
1421 def C2_mask : SInst<(outs DoubleRegs:$Rd), (ins PredRegs:$Pt),
1422 "$Rd = mask($Pt)", [], "", S_2op_tc_1_SLOT23> {
1426 let IClass = 0b1000;
1427 let Inst{27-24} = 0b0110;
1432 // User control register transfer.
1433 //===----------------------------------------------------------------------===//
1435 //===----------------------------------------------------------------------===//
1437 //===----------------------------------------------------------------------===//
1439 //===----------------------------------------------------------------------===//
1441 def retflag : SDNode<"HexagonISD::RET_FLAG", SDTNone,
1442 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
1443 def eh_return: SDNode<"HexagonISD::EH_RETURN", SDTNone, [SDNPHasChain]>;
1445 def SDHexagonBR_JT: SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
1446 def HexagonBR_JT: SDNode<"HexagonISD::BR_JT", SDHexagonBR_JT, [SDNPHasChain]>;
1448 class CondStr<string CReg, bit True, bit New> {
1449 string S = "if (" # !if(True,"","!") # CReg # !if(New,".new","") # ") ";
1451 class JumpOpcStr<string Mnemonic, bit New, bit Taken> {
1452 string S = Mnemonic # !if(New, !if(Taken,":t",":nt"), "");
1455 let isBranch = 1, isBarrier = 1, Defs = [PC], hasSideEffects = 0,
1457 isExtendable = 1, opExtendable = 0, isExtentSigned = 1,
1458 opExtentBits = 24, opExtentAlign = 2, InputType = "imm" in
1459 class T_JMP<string ExtStr>
1460 : JInst<(outs), (ins brtarget:$dst),
1461 "jump " # ExtStr # "$dst",
1462 [], "", J_tc_2early_SLOT23> {
1464 let IClass = 0b0101;
1466 let Inst{27-25} = 0b100;
1467 let Inst{24-16} = dst{23-15};
1468 let Inst{13-1} = dst{14-2};
1471 let isBranch = 1, Defs = [PC], hasSideEffects = 0, isPredicated = 1,
1472 isExtendable = 1, opExtendable = 1, isExtentSigned = 1,
1473 opExtentBits = 17, opExtentAlign = 2, InputType = "imm" in
1474 class T_JMP_c<bit PredNot, bit isPredNew, bit isTak, string ExtStr>
1475 : JInst<(outs), (ins PredRegs:$src, brtarget:$dst),
1476 CondStr<"$src", !if(PredNot,0,1), isPredNew>.S #
1477 JumpOpcStr<"jump", isPredNew, isTak>.S # " " #
1479 [], "", J_tc_2early_SLOT23>, ImmRegRel {
1480 let isTaken = isTak;
1481 let isPredicatedFalse = PredNot;
1482 let isPredicatedNew = isPredNew;
1486 let IClass = 0b0101;
1488 let Inst{27-24} = 0b1100;
1489 let Inst{21} = PredNot;
1490 let Inst{12} = !if(isPredNew, isTak, zero);
1491 let Inst{11} = isPredNew;
1492 let Inst{9-8} = src;
1493 let Inst{23-22} = dst{16-15};
1494 let Inst{20-16} = dst{14-10};
1495 let Inst{13} = dst{9};
1496 let Inst{7-1} = dst{8-2};
1499 multiclass JMP_Pred<bit PredNot, string ExtStr> {
1500 def NAME : T_JMP_c<PredNot, 0, 0, ExtStr>;
1502 def NAME#newpt : T_JMP_c<PredNot, 1, 1, ExtStr>; // taken
1503 def NAME#new : T_JMP_c<PredNot, 1, 0, ExtStr>; // not taken
1506 multiclass JMP_base<string BaseOp, string ExtStr> {
1507 let BaseOpcode = BaseOp in {
1508 def NAME : T_JMP<ExtStr>;
1509 defm t : JMP_Pred<0, ExtStr>;
1510 defm f : JMP_Pred<1, ExtStr>;
1514 // Jumps to address stored in a register, JUMPR_MISC
1515 // if ([[!]P[.new]]) jumpr[:t/nt] Rs
1516 let isBranch = 1, isIndirectBranch = 1, isBarrier = 1, Defs = [PC],
1517 isPredicable = 1, hasSideEffects = 0, InputType = "reg" in
1519 : JRInst<(outs), (ins IntRegs:$dst),
1520 "jumpr $dst", [], "", J_tc_2early_SLOT2> {
1523 let IClass = 0b0101;
1524 let Inst{27-21} = 0b0010100;
1525 let Inst{20-16} = dst;
1528 let isBranch = 1, isIndirectBranch = 1, Defs = [PC], isPredicated = 1,
1529 hasSideEffects = 0, InputType = "reg" in
1530 class T_JMPr_c <bit PredNot, bit isPredNew, bit isTak>
1531 : JRInst <(outs), (ins PredRegs:$src, IntRegs:$dst),
1532 CondStr<"$src", !if(PredNot,0,1), isPredNew>.S #
1533 JumpOpcStr<"jumpr", isPredNew, isTak>.S # " $dst", [],
1534 "", J_tc_2early_SLOT2> {
1536 let isTaken = isTak;
1537 let isPredicatedFalse = PredNot;
1538 let isPredicatedNew = isPredNew;
1542 let IClass = 0b0101;
1544 let Inst{27-22} = 0b001101;
1545 let Inst{21} = PredNot;
1546 let Inst{20-16} = dst;
1547 let Inst{12} = !if(isPredNew, isTak, zero);
1548 let Inst{11} = isPredNew;
1549 let Inst{9-8} = src;
1552 multiclass JMPR_Pred<bit PredNot> {
1553 def NAME: T_JMPr_c<PredNot, 0, 0>;
1555 def NAME#newpt : T_JMPr_c<PredNot, 1, 1>; // taken
1556 def NAME#new : T_JMPr_c<PredNot, 1, 0>; // not taken
1559 multiclass JMPR_base<string BaseOp> {
1560 let BaseOpcode = BaseOp in {
1562 defm t : JMPR_Pred<0>;
1563 defm f : JMPR_Pred<1>;
1567 let isCall = 1, hasSideEffects = 1 in
1568 class JUMPR_MISC_CALLR<bit isPred, bit isPredNot,
1569 dag InputDag = (ins IntRegs:$Rs)>
1570 : JRInst<(outs), InputDag,
1571 !if(isPred, !if(isPredNot, "if (!$Pu) callr $Rs",
1572 "if ($Pu) callr $Rs"),
1574 [], "", J_tc_2early_SLOT2> {
1577 let isPredicated = isPred;
1578 let isPredicatedFalse = isPredNot;
1580 let IClass = 0b0101;
1581 let Inst{27-25} = 0b000;
1582 let Inst{24-23} = !if (isPred, 0b10, 0b01);
1584 let Inst{21} = isPredNot;
1585 let Inst{9-8} = !if (isPred, Pu, 0b00);
1586 let Inst{20-16} = Rs;
1590 let Defs = VolatileV3.Regs, isCodeGenOnly = 0 in {
1591 def J2_callrt : JUMPR_MISC_CALLR<1, 0, (ins PredRegs:$Pu, IntRegs:$Rs)>;
1592 def J2_callrf : JUMPR_MISC_CALLR<1, 1, (ins PredRegs:$Pu, IntRegs:$Rs)>;
1595 let isTerminator = 1, hasSideEffects = 0, isCodeGenOnly = 0 in {
1596 defm J2_jump : JMP_base<"JMP", "">, PredNewRel;
1598 // Deal with explicit assembly
1599 // - never extened a jump #, always extend a jump ##
1600 let isAsmParserOnly = 1 in {
1601 defm J2_jump_ext : JMP_base<"JMP", "##">;
1602 defm J2_jump_noext : JMP_base<"JMP", "#">;
1605 defm J2_jumpr : JMPR_base<"JMPr">, PredNewRel;
1607 let isReturn = 1, isCodeGenOnly = 1 in
1608 defm JMPret : JMPR_base<"JMPret">, PredNewRel;
1611 def: Pat<(br bb:$dst),
1612 (J2_jump brtarget:$dst)>;
1614 (JMPret (i32 R31))>;
1615 def: Pat<(brcond (i1 PredRegs:$src1), bb:$offset),
1616 (J2_jumpt PredRegs:$src1, bb:$offset)>;
1618 // A return through builtin_eh_return.
1619 let isReturn = 1, isTerminator = 1, isBarrier = 1, hasSideEffects = 0,
1620 isCodeGenOnly = 1, Defs = [PC], Uses = [R28], isPredicable = 0 in
1621 def EH_RETURN_JMPR : T_JMPr;
1623 def: Pat<(eh_return),
1624 (EH_RETURN_JMPR (i32 R31))>;
1625 def: Pat<(HexagonBR_JT (i32 IntRegs:$dst)),
1626 (J2_jumpr IntRegs:$dst)>;
1627 def: Pat<(brind (i32 IntRegs:$dst)),
1628 (J2_jumpr IntRegs:$dst)>;
1630 //===----------------------------------------------------------------------===//
1632 //===----------------------------------------------------------------------===//
1634 //===----------------------------------------------------------------------===//
1636 //===----------------------------------------------------------------------===//
1637 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, AddedComplexity = 20 in
1638 class T_load_io <string mnemonic, RegisterClass RC, bits<4> MajOp,
1640 : LDInst<(outs RC:$dst), (ins IntRegs:$src1, ImmOp:$offset),
1641 "$dst = "#mnemonic#"($src1 + #$offset)", []>, AddrModeRel {
1646 bits<11> offsetBits;
1648 string ImmOpStr = !cast<string>(ImmOp);
1649 let offsetBits = !if (!eq(ImmOpStr, "s11_3Ext"), offset{13-3},
1650 !if (!eq(ImmOpStr, "s11_2Ext"), offset{12-2},
1651 !if (!eq(ImmOpStr, "s11_1Ext"), offset{11-1},
1652 /* s11_0Ext */ offset{10-0})));
1653 let opExtentBits = !if (!eq(ImmOpStr, "s11_3Ext"), 14,
1654 !if (!eq(ImmOpStr, "s11_2Ext"), 13,
1655 !if (!eq(ImmOpStr, "s11_1Ext"), 12,
1656 /* s11_0Ext */ 11)));
1657 let hasNewValue = !if (!eq(ImmOpStr, "s11_3Ext"), 0, 1);
1659 let IClass = 0b1001;
1662 let Inst{26-25} = offsetBits{10-9};
1663 let Inst{24-21} = MajOp;
1664 let Inst{20-16} = src1;
1665 let Inst{13-5} = offsetBits{8-0};
1666 let Inst{4-0} = dst;
1669 let opExtendable = 3, isExtentSigned = 0, isPredicated = 1 in
1670 class T_pload_io <string mnemonic, RegisterClass RC, bits<4>MajOp,
1671 Operand ImmOp, bit isNot, bit isPredNew>
1672 : LDInst<(outs RC:$dst),
1673 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset),
1674 "if ("#!if(isNot, "!$src1", "$src1")
1675 #!if(isPredNew, ".new", "")
1676 #") $dst = "#mnemonic#"($src2 + #$offset)",
1677 [],"", V2LDST_tc_ld_SLOT01> , AddrModeRel {
1683 string ImmOpStr = !cast<string>(ImmOp);
1685 let offsetBits = !if (!eq(ImmOpStr, "u6_3Ext"), offset{8-3},
1686 !if (!eq(ImmOpStr, "u6_2Ext"), offset{7-2},
1687 !if (!eq(ImmOpStr, "u6_1Ext"), offset{6-1},
1688 /* u6_0Ext */ offset{5-0})));
1689 let opExtentBits = !if (!eq(ImmOpStr, "u6_3Ext"), 9,
1690 !if (!eq(ImmOpStr, "u6_2Ext"), 8,
1691 !if (!eq(ImmOpStr, "u6_1Ext"), 7,
1693 let hasNewValue = !if (!eq(ImmOpStr, "u6_3Ext"), 0, 1);
1694 let isPredicatedNew = isPredNew;
1695 let isPredicatedFalse = isNot;
1697 let IClass = 0b0100;
1701 let Inst{26} = isNot;
1702 let Inst{25} = isPredNew;
1703 let Inst{24-21} = MajOp;
1704 let Inst{20-16} = src2;
1706 let Inst{12-11} = src1;
1707 let Inst{10-5} = offsetBits;
1708 let Inst{4-0} = dst;
1711 let isExtendable = 1, hasSideEffects = 0, addrMode = BaseImmOffset in
1712 multiclass LD_Idxd<string mnemonic, string CextOp, RegisterClass RC,
1713 Operand ImmOp, Operand predImmOp, bits<4>MajOp> {
1714 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed in {
1715 let isPredicable = 1 in
1716 def L2_#NAME#_io : T_load_io <mnemonic, RC, MajOp, ImmOp>;
1719 def L2_p#NAME#t_io : T_pload_io <mnemonic, RC, MajOp, predImmOp, 0, 0>;
1720 def L2_p#NAME#f_io : T_pload_io <mnemonic, RC, MajOp, predImmOp, 1, 0>;
1723 def L2_p#NAME#tnew_io : T_pload_io <mnemonic, RC, MajOp, predImmOp, 0, 1>;
1724 def L2_p#NAME#fnew_io : T_pload_io <mnemonic, RC, MajOp, predImmOp, 1, 1>;
1728 let accessSize = ByteAccess, isCodeGenOnly = 0 in {
1729 defm loadrb: LD_Idxd <"memb", "LDrib", IntRegs, s11_0Ext, u6_0Ext, 0b1000>;
1730 defm loadrub: LD_Idxd <"memub", "LDriub", IntRegs, s11_0Ext, u6_0Ext, 0b1001>;
1733 let accessSize = HalfWordAccess, opExtentAlign = 1, isCodeGenOnly = 0 in {
1734 defm loadrh: LD_Idxd <"memh", "LDrih", IntRegs, s11_1Ext, u6_1Ext, 0b1010>;
1735 defm loadruh: LD_Idxd <"memuh", "LDriuh", IntRegs, s11_1Ext, u6_1Ext, 0b1011>;
1738 let accessSize = WordAccess, opExtentAlign = 2, isCodeGenOnly = 0 in
1739 defm loadri: LD_Idxd <"memw", "LDriw", IntRegs, s11_2Ext, u6_2Ext, 0b1100>;
1741 let accessSize = DoubleWordAccess, opExtentAlign = 3, isCodeGenOnly = 0 in
1742 defm loadrd: LD_Idxd <"memd", "LDrid", DoubleRegs, s11_3Ext, u6_3Ext, 0b1110>;
1744 // Patterns to select load-indexed (i.e. load from base+offset).
1745 multiclass Loadx_pat<PatFrag Load, ValueType VT, PatLeaf ImmPred,
1747 def: Pat<(VT (Load AddrFI:$fi)), (VT (MI AddrFI:$fi, 0))>;
1748 def: Pat<(VT (Load (add (i32 IntRegs:$Rs), ImmPred:$Off))),
1749 (VT (MI IntRegs:$Rs, imm:$Off))>;
1750 def: Pat<(VT (Load (i32 IntRegs:$Rs))), (VT (MI IntRegs:$Rs, 0))>;
1753 let AddedComplexity = 20 in {
1754 defm: Loadx_pat<load, i32, s11_2ExtPred, L2_loadri_io>;
1755 defm: Loadx_pat<load, i64, s11_3ExtPred, L2_loadrd_io>;
1756 defm: Loadx_pat<atomic_load_8 , i32, s11_0ExtPred, L2_loadrub_io>;
1757 defm: Loadx_pat<atomic_load_16, i32, s11_1ExtPred, L2_loadruh_io>;
1758 defm: Loadx_pat<atomic_load_32, i32, s11_2ExtPred, L2_loadri_io>;
1759 defm: Loadx_pat<atomic_load_64, i64, s11_3ExtPred, L2_loadrd_io>;
1761 defm: Loadx_pat<extloadi1, i32, s11_0ExtPred, L2_loadrub_io>;
1762 defm: Loadx_pat<extloadi8, i32, s11_0ExtPred, L2_loadrub_io>;
1763 defm: Loadx_pat<extloadi16, i32, s11_1ExtPred, L2_loadruh_io>;
1764 defm: Loadx_pat<sextloadi8, i32, s11_0ExtPred, L2_loadrb_io>;
1765 defm: Loadx_pat<sextloadi16, i32, s11_1ExtPred, L2_loadrh_io>;
1766 defm: Loadx_pat<zextloadi1, i32, s11_0ExtPred, L2_loadrub_io>;
1767 defm: Loadx_pat<zextloadi8, i32, s11_0ExtPred, L2_loadrub_io>;
1768 defm: Loadx_pat<zextloadi16, i32, s11_1ExtPred, L2_loadruh_io>;
1772 // Sign-extending loads of i1 need to replicate the lowest bit throughout
1773 // the 32-bit value. Since the loaded value can only be 0 or 1, 0-v should
1775 let AddedComplexity = 20 in
1776 def: Pat<(i32 (sextloadi1 (i32 IntRegs:$Rs))),
1777 (SUB_ri 0, (L2_loadrub_io IntRegs:$Rs, 0))>;
1779 //===----------------------------------------------------------------------===//
1780 // Post increment load
1781 //===----------------------------------------------------------------------===//
1782 //===----------------------------------------------------------------------===//
1783 // Template class for non-predicated post increment loads with immediate offset.
1784 //===----------------------------------------------------------------------===//
1785 let hasSideEffects = 0, addrMode = PostInc in
1786 class T_load_pi <string mnemonic, RegisterClass RC, Operand ImmOp,
1788 : LDInstPI <(outs RC:$dst, IntRegs:$dst2),
1789 (ins IntRegs:$src1, ImmOp:$offset),
1790 "$dst = "#mnemonic#"($src1++#$offset)" ,
1799 string ImmOpStr = !cast<string>(ImmOp);
1800 let offsetBits = !if (!eq(ImmOpStr, "s4_3Imm"), offset{6-3},
1801 !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2},
1802 !if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1},
1803 /* s4_0Imm */ offset{3-0})));
1804 let hasNewValue = !if (!eq(ImmOpStr, "s4_3Imm"), 0, 1);
1806 let IClass = 0b1001;
1808 let Inst{27-25} = 0b101;
1809 let Inst{24-21} = MajOp;
1810 let Inst{20-16} = src1;
1811 let Inst{13-12} = 0b00;
1812 let Inst{8-5} = offsetBits;
1813 let Inst{4-0} = dst;
1816 //===----------------------------------------------------------------------===//
1817 // Template class for predicated post increment loads with immediate offset.
1818 //===----------------------------------------------------------------------===//
1819 let isPredicated = 1, hasSideEffects = 0, addrMode = PostInc in
1820 class T_pload_pi <string mnemonic, RegisterClass RC, Operand ImmOp,
1821 bits<4> MajOp, bit isPredNot, bit isPredNew >
1822 : LDInst <(outs RC:$dst, IntRegs:$dst2),
1823 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset),
1824 !if(isPredNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1825 ") ")#"$dst = "#mnemonic#"($src2++#$offset)",
1835 let isPredicatedNew = isPredNew;
1836 let isPredicatedFalse = isPredNot;
1838 string ImmOpStr = !cast<string>(ImmOp);
1839 let offsetBits = !if (!eq(ImmOpStr, "s4_3Imm"), offset{6-3},
1840 !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2},
1841 !if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1},
1842 /* s4_0Imm */ offset{3-0})));
1843 let hasNewValue = !if (!eq(ImmOpStr, "s4_3Imm"), 0, 1);
1845 let IClass = 0b1001;
1847 let Inst{27-25} = 0b101;
1848 let Inst{24-21} = MajOp;
1849 let Inst{20-16} = src2;
1851 let Inst{12} = isPredNew;
1852 let Inst{11} = isPredNot;
1853 let Inst{10-9} = src1;
1854 let Inst{8-5} = offsetBits;
1855 let Inst{4-0} = dst;
1858 //===----------------------------------------------------------------------===//
1859 // Multiclass for post increment loads with immediate offset.
1860 //===----------------------------------------------------------------------===//
1862 multiclass LD_PostInc <string mnemonic, string BaseOp, RegisterClass RC,
1863 Operand ImmOp, bits<4> MajOp> {
1864 let BaseOpcode = "POST_"#BaseOp in {
1865 let isPredicable = 1 in
1866 def L2_#NAME#_pi : T_load_pi < mnemonic, RC, ImmOp, MajOp>;
1869 def L2_p#NAME#t_pi : T_pload_pi < mnemonic, RC, ImmOp, MajOp, 0, 0>;
1870 def L2_p#NAME#f_pi : T_pload_pi < mnemonic, RC, ImmOp, MajOp, 1, 0>;
1873 def L2_p#NAME#tnew_pi : T_pload_pi < mnemonic, RC, ImmOp, MajOp, 0, 1>;
1874 def L2_p#NAME#fnew_pi : T_pload_pi < mnemonic, RC, ImmOp, MajOp, 1, 1>;
1878 // post increment byte loads with immediate offset
1879 let accessSize = ByteAccess, isCodeGenOnly = 0 in {
1880 defm loadrb : LD_PostInc <"memb", "LDrib", IntRegs, s4_0Imm, 0b1000>;
1881 defm loadrub : LD_PostInc <"memub", "LDriub", IntRegs, s4_0Imm, 0b1001>;
1884 // post increment halfword loads with immediate offset
1885 let accessSize = HalfWordAccess, opExtentAlign = 1, isCodeGenOnly = 0 in {
1886 defm loadrh : LD_PostInc <"memh", "LDrih", IntRegs, s4_1Imm, 0b1010>;
1887 defm loadruh : LD_PostInc <"memuh", "LDriuh", IntRegs, s4_1Imm, 0b1011>;
1890 // post increment word loads with immediate offset
1891 let accessSize = WordAccess, opExtentAlign = 2, isCodeGenOnly = 0 in
1892 defm loadri : LD_PostInc <"memw", "LDriw", IntRegs, s4_2Imm, 0b1100>;
1894 // post increment doubleword loads with immediate offset
1895 let accessSize = DoubleWordAccess, opExtentAlign = 3, isCodeGenOnly = 0 in
1896 defm loadrd : LD_PostInc <"memd", "LDrid", DoubleRegs, s4_3Imm, 0b1110>;
1898 //===----------------------------------------------------------------------===//
1899 // Template class for post increment loads with register offset.
1900 //===----------------------------------------------------------------------===//
1901 let hasSideEffects = 0, addrMode = PostInc in
1902 class T_load_pr <string mnemonic, RegisterClass RC, bits<4> MajOp,
1903 MemAccessSize AccessSz>
1904 : LDInstPI <(outs RC:$dst, IntRegs:$_dst_),
1905 (ins IntRegs:$src1, ModRegs:$src2),
1906 "$dst = "#mnemonic#"($src1++$src2)" ,
1907 [], "$src1 = $_dst_" > {
1912 let accessSize = AccessSz;
1913 let IClass = 0b1001;
1915 let Inst{27-25} = 0b110;
1916 let Inst{24-21} = MajOp;
1917 let Inst{20-16} = src1;
1918 let Inst{13} = src2;
1921 let Inst{4-0} = dst;
1924 let hasNewValue = 1, isCodeGenOnly = 0 in {
1925 def L2_loadrb_pr : T_load_pr <"memb", IntRegs, 0b1000, ByteAccess>;
1926 def L2_loadrub_pr : T_load_pr <"memub", IntRegs, 0b1001, ByteAccess>;
1927 def L2_loadrh_pr : T_load_pr <"memh", IntRegs, 0b1010, HalfWordAccess>;
1928 def L2_loadruh_pr : T_load_pr <"memuh", IntRegs, 0b1011, HalfWordAccess>;
1929 def L2_loadri_pr : T_load_pr <"memw", IntRegs, 0b1100, WordAccess>;
1932 let isCodeGenOnly = 0 in
1933 def L2_loadrd_pr : T_load_pr <"memd", DoubleRegs, 0b1110, DoubleWordAccess>;
1936 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 13,
1937 isPseudo = 1, Defs = [R10,R11,D5], hasSideEffects = 0 in
1938 def LDriw_pred : LDInst2<(outs PredRegs:$dst),
1940 "Error; should not emit",
1943 let Defs = [R29, R30, R31], Uses = [R30], hasSideEffects = 0, isCodeGenOnly = 0 in
1944 def L2_deallocframe : LDInst<(outs), (ins),
1947 let IClass = 0b1001;
1949 let Inst{27-16} = 0b000000011110;
1951 let Inst{4-0} = 0b11110;
1954 // Load / Post increment circular addressing mode.
1955 let Uses = [CS], hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in
1956 class T_load_pcr<string mnemonic, RegisterClass RC, bits<4> MajOp>
1957 : LDInst <(outs RC:$dst, IntRegs:$_dst_),
1958 (ins IntRegs:$Rz, ModRegs:$Mu),
1959 "$dst = "#mnemonic#"($Rz ++ I:circ($Mu))", [],
1965 let IClass = 0b1001;
1967 let Inst{27-25} = 0b100;
1968 let Inst{24-21} = MajOp;
1969 let Inst{20-16} = Rz;
1974 let Inst{4-0} = dst;
1977 let accessSize = ByteAccess, isCodeGenOnly = 0 in {
1978 def L2_loadrb_pcr : T_load_pcr <"memb", IntRegs, 0b1000>;
1979 def L2_loadrub_pcr : T_load_pcr <"memub", IntRegs, 0b1001>;
1982 let accessSize = HalfWordAccess, isCodeGenOnly = 0 in {
1983 def L2_loadrh_pcr : T_load_pcr <"memh", IntRegs, 0b1010>;
1984 def L2_loadruh_pcr : T_load_pcr <"memuh", IntRegs, 0b1011>;
1987 let accessSize = WordAccess, isCodeGenOnly = 0 in {
1988 def L2_loadri_pcr : T_load_pcr <"memw", IntRegs, 0b1100>;
1991 let accessSize = DoubleWordAccess, isCodeGenOnly = 0 in
1992 def L2_loadrd_pcr : T_load_pcr <"memd", DoubleRegs, 0b1110>;
1994 //===----------------------------------------------------------------------===//
1995 // Circular loads with immediate offset.
1996 //===----------------------------------------------------------------------===//
1997 let Uses = [CS], mayLoad = 1, hasSideEffects = 0, hasNewValue = 1 in
1998 class T_load_pci <string mnemonic, RegisterClass RC,
1999 Operand ImmOp, bits<4> MajOp>
2000 : LDInstPI<(outs RC:$dst, IntRegs:$_dst_),
2001 (ins IntRegs:$Rz, ImmOp:$offset, ModRegs:$Mu),
2002 "$dst = "#mnemonic#"($Rz ++ #$offset:circ($Mu))", [],
2010 string ImmOpStr = !cast<string>(ImmOp);
2011 let offsetBits = !if (!eq(ImmOpStr, "s4_3Imm"), offset{6-3},
2012 !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2},
2013 !if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1},
2014 /* s4_0Imm */ offset{3-0})));
2015 let IClass = 0b1001;
2016 let Inst{27-25} = 0b100;
2017 let Inst{24-21} = MajOp;
2018 let Inst{20-16} = Rz;
2022 let Inst{8-5} = offsetBits;
2023 let Inst{4-0} = dst;
2026 // Byte variants of circ load
2027 let accessSize = ByteAccess, isCodeGenOnly = 0 in {
2028 def L2_loadrb_pci : T_load_pci <"memb", IntRegs, s4_0Imm, 0b1000>;
2029 def L2_loadrub_pci : T_load_pci <"memub", IntRegs, s4_0Imm, 0b1001>;
2032 // Half word variants of circ load
2033 let accessSize = HalfWordAccess, isCodeGenOnly = 0 in {
2034 def L2_loadrh_pci : T_load_pci <"memh", IntRegs, s4_1Imm, 0b1010>;
2035 def L2_loadruh_pci : T_load_pci <"memuh", IntRegs, s4_1Imm, 0b1011>;
2038 // Word variants of circ load
2039 let accessSize = WordAccess, isCodeGenOnly = 0 in
2040 def L2_loadri_pci : T_load_pci <"memw", IntRegs, s4_2Imm, 0b1100>;
2042 let accessSize = DoubleWordAccess, hasNewValue = 0, isCodeGenOnly = 0 in
2043 def L2_loadrd_pci : T_load_pci <"memd", DoubleRegs, s4_3Imm, 0b1110>;
2045 // L[24]_load[wd]_locked: Load word/double with lock.
2047 class T_load_locked <string mnemonic, RegisterClass RC>
2048 : LD0Inst <(outs RC:$dst),
2050 "$dst = "#mnemonic#"($src)"> {
2053 let IClass = 0b1001;
2054 let Inst{27-21} = 0b0010000;
2055 let Inst{20-16} = src;
2056 let Inst{13-12} = !if (!eq(mnemonic, "memd_locked"), 0b01, 0b00);
2057 let Inst{4-0} = dst;
2059 let hasNewValue = 1, accessSize = WordAccess, opNewValue = 0, isCodeGenOnly = 0 in
2060 def L2_loadw_locked : T_load_locked <"memw_locked", IntRegs>;
2061 let accessSize = DoubleWordAccess, isCodeGenOnly = 0 in
2062 def L4_loadd_locked : T_load_locked <"memd_locked", DoubleRegs>;
2063 //===----------------------------------------------------------------------===//
2064 // Bit-reversed loads with auto-increment register
2065 //===----------------------------------------------------------------------===//
2066 let hasSideEffects = 0 in
2067 class T_load_pbr<string mnemonic, RegisterClass RC,
2068 MemAccessSize addrSize, bits<4> majOp>
2070 <(outs RC:$dst, IntRegs:$_dst_),
2071 (ins IntRegs:$Rz, ModRegs:$Mu),
2072 "$dst = "#mnemonic#"($Rz ++ $Mu:brev)" ,
2073 [] , "$Rz = $_dst_" > {
2075 let accessSize = addrSize;
2081 let IClass = 0b1001;
2083 let Inst{27-25} = 0b111;
2084 let Inst{24-21} = majOp;
2085 let Inst{20-16} = Rz;
2089 let Inst{4-0} = dst;
2092 let hasNewValue =1, opNewValue = 0, isCodeGenOnly = 0 in {
2093 def L2_loadrb_pbr : T_load_pbr <"memb", IntRegs, ByteAccess, 0b1000>;
2094 def L2_loadrub_pbr : T_load_pbr <"memub", IntRegs, ByteAccess, 0b1001>;
2095 def L2_loadrh_pbr : T_load_pbr <"memh", IntRegs, HalfWordAccess, 0b1010>;
2096 def L2_loadruh_pbr : T_load_pbr <"memuh", IntRegs, HalfWordAccess, 0b1011>;
2097 def L2_loadri_pbr : T_load_pbr <"memw", IntRegs, WordAccess, 0b1100>;
2100 let isCodeGenOnly = 0 in
2101 def L2_loadrd_pbr : T_load_pbr <"memd", DoubleRegs, DoubleWordAccess, 0b1110>;
2103 //===----------------------------------------------------------------------===//
2105 //===----------------------------------------------------------------------===//
2107 //===----------------------------------------------------------------------===//
2109 //===----------------------------------------------------------------------===//
2110 //===----------------------------------------------------------------------===//
2112 //===----------------------------------------------------------------------===//
2114 //===----------------------------------------------------------------------===//
2116 //===----------------------------------------------------------------------===//
2117 //===----------------------------------------------------------------------===//
2119 //===----------------------------------------------------------------------===//
2121 //===----------------------------------------------------------------------===//
2123 //===----------------------------------------------------------------------===//
2125 //===----------------------------------------------------------------------===//
2127 // MPYS / Multipy signed/unsigned halfwords
2128 //Rd=mpy[u](Rs.[H|L],Rt.[H|L])[:<<1][:rnd][:sat]
2129 //===----------------------------------------------------------------------===//
2131 let hasNewValue = 1, opNewValue = 0 in
2132 class T_M2_mpy < bits<2> LHbits, bit isSat, bit isRnd,
2133 bit hasShift, bit isUnsigned>
2134 : MInst < (outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt),
2135 "$Rd = "#!if(isUnsigned,"mpyu","mpy")#"($Rs."#!if(LHbits{1},"h","l")
2136 #", $Rt."#!if(LHbits{0},"h)","l)")
2137 #!if(hasShift,":<<1","")
2138 #!if(isRnd,":rnd","")
2139 #!if(isSat,":sat",""),
2140 [], "", M_tc_3x_SLOT23 > {
2145 let IClass = 0b1110;
2147 let Inst{27-24} = 0b1100;
2148 let Inst{23} = hasShift;
2149 let Inst{22} = isUnsigned;
2150 let Inst{21} = isRnd;
2151 let Inst{7} = isSat;
2152 let Inst{6-5} = LHbits;
2154 let Inst{20-16} = Rs;
2155 let Inst{12-8} = Rt;
2158 //Rd=mpy(Rs.[H|L],Rt.[H|L])[:<<1]
2159 let isCodeGenOnly = 0 in {
2160 def M2_mpy_ll_s1: T_M2_mpy<0b00, 0, 0, 1, 0>;
2161 def M2_mpy_ll_s0: T_M2_mpy<0b00, 0, 0, 0, 0>;
2162 def M2_mpy_lh_s1: T_M2_mpy<0b01, 0, 0, 1, 0>;
2163 def M2_mpy_lh_s0: T_M2_mpy<0b01, 0, 0, 0, 0>;
2164 def M2_mpy_hl_s1: T_M2_mpy<0b10, 0, 0, 1, 0>;
2165 def M2_mpy_hl_s0: T_M2_mpy<0b10, 0, 0, 0, 0>;
2166 def M2_mpy_hh_s1: T_M2_mpy<0b11, 0, 0, 1, 0>;
2167 def M2_mpy_hh_s0: T_M2_mpy<0b11, 0, 0, 0, 0>;
2170 //Rd=mpyu(Rs.[H|L],Rt.[H|L])[:<<1]
2171 let isCodeGenOnly = 0 in {
2172 def M2_mpyu_ll_s1: T_M2_mpy<0b00, 0, 0, 1, 1>;
2173 def M2_mpyu_ll_s0: T_M2_mpy<0b00, 0, 0, 0, 1>;
2174 def M2_mpyu_lh_s1: T_M2_mpy<0b01, 0, 0, 1, 1>;
2175 def M2_mpyu_lh_s0: T_M2_mpy<0b01, 0, 0, 0, 1>;
2176 def M2_mpyu_hl_s1: T_M2_mpy<0b10, 0, 0, 1, 1>;
2177 def M2_mpyu_hl_s0: T_M2_mpy<0b10, 0, 0, 0, 1>;
2178 def M2_mpyu_hh_s1: T_M2_mpy<0b11, 0, 0, 1, 1>;
2179 def M2_mpyu_hh_s0: T_M2_mpy<0b11, 0, 0, 0, 1>;
2182 //Rd=mpy(Rs.[H|L],Rt.[H|L])[:<<1]:rnd
2183 let isCodeGenOnly = 0 in {
2184 def M2_mpy_rnd_ll_s1: T_M2_mpy <0b00, 0, 1, 1, 0>;
2185 def M2_mpy_rnd_ll_s0: T_M2_mpy <0b00, 0, 1, 0, 0>;
2186 def M2_mpy_rnd_lh_s1: T_M2_mpy <0b01, 0, 1, 1, 0>;
2187 def M2_mpy_rnd_lh_s0: T_M2_mpy <0b01, 0, 1, 0, 0>;
2188 def M2_mpy_rnd_hl_s1: T_M2_mpy <0b10, 0, 1, 1, 0>;
2189 def M2_mpy_rnd_hl_s0: T_M2_mpy <0b10, 0, 1, 0, 0>;
2190 def M2_mpy_rnd_hh_s1: T_M2_mpy <0b11, 0, 1, 1, 0>;
2191 def M2_mpy_rnd_hh_s0: T_M2_mpy <0b11, 0, 1, 0, 0>;
2194 //Rd=mpy(Rs.[H|L],Rt.[H|L])[:<<1][:sat]
2195 //Rd=mpy(Rs.[H|L],Rt.[H|L])[:<<1][:rnd][:sat]
2196 let Defs = [USR_OVF], isCodeGenOnly = 0 in {
2197 def M2_mpy_sat_ll_s1: T_M2_mpy <0b00, 1, 0, 1, 0>;
2198 def M2_mpy_sat_ll_s0: T_M2_mpy <0b00, 1, 0, 0, 0>;
2199 def M2_mpy_sat_lh_s1: T_M2_mpy <0b01, 1, 0, 1, 0>;
2200 def M2_mpy_sat_lh_s0: T_M2_mpy <0b01, 1, 0, 0, 0>;
2201 def M2_mpy_sat_hl_s1: T_M2_mpy <0b10, 1, 0, 1, 0>;
2202 def M2_mpy_sat_hl_s0: T_M2_mpy <0b10, 1, 0, 0, 0>;
2203 def M2_mpy_sat_hh_s1: T_M2_mpy <0b11, 1, 0, 1, 0>;
2204 def M2_mpy_sat_hh_s0: T_M2_mpy <0b11, 1, 0, 0, 0>;
2206 def M2_mpy_sat_rnd_ll_s1: T_M2_mpy <0b00, 1, 1, 1, 0>;
2207 def M2_mpy_sat_rnd_ll_s0: T_M2_mpy <0b00, 1, 1, 0, 0>;
2208 def M2_mpy_sat_rnd_lh_s1: T_M2_mpy <0b01, 1, 1, 1, 0>;
2209 def M2_mpy_sat_rnd_lh_s0: T_M2_mpy <0b01, 1, 1, 0, 0>;
2210 def M2_mpy_sat_rnd_hl_s1: T_M2_mpy <0b10, 1, 1, 1, 0>;
2211 def M2_mpy_sat_rnd_hl_s0: T_M2_mpy <0b10, 1, 1, 0, 0>;
2212 def M2_mpy_sat_rnd_hh_s1: T_M2_mpy <0b11, 1, 1, 1, 0>;
2213 def M2_mpy_sat_rnd_hh_s0: T_M2_mpy <0b11, 1, 1, 0, 0>;
2216 //===----------------------------------------------------------------------===//
2218 // MPYS / Multipy signed/unsigned halfwords and add/subtract the
2219 // result from the accumulator.
2220 //Rx [-+]= mpy[u](Rs.[H|L],Rt.[H|L])[:<<1][:sat]
2221 //===----------------------------------------------------------------------===//
2223 let hasNewValue = 1, opNewValue = 0 in
2224 class T_M2_mpy_acc < bits<2> LHbits, bit isSat, bit isNac,
2225 bit hasShift, bit isUnsigned >
2226 : MInst_acc<(outs IntRegs:$Rx), (ins IntRegs:$dst2, IntRegs:$Rs, IntRegs:$Rt),
2227 "$Rx "#!if(isNac,"-= ","+= ")#!if(isUnsigned,"mpyu","mpy")
2228 #"($Rs."#!if(LHbits{1},"h","l")
2229 #", $Rt."#!if(LHbits{0},"h)","l)")
2230 #!if(hasShift,":<<1","")
2231 #!if(isSat,":sat",""),
2232 [], "$dst2 = $Rx", M_tc_3x_SLOT23 > {
2237 let IClass = 0b1110;
2238 let Inst{27-24} = 0b1110;
2239 let Inst{23} = hasShift;
2240 let Inst{22} = isUnsigned;
2241 let Inst{21} = isNac;
2242 let Inst{7} = isSat;
2243 let Inst{6-5} = LHbits;
2245 let Inst{20-16} = Rs;
2246 let Inst{12-8} = Rt;
2249 //Rx += mpy(Rs.[H|L],Rt.[H|L])[:<<1]
2250 let isCodeGenOnly = 0 in {
2251 def M2_mpy_acc_ll_s1: T_M2_mpy_acc <0b00, 0, 0, 1, 0>;
2252 def M2_mpy_acc_ll_s0: T_M2_mpy_acc <0b00, 0, 0, 0, 0>;
2253 def M2_mpy_acc_lh_s1: T_M2_mpy_acc <0b01, 0, 0, 1, 0>;
2254 def M2_mpy_acc_lh_s0: T_M2_mpy_acc <0b01, 0, 0, 0, 0>;
2255 def M2_mpy_acc_hl_s1: T_M2_mpy_acc <0b10, 0, 0, 1, 0>;
2256 def M2_mpy_acc_hl_s0: T_M2_mpy_acc <0b10, 0, 0, 0, 0>;
2257 def M2_mpy_acc_hh_s1: T_M2_mpy_acc <0b11, 0, 0, 1, 0>;
2258 def M2_mpy_acc_hh_s0: T_M2_mpy_acc <0b11, 0, 0, 0, 0>;
2261 //Rx += mpyu(Rs.[H|L],Rt.[H|L])[:<<1]
2262 let isCodeGenOnly = 0 in {
2263 def M2_mpyu_acc_ll_s1: T_M2_mpy_acc <0b00, 0, 0, 1, 1>;
2264 def M2_mpyu_acc_ll_s0: T_M2_mpy_acc <0b00, 0, 0, 0, 1>;
2265 def M2_mpyu_acc_lh_s1: T_M2_mpy_acc <0b01, 0, 0, 1, 1>;
2266 def M2_mpyu_acc_lh_s0: T_M2_mpy_acc <0b01, 0, 0, 0, 1>;
2267 def M2_mpyu_acc_hl_s1: T_M2_mpy_acc <0b10, 0, 0, 1, 1>;
2268 def M2_mpyu_acc_hl_s0: T_M2_mpy_acc <0b10, 0, 0, 0, 1>;
2269 def M2_mpyu_acc_hh_s1: T_M2_mpy_acc <0b11, 0, 0, 1, 1>;
2270 def M2_mpyu_acc_hh_s0: T_M2_mpy_acc <0b11, 0, 0, 0, 1>;
2273 //Rx -= mpy(Rs.[H|L],Rt.[H|L])[:<<1]
2274 let isCodeGenOnly = 0 in {
2275 def M2_mpy_nac_ll_s1: T_M2_mpy_acc <0b00, 0, 1, 1, 0>;
2276 def M2_mpy_nac_ll_s0: T_M2_mpy_acc <0b00, 0, 1, 0, 0>;
2277 def M2_mpy_nac_lh_s1: T_M2_mpy_acc <0b01, 0, 1, 1, 0>;
2278 def M2_mpy_nac_lh_s0: T_M2_mpy_acc <0b01, 0, 1, 0, 0>;
2279 def M2_mpy_nac_hl_s1: T_M2_mpy_acc <0b10, 0, 1, 1, 0>;
2280 def M2_mpy_nac_hl_s0: T_M2_mpy_acc <0b10, 0, 1, 0, 0>;
2281 def M2_mpy_nac_hh_s1: T_M2_mpy_acc <0b11, 0, 1, 1, 0>;
2282 def M2_mpy_nac_hh_s0: T_M2_mpy_acc <0b11, 0, 1, 0, 0>;
2285 //Rx -= mpyu(Rs.[H|L],Rt.[H|L])[:<<1]
2286 let isCodeGenOnly = 0 in {
2287 def M2_mpyu_nac_ll_s1: T_M2_mpy_acc <0b00, 0, 1, 1, 1>;
2288 def M2_mpyu_nac_ll_s0: T_M2_mpy_acc <0b00, 0, 1, 0, 1>;
2289 def M2_mpyu_nac_lh_s1: T_M2_mpy_acc <0b01, 0, 1, 1, 1>;
2290 def M2_mpyu_nac_lh_s0: T_M2_mpy_acc <0b01, 0, 1, 0, 1>;
2291 def M2_mpyu_nac_hl_s1: T_M2_mpy_acc <0b10, 0, 1, 1, 1>;
2292 def M2_mpyu_nac_hl_s0: T_M2_mpy_acc <0b10, 0, 1, 0, 1>;
2293 def M2_mpyu_nac_hh_s1: T_M2_mpy_acc <0b11, 0, 1, 1, 1>;
2294 def M2_mpyu_nac_hh_s0: T_M2_mpy_acc <0b11, 0, 1, 0, 1>;
2297 //Rx += mpy(Rs.[H|L],Rt.[H|L])[:<<1]:sat
2298 let isCodeGenOnly = 0 in {
2299 def M2_mpy_acc_sat_ll_s1: T_M2_mpy_acc <0b00, 1, 0, 1, 0>;
2300 def M2_mpy_acc_sat_ll_s0: T_M2_mpy_acc <0b00, 1, 0, 0, 0>;
2301 def M2_mpy_acc_sat_lh_s1: T_M2_mpy_acc <0b01, 1, 0, 1, 0>;
2302 def M2_mpy_acc_sat_lh_s0: T_M2_mpy_acc <0b01, 1, 0, 0, 0>;
2303 def M2_mpy_acc_sat_hl_s1: T_M2_mpy_acc <0b10, 1, 0, 1, 0>;
2304 def M2_mpy_acc_sat_hl_s0: T_M2_mpy_acc <0b10, 1, 0, 0, 0>;
2305 def M2_mpy_acc_sat_hh_s1: T_M2_mpy_acc <0b11, 1, 0, 1, 0>;
2306 def M2_mpy_acc_sat_hh_s0: T_M2_mpy_acc <0b11, 1, 0, 0, 0>;
2309 //Rx -= mpy(Rs.[H|L],Rt.[H|L])[:<<1]:sat
2310 let isCodeGenOnly = 0 in {
2311 def M2_mpy_nac_sat_ll_s1: T_M2_mpy_acc <0b00, 1, 1, 1, 0>;
2312 def M2_mpy_nac_sat_ll_s0: T_M2_mpy_acc <0b00, 1, 1, 0, 0>;
2313 def M2_mpy_nac_sat_lh_s1: T_M2_mpy_acc <0b01, 1, 1, 1, 0>;
2314 def M2_mpy_nac_sat_lh_s0: T_M2_mpy_acc <0b01, 1, 1, 0, 0>;
2315 def M2_mpy_nac_sat_hl_s1: T_M2_mpy_acc <0b10, 1, 1, 1, 0>;
2316 def M2_mpy_nac_sat_hl_s0: T_M2_mpy_acc <0b10, 1, 1, 0, 0>;
2317 def M2_mpy_nac_sat_hh_s1: T_M2_mpy_acc <0b11, 1, 1, 1, 0>;
2318 def M2_mpy_nac_sat_hh_s0: T_M2_mpy_acc <0b11, 1, 1, 0, 0>;
2321 //===----------------------------------------------------------------------===//
2323 // MPYS / Multipy signed/unsigned halfwords and add/subtract the
2324 // result from the 64-bit destination register.
2325 //Rxx [-+]= mpy[u](Rs.[H|L],Rt.[H|L])[:<<1][:sat]
2326 //===----------------------------------------------------------------------===//
2328 class T_M2_mpyd_acc < bits<2> LHbits, bit isNac, bit hasShift, bit isUnsigned>
2329 : MInst_acc<(outs DoubleRegs:$Rxx),
2330 (ins DoubleRegs:$dst2, IntRegs:$Rs, IntRegs:$Rt),
2331 "$Rxx "#!if(isNac,"-= ","+= ")#!if(isUnsigned,"mpyu","mpy")
2332 #"($Rs."#!if(LHbits{1},"h","l")
2333 #", $Rt."#!if(LHbits{0},"h)","l)")
2334 #!if(hasShift,":<<1",""),
2335 [], "$dst2 = $Rxx", M_tc_3x_SLOT23 > {
2340 let IClass = 0b1110;
2342 let Inst{27-24} = 0b0110;
2343 let Inst{23} = hasShift;
2344 let Inst{22} = isUnsigned;
2345 let Inst{21} = isNac;
2347 let Inst{6-5} = LHbits;
2348 let Inst{4-0} = Rxx;
2349 let Inst{20-16} = Rs;
2350 let Inst{12-8} = Rt;
2353 let isCodeGenOnly = 0 in {
2354 def M2_mpyd_acc_hh_s0: T_M2_mpyd_acc <0b11, 0, 0, 0>;
2355 def M2_mpyd_acc_hl_s0: T_M2_mpyd_acc <0b10, 0, 0, 0>;
2356 def M2_mpyd_acc_lh_s0: T_M2_mpyd_acc <0b01, 0, 0, 0>;
2357 def M2_mpyd_acc_ll_s0: T_M2_mpyd_acc <0b00, 0, 0, 0>;
2359 def M2_mpyd_acc_hh_s1: T_M2_mpyd_acc <0b11, 0, 1, 0>;
2360 def M2_mpyd_acc_hl_s1: T_M2_mpyd_acc <0b10, 0, 1, 0>;
2361 def M2_mpyd_acc_lh_s1: T_M2_mpyd_acc <0b01, 0, 1, 0>;
2362 def M2_mpyd_acc_ll_s1: T_M2_mpyd_acc <0b00, 0, 1, 0>;
2364 def M2_mpyd_nac_hh_s0: T_M2_mpyd_acc <0b11, 1, 0, 0>;
2365 def M2_mpyd_nac_hl_s0: T_M2_mpyd_acc <0b10, 1, 0, 0>;
2366 def M2_mpyd_nac_lh_s0: T_M2_mpyd_acc <0b01, 1, 0, 0>;
2367 def M2_mpyd_nac_ll_s0: T_M2_mpyd_acc <0b00, 1, 0, 0>;
2369 def M2_mpyd_nac_hh_s1: T_M2_mpyd_acc <0b11, 1, 1, 0>;
2370 def M2_mpyd_nac_hl_s1: T_M2_mpyd_acc <0b10, 1, 1, 0>;
2371 def M2_mpyd_nac_lh_s1: T_M2_mpyd_acc <0b01, 1, 1, 0>;
2372 def M2_mpyd_nac_ll_s1: T_M2_mpyd_acc <0b00, 1, 1, 0>;
2374 def M2_mpyud_acc_hh_s0: T_M2_mpyd_acc <0b11, 0, 0, 1>;
2375 def M2_mpyud_acc_hl_s0: T_M2_mpyd_acc <0b10, 0, 0, 1>;
2376 def M2_mpyud_acc_lh_s0: T_M2_mpyd_acc <0b01, 0, 0, 1>;
2377 def M2_mpyud_acc_ll_s0: T_M2_mpyd_acc <0b00, 0, 0, 1>;
2379 def M2_mpyud_acc_hh_s1: T_M2_mpyd_acc <0b11, 0, 1, 1>;
2380 def M2_mpyud_acc_hl_s1: T_M2_mpyd_acc <0b10, 0, 1, 1>;
2381 def M2_mpyud_acc_lh_s1: T_M2_mpyd_acc <0b01, 0, 1, 1>;
2382 def M2_mpyud_acc_ll_s1: T_M2_mpyd_acc <0b00, 0, 1, 1>;
2384 def M2_mpyud_nac_hh_s0: T_M2_mpyd_acc <0b11, 1, 0, 1>;
2385 def M2_mpyud_nac_hl_s0: T_M2_mpyd_acc <0b10, 1, 0, 1>;
2386 def M2_mpyud_nac_lh_s0: T_M2_mpyd_acc <0b01, 1, 0, 1>;
2387 def M2_mpyud_nac_ll_s0: T_M2_mpyd_acc <0b00, 1, 0, 1>;
2389 def M2_mpyud_nac_hh_s1: T_M2_mpyd_acc <0b11, 1, 1, 1>;
2390 def M2_mpyud_nac_hl_s1: T_M2_mpyd_acc <0b10, 1, 1, 1>;
2391 def M2_mpyud_nac_lh_s1: T_M2_mpyd_acc <0b01, 1, 1, 1>;
2392 def M2_mpyud_nac_ll_s1: T_M2_mpyd_acc <0b00, 1, 1, 1>;
2395 let hasNewValue = 1, opNewValue = 0 in
2396 class T_MType_mpy <string mnemonic, bits<4> RegTyBits, RegisterClass RC,
2397 bits<3> MajOp, bits<3> MinOp, bit isSat = 0, bit isRnd = 0,
2398 string op2Suffix = "", bit isRaw = 0, bit isHi = 0 >
2399 : MInst <(outs IntRegs:$dst), (ins RC:$src1, RC:$src2),
2401 #"($src1, $src2"#op2Suffix#")"
2402 #!if(MajOp{2}, ":<<1", "")
2403 #!if(isRnd, ":rnd", "")
2404 #!if(isSat, ":sat", "")
2405 #!if(isRaw, !if(isHi, ":raw:hi", ":raw:lo"), ""), [] > {
2410 let IClass = 0b1110;
2412 let Inst{27-24} = RegTyBits;
2413 let Inst{23-21} = MajOp;
2414 let Inst{20-16} = src1;
2416 let Inst{12-8} = src2;
2417 let Inst{7-5} = MinOp;
2418 let Inst{4-0} = dst;
2421 class T_MType_dd <string mnemonic, bits<3> MajOp, bits<3> MinOp,
2422 bit isSat = 0, bit isRnd = 0 >
2423 : T_MType_mpy <mnemonic, 0b1001, DoubleRegs, MajOp, MinOp, isSat, isRnd>;
2425 class T_MType_rr1 <string mnemonic, bits<3> MajOp, bits<3> MinOp,
2426 bit isSat = 0, bit isRnd = 0 >
2427 : T_MType_mpy<mnemonic, 0b1101, IntRegs, MajOp, MinOp, isSat, isRnd>;
2429 class T_MType_rr2 <string mnemonic, bits<3> MajOp, bits<3> MinOp,
2430 bit isSat = 0, bit isRnd = 0, string op2str = "" >
2431 : T_MType_mpy<mnemonic, 0b1101, IntRegs, MajOp, MinOp, isSat, isRnd, op2str>;
2433 let CextOpcode = "mpyi", InputType = "reg", isCodeGenOnly = 0 in
2434 def M2_mpyi : T_MType_rr1 <"mpyi", 0b000, 0b000>, ImmRegRel;
2436 let isCodeGenOnly = 0 in {
2437 def M2_mpy_up : T_MType_rr1 <"mpy", 0b000, 0b001>;
2438 def M2_mpyu_up : T_MType_rr1 <"mpyu", 0b010, 0b001>;
2441 let isCodeGenOnly = 0 in
2442 def M2_dpmpyss_rnd_s0 : T_MType_rr1 <"mpy", 0b001, 0b001, 0, 1>;
2444 let isCodeGenOnly = 0 in {
2445 def M2_hmmpyh_rs1 : T_MType_rr2 <"mpy", 0b101, 0b100, 1, 1, ".h">;
2446 def M2_hmmpyl_rs1 : T_MType_rr2 <"mpy", 0b111, 0b100, 1, 1, ".l">;
2450 let isCodeGenOnly = 0 in {
2451 def M2_mpysu_up : T_MType_rr1 <"mpysu", 0b011, 0b001, 0>;
2452 def M2_mpy_up_s1 : T_MType_rr1 <"mpy", 0b101, 0b010, 0>;
2453 def M2_mpy_up_s1_sat : T_MType_rr1 <"mpy", 0b111, 0b000, 1>;
2455 def M2_hmmpyh_s1 : T_MType_rr2 <"mpy", 0b101, 0b000, 1, 0, ".h">;
2456 def M2_hmmpyl_s1 : T_MType_rr2 <"mpy", 0b101, 0b001, 1, 0, ".l">;
2459 def: Pat<(i32 (mul I32:$src1, I32:$src2)), (M2_mpyi I32:$src1, I32:$src2)>;
2460 def: Pat<(i32 (mulhs I32:$src1, I32:$src2)), (M2_mpy_up I32:$src1, I32:$src2)>;
2461 def: Pat<(i32 (mulhu I32:$src1, I32:$src2)), (M2_mpyu_up I32:$src1, I32:$src2)>;
2463 let hasNewValue = 1, opNewValue = 0 in
2464 class T_MType_mpy_ri <bit isNeg, Operand ImmOp, list<dag> pattern>
2465 : MInst < (outs IntRegs:$Rd), (ins IntRegs:$Rs, ImmOp:$u8),
2466 "$Rd ="#!if(isNeg, "- ", "+ ")#"mpyi($Rs, #$u8)" ,
2467 pattern, "", M_tc_3x_SLOT23> {
2472 let IClass = 0b1110;
2474 let Inst{27-24} = 0b0000;
2475 let Inst{23} = isNeg;
2478 let Inst{20-16} = Rs;
2479 let Inst{12-5} = u8;
2482 let isExtendable = 1, opExtentBits = 8, opExtendable = 2, isCodeGenOnly = 0 in
2483 def M2_mpysip : T_MType_mpy_ri <0, u8Ext,
2484 [(set (i32 IntRegs:$Rd), (mul IntRegs:$Rs, u8ExtPred:$u8))]>;
2486 let isCodeGenOnly = 0 in
2487 def M2_mpysin : T_MType_mpy_ri <1, u8Imm,
2488 [(set (i32 IntRegs:$Rd), (ineg (mul IntRegs:$Rs,
2491 // Assember mapped to M2_mpyi
2492 let isAsmParserOnly = 1 in
2493 def M2_mpyui : MInst<(outs IntRegs:$dst),
2494 (ins IntRegs:$src1, IntRegs:$src2),
2495 "$dst = mpyui($src1, $src2)">;
2498 // s9 is NOT the same as m9 - but it works.. so far.
2499 // Assembler maps to either Rd=+mpyi(Rs,#u8) or Rd=-mpyi(Rs,#u8)
2500 // depending on the value of m9. See Arch Spec.
2501 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 9,
2502 CextOpcode = "mpyi", InputType = "imm", hasNewValue = 1 in
2503 def M2_mpysmi : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, s9Ext:$src2),
2504 "$dst = mpyi($src1, #$src2)",
2505 [(set (i32 IntRegs:$dst), (mul (i32 IntRegs:$src1),
2506 s9ExtPred:$src2))]>, ImmRegRel;
2508 let hasNewValue = 1, isExtendable = 1, opExtentBits = 8, opExtendable = 3,
2509 InputType = "imm" in
2510 class T_MType_acc_ri <string mnemonic, bits<3> MajOp, Operand ImmOp,
2511 list<dag> pattern = []>
2512 : MInst < (outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2, ImmOp:$src3),
2513 "$dst "#mnemonic#"($src2, #$src3)",
2514 pattern, "$src1 = $dst", M_tc_2_SLOT23> {
2519 let IClass = 0b1110;
2521 let Inst{27-26} = 0b00;
2522 let Inst{25-23} = MajOp;
2523 let Inst{20-16} = src2;
2525 let Inst{12-5} = src3;
2526 let Inst{4-0} = dst;
2529 let InputType = "reg", hasNewValue = 1 in
2530 class T_MType_acc_rr <string mnemonic, bits<3> MajOp, bits<3> MinOp,
2531 bit isSwap = 0, list<dag> pattern = [], bit hasNot = 0,
2532 bit isSat = 0, bit isShift = 0>
2533 : MInst < (outs IntRegs:$dst),
2534 (ins IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
2535 "$dst "#mnemonic#"($src2, "#!if(hasNot, "~$src3)","$src3)")
2536 #!if(isShift, ":<<1", "")
2537 #!if(isSat, ":sat", ""),
2538 pattern, "$src1 = $dst", M_tc_2_SLOT23 > {
2543 let IClass = 0b1110;
2545 let Inst{27-24} = 0b1111;
2546 let Inst{23-21} = MajOp;
2547 let Inst{20-16} = !if(isSwap, src3, src2);
2549 let Inst{12-8} = !if(isSwap, src2, src3);
2550 let Inst{7-5} = MinOp;
2551 let Inst{4-0} = dst;
2554 let CextOpcode = "MPYI_acc", Itinerary = M_tc_3x_SLOT23, isCodeGenOnly = 0 in {
2555 def M2_macsip : T_MType_acc_ri <"+= mpyi", 0b010, u8Ext,
2556 [(set (i32 IntRegs:$dst),
2557 (add (mul IntRegs:$src2, u8ExtPred:$src3),
2558 IntRegs:$src1))]>, ImmRegRel;
2560 def M2_maci : T_MType_acc_rr <"+= mpyi", 0b000, 0b000, 0,
2561 [(set (i32 IntRegs:$dst),
2562 (add (mul IntRegs:$src2, IntRegs:$src3),
2563 IntRegs:$src1))]>, ImmRegRel;
2566 let CextOpcode = "ADD_acc", isCodeGenOnly = 0 in {
2567 let isExtentSigned = 1 in
2568 def M2_accii : T_MType_acc_ri <"+= add", 0b100, s8Ext,
2569 [(set (i32 IntRegs:$dst),
2570 (add (add (i32 IntRegs:$src2), s8_16ExtPred:$src3),
2571 (i32 IntRegs:$src1)))]>, ImmRegRel;
2573 def M2_acci : T_MType_acc_rr <"+= add", 0b000, 0b001, 0,
2574 [(set (i32 IntRegs:$dst),
2575 (add (add (i32 IntRegs:$src2), (i32 IntRegs:$src3)),
2576 (i32 IntRegs:$src1)))]>, ImmRegRel;
2579 let CextOpcode = "SUB_acc", isCodeGenOnly = 0 in {
2580 let isExtentSigned = 1 in
2581 def M2_naccii : T_MType_acc_ri <"-= add", 0b101, s8Ext>, ImmRegRel;
2583 def M2_nacci : T_MType_acc_rr <"-= add", 0b100, 0b001, 0>, ImmRegRel;
2586 let Itinerary = M_tc_3x_SLOT23, isCodeGenOnly = 0 in
2587 def M2_macsin : T_MType_acc_ri <"-= mpyi", 0b011, u8Ext>;
2589 let isCodeGenOnly = 0 in {
2590 def M2_xor_xacc : T_MType_acc_rr < "^= xor", 0b100, 0b011, 0>;
2591 def M2_subacc : T_MType_acc_rr <"+= sub", 0b000, 0b011, 1>;
2594 class T_MType_acc_pat1 <InstHexagon MI, SDNode firstOp, SDNode secOp,
2596 : Pat <(secOp IntRegs:$src1, (firstOp IntRegs:$src2, ImmPred:$src3)),
2597 (MI IntRegs:$src1, IntRegs:$src2, ImmPred:$src3)>;
2599 class T_MType_acc_pat2 <InstHexagon MI, SDNode firstOp, SDNode secOp>
2600 : Pat <(i32 (secOp IntRegs:$src1, (firstOp IntRegs:$src2, IntRegs:$src3))),
2601 (MI IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
2603 def : T_MType_acc_pat2 <M2_xor_xacc, xor, xor>;
2604 def : T_MType_acc_pat1 <M2_macsin, mul, sub, u8ExtPred>;
2606 def : T_MType_acc_pat1 <M2_naccii, add, sub, s8_16ExtPred>;
2607 def : T_MType_acc_pat2 <M2_nacci, add, sub>;
2608 //===----------------------------------------------------------------------===//
2609 // Template Class -- Multiply signed/unsigned halfwords with and without
2610 // saturation and rounding
2611 //===----------------------------------------------------------------------===//
2612 class T_M2_mpyd < bits<2> LHbits, bit isRnd, bit hasShift, bit isUnsigned >
2613 : MInst < (outs DoubleRegs:$Rdd), (ins IntRegs:$Rs, IntRegs:$Rt),
2614 "$Rdd = "#!if(isUnsigned,"mpyu","mpy")#"($Rs."#!if(LHbits{1},"h","l")
2615 #", $Rt."#!if(LHbits{0},"h)","l)")
2616 #!if(hasShift,":<<1","")
2617 #!if(isRnd,":rnd",""),
2623 let IClass = 0b1110;
2625 let Inst{27-24} = 0b0100;
2626 let Inst{23} = hasShift;
2627 let Inst{22} = isUnsigned;
2628 let Inst{21} = isRnd;
2629 let Inst{6-5} = LHbits;
2630 let Inst{4-0} = Rdd;
2631 let Inst{20-16} = Rs;
2632 let Inst{12-8} = Rt;
2635 let isCodeGenOnly = 0 in {
2636 def M2_mpyd_hh_s0: T_M2_mpyd<0b11, 0, 0, 0>;
2637 def M2_mpyd_hl_s0: T_M2_mpyd<0b10, 0, 0, 0>;
2638 def M2_mpyd_lh_s0: T_M2_mpyd<0b01, 0, 0, 0>;
2639 def M2_mpyd_ll_s0: T_M2_mpyd<0b00, 0, 0, 0>;
2641 def M2_mpyd_hh_s1: T_M2_mpyd<0b11, 0, 1, 0>;
2642 def M2_mpyd_hl_s1: T_M2_mpyd<0b10, 0, 1, 0>;
2643 def M2_mpyd_lh_s1: T_M2_mpyd<0b01, 0, 1, 0>;
2644 def M2_mpyd_ll_s1: T_M2_mpyd<0b00, 0, 1, 0>;
2646 def M2_mpyd_rnd_hh_s0: T_M2_mpyd<0b11, 1, 0, 0>;
2647 def M2_mpyd_rnd_hl_s0: T_M2_mpyd<0b10, 1, 0, 0>;
2648 def M2_mpyd_rnd_lh_s0: T_M2_mpyd<0b01, 1, 0, 0>;
2649 def M2_mpyd_rnd_ll_s0: T_M2_mpyd<0b00, 1, 0, 0>;
2651 def M2_mpyd_rnd_hh_s1: T_M2_mpyd<0b11, 1, 1, 0>;
2652 def M2_mpyd_rnd_hl_s1: T_M2_mpyd<0b10, 1, 1, 0>;
2653 def M2_mpyd_rnd_lh_s1: T_M2_mpyd<0b01, 1, 1, 0>;
2654 def M2_mpyd_rnd_ll_s1: T_M2_mpyd<0b00, 1, 1, 0>;
2656 //Rdd=mpyu(Rs.[HL],Rt.[HL])[:<<1]
2657 def M2_mpyud_hh_s0: T_M2_mpyd<0b11, 0, 0, 1>;
2658 def M2_mpyud_hl_s0: T_M2_mpyd<0b10, 0, 0, 1>;
2659 def M2_mpyud_lh_s0: T_M2_mpyd<0b01, 0, 0, 1>;
2660 def M2_mpyud_ll_s0: T_M2_mpyd<0b00, 0, 0, 1>;
2662 def M2_mpyud_hh_s1: T_M2_mpyd<0b11, 0, 1, 1>;
2663 def M2_mpyud_hl_s1: T_M2_mpyd<0b10, 0, 1, 1>;
2664 def M2_mpyud_lh_s1: T_M2_mpyd<0b01, 0, 1, 1>;
2665 def M2_mpyud_ll_s1: T_M2_mpyd<0b00, 0, 1, 1>;
2667 //===----------------------------------------------------------------------===//
2668 // Template Class for xtype mpy:
2671 // multiply 32X32 and use full result
2672 //===----------------------------------------------------------------------===//
2673 let hasSideEffects = 0 in
2674 class T_XTYPE_mpy64 <string mnemonic, bits<3> MajOp, bits<3> MinOp,
2675 bit isSat, bit hasShift, bit isConj>
2676 : MInst <(outs DoubleRegs:$Rdd),
2677 (ins IntRegs:$Rs, IntRegs:$Rt),
2678 "$Rdd = "#mnemonic#"($Rs, $Rt"#!if(isConj,"*)",")")
2679 #!if(hasShift,":<<1","")
2680 #!if(isSat,":sat",""),
2686 let IClass = 0b1110;
2688 let Inst{27-24} = 0b0101;
2689 let Inst{23-21} = MajOp;
2690 let Inst{20-16} = Rs;
2691 let Inst{12-8} = Rt;
2692 let Inst{7-5} = MinOp;
2693 let Inst{4-0} = Rdd;
2696 //===----------------------------------------------------------------------===//
2697 // Template Class for xtype mpy with accumulation into 64-bit:
2700 // multiply 32X32 and use full result
2701 //===----------------------------------------------------------------------===//
2702 class T_XTYPE_mpy64_acc <string op1, string op2, bits<3> MajOp, bits<3> MinOp,
2703 bit isSat, bit hasShift, bit isConj>
2704 : MInst <(outs DoubleRegs:$Rxx),
2705 (ins DoubleRegs:$dst2, IntRegs:$Rs, IntRegs:$Rt),
2706 "$Rxx "#op2#"= "#op1#"($Rs, $Rt"#!if(isConj,"*)",")")
2707 #!if(hasShift,":<<1","")
2708 #!if(isSat,":sat",""),
2710 [] , "$dst2 = $Rxx" > {
2715 let IClass = 0b1110;
2717 let Inst{27-24} = 0b0111;
2718 let Inst{23-21} = MajOp;
2719 let Inst{20-16} = Rs;
2720 let Inst{12-8} = Rt;
2721 let Inst{7-5} = MinOp;
2722 let Inst{4-0} = Rxx;
2725 // MPY - Multiply and use full result
2726 // Rdd = mpy[u](Rs,Rt)
2727 let isCodeGenOnly = 0 in {
2728 def M2_dpmpyss_s0 : T_XTYPE_mpy64 < "mpy", 0b000, 0b000, 0, 0, 0>;
2729 def M2_dpmpyuu_s0 : T_XTYPE_mpy64 < "mpyu", 0b010, 0b000, 0, 0, 0>;
2731 // Rxx[+-]= mpy[u](Rs,Rt)
2732 def M2_dpmpyss_acc_s0 : T_XTYPE_mpy64_acc < "mpy", "+", 0b000, 0b000, 0, 0, 0>;
2733 def M2_dpmpyss_nac_s0 : T_XTYPE_mpy64_acc < "mpy", "-", 0b001, 0b000, 0, 0, 0>;
2734 def M2_dpmpyuu_acc_s0 : T_XTYPE_mpy64_acc < "mpyu", "+", 0b010, 0b000, 0, 0, 0>;
2735 def M2_dpmpyuu_nac_s0 : T_XTYPE_mpy64_acc < "mpyu", "-", 0b011, 0b000, 0, 0, 0>;
2738 def: Pat<(i64 (mul (i64 (anyext (i32 IntRegs:$src1))),
2739 (i64 (anyext (i32 IntRegs:$src2))))),
2740 (M2_dpmpyuu_s0 IntRegs:$src1, IntRegs:$src2)>;
2742 def: Pat<(i64 (mul (i64 (sext (i32 IntRegs:$src1))),
2743 (i64 (sext (i32 IntRegs:$src2))))),
2744 (M2_dpmpyss_s0 IntRegs:$src1, IntRegs:$src2)>;
2746 def: Pat<(i64 (mul (is_sext_i32:$src1),
2747 (is_sext_i32:$src2))),
2748 (M2_dpmpyss_s0 (LoReg DoubleRegs:$src1), (LoReg DoubleRegs:$src2))>;
2750 // Multiply and accumulate, use full result.
2751 // Rxx[+-]=mpy(Rs,Rt)
2753 def: Pat<(i64 (add (i64 DoubleRegs:$src1),
2754 (mul (i64 (sext (i32 IntRegs:$src2))),
2755 (i64 (sext (i32 IntRegs:$src3)))))),
2756 (M2_dpmpyss_acc_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
2758 def: Pat<(i64 (sub (i64 DoubleRegs:$src1),
2759 (mul (i64 (sext (i32 IntRegs:$src2))),
2760 (i64 (sext (i32 IntRegs:$src3)))))),
2761 (M2_dpmpyss_nac_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
2763 def: Pat<(i64 (add (i64 DoubleRegs:$src1),
2764 (mul (i64 (anyext (i32 IntRegs:$src2))),
2765 (i64 (anyext (i32 IntRegs:$src3)))))),
2766 (M2_dpmpyuu_acc_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
2768 def: Pat<(i64 (add (i64 DoubleRegs:$src1),
2769 (mul (i64 (zext (i32 IntRegs:$src2))),
2770 (i64 (zext (i32 IntRegs:$src3)))))),
2771 (M2_dpmpyuu_acc_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
2773 def: Pat<(i64 (sub (i64 DoubleRegs:$src1),
2774 (mul (i64 (anyext (i32 IntRegs:$src2))),
2775 (i64 (anyext (i32 IntRegs:$src3)))))),
2776 (M2_dpmpyuu_nac_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
2778 def: Pat<(i64 (sub (i64 DoubleRegs:$src1),
2779 (mul (i64 (zext (i32 IntRegs:$src2))),
2780 (i64 (zext (i32 IntRegs:$src3)))))),
2781 (M2_dpmpyuu_nac_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
2783 //===----------------------------------------------------------------------===//
2785 //===----------------------------------------------------------------------===//
2787 //===----------------------------------------------------------------------===//
2789 //===----------------------------------------------------------------------===//
2790 //===----------------------------------------------------------------------===//
2792 //===----------------------------------------------------------------------===//
2794 //===----------------------------------------------------------------------===//
2796 //===----------------------------------------------------------------------===//
2797 //===----------------------------------------------------------------------===//
2799 //===----------------------------------------------------------------------===//
2801 //===----------------------------------------------------------------------===//
2803 //===----------------------------------------------------------------------===//
2804 //===----------------------------------------------------------------------===//
2806 //===----------------------------------------------------------------------===//
2808 //===----------------------------------------------------------------------===//
2810 //===----------------------------------------------------------------------===//
2812 // Store doubleword.
2813 //===----------------------------------------------------------------------===//
2814 // Template class for non-predicated post increment stores with immediate offset
2815 //===----------------------------------------------------------------------===//
2816 let isPredicable = 1, hasSideEffects = 0, addrMode = PostInc in
2817 class T_store_pi <string mnemonic, RegisterClass RC, Operand ImmOp,
2818 bits<4> MajOp, bit isHalf >
2819 : STInst <(outs IntRegs:$_dst_),
2820 (ins IntRegs:$src1, ImmOp:$offset, RC:$src2),
2821 mnemonic#"($src1++#$offset) = $src2"#!if(isHalf, ".h", ""),
2822 [], "$src1 = $_dst_" >,
2829 string ImmOpStr = !cast<string>(ImmOp);
2830 let offsetBits = !if (!eq(ImmOpStr, "s4_3Imm"), offset{6-3},
2831 !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2},
2832 !if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1},
2833 /* s4_0Imm */ offset{3-0})));
2834 let isNVStorable = !if (!eq(ImmOpStr, "s4_3Imm"), 0, 1);
2836 let IClass = 0b1010;
2838 let Inst{27-25} = 0b101;
2839 let Inst{24-21} = MajOp;
2840 let Inst{20-16} = src1;
2842 let Inst{12-8} = src2;
2844 let Inst{6-3} = offsetBits;
2848 //===----------------------------------------------------------------------===//
2849 // Template class for predicated post increment stores with immediate offset
2850 //===----------------------------------------------------------------------===//
2851 let isPredicated = 1, hasSideEffects = 0, addrMode = PostInc in
2852 class T_pstore_pi <string mnemonic, RegisterClass RC, Operand ImmOp,
2853 bits<4> MajOp, bit isHalf, bit isPredNot, bit isPredNew >
2854 : STInst <(outs IntRegs:$_dst_),
2855 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset, RC:$src3),
2856 !if(isPredNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
2857 ") ")#mnemonic#"($src2++#$offset) = $src3"#!if(isHalf, ".h", ""),
2858 [], "$src2 = $_dst_" >,
2866 string ImmOpStr = !cast<string>(ImmOp);
2867 let offsetBits = !if (!eq(ImmOpStr, "s4_3Imm"), offset{6-3},
2868 !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2},
2869 !if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1},
2870 /* s4_0Imm */ offset{3-0})));
2872 let isNVStorable = !if (!eq(ImmOpStr, "s4_3Imm"), 0, 1);
2873 let isPredicatedNew = isPredNew;
2874 let isPredicatedFalse = isPredNot;
2876 let IClass = 0b1010;
2878 let Inst{27-25} = 0b101;
2879 let Inst{24-21} = MajOp;
2880 let Inst{20-16} = src2;
2882 let Inst{12-8} = src3;
2883 let Inst{7} = isPredNew;
2884 let Inst{6-3} = offsetBits;
2885 let Inst{2} = isPredNot;
2886 let Inst{1-0} = src1;
2889 multiclass ST_PostInc<string mnemonic, string BaseOp, RegisterClass RC,
2890 Operand ImmOp, bits<4> MajOp, bit isHalf = 0 > {
2892 let BaseOpcode = "POST_"#BaseOp in {
2893 def S2_#NAME#_pi : T_store_pi <mnemonic, RC, ImmOp, MajOp, isHalf>;
2896 def S2_p#NAME#t_pi : T_pstore_pi <mnemonic, RC, ImmOp, MajOp, isHalf, 0, 0>;
2897 def S2_p#NAME#f_pi : T_pstore_pi <mnemonic, RC, ImmOp, MajOp, isHalf, 1, 0>;
2900 def S2_p#NAME#tnew_pi : T_pstore_pi <mnemonic, RC, ImmOp, MajOp,
2902 def S2_p#NAME#fnew_pi : T_pstore_pi <mnemonic, RC, ImmOp, MajOp,
2907 let accessSize = ByteAccess, isCodeGenOnly = 0 in
2908 defm storerb: ST_PostInc <"memb", "STrib", IntRegs, s4_0Imm, 0b1000>;
2910 let accessSize = HalfWordAccess, isCodeGenOnly = 0 in
2911 defm storerh: ST_PostInc <"memh", "STrih", IntRegs, s4_1Imm, 0b1010>;
2913 let accessSize = WordAccess, isCodeGenOnly = 0 in
2914 defm storeri: ST_PostInc <"memw", "STriw", IntRegs, s4_2Imm, 0b1100>;
2916 let accessSize = DoubleWordAccess, isCodeGenOnly = 0 in
2917 defm storerd: ST_PostInc <"memd", "STrid", DoubleRegs, s4_3Imm, 0b1110>;
2919 let accessSize = HalfWordAccess, isNVStorable = 0, isCodeGenOnly = 0 in
2920 defm storerf: ST_PostInc <"memh", "STrih_H", IntRegs, s4_1Imm, 0b1011, 1>;
2922 // Patterns for generating stores, where the address takes different forms:
2925 // - simple (base address without offset).
2926 // These would usually be used together (via Storex_pat defined below), but
2927 // in some cases one may want to apply different properties (such as
2928 // AddedComplexity) to the individual patterns.
2929 class Storex_fi_pat<PatFrag Store, PatFrag Value, InstHexagon MI>
2930 : Pat<(Store Value:$Rs, AddrFI:$fi), (MI AddrFI:$fi, 0, Value:$Rs)>;
2931 class Storex_add_pat<PatFrag Store, PatFrag Value, PatFrag ImmPred,
2933 : Pat<(Store Value:$Rt, (add (i32 IntRegs:$Rs), ImmPred:$Off)),
2934 (MI IntRegs:$Rs, imm:$Off, Value:$Rt)>;
2936 multiclass Storex_pat<PatFrag Store, PatFrag Value, PatLeaf ImmPred,
2938 def: Storex_fi_pat <Store, Value, MI>;
2939 def: Storex_add_pat <Store, Value, ImmPred, MI>;
2942 def : Pat<(post_truncsti8 (i32 IntRegs:$src1), IntRegs:$src2,
2943 s4_3ImmPred:$offset),
2944 (S2_storerb_pi IntRegs:$src2, s4_0ImmPred:$offset, IntRegs:$src1)>;
2946 def : Pat<(post_truncsti16 (i32 IntRegs:$src1), IntRegs:$src2,
2947 s4_3ImmPred:$offset),
2948 (S2_storerh_pi IntRegs:$src2, s4_1ImmPred:$offset, IntRegs:$src1)>;
2950 def : Pat<(post_store (i32 IntRegs:$src1), IntRegs:$src2, s4_2ImmPred:$offset),
2951 (S2_storeri_pi IntRegs:$src2, s4_1ImmPred:$offset, IntRegs:$src1)>;
2953 def : Pat<(post_store (i64 DoubleRegs:$src1), IntRegs:$src2,
2954 s4_3ImmPred:$offset),
2955 (S2_storerd_pi IntRegs:$src2, s4_3ImmPred:$offset, DoubleRegs:$src1)>;
2957 //===----------------------------------------------------------------------===//
2958 // Template class for post increment stores with register offset.
2959 //===----------------------------------------------------------------------===//
2960 let isNVStorable = 1 in
2961 class T_store_pr <string mnemonic, RegisterClass RC, bits<3> MajOp,
2962 MemAccessSize AccessSz, bit isHalf = 0>
2963 : STInst <(outs IntRegs:$_dst_),
2964 (ins IntRegs:$src1, ModRegs:$src2, RC:$src3),
2965 mnemonic#"($src1++$src2) = $src3"#!if(isHalf, ".h", ""),
2966 [], "$src1 = $_dst_" > {
2970 let accessSize = AccessSz;
2972 let IClass = 0b1010;
2974 let Inst{27-24} = 0b1101;
2975 let Inst{23-21} = MajOp;
2976 let Inst{20-16} = src1;
2977 let Inst{13} = src2;
2978 let Inst{12-8} = src3;
2982 let isCodeGenOnly = 0 in {
2983 def S2_storerb_pr : T_store_pr<"memb", IntRegs, 0b000, ByteAccess>;
2984 def S2_storerh_pr : T_store_pr<"memh", IntRegs, 0b010, HalfWordAccess>;
2985 def S2_storeri_pr : T_store_pr<"memw", IntRegs, 0b100, WordAccess>;
2986 def S2_storerd_pr : T_store_pr<"memd", DoubleRegs, 0b110, DoubleWordAccess>;
2988 def S2_storerf_pr : T_store_pr<"memh", IntRegs, 0b011, HalfWordAccess, 1>;
2990 let opExtendable = 1, isExtentSigned = 1, isPredicable = 1 in
2991 class T_store_io <string mnemonic, RegisterClass RC, Operand ImmOp,
2992 bits<3>MajOp, bit isH = 0>
2994 (ins IntRegs:$src1, ImmOp:$src2, RC:$src3),
2995 mnemonic#"($src1+#$src2) = $src3"#!if(isH,".h","")>,
2996 AddrModeRel, ImmRegRel {
2998 bits<14> src2; // Actual address offset
3000 bits<11> offsetBits; // Represents offset encoding
3002 string ImmOpStr = !cast<string>(ImmOp);
3004 let opExtentBits = !if (!eq(ImmOpStr, "s11_3Ext"), 14,
3005 !if (!eq(ImmOpStr, "s11_2Ext"), 13,
3006 !if (!eq(ImmOpStr, "s11_1Ext"), 12,
3007 /* s11_0Ext */ 11)));
3008 let offsetBits = !if (!eq(ImmOpStr, "s11_3Ext"), src2{13-3},
3009 !if (!eq(ImmOpStr, "s11_2Ext"), src2{12-2},
3010 !if (!eq(ImmOpStr, "s11_1Ext"), src2{11-1},
3011 /* s11_0Ext */ src2{10-0})));
3012 let IClass = 0b1010;
3015 let Inst{26-25} = offsetBits{10-9};
3017 let Inst{23-21} = MajOp;
3018 let Inst{20-16} = src1;
3019 let Inst{13} = offsetBits{8};
3020 let Inst{12-8} = src3;
3021 let Inst{7-0} = offsetBits{7-0};
3024 let opExtendable = 2, isPredicated = 1 in
3025 class T_pstore_io <string mnemonic, RegisterClass RC, Operand ImmOp,
3026 bits<3>MajOp, bit PredNot, bit isPredNew, bit isH = 0>
3028 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$src3, RC:$src4),
3029 !if(PredNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
3030 ") ")#mnemonic#"($src2+#$src3) = $src4"#!if(isH,".h",""),
3031 [],"",V2LDST_tc_st_SLOT01 >,
3032 AddrModeRel, ImmRegRel {
3035 bits<9> src3; // Actual address offset
3037 bits<6> offsetBits; // Represents offset encoding
3039 let isPredicatedNew = isPredNew;
3040 let isPredicatedFalse = PredNot;
3042 string ImmOpStr = !cast<string>(ImmOp);
3043 let opExtentBits = !if (!eq(ImmOpStr, "u6_3Ext"), 9,
3044 !if (!eq(ImmOpStr, "u6_2Ext"), 8,
3045 !if (!eq(ImmOpStr, "u6_1Ext"), 7,
3047 let offsetBits = !if (!eq(ImmOpStr, "u6_3Ext"), src3{8-3},
3048 !if (!eq(ImmOpStr, "u6_2Ext"), src3{7-2},
3049 !if (!eq(ImmOpStr, "u6_1Ext"), src3{6-1},
3050 /* u6_0Ext */ src3{5-0})));
3051 let IClass = 0b0100;
3054 let Inst{26} = PredNot;
3055 let Inst{25} = isPredNew;
3057 let Inst{23-21} = MajOp;
3058 let Inst{20-16} = src2;
3059 let Inst{13} = offsetBits{5};
3060 let Inst{12-8} = src4;
3061 let Inst{7-3} = offsetBits{4-0};
3062 let Inst{1-0} = src1;
3065 let isExtendable = 1, isNVStorable = 1, hasSideEffects = 0 in
3066 multiclass ST_Idxd<string mnemonic, string CextOp, RegisterClass RC,
3067 Operand ImmOp, Operand predImmOp, bits<3> MajOp, bit isH = 0> {
3068 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed in {
3069 def S2_#NAME#_io : T_store_io <mnemonic, RC, ImmOp, MajOp, isH>;
3072 def S2_p#NAME#t_io : T_pstore_io<mnemonic, RC, predImmOp, MajOp, 0, 0, isH>;
3073 def S2_p#NAME#f_io : T_pstore_io<mnemonic, RC, predImmOp, MajOp, 1, 0, isH>;
3076 def S4_p#NAME#tnew_io : T_pstore_io <mnemonic, RC, predImmOp,
3078 def S4_p#NAME#fnew_io : T_pstore_io <mnemonic, RC, predImmOp,
3083 let addrMode = BaseImmOffset, InputType = "imm", isCodeGenOnly = 0 in {
3084 let accessSize = ByteAccess in
3085 defm storerb: ST_Idxd < "memb", "STrib", IntRegs, s11_0Ext, u6_0Ext, 0b000>;
3087 let accessSize = HalfWordAccess, opExtentAlign = 1 in
3088 defm storerh: ST_Idxd < "memh", "STrih", IntRegs, s11_1Ext, u6_1Ext, 0b010>;
3090 let accessSize = WordAccess, opExtentAlign = 2 in
3091 defm storeri: ST_Idxd < "memw", "STriw", IntRegs, s11_2Ext, u6_2Ext, 0b100>;
3093 let accessSize = DoubleWordAccess, isNVStorable = 0, opExtentAlign = 3 in
3094 defm storerd: ST_Idxd < "memd", "STrid", DoubleRegs, s11_3Ext,
3097 let accessSize = HalfWordAccess, opExtentAlign = 1 in
3098 defm storerf: ST_Idxd < "memh", "STrif", IntRegs, s11_1Ext,
3102 class Storex_simple_pat<PatFrag Store, PatFrag Value, InstHexagon MI>
3103 : Pat<(Store Value:$Rt, (i32 IntRegs:$Rs)),
3104 (MI IntRegs:$Rs, 0, Value:$Rt)>;
3106 // Regular stores in the DAG have two operands: value and address.
3107 // Atomic stores also have two, but they are reversed: address, value.
3108 // To use atomic stores with the patterns, they need to have their operands
3109 // swapped. This relies on the knowledge that the F.Fragment uses names
3111 class SwapSt<PatFrag F>
3112 : PatFrag<(ops node:$val, node:$ptr), F.Fragment>;
3114 def: Storex_simple_pat<SwapSt<atomic_store_8>, I32, S2_storerb_io>;
3115 def: Storex_simple_pat<SwapSt<atomic_store_16>, I32, S2_storerh_io>;
3116 def: Storex_simple_pat<SwapSt<atomic_store_32>, I32, S2_storeri_io>;
3117 def: Storex_simple_pat<SwapSt<atomic_store_64>, I64, S2_storerd_io>;
3119 def : Pat<(truncstorei8 (i32 IntRegs:$src1), ADDRriS11_0:$addr),
3120 (S2_storerb_io AddrFI:$addr, 0, (i32 IntRegs:$src1))>;
3122 def : Pat<(truncstorei16 (i32 IntRegs:$src1), ADDRriS11_1:$addr),
3123 (S2_storerh_io AddrFI:$addr, 0, (i32 IntRegs:$src1))>;
3125 def : Pat<(store (i32 IntRegs:$src1), ADDRriS11_2:$addr),
3126 (S2_storeri_io AddrFI:$addr, 0, (i32 IntRegs:$src1))>;
3128 def : Pat<(store (i64 DoubleRegs:$src1), ADDRriS11_3:$addr),
3129 (S2_storerd_io AddrFI:$addr, 0, (i64 DoubleRegs:$src1))>;
3132 let AddedComplexity = 10 in {
3133 def : Pat<(truncstorei8 (i32 IntRegs:$src1), (add IntRegs:$src2,
3134 s11_0ExtPred:$offset)),
3135 (S2_storerb_io IntRegs:$src2, s11_0ImmPred:$offset,
3136 (i32 IntRegs:$src1))>;
3138 def : Pat<(truncstorei16 (i32 IntRegs:$src1), (add IntRegs:$src2,
3139 s11_1ExtPred:$offset)),
3140 (S2_storerh_io IntRegs:$src2, s11_1ImmPred:$offset,
3141 (i32 IntRegs:$src1))>;
3143 def : Pat<(store (i32 IntRegs:$src1), (add IntRegs:$src2,
3144 s11_2ExtPred:$offset)),
3145 (S2_storeri_io IntRegs:$src2, s11_2ImmPred:$offset,
3146 (i32 IntRegs:$src1))>;
3148 def : Pat<(store (i64 DoubleRegs:$src1), (add IntRegs:$src2,
3149 s11_3ExtPred:$offset)),
3150 (S2_storerd_io IntRegs:$src2, s11_3ImmPred:$offset,
3151 (i64 DoubleRegs:$src1))>;
3154 // memh(Rx++#s4:1)=Rt.H
3157 let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 13,
3158 isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 0 in
3159 def STriw_pred : STInst<(outs),
3160 (ins IntRegs:$addr, s11_2Ext:$off, PredRegs:$src1),
3161 ".error \"should not emit\"", []>;
3163 // S2_allocframe: Allocate stack frame.
3164 let Defs = [R29, R30], Uses = [R29, R31, R30],
3165 hasSideEffects = 0, accessSize = DoubleWordAccess, isCodeGenOnly = 0 in
3166 def S2_allocframe: ST0Inst <
3167 (outs), (ins u11_3Imm:$u11_3),
3168 "allocframe(#$u11_3)" > {
3171 let IClass = 0b1010;
3172 let Inst{27-16} = 0b000010011101;
3173 let Inst{13-11} = 0b000;
3174 let Inst{10-0} = u11_3{13-3};
3177 // S2_storer[bhwdf]_pci: Store byte/half/word/double.
3178 // S2_storer[bhwdf]_pci -> S2_storerbnew_pci
3179 let Uses = [CS], isNVStorable = 1 in
3180 class T_store_pci <string mnemonic, RegisterClass RC,
3181 Operand Imm, bits<4>MajOp,
3182 MemAccessSize AlignSize, string RegSrc = "Rt">
3183 : STInst <(outs IntRegs:$_dst_),
3184 (ins IntRegs:$Rz, Imm:$offset, ModRegs:$Mu, RC:$Rt),
3185 #mnemonic#"($Rz ++ #$offset:circ($Mu)) = $"#RegSrc#"",
3192 let accessSize = AlignSize;
3194 let IClass = 0b1010;
3195 let Inst{27-25} = 0b100;
3196 let Inst{24-21} = MajOp;
3197 let Inst{20-16} = Rz;
3199 let Inst{12-8} = Rt;
3202 !if (!eq(!cast<string>(AlignSize), "DoubleWordAccess"), offset{6-3},
3203 !if (!eq(!cast<string>(AlignSize), "WordAccess"), offset{5-2},
3204 !if (!eq(!cast<string>(AlignSize), "HalfWordAccess"), offset{4-1},
3205 /* ByteAccess */ offset{3-0})));
3209 let isCodeGenOnly = 0 in {
3210 def S2_storerb_pci : T_store_pci<"memb", IntRegs, s4_0Imm, 0b1000,
3212 def S2_storerh_pci : T_store_pci<"memh", IntRegs, s4_1Imm, 0b1010,
3214 def S2_storerf_pci : T_store_pci<"memh", IntRegs, s4_1Imm, 0b1011,
3215 HalfWordAccess, "Rt.h">;
3216 def S2_storeri_pci : T_store_pci<"memw", IntRegs, s4_2Imm, 0b1100,
3218 def S2_storerd_pci : T_store_pci<"memd", DoubleRegs, s4_3Imm, 0b1110,
3222 let Uses = [CS], isNewValue = 1, mayStore = 1, isNVStore = 1, opNewValue = 4 in
3223 class T_storenew_pci <string mnemonic, Operand Imm,
3224 bits<2>MajOp, MemAccessSize AlignSize>
3225 : NVInst < (outs IntRegs:$_dst_),
3226 (ins IntRegs:$Rz, Imm:$offset, ModRegs:$Mu, IntRegs:$Nt),
3227 #mnemonic#"($Rz ++ #$offset:circ($Mu)) = $Nt.new",
3235 let accessSize = AlignSize;
3237 let IClass = 0b1010;
3238 let Inst{27-21} = 0b1001101;
3239 let Inst{20-16} = Rz;
3241 let Inst{12-11} = MajOp;
3242 let Inst{10-8} = Nt;
3245 !if (!eq(!cast<string>(AlignSize), "WordAccess"), offset{5-2},
3246 !if (!eq(!cast<string>(AlignSize), "HalfWordAccess"), offset{4-1},
3247 /* ByteAccess */ offset{3-0}));
3250 let isCodeGenOnly = 0 in {
3251 def S2_storerbnew_pci : T_storenew_pci <"memb", s4_0Imm, 0b00, ByteAccess>;
3252 def S2_storerhnew_pci : T_storenew_pci <"memh", s4_1Imm, 0b01, HalfWordAccess>;
3253 def S2_storerinew_pci : T_storenew_pci <"memw", s4_2Imm, 0b10, WordAccess>;
3256 //===----------------------------------------------------------------------===//
3257 // Circular stores with auto-increment register
3258 //===----------------------------------------------------------------------===//
3259 let Uses = [CS], isNVStorable = 1, isCodeGenOnly = 0 in
3260 class T_store_pcr <string mnemonic, RegisterClass RC, bits<4>MajOp,
3261 MemAccessSize AlignSize, string RegSrc = "Rt">
3262 : STInst <(outs IntRegs:$_dst_),
3263 (ins IntRegs:$Rz, ModRegs:$Mu, RC:$Rt),
3264 #mnemonic#"($Rz ++ I:circ($Mu)) = $"#RegSrc#"",
3271 let accessSize = AlignSize;
3273 let IClass = 0b1010;
3274 let Inst{27-25} = 0b100;
3275 let Inst{24-21} = MajOp;
3276 let Inst{20-16} = Rz;
3278 let Inst{12-8} = Rt;
3283 let isCodeGenOnly = 0 in {
3284 def S2_storerb_pcr : T_store_pcr<"memb", IntRegs, 0b1000, ByteAccess>;
3285 def S2_storerh_pcr : T_store_pcr<"memh", IntRegs, 0b1010, HalfWordAccess>;
3286 def S2_storeri_pcr : T_store_pcr<"memw", IntRegs, 0b1100, WordAccess>;
3287 def S2_storerd_pcr : T_store_pcr<"memd", DoubleRegs, 0b1110, DoubleWordAccess>;
3288 def S2_storerf_pcr : T_store_pcr<"memh", IntRegs, 0b1011,
3289 HalfWordAccess, "Rt.h">;
3292 //===----------------------------------------------------------------------===//
3293 // Circular .new stores with auto-increment register
3294 //===----------------------------------------------------------------------===//
3295 let Uses = [CS], isNewValue = 1, mayStore = 1, isNVStore = 1, opNewValue = 3 in
3296 class T_storenew_pcr <string mnemonic, bits<2>MajOp,
3297 MemAccessSize AlignSize>
3298 : NVInst <(outs IntRegs:$_dst_),
3299 (ins IntRegs:$Rz, ModRegs:$Mu, IntRegs:$Nt),
3300 #mnemonic#"($Rz ++ I:circ($Mu)) = $Nt.new" ,
3307 let accessSize = AlignSize;
3309 let IClass = 0b1010;
3310 let Inst{27-21} = 0b1001101;
3311 let Inst{20-16} = Rz;
3313 let Inst{12-11} = MajOp;
3314 let Inst{10-8} = Nt;
3319 let isCodeGenOnly = 0 in {
3320 def S2_storerbnew_pcr : T_storenew_pcr <"memb", 0b00, ByteAccess>;
3321 def S2_storerhnew_pcr : T_storenew_pcr <"memh", 0b01, HalfWordAccess>;
3322 def S2_storerinew_pcr : T_storenew_pcr <"memw", 0b10, WordAccess>;
3325 //===----------------------------------------------------------------------===//
3326 // Bit-reversed stores with auto-increment register
3327 //===----------------------------------------------------------------------===//
3328 let hasSideEffects = 0 in
3329 class T_store_pbr<string mnemonic, RegisterClass RC,
3330 MemAccessSize addrSize, bits<3> majOp,
3333 <(outs IntRegs:$_dst_),
3334 (ins IntRegs:$Rz, ModRegs:$Mu, RC:$src),
3335 #mnemonic#"($Rz ++ $Mu:brev) = $src"#!if (!eq(isHalf, 1), ".h", ""),
3336 [], "$Rz = $_dst_" > {
3338 let accessSize = addrSize;
3344 let IClass = 0b1010;
3346 let Inst{27-24} = 0b1111;
3347 let Inst{23-21} = majOp;
3349 let Inst{20-16} = Rz;
3351 let Inst{12-8} = src;
3354 let isNVStorable = 1, isCodeGenOnly = 0 in {
3355 let BaseOpcode = "S2_storerb_pbr" in
3356 def S2_storerb_pbr : T_store_pbr<"memb", IntRegs, ByteAccess,
3357 0b000>, NewValueRel;
3358 let BaseOpcode = "S2_storerh_pbr" in
3359 def S2_storerh_pbr : T_store_pbr<"memh", IntRegs, HalfWordAccess,
3360 0b010>, NewValueRel;
3361 let BaseOpcode = "S2_storeri_pbr" in
3362 def S2_storeri_pbr : T_store_pbr<"memw", IntRegs, WordAccess,
3363 0b100>, NewValueRel;
3365 let isCodeGenOnly = 0 in {
3366 def S2_storerf_pbr : T_store_pbr<"memh", IntRegs, HalfWordAccess, 0b011, 1>;
3367 def S2_storerd_pbr : T_store_pbr<"memd", DoubleRegs, DoubleWordAccess, 0b110>;
3370 //===----------------------------------------------------------------------===//
3371 // Bit-reversed .new stores with auto-increment register
3372 //===----------------------------------------------------------------------===//
3373 let isNewValue = 1, mayStore = 1, isNVStore = 1, opNewValue = 3,
3374 hasSideEffects = 0 in
3375 class T_storenew_pbr<string mnemonic, MemAccessSize addrSize, bits<2> majOp>
3376 : NVInst <(outs IntRegs:$_dst_),
3377 (ins IntRegs:$Rz, ModRegs:$Mu, IntRegs:$Nt),
3378 #mnemonic#"($Rz ++ $Mu:brev) = $Nt.new", [],
3379 "$Rz = $_dst_">, NewValueRel {
3380 let accessSize = addrSize;
3385 let IClass = 0b1010;
3387 let Inst{27-21} = 0b1111101;
3388 let Inst{12-11} = majOp;
3390 let Inst{20-16} = Rz;
3392 let Inst{10-8} = Nt;
3395 let BaseOpcode = "S2_storerb_pbr", isCodeGenOnly = 0 in
3396 def S2_storerbnew_pbr : T_storenew_pbr<"memb", ByteAccess, 0b00>;
3398 let BaseOpcode = "S2_storerh_pbr", isCodeGenOnly = 0 in
3399 def S2_storerhnew_pbr : T_storenew_pbr<"memh", HalfWordAccess, 0b01>;
3401 let BaseOpcode = "S2_storeri_pbr", isCodeGenOnly = 0 in
3402 def S2_storerinew_pbr : T_storenew_pbr<"memw", WordAccess, 0b10>;
3404 //===----------------------------------------------------------------------===//
3406 //===----------------------------------------------------------------------===//
3408 //===----------------------------------------------------------------------===//
3410 //===----------------------------------------------------------------------===//
3412 def NOT_rr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1),
3413 "$dst = not($src1)",
3414 [(set (i64 DoubleRegs:$dst), (not (i64 DoubleRegs:$src1)))]>;
3417 //===----------------------------------------------------------------------===//
3419 //===----------------------------------------------------------------------===//
3421 let hasSideEffects = 0 in
3422 class T_S2op_1 <string mnemonic, bits<4> RegTyBits, RegisterClass RCOut,
3423 RegisterClass RCIn, bits<2> MajOp, bits<3> MinOp, bit isSat>
3424 : SInst <(outs RCOut:$dst), (ins RCIn:$src),
3425 "$dst = "#mnemonic#"($src)"#!if(isSat, ":sat", ""),
3426 [], "", S_2op_tc_1_SLOT23 > {
3430 let IClass = 0b1000;
3432 let Inst{27-24} = RegTyBits;
3433 let Inst{23-22} = MajOp;
3435 let Inst{20-16} = src;
3436 let Inst{7-5} = MinOp;
3437 let Inst{4-0} = dst;
3440 class T_S2op_1_di <string mnemonic, bits<2> MajOp, bits<3> MinOp>
3441 : T_S2op_1 <mnemonic, 0b0100, DoubleRegs, IntRegs, MajOp, MinOp, 0>;
3443 let hasNewValue = 1 in
3444 class T_S2op_1_id <string mnemonic, bits<2> MajOp, bits<3> MinOp, bit isSat = 0>
3445 : T_S2op_1 <mnemonic, 0b1000, IntRegs, DoubleRegs, MajOp, MinOp, isSat>;
3447 let hasNewValue = 1 in
3448 class T_S2op_1_ii <string mnemonic, bits<2> MajOp, bits<3> MinOp, bit isSat = 0>
3449 : T_S2op_1 <mnemonic, 0b1100, IntRegs, IntRegs, MajOp, MinOp, isSat>;
3451 // Sign extend word to doubleword
3452 let isCodeGenOnly = 0 in
3453 def A2_sxtw : T_S2op_1_di <"sxtw", 0b01, 0b000>;
3455 def: Pat <(i64 (sext I32:$src)), (A2_sxtw I32:$src)>;
3457 // Swizzle the bytes of a word
3458 let isCodeGenOnly = 0 in
3459 def A2_swiz : T_S2op_1_ii <"swiz", 0b10, 0b111>;
3462 let Defs = [USR_OVF], isCodeGenOnly = 0 in {
3463 def A2_sat : T_S2op_1_id <"sat", 0b11, 0b000>;
3464 def A2_satb : T_S2op_1_ii <"satb", 0b11, 0b111>;
3465 def A2_satub : T_S2op_1_ii <"satub", 0b11, 0b110>;
3466 def A2_sath : T_S2op_1_ii <"sath", 0b11, 0b100>;
3467 def A2_satuh : T_S2op_1_ii <"satuh", 0b11, 0b101>;
3468 def A2_roundsat : T_S2op_1_id <"round", 0b11, 0b001, 0b1>;
3471 let Itinerary = S_2op_tc_2_SLOT23, isCodeGenOnly = 0 in {
3473 def S2_brev : T_S2op_1_ii <"brev", 0b01, 0b110>;
3475 // Absolute value word
3476 def A2_abs : T_S2op_1_ii <"abs", 0b10, 0b100>;
3478 let Defs = [USR_OVF] in
3479 def A2_abssat : T_S2op_1_ii <"abs", 0b10, 0b101, 1>;
3481 // Negate with saturation
3482 let Defs = [USR_OVF] in
3483 def A2_negsat : T_S2op_1_ii <"neg", 0b10, 0b110, 1>;
3486 def: Pat<(i32 (select (i1 (setlt (i32 IntRegs:$src), 0)),
3487 (i32 (sub 0, (i32 IntRegs:$src))),
3488 (i32 IntRegs:$src))),
3489 (A2_abs IntRegs:$src)>;
3491 let AddedComplexity = 50 in
3492 def: Pat<(i32 (xor (add (sra (i32 IntRegs:$src), (i32 31)),
3493 (i32 IntRegs:$src)),
3494 (sra (i32 IntRegs:$src), (i32 31)))),
3495 (A2_abs IntRegs:$src)>;
3497 class T_S2op_2 <string mnemonic, bits<4> RegTyBits, RegisterClass RCOut,
3498 RegisterClass RCIn, bits<3> MajOp, bits<3> MinOp,
3499 bit isSat, bit isRnd, list<dag> pattern = []>
3500 : SInst <(outs RCOut:$dst),
3501 (ins RCIn:$src, u5Imm:$u5),
3502 "$dst = "#mnemonic#"($src, #$u5)"#!if(isSat, ":sat", "")
3503 #!if(isRnd, ":rnd", ""),
3504 pattern, "", S_2op_tc_2_SLOT23> {
3509 let IClass = 0b1000;
3511 let Inst{27-24} = RegTyBits;
3512 let Inst{23-21} = MajOp;
3513 let Inst{20-16} = src;
3515 let Inst{12-8} = u5;
3516 let Inst{7-5} = MinOp;
3517 let Inst{4-0} = dst;
3520 class T_S2op_2_di <string mnemonic, bits<3> MajOp, bits<3> MinOp>
3521 : T_S2op_2 <mnemonic, 0b1000, DoubleRegs, IntRegs, MajOp, MinOp, 0, 0>;
3523 let hasNewValue = 1 in
3524 class T_S2op_2_id <string mnemonic, bits<3> MajOp, bits<3> MinOp>
3525 : T_S2op_2 <mnemonic, 0b1000, IntRegs, DoubleRegs, MajOp, MinOp, 0, 0>;
3527 let hasNewValue = 1 in
3528 class T_S2op_2_ii <string mnemonic, bits<3> MajOp, bits<3> MinOp,
3529 bit isSat = 0, bit isRnd = 0, list<dag> pattern = []>
3530 : T_S2op_2 <mnemonic, 0b1100, IntRegs, IntRegs, MajOp, MinOp,
3531 isSat, isRnd, pattern>;
3533 class T_S2op_shift <string mnemonic, bits<3> MajOp, bits<3> MinOp, SDNode OpNd>
3534 : T_S2op_2_ii <mnemonic, MajOp, MinOp, 0, 0,
3535 [(set (i32 IntRegs:$dst), (OpNd (i32 IntRegs:$src),
3536 (u5ImmPred:$u5)))]>;
3538 // Arithmetic/logical shift right/left by immediate
3539 let Itinerary = S_2op_tc_1_SLOT23, isCodeGenOnly = 0 in {
3540 def S2_asr_i_r : T_S2op_shift <"asr", 0b000, 0b000, sra>;
3541 def S2_lsr_i_r : T_S2op_shift <"lsr", 0b000, 0b001, srl>;
3542 def S2_asl_i_r : T_S2op_shift <"asl", 0b000, 0b010, shl>;
3545 // Shift left by immediate with saturation
3546 let Defs = [USR_OVF], isCodeGenOnly = 0 in
3547 def S2_asl_i_r_sat : T_S2op_2_ii <"asl", 0b010, 0b010, 1>;
3549 // Shift right with round
3550 let isCodeGenOnly = 0 in
3551 def S2_asr_i_r_rnd : T_S2op_2_ii <"asr", 0b010, 0b000, 0, 1>;
3553 def S2_asr_i_r_rnd_goodsyntax
3554 : SInst <(outs IntRegs:$dst), (ins IntRegs:$src, u5Imm:$u5),
3555 "$dst = asrrnd($src, #$u5)",
3556 [], "", S_2op_tc_1_SLOT23>;
3558 def: Pat<(i32 (sra (i32 (add (i32 (sra I32:$src1, u5ImmPred:$src2)),
3561 (S2_asr_i_r_rnd IntRegs:$src1, u5ImmPred:$src2)>;
3563 class T_S2op_3<string opc, bits<2>MajOp, bits<3>minOp, bits<1> sat = 0>
3564 : SInst<(outs DoubleRegs:$Rdd), (ins DoubleRegs:$Rss),
3565 "$Rdd = "#opc#"($Rss)"#!if(!eq(sat, 1),":sat","")> {
3568 let IClass = 0b1000;
3569 let Inst{27-24} = 0;
3570 let Inst{23-22} = MajOp;
3571 let Inst{20-16} = Rss;
3572 let Inst{7-5} = minOp;
3573 let Inst{4-0} = Rdd;
3576 let isCodeGenOnly = 0 in {
3577 def A2_absp : T_S2op_3 <"abs", 0b10, 0b110>;
3578 def A2_negp : T_S2op_3 <"neg", 0b10, 0b101>;
3579 def A2_notp : T_S2op_3 <"not", 0b10, 0b100>;
3582 // Innterleave/deinterleave
3583 let isCodeGenOnly = 0 in {
3584 def S2_interleave : T_S2op_3 <"interleave", 0b11, 0b101>;
3585 def S2_deinterleave : T_S2op_3 <"deinterleave", 0b11, 0b100>;
3588 //===----------------------------------------------------------------------===//
3590 //===----------------------------------------------------------------------===//
3593 let hasSideEffects = 0, hasNewValue = 1 in
3594 class T_COUNT_LEADING<string MnOp, bits<3> MajOp, bits<3> MinOp, bit Is32,
3596 : SInst<Out, Inp, "$Rd = "#MnOp#"($Rs)", [], "", S_2op_tc_1_SLOT23> {
3599 let IClass = 0b1000;
3601 let Inst{26} = Is32;
3602 let Inst{25-24} = 0b00;
3603 let Inst{23-21} = MajOp;
3604 let Inst{20-16} = Rs;
3605 let Inst{7-5} = MinOp;
3609 class T_COUNT_LEADING_32<string MnOp, bits<3> MajOp, bits<3> MinOp>
3610 : T_COUNT_LEADING<MnOp, MajOp, MinOp, 0b1,
3611 (outs IntRegs:$Rd), (ins IntRegs:$Rs)>;
3613 class T_COUNT_LEADING_64<string MnOp, bits<3> MajOp, bits<3> MinOp>
3614 : T_COUNT_LEADING<MnOp, MajOp, MinOp, 0b0,
3615 (outs IntRegs:$Rd), (ins DoubleRegs:$Rs)>;
3617 let isCodeGenOnly = 0 in {
3618 def S2_cl0 : T_COUNT_LEADING_32<"cl0", 0b000, 0b101>;
3619 def S2_cl1 : T_COUNT_LEADING_32<"cl1", 0b000, 0b110>;
3620 def S2_ct0 : T_COUNT_LEADING_32<"ct0", 0b010, 0b100>;
3621 def S2_ct1 : T_COUNT_LEADING_32<"ct1", 0b010, 0b101>;
3622 def S2_cl0p : T_COUNT_LEADING_64<"cl0", 0b010, 0b010>;
3623 def S2_cl1p : T_COUNT_LEADING_64<"cl1", 0b010, 0b100>;
3624 def S2_clb : T_COUNT_LEADING_32<"clb", 0b000, 0b100>;
3625 def S2_clbp : T_COUNT_LEADING_64<"clb", 0b010, 0b000>;
3626 def S2_clbnorm : T_COUNT_LEADING_32<"normamt", 0b000, 0b111>;
3629 def: Pat<(i32 (ctlz I32:$Rs)), (S2_cl0 I32:$Rs)>;
3630 def: Pat<(i32 (ctlz (not I32:$Rs))), (S2_cl1 I32:$Rs)>;
3631 def: Pat<(i32 (cttz I32:$Rs)), (S2_ct0 I32:$Rs)>;
3632 def: Pat<(i32 (cttz (not I32:$Rs))), (S2_ct1 I32:$Rs)>;
3633 def: Pat<(i32 (trunc (ctlz I64:$Rss))), (S2_cl0p I64:$Rss)>;
3634 def: Pat<(i32 (trunc (ctlz (not I64:$Rss)))), (S2_cl1p I64:$Rss)>;
3636 // Bit set/clear/toggle
3638 let hasSideEffects = 0, hasNewValue = 1 in
3639 class T_SCT_BIT_IMM<string MnOp, bits<3> MinOp>
3640 : SInst<(outs IntRegs:$Rd), (ins IntRegs:$Rs, u5Imm:$u5),
3641 "$Rd = "#MnOp#"($Rs, #$u5)", [], "", S_2op_tc_1_SLOT23> {
3645 let IClass = 0b1000;
3646 let Inst{27-21} = 0b1100110;
3647 let Inst{20-16} = Rs;
3649 let Inst{12-8} = u5;
3650 let Inst{7-5} = MinOp;
3654 let hasSideEffects = 0, hasNewValue = 1 in
3655 class T_SCT_BIT_REG<string MnOp, bits<2> MinOp>
3656 : SInst<(outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt),
3657 "$Rd = "#MnOp#"($Rs, $Rt)", [], "", S_3op_tc_1_SLOT23> {
3661 let IClass = 0b1100;
3662 let Inst{27-22} = 0b011010;
3663 let Inst{20-16} = Rs;
3664 let Inst{12-8} = Rt;
3665 let Inst{7-6} = MinOp;
3669 let isCodeGenOnly = 0 in {
3670 def S2_clrbit_i : T_SCT_BIT_IMM<"clrbit", 0b001>;
3671 def S2_setbit_i : T_SCT_BIT_IMM<"setbit", 0b000>;
3672 def S2_togglebit_i : T_SCT_BIT_IMM<"togglebit", 0b010>;
3673 def S2_clrbit_r : T_SCT_BIT_REG<"clrbit", 0b01>;
3674 def S2_setbit_r : T_SCT_BIT_REG<"setbit", 0b00>;
3675 def S2_togglebit_r : T_SCT_BIT_REG<"togglebit", 0b10>;
3678 def: Pat<(i32 (and (i32 IntRegs:$Rs), (not (shl 1, u5ImmPred:$u5)))),
3679 (S2_clrbit_i IntRegs:$Rs, u5ImmPred:$u5)>;
3680 def: Pat<(i32 (or (i32 IntRegs:$Rs), (shl 1, u5ImmPred:$u5))),
3681 (S2_setbit_i IntRegs:$Rs, u5ImmPred:$u5)>;
3682 def: Pat<(i32 (xor (i32 IntRegs:$Rs), (shl 1, u5ImmPred:$u5))),
3683 (S2_togglebit_i IntRegs:$Rs, u5ImmPred:$u5)>;
3684 def: Pat<(i32 (and (i32 IntRegs:$Rs), (not (shl 1, (i32 IntRegs:$Rt))))),
3685 (S2_clrbit_r IntRegs:$Rs, IntRegs:$Rt)>;
3686 def: Pat<(i32 (or (i32 IntRegs:$Rs), (shl 1, (i32 IntRegs:$Rt)))),
3687 (S2_setbit_r IntRegs:$Rs, IntRegs:$Rt)>;
3688 def: Pat<(i32 (xor (i32 IntRegs:$Rs), (shl 1, (i32 IntRegs:$Rt)))),
3689 (S2_togglebit_r IntRegs:$Rs, IntRegs:$Rt)>;
3693 let hasSideEffects = 0 in
3694 class T_TEST_BIT_IMM<string MnOp, bits<3> MajOp>
3695 : SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, u5Imm:$u5),
3696 "$Pd = "#MnOp#"($Rs, #$u5)",
3697 [], "", S_2op_tc_2early_SLOT23> {
3701 let IClass = 0b1000;
3702 let Inst{27-24} = 0b0101;
3703 let Inst{23-21} = MajOp;
3704 let Inst{20-16} = Rs;
3706 let Inst{12-8} = u5;
3710 let hasSideEffects = 0 in
3711 class T_TEST_BIT_REG<string MnOp, bit IsNeg>
3712 : SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, IntRegs:$Rt),
3713 "$Pd = "#MnOp#"($Rs, $Rt)",
3714 [], "", S_3op_tc_2early_SLOT23> {
3718 let IClass = 0b1100;
3719 let Inst{27-22} = 0b011100;
3720 let Inst{21} = IsNeg;
3721 let Inst{20-16} = Rs;
3722 let Inst{12-8} = Rt;
3726 let isCodeGenOnly = 0 in {
3727 def S2_tstbit_i : T_TEST_BIT_IMM<"tstbit", 0b000>;
3728 def S2_tstbit_r : T_TEST_BIT_REG<"tstbit", 0>;
3731 let AddedComplexity = 20 in { // Complexity greater than cmp reg-imm.
3732 def: Pat<(i1 (setne (and (shl 1, u5ImmPred:$u5), (i32 IntRegs:$Rs)), 0)),
3733 (S2_tstbit_i IntRegs:$Rs, u5ImmPred:$u5)>;
3734 def: Pat<(i1 (setne (and (shl 1, (i32 IntRegs:$Rt)), (i32 IntRegs:$Rs)), 0)),
3735 (S2_tstbit_r IntRegs:$Rs, IntRegs:$Rt)>;
3736 def: Pat<(i1 (trunc (i32 IntRegs:$Rs))),
3737 (S2_tstbit_i IntRegs:$Rs, 0)>;
3738 def: Pat<(i1 (trunc (i64 DoubleRegs:$Rs))),
3739 (S2_tstbit_i (LoReg DoubleRegs:$Rs), 0)>;
3741 let hasSideEffects = 0 in
3742 class T_TEST_BITS_IMM<string MnOp, bits<2> MajOp, bit IsNeg>
3743 : SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, u6Imm:$u6),
3744 "$Pd = "#MnOp#"($Rs, #$u6)",
3745 [], "", S_2op_tc_2early_SLOT23> {
3749 let IClass = 0b1000;
3750 let Inst{27-24} = 0b0101;
3751 let Inst{23-22} = MajOp;
3752 let Inst{21} = IsNeg;
3753 let Inst{20-16} = Rs;
3754 let Inst{13-8} = u6;
3758 let hasSideEffects = 0 in
3759 class T_TEST_BITS_REG<string MnOp, bits<2> MajOp, bit IsNeg>
3760 : SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, IntRegs:$Rt),
3761 "$Pd = "#MnOp#"($Rs, $Rt)",
3762 [], "", S_3op_tc_2early_SLOT23> {
3766 let IClass = 0b1100;
3767 let Inst{27-24} = 0b0111;
3768 let Inst{23-22} = MajOp;
3769 let Inst{21} = IsNeg;
3770 let Inst{20-16} = Rs;
3771 let Inst{12-8} = Rt;
3775 let isCodeGenOnly = 0 in {
3776 def C2_bitsclri : T_TEST_BITS_IMM<"bitsclr", 0b10, 0>;
3777 def C2_bitsclr : T_TEST_BITS_REG<"bitsclr", 0b10, 0>;
3778 def C2_bitsset : T_TEST_BITS_REG<"bitsset", 0b01, 0>;
3781 let AddedComplexity = 20 in { // Complexity greater than compare reg-imm.
3782 def: Pat<(i1 (seteq (and (i32 IntRegs:$Rs), u6ImmPred:$u6), 0)),
3783 (C2_bitsclri IntRegs:$Rs, u6ImmPred:$u6)>;
3784 def: Pat<(i1 (seteq (and (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)), 0)),
3785 (C2_bitsclr IntRegs:$Rs, IntRegs:$Rt)>;
3788 let AddedComplexity = 10 in // Complexity greater than compare reg-reg.
3789 def: Pat<(i1 (seteq (and (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)), IntRegs:$Rt)),
3790 (C2_bitsset IntRegs:$Rs, IntRegs:$Rt)>;
3792 //===----------------------------------------------------------------------===//
3794 //===----------------------------------------------------------------------===//
3796 //===----------------------------------------------------------------------===//
3798 //===----------------------------------------------------------------------===//
3799 //===----------------------------------------------------------------------===//
3801 //===----------------------------------------------------------------------===//
3803 //===----------------------------------------------------------------------===//
3805 //===----------------------------------------------------------------------===//
3807 //===----------------------------------------------------------------------===//
3809 //===----------------------------------------------------------------------===//
3811 //===----------------------------------------------------------------------===//
3813 //===----------------------------------------------------------------------===//
3815 // Predicate transfer.
3816 let hasSideEffects = 0, hasNewValue = 1, isCodeGenOnly = 0 in
3817 def C2_tfrpr : SInst<(outs IntRegs:$Rd), (ins PredRegs:$Ps),
3818 "$Rd = $Ps", [], "", S_2op_tc_1_SLOT23> {
3822 let IClass = 0b1000;
3823 let Inst{27-24} = 0b1001;
3825 let Inst{17-16} = Ps;
3829 // Transfer general register to predicate.
3830 let hasSideEffects = 0, isCodeGenOnly = 0 in
3831 def C2_tfrrp: SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs),
3832 "$Pd = $Rs", [], "", S_2op_tc_2early_SLOT23> {
3836 let IClass = 0b1000;
3837 let Inst{27-21} = 0b0101010;
3838 let Inst{20-16} = Rs;
3843 //===----------------------------------------------------------------------===//
3845 //===----------------------------------------------------------------------===//
3847 //===----------------------------------------------------------------------===//
3849 //===----------------------------------------------------------------------===//
3850 class S_2OpInstImm<string Mnemonic, bits<3>MajOp, bits<3>MinOp,
3851 Operand Imm, list<dag> pattern = [], bit isRnd = 0>
3852 : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, Imm:$src2),
3853 "$dst = "#Mnemonic#"($src1, #$src2)"#!if(isRnd, ":rnd", ""),
3857 let IClass = 0b1000;
3858 let Inst{27-24} = 0;
3859 let Inst{23-21} = MajOp;
3860 let Inst{20-16} = src1;
3861 let Inst{7-5} = MinOp;
3862 let Inst{4-0} = dst;
3865 class S_2OpInstImmI6<string Mnemonic, SDNode OpNode, bits<3>MinOp>
3866 : S_2OpInstImm<Mnemonic, 0b000, MinOp, u6Imm,
3867 [(set (i64 DoubleRegs:$dst), (OpNode (i64 DoubleRegs:$src1),
3868 u6ImmPred:$src2))]> {
3870 let Inst{13-8} = src2;
3873 // Shift by immediate.
3874 let isCodeGenOnly = 0 in {
3875 def S2_asr_i_p : S_2OpInstImmI6<"asr", sra, 0b000>;
3876 def S2_asl_i_p : S_2OpInstImmI6<"asl", shl, 0b010>;
3877 def S2_lsr_i_p : S_2OpInstImmI6<"lsr", srl, 0b001>;
3880 // Shift left by small amount and add.
3881 let AddedComplexity = 100, hasNewValue = 1, hasSideEffects = 0,
3882 isCodeGenOnly = 0 in
3883 def S2_addasl_rrri: SInst <(outs IntRegs:$Rd),
3884 (ins IntRegs:$Rt, IntRegs:$Rs, u3Imm:$u3),
3885 "$Rd = addasl($Rt, $Rs, #$u3)" ,
3886 [(set (i32 IntRegs:$Rd), (add (i32 IntRegs:$Rt),
3887 (shl (i32 IntRegs:$Rs), u3ImmPred:$u3)))],
3888 "", S_3op_tc_2_SLOT23> {
3894 let IClass = 0b1100;
3896 let Inst{27-21} = 0b0100000;
3897 let Inst{20-16} = Rs;
3899 let Inst{12-8} = Rt;
3904 //===----------------------------------------------------------------------===//
3906 //===----------------------------------------------------------------------===//
3908 //===----------------------------------------------------------------------===//
3910 //===----------------------------------------------------------------------===//
3911 //===----------------------------------------------------------------------===//
3913 //===----------------------------------------------------------------------===//
3915 //===----------------------------------------------------------------------===//
3917 //===----------------------------------------------------------------------===//
3918 //===----------------------------------------------------------------------===//
3920 //===----------------------------------------------------------------------===//
3922 //===----------------------------------------------------------------------===//
3924 //===----------------------------------------------------------------------===//
3926 //===----------------------------------------------------------------------===//
3928 //===----------------------------------------------------------------------===//
3929 def HexagonBARRIER: SDNode<"HexagonISD::BARRIER", SDTNone, [SDNPHasChain]>;
3931 let hasSideEffects = 1, isSoloAX = 1, isCodeGenOnly = 0 in
3932 def BARRIER : SYSInst<(outs), (ins),
3934 [(HexagonBARRIER)],"",ST_tc_st_SLOT0> {
3935 let Inst{31-28} = 0b1010;
3936 let Inst{27-21} = 0b1000000;
3939 //===----------------------------------------------------------------------===//
3941 //===----------------------------------------------------------------------===//
3942 //===----------------------------------------------------------------------===//
3944 //===----------------------------------------------------------------------===//
3946 let isExtendable = 1, isExtentSigned = 1, opExtentBits = 9, opExtentAlign = 2,
3947 opExtendable = 0, hasSideEffects = 0 in
3948 class LOOP_iBase<string mnemonic, Operand brOp, bit mustExtend = 0>
3949 : CRInst<(outs), (ins brOp:$offset, u10Imm:$src2),
3950 #mnemonic#"($offset, #$src2)",
3951 [], "" , CR_tc_3x_SLOT3> {
3955 let IClass = 0b0110;
3957 let Inst{27-22} = 0b100100;
3958 let Inst{21} = !if (!eq(mnemonic, "loop0"), 0b0, 0b1);
3959 let Inst{20-16} = src2{9-5};
3960 let Inst{12-8} = offset{8-4};
3961 let Inst{7-5} = src2{4-2};
3962 let Inst{4-3} = offset{3-2};
3963 let Inst{1-0} = src2{1-0};
3966 let isExtendable = 1, isExtentSigned = 1, opExtentBits = 9, opExtentAlign = 2,
3967 opExtendable = 0, hasSideEffects = 0 in
3968 class LOOP_rBase<string mnemonic, Operand brOp, bit mustExtend = 0>
3969 : CRInst<(outs), (ins brOp:$offset, IntRegs:$src2),
3970 #mnemonic#"($offset, $src2)",
3971 [], "" ,CR_tc_3x_SLOT3> {
3975 let IClass = 0b0110;
3977 let Inst{27-22} = 0b000000;
3978 let Inst{21} = !if (!eq(mnemonic, "loop0"), 0b0, 0b1);
3979 let Inst{20-16} = src2;
3980 let Inst{12-8} = offset{8-4};
3981 let Inst{4-3} = offset{3-2};
3984 multiclass LOOP_ri<string mnemonic> {
3985 def i : LOOP_iBase<mnemonic, brtarget>;
3986 def r : LOOP_rBase<mnemonic, brtarget>;
3990 let Defs = [SA0, LC0, USR], isCodeGenOnly = 0 in
3991 defm J2_loop0 : LOOP_ri<"loop0">;
3993 // Interestingly only loop0's appear to set usr.lpcfg
3994 let Defs = [SA1, LC1], isCodeGenOnly = 0 in
3995 defm J2_loop1 : LOOP_ri<"loop1">;
3997 let isBranch = 1, isTerminator = 1, hasSideEffects = 0,
3998 Defs = [PC, LC0], Uses = [SA0, LC0] in {
3999 def ENDLOOP0 : Endloop<(outs), (ins brtarget:$offset),
4004 let isBranch = 1, isTerminator = 1, hasSideEffects = 0,
4005 Defs = [PC, LC1], Uses = [SA1, LC1] in {
4006 def ENDLOOP1 : Endloop<(outs), (ins brtarget:$offset),
4011 // Pipelined loop instructions, sp[123]loop0
4012 let Defs = [LC0, SA0, P3, USR], hasSideEffects = 0,
4013 isExtentSigned = 1, isExtendable = 1, opExtentBits = 9, opExtentAlign = 2,
4014 opExtendable = 0, isPredicateLate = 1 in
4015 class SPLOOP_iBase<string SP, bits<2> op>
4016 : CRInst <(outs), (ins brtarget:$r7_2, u10Imm:$U10),
4017 "p3 = sp"#SP#"loop0($r7_2, #$U10)" > {
4021 let IClass = 0b0110;
4023 let Inst{22-21} = op;
4024 let Inst{27-23} = 0b10011;
4025 let Inst{20-16} = U10{9-5};
4026 let Inst{12-8} = r7_2{8-4};
4027 let Inst{7-5} = U10{4-2};
4028 let Inst{4-3} = r7_2{3-2};
4029 let Inst{1-0} = U10{1-0};
4032 let Defs = [LC0, SA0, P3, USR], hasSideEffects = 0,
4033 isExtentSigned = 1, isExtendable = 1, opExtentBits = 9, opExtentAlign = 2,
4034 opExtendable = 0, isPredicateLate = 1 in
4035 class SPLOOP_rBase<string SP, bits<2> op>
4036 : CRInst <(outs), (ins brtarget:$r7_2, IntRegs:$Rs),
4037 "p3 = sp"#SP#"loop0($r7_2, $Rs)" > {
4041 let IClass = 0b0110;
4043 let Inst{22-21} = op;
4044 let Inst{27-23} = 0b00001;
4045 let Inst{20-16} = Rs;
4046 let Inst{12-8} = r7_2{8-4};
4047 let Inst{4-3} = r7_2{3-2};
4050 multiclass SPLOOP_ri<string mnemonic, bits<2> op> {
4051 def i : SPLOOP_iBase<mnemonic, op>;
4052 def r : SPLOOP_rBase<mnemonic, op>;
4055 let isCodeGenOnly = 0 in {
4056 defm J2_ploop1s : SPLOOP_ri<"1", 0b01>;
4057 defm J2_ploop2s : SPLOOP_ri<"2", 0b10>;
4058 defm J2_ploop3s : SPLOOP_ri<"3", 0b11>;
4061 // Transfer to/from Control/GPR Guest/GPR
4062 let hasSideEffects = 0 in
4063 class TFR_CR_RS_base<RegisterClass CTRC, RegisterClass RC, bit isDouble>
4064 : CRInst <(outs CTRC:$dst), (ins RC:$src),
4065 "$dst = $src", [], "", CR_tc_3x_SLOT3> {
4069 let IClass = 0b0110;
4071 let Inst{27-25} = 0b001;
4072 let Inst{24} = isDouble;
4073 let Inst{23-21} = 0b001;
4074 let Inst{20-16} = src;
4075 let Inst{4-0} = dst;
4077 let isCodeGenOnly = 0 in
4078 def A2_tfrrcr : TFR_CR_RS_base<CtrRegs, IntRegs, 0b0>;
4079 def : InstAlias<"m0 = $Rs", (A2_tfrrcr C6, IntRegs:$Rs)>;
4080 def : InstAlias<"m1 = $Rs", (A2_tfrrcr C7, IntRegs:$Rs)>;
4082 let hasSideEffects = 0 in
4083 class TFR_RD_CR_base<RegisterClass RC, RegisterClass CTRC, bit isSingle>
4084 : CRInst <(outs RC:$dst), (ins CTRC:$src),
4085 "$dst = $src", [], "", CR_tc_3x_SLOT3> {
4089 let IClass = 0b0110;
4091 let Inst{27-26} = 0b10;
4092 let Inst{25} = isSingle;
4093 let Inst{24-21} = 0b0000;
4094 let Inst{20-16} = src;
4095 let Inst{4-0} = dst;
4098 let hasNewValue = 1, opNewValue = 0, isCodeGenOnly = 0 in
4099 def A2_tfrcrr : TFR_RD_CR_base<IntRegs, CtrRegs, 1>;
4100 def : InstAlias<"$Rd = m0", (A2_tfrcrr IntRegs:$Rd, C6)>;
4101 def : InstAlias<"$Rd = m1", (A2_tfrcrr IntRegs:$Rd, C7)>;
4103 // Y4_trace: Send value to etm trace.
4104 let isSoloAX = 1, hasSideEffects = 0, isCodeGenOnly = 0 in
4105 def Y4_trace: CRInst <(outs), (ins IntRegs:$Rs),
4109 let IClass = 0b0110;
4110 let Inst{27-21} = 0b0010010;
4111 let Inst{20-16} = Rs;
4114 let AddedComplexity = 100, isPredicated = 1 in
4115 def TFR_condset_ri : ALU32_rr<(outs IntRegs:$dst),
4116 (ins PredRegs:$src1, IntRegs:$src2, s12Imm:$src3),
4117 "Error; should not emit",
4118 [(set (i32 IntRegs:$dst),
4119 (i32 (select (i1 PredRegs:$src1), (i32 IntRegs:$src2),
4120 s12ImmPred:$src3)))]>;
4122 let AddedComplexity = 100, isPredicated = 1 in
4123 def TFR_condset_ir : ALU32_rr<(outs IntRegs:$dst),
4124 (ins PredRegs:$src1, s12Imm:$src2, IntRegs:$src3),
4125 "Error; should not emit",
4126 [(set (i32 IntRegs:$dst),
4127 (i32 (select (i1 PredRegs:$src1), s12ImmPred:$src2,
4128 (i32 IntRegs:$src3))))]>;
4130 let AddedComplexity = 100, isPredicated = 1 in
4131 def TFR_condset_ii : ALU32_rr<(outs IntRegs:$dst),
4132 (ins PredRegs:$src1, s12Imm:$src2, s12Imm:$src3),
4133 "Error; should not emit",
4134 [(set (i32 IntRegs:$dst),
4135 (i32 (select (i1 PredRegs:$src1), s12ImmPred:$src2,
4136 s12ImmPred:$src3)))]>;
4138 // Generate frameindex addresses.
4139 let isReMaterializable = 1 in
4140 def TFR_FI : ALU32_ri<(outs IntRegs:$dst), (ins FrameIndex:$src1),
4141 "$dst = add($src1)",
4142 [(set (i32 IntRegs:$dst), ADDRri:$src1)]>;
4144 // Support for generating global address.
4145 // Taken from X86InstrInfo.td.
4146 def SDTHexagonCONST32 : SDTypeProfile<1, 1, [SDTCisVT<0, i32>,
4149 def HexagonCONST32 : SDNode<"HexagonISD::CONST32", SDTHexagonCONST32>;
4150 def HexagonCONST32_GP : SDNode<"HexagonISD::CONST32_GP", SDTHexagonCONST32>;
4152 // HI/LO Instructions
4153 let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0 in
4154 def LO : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$global),
4155 "$dst.l = #LO($global)",
4158 let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0 in
4159 def HI : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$global),
4160 "$dst.h = #HI($global)",
4163 let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0 in
4164 def LOi : ALU32_ri<(outs IntRegs:$dst), (ins i32imm:$imm_value),
4165 "$dst.l = #LO($imm_value)",
4169 let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0 in
4170 def HIi : ALU32_ri<(outs IntRegs:$dst), (ins i32imm:$imm_value),
4171 "$dst.h = #HI($imm_value)",
4174 let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0 in
4175 def LO_jt : ALU32_ri<(outs IntRegs:$dst), (ins jumptablebase:$jt),
4176 "$dst.l = #LO($jt)",
4179 let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0 in
4180 def HI_jt : ALU32_ri<(outs IntRegs:$dst), (ins jumptablebase:$jt),
4181 "$dst.h = #HI($jt)",
4185 let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0 in
4186 def LO_label : ALU32_ri<(outs IntRegs:$dst), (ins bblabel:$label),
4187 "$dst.l = #LO($label)",
4190 let isReMaterializable = 1, isMoveImm = 1 , hasSideEffects = 0 in
4191 def HI_label : ALU32_ri<(outs IntRegs:$dst), (ins bblabel:$label),
4192 "$dst.h = #HI($label)",
4195 // This pattern is incorrect. When we add small data, we should change
4196 // this pattern to use memw(#foo).
4197 // This is for sdata.
4198 let isMoveImm = 1 in
4199 def CONST32 : LDInst<(outs IntRegs:$dst), (ins globaladdress:$global),
4200 "$dst = CONST32(#$global)",
4201 [(set (i32 IntRegs:$dst),
4202 (load (HexagonCONST32 tglobaltlsaddr:$global)))]>;
4204 // This is for non-sdata.
4205 let isReMaterializable = 1, isMoveImm = 1 in
4206 def CONST32_set : LDInst2<(outs IntRegs:$dst), (ins globaladdress:$global),
4207 "$dst = CONST32(#$global)",
4208 [(set (i32 IntRegs:$dst),
4209 (HexagonCONST32 tglobaladdr:$global))]>;
4211 let isReMaterializable = 1, isMoveImm = 1 in
4212 def CONST32_set_jt : LDInst2<(outs IntRegs:$dst), (ins jumptablebase:$jt),
4213 "$dst = CONST32(#$jt)",
4214 [(set (i32 IntRegs:$dst),
4215 (HexagonCONST32 tjumptable:$jt))]>;
4217 let isReMaterializable = 1, isMoveImm = 1 in
4218 def CONST32GP_set : LDInst2<(outs IntRegs:$dst), (ins globaladdress:$global),
4219 "$dst = CONST32(#$global)",
4220 [(set (i32 IntRegs:$dst),
4221 (HexagonCONST32_GP tglobaladdr:$global))]>;
4223 let isReMaterializable = 1, isMoveImm = 1 in
4224 def CONST32_Int_Real : LDInst2<(outs IntRegs:$dst), (ins i32imm:$global),
4225 "$dst = CONST32(#$global)",
4226 [(set (i32 IntRegs:$dst), imm:$global) ]>;
4228 // Map BlockAddress lowering to CONST32_Int_Real
4229 def : Pat<(HexagonCONST32_GP tblockaddress:$addr),
4230 (CONST32_Int_Real tblockaddress:$addr)>;
4232 let isReMaterializable = 1, isMoveImm = 1 in
4233 def CONST32_Label : LDInst2<(outs IntRegs:$dst), (ins bblabel:$label),
4234 "$dst = CONST32($label)",
4235 [(set (i32 IntRegs:$dst), (HexagonCONST32 bbl:$label))]>;
4237 let isReMaterializable = 1, isMoveImm = 1 in
4238 def CONST64_Int_Real : LDInst2<(outs DoubleRegs:$dst), (ins i64imm:$global),
4239 "$dst = CONST64(#$global)",
4240 [(set (i64 DoubleRegs:$dst), imm:$global) ]>;
4242 def TFR_PdFalse : SInst<(outs PredRegs:$dst), (ins),
4243 "$dst = xor($dst, $dst)",
4244 [(set (i1 PredRegs:$dst), 0)]>;
4246 // Pseudo instructions.
4247 def SDT_SPCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
4248 def SDT_SPCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
4249 SDTCisVT<1, i32> ]>;
4251 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeqStart,
4252 [SDNPHasChain, SDNPOutGlue]>;
4253 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeqEnd,
4254 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
4256 def SDT_SPCall : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
4258 // For tailcalls a HexagonTCRet SDNode has 3 SDNode Properties - a chain,
4259 // Optional Flag and Variable Arguments.
4260 // Its 1 Operand has pointer type.
4261 def HexagonTCRet : SDNode<"HexagonISD::TC_RETURN", SDT_SPCall,
4262 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
4264 let Defs = [R29, R30], Uses = [R31, R30, R29] in {
4265 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
4266 "Should never be emitted",
4267 [(callseq_start timm:$amt)]>;
4270 let Defs = [R29, R30, R31], Uses = [R29] in {
4271 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
4272 "Should never be emitted",
4273 [(callseq_end timm:$amt1, timm:$amt2)]>;
4276 let isCall = 1, hasSideEffects = 0,
4277 Defs = [D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10,
4278 R22, R23, R28, R31, P0, P1, P2, P3, LC0, LC1, SA0, SA1] in {
4279 def CALL : JInst<(outs), (ins calltarget:$dst),
4283 // Call subroutine indirectly.
4284 let Defs = VolatileV3.Regs, isCodeGenOnly = 0 in
4285 def J2_callr : JUMPR_MISC_CALLR<0, 1>;
4287 // Indirect tail-call.
4288 let isCodeGenOnly = 1, isCall = 1, isReturn = 1 in
4289 def TCRETURNR : T_JMPr;
4291 // Direct tail-calls.
4292 let isCall = 1, isReturn = 1, isBarrier = 1, isPredicable = 0,
4293 isTerminator = 1, isCodeGenOnly = 1 in {
4294 def TCRETURNtg : JInst<(outs), (ins calltarget:$dst), "jump $dst",
4295 [], "", J_tc_2early_SLOT23>;
4296 def TCRETURNtext : JInst<(outs), (ins calltarget:$dst), "jump $dst",
4297 [], "", J_tc_2early_SLOT23>;
4301 def : Pat<(HexagonTCRet tglobaladdr:$dst),
4302 (TCRETURNtg tglobaladdr:$dst)>;
4303 def : Pat<(HexagonTCRet texternalsym:$dst),
4304 (TCRETURNtext texternalsym:$dst)>;
4305 def : Pat<(HexagonTCRet (i32 IntRegs:$dst)),
4306 (TCRETURNR (i32 IntRegs:$dst))>;
4308 // Map from r0 = and(r1, 65535) to r0 = zxth(r1)
4309 def : Pat <(and (i32 IntRegs:$src1), 65535),
4310 (A2_zxth (i32 IntRegs:$src1))>;
4312 // Map from r0 = and(r1, 255) to r0 = zxtb(r1).
4313 def : Pat <(and (i32 IntRegs:$src1), 255),
4314 (A2_zxtb (i32 IntRegs:$src1))>;
4316 // Map Add(p1, true) to p1 = not(p1).
4317 // Add(p1, false) should never be produced,
4318 // if it does, it got to be mapped to NOOP.
4319 def : Pat <(add (i1 PredRegs:$src1), -1),
4320 (C2_not (i1 PredRegs:$src1))>;
4322 // Map from p0 = pnot(p0); r0 = mux(p0, #i, #j) => r0 = mux(p0, #j, #i).
4323 def : Pat <(select (not (i1 PredRegs:$src1)), s8ImmPred:$src2, s8ImmPred:$src3),
4324 (i32 (TFR_condset_ii (i1 PredRegs:$src1), s8ImmPred:$src3,
4327 // Map from p0 = pnot(p0); r0 = select(p0, #i, r1)
4328 // => r0 = TFR_condset_ri(p0, r1, #i)
4329 def : Pat <(select (not (i1 PredRegs:$src1)), s12ImmPred:$src2,
4330 (i32 IntRegs:$src3)),
4331 (i32 (TFR_condset_ri (i1 PredRegs:$src1), (i32 IntRegs:$src3),
4332 s12ImmPred:$src2))>;
4334 // Map from p0 = pnot(p0); r0 = mux(p0, r1, #i)
4335 // => r0 = TFR_condset_ir(p0, #i, r1)
4336 def : Pat <(select (not (i1 PredRegs:$src1)), IntRegs:$src2, s12ImmPred:$src3),
4337 (i32 (TFR_condset_ir (i1 PredRegs:$src1), s12ImmPred:$src3,
4338 (i32 IntRegs:$src2)))>;
4340 // Map from p0 = pnot(p0); if (p0) jump => if (!p0) jump.
4341 def : Pat <(brcond (not (i1 PredRegs:$src1)), bb:$offset),
4342 (J2_jumpf (i1 PredRegs:$src1), bb:$offset)>;
4344 // Map from p2 = pnot(p2); p1 = and(p0, p2) => p1 = and(p0, !p2).
4345 def : Pat <(and (i1 PredRegs:$src1), (not (i1 PredRegs:$src2))),
4346 (i1 (C2_andn (i1 PredRegs:$src1), (i1 PredRegs:$src2)))>;
4349 let AddedComplexity = 100 in
4350 def : Pat <(i64 (zextloadi1 (HexagonCONST32 tglobaladdr:$global))),
4351 (i64 (A2_combinew (A2_tfrsi 0),
4352 (L2_loadrub_io (CONST32_set tglobaladdr:$global), 0)))>,
4355 // Map from i1 loads to 32 bits. This assumes that the i1* is byte aligned.
4356 let AddedComplexity = 10 in
4357 def : Pat <(i32 (zextloadi1 ADDRriS11_0:$addr)),
4358 (i32 (A2_and (i32 (L2_loadrb_io AddrFI:$addr, 0)), (A2_tfrsi 0x1)))>;
4360 // Map from Rdd = sign_extend_inreg(Rss, i32) -> Rdd = A2_sxtw(Rss.lo).
4361 def : Pat <(i64 (sext_inreg (i64 DoubleRegs:$src1), i32)),
4362 (i64 (A2_sxtw (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_loreg))))>;
4364 // Map from Rdd = sign_extend_inreg(Rss, i16) -> Rdd = A2_sxtw(SXTH(Rss.lo)).
4365 def : Pat <(i64 (sext_inreg (i64 DoubleRegs:$src1), i16)),
4366 (i64 (A2_sxtw (i32 (A2_sxth (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
4367 subreg_loreg))))))>;
4369 // Map from Rdd = sign_extend_inreg(Rss, i8) -> Rdd = A2_sxtw(SXTB(Rss.lo)).
4370 def : Pat <(i64 (sext_inreg (i64 DoubleRegs:$src1), i8)),
4371 (i64 (A2_sxtw (i32 (A2_sxtb (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
4372 subreg_loreg))))))>;
4374 // We want to prevent emitting pnot's as much as possible.
4375 // Map brcond with an unsupported setcc to a J2_jumpf.
4376 def : Pat <(brcond (i1 (setne (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
4378 (J2_jumpf (C2_cmpeq (i32 IntRegs:$src1), (i32 IntRegs:$src2)),
4381 def : Pat <(brcond (i1 (setne (i32 IntRegs:$src1), s10ImmPred:$src2)),
4383 (J2_jumpf (C2_cmpeqi (i32 IntRegs:$src1), s10ImmPred:$src2), bb:$offset)>;
4385 def : Pat <(brcond (i1 (setne (i1 PredRegs:$src1), (i1 -1))), bb:$offset),
4386 (J2_jumpf (i1 PredRegs:$src1), bb:$offset)>;
4388 def : Pat <(brcond (i1 (setne (i1 PredRegs:$src1), (i1 0))), bb:$offset),
4389 (J2_jumpt (i1 PredRegs:$src1), bb:$offset)>;
4391 // cmp.lt(Rs, Imm) -> !cmp.ge(Rs, Imm) -> !cmp.gt(Rs, Imm-1)
4392 def : Pat <(brcond (i1 (setlt (i32 IntRegs:$src1), s8ImmPred:$src2)),
4394 (J2_jumpf (C2_cmpgti (i32 IntRegs:$src1),
4395 (DEC_CONST_SIGNED s8ImmPred:$src2)), bb:$offset)>;
4397 // cmp.lt(r0, r1) -> cmp.gt(r1, r0)
4398 def : Pat <(brcond (i1 (setlt (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
4400 (J2_jumpt (C2_cmpgt (i32 IntRegs:$src2), (i32 IntRegs:$src1)), bb:$offset)>;
4402 def : Pat <(brcond (i1 (setuge (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
4404 (J2_jumpf (C2_cmpgtup (i64 DoubleRegs:$src2), (i64 DoubleRegs:$src1)),
4407 def : Pat <(brcond (i1 (setule (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
4409 (J2_jumpf (C2_cmpgtu (i32 IntRegs:$src1), (i32 IntRegs:$src2)),
4412 def : Pat <(brcond (i1 (setule (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
4414 (J2_jumpf (C2_cmpgtup (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2)),
4417 // Map from a 64-bit select to an emulated 64-bit mux.
4418 // Hexagon does not support 64-bit MUXes; so emulate with combines.
4419 def : Pat <(select (i1 PredRegs:$src1), (i64 DoubleRegs:$src2),
4420 (i64 DoubleRegs:$src3)),
4421 (i64 (A2_combinew (i32 (C2_mux (i1 PredRegs:$src1),
4422 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
4424 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src3),
4426 (i32 (C2_mux (i1 PredRegs:$src1),
4427 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
4429 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src3),
4430 subreg_loreg))))))>;
4432 // Map from a 1-bit select to logical ops.
4433 // From LegalizeDAG.cpp: (B1 ? B2 : B3) <=> (B1 & B2)|(!B1&B3).
4434 def : Pat <(select (i1 PredRegs:$src1), (i1 PredRegs:$src2),
4435 (i1 PredRegs:$src3)),
4436 (C2_or (C2_and (i1 PredRegs:$src1), (i1 PredRegs:$src2)),
4437 (C2_and (C2_not (i1 PredRegs:$src1)), (i1 PredRegs:$src3)))>;
4439 // Map Pd = load(addr) -> Rs = load(addr); Pd = Rs.
4440 def : Pat<(i1 (load ADDRriS11_2:$addr)),
4441 (i1 (C2_tfrrp (i32 (L2_loadrb_io AddrFI:$addr, 0))))>;
4443 // Map for truncating from 64 immediates to 32 bit immediates.
4444 def : Pat<(i32 (trunc (i64 DoubleRegs:$src))),
4445 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src), subreg_loreg))>;
4447 // Map for truncating from i64 immediates to i1 bit immediates.
4448 def : Pat<(i1 (trunc (i64 DoubleRegs:$src))),
4449 (i1 (C2_tfrrp (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
4452 // Map memb(Rs) = Rdd -> memb(Rs) = Rt.
4453 def : Pat<(truncstorei8 (i64 DoubleRegs:$src), ADDRriS11_0:$addr),
4454 (S2_storerb_io AddrFI:$addr, 0, (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
4457 // Map memh(Rs) = Rdd -> memh(Rs) = Rt.
4458 def : Pat<(truncstorei16 (i64 DoubleRegs:$src), ADDRriS11_0:$addr),
4459 (S2_storerh_io AddrFI:$addr, 0, (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
4461 // Map memw(Rs) = Rdd -> memw(Rs) = Rt
4462 def : Pat<(truncstorei32 (i64 DoubleRegs:$src), ADDRriS11_0:$addr),
4463 (S2_storeri_io AddrFI:$addr, 0, (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
4466 // Map memw(Rs) = Rdd -> memw(Rs) = Rt.
4467 def : Pat<(truncstorei32 (i64 DoubleRegs:$src), ADDRriS11_0:$addr),
4468 (S2_storeri_io AddrFI:$addr, 0, (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
4471 // Map from i1 = constant<-1>; memw(addr) = i1 -> r0 = 1; memw(addr) = r0.
4472 def : Pat<(store (i1 -1), ADDRriS11_2:$addr),
4473 (S2_storerb_io AddrFI:$addr, 0, (A2_tfrsi 1))>;
4476 // Map from i1 = constant<-1>; store i1 -> r0 = 1; store r0.
4477 def : Pat<(store (i1 -1), ADDRriS11_2:$addr),
4478 (S2_storerb_io AddrFI:$addr, 0, (A2_tfrsi 1))>;
4480 // Map from memb(Rs) = Pd -> Rt = mux(Pd, #0, #1); store Rt.
4481 def : Pat<(store (i1 PredRegs:$src1), ADDRriS11_2:$addr),
4482 (S2_storerb_io AddrFI:$addr, 0, (i32 (C2_muxii (i1 PredRegs:$src1), 1, 0)) )>;
4484 // Map Rdd = anyext(Rs) -> Rdd = A2_sxtw(Rs).
4485 // Hexagon_TODO: We can probably use combine but that will cost 2 instructions.
4486 // Better way to do this?
4487 def : Pat<(i64 (anyext (i32 IntRegs:$src1))),
4488 (i64 (A2_sxtw (i32 IntRegs:$src1)))>;
4490 // Map cmple -> cmpgt.
4491 // rs <= rt -> !(rs > rt).
4492 def : Pat<(i1 (setle (i32 IntRegs:$src1), s10ExtPred:$src2)),
4493 (i1 (C2_not (C2_cmpgti (i32 IntRegs:$src1), s10ExtPred:$src2)))>;
4495 // rs <= rt -> !(rs > rt).
4496 def : Pat<(i1 (setle (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
4497 (i1 (C2_not (C2_cmpgt (i32 IntRegs:$src1), (i32 IntRegs:$src2))))>;
4499 // Rss <= Rtt -> !(Rss > Rtt).
4500 def : Pat<(i1 (setle (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
4501 (i1 (C2_not (C2_cmpgtp (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))))>;
4503 // Map cmpne -> cmpeq.
4504 // Hexagon_TODO: We should improve on this.
4505 // rs != rt -> !(rs == rt).
4506 def : Pat <(i1 (setne (i32 IntRegs:$src1), s10ExtPred:$src2)),
4507 (i1 (C2_not(i1 (C2_cmpeqi (i32 IntRegs:$src1), s10ExtPred:$src2))))>;
4509 // Map cmpne(Rs) -> !cmpeqe(Rs).
4510 // rs != rt -> !(rs == rt).
4511 def : Pat <(i1 (setne (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
4512 (i1 (C2_not (i1 (C2_cmpeq (i32 IntRegs:$src1), (i32 IntRegs:$src2)))))>;
4514 // Convert setne back to xor for hexagon since we compute w/ pred registers.
4515 def : Pat <(i1 (setne (i1 PredRegs:$src1), (i1 PredRegs:$src2))),
4516 (i1 (C2_xor (i1 PredRegs:$src1), (i1 PredRegs:$src2)))>;
4518 // Map cmpne(Rss) -> !cmpew(Rss).
4519 // rs != rt -> !(rs == rt).
4520 def : Pat <(i1 (setne (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
4521 (i1 (C2_not (i1 (C2_cmpeqp (i64 DoubleRegs:$src1),
4522 (i64 DoubleRegs:$src2)))))>;
4524 // Map cmpge(Rs, Rt) -> !(cmpgt(Rs, Rt).
4525 // rs >= rt -> !(rt > rs).
4526 def : Pat <(i1 (setge (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
4527 (i1 (C2_not (i1 (C2_cmpgt (i32 IntRegs:$src2), (i32 IntRegs:$src1)))))>;
4529 // cmpge(Rs, Imm) -> cmpgt(Rs, Imm-1)
4530 def : Pat <(i1 (setge (i32 IntRegs:$src1), s8ExtPred:$src2)),
4531 (i1 (C2_cmpgti (i32 IntRegs:$src1), (DEC_CONST_SIGNED s8ExtPred:$src2)))>;
4533 // Map cmpge(Rss, Rtt) -> !cmpgt(Rtt, Rss).
4534 // rss >= rtt -> !(rtt > rss).
4535 def : Pat <(i1 (setge (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
4536 (i1 (C2_not (i1 (C2_cmpgtp (i64 DoubleRegs:$src2),
4537 (i64 DoubleRegs:$src1)))))>;
4539 // Map cmplt(Rs, Imm) -> !cmpge(Rs, Imm).
4540 // !cmpge(Rs, Imm) -> !cmpgt(Rs, Imm-1).
4541 // rs < rt -> !(rs >= rt).
4542 def : Pat <(i1 (setlt (i32 IntRegs:$src1), s8ExtPred:$src2)),
4543 (i1 (C2_not (C2_cmpgti (i32 IntRegs:$src1), (DEC_CONST_SIGNED s8ExtPred:$src2))))>;
4545 // Map cmplt(Rs, Rt) -> cmpgt(Rt, Rs).
4546 // rs < rt -> rt > rs.
4547 // We can let assembler map it, or we can do in the compiler itself.
4548 def : Pat <(i1 (setlt (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
4549 (i1 (C2_cmpgt (i32 IntRegs:$src2), (i32 IntRegs:$src1)))>;
4551 // Map cmplt(Rss, Rtt) -> cmpgt(Rtt, Rss).
4552 // rss < rtt -> (rtt > rss).
4553 def : Pat <(i1 (setlt (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
4554 (i1 (C2_cmpgtp (i64 DoubleRegs:$src2), (i64 DoubleRegs:$src1)))>;
4556 // Map from cmpltu(Rs, Rd) -> cmpgtu(Rd, Rs)
4557 // rs < rt -> rt > rs.
4558 // We can let assembler map it, or we can do in the compiler itself.
4559 def : Pat <(i1 (setult (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
4560 (i1 (C2_cmpgtu (i32 IntRegs:$src2), (i32 IntRegs:$src1)))>;
4562 // Map from cmpltu(Rss, Rdd) -> cmpgtu(Rdd, Rss).
4563 // rs < rt -> rt > rs.
4564 def : Pat <(i1 (setult (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
4565 (i1 (C2_cmpgtup (i64 DoubleRegs:$src2), (i64 DoubleRegs:$src1)))>;
4567 // Generate cmpgeu(Rs, #0) -> cmpeq(Rs, Rs)
4568 def : Pat <(i1 (setuge (i32 IntRegs:$src1), 0)),
4569 (i1 (C2_cmpeq (i32 IntRegs:$src1), (i32 IntRegs:$src1)))>;
4571 // Generate cmpgeu(Rs, #u8) -> cmpgtu(Rs, #u8 -1)
4572 def : Pat <(i1 (setuge (i32 IntRegs:$src1), u8ExtPred:$src2)),
4573 (i1 (C2_cmpgtui (i32 IntRegs:$src1), (DEC_CONST_UNSIGNED u8ExtPred:$src2)))>;
4575 // Generate cmpgtu(Rs, #u9)
4576 def : Pat <(i1 (setugt (i32 IntRegs:$src1), u9ExtPred:$src2)),
4577 (i1 (C2_cmpgtui (i32 IntRegs:$src1), u9ExtPred:$src2))>;
4579 // Map from Rs >= Rt -> !(Rt > Rs).
4580 // rs >= rt -> !(rt > rs).
4581 def : Pat <(i1 (setuge (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
4582 (i1 (C2_not (C2_cmpgtu (i32 IntRegs:$src2), (i32 IntRegs:$src1))))>;
4584 // Map from Rs >= Rt -> !(Rt > Rs).
4585 // rs >= rt -> !(rt > rs).
4586 def : Pat <(i1 (setuge (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
4587 (i1 (C2_not (C2_cmpgtup (i64 DoubleRegs:$src2), (i64 DoubleRegs:$src1))))>;
4589 // Map from cmpleu(Rs, Rt) -> !cmpgtu(Rs, Rt).
4590 // Map from (Rs <= Rt) -> !(Rs > Rt).
4591 def : Pat <(i1 (setule (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
4592 (i1 (C2_not (C2_cmpgtu (i32 IntRegs:$src1), (i32 IntRegs:$src2))))>;
4594 // Map from cmpleu(Rss, Rtt) -> !cmpgtu(Rss, Rtt-1).
4595 // Map from (Rs <= Rt) -> !(Rs > Rt).
4596 def : Pat <(i1 (setule (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
4597 (i1 (C2_not (C2_cmpgtup (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))))>;
4601 def : Pat <(i32 (sext (i1 PredRegs:$src1))),
4602 (i32 (C2_muxii (i1 PredRegs:$src1), -1, 0))>;
4605 def : Pat <(i64 (sext (i1 PredRegs:$src1))),
4606 (i64 (A2_combinew (A2_tfrsi -1), (C2_muxii (i1 PredRegs:$src1), -1, 0)))>;
4608 // Convert sign-extended load back to load and sign extend.
4610 def: Pat <(i64 (sextloadi8 ADDRriS11_0:$src1)),
4611 (i64 (A2_sxtw (L2_loadrb_io AddrFI:$src1, 0)))>;
4613 // Convert any-extended load back to load and sign extend.
4615 def: Pat <(i64 (extloadi8 ADDRriS11_0:$src1)),
4616 (i64 (A2_sxtw (L2_loadrb_io AddrFI:$src1, 0)))>;
4618 // Convert sign-extended load back to load and sign extend.
4620 def: Pat <(i64 (sextloadi16 ADDRriS11_1:$src1)),
4621 (i64 (A2_sxtw (L2_loadrh_io AddrFI:$src1, 0)))>;
4623 // Convert sign-extended load back to load and sign extend.
4625 def: Pat <(i64 (sextloadi32 ADDRriS11_2:$src1)),
4626 (i64 (A2_sxtw (L2_loadri_io AddrFI:$src1, 0)))>;
4631 def : Pat <(i32 (zext (i1 PredRegs:$src1))),
4632 (i32 (C2_muxii (i1 PredRegs:$src1), 1, 0))>;
4635 def : Pat <(i64 (zext (i1 PredRegs:$src1))),
4636 (i64 (A2_combinew (A2_tfrsi 0), (C2_muxii (i1 PredRegs:$src1), 1, 0)))>,
4640 def : Pat <(i64 (zext (i32 IntRegs:$src1))),
4641 (i64 (A2_combinew (A2_tfrsi 0), (i32 IntRegs:$src1)))>,
4645 def: Pat <(i64 (zextloadi8 ADDRriS11_0:$src1)),
4646 (i64 (A2_combinew (A2_tfrsi 0), (L2_loadrub_io AddrFI:$src1, 0)))>,
4649 let AddedComplexity = 20 in
4650 def: Pat <(i64 (zextloadi8 (add (i32 IntRegs:$src1),
4651 s11_0ExtPred:$offset))),
4652 (i64 (A2_combinew (A2_tfrsi 0), (L2_loadrub_io IntRegs:$src1,
4653 s11_0ExtPred:$offset)))>,
4657 def: Pat <(i64 (zextloadi1 ADDRriS11_0:$src1)),
4658 (i64 (A2_combinew (A2_tfrsi 0), (L2_loadrub_io AddrFI:$src1, 0)))>,
4661 let AddedComplexity = 20 in
4662 def: Pat <(i64 (zextloadi1 (add (i32 IntRegs:$src1),
4663 s11_0ExtPred:$offset))),
4664 (i64 (A2_combinew (A2_tfrsi 0), (L2_loadrub_io IntRegs:$src1,
4665 s11_0ExtPred:$offset)))>,
4669 def: Pat <(i64 (zextloadi16 ADDRriS11_1:$src1)),
4670 (i64 (A2_combinew (A2_tfrsi 0), (L2_loadruh_io AddrFI:$src1, 0)))>,
4673 let AddedComplexity = 20 in
4674 def: Pat <(i64 (zextloadi16 (add (i32 IntRegs:$src1),
4675 s11_1ExtPred:$offset))),
4676 (i64 (A2_combinew (A2_tfrsi 0), (L2_loadruh_io IntRegs:$src1,
4677 s11_1ExtPred:$offset)))>,
4681 def: Pat <(i64 (zextloadi32 ADDRriS11_2:$src1)),
4682 (i64 (A2_combinew (A2_tfrsi 0), (L2_loadri_io AddrFI:$src1, 0)))>,
4685 let AddedComplexity = 100 in
4686 def: Pat <(i64 (zextloadi32 (i32 (add IntRegs:$src1, s11_2ExtPred:$offset)))),
4687 (i64 (A2_combinew (A2_tfrsi 0), (L2_loadri_io IntRegs:$src1,
4688 s11_2ExtPred:$offset)))>,
4691 let AddedComplexity = 10 in
4692 def: Pat <(i32 (zextloadi1 ADDRriS11_0:$src1)),
4693 (i32 (L2_loadri_io AddrFI:$src1, 0))>;
4695 // Map from Rs = Pd to Pd = mux(Pd, #1, #0)
4696 def : Pat <(i32 (zext (i1 PredRegs:$src1))),
4697 (i32 (C2_muxii (i1 PredRegs:$src1), 1, 0))>;
4699 // Map from Rs = Pd to Pd = mux(Pd, #1, #0)
4700 def : Pat <(i32 (anyext (i1 PredRegs:$src1))),
4701 (i32 (C2_muxii (i1 PredRegs:$src1), 1, 0))>;
4703 // Map from Rss = Pd to Rdd = A2_sxtw (mux(Pd, #1, #0))
4704 def : Pat <(i64 (anyext (i1 PredRegs:$src1))),
4705 (i64 (A2_sxtw (i32 (C2_muxii (i1 PredRegs:$src1), 1, 0))))>;
4708 let AddedComplexity = 100 in
4709 def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh),
4711 (i64 (zextloadi32 (i32 (add IntRegs:$src2,
4712 s11_2ExtPred:$offset2)))))),
4713 (i64 (A2_combinew (EXTRACT_SUBREG (i64 DoubleRegs:$srcHigh), subreg_loreg),
4714 (L2_loadri_io IntRegs:$src2,
4715 s11_2ExtPred:$offset2)))>;
4717 def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh),
4719 (i64 (zextloadi32 ADDRriS11_2:$srcLow)))),
4720 (i64 (A2_combinew (EXTRACT_SUBREG (i64 DoubleRegs:$srcHigh), subreg_loreg),
4721 (L2_loadri_io AddrFI:$srcLow, 0)))>;
4723 def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh),
4725 (i64 (zext (i32 IntRegs:$srcLow))))),
4726 (i64 (A2_combinew (EXTRACT_SUBREG (i64 DoubleRegs:$srcHigh), subreg_loreg),
4729 let AddedComplexity = 100 in
4730 def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh),
4732 (i64 (zextloadi32 (i32 (add IntRegs:$src2,
4733 s11_2ExtPred:$offset2)))))),
4734 (i64 (A2_combinew (EXTRACT_SUBREG (i64 DoubleRegs:$srcHigh), subreg_loreg),
4735 (L2_loadri_io IntRegs:$src2,
4736 s11_2ExtPred:$offset2)))>;
4738 def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh),
4740 (i64 (zextloadi32 ADDRriS11_2:$srcLow)))),
4741 (i64 (A2_combinew (EXTRACT_SUBREG (i64 DoubleRegs:$srcHigh), subreg_loreg),
4742 (L2_loadri_io AddrFI:$srcLow, 0)))>;
4744 def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh),
4746 (i64 (zext (i32 IntRegs:$srcLow))))),
4747 (i64 (A2_combinew (EXTRACT_SUBREG (i64 DoubleRegs:$srcHigh), subreg_loreg),
4750 // Any extended 64-bit load.
4751 // anyext i32 -> i64
4752 def: Pat <(i64 (extloadi32 ADDRriS11_2:$src1)),
4753 (i64 (A2_combinew (A2_tfrsi 0), (L2_loadri_io AddrFI:$src1, 0)))>,
4756 // When there is an offset we should prefer the pattern below over the pattern above.
4757 // The complexity of the above is 13 (gleaned from HexagonGenDAGIsel.inc)
4758 // So this complexity below is comfortably higher to allow for choosing the below.
4759 // If this is not done then we generate addresses such as
4760 // ********************************************
4761 // r1 = add (r0, #4)
4762 // r1 = memw(r1 + #0)
4764 // r1 = memw(r0 + #4)
4765 // ********************************************
4766 let AddedComplexity = 100 in
4767 def: Pat <(i64 (extloadi32 (i32 (add IntRegs:$src1, s11_2ExtPred:$offset)))),
4768 (i64 (A2_combinew (A2_tfrsi 0), (L2_loadri_io IntRegs:$src1,
4769 s11_2ExtPred:$offset)))>,
4772 // anyext i16 -> i64.
4773 def: Pat <(i64 (extloadi16 ADDRriS11_2:$src1)),
4774 (i64 (A2_combinew (A2_tfrsi 0), (L2_loadrh_io AddrFI:$src1, 0)))>,
4777 let AddedComplexity = 20 in
4778 def: Pat <(i64 (extloadi16 (add (i32 IntRegs:$src1),
4779 s11_1ExtPred:$offset))),
4780 (i64 (A2_combinew (A2_tfrsi 0), (L2_loadrh_io IntRegs:$src1,
4781 s11_1ExtPred:$offset)))>,
4784 // Map from Rdd = zxtw(Rs) -> Rdd = combine(0, Rs).
4785 def : Pat<(i64 (zext (i32 IntRegs:$src1))),
4786 (i64 (A2_combinew (A2_tfrsi 0), (i32 IntRegs:$src1)))>,
4789 // Multiply 64-bit unsigned and use upper result.
4790 def : Pat <(mulhu (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2)),
4805 (A2_combinew (A2_tfrsi 0),
4812 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
4814 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
4815 subreg_loreg)))), 32)),
4817 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg)),
4818 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_loreg)))),
4819 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_loreg)),
4820 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg)))),
4821 32)), subreg_loreg)))),
4822 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg)),
4823 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg))))>;
4825 // Multiply 64-bit signed and use upper result.
4826 def : Pat <(mulhs (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2)),
4830 (A2_combinew (A2_tfrsi 0),
4840 (A2_combinew (A2_tfrsi 0),
4847 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
4849 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
4850 subreg_loreg)))), 32)),
4852 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg)),
4853 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_loreg)))),
4854 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_loreg)),
4855 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg)))),
4856 32)), subreg_loreg)))),
4857 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg)),
4858 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg))))>;
4860 // Hexagon specific ISD nodes.
4861 //def SDTHexagonADJDYNALLOC : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>]>;
4862 def SDTHexagonADJDYNALLOC : SDTypeProfile<1, 2,
4863 [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
4864 def Hexagon_ADJDYNALLOC : SDNode<"HexagonISD::ADJDYNALLOC",
4865 SDTHexagonADJDYNALLOC>;
4866 // Needed to tag these instructions for stack layout.
4867 let usesCustomInserter = 1 in
4868 def ADJDYNALLOC : ALU32_ri<(outs IntRegs:$dst), (ins IntRegs:$src1,
4870 "$dst = add($src1, #$src2)",
4871 [(set (i32 IntRegs:$dst),
4872 (Hexagon_ADJDYNALLOC (i32 IntRegs:$src1),
4873 s16ImmPred:$src2))]>;
4875 def SDTHexagonARGEXTEND : SDTypeProfile<1, 1, [SDTCisVT<0, i32>]>;
4876 def Hexagon_ARGEXTEND : SDNode<"HexagonISD::ARGEXTEND", SDTHexagonARGEXTEND>;
4877 def ARGEXTEND : ALU32_rr <(outs IntRegs:$dst), (ins IntRegs:$src1),
4879 [(set (i32 IntRegs:$dst),
4880 (Hexagon_ARGEXTEND (i32 IntRegs:$src1)))]>;
4882 let AddedComplexity = 100 in
4883 def : Pat<(i32 (sext_inreg (Hexagon_ARGEXTEND (i32 IntRegs:$src1)), i16)),
4884 (COPY (i32 IntRegs:$src1))>;
4886 def HexagonWrapperJT: SDNode<"HexagonISD::WrapperJT", SDTIntUnaryOp>;
4888 def : Pat<(HexagonWrapperJT tjumptable:$dst),
4889 (i32 (CONST32_set_jt tjumptable:$dst))>;
4893 //===----------------------------------------------------------------------===//
4895 // Shift by immediate/register and accumulate/logical
4896 //===----------------------------------------------------------------------===//
4898 // Rx[+-&|]=asr(Rs,#u5)
4899 // Rx[+-&|^]=lsr(Rs,#u5)
4900 // Rx[+-&|^]=asl(Rs,#u5)
4902 let hasNewValue = 1, opNewValue = 0 in
4903 class T_shift_imm_acc_r <string opc1, string opc2, SDNode OpNode1,
4904 SDNode OpNode2, bits<3> majOp, bits<2> minOp>
4905 : SInst_acc<(outs IntRegs:$Rx),
4906 (ins IntRegs:$src1, IntRegs:$Rs, u5Imm:$u5),
4907 "$Rx "#opc2#opc1#"($Rs, #$u5)",
4908 [(set (i32 IntRegs:$Rx),
4909 (OpNode2 (i32 IntRegs:$src1),
4910 (OpNode1 (i32 IntRegs:$Rs), u5ImmPred:$u5)))],
4911 "$src1 = $Rx", S_2op_tc_2_SLOT23> {
4916 let IClass = 0b1000;
4918 let Inst{27-24} = 0b1110;
4919 let Inst{23-22} = majOp{2-1};
4921 let Inst{7} = majOp{0};
4922 let Inst{6-5} = minOp;
4924 let Inst{20-16} = Rs;
4925 let Inst{12-8} = u5;
4928 // Rx[+-&|]=asr(Rs,Rt)
4929 // Rx[+-&|^]=lsr(Rs,Rt)
4930 // Rx[+-&|^]=asl(Rs,Rt)
4932 let hasNewValue = 1, opNewValue = 0 in
4933 class T_shift_reg_acc_r <string opc1, string opc2, SDNode OpNode1,
4934 SDNode OpNode2, bits<2> majOp, bits<2> minOp>
4935 : SInst_acc<(outs IntRegs:$Rx),
4936 (ins IntRegs:$src1, IntRegs:$Rs, IntRegs:$Rt),
4937 "$Rx "#opc2#opc1#"($Rs, $Rt)",
4938 [(set (i32 IntRegs:$Rx),
4939 (OpNode2 (i32 IntRegs:$src1),
4940 (OpNode1 (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))],
4941 "$src1 = $Rx", S_3op_tc_2_SLOT23 > {
4946 let IClass = 0b1100;
4948 let Inst{27-24} = 0b1100;
4949 let Inst{23-22} = majOp;
4950 let Inst{7-6} = minOp;
4952 let Inst{20-16} = Rs;
4953 let Inst{12-8} = Rt;
4956 // Rxx[+-&|]=asr(Rss,#u6)
4957 // Rxx[+-&|^]=lsr(Rss,#u6)
4958 // Rxx[+-&|^]=asl(Rss,#u6)
4960 class T_shift_imm_acc_p <string opc1, string opc2, SDNode OpNode1,
4961 SDNode OpNode2, bits<3> majOp, bits<2> minOp>
4962 : SInst_acc<(outs DoubleRegs:$Rxx),
4963 (ins DoubleRegs:$src1, DoubleRegs:$Rss, u6Imm:$u6),
4964 "$Rxx "#opc2#opc1#"($Rss, #$u6)",
4965 [(set (i64 DoubleRegs:$Rxx),
4966 (OpNode2 (i64 DoubleRegs:$src1),
4967 (OpNode1 (i64 DoubleRegs:$Rss), u6ImmPred:$u6)))],
4968 "$src1 = $Rxx", S_2op_tc_2_SLOT23> {
4973 let IClass = 0b1000;
4975 let Inst{27-24} = 0b0010;
4976 let Inst{23-22} = majOp{2-1};
4977 let Inst{7} = majOp{0};
4978 let Inst{6-5} = minOp;
4979 let Inst{4-0} = Rxx;
4980 let Inst{20-16} = Rss;
4981 let Inst{13-8} = u6;
4985 // Rxx[+-&|]=asr(Rss,Rt)
4986 // Rxx[+-&|^]=lsr(Rss,Rt)
4987 // Rxx[+-&|^]=asl(Rss,Rt)
4988 // Rxx[+-&|^]=lsl(Rss,Rt)
4990 class T_shift_reg_acc_p <string opc1, string opc2, SDNode OpNode1,
4991 SDNode OpNode2, bits<3> majOp, bits<2> minOp>
4992 : SInst_acc<(outs DoubleRegs:$Rxx),
4993 (ins DoubleRegs:$src1, DoubleRegs:$Rss, IntRegs:$Rt),
4994 "$Rxx "#opc2#opc1#"($Rss, $Rt)",
4995 [(set (i64 DoubleRegs:$Rxx),
4996 (OpNode2 (i64 DoubleRegs:$src1),
4997 (OpNode1 (i64 DoubleRegs:$Rss), (i32 IntRegs:$Rt))))],
4998 "$src1 = $Rxx", S_3op_tc_2_SLOT23> {
5003 let IClass = 0b1100;
5005 let Inst{27-24} = 0b1011;
5006 let Inst{23-21} = majOp;
5007 let Inst{20-16} = Rss;
5008 let Inst{12-8} = Rt;
5009 let Inst{7-6} = minOp;
5010 let Inst{4-0} = Rxx;
5013 //===----------------------------------------------------------------------===//
5014 // Multi-class for the shift instructions with logical/arithmetic operators.
5015 //===----------------------------------------------------------------------===//
5017 multiclass xtype_imm_base<string OpcStr1, string OpcStr2, SDNode OpNode1,
5018 SDNode OpNode2, bits<3> majOp, bits<2> minOp > {
5019 def _i_r#NAME : T_shift_imm_acc_r< OpcStr1, OpcStr2, OpNode1,
5020 OpNode2, majOp, minOp >;
5021 def _i_p#NAME : T_shift_imm_acc_p< OpcStr1, OpcStr2, OpNode1,
5022 OpNode2, majOp, minOp >;
5025 multiclass xtype_imm_acc<string opc1, SDNode OpNode, bits<2>minOp> {
5026 let AddedComplexity = 100 in
5027 defm _acc : xtype_imm_base< opc1, "+= ", OpNode, add, 0b001, minOp>;
5029 defm _nac : xtype_imm_base< opc1, "-= ", OpNode, sub, 0b000, minOp>;
5030 defm _and : xtype_imm_base< opc1, "&= ", OpNode, and, 0b010, minOp>;
5031 defm _or : xtype_imm_base< opc1, "|= ", OpNode, or, 0b011, minOp>;
5034 multiclass xtype_xor_imm_acc<string opc1, SDNode OpNode, bits<2>minOp> {
5035 let AddedComplexity = 100 in
5036 defm _xacc : xtype_imm_base< opc1, "^= ", OpNode, xor, 0b100, minOp>;
5039 let isCodeGenOnly = 0 in {
5040 defm S2_asr : xtype_imm_acc<"asr", sra, 0b00>;
5042 defm S2_lsr : xtype_imm_acc<"lsr", srl, 0b01>,
5043 xtype_xor_imm_acc<"lsr", srl, 0b01>;
5045 defm S2_asl : xtype_imm_acc<"asl", shl, 0b10>,
5046 xtype_xor_imm_acc<"asl", shl, 0b10>;
5049 multiclass xtype_reg_acc_r<string opc1, SDNode OpNode, bits<2>minOp> {
5050 let AddedComplexity = 100 in
5051 def _acc : T_shift_reg_acc_r <opc1, "+= ", OpNode, add, 0b11, minOp>;
5053 def _nac : T_shift_reg_acc_r <opc1, "-= ", OpNode, sub, 0b10, minOp>;
5054 def _and : T_shift_reg_acc_r <opc1, "&= ", OpNode, and, 0b01, minOp>;
5055 def _or : T_shift_reg_acc_r <opc1, "|= ", OpNode, or, 0b00, minOp>;
5058 multiclass xtype_reg_acc_p<string opc1, SDNode OpNode, bits<2>minOp> {
5059 let AddedComplexity = 100 in
5060 def _acc : T_shift_reg_acc_p <opc1, "+= ", OpNode, add, 0b110, minOp>;
5062 def _nac : T_shift_reg_acc_p <opc1, "-= ", OpNode, sub, 0b100, minOp>;
5063 def _and : T_shift_reg_acc_p <opc1, "&= ", OpNode, and, 0b010, minOp>;
5064 def _or : T_shift_reg_acc_p <opc1, "|= ", OpNode, or, 0b000, minOp>;
5065 def _xor : T_shift_reg_acc_p <opc1, "^= ", OpNode, xor, 0b011, minOp>;
5068 multiclass xtype_reg_acc<string OpcStr, SDNode OpNode, bits<2> minOp > {
5069 defm _r_r : xtype_reg_acc_r <OpcStr, OpNode, minOp>;
5070 defm _r_p : xtype_reg_acc_p <OpcStr, OpNode, minOp>;
5073 let isCodeGenOnly = 0 in {
5074 defm S2_asl : xtype_reg_acc<"asl", shl, 0b10>;
5075 defm S2_asr : xtype_reg_acc<"asr", sra, 0b00>;
5076 defm S2_lsr : xtype_reg_acc<"lsr", srl, 0b01>;
5077 defm S2_lsl : xtype_reg_acc<"lsl", shl, 0b11>;
5080 //===----------------------------------------------------------------------===//
5081 let hasSideEffects = 0 in
5082 class T_S3op_1 <string mnemonic, RegisterClass RC, bits<2> MajOp, bits<3> MinOp,
5083 bit SwapOps, bit isSat = 0, bit isRnd = 0, bit hasShift = 0>
5084 : SInst <(outs RC:$dst),
5085 (ins DoubleRegs:$src1, DoubleRegs:$src2),
5086 "$dst = "#mnemonic#"($src1, $src2)"#!if(isRnd, ":rnd", "")
5087 #!if(hasShift,":>>1","")
5088 #!if(isSat, ":sat", ""),
5089 [], "", S_3op_tc_2_SLOT23 > {
5094 let IClass = 0b1100;
5096 let Inst{27-24} = 0b0001;
5097 let Inst{23-22} = MajOp;
5098 let Inst{20-16} = !if (SwapOps, src2, src1);
5099 let Inst{12-8} = !if (SwapOps, src1, src2);
5100 let Inst{7-5} = MinOp;
5101 let Inst{4-0} = dst;
5104 class T_S3op_64 <string mnemonic, bits<2> MajOp, bits<3> MinOp, bit SwapOps,
5105 bit isSat = 0, bit isRnd = 0, bit hasShift = 0 >
5106 : T_S3op_1 <mnemonic, DoubleRegs, MajOp, MinOp, SwapOps,
5107 isSat, isRnd, hasShift>;
5109 let isCodeGenOnly = 0 in
5110 def S2_lfsp : T_S3op_64 < "lfs", 0b10, 0b110, 0>;
5112 let hasSideEffects = 0 in
5113 class T_S3op_2 <string mnemonic, bits<3> MajOp, bit SwapOps>
5114 : SInst < (outs DoubleRegs:$Rdd),
5115 (ins DoubleRegs:$Rss, DoubleRegs:$Rtt, PredRegs:$Pu),
5116 "$Rdd = "#mnemonic#"($Rss, $Rtt, $Pu)",
5117 [], "", S_3op_tc_1_SLOT23 > {
5123 let IClass = 0b1100;
5125 let Inst{27-24} = 0b0010;
5126 let Inst{23-21} = MajOp;
5127 let Inst{20-16} = !if (SwapOps, Rtt, Rss);
5128 let Inst{12-8} = !if (SwapOps, Rss, Rtt);
5130 let Inst{4-0} = Rdd;
5133 let isCodeGenOnly = 0 in {
5134 def S2_valignrb : T_S3op_2 < "valignb", 0b000, 1>;
5135 def S2_vsplicerb : T_S3op_2 < "vspliceb", 0b100, 0>;
5138 //===----------------------------------------------------------------------===//
5139 // Template class used by vector shift, vector rotate, vector neg,
5140 // 32-bit shift, 64-bit shifts, etc.
5141 //===----------------------------------------------------------------------===//
5143 let hasSideEffects = 0 in
5144 class T_S3op_3 <string mnemonic, RegisterClass RC, bits<2> MajOp,
5145 bits<2> MinOp, bit isSat = 0, list<dag> pattern = [] >
5146 : SInst <(outs RC:$dst),
5147 (ins RC:$src1, IntRegs:$src2),
5148 "$dst = "#mnemonic#"($src1, $src2)"#!if(isSat, ":sat", ""),
5149 pattern, "", S_3op_tc_1_SLOT23> {
5154 let IClass = 0b1100;
5156 let Inst{27-24} = !if(!eq(!cast<string>(RC), "IntRegs"), 0b0110, 0b0011);
5157 let Inst{23-22} = MajOp;
5158 let Inst{20-16} = src1;
5159 let Inst{12-8} = src2;
5160 let Inst{7-6} = MinOp;
5161 let Inst{4-0} = dst;
5164 let hasNewValue = 1 in
5165 class T_S3op_shift32 <string mnemonic, SDNode OpNode, bits<2> MinOp>
5166 : T_S3op_3 <mnemonic, IntRegs, 0b01, MinOp, 0,
5167 [(set (i32 IntRegs:$dst), (OpNode (i32 IntRegs:$src1),
5168 (i32 IntRegs:$src2)))]>;
5170 let hasNewValue = 1, Itinerary = S_3op_tc_2_SLOT23 in
5171 class T_S3op_shift32_Sat <string mnemonic, bits<2> MinOp>
5172 : T_S3op_3 <mnemonic, IntRegs, 0b00, MinOp, 1, []>;
5175 class T_S3op_shift64 <string mnemonic, SDNode OpNode, bits<2> MinOp>
5176 : T_S3op_3 <mnemonic, DoubleRegs, 0b10, MinOp, 0,
5177 [(set (i64 DoubleRegs:$dst), (OpNode (i64 DoubleRegs:$src1),
5178 (i32 IntRegs:$src2)))]>;
5181 class T_S3op_shiftVect <string mnemonic, bits<2> MajOp, bits<2> MinOp>
5182 : T_S3op_3 <mnemonic, DoubleRegs, MajOp, MinOp, 0, []>;
5185 // Shift by register
5186 // Rdd=[asr|lsr|asl|lsl](Rss,Rt)
5188 let isCodeGenOnly = 0 in {
5189 def S2_asr_r_p : T_S3op_shift64 < "asr", sra, 0b00>;
5190 def S2_lsr_r_p : T_S3op_shift64 < "lsr", srl, 0b01>;
5191 def S2_asl_r_p : T_S3op_shift64 < "asl", shl, 0b10>;
5192 def S2_lsl_r_p : T_S3op_shift64 < "lsl", shl, 0b11>;
5195 // Rd=[asr|lsr|asl|lsl](Rs,Rt)
5197 let isCodeGenOnly = 0 in {
5198 def S2_asr_r_r : T_S3op_shift32<"asr", sra, 0b00>;
5199 def S2_lsr_r_r : T_S3op_shift32<"lsr", srl, 0b01>;
5200 def S2_asl_r_r : T_S3op_shift32<"asl", shl, 0b10>;
5201 def S2_lsl_r_r : T_S3op_shift32<"lsl", shl, 0b11>;
5204 // Shift by register with saturation
5205 // Rd=asr(Rs,Rt):sat
5206 // Rd=asl(Rs,Rt):sat
5208 let Defs = [USR_OVF], isCodeGenOnly = 0 in {
5209 def S2_asr_r_r_sat : T_S3op_shift32_Sat<"asr", 0b00>;
5210 def S2_asl_r_r_sat : T_S3op_shift32_Sat<"asl", 0b10>;
5213 //===----------------------------------------------------------------------===//
5214 // Template class for 'insert bitfield' instructions
5215 //===----------------------------------------------------------------------===//
5216 let hasSideEffects = 0 in
5217 class T_S3op_insert <string mnemonic, RegisterClass RC>
5218 : SInst <(outs RC:$dst),
5219 (ins RC:$src1, RC:$src2, DoubleRegs:$src3),
5220 "$dst = "#mnemonic#"($src2, $src3)" ,
5221 [], "$src1 = $dst", S_3op_tc_1_SLOT23 > {
5226 let IClass = 0b1100;
5228 let Inst{27-26} = 0b10;
5229 let Inst{25-24} = !if(!eq(!cast<string>(RC), "IntRegs"), 0b00, 0b10);
5231 let Inst{20-16} = src2;
5232 let Inst{12-8} = src3;
5233 let Inst{4-0} = dst;
5236 let hasSideEffects = 0 in
5237 class T_S2op_insert <bits<4> RegTyBits, RegisterClass RC, Operand ImmOp>
5238 : SInst <(outs RC:$dst), (ins RC:$dst2, RC:$src1, ImmOp:$src2, ImmOp:$src3),
5239 "$dst = insert($src1, #$src2, #$src3)",
5240 [], "$dst2 = $dst", S_2op_tc_2_SLOT23> {
5247 string ImmOpStr = !cast<string>(ImmOp);
5249 let bit23 = !if (!eq(ImmOpStr, "u6Imm"), src3{5}, 0);
5250 let bit13 = !if (!eq(ImmOpStr, "u6Imm"), src2{5}, 0);
5252 let IClass = 0b1000;
5254 let Inst{27-24} = RegTyBits;
5255 let Inst{23} = bit23;
5256 let Inst{22-21} = src3{4-3};
5257 let Inst{20-16} = src1;
5258 let Inst{13} = bit13;
5259 let Inst{12-8} = src2{4-0};
5260 let Inst{7-5} = src3{2-0};
5261 let Inst{4-0} = dst;
5264 // Rx=insert(Rs,Rtt)
5265 // Rx=insert(Rs,#u5,#U5)
5266 let hasNewValue = 1, isCodeGenOnly = 0 in {
5267 def S2_insert_rp : T_S3op_insert <"insert", IntRegs>;
5268 def S2_insert : T_S2op_insert <0b1111, IntRegs, u5Imm>;
5271 // Rxx=insert(Rss,Rtt)
5272 // Rxx=insert(Rss,#u6,#U6)
5273 let isCodeGenOnly = 0 in {
5274 def S2_insertp_rp : T_S3op_insert<"insert", DoubleRegs>;
5275 def S2_insertp : T_S2op_insert <0b0011, DoubleRegs, u6Imm>;
5278 //===----------------------------------------------------------------------===//
5279 // Template class for 'extract bitfield' instructions
5280 //===----------------------------------------------------------------------===//
5281 let hasNewValue = 1, hasSideEffects = 0 in
5282 class T_S3op_extract <string mnemonic, bits<2> MinOp>
5283 : SInst <(outs IntRegs:$Rd), (ins IntRegs:$Rs, DoubleRegs:$Rtt),
5284 "$Rd = "#mnemonic#"($Rs, $Rtt)",
5285 [], "", S_3op_tc_2_SLOT23 > {
5290 let IClass = 0b1100;
5292 let Inst{27-22} = 0b100100;
5293 let Inst{20-16} = Rs;
5294 let Inst{12-8} = Rtt;
5295 let Inst{7-6} = MinOp;
5299 let hasSideEffects = 0 in
5300 class T_S2op_extract <string mnemonic, bits<4> RegTyBits,
5301 RegisterClass RC, Operand ImmOp>
5302 : SInst <(outs RC:$dst), (ins RC:$src1, ImmOp:$src2, ImmOp:$src3),
5303 "$dst = "#mnemonic#"($src1, #$src2, #$src3)",
5304 [], "", S_2op_tc_2_SLOT23> {
5311 string ImmOpStr = !cast<string>(ImmOp);
5313 let bit23 = !if (!eq(ImmOpStr, "u6Imm"), src3{5},
5314 !if (!eq(mnemonic, "extractu"), 0, 1));
5316 let bit13 = !if (!eq(ImmOpStr, "u6Imm"), src2{5}, 0);
5318 let IClass = 0b1000;
5320 let Inst{27-24} = RegTyBits;
5321 let Inst{23} = bit23;
5322 let Inst{22-21} = src3{4-3};
5323 let Inst{20-16} = src1;
5324 let Inst{13} = bit13;
5325 let Inst{12-8} = src2{4-0};
5326 let Inst{7-5} = src3{2-0};
5327 let Inst{4-0} = dst;
5332 // Rdd=extractu(Rss,Rtt)
5333 // Rdd=extractu(Rss,#u6,#U6)
5334 let isCodeGenOnly = 0 in {
5335 def S2_extractup_rp : T_S3op_64 < "extractu", 0b00, 0b000, 0>;
5336 def S2_extractup : T_S2op_extract <"extractu", 0b0001, DoubleRegs, u6Imm>;
5339 // Rd=extractu(Rs,Rtt)
5340 // Rd=extractu(Rs,#u5,#U5)
5341 let hasNewValue = 1, isCodeGenOnly = 0 in {
5342 def S2_extractu_rp : T_S3op_extract<"extractu", 0b00>;
5343 def S2_extractu : T_S2op_extract <"extractu", 0b1101, IntRegs, u5Imm>;
5346 //===----------------------------------------------------------------------===//
5347 // :raw for of tableindx[bdhw] insns
5348 //===----------------------------------------------------------------------===//
5350 let hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in
5351 class tableidxRaw<string OpStr, bits<2>MinOp>
5352 : SInst <(outs IntRegs:$Rx),
5353 (ins IntRegs:$_dst_, IntRegs:$Rs, u4Imm:$u4, s6Imm:$S6),
5354 "$Rx = "#OpStr#"($Rs, #$u4, #$S6):raw",
5355 [], "$Rx = $_dst_" > {
5361 let IClass = 0b1000;
5363 let Inst{27-24} = 0b0111;
5364 let Inst{23-22} = MinOp;
5365 let Inst{21} = u4{3};
5366 let Inst{20-16} = Rs;
5367 let Inst{13-8} = S6;
5368 let Inst{7-5} = u4{2-0};
5372 let isCodeGenOnly = 0 in {
5373 def S2_tableidxb : tableidxRaw<"tableidxb", 0b00>;
5374 def S2_tableidxh : tableidxRaw<"tableidxh", 0b01>;
5375 def S2_tableidxw : tableidxRaw<"tableidxw", 0b10>;
5376 def S2_tableidxd : tableidxRaw<"tableidxd", 0b11>;
5379 // Change the sign of the immediate for Rd=-mpyi(Rs,#u8)
5380 def : Pat <(mul (i32 IntRegs:$src1), (ineg n8ImmPred:$src2)),
5381 (i32 (M2_mpysin (i32 IntRegs:$src1), u8ImmPred:$src2))>;
5383 //===----------------------------------------------------------------------===//
5384 // V3 Instructions +
5385 //===----------------------------------------------------------------------===//
5387 include "HexagonInstrInfoV3.td"
5389 //===----------------------------------------------------------------------===//
5390 // V3 Instructions -
5391 //===----------------------------------------------------------------------===//
5393 //===----------------------------------------------------------------------===//
5394 // V4 Instructions +
5395 //===----------------------------------------------------------------------===//
5397 include "HexagonInstrInfoV4.td"
5399 //===----------------------------------------------------------------------===//
5400 // V4 Instructions -
5401 //===----------------------------------------------------------------------===//
5403 //===----------------------------------------------------------------------===//
5404 // V5 Instructions +
5405 //===----------------------------------------------------------------------===//
5407 include "HexagonInstrInfoV5.td"
5409 //===----------------------------------------------------------------------===//
5410 // V5 Instructions -
5411 //===----------------------------------------------------------------------===//