1 //==- HexagonInstrInfo.td - Target Description for Hexagon -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Hexagon instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 include "HexagonInstrFormats.td"
15 include "HexagonOperands.td"
17 // Pattern fragment that combines the value type and the register class
18 // into a single parameter.
19 // The pat frags in the definitions below need to have a named register,
20 // otherwise i32 will be assumed regardless of the register class. The
21 // name of the register does not matter.
22 def I1 : PatLeaf<(i1 PredRegs:$R)>;
23 def I32 : PatLeaf<(i32 IntRegs:$R)>;
24 def I64 : PatLeaf<(i64 DoubleRegs:$R)>;
25 def F32 : PatLeaf<(f32 IntRegs:$R)>;
26 def F64 : PatLeaf<(f64 DoubleRegs:$R)>;
28 //===----------------------------------------------------------------------===//
30 //===----------------------------------------------------------------------===//
32 //===----------------------------------------------------------------------===//
33 let hasSideEffects = 0, isCompare = 1, InputType = "imm", isExtendable = 1,
35 class T_CMP <string mnemonic, bits<2> MajOp, bit isNot, Operand ImmOp>
36 : ALU32Inst <(outs PredRegs:$dst),
37 (ins IntRegs:$src1, ImmOp:$src2),
38 "$dst = "#!if(isNot, "!","")#mnemonic#"($src1, #$src2)",
39 [], "",ALU32_2op_tc_2early_SLOT0123 >, ImmRegRel {
43 let CextOpcode = mnemonic;
44 let opExtentBits = !if(!eq(mnemonic, "cmp.gtu"), 9, 10);
45 let isExtentSigned = !if(!eq(mnemonic, "cmp.gtu"), 0, 1);
49 let Inst{27-24} = 0b0101;
50 let Inst{23-22} = MajOp;
51 let Inst{21} = !if(!eq(mnemonic, "cmp.gtu"), 0, src2{9});
52 let Inst{20-16} = src1;
53 let Inst{13-5} = src2{8-0};
59 def C2_cmpeqi : T_CMP <"cmp.eq", 0b00, 0, s10Ext>;
60 def C2_cmpgti : T_CMP <"cmp.gt", 0b01, 0, s10Ext>;
61 def C2_cmpgtui : T_CMP <"cmp.gtu", 0b10, 0, u9Ext>;
63 class T_CMP_pat <InstHexagon MI, PatFrag OpNode, PatLeaf ImmPred>
64 : Pat<(i1 (OpNode (i32 IntRegs:$src1), ImmPred:$src2)),
65 (MI IntRegs:$src1, ImmPred:$src2)>;
67 def : T_CMP_pat <C2_cmpeqi, seteq, s10ImmPred>;
68 def : T_CMP_pat <C2_cmpgti, setgt, s10ImmPred>;
69 def : T_CMP_pat <C2_cmpgtui, setugt, u9ImmPred>;
71 // Multi-class for logical operators.
72 multiclass ALU32_rr_ri<string OpcStr, SDNode OpNode> {
73 def rr : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
74 !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
75 [(set (i32 IntRegs:$dst), (OpNode (i32 IntRegs:$b),
77 def ri : ALU32_ri<(outs IntRegs:$dst), (ins s10Imm:$b, IntRegs:$c),
78 !strconcat("$dst = ", !strconcat(OpcStr, "(#$b, $c)")),
79 [(set (i32 IntRegs:$dst), (OpNode s10Imm:$b,
83 //===----------------------------------------------------------------------===//
85 //===----------------------------------------------------------------------===//
86 def SDTHexagonI64I32I32 : SDTypeProfile<1, 2,
87 [SDTCisVT<0, i64>, SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
89 def HexagonCOMBINE : SDNode<"HexagonISD::COMBINE", SDTHexagonI64I32I32>;
91 def HexagonWrapperCombineII :
92 SDNode<"HexagonISD::WrapperCombineII", SDTHexagonI64I32I32>;
94 def HexagonWrapperCombineRR :
95 SDNode<"HexagonISD::WrapperCombineRR", SDTHexagonI64I32I32>;
97 let hasSideEffects = 0, hasNewValue = 1, InputType = "reg" in
98 class T_ALU32_3op<string mnemonic, bits<3> MajOp, bits<3> MinOp, bit OpsRev,
100 : ALU32_rr<(outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt),
101 "$Rd = "#mnemonic#"($Rs, $Rt)",
102 [], "", ALU32_3op_tc_1_SLOT0123>, ImmRegRel, PredRel {
103 let isCommutable = IsComm;
104 let BaseOpcode = mnemonic#_rr;
105 let CextOpcode = mnemonic;
113 let Inst{26-24} = MajOp;
114 let Inst{23-21} = MinOp;
115 let Inst{20-16} = !if(OpsRev,Rt,Rs);
116 let Inst{12-8} = !if(OpsRev,Rs,Rt);
120 let hasSideEffects = 0, hasNewValue = 1 in
121 class T_ALU32_3op_pred<string mnemonic, bits<3> MajOp, bits<3> MinOp,
122 bit OpsRev, bit PredNot, bit PredNew>
123 : ALU32_rr<(outs IntRegs:$Rd), (ins PredRegs:$Pu, IntRegs:$Rs, IntRegs:$Rt),
124 "if ("#!if(PredNot,"!","")#"$Pu"#!if(PredNew,".new","")#") "#
125 "$Rd = "#mnemonic#"($Rs, $Rt)",
126 [], "", ALU32_3op_tc_1_SLOT0123>, ImmRegRel, PredNewRel {
127 let isPredicated = 1;
128 let isPredicatedFalse = PredNot;
129 let isPredicatedNew = PredNew;
130 let BaseOpcode = mnemonic#_rr;
131 let CextOpcode = mnemonic;
140 let Inst{26-24} = MajOp;
141 let Inst{23-21} = MinOp;
142 let Inst{20-16} = !if(OpsRev,Rt,Rs);
143 let Inst{13} = PredNew;
144 let Inst{12-8} = !if(OpsRev,Rs,Rt);
145 let Inst{7} = PredNot;
150 class T_ALU32_combineh<string Op1, string Op2, bits<3> MajOp, bits<3> MinOp,
152 : T_ALU32_3op<"", MajOp, MinOp, OpsRev, 0> {
153 let AsmString = "$Rd = combine($Rs"#Op1#", $Rt"#Op2#")";
156 let isCodeGenOnly = 0 in {
157 def A2_combine_hh : T_ALU32_combineh<".h", ".h", 0b011, 0b100, 1>;
158 def A2_combine_hl : T_ALU32_combineh<".h", ".l", 0b011, 0b101, 1>;
159 def A2_combine_lh : T_ALU32_combineh<".l", ".h", 0b011, 0b110, 1>;
160 def A2_combine_ll : T_ALU32_combineh<".l", ".l", 0b011, 0b111, 1>;
163 class T_ALU32_3op_sfx<string mnemonic, string suffix, bits<3> MajOp,
164 bits<3> MinOp, bit OpsRev, bit IsComm>
165 : T_ALU32_3op<"", MajOp, MinOp, OpsRev, IsComm> {
166 let AsmString = "$Rd = "#mnemonic#"($Rs, $Rt)"#suffix;
169 let Defs = [USR_OVF], Itinerary = ALU32_3op_tc_2_SLOT0123,
170 isCodeGenOnly = 0 in {
171 def A2_addsat : T_ALU32_3op_sfx<"add", ":sat", 0b110, 0b010, 0, 1>;
172 def A2_subsat : T_ALU32_3op_sfx<"sub", ":sat", 0b110, 0b110, 1, 0>;
175 multiclass T_ALU32_3op_p<string mnemonic, bits<3> MajOp, bits<3> MinOp,
177 def t : T_ALU32_3op_pred<mnemonic, MajOp, MinOp, OpsRev, 0, 0>;
178 def f : T_ALU32_3op_pred<mnemonic, MajOp, MinOp, OpsRev, 1, 0>;
179 def tnew : T_ALU32_3op_pred<mnemonic, MajOp, MinOp, OpsRev, 0, 1>;
180 def fnew : T_ALU32_3op_pred<mnemonic, MajOp, MinOp, OpsRev, 1, 1>;
183 multiclass T_ALU32_3op_A2<string mnemonic, bits<3> MajOp, bits<3> MinOp,
184 bit OpsRev, bit IsComm> {
185 let isPredicable = 1 in
186 def A2_#NAME : T_ALU32_3op <mnemonic, MajOp, MinOp, OpsRev, IsComm>;
187 defm A2_p#NAME : T_ALU32_3op_p<mnemonic, MajOp, MinOp, OpsRev>;
190 let isCodeGenOnly = 0 in {
191 defm add : T_ALU32_3op_A2<"add", 0b011, 0b000, 0, 1>;
192 defm and : T_ALU32_3op_A2<"and", 0b001, 0b000, 0, 1>;
193 defm or : T_ALU32_3op_A2<"or", 0b001, 0b001, 0, 1>;
194 defm sub : T_ALU32_3op_A2<"sub", 0b011, 0b001, 1, 0>;
195 defm xor : T_ALU32_3op_A2<"xor", 0b001, 0b011, 0, 1>;
198 // Pats for instruction selection.
199 class BinOp32_pat<SDNode Op, InstHexagon MI, ValueType ResT>
200 : Pat<(ResT (Op (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))),
201 (ResT (MI IntRegs:$Rs, IntRegs:$Rt))>;
203 def: BinOp32_pat<add, A2_add, i32>;
204 def: BinOp32_pat<and, A2_and, i32>;
205 def: BinOp32_pat<or, A2_or, i32>;
206 def: BinOp32_pat<sub, A2_sub, i32>;
207 def: BinOp32_pat<xor, A2_xor, i32>;
209 // A few special cases producing register pairs:
210 let OutOperandList = (outs DoubleRegs:$Rd), hasNewValue = 0,
211 isCodeGenOnly = 0 in {
212 def S2_packhl : T_ALU32_3op <"packhl", 0b101, 0b100, 0, 0>;
214 let isPredicable = 1 in
215 def A2_combinew : T_ALU32_3op <"combine", 0b101, 0b000, 0, 0>;
217 // Conditional combinew uses "newt/f" instead of "t/fnew".
218 def C2_ccombinewt : T_ALU32_3op_pred<"combine", 0b101, 0b000, 0, 0, 0>;
219 def C2_ccombinewf : T_ALU32_3op_pred<"combine", 0b101, 0b000, 0, 1, 0>;
222 let hasSideEffects = 0, hasNewValue = 1, isCompare = 1, InputType = "reg" in
223 class T_ALU32_3op_cmp<string mnemonic, bits<2> MinOp, bit IsNeg, bit IsComm>
224 : ALU32_rr<(outs PredRegs:$Pd), (ins IntRegs:$Rs, IntRegs:$Rt),
225 "$Pd = "#mnemonic#"($Rs, $Rt)",
226 [], "", ALU32_3op_tc_1_SLOT0123>, ImmRegRel {
227 let CextOpcode = mnemonic;
228 let isCommutable = IsComm;
234 let Inst{27-24} = 0b0010;
235 let Inst{22-21} = MinOp;
236 let Inst{20-16} = Rs;
239 let Inst{3-2} = 0b00;
243 let Itinerary = ALU32_3op_tc_2early_SLOT0123, isCodeGenOnly = 0 in {
244 def C2_cmpeq : T_ALU32_3op_cmp< "cmp.eq", 0b00, 0, 1>;
245 def C2_cmpgt : T_ALU32_3op_cmp< "cmp.gt", 0b10, 0, 0>;
246 def C2_cmpgtu : T_ALU32_3op_cmp< "cmp.gtu", 0b11, 0, 0>;
249 // Patfrag to convert the usual comparison patfrags (e.g. setlt) to ones
250 // that reverse the order of the operands.
251 class RevCmp<PatFrag F> : PatFrag<(ops node:$rhs, node:$lhs), F.Fragment>;
253 // Pats for compares. They use PatFrags as operands, not SDNodes,
254 // since seteq/setgt/etc. are defined as ParFrags.
255 class T_cmp32_rr_pat<InstHexagon MI, PatFrag Op, ValueType VT>
256 : Pat<(VT (Op (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))),
257 (VT (MI IntRegs:$Rs, IntRegs:$Rt))>;
259 def: T_cmp32_rr_pat<C2_cmpeq, seteq, i1>;
260 def: T_cmp32_rr_pat<C2_cmpgt, setgt, i1>;
261 def: T_cmp32_rr_pat<C2_cmpgtu, setugt, i1>;
263 def: T_cmp32_rr_pat<C2_cmpgt, RevCmp<setlt>, i1>;
264 def: T_cmp32_rr_pat<C2_cmpgtu, RevCmp<setult>, i1>;
266 let CextOpcode = "MUX", InputType = "reg", hasNewValue = 1,
268 def C2_mux: ALU32_rr<(outs IntRegs:$Rd),
269 (ins PredRegs:$Pu, IntRegs:$Rs, IntRegs:$Rt),
270 "$Rd = mux($Pu, $Rs, $Rt)", [], "", ALU32_3op_tc_1_SLOT0123>, ImmRegRel {
276 let CextOpcode = "mux";
277 let InputType = "reg";
278 let hasSideEffects = 0;
281 let Inst{27-24} = 0b0100;
282 let Inst{20-16} = Rs;
288 def: Pat<(i32 (select (i1 PredRegs:$Pu), (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))),
289 (C2_mux PredRegs:$Pu, IntRegs:$Rs, IntRegs:$Rt)>;
291 // Combines the two immediates into a double register.
292 // Increase complexity to make it greater than any complexity of a combine
293 // that involves a register.
295 let isReMaterializable = 1, isMoveImm = 1, isAsCheapAsAMove = 1,
296 isExtentSigned = 1, isExtendable = 1, opExtentBits = 8, opExtendable = 1,
297 AddedComplexity = 75, isCodeGenOnly = 0 in
298 def A2_combineii: ALU32Inst <(outs DoubleRegs:$Rdd), (ins s8Ext:$s8, s8Imm:$S8),
299 "$Rdd = combine(#$s8, #$S8)",
300 [(set (i64 DoubleRegs:$Rdd),
301 (i64 (HexagonCOMBINE(i32 s8ExtPred:$s8), (i32 s8ImmPred:$S8))))]> {
307 let Inst{27-23} = 0b11000;
308 let Inst{22-16} = S8{7-1};
309 let Inst{13} = S8{0};
314 //===----------------------------------------------------------------------===//
315 // Template class for predicated ADD of a reg and an Immediate value.
316 //===----------------------------------------------------------------------===//
317 let hasNewValue = 1 in
318 class T_Addri_Pred <bit PredNot, bit PredNew>
319 : ALU32_ri <(outs IntRegs:$Rd),
320 (ins PredRegs:$Pu, IntRegs:$Rs, s8Ext:$s8),
321 !if(PredNot, "if (!$Pu", "if ($Pu")#!if(PredNew,".new) $Rd = ",
322 ") $Rd = ")#"add($Rs, #$s8)"> {
328 let isPredicatedNew = PredNew;
331 let Inst{27-24} = 0b0100;
332 let Inst{23} = PredNot;
333 let Inst{22-21} = Pu;
334 let Inst{20-16} = Rs;
335 let Inst{13} = PredNew;
340 //===----------------------------------------------------------------------===//
341 // A2_addi: Add a signed immediate to a register.
342 //===----------------------------------------------------------------------===//
343 let hasNewValue = 1 in
344 class T_Addri <Operand immOp, list<dag> pattern = [] >
345 : ALU32_ri <(outs IntRegs:$Rd),
346 (ins IntRegs:$Rs, immOp:$s16),
347 "$Rd = add($Rs, #$s16)", pattern,
348 //[(set (i32 IntRegs:$Rd), (add (i32 IntRegs:$Rs), (s16ExtPred:$s16)))],
349 "", ALU32_ADDI_tc_1_SLOT0123> {
356 let Inst{27-21} = s16{15-9};
357 let Inst{20-16} = Rs;
358 let Inst{13-5} = s16{8-0};
362 //===----------------------------------------------------------------------===//
363 // Multiclass for ADD of a register and an immediate value.
364 //===----------------------------------------------------------------------===//
365 multiclass Addri_Pred<string mnemonic, bit PredNot> {
366 let isPredicatedFalse = PredNot in {
367 def _c#NAME : T_Addri_Pred<PredNot, 0>;
369 def _cdn#NAME : T_Addri_Pred<PredNot, 1>;
373 let isExtendable = 1, InputType = "imm" in
374 multiclass Addri_base<string mnemonic, SDNode OpNode> {
375 let CextOpcode = mnemonic, BaseOpcode = mnemonic#_ri in {
376 let opExtendable = 2, isExtentSigned = 1, opExtentBits = 16,
378 def NAME : T_Addri< s16Ext, // Rd=add(Rs,#s16)
379 [(set (i32 IntRegs:$Rd),
380 (add IntRegs:$Rs, s16ExtPred:$s16))]>;
382 let opExtendable = 3, isExtentSigned = 1, opExtentBits = 8,
383 hasSideEffects = 0, isPredicated = 1 in {
384 defm Pt : Addri_Pred<mnemonic, 0>;
385 defm NotPt : Addri_Pred<mnemonic, 1>;
390 let isCodeGenOnly = 0 in
391 defm ADD_ri : Addri_base<"add", add>, ImmRegRel, PredNewRel;
393 //===----------------------------------------------------------------------===//
394 // Template class used for the following ALU32 instructions.
397 //===----------------------------------------------------------------------===//
398 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 10,
399 InputType = "imm", hasNewValue = 1 in
400 class T_ALU32ri_logical <string mnemonic, SDNode OpNode, bits<2> MinOp>
401 : ALU32_ri <(outs IntRegs:$Rd),
402 (ins IntRegs:$Rs, s10Ext:$s10),
403 "$Rd = "#mnemonic#"($Rs, #$s10)" ,
404 [(set (i32 IntRegs:$Rd), (OpNode (i32 IntRegs:$Rs), s10ExtPred:$s10))]> {
408 let CextOpcode = mnemonic;
412 let Inst{27-24} = 0b0110;
413 let Inst{23-22} = MinOp;
414 let Inst{21} = s10{9};
415 let Inst{20-16} = Rs;
416 let Inst{13-5} = s10{8-0};
420 let isCodeGenOnly = 0 in {
421 def OR_ri : T_ALU32ri_logical<"or", or, 0b10>, ImmRegRel;
422 def AND_ri : T_ALU32ri_logical<"and", and, 0b00>, ImmRegRel;
425 // Subtract register from immediate
426 // Rd32=sub(#s10,Rs32)
427 let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 10,
428 CextOpcode = "sub", InputType = "imm", hasNewValue = 1, isCodeGenOnly = 0 in
429 def SUB_ri: ALU32_ri <(outs IntRegs:$Rd), (ins s10Ext:$s10, IntRegs:$Rs),
430 "$Rd = sub(#$s10, $Rs)" ,
431 [(set IntRegs:$Rd, (sub s10ExtPred:$s10, IntRegs:$Rs))] > ,
439 let Inst{27-22} = 0b011001;
440 let Inst{21} = s10{9};
441 let Inst{20-16} = Rs;
442 let Inst{13-5} = s10{8-0};
447 let hasSideEffects = 0, isCodeGenOnly = 0 in
448 def A2_nop: ALU32Inst <(outs), (ins), "nop" > {
450 let Inst{27-24} = 0b1111;
452 // Rd = not(Rs) gets mapped to Rd=sub(#-1, Rs).
453 def : Pat<(not (i32 IntRegs:$src1)),
454 (SUB_ri -1, (i32 IntRegs:$src1))>;
456 multiclass ALU32_Pbase<string mnemonic, RegisterClass RC, bit isNot,
458 let isPredicatedNew = isPredNew in
459 def NAME : ALU32_rr<(outs RC:$dst),
460 (ins PredRegs:$src1, IntRegs:$src2, IntRegs: $src3),
461 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew,".new) $dst = ",
462 ") $dst = ")#mnemonic#"($src2, $src3)",
466 let hasSideEffects = 0, hasNewValue = 1 in
467 class T_tfr16<bit isHi>
468 : ALU32Inst <(outs IntRegs:$Rx), (ins IntRegs:$src1, u16Imm:$u16),
469 "$Rx"#!if(isHi, ".h", ".l")#" = #$u16",
470 [], "$src1 = $Rx" > {
475 let Inst{27-26} = 0b00;
476 let Inst{25-24} = !if(isHi, 0b10, 0b01);
477 let Inst{23-22} = u16{15-14};
479 let Inst{20-16} = Rx;
480 let Inst{13-0} = u16{13-0};
483 let isCodeGenOnly = 0 in {
484 def A2_tfril: T_tfr16<0>;
485 def A2_tfrih: T_tfr16<1>;
488 multiclass ALU32_Pred<string mnemonic, RegisterClass RC, bit PredNot> {
489 let isPredicatedFalse = PredNot in {
490 defm _c#NAME : ALU32_Pbase<mnemonic, RC, PredNot, 0>;
492 defm _cdn#NAME : ALU32_Pbase<mnemonic, RC, PredNot, 1>;
496 // Combines the two integer registers SRC1 and SRC2 into a double register.
497 let isPredicable = 1 in
498 class T_Combine : ALU32_rr<(outs DoubleRegs:$dst),
499 (ins IntRegs:$src1, IntRegs:$src2),
500 "$dst = combine($src1, $src2)",
501 [(set (i64 DoubleRegs:$dst),
502 (i64 (HexagonWrapperCombineRR (i32 IntRegs:$src1),
503 (i32 IntRegs:$src2))))]>;
505 multiclass Combine_base {
506 let BaseOpcode = "combine" in {
507 def NAME : T_Combine;
508 let hasSideEffects = 0, isPredicated = 1 in {
509 defm Pt : ALU32_Pred<"combine", DoubleRegs, 0>;
510 defm NotPt : ALU32_Pred<"combine", DoubleRegs, 1>;
515 defm COMBINE_rr : Combine_base, PredNewRel;
517 // Combines the two immediates SRC1 and SRC2 into a double register.
518 class COMBINE_imm<Operand imm1, Operand imm2, PatLeaf pat1, PatLeaf pat2> :
519 ALU32_ii<(outs DoubleRegs:$dst), (ins imm1:$src1, imm2:$src2),
520 "$dst = combine(#$src1, #$src2)",
521 [(set (i64 DoubleRegs:$dst),
522 (i64 (HexagonWrapperCombineII (i32 pat1:$src1), (i32 pat2:$src2))))]>;
524 let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 8 in
525 def COMBINE_Ii : COMBINE_imm<s8Ext, s8Imm, s8ExtPred, s8ImmPred>;
527 // Rd = neg(Rs) gets mapped to Rd=sub(#0, Rs).
528 // Pattern definition for 'neg' was not necessary.
530 multiclass TFR_Pred<bit PredNot> {
531 let isPredicatedFalse = PredNot in {
532 def _c#NAME : ALU32_rr<(outs IntRegs:$dst),
533 (ins PredRegs:$src1, IntRegs:$src2),
534 !if(PredNot, "if (!$src1", "if ($src1")#") $dst = $src2",
537 let isPredicatedNew = 1 in
538 def _cdn#NAME : ALU32_rr<(outs IntRegs:$dst),
539 (ins PredRegs:$src1, IntRegs:$src2),
540 !if(PredNot, "if (!$src1", "if ($src1")#".new) $dst = $src2",
545 let InputType = "reg", hasSideEffects = 0 in
546 multiclass TFR_base<string CextOp> {
547 let CextOpcode = CextOp, BaseOpcode = CextOp in {
548 let isPredicable = 1 in
549 def NAME : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
553 let isPredicated = 1 in {
554 defm Pt : TFR_Pred<0>;
555 defm NotPt : TFR_Pred<1>;
560 class T_TFR64_Pred<bit PredNot, bit isPredNew>
561 : ALU32_rr<(outs DoubleRegs:$dst),
562 (ins PredRegs:$src1, DoubleRegs:$src2),
563 !if(PredNot, "if (!$src1", "if ($src1")#
564 !if(isPredNew, ".new) ", ") ")#"$dst = $src2", []>
571 let Inst{27-24} = 0b1101;
572 let Inst{13} = isPredNew;
573 let Inst{7} = PredNot;
575 let Inst{6-5} = src1;
576 let Inst{20-17} = src2{4-1};
578 let Inst{12-9} = src2{4-1};
582 multiclass TFR64_Pred<bit PredNot> {
583 let isPredicatedFalse = PredNot in {
584 def _c#NAME : T_TFR64_Pred<PredNot, 0>;
586 let isPredicatedNew = 1 in
587 def _cdn#NAME : T_TFR64_Pred<PredNot, 1>; // Predicate new
591 let hasSideEffects = 0 in
592 multiclass TFR64_base<string BaseName> {
593 let BaseOpcode = BaseName in {
594 let isPredicable = 1 in
595 def NAME : ALU32Inst <(outs DoubleRegs:$dst),
596 (ins DoubleRegs:$src1),
602 let Inst{27-23} = 0b01010;
604 let Inst{20-17} = src1{4-1};
606 let Inst{12-9} = src1{4-1};
610 let isPredicated = 1 in {
611 defm Pt : TFR64_Pred<0>;
612 defm NotPt : TFR64_Pred<1>;
617 multiclass TFRI_Pred<bit PredNot> {
618 let isMoveImm = 1, isPredicatedFalse = PredNot in {
619 def _c#NAME : ALU32_ri<(outs IntRegs:$dst),
620 (ins PredRegs:$src1, s12Ext:$src2),
621 !if(PredNot, "if (!$src1", "if ($src1")#") $dst = #$src2",
625 let isPredicatedNew = 1 in
626 def _cdn#NAME : ALU32_rr<(outs IntRegs:$dst),
627 (ins PredRegs:$src1, s12Ext:$src2),
628 !if(PredNot, "if (!$src1", "if ($src1")#".new) $dst = #$src2",
633 let InputType = "imm", isExtendable = 1, isExtentSigned = 1 in
634 multiclass TFRI_base<string CextOp> {
635 let CextOpcode = CextOp, BaseOpcode = CextOp#I in {
636 let isAsCheapAsAMove = 1 , opExtendable = 1, opExtentBits = 16,
637 isMoveImm = 1, isPredicable = 1, isReMaterializable = 1 in
638 def NAME : ALU32_ri<(outs IntRegs:$dst), (ins s16Ext:$src1),
640 [(set (i32 IntRegs:$dst), s16ExtPred:$src1)]>;
642 let opExtendable = 2, opExtentBits = 12, hasSideEffects = 0,
643 isPredicated = 1 in {
644 defm Pt : TFRI_Pred<0>;
645 defm NotPt : TFRI_Pred<1>;
650 defm TFRI : TFRI_base<"TFR">, ImmRegRel, PredNewRel;
651 defm TFR : TFR_base<"TFR">, ImmRegRel, PredNewRel;
652 defm TFR64 : TFR64_base<"TFR64">, PredNewRel;
654 // Transfer control register.
655 let hasSideEffects = 0 in
656 def TFCR : CRInst<(outs CRRegs:$dst), (ins IntRegs:$src1),
659 //===----------------------------------------------------------------------===//
661 //===----------------------------------------------------------------------===//
664 //===----------------------------------------------------------------------===//
666 //===----------------------------------------------------------------------===//
667 // Scalar mux register immediate.
668 let hasSideEffects = 0, isExtentSigned = 1, CextOpcode = "MUX",
669 InputType = "imm", hasNewValue = 1, isExtendable = 1, opExtentBits = 8 in
670 class T_MUX1 <bit MajOp, dag ins, string AsmStr>
671 : ALU32Inst <(outs IntRegs:$Rd), ins, AsmStr>, ImmRegRel {
678 let Inst{27-24} = 0b0011;
679 let Inst{23} = MajOp;
680 let Inst{22-21} = Pu;
681 let Inst{20-16} = Rs;
687 let opExtendable = 2, isCodeGenOnly = 0 in
688 def C2_muxri : T_MUX1<0b1, (ins PredRegs:$Pu, s8Ext:$s8, IntRegs:$Rs),
689 "$Rd = mux($Pu, #$s8, $Rs)">;
691 let opExtendable = 3, isCodeGenOnly = 0 in
692 def C2_muxir : T_MUX1<0b0, (ins PredRegs:$Pu, IntRegs:$Rs, s8Ext:$s8),
693 "$Rd = mux($Pu, $Rs, #$s8)">;
695 def : Pat<(i32 (select I1:$Pu, s8ExtPred:$s8, I32:$Rs)),
696 (C2_muxri I1:$Pu, s8ExtPred:$s8, I32:$Rs)>;
698 def : Pat<(i32 (select I1:$Pu, I32:$Rs, s8ExtPred:$s8)),
699 (C2_muxir I1:$Pu, I32:$Rs, s8ExtPred:$s8)>;
701 // C2_muxii: Scalar mux immediates.
702 let isExtentSigned = 1, hasNewValue = 1, isExtendable = 1,
703 opExtentBits = 8, opExtendable = 2, isCodeGenOnly = 0 in
704 def C2_muxii: ALU32Inst <(outs IntRegs:$Rd),
705 (ins PredRegs:$Pu, s8Ext:$s8, s8Imm:$S8),
706 "$Rd = mux($Pu, #$s8, #$S8)" ,
707 [(set (i32 IntRegs:$Rd),
708 (i32 (select I1:$Pu, s8ExtPred:$s8, s8ImmPred:$S8)))] > {
716 let Inst{27-25} = 0b101;
717 let Inst{24-23} = Pu;
718 let Inst{22-16} = S8{7-1};
719 let Inst{13} = S8{0};
724 //===----------------------------------------------------------------------===//
725 // template class for non-predicated alu32_2op instructions
726 // - aslh, asrh, sxtb, sxth, zxth
727 //===----------------------------------------------------------------------===//
728 let hasNewValue = 1, opNewValue = 0 in
729 class T_ALU32_2op <string mnemonic, bits<3> minOp> :
730 ALU32Inst < (outs IntRegs:$Rd), (ins IntRegs:$Rs),
731 "$Rd = "#mnemonic#"($Rs)", [] > {
737 let Inst{27-24} = 0b0000;
738 let Inst{23-21} = minOp;
741 let Inst{20-16} = Rs;
744 //===----------------------------------------------------------------------===//
745 // template class for predicated alu32_2op instructions
746 // - aslh, asrh, sxtb, sxth, zxtb, zxth
747 //===----------------------------------------------------------------------===//
748 let hasSideEffects = 0, validSubTargets = HasV4SubT,
749 hasNewValue = 1, opNewValue = 0 in
750 class T_ALU32_2op_Pred <string mnemonic, bits<3> minOp, bit isPredNot,
752 ALU32Inst <(outs IntRegs:$Rd), (ins PredRegs:$Pu, IntRegs:$Rs),
753 !if(isPredNot, "if (!$Pu", "if ($Pu")
754 #!if(isPredNew, ".new) ",") ")#"$Rd = "#mnemonic#"($Rs)"> {
761 let Inst{27-24} = 0b0000;
762 let Inst{23-21} = minOp;
764 let Inst{11} = isPredNot;
765 let Inst{10} = isPredNew;
768 let Inst{20-16} = Rs;
771 multiclass ALU32_2op_Pred<string mnemonic, bits<3> minOp, bit PredNot> {
772 let isPredicatedFalse = PredNot in {
773 def NAME : T_ALU32_2op_Pred<mnemonic, minOp, PredNot, 0>;
776 let isPredicatedNew = 1 in
777 def NAME#new : T_ALU32_2op_Pred<mnemonic, minOp, PredNot, 1>;
781 multiclass ALU32_2op_base<string mnemonic, bits<3> minOp> {
782 let BaseOpcode = mnemonic in {
783 let isPredicable = 1, hasSideEffects = 0 in
784 def A2_#NAME : T_ALU32_2op<mnemonic, minOp>;
786 let validSubTargets = HasV4SubT, isPredicated = 1, hasSideEffects = 0 in {
787 defm A4_p#NAME#t : ALU32_2op_Pred<mnemonic, minOp, 0>;
788 defm A4_p#NAME#f : ALU32_2op_Pred<mnemonic, minOp, 1>;
793 let isCodeGenOnly = 0 in {
794 defm aslh : ALU32_2op_base<"aslh", 0b000>, PredNewRel;
795 defm asrh : ALU32_2op_base<"asrh", 0b001>, PredNewRel;
796 defm sxtb : ALU32_2op_base<"sxtb", 0b101>, PredNewRel;
797 defm sxth : ALU32_2op_base<"sxth", 0b111>, PredNewRel;
798 defm zxth : ALU32_2op_base<"zxth", 0b110>, PredNewRel;
801 // Rd=zxtb(Rs): assembler mapped to Rd=and(Rs,#255).
802 // Compiler would want to generate 'zxtb' instead of 'and' becuase 'zxtb' has
803 // predicated forms while 'and' doesn't. Since integrated assembler can't
804 // handle 'mapped' instructions, we need to encode 'zxtb' same as 'and' where
805 // immediate operand is set to '255'.
807 let hasNewValue = 1, opNewValue = 0 in
808 class T_ZXTB: ALU32Inst < (outs IntRegs:$Rd), (ins IntRegs:$Rs),
809 "$Rd = zxtb($Rs)", [] > { // Rd = and(Rs,255)
816 let Inst{27-22} = 0b011000;
818 let Inst{20-16} = Rs;
819 let Inst{21} = s10{9};
820 let Inst{13-5} = s10{8-0};
823 //Rd=zxtb(Rs): assembler mapped to "Rd=and(Rs,#255)
824 multiclass ZXTB_base <string mnemonic, bits<3> minOp> {
825 let BaseOpcode = mnemonic in {
826 let isPredicable = 1, hasSideEffects = 0 in
827 def A2_#NAME : T_ZXTB;
829 let validSubTargets = HasV4SubT, isPredicated = 1, hasSideEffects = 0 in {
830 defm A4_p#NAME#t : ALU32_2op_Pred<mnemonic, minOp, 0>;
831 defm A4_p#NAME#f : ALU32_2op_Pred<mnemonic, minOp, 1>;
836 let isCodeGenOnly=0 in
837 defm zxtb : ZXTB_base<"zxtb",0b100>, PredNewRel;
839 def: Pat<(shl I32:$src1, (i32 16)), (A2_aslh I32:$src1)>;
840 def: Pat<(sra I32:$src1, (i32 16)), (A2_asrh I32:$src1)>;
841 def: Pat<(sext_inreg I32:$src1, i8), (A2_sxtb I32:$src1)>;
842 def: Pat<(sext_inreg I32:$src1, i16), (A2_sxth I32:$src1)>;
845 def VMUX_prr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins PredRegs:$src1,
848 "$dst = vmux($src1, $src2, $src3)",
852 //===----------------------------------------------------------------------===//
854 //===----------------------------------------------------------------------===//
857 //===----------------------------------------------------------------------===//
859 //===----------------------------------------------------------------------===//
861 // SDNode for converting immediate C to C-1.
862 def DEC_CONST_SIGNED : SDNodeXForm<imm, [{
863 // Return the byte immediate const-1 as an SDNode.
864 int32_t imm = N->getSExtValue();
865 return XformSToSM1Imm(imm);
868 // SDNode for converting immediate C to C-1.
869 def DEC_CONST_UNSIGNED : SDNodeXForm<imm, [{
870 // Return the byte immediate const-1 as an SDNode.
871 uint32_t imm = N->getZExtValue();
872 return XformUToUM1Imm(imm);
875 def CTLZ_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1),
877 [(set (i32 IntRegs:$dst), (ctlz (i32 IntRegs:$src1)))]>;
879 def CTTZ_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1),
881 [(set (i32 IntRegs:$dst), (cttz (i32 IntRegs:$src1)))]>;
883 def CTLZ64_rr : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1),
885 [(set (i32 IntRegs:$dst), (i32 (trunc (ctlz (i64 DoubleRegs:$src1)))))]>;
887 def CTTZ64_rr : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1),
889 [(set (i32 IntRegs:$dst), (i32 (trunc (cttz (i64 DoubleRegs:$src1)))))]>;
891 def TSTBIT_rr : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
892 "$dst = tstbit($src1, $src2)",
893 [(set (i1 PredRegs:$dst),
894 (setne (and (shl 1, (i32 IntRegs:$src2)), (i32 IntRegs:$src1)), 0))]>;
896 //===----------------------------------------------------------------------===//
898 //===----------------------------------------------------------------------===//
901 //===----------------------------------------------------------------------===//
903 //===----------------------------------------------------------------------===//// Add.
904 //===----------------------------------------------------------------------===//
906 // Add/Subtract halfword
907 // Rd=add(Rt.L,Rs.[HL])[:sat]
908 // Rd=sub(Rt.L,Rs.[HL])[:sat]
909 // Rd=add(Rt.[LH],Rs.[HL])[:sat][:<16]
910 // Rd=sub(Rt.[LH],Rs.[HL])[:sat][:<16]
911 //===----------------------------------------------------------------------===//
913 let hasNewValue = 1, opNewValue = 0 in
914 class T_XTYPE_ADD_SUB <bits<2> LHbits, bit isSat, bit hasShift, bit isSub>
915 : ALU64Inst <(outs IntRegs:$Rd), (ins IntRegs:$Rt, IntRegs:$Rs),
916 "$Rd = "#!if(isSub,"sub","add")#"($Rt."
917 #!if(hasShift, !if(LHbits{1},"h","l"),"l") #", $Rs."
918 #!if(hasShift, !if(LHbits{0},"h)","l)"), !if(LHbits{1},"h)","l)"))
919 #!if(isSat,":sat","")
920 #!if(hasShift,":<<16",""), [], "", ALU64_tc_1_SLOT23> {
926 let Inst{27-23} = 0b01010;
927 let Inst{22} = hasShift;
928 let Inst{21} = isSub;
930 let Inst{6-5} = LHbits;
933 let Inst{20-16} = Rs;
936 //Rd=sub(Rt.L,Rs.[LH])
937 let isCodeGenOnly = 0 in {
938 def A2_subh_l16_ll : T_XTYPE_ADD_SUB <0b00, 0, 0, 1>;
939 def A2_subh_l16_hl : T_XTYPE_ADD_SUB <0b10, 0, 0, 1>;
942 let isCodeGenOnly = 0 in {
943 //Rd=add(Rt.L,Rs.[LH])
944 def A2_addh_l16_ll : T_XTYPE_ADD_SUB <0b00, 0, 0, 0>;
945 def A2_addh_l16_hl : T_XTYPE_ADD_SUB <0b10, 0, 0, 0>;
948 let Itinerary = ALU64_tc_2_SLOT23, Defs = [USR_OVF], isCodeGenOnly = 0 in {
949 //Rd=sub(Rt.L,Rs.[LH]):sat
950 def A2_subh_l16_sat_ll : T_XTYPE_ADD_SUB <0b00, 1, 0, 1>;
951 def A2_subh_l16_sat_hl : T_XTYPE_ADD_SUB <0b10, 1, 0, 1>;
953 //Rd=add(Rt.L,Rs.[LH]):sat
954 def A2_addh_l16_sat_ll : T_XTYPE_ADD_SUB <0b00, 1, 0, 0>;
955 def A2_addh_l16_sat_hl : T_XTYPE_ADD_SUB <0b10, 1, 0, 0>;
958 //Rd=sub(Rt.[LH],Rs.[LH]):<<16
959 let isCodeGenOnly = 0 in {
960 def A2_subh_h16_ll : T_XTYPE_ADD_SUB <0b00, 0, 1, 1>;
961 def A2_subh_h16_lh : T_XTYPE_ADD_SUB <0b01, 0, 1, 1>;
962 def A2_subh_h16_hl : T_XTYPE_ADD_SUB <0b10, 0, 1, 1>;
963 def A2_subh_h16_hh : T_XTYPE_ADD_SUB <0b11, 0, 1, 1>;
966 //Rd=add(Rt.[LH],Rs.[LH]):<<16
967 let isCodeGenOnly = 0 in {
968 def A2_addh_h16_ll : T_XTYPE_ADD_SUB <0b00, 0, 1, 0>;
969 def A2_addh_h16_lh : T_XTYPE_ADD_SUB <0b01, 0, 1, 0>;
970 def A2_addh_h16_hl : T_XTYPE_ADD_SUB <0b10, 0, 1, 0>;
971 def A2_addh_h16_hh : T_XTYPE_ADD_SUB <0b11, 0, 1, 0>;
974 let Itinerary = ALU64_tc_2_SLOT23, Defs = [USR_OVF], isCodeGenOnly = 0 in {
975 //Rd=sub(Rt.[LH],Rs.[LH]):sat:<<16
976 def A2_subh_h16_sat_ll : T_XTYPE_ADD_SUB <0b00, 1, 1, 1>;
977 def A2_subh_h16_sat_lh : T_XTYPE_ADD_SUB <0b01, 1, 1, 1>;
978 def A2_subh_h16_sat_hl : T_XTYPE_ADD_SUB <0b10, 1, 1, 1>;
979 def A2_subh_h16_sat_hh : T_XTYPE_ADD_SUB <0b11, 1, 1, 1>;
981 //Rd=add(Rt.[LH],Rs.[LH]):sat:<<16
982 def A2_addh_h16_sat_ll : T_XTYPE_ADD_SUB <0b00, 1, 1, 0>;
983 def A2_addh_h16_sat_lh : T_XTYPE_ADD_SUB <0b01, 1, 1, 0>;
984 def A2_addh_h16_sat_hl : T_XTYPE_ADD_SUB <0b10, 1, 1, 0>;
985 def A2_addh_h16_sat_hh : T_XTYPE_ADD_SUB <0b11, 1, 1, 0>;
989 def: Pat<(sext_inreg (add I32:$src1, I32:$src2), i16),
990 (A2_addh_l16_ll I32:$src1, I32:$src2)>;
992 def: Pat<(sra (add (shl I32:$src1, (i32 16)), I32:$src2), (i32 16)),
993 (A2_addh_l16_hl I32:$src1, I32:$src2)>;
995 def: Pat<(shl (add I32:$src1, I32:$src2), (i32 16)),
996 (A2_addh_h16_ll I32:$src1, I32:$src2)>;
998 // Subtract halfword.
999 def: Pat<(sext_inreg (sub I32:$src1, I32:$src2), i16),
1000 (A2_subh_l16_ll I32:$src1, I32:$src2)>;
1002 def: Pat<(shl (sub I32:$src1, I32:$src2), (i32 16)),
1003 (A2_subh_h16_ll I32:$src1, I32:$src2)>;
1005 let hasSideEffects = 0, hasNewValue = 1, isCodeGenOnly = 0 in
1006 def S2_parityp: ALU64Inst<(outs IntRegs:$Rd),
1007 (ins DoubleRegs:$Rs, DoubleRegs:$Rt),
1008 "$Rd = parity($Rs, $Rt)", [], "", ALU64_tc_2_SLOT23> {
1013 let IClass = 0b1101;
1014 let Inst{27-24} = 0b0000;
1015 let Inst{20-16} = Rs;
1016 let Inst{12-8} = Rt;
1020 let hasNewValue = 1, opNewValue = 0, hasSideEffects = 0 in
1021 class T_XTYPE_MIN_MAX < bit isMax, bit isUnsigned >
1022 : ALU64Inst < (outs IntRegs:$Rd), (ins IntRegs:$Rt, IntRegs:$Rs),
1023 "$Rd = "#!if(isMax,"max","min")#!if(isUnsigned,"u","")
1024 #"($Rt, $Rs)", [], "", ALU64_tc_2_SLOT23> {
1029 let IClass = 0b1101;
1031 let Inst{27-23} = 0b01011;
1032 let Inst{22-21} = !if(isMax, 0b10, 0b01);
1033 let Inst{7} = isUnsigned;
1035 let Inst{12-8} = !if(isMax, Rs, Rt);
1036 let Inst{20-16} = !if(isMax, Rt, Rs);
1039 let isCodeGenOnly = 0 in {
1040 def A2_min : T_XTYPE_MIN_MAX < 0, 0 >;
1041 def A2_minu : T_XTYPE_MIN_MAX < 0, 1 >;
1042 def A2_max : T_XTYPE_MIN_MAX < 1, 0 >;
1043 def A2_maxu : T_XTYPE_MIN_MAX < 1, 1 >;
1046 // Here, depending on the operand being selected, we'll either generate a
1047 // min or max instruction.
1049 // (a>b)?a:b --> max(a,b) => Here check performed is '>' and the value selected
1050 // is the larger of two. So, the corresponding HexagonInst is passed in 'Inst'.
1051 // (a>b)?b:a --> min(a,b) => Here check performed is '>' but the smaller value
1052 // is selected and the corresponding HexagonInst is passed in 'SwapInst'.
1054 multiclass T_MinMax_pats <PatFrag Op, RegisterClass RC, ValueType VT,
1055 InstHexagon Inst, InstHexagon SwapInst> {
1056 def: Pat<(select (i1 (Op (VT RC:$src1), (VT RC:$src2))),
1057 (VT RC:$src1), (VT RC:$src2)),
1058 (Inst RC:$src1, RC:$src2)>;
1059 def: Pat<(select (i1 (Op (VT RC:$src1), (VT RC:$src2))),
1060 (VT RC:$src2), (VT RC:$src1)),
1061 (SwapInst RC:$src1, RC:$src2)>;
1065 multiclass MinMax_pats <PatFrag Op, InstHexagon Inst, InstHexagon SwapInst> {
1066 defm: T_MinMax_pats<Op, IntRegs, i32, Inst, SwapInst>;
1068 def: Pat<(sext_inreg (i32 (select (i1 (Op (i32 PositiveHalfWord:$src1),
1069 (i32 PositiveHalfWord:$src2))),
1070 (i32 PositiveHalfWord:$src1),
1071 (i32 PositiveHalfWord:$src2))), i16),
1072 (Inst IntRegs:$src1, IntRegs:$src2)>;
1074 def: Pat<(sext_inreg (i32 (select (i1 (Op (i32 PositiveHalfWord:$src1),
1075 (i32 PositiveHalfWord:$src2))),
1076 (i32 PositiveHalfWord:$src2),
1077 (i32 PositiveHalfWord:$src1))), i16),
1078 (SwapInst IntRegs:$src1, IntRegs:$src2)>;
1081 let AddedComplexity = 200 in {
1082 defm: MinMax_pats<setge, A2_max, A2_min>;
1083 defm: MinMax_pats<setgt, A2_max, A2_min>;
1084 defm: MinMax_pats<setle, A2_min, A2_max>;
1085 defm: MinMax_pats<setlt, A2_min, A2_max>;
1086 defm: MinMax_pats<setuge, A2_maxu, A2_minu>;
1087 defm: MinMax_pats<setugt, A2_maxu, A2_minu>;
1088 defm: MinMax_pats<setule, A2_minu, A2_maxu>;
1089 defm: MinMax_pats<setult, A2_minu, A2_maxu>;
1092 class T_cmp64_rr<string mnemonic, bits<3> MinOp, bit IsComm>
1093 : ALU64_rr<(outs PredRegs:$Pd), (ins DoubleRegs:$Rs, DoubleRegs:$Rt),
1094 "$Pd = "#mnemonic#"($Rs, $Rt)", [], "", ALU64_tc_2early_SLOT23> {
1096 let isCommutable = IsComm;
1097 let hasSideEffects = 0;
1103 let IClass = 0b1101;
1104 let Inst{27-21} = 0b0010100;
1105 let Inst{20-16} = Rs;
1106 let Inst{12-8} = Rt;
1107 let Inst{7-5} = MinOp;
1111 let isCodeGenOnly = 0 in {
1112 def C2_cmpeqp : T_cmp64_rr<"cmp.eq", 0b000, 1>;
1113 def C2_cmpgtp : T_cmp64_rr<"cmp.gt", 0b010, 0>;
1114 def C2_cmpgtup : T_cmp64_rr<"cmp.gtu", 0b100, 0>;
1117 class T_cmp64_rr_pat<InstHexagon MI, PatFrag CmpOp>
1118 : Pat<(i1 (CmpOp (i64 DoubleRegs:$Rs), (i64 DoubleRegs:$Rt))),
1119 (i1 (MI DoubleRegs:$Rs, DoubleRegs:$Rt))>;
1121 def: T_cmp64_rr_pat<C2_cmpeqp, seteq>;
1122 def: T_cmp64_rr_pat<C2_cmpgtp, setgt>;
1123 def: T_cmp64_rr_pat<C2_cmpgtup, setugt>;
1124 def: T_cmp64_rr_pat<C2_cmpgtp, RevCmp<setlt>>;
1125 def: T_cmp64_rr_pat<C2_cmpgtup, RevCmp<setult>>;
1127 class T_ALU64_rr<string mnemonic, string suffix, bits<4> RegType,
1128 bits<3> MajOp, bits<3> MinOp, bit OpsRev, bit IsComm,
1130 : ALU64_rr<(outs DoubleRegs:$Rd), (ins DoubleRegs:$Rs, DoubleRegs:$Rt),
1131 "$Rd = " #mnemonic# "($Rs, " #Op2Pfx# "$Rt)" #suffix, [],
1132 "", ALU64_tc_1_SLOT23> {
1133 let hasSideEffects = 0;
1134 let isCommutable = IsComm;
1140 let IClass = 0b1101;
1141 let Inst{27-24} = RegType;
1142 let Inst{23-21} = MajOp;
1143 let Inst{20-16} = !if (OpsRev,Rt,Rs);
1144 let Inst{12-8} = !if (OpsRev,Rs,Rt);
1145 let Inst{7-5} = MinOp;
1149 class T_ALU64_arith<string mnemonic, bits<3> MajOp, bits<3> MinOp, bit IsSat,
1150 bit OpsRev, bit IsComm>
1151 : T_ALU64_rr<mnemonic, !if(IsSat,":sat",""), 0b0011, MajOp, MinOp, OpsRev,
1154 let isCodeGenOnly = 0 in {
1155 def A2_addp : T_ALU64_arith<"add", 0b000, 0b111, 0, 0, 1>;
1156 def A2_subp : T_ALU64_arith<"sub", 0b001, 0b111, 0, 1, 0>;
1159 def: Pat<(i64 (add I64:$Rs, I64:$Rt)), (A2_addp I64:$Rs, I64:$Rt)>;
1160 def: Pat<(i64 (sub I64:$Rs, I64:$Rt)), (A2_subp I64:$Rs, I64:$Rt)>;
1162 class T_ALU64_logical<string mnemonic, bits<3> MinOp, bit OpsRev, bit IsComm,
1164 : T_ALU64_rr<mnemonic, "", 0b0011, 0b111, MinOp, OpsRev, IsComm,
1167 let isCodeGenOnly = 0 in {
1168 def A2_andp : T_ALU64_logical<"and", 0b000, 0, 1, 0>;
1169 def A2_orp : T_ALU64_logical<"or", 0b010, 0, 1, 0>;
1170 def A2_xorp : T_ALU64_logical<"xor", 0b100, 0, 1, 0>;
1173 def: Pat<(i64 (and I64:$Rs, I64:$Rt)), (A2_andp I64:$Rs, I64:$Rt)>;
1174 def: Pat<(i64 (or I64:$Rs, I64:$Rt)), (A2_orp I64:$Rs, I64:$Rt)>;
1175 def: Pat<(i64 (xor I64:$Rs, I64:$Rt)), (A2_xorp I64:$Rs, I64:$Rt)>;
1177 //===----------------------------------------------------------------------===//
1179 //===----------------------------------------------------------------------===//
1181 //===----------------------------------------------------------------------===//
1183 //===----------------------------------------------------------------------===//
1185 //===----------------------------------------------------------------------===//
1187 //===----------------------------------------------------------------------===//
1189 //===----------------------------------------------------------------------===//
1191 //===----------------------------------------------------------------------===//
1193 //===----------------------------------------------------------------------===//
1195 //===----------------------------------------------------------------------===//
1197 //===----------------------------------------------------------------------===//
1199 //===----------------------------------------------------------------------===//
1200 // Logical reductions on predicates.
1202 // Looping instructions.
1204 // Pipelined looping instructions.
1206 // Logical operations on predicates.
1207 let hasSideEffects = 0 in
1208 class T_LOGICAL_1OP<string MnOp, bits<2> OpBits>
1209 : CRInst<(outs PredRegs:$Pd), (ins PredRegs:$Ps),
1210 "$Pd = " # MnOp # "($Ps)", [], "", CR_tc_2early_SLOT23> {
1214 let IClass = 0b0110;
1215 let Inst{27-23} = 0b10111;
1216 let Inst{22-21} = OpBits;
1218 let Inst{17-16} = Ps;
1223 let isCodeGenOnly = 0 in {
1224 def C2_any8 : T_LOGICAL_1OP<"any8", 0b00>;
1225 def C2_all8 : T_LOGICAL_1OP<"all8", 0b01>;
1226 def C2_not : T_LOGICAL_1OP<"not", 0b10>;
1229 def: Pat<(i1 (not (i1 PredRegs:$Ps))),
1230 (C2_not PredRegs:$Ps)>;
1232 let hasSideEffects = 0 in
1233 class T_LOGICAL_2OP<string MnOp, bits<3> OpBits, bit IsNeg, bit Rev>
1234 : CRInst<(outs PredRegs:$Pd), (ins PredRegs:$Ps, PredRegs:$Pt),
1235 "$Pd = " # MnOp # "($Ps, " # !if (IsNeg,"!","") # "$Pt)",
1236 [], "", CR_tc_2early_SLOT23> {
1241 let IClass = 0b0110;
1242 let Inst{27-24} = 0b1011;
1243 let Inst{23-21} = OpBits;
1245 let Inst{17-16} = !if(Rev,Pt,Ps); // Rs and Rt are reversed for some
1246 let Inst{13} = 0b0; // instructions.
1247 let Inst{9-8} = !if(Rev,Ps,Pt);
1251 let isCodeGenOnly = 0 in {
1252 def C2_and : T_LOGICAL_2OP<"and", 0b000, 0, 1>;
1253 def C2_or : T_LOGICAL_2OP<"or", 0b001, 0, 1>;
1254 def C2_xor : T_LOGICAL_2OP<"xor", 0b010, 0, 0>;
1255 def C2_andn : T_LOGICAL_2OP<"and", 0b011, 1, 1>;
1256 def C2_orn : T_LOGICAL_2OP<"or", 0b111, 1, 1>;
1259 def: Pat<(i1 (and I1:$Ps, I1:$Pt)), (C2_and I1:$Ps, I1:$Pt)>;
1260 def: Pat<(i1 (or I1:$Ps, I1:$Pt)), (C2_or I1:$Ps, I1:$Pt)>;
1261 def: Pat<(i1 (xor I1:$Ps, I1:$Pt)), (C2_xor I1:$Ps, I1:$Pt)>;
1262 def: Pat<(i1 (and I1:$Ps, (not I1:$Pt))), (C2_andn I1:$Ps, I1:$Pt)>;
1263 def: Pat<(i1 (or I1:$Ps, (not I1:$Pt))), (C2_orn I1:$Ps, I1:$Pt)>;
1265 let hasSideEffects = 0, hasNewValue = 1, isCodeGenOnly = 0 in
1266 def C2_vitpack : SInst<(outs IntRegs:$Rd), (ins PredRegs:$Ps, PredRegs:$Pt),
1267 "$Rd = vitpack($Ps, $Pt)", [], "", S_2op_tc_1_SLOT23> {
1272 let IClass = 0b1000;
1273 let Inst{27-24} = 0b1001;
1274 let Inst{22-21} = 0b00;
1275 let Inst{17-16} = Ps;
1280 let hasSideEffects = 0, isCodeGenOnly = 0 in
1281 def C2_mask : SInst<(outs DoubleRegs:$Rd), (ins PredRegs:$Pt),
1282 "$Rd = mask($Pt)", [], "", S_2op_tc_1_SLOT23> {
1286 let IClass = 0b1000;
1287 let Inst{27-24} = 0b0110;
1292 def VALIGN_rrp : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
1295 "$dst = valignb($src1, $src2, $src3)",
1298 def VSPLICE_rrp : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
1301 "$dst = vspliceb($src1, $src2, $src3)",
1304 // User control register transfer.
1305 //===----------------------------------------------------------------------===//
1307 //===----------------------------------------------------------------------===//
1309 def retflag : SDNode<"HexagonISD::RET_FLAG", SDTNone,
1310 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
1311 def eh_return: SDNode<"HexagonISD::EH_RETURN", SDTNone,
1314 def SDHexagonBR_JT: SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
1315 def HexagonBR_JT: SDNode<"HexagonISD::BR_JT", SDHexagonBR_JT, [SDNPHasChain]>;
1317 let InputType = "imm", isBarrier = 1, isPredicable = 1,
1318 Defs = [PC], isExtendable = 1, opExtendable = 0, isExtentSigned = 1,
1319 opExtentBits = 24, isCodeGenOnly = 0 in
1320 class T_JMP <dag InsDag, list<dag> JumpList = []>
1321 : JInst<(outs), InsDag,
1322 "jump $dst" , JumpList> {
1325 let IClass = 0b0101;
1327 let Inst{27-25} = 0b100;
1328 let Inst{24-16} = dst{23-15};
1329 let Inst{13-1} = dst{14-2};
1332 let InputType = "imm", isExtendable = 1, opExtendable = 1, isExtentSigned = 1,
1333 Defs = [PC], isPredicated = 1, opExtentBits = 17 in
1334 class T_JMP_c <bit PredNot, bit isPredNew, bit isTak>:
1335 JInst<(outs ), (ins PredRegs:$src, brtarget:$dst),
1336 !if(PredNot, "if (!$src", "if ($src")#
1337 !if(isPredNew, ".new) ", ") ")#"jump"#
1338 !if(isPredNew, !if(isTak, ":t ", ":nt "), " ")#"$dst"> {
1340 let isTaken = isTak;
1341 let isBrTaken = !if(isPredNew, !if(isTaken, "true", "false"), "");
1342 let isPredicatedFalse = PredNot;
1343 let isPredicatedNew = isPredNew;
1347 let IClass = 0b0101;
1349 let Inst{27-24} = 0b1100;
1350 let Inst{21} = PredNot;
1351 let Inst{12} = !if(isPredNew, isTak, zero);
1352 let Inst{11} = isPredNew;
1353 let Inst{9-8} = src;
1354 let Inst{23-22} = dst{16-15};
1355 let Inst{20-16} = dst{14-10};
1356 let Inst{13} = dst{9};
1357 let Inst{7-1} = dst{8-2};
1360 let isBarrier = 1, Defs = [PC], isPredicable = 1, InputType = "reg" in
1361 class T_JMPr<dag InsDag = (ins IntRegs:$dst)>
1362 : JRInst<(outs ), InsDag,
1367 let IClass = 0b0101;
1368 let Inst{27-21} = 0b0010100;
1369 let Inst{20-16} = dst;
1372 let Defs = [PC], isPredicated = 1, InputType = "reg" in
1373 class T_JMPr_c <bit PredNot, bit isPredNew, bit isTak>:
1374 JRInst <(outs ), (ins PredRegs:$src, IntRegs:$dst),
1375 !if(PredNot, "if (!$src", "if ($src")#
1376 !if(isPredNew, ".new) ", ") ")#"jumpr"#
1377 !if(isPredNew, !if(isTak, ":t ", ":nt "), " ")#"$dst"> {
1379 let isTaken = isTak;
1380 let isBrTaken = !if(isPredNew, !if(isTaken, "true", "false"), "");
1381 let isPredicatedFalse = PredNot;
1382 let isPredicatedNew = isPredNew;
1386 let IClass = 0b0101;
1388 let Inst{27-22} = 0b001101;
1389 let Inst{21} = PredNot;
1390 let Inst{20-16} = dst;
1391 let Inst{12} = !if(isPredNew, isTak, zero);
1392 let Inst{11} = isPredNew;
1393 let Inst{9-8} = src;
1394 let Predicates = !if(isPredNew, [HasV3T], [HasV2T]);
1395 let validSubTargets = !if(isPredNew, HasV3SubT, HasV2SubT);
1398 multiclass JMP_Pred<bit PredNot> {
1399 def _#NAME : T_JMP_c<PredNot, 0, 0>;
1401 def _#NAME#new_t : T_JMP_c<PredNot, 1, 1>; // taken
1402 def _#NAME#new_nt : T_JMP_c<PredNot, 1, 0>; // not taken
1405 multiclass JMP_base<string BaseOp> {
1406 let BaseOpcode = BaseOp in {
1407 def NAME : T_JMP<(ins brtarget:$dst), [(br bb:$dst)]>;
1408 defm t : JMP_Pred<0>;
1409 defm f : JMP_Pred<1>;
1413 multiclass JMPR_Pred<bit PredNot> {
1414 def NAME: T_JMPr_c<PredNot, 0, 0>;
1416 def NAME#new_tV3 : T_JMPr_c<PredNot, 1, 1>; // taken
1417 def NAME#new_ntV3 : T_JMPr_c<PredNot, 1, 0>; // not taken
1420 multiclass JMPR_base<string BaseOp> {
1421 let BaseOpcode = BaseOp in {
1423 defm _t : JMPR_Pred<0>;
1424 defm _f : JMPR_Pred<1>;
1428 let isTerminator = 1, hasSideEffects = 0 in {
1430 defm JMP : JMP_base<"JMP">, PredNewRel;
1432 let isBranch = 1, isIndirectBranch = 1 in
1433 defm JMPR : JMPR_base<"JMPr">, PredNewRel;
1435 let isReturn = 1, isCodeGenOnly = 1 in
1436 defm JMPret : JMPR_base<"JMPret">, PredNewRel;
1439 def : Pat<(retflag),
1440 (JMPret (i32 R31))>;
1442 def : Pat <(brcond (i1 PredRegs:$src1), bb:$offset),
1443 (JMP_t (i1 PredRegs:$src1), bb:$offset)>;
1445 // A return through builtin_eh_return.
1446 let isReturn = 1, isTerminator = 1, isBarrier = 1, hasSideEffects = 0,
1447 isCodeGenOnly = 1, Defs = [PC], Uses = [R28], isPredicable = 0 in
1448 def EH_RETURN_JMPR : T_JMPr;
1450 def : Pat<(eh_return),
1451 (EH_RETURN_JMPR (i32 R31))>;
1453 def : Pat<(HexagonBR_JT (i32 IntRegs:$dst)),
1454 (JMPR (i32 IntRegs:$dst))>;
1456 def : Pat<(brind (i32 IntRegs:$dst)),
1457 (JMPR (i32 IntRegs:$dst))>;
1459 //===----------------------------------------------------------------------===//
1461 //===----------------------------------------------------------------------===//
1463 //===----------------------------------------------------------------------===//
1465 //===----------------------------------------------------------------------===//
1467 // Load -- MEMri operand
1468 multiclass LD_MEMri_Pbase<string mnemonic, RegisterClass RC,
1469 bit isNot, bit isPredNew> {
1470 let isPredicatedNew = isPredNew in
1471 def NAME : LDInst2<(outs RC:$dst),
1472 (ins PredRegs:$src1, MEMri:$addr),
1473 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1474 ") ")#"$dst = "#mnemonic#"($addr)",
1478 multiclass LD_MEMri_Pred<string mnemonic, RegisterClass RC, bit PredNot> {
1479 let isPredicatedFalse = PredNot in {
1480 defm _c#NAME : LD_MEMri_Pbase<mnemonic, RC, PredNot, 0>;
1482 defm _cdn#NAME : LD_MEMri_Pbase<mnemonic, RC, PredNot, 1>;
1486 let isExtendable = 1, hasSideEffects = 0 in
1487 multiclass LD_MEMri<string mnemonic, string CextOp, RegisterClass RC,
1488 bits<5> ImmBits, bits<5> PredImmBits> {
1490 let CextOpcode = CextOp, BaseOpcode = CextOp in {
1491 let opExtendable = 2, isExtentSigned = 1, opExtentBits = ImmBits,
1493 def NAME : LDInst2<(outs RC:$dst), (ins MEMri:$addr),
1494 "$dst = "#mnemonic#"($addr)",
1497 let opExtendable = 3, isExtentSigned = 0, opExtentBits = PredImmBits,
1498 isPredicated = 1 in {
1499 defm Pt : LD_MEMri_Pred<mnemonic, RC, 0 >;
1500 defm NotPt : LD_MEMri_Pred<mnemonic, RC, 1 >;
1505 let addrMode = BaseImmOffset, isMEMri = "true" in {
1506 let accessSize = ByteAccess in {
1507 defm LDrib: LD_MEMri < "memb", "LDrib", IntRegs, 11, 6>, AddrModeRel;
1508 defm LDriub: LD_MEMri < "memub" , "LDriub", IntRegs, 11, 6>, AddrModeRel;
1511 let accessSize = HalfWordAccess in {
1512 defm LDrih: LD_MEMri < "memh", "LDrih", IntRegs, 12, 7>, AddrModeRel;
1513 defm LDriuh: LD_MEMri < "memuh", "LDriuh", IntRegs, 12, 7>, AddrModeRel;
1516 let accessSize = WordAccess in
1517 defm LDriw: LD_MEMri < "memw", "LDriw", IntRegs, 13, 8>, AddrModeRel;
1519 let accessSize = DoubleWordAccess in
1520 defm LDrid: LD_MEMri < "memd", "LDrid", DoubleRegs, 14, 9>, AddrModeRel;
1523 def : Pat < (i32 (sextloadi8 ADDRriS11_0:$addr)),
1524 (LDrib ADDRriS11_0:$addr) >;
1526 def : Pat < (i32 (zextloadi8 ADDRriS11_0:$addr)),
1527 (LDriub ADDRriS11_0:$addr) >;
1529 def : Pat < (i32 (sextloadi16 ADDRriS11_1:$addr)),
1530 (LDrih ADDRriS11_1:$addr) >;
1532 def : Pat < (i32 (zextloadi16 ADDRriS11_1:$addr)),
1533 (LDriuh ADDRriS11_1:$addr) >;
1535 def : Pat < (i32 (load ADDRriS11_2:$addr)),
1536 (LDriw ADDRriS11_2:$addr) >;
1538 def : Pat < (i64 (load ADDRriS11_3:$addr)),
1539 (LDrid ADDRriS11_3:$addr) >;
1542 // Load - Base with Immediate offset addressing mode
1543 multiclass LD_Idxd_Pbase<string mnemonic, RegisterClass RC, Operand predImmOp,
1544 bit isNot, bit isPredNew> {
1545 let isPredicatedNew = isPredNew in
1546 def NAME : LDInst2<(outs RC:$dst),
1547 (ins PredRegs:$src1, IntRegs:$src2, predImmOp:$src3),
1548 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1549 ") ")#"$dst = "#mnemonic#"($src2+#$src3)",
1553 multiclass LD_Idxd_Pred<string mnemonic, RegisterClass RC, Operand predImmOp,
1555 let isPredicatedFalse = PredNot in {
1556 defm _c#NAME : LD_Idxd_Pbase<mnemonic, RC, predImmOp, PredNot, 0>;
1558 defm _cdn#NAME : LD_Idxd_Pbase<mnemonic, RC, predImmOp, PredNot, 1>;
1562 let isExtendable = 1, hasSideEffects = 0 in
1563 multiclass LD_Idxd<string mnemonic, string CextOp, RegisterClass RC,
1564 Operand ImmOp, Operand predImmOp, bits<5> ImmBits,
1565 bits<5> PredImmBits> {
1567 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed in {
1568 let opExtendable = 2, isExtentSigned = 1, opExtentBits = ImmBits,
1569 isPredicable = 1, AddedComplexity = 20 in
1570 def NAME : LDInst2<(outs RC:$dst), (ins IntRegs:$src1, ImmOp:$offset),
1571 "$dst = "#mnemonic#"($src1+#$offset)",
1574 let opExtendable = 3, isExtentSigned = 0, opExtentBits = PredImmBits,
1575 isPredicated = 1 in {
1576 defm Pt : LD_Idxd_Pred<mnemonic, RC, predImmOp, 0 >;
1577 defm NotPt : LD_Idxd_Pred<mnemonic, RC, predImmOp, 1 >;
1582 let addrMode = BaseImmOffset in {
1583 let accessSize = ByteAccess in {
1584 defm LDrib_indexed: LD_Idxd <"memb", "LDrib", IntRegs, s11_0Ext, u6_0Ext,
1585 11, 6>, AddrModeRel;
1586 defm LDriub_indexed: LD_Idxd <"memub" , "LDriub", IntRegs, s11_0Ext, u6_0Ext,
1587 11, 6>, AddrModeRel;
1589 let accessSize = HalfWordAccess in {
1590 defm LDrih_indexed: LD_Idxd <"memh", "LDrih", IntRegs, s11_1Ext, u6_1Ext,
1591 12, 7>, AddrModeRel;
1592 defm LDriuh_indexed: LD_Idxd <"memuh", "LDriuh", IntRegs, s11_1Ext, u6_1Ext,
1593 12, 7>, AddrModeRel;
1595 let accessSize = WordAccess in
1596 defm LDriw_indexed: LD_Idxd <"memw", "LDriw", IntRegs, s11_2Ext, u6_2Ext,
1597 13, 8>, AddrModeRel;
1599 let accessSize = DoubleWordAccess in
1600 defm LDrid_indexed: LD_Idxd <"memd", "LDrid", DoubleRegs, s11_3Ext, u6_3Ext,
1601 14, 9>, AddrModeRel;
1604 let AddedComplexity = 20 in {
1605 def : Pat < (i32 (sextloadi8 (add IntRegs:$src1, s11_0ExtPred:$offset))),
1606 (LDrib_indexed IntRegs:$src1, s11_0ExtPred:$offset) >;
1608 def : Pat < (i32 (zextloadi8 (add IntRegs:$src1, s11_0ExtPred:$offset))),
1609 (LDriub_indexed IntRegs:$src1, s11_0ExtPred:$offset) >;
1611 def : Pat < (i32 (sextloadi16 (add IntRegs:$src1, s11_1ExtPred:$offset))),
1612 (LDrih_indexed IntRegs:$src1, s11_1ExtPred:$offset) >;
1614 def : Pat < (i32 (zextloadi16 (add IntRegs:$src1, s11_1ExtPred:$offset))),
1615 (LDriuh_indexed IntRegs:$src1, s11_1ExtPred:$offset) >;
1617 def : Pat < (i32 (load (add IntRegs:$src1, s11_2ExtPred:$offset))),
1618 (LDriw_indexed IntRegs:$src1, s11_2ExtPred:$offset) >;
1620 def : Pat < (i64 (load (add IntRegs:$src1, s11_3ExtPred:$offset))),
1621 (LDrid_indexed IntRegs:$src1, s11_3ExtPred:$offset) >;
1624 //===----------------------------------------------------------------------===//
1625 // Post increment load
1626 //===----------------------------------------------------------------------===//
1628 multiclass LD_PostInc_Pbase<string mnemonic, RegisterClass RC, Operand ImmOp,
1629 bit isNot, bit isPredNew> {
1630 let isPredicatedNew = isPredNew in
1631 def NAME : LDInst2PI<(outs RC:$dst, IntRegs:$dst2),
1632 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset),
1633 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1634 ") ")#"$dst = "#mnemonic#"($src2++#$offset)",
1639 multiclass LD_PostInc_Pred<string mnemonic, RegisterClass RC,
1640 Operand ImmOp, bit PredNot> {
1641 let isPredicatedFalse = PredNot in {
1642 defm _c#NAME : LD_PostInc_Pbase<mnemonic, RC, ImmOp, PredNot, 0>;
1644 let Predicates = [HasV4T], validSubTargets = HasV4SubT in
1645 defm _cdn#NAME#_V4 : LD_PostInc_Pbase<mnemonic, RC, ImmOp, PredNot, 1>;
1649 multiclass LD_PostInc<string mnemonic, string BaseOp, RegisterClass RC,
1652 let BaseOpcode = "POST_"#BaseOp in {
1653 let isPredicable = 1 in
1654 def NAME : LDInst2PI<(outs RC:$dst, IntRegs:$dst2),
1655 (ins IntRegs:$src1, ImmOp:$offset),
1656 "$dst = "#mnemonic#"($src1++#$offset)",
1660 let isPredicated = 1 in {
1661 defm Pt : LD_PostInc_Pred<mnemonic, RC, ImmOp, 0 >;
1662 defm NotPt : LD_PostInc_Pred<mnemonic, RC, ImmOp, 1 >;
1667 let hasCtrlDep = 1, hasSideEffects = 0, addrMode = PostInc in {
1668 defm POST_LDrib : LD_PostInc<"memb", "LDrib", IntRegs, s4_0Imm>,
1670 defm POST_LDriub : LD_PostInc<"memub", "LDriub", IntRegs, s4_0Imm>,
1672 defm POST_LDrih : LD_PostInc<"memh", "LDrih", IntRegs, s4_1Imm>,
1674 defm POST_LDriuh : LD_PostInc<"memuh", "LDriuh", IntRegs, s4_1Imm>,
1676 defm POST_LDriw : LD_PostInc<"memw", "LDriw", IntRegs, s4_2Imm>,
1678 defm POST_LDrid : LD_PostInc<"memd", "LDrid", DoubleRegs, s4_3Imm>,
1682 def : Pat< (i32 (extloadi1 ADDRriS11_0:$addr)),
1683 (i32 (LDrib ADDRriS11_0:$addr)) >;
1685 // Load byte any-extend.
1686 def : Pat < (i32 (extloadi8 ADDRriS11_0:$addr)),
1687 (i32 (LDrib ADDRriS11_0:$addr)) >;
1689 // Indexed load byte any-extend.
1690 let AddedComplexity = 20 in
1691 def : Pat < (i32 (extloadi8 (add IntRegs:$src1, s11_0ImmPred:$offset))),
1692 (i32 (LDrib_indexed IntRegs:$src1, s11_0ImmPred:$offset)) >;
1694 def : Pat < (i32 (extloadi16 ADDRriS11_1:$addr)),
1695 (i32 (LDrih ADDRriS11_1:$addr))>;
1697 let AddedComplexity = 20 in
1698 def : Pat < (i32 (extloadi16 (add IntRegs:$src1, s11_1ImmPred:$offset))),
1699 (i32 (LDrih_indexed IntRegs:$src1, s11_1ImmPred:$offset)) >;
1701 let AddedComplexity = 10 in
1702 def : Pat < (i32 (zextloadi1 ADDRriS11_0:$addr)),
1703 (i32 (LDriub ADDRriS11_0:$addr))>;
1705 let AddedComplexity = 20 in
1706 def : Pat < (i32 (zextloadi1 (add IntRegs:$src1, s11_0ImmPred:$offset))),
1707 (i32 (LDriub_indexed IntRegs:$src1, s11_0ImmPred:$offset))>;
1710 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 13,
1711 isPseudo = 1, Defs = [R10,R11,D5], hasSideEffects = 0 in
1712 def LDriw_pred : LDInst2<(outs PredRegs:$dst),
1714 "Error; should not emit",
1717 // Deallocate stack frame.
1718 let Defs = [R29, R30, R31], Uses = [R29], hasSideEffects = 0 in {
1719 def DEALLOCFRAME : LDInst2<(outs), (ins),
1724 // Load and unpack bytes to halfwords.
1725 //===----------------------------------------------------------------------===//
1727 //===----------------------------------------------------------------------===//
1729 //===----------------------------------------------------------------------===//
1731 //===----------------------------------------------------------------------===//
1732 //===----------------------------------------------------------------------===//
1734 //===----------------------------------------------------------------------===//
1736 //===----------------------------------------------------------------------===//
1738 //===----------------------------------------------------------------------===//
1739 //===----------------------------------------------------------------------===//
1741 //===----------------------------------------------------------------------===//
1743 //===----------------------------------------------------------------------===//
1745 //===----------------------------------------------------------------------===//
1746 // Multiply and use lower result.
1748 let isExtendable = 1, opExtendable = 2, isExtentSigned = 0, opExtentBits = 8 in
1749 def MPYI_riu : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u8Ext:$src2),
1750 "$dst =+ mpyi($src1, #$src2)",
1751 [(set (i32 IntRegs:$dst), (mul (i32 IntRegs:$src1),
1752 u8ExtPred:$src2))]>;
1755 def MPYI_rin : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u8Imm:$src2),
1756 "$dst =- mpyi($src1, #$src2)",
1757 [(set (i32 IntRegs:$dst), (ineg (mul (i32 IntRegs:$src1),
1758 u8ImmPred:$src2)))]>;
1761 // s9 is NOT the same as m9 - but it works.. so far.
1762 // Assembler maps to either Rd=+mpyi(Rs,#u8 or Rd=-mpyi(Rs,#u8)
1763 // depending on the value of m9. See Arch Spec.
1764 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 9,
1765 CextOpcode = "MPYI", InputType = "imm" in
1766 def MPYI_ri : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, s9Ext:$src2),
1767 "$dst = mpyi($src1, #$src2)",
1768 [(set (i32 IntRegs:$dst), (mul (i32 IntRegs:$src1),
1769 s9ExtPred:$src2))]>, ImmRegRel;
1772 let CextOpcode = "MPYI", InputType = "reg" in
1773 def MPYI : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1774 "$dst = mpyi($src1, $src2)",
1775 [(set (i32 IntRegs:$dst), (mul (i32 IntRegs:$src1),
1776 (i32 IntRegs:$src2)))]>, ImmRegRel;
1779 let isExtendable = 1, opExtendable = 3, isExtentSigned = 0, opExtentBits = 8,
1780 CextOpcode = "MPYI_acc", InputType = "imm" in
1781 def MPYI_acc_ri : MInst_acc<(outs IntRegs:$dst),
1782 (ins IntRegs:$src1, IntRegs:$src2, u8Ext:$src3),
1783 "$dst += mpyi($src2, #$src3)",
1784 [(set (i32 IntRegs:$dst),
1785 (add (mul (i32 IntRegs:$src2), u8ExtPred:$src3),
1786 (i32 IntRegs:$src1)))],
1787 "$src1 = $dst">, ImmRegRel;
1790 let CextOpcode = "MPYI_acc", InputType = "reg" in
1791 def MPYI_acc_rr : MInst_acc<(outs IntRegs:$dst),
1792 (ins IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
1793 "$dst += mpyi($src2, $src3)",
1794 [(set (i32 IntRegs:$dst),
1795 (add (mul (i32 IntRegs:$src2), (i32 IntRegs:$src3)),
1796 (i32 IntRegs:$src1)))],
1797 "$src1 = $dst">, ImmRegRel;
1800 let isExtendable = 1, opExtendable = 3, isExtentSigned = 0, opExtentBits = 8 in
1801 def MPYI_sub_ri : MInst_acc<(outs IntRegs:$dst),
1802 (ins IntRegs:$src1, IntRegs:$src2, u8Ext:$src3),
1803 "$dst -= mpyi($src2, #$src3)",
1804 [(set (i32 IntRegs:$dst),
1805 (sub (i32 IntRegs:$src1), (mul (i32 IntRegs:$src2),
1806 u8ExtPred:$src3)))],
1809 // Multiply and use upper result.
1810 // Rd=mpy(Rs,Rt.H):<<1:rnd:sat
1811 // Rd=mpy(Rs,Rt.L):<<1:rnd:sat
1813 def MPY : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1814 "$dst = mpy($src1, $src2)",
1815 [(set (i32 IntRegs:$dst), (mulhs (i32 IntRegs:$src1),
1816 (i32 IntRegs:$src2)))]>;
1818 // Rd=mpy(Rs,Rt):rnd
1820 def MPYU : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1821 "$dst = mpyu($src1, $src2)",
1822 [(set (i32 IntRegs:$dst), (mulhu (i32 IntRegs:$src1),
1823 (i32 IntRegs:$src2)))]>;
1825 // Multiply and use full result.
1827 def MPYU64 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1828 "$dst = mpyu($src1, $src2)",
1829 [(set (i64 DoubleRegs:$dst),
1830 (mul (i64 (anyext (i32 IntRegs:$src1))),
1831 (i64 (anyext (i32 IntRegs:$src2)))))]>;
1834 def MPY64 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1835 "$dst = mpy($src1, $src2)",
1836 [(set (i64 DoubleRegs:$dst),
1837 (mul (i64 (sext (i32 IntRegs:$src1))),
1838 (i64 (sext (i32 IntRegs:$src2)))))]>;
1840 // Multiply and accumulate, use full result.
1841 // Rxx[+-]=mpy(Rs,Rt)
1843 def MPY64_acc : MInst_acc<(outs DoubleRegs:$dst),
1844 (ins DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),
1845 "$dst += mpy($src2, $src3)",
1846 [(set (i64 DoubleRegs:$dst),
1847 (add (mul (i64 (sext (i32 IntRegs:$src2))),
1848 (i64 (sext (i32 IntRegs:$src3)))),
1849 (i64 DoubleRegs:$src1)))],
1853 def MPY64_sub : MInst_acc<(outs DoubleRegs:$dst),
1854 (ins DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),
1855 "$dst -= mpy($src2, $src3)",
1856 [(set (i64 DoubleRegs:$dst),
1857 (sub (i64 DoubleRegs:$src1),
1858 (mul (i64 (sext (i32 IntRegs:$src2))),
1859 (i64 (sext (i32 IntRegs:$src3))))))],
1862 // Rxx[+-]=mpyu(Rs,Rt)
1864 def MPYU64_acc : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
1865 IntRegs:$src2, IntRegs:$src3),
1866 "$dst += mpyu($src2, $src3)",
1867 [(set (i64 DoubleRegs:$dst),
1868 (add (mul (i64 (anyext (i32 IntRegs:$src2))),
1869 (i64 (anyext (i32 IntRegs:$src3)))),
1870 (i64 DoubleRegs:$src1)))], "$src1 = $dst">;
1873 def MPYU64_sub : MInst_acc<(outs DoubleRegs:$dst),
1874 (ins DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),
1875 "$dst -= mpyu($src2, $src3)",
1876 [(set (i64 DoubleRegs:$dst),
1877 (sub (i64 DoubleRegs:$src1),
1878 (mul (i64 (anyext (i32 IntRegs:$src2))),
1879 (i64 (anyext (i32 IntRegs:$src3))))))],
1883 let InputType = "reg", CextOpcode = "ADD_acc" in
1884 def ADDrr_acc : MInst_acc<(outs IntRegs: $dst), (ins IntRegs:$src1,
1885 IntRegs:$src2, IntRegs:$src3),
1886 "$dst += add($src2, $src3)",
1887 [(set (i32 IntRegs:$dst), (add (add (i32 IntRegs:$src2),
1888 (i32 IntRegs:$src3)),
1889 (i32 IntRegs:$src1)))],
1890 "$src1 = $dst">, ImmRegRel;
1892 let isExtendable = 1, opExtendable = 3, isExtentSigned = 1, opExtentBits = 8,
1893 InputType = "imm", CextOpcode = "ADD_acc" in
1894 def ADDri_acc : MInst_acc<(outs IntRegs: $dst), (ins IntRegs:$src1,
1895 IntRegs:$src2, s8Ext:$src3),
1896 "$dst += add($src2, #$src3)",
1897 [(set (i32 IntRegs:$dst), (add (add (i32 IntRegs:$src2),
1898 s8_16ExtPred:$src3),
1899 (i32 IntRegs:$src1)))],
1900 "$src1 = $dst">, ImmRegRel;
1902 let CextOpcode = "SUB_acc", InputType = "reg" in
1903 def SUBrr_acc : MInst_acc<(outs IntRegs: $dst), (ins IntRegs:$src1,
1904 IntRegs:$src2, IntRegs:$src3),
1905 "$dst -= add($src2, $src3)",
1906 [(set (i32 IntRegs:$dst),
1907 (sub (i32 IntRegs:$src1), (add (i32 IntRegs:$src2),
1908 (i32 IntRegs:$src3))))],
1909 "$src1 = $dst">, ImmRegRel;
1911 let isExtendable = 1, opExtendable = 3, isExtentSigned = 1, opExtentBits = 8,
1912 CextOpcode = "SUB_acc", InputType = "imm" in
1913 def SUBri_acc : MInst_acc<(outs IntRegs: $dst), (ins IntRegs:$src1,
1914 IntRegs:$src2, s8Ext:$src3),
1915 "$dst -= add($src2, #$src3)",
1916 [(set (i32 IntRegs:$dst), (sub (i32 IntRegs:$src1),
1917 (add (i32 IntRegs:$src2),
1918 s8_16ExtPred:$src3)))],
1919 "$src1 = $dst">, ImmRegRel;
1921 //===----------------------------------------------------------------------===//
1923 //===----------------------------------------------------------------------===//
1925 //===----------------------------------------------------------------------===//
1927 //===----------------------------------------------------------------------===//
1928 //===----------------------------------------------------------------------===//
1930 //===----------------------------------------------------------------------===//
1932 //===----------------------------------------------------------------------===//
1934 //===----------------------------------------------------------------------===//
1935 //===----------------------------------------------------------------------===//
1937 //===----------------------------------------------------------------------===//
1939 //===----------------------------------------------------------------------===//
1941 //===----------------------------------------------------------------------===//
1942 //===----------------------------------------------------------------------===//
1944 //===----------------------------------------------------------------------===//
1946 //===----------------------------------------------------------------------===//
1948 //===----------------------------------------------------------------------===//
1950 // Store doubleword.
1952 //===----------------------------------------------------------------------===//
1953 // Post increment store
1954 //===----------------------------------------------------------------------===//
1956 multiclass ST_PostInc_Pbase<string mnemonic, RegisterClass RC, Operand ImmOp,
1957 bit isNot, bit isPredNew> {
1958 let isPredicatedNew = isPredNew in
1959 def NAME : STInst2PI<(outs IntRegs:$dst),
1960 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset, RC:$src3),
1961 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1962 ") ")#mnemonic#"($src2++#$offset) = $src3",
1967 multiclass ST_PostInc_Pred<string mnemonic, RegisterClass RC,
1968 Operand ImmOp, bit PredNot> {
1969 let isPredicatedFalse = PredNot in {
1970 defm _c#NAME : ST_PostInc_Pbase<mnemonic, RC, ImmOp, PredNot, 0>;
1972 let Predicates = [HasV4T], validSubTargets = HasV4SubT in
1973 defm _cdn#NAME#_V4 : ST_PostInc_Pbase<mnemonic, RC, ImmOp, PredNot, 1>;
1977 let hasCtrlDep = 1, isNVStorable = 1, hasSideEffects = 0 in
1978 multiclass ST_PostInc<string mnemonic, string BaseOp, RegisterClass RC,
1981 let hasCtrlDep = 1, BaseOpcode = "POST_"#BaseOp in {
1982 let isPredicable = 1 in
1983 def NAME : STInst2PI<(outs IntRegs:$dst),
1984 (ins IntRegs:$src1, ImmOp:$offset, RC:$src2),
1985 mnemonic#"($src1++#$offset) = $src2",
1989 let isPredicated = 1 in {
1990 defm Pt : ST_PostInc_Pred<mnemonic, RC, ImmOp, 0 >;
1991 defm NotPt : ST_PostInc_Pred<mnemonic, RC, ImmOp, 1 >;
1996 defm POST_STbri: ST_PostInc <"memb", "STrib", IntRegs, s4_0Imm>, AddrModeRel;
1997 defm POST_SThri: ST_PostInc <"memh", "STrih", IntRegs, s4_1Imm>, AddrModeRel;
1998 defm POST_STwri: ST_PostInc <"memw", "STriw", IntRegs, s4_2Imm>, AddrModeRel;
2000 let isNVStorable = 0 in
2001 defm POST_STdri: ST_PostInc <"memd", "STrid", DoubleRegs, s4_3Imm>, AddrModeRel;
2003 def : Pat<(post_truncsti8 (i32 IntRegs:$src1), IntRegs:$src2,
2004 s4_3ImmPred:$offset),
2005 (POST_STbri IntRegs:$src2, s4_0ImmPred:$offset, IntRegs:$src1)>;
2007 def : Pat<(post_truncsti16 (i32 IntRegs:$src1), IntRegs:$src2,
2008 s4_3ImmPred:$offset),
2009 (POST_SThri IntRegs:$src2, s4_1ImmPred:$offset, IntRegs:$src1)>;
2011 def : Pat<(post_store (i32 IntRegs:$src1), IntRegs:$src2, s4_2ImmPred:$offset),
2012 (POST_STwri IntRegs:$src2, s4_1ImmPred:$offset, IntRegs:$src1)>;
2014 def : Pat<(post_store (i64 DoubleRegs:$src1), IntRegs:$src2,
2015 s4_3ImmPred:$offset),
2016 (POST_STdri IntRegs:$src2, s4_3ImmPred:$offset, DoubleRegs:$src1)>;
2018 //===----------------------------------------------------------------------===//
2019 // multiclass for the store instructions with MEMri operand.
2020 //===----------------------------------------------------------------------===//
2021 multiclass ST_MEMri_Pbase<string mnemonic, RegisterClass RC, bit isNot,
2023 let isPredicatedNew = isPredNew in
2024 def NAME : STInst2<(outs),
2025 (ins PredRegs:$src1, MEMri:$addr, RC: $src2),
2026 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
2027 ") ")#mnemonic#"($addr) = $src2",
2031 multiclass ST_MEMri_Pred<string mnemonic, RegisterClass RC, bit PredNot> {
2032 let isPredicatedFalse = PredNot in {
2033 defm _c#NAME : ST_MEMri_Pbase<mnemonic, RC, PredNot, 0>;
2036 let validSubTargets = HasV4SubT, Predicates = [HasV4T] in
2037 defm _cdn#NAME#_V4 : ST_MEMri_Pbase<mnemonic, RC, PredNot, 1>;
2041 let isExtendable = 1, isNVStorable = 1, hasSideEffects = 0 in
2042 multiclass ST_MEMri<string mnemonic, string CextOp, RegisterClass RC,
2043 bits<5> ImmBits, bits<5> PredImmBits> {
2045 let CextOpcode = CextOp, BaseOpcode = CextOp in {
2046 let opExtendable = 1, isExtentSigned = 1, opExtentBits = ImmBits,
2048 def NAME : STInst2<(outs),
2049 (ins MEMri:$addr, RC:$src),
2050 mnemonic#"($addr) = $src",
2053 let opExtendable = 2, isExtentSigned = 0, opExtentBits = PredImmBits,
2054 isPredicated = 1 in {
2055 defm Pt : ST_MEMri_Pred<mnemonic, RC, 0>;
2056 defm NotPt : ST_MEMri_Pred<mnemonic, RC, 1>;
2061 let addrMode = BaseImmOffset, isMEMri = "true" in {
2062 let accessSize = ByteAccess in
2063 defm STrib: ST_MEMri < "memb", "STrib", IntRegs, 11, 6>, AddrModeRel;
2065 let accessSize = HalfWordAccess in
2066 defm STrih: ST_MEMri < "memh", "STrih", IntRegs, 12, 7>, AddrModeRel;
2068 let accessSize = WordAccess in
2069 defm STriw: ST_MEMri < "memw", "STriw", IntRegs, 13, 8>, AddrModeRel;
2071 let accessSize = DoubleWordAccess, isNVStorable = 0 in
2072 defm STrid: ST_MEMri < "memd", "STrid", DoubleRegs, 14, 9>, AddrModeRel;
2075 def : Pat<(truncstorei8 (i32 IntRegs:$src1), ADDRriS11_0:$addr),
2076 (STrib ADDRriS11_0:$addr, (i32 IntRegs:$src1))>;
2078 def : Pat<(truncstorei16 (i32 IntRegs:$src1), ADDRriS11_1:$addr),
2079 (STrih ADDRriS11_1:$addr, (i32 IntRegs:$src1))>;
2081 def : Pat<(store (i32 IntRegs:$src1), ADDRriS11_2:$addr),
2082 (STriw ADDRriS11_2:$addr, (i32 IntRegs:$src1))>;
2084 def : Pat<(store (i64 DoubleRegs:$src1), ADDRriS11_3:$addr),
2085 (STrid ADDRriS11_3:$addr, (i64 DoubleRegs:$src1))>;
2088 //===----------------------------------------------------------------------===//
2089 // multiclass for the store instructions with base+immediate offset
2091 //===----------------------------------------------------------------------===//
2092 multiclass ST_Idxd_Pbase<string mnemonic, RegisterClass RC, Operand predImmOp,
2093 bit isNot, bit isPredNew> {
2094 let isPredicatedNew = isPredNew in
2095 def NAME : STInst2<(outs),
2096 (ins PredRegs:$src1, IntRegs:$src2, predImmOp:$src3, RC: $src4),
2097 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
2098 ") ")#mnemonic#"($src2+#$src3) = $src4",
2102 multiclass ST_Idxd_Pred<string mnemonic, RegisterClass RC, Operand predImmOp,
2104 let isPredicatedFalse = PredNot, isPredicated = 1 in {
2105 defm _c#NAME : ST_Idxd_Pbase<mnemonic, RC, predImmOp, PredNot, 0>;
2108 let validSubTargets = HasV4SubT, Predicates = [HasV4T] in
2109 defm _cdn#NAME#_V4 : ST_Idxd_Pbase<mnemonic, RC, predImmOp, PredNot, 1>;
2113 let isExtendable = 1, isNVStorable = 1, hasSideEffects = 0 in
2114 multiclass ST_Idxd<string mnemonic, string CextOp, RegisterClass RC,
2115 Operand ImmOp, Operand predImmOp, bits<5> ImmBits,
2116 bits<5> PredImmBits> {
2118 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed in {
2119 let opExtendable = 1, isExtentSigned = 1, opExtentBits = ImmBits,
2121 def NAME : STInst2<(outs),
2122 (ins IntRegs:$src1, ImmOp:$src2, RC:$src3),
2123 mnemonic#"($src1+#$src2) = $src3",
2126 let opExtendable = 2, isExtentSigned = 0, opExtentBits = PredImmBits in {
2127 defm Pt : ST_Idxd_Pred<mnemonic, RC, predImmOp, 0>;
2128 defm NotPt : ST_Idxd_Pred<mnemonic, RC, predImmOp, 1>;
2133 let addrMode = BaseImmOffset, InputType = "reg" in {
2134 let accessSize = ByteAccess in
2135 defm STrib_indexed: ST_Idxd < "memb", "STrib", IntRegs, s11_0Ext,
2136 u6_0Ext, 11, 6>, AddrModeRel, ImmRegRel;
2138 let accessSize = HalfWordAccess in
2139 defm STrih_indexed: ST_Idxd < "memh", "STrih", IntRegs, s11_1Ext,
2140 u6_1Ext, 12, 7>, AddrModeRel, ImmRegRel;
2142 let accessSize = WordAccess in
2143 defm STriw_indexed: ST_Idxd < "memw", "STriw", IntRegs, s11_2Ext,
2144 u6_2Ext, 13, 8>, AddrModeRel, ImmRegRel;
2146 let accessSize = DoubleWordAccess, isNVStorable = 0 in
2147 defm STrid_indexed: ST_Idxd < "memd", "STrid", DoubleRegs, s11_3Ext,
2148 u6_3Ext, 14, 9>, AddrModeRel;
2151 let AddedComplexity = 10 in {
2152 def : Pat<(truncstorei8 (i32 IntRegs:$src1), (add IntRegs:$src2,
2153 s11_0ExtPred:$offset)),
2154 (STrib_indexed IntRegs:$src2, s11_0ImmPred:$offset,
2155 (i32 IntRegs:$src1))>;
2157 def : Pat<(truncstorei16 (i32 IntRegs:$src1), (add IntRegs:$src2,
2158 s11_1ExtPred:$offset)),
2159 (STrih_indexed IntRegs:$src2, s11_1ImmPred:$offset,
2160 (i32 IntRegs:$src1))>;
2162 def : Pat<(store (i32 IntRegs:$src1), (add IntRegs:$src2,
2163 s11_2ExtPred:$offset)),
2164 (STriw_indexed IntRegs:$src2, s11_2ImmPred:$offset,
2165 (i32 IntRegs:$src1))>;
2167 def : Pat<(store (i64 DoubleRegs:$src1), (add IntRegs:$src2,
2168 s11_3ExtPred:$offset)),
2169 (STrid_indexed IntRegs:$src2, s11_3ImmPred:$offset,
2170 (i64 DoubleRegs:$src1))>;
2173 // memh(Rx++#s4:1)=Rt.H
2177 let Defs = [R10,R11,D5], hasSideEffects = 0 in
2178 def STriw_pred : STInst2<(outs),
2179 (ins MEMri:$addr, PredRegs:$src1),
2180 "Error; should not emit",
2183 // Allocate stack frame.
2184 let Defs = [R29, R30], Uses = [R31, R30], hasSideEffects = 0 in {
2185 def ALLOCFRAME : STInst2<(outs),
2187 "allocframe(#$amt)",
2190 //===----------------------------------------------------------------------===//
2192 //===----------------------------------------------------------------------===//
2194 //===----------------------------------------------------------------------===//
2196 //===----------------------------------------------------------------------===//
2198 def NOT_rr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1),
2199 "$dst = not($src1)",
2200 [(set (i64 DoubleRegs:$dst), (not (i64 DoubleRegs:$src1)))]>;
2203 // Sign extend word to doubleword.
2204 def SXTW : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src1),
2205 "$dst = sxtw($src1)",
2206 [(set (i64 DoubleRegs:$dst), (sext (i32 IntRegs:$src1)))]>;
2207 //===----------------------------------------------------------------------===//
2209 //===----------------------------------------------------------------------===//
2211 //===----------------------------------------------------------------------===//
2213 //===----------------------------------------------------------------------===//
2216 def CLRBIT : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
2217 "$dst = clrbit($src1, #$src2)",
2218 [(set (i32 IntRegs:$dst), (and (i32 IntRegs:$src1),
2220 (shl 1, u5ImmPred:$src2))))]>;
2222 def CLRBIT_31 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
2223 "$dst = clrbit($src1, #$src2)",
2226 // Map from r0 = and(r1, 2147483647) to r0 = clrbit(r1, #31).
2227 def : Pat <(and (i32 IntRegs:$src1), 2147483647),
2228 (CLRBIT_31 (i32 IntRegs:$src1), 31)>;
2231 def SETBIT : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
2232 "$dst = setbit($src1, #$src2)",
2233 [(set (i32 IntRegs:$dst), (or (i32 IntRegs:$src1),
2234 (shl 1, u5ImmPred:$src2)))]>;
2236 // Map from r0 = or(r1, -2147483648) to r0 = setbit(r1, #31).
2237 def SETBIT_31 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
2238 "$dst = setbit($src1, #$src2)",
2241 def : Pat <(or (i32 IntRegs:$src1), -2147483648),
2242 (SETBIT_31 (i32 IntRegs:$src1), 31)>;
2245 def TOGBIT : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
2246 "$dst = setbit($src1, #$src2)",
2247 [(set (i32 IntRegs:$dst), (xor (i32 IntRegs:$src1),
2248 (shl 1, u5ImmPred:$src2)))]>;
2250 // Map from r0 = xor(r1, -2147483648) to r0 = togglebit(r1, #31).
2251 def TOGBIT_31 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
2252 "$dst = togglebit($src1, #$src2)",
2255 def : Pat <(xor (i32 IntRegs:$src1), -2147483648),
2256 (TOGBIT_31 (i32 IntRegs:$src1), 31)>;
2258 //===----------------------------------------------------------------------===//
2260 //===----------------------------------------------------------------------===//
2262 //===----------------------------------------------------------------------===//
2264 //===----------------------------------------------------------------------===//
2266 // Predicate transfer.
2267 let hasSideEffects = 0, hasNewValue = 1, isCodeGenOnly = 0 in
2268 def C2_tfrpr : SInst<(outs IntRegs:$Rd), (ins PredRegs:$Ps),
2269 "$Rd = $Ps", [], "", S_2op_tc_1_SLOT23> {
2273 let IClass = 0b1000;
2274 let Inst{27-24} = 0b1001;
2276 let Inst{17-16} = Ps;
2280 // Transfer general register to predicate.
2281 let hasSideEffects = 0, isCodeGenOnly = 0 in
2282 def C2_tfrrp: SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs),
2283 "$Pd = $Rs", [], "", S_2op_tc_2early_SLOT23> {
2287 let IClass = 0b1000;
2288 let Inst{27-21} = 0b0101010;
2289 let Inst{20-16} = Rs;
2293 let hasSideEffects = 0 in
2294 class T_TEST_BIT_IMM<string MnOp, bits<3> MajOp>
2295 : SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, u5Imm:$u5),
2296 "$Pd = "#MnOp#"($Rs, #$u5)",
2297 [], "", S_2op_tc_2early_SLOT23> {
2301 let IClass = 0b1000;
2302 let Inst{27-24} = 0b0101;
2303 let Inst{23-21} = MajOp;
2304 let Inst{20-16} = Rs;
2306 let Inst{12-8} = u5;
2310 def S2_tstbit_i : T_TEST_BIT_IMM<"tstbit", 0b000>;
2312 let AddedComplexity = 20 in { // Complexity greater than cmp reg-imm.
2313 def: Pat<(i1 (trunc (i32 IntRegs:$Rs))),
2314 (S2_tstbit_i IntRegs:$Rs, 0)>;
2318 //===----------------------------------------------------------------------===//
2320 //===----------------------------------------------------------------------===//
2322 //===----------------------------------------------------------------------===//
2324 //===----------------------------------------------------------------------===//
2325 // Shift by immediate.
2326 def ASR_ri : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
2327 "$dst = asr($src1, #$src2)",
2328 [(set (i32 IntRegs:$dst), (sra (i32 IntRegs:$src1),
2329 u5ImmPred:$src2))]>;
2331 def ASRd_ri : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u6Imm:$src2),
2332 "$dst = asr($src1, #$src2)",
2333 [(set (i64 DoubleRegs:$dst), (sra (i64 DoubleRegs:$src1),
2334 u6ImmPred:$src2))]>;
2336 def ASL : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
2337 "$dst = asl($src1, #$src2)",
2338 [(set (i32 IntRegs:$dst), (shl (i32 IntRegs:$src1),
2339 u5ImmPred:$src2))]>;
2341 def ASLd_ri : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u6Imm:$src2),
2342 "$dst = asl($src1, #$src2)",
2343 [(set (i64 DoubleRegs:$dst), (shl (i64 DoubleRegs:$src1),
2344 u6ImmPred:$src2))]>;
2346 def LSR_ri : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
2347 "$dst = lsr($src1, #$src2)",
2348 [(set (i32 IntRegs:$dst), (srl (i32 IntRegs:$src1),
2349 u5ImmPred:$src2))]>;
2351 def LSRd_ri : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u6Imm:$src2),
2352 "$dst = lsr($src1, #$src2)",
2353 [(set (i64 DoubleRegs:$dst), (srl (i64 DoubleRegs:$src1),
2354 u6ImmPred:$src2))]>;
2356 // Shift by immediate and add.
2357 let AddedComplexity = 100 in
2358 def ADDASL : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2,
2360 "$dst = addasl($src1, $src2, #$src3)",
2361 [(set (i32 IntRegs:$dst), (add (i32 IntRegs:$src1),
2362 (shl (i32 IntRegs:$src2),
2363 u3ImmPred:$src3)))]>;
2365 // Shift by register.
2366 def ASL_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2367 "$dst = asl($src1, $src2)",
2368 [(set (i32 IntRegs:$dst), (shl (i32 IntRegs:$src1),
2369 (i32 IntRegs:$src2)))]>;
2371 def ASR_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2372 "$dst = asr($src1, $src2)",
2373 [(set (i32 IntRegs:$dst), (sra (i32 IntRegs:$src1),
2374 (i32 IntRegs:$src2)))]>;
2376 def LSL_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2377 "$dst = lsl($src1, $src2)",
2378 [(set (i32 IntRegs:$dst), (shl (i32 IntRegs:$src1),
2379 (i32 IntRegs:$src2)))]>;
2381 def LSR_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2382 "$dst = lsr($src1, $src2)",
2383 [(set (i32 IntRegs:$dst), (srl (i32 IntRegs:$src1),
2384 (i32 IntRegs:$src2)))]>;
2386 def ASLd : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
2387 "$dst = asl($src1, $src2)",
2388 [(set (i64 DoubleRegs:$dst), (shl (i64 DoubleRegs:$src1),
2389 (i32 IntRegs:$src2)))]>;
2391 def LSLd : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
2392 "$dst = lsl($src1, $src2)",
2393 [(set (i64 DoubleRegs:$dst), (shl (i64 DoubleRegs:$src1),
2394 (i32 IntRegs:$src2)))]>;
2396 def ASRd_rr : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
2398 "$dst = asr($src1, $src2)",
2399 [(set (i64 DoubleRegs:$dst), (sra (i64 DoubleRegs:$src1),
2400 (i32 IntRegs:$src2)))]>;
2402 def LSRd_rr : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
2404 "$dst = lsr($src1, $src2)",
2405 [(set (i64 DoubleRegs:$dst), (srl (i64 DoubleRegs:$src1),
2406 (i32 IntRegs:$src2)))]>;
2408 //===----------------------------------------------------------------------===//
2410 //===----------------------------------------------------------------------===//
2412 //===----------------------------------------------------------------------===//
2414 //===----------------------------------------------------------------------===//
2415 //===----------------------------------------------------------------------===//
2417 //===----------------------------------------------------------------------===//
2419 //===----------------------------------------------------------------------===//
2421 //===----------------------------------------------------------------------===//
2422 //===----------------------------------------------------------------------===//
2424 //===----------------------------------------------------------------------===//
2426 //===----------------------------------------------------------------------===//
2428 //===----------------------------------------------------------------------===//
2430 //===----------------------------------------------------------------------===//
2432 //===----------------------------------------------------------------------===//
2433 def SDHexagonBARRIER: SDTypeProfile<0, 0, []>;
2434 def HexagonBARRIER: SDNode<"HexagonISD::BARRIER", SDHexagonBARRIER,
2437 let hasSideEffects = 1, isSolo = 1 in
2438 def BARRIER : SYSInst<(outs), (ins),
2440 [(HexagonBARRIER)]>;
2442 //===----------------------------------------------------------------------===//
2444 //===----------------------------------------------------------------------===//
2446 // TFRI64 - assembly mapped.
2447 let isReMaterializable = 1 in
2448 def TFRI64 : ALU64_rr<(outs DoubleRegs:$dst), (ins s8Imm64:$src1),
2450 [(set (i64 DoubleRegs:$dst), s8Imm64Pred:$src1)]>;
2452 let AddedComplexity = 100, isPredicated = 1 in
2453 def TFR_condset_ri : ALU32_rr<(outs IntRegs:$dst),
2454 (ins PredRegs:$src1, IntRegs:$src2, s12Imm:$src3),
2455 "Error; should not emit",
2456 [(set (i32 IntRegs:$dst),
2457 (i32 (select (i1 PredRegs:$src1), (i32 IntRegs:$src2),
2458 s12ImmPred:$src3)))]>;
2460 let AddedComplexity = 100, isPredicated = 1 in
2461 def TFR_condset_ir : ALU32_rr<(outs IntRegs:$dst),
2462 (ins PredRegs:$src1, s12Imm:$src2, IntRegs:$src3),
2463 "Error; should not emit",
2464 [(set (i32 IntRegs:$dst),
2465 (i32 (select (i1 PredRegs:$src1), s12ImmPred:$src2,
2466 (i32 IntRegs:$src3))))]>;
2468 let AddedComplexity = 100, isPredicated = 1 in
2469 def TFR_condset_ii : ALU32_rr<(outs IntRegs:$dst),
2470 (ins PredRegs:$src1, s12Imm:$src2, s12Imm:$src3),
2471 "Error; should not emit",
2472 [(set (i32 IntRegs:$dst),
2473 (i32 (select (i1 PredRegs:$src1), s12ImmPred:$src2,
2474 s12ImmPred:$src3)))]>;
2476 // Generate frameindex addresses.
2477 let isReMaterializable = 1 in
2478 def TFR_FI : ALU32_ri<(outs IntRegs:$dst), (ins FrameIndex:$src1),
2479 "$dst = add($src1)",
2480 [(set (i32 IntRegs:$dst), ADDRri:$src1)]>;
2485 let hasSideEffects = 0, Defs = [SA0, LC0] in {
2486 def LOOP0_i : CRInst<(outs), (ins brtarget:$offset, u10Imm:$src2),
2487 "loop0($offset, #$src2)",
2491 let hasSideEffects = 0, Defs = [SA0, LC0] in {
2492 def LOOP0_r : CRInst<(outs), (ins brtarget:$offset, IntRegs:$src2),
2493 "loop0($offset, $src2)",
2497 let isBranch = 1, isTerminator = 1, hasSideEffects = 0,
2498 Defs = [PC, LC0], Uses = [SA0, LC0] in {
2499 def ENDLOOP0 : Endloop<(outs), (ins brtarget:$offset),
2504 // Support for generating global address.
2505 // Taken from X86InstrInfo.td.
2506 def SDTHexagonCONST32 : SDTypeProfile<1, 1, [
2510 def HexagonCONST32 : SDNode<"HexagonISD::CONST32", SDTHexagonCONST32>;
2511 def HexagonCONST32_GP : SDNode<"HexagonISD::CONST32_GP", SDTHexagonCONST32>;
2513 // HI/LO Instructions
2514 let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0 in
2515 def LO : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$global),
2516 "$dst.l = #LO($global)",
2519 let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0 in
2520 def HI : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$global),
2521 "$dst.h = #HI($global)",
2524 let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0 in
2525 def LOi : ALU32_ri<(outs IntRegs:$dst), (ins i32imm:$imm_value),
2526 "$dst.l = #LO($imm_value)",
2530 let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0 in
2531 def HIi : ALU32_ri<(outs IntRegs:$dst), (ins i32imm:$imm_value),
2532 "$dst.h = #HI($imm_value)",
2535 let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0 in
2536 def LO_jt : ALU32_ri<(outs IntRegs:$dst), (ins jumptablebase:$jt),
2537 "$dst.l = #LO($jt)",
2540 let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0 in
2541 def HI_jt : ALU32_ri<(outs IntRegs:$dst), (ins jumptablebase:$jt),
2542 "$dst.h = #HI($jt)",
2546 let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0 in
2547 def LO_label : ALU32_ri<(outs IntRegs:$dst), (ins bblabel:$label),
2548 "$dst.l = #LO($label)",
2551 let isReMaterializable = 1, isMoveImm = 1 , hasSideEffects = 0 in
2552 def HI_label : ALU32_ri<(outs IntRegs:$dst), (ins bblabel:$label),
2553 "$dst.h = #HI($label)",
2556 // This pattern is incorrect. When we add small data, we should change
2557 // this pattern to use memw(#foo).
2558 // This is for sdata.
2559 let isMoveImm = 1 in
2560 def CONST32 : LDInst<(outs IntRegs:$dst), (ins globaladdress:$global),
2561 "$dst = CONST32(#$global)",
2562 [(set (i32 IntRegs:$dst),
2563 (load (HexagonCONST32 tglobaltlsaddr:$global)))]>;
2565 // This is for non-sdata.
2566 let isReMaterializable = 1, isMoveImm = 1 in
2567 def CONST32_set : LDInst2<(outs IntRegs:$dst), (ins globaladdress:$global),
2568 "$dst = CONST32(#$global)",
2569 [(set (i32 IntRegs:$dst),
2570 (HexagonCONST32 tglobaladdr:$global))]>;
2572 let isReMaterializable = 1, isMoveImm = 1 in
2573 def CONST32_set_jt : LDInst2<(outs IntRegs:$dst), (ins jumptablebase:$jt),
2574 "$dst = CONST32(#$jt)",
2575 [(set (i32 IntRegs:$dst),
2576 (HexagonCONST32 tjumptable:$jt))]>;
2578 let isReMaterializable = 1, isMoveImm = 1 in
2579 def CONST32GP_set : LDInst2<(outs IntRegs:$dst), (ins globaladdress:$global),
2580 "$dst = CONST32(#$global)",
2581 [(set (i32 IntRegs:$dst),
2582 (HexagonCONST32_GP tglobaladdr:$global))]>;
2584 let isReMaterializable = 1, isMoveImm = 1 in
2585 def CONST32_Int_Real : LDInst2<(outs IntRegs:$dst), (ins i32imm:$global),
2586 "$dst = CONST32(#$global)",
2587 [(set (i32 IntRegs:$dst), imm:$global) ]>;
2589 // Map BlockAddress lowering to CONST32_Int_Real
2590 def : Pat<(HexagonCONST32_GP tblockaddress:$addr),
2591 (CONST32_Int_Real tblockaddress:$addr)>;
2593 let isReMaterializable = 1, isMoveImm = 1 in
2594 def CONST32_Label : LDInst2<(outs IntRegs:$dst), (ins bblabel:$label),
2595 "$dst = CONST32($label)",
2596 [(set (i32 IntRegs:$dst), (HexagonCONST32 bbl:$label))]>;
2598 let isReMaterializable = 1, isMoveImm = 1 in
2599 def CONST64_Int_Real : LDInst2<(outs DoubleRegs:$dst), (ins i64imm:$global),
2600 "$dst = CONST64(#$global)",
2601 [(set (i64 DoubleRegs:$dst), imm:$global) ]>;
2603 def TFR_PdFalse : SInst<(outs PredRegs:$dst), (ins),
2604 "$dst = xor($dst, $dst)",
2605 [(set (i1 PredRegs:$dst), 0)]>;
2607 def MPY_trsext : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
2608 "$dst = mpy($src1, $src2)",
2609 [(set (i32 IntRegs:$dst),
2610 (trunc (i64 (srl (i64 (mul (i64 (sext (i32 IntRegs:$src1))),
2611 (i64 (sext (i32 IntRegs:$src2))))),
2614 // Pseudo instructions.
2615 def SDT_SPCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
2617 def SDT_SPCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
2618 SDTCisVT<1, i32> ]>;
2620 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeqEnd,
2621 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
2623 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeqStart,
2624 [SDNPHasChain, SDNPOutGlue]>;
2626 def SDT_SPCall : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
2628 def call : SDNode<"HexagonISD::CALL", SDT_SPCall,
2629 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, SDNPVariadic]>;
2631 // For tailcalls a HexagonTCRet SDNode has 3 SDNode Properties - a chain,
2632 // Optional Flag and Variable Arguments.
2633 // Its 1 Operand has pointer type.
2634 def HexagonTCRet : SDNode<"HexagonISD::TC_RETURN", SDT_SPCall,
2635 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
2637 let Defs = [R29, R30], Uses = [R31, R30, R29] in {
2638 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
2639 "Should never be emitted",
2640 [(callseq_start timm:$amt)]>;
2643 let Defs = [R29, R30, R31], Uses = [R29] in {
2644 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
2645 "Should never be emitted",
2646 [(callseq_end timm:$amt1, timm:$amt2)]>;
2649 let isCall = 1, hasSideEffects = 0,
2650 Defs = [D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10,
2651 R22, R23, R28, R31, P0, P1, P2, P3, LC0, LC1, SA0, SA1] in {
2652 def CALL : JInst<(outs), (ins calltarget:$dst),
2656 // Call subroutine from register.
2657 let isCall = 1, hasSideEffects = 0,
2658 Defs = [D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10,
2659 R22, R23, R28, R31, P0, P1, P2, P3, LC0, LC1, SA0, SA1] in {
2660 def CALLR : JRInst<(outs), (ins IntRegs:$dst),
2666 // Indirect tail-call.
2667 let isCodeGenOnly = 1, isCall = 1, isReturn = 1 in
2668 def TCRETURNR : T_JMPr;
2670 // Direct tail-calls.
2671 let isCall = 1, isReturn = 1, isBarrier = 1, isPredicable = 0,
2672 isTerminator = 1, isCodeGenOnly = 1 in {
2673 def TCRETURNtg : T_JMP<(ins calltarget:$dst)>;
2674 def TCRETURNtext : T_JMP<(ins calltarget:$dst)>;
2677 // Map call instruction.
2678 def : Pat<(call (i32 IntRegs:$dst)),
2679 (CALLR (i32 IntRegs:$dst))>, Requires<[HasV2TOnly]>;
2680 def : Pat<(call tglobaladdr:$dst),
2681 (CALL tglobaladdr:$dst)>, Requires<[HasV2TOnly]>;
2682 def : Pat<(call texternalsym:$dst),
2683 (CALL texternalsym:$dst)>, Requires<[HasV2TOnly]>;
2685 def : Pat<(HexagonTCRet tglobaladdr:$dst),
2686 (TCRETURNtg tglobaladdr:$dst)>;
2687 def : Pat<(HexagonTCRet texternalsym:$dst),
2688 (TCRETURNtext texternalsym:$dst)>;
2689 def : Pat<(HexagonTCRet (i32 IntRegs:$dst)),
2690 (TCRETURNR (i32 IntRegs:$dst))>;
2692 // Atomic load and store support
2693 // 8 bit atomic load
2694 def : Pat<(atomic_load_8 ADDRriS11_0:$src1),
2695 (i32 (LDriub ADDRriS11_0:$src1))>;
2697 def : Pat<(atomic_load_8 (add (i32 IntRegs:$src1), s11_0ImmPred:$offset)),
2698 (i32 (LDriub_indexed (i32 IntRegs:$src1), s11_0ImmPred:$offset))>;
2700 // 16 bit atomic load
2701 def : Pat<(atomic_load_16 ADDRriS11_1:$src1),
2702 (i32 (LDriuh ADDRriS11_1:$src1))>;
2704 def : Pat<(atomic_load_16 (add (i32 IntRegs:$src1), s11_1ImmPred:$offset)),
2705 (i32 (LDriuh_indexed (i32 IntRegs:$src1), s11_1ImmPred:$offset))>;
2707 def : Pat<(atomic_load_32 ADDRriS11_2:$src1),
2708 (i32 (LDriw ADDRriS11_2:$src1))>;
2710 def : Pat<(atomic_load_32 (add (i32 IntRegs:$src1), s11_2ImmPred:$offset)),
2711 (i32 (LDriw_indexed (i32 IntRegs:$src1), s11_2ImmPred:$offset))>;
2713 // 64 bit atomic load
2714 def : Pat<(atomic_load_64 ADDRriS11_3:$src1),
2715 (i64 (LDrid ADDRriS11_3:$src1))>;
2717 def : Pat<(atomic_load_64 (add (i32 IntRegs:$src1), s11_3ImmPred:$offset)),
2718 (i64 (LDrid_indexed (i32 IntRegs:$src1), s11_3ImmPred:$offset))>;
2721 def : Pat<(atomic_store_8 ADDRriS11_0:$src2, (i32 IntRegs:$src1)),
2722 (STrib ADDRriS11_0:$src2, (i32 IntRegs:$src1))>;
2724 def : Pat<(atomic_store_8 (add (i32 IntRegs:$src2), s11_0ImmPred:$offset),
2725 (i32 IntRegs:$src1)),
2726 (STrib_indexed (i32 IntRegs:$src2), s11_0ImmPred:$offset,
2727 (i32 IntRegs:$src1))>;
2730 def : Pat<(atomic_store_16 ADDRriS11_1:$src2, (i32 IntRegs:$src1)),
2731 (STrih ADDRriS11_1:$src2, (i32 IntRegs:$src1))>;
2733 def : Pat<(atomic_store_16 (i32 IntRegs:$src1),
2734 (add (i32 IntRegs:$src2), s11_1ImmPred:$offset)),
2735 (STrih_indexed (i32 IntRegs:$src2), s11_1ImmPred:$offset,
2736 (i32 IntRegs:$src1))>;
2738 def : Pat<(atomic_store_32 ADDRriS11_2:$src2, (i32 IntRegs:$src1)),
2739 (STriw ADDRriS11_2:$src2, (i32 IntRegs:$src1))>;
2741 def : Pat<(atomic_store_32 (add (i32 IntRegs:$src2), s11_2ImmPred:$offset),
2742 (i32 IntRegs:$src1)),
2743 (STriw_indexed (i32 IntRegs:$src2), s11_2ImmPred:$offset,
2744 (i32 IntRegs:$src1))>;
2749 def : Pat<(atomic_store_64 ADDRriS11_3:$src2, (i64 DoubleRegs:$src1)),
2750 (STrid ADDRriS11_3:$src2, (i64 DoubleRegs:$src1))>;
2752 def : Pat<(atomic_store_64 (add (i32 IntRegs:$src2), s11_3ImmPred:$offset),
2753 (i64 DoubleRegs:$src1)),
2754 (STrid_indexed (i32 IntRegs:$src2), s11_3ImmPred:$offset,
2755 (i64 DoubleRegs:$src1))>;
2757 // Map from r0 = and(r1, 65535) to r0 = zxth(r1)
2758 def : Pat <(and (i32 IntRegs:$src1), 65535),
2759 (A2_zxth (i32 IntRegs:$src1))>;
2761 // Map from r0 = and(r1, 255) to r0 = zxtb(r1).
2762 def : Pat <(and (i32 IntRegs:$src1), 255),
2763 (A2_zxtb (i32 IntRegs:$src1))>;
2765 // Map Add(p1, true) to p1 = not(p1).
2766 // Add(p1, false) should never be produced,
2767 // if it does, it got to be mapped to NOOP.
2768 def : Pat <(add (i1 PredRegs:$src1), -1),
2769 (C2_not (i1 PredRegs:$src1))>;
2771 // Map from p0 = pnot(p0); r0 = mux(p0, #i, #j) => r0 = mux(p0, #j, #i).
2772 def : Pat <(select (not (i1 PredRegs:$src1)), s8ImmPred:$src2, s8ImmPred:$src3),
2773 (i32 (TFR_condset_ii (i1 PredRegs:$src1), s8ImmPred:$src3,
2776 // Map from p0 = pnot(p0); r0 = select(p0, #i, r1)
2777 // => r0 = TFR_condset_ri(p0, r1, #i)
2778 def : Pat <(select (not (i1 PredRegs:$src1)), s12ImmPred:$src2,
2779 (i32 IntRegs:$src3)),
2780 (i32 (TFR_condset_ri (i1 PredRegs:$src1), (i32 IntRegs:$src3),
2781 s12ImmPred:$src2))>;
2783 // Map from p0 = pnot(p0); r0 = mux(p0, r1, #i)
2784 // => r0 = TFR_condset_ir(p0, #i, r1)
2785 def : Pat <(select (not (i1 PredRegs:$src1)), IntRegs:$src2, s12ImmPred:$src3),
2786 (i32 (TFR_condset_ir (i1 PredRegs:$src1), s12ImmPred:$src3,
2787 (i32 IntRegs:$src2)))>;
2789 // Map from p0 = pnot(p0); if (p0) jump => if (!p0) jump.
2790 def : Pat <(brcond (not (i1 PredRegs:$src1)), bb:$offset),
2791 (JMP_f (i1 PredRegs:$src1), bb:$offset)>;
2793 // Map from p2 = pnot(p2); p1 = and(p0, p2) => p1 = and(p0, !p2).
2794 def : Pat <(and (i1 PredRegs:$src1), (not (i1 PredRegs:$src2))),
2795 (i1 (C2_andn (i1 PredRegs:$src1), (i1 PredRegs:$src2)))>;
2798 let AddedComplexity = 100 in
2799 def : Pat <(i64 (zextloadi1 (HexagonCONST32 tglobaladdr:$global))),
2800 (i64 (COMBINE_rr (TFRI 0),
2801 (LDriub_indexed (CONST32_set tglobaladdr:$global), 0)))>,
2804 // Map from i1 loads to 32 bits. This assumes that the i1* is byte aligned.
2805 let AddedComplexity = 10 in
2806 def : Pat <(i32 (zextloadi1 ADDRriS11_0:$addr)),
2807 (i32 (A2_and (i32 (LDrib ADDRriS11_0:$addr)), (TFRI 0x1)))>;
2809 // Map from Rdd = sign_extend_inreg(Rss, i32) -> Rdd = SXTW(Rss.lo).
2810 def : Pat <(i64 (sext_inreg (i64 DoubleRegs:$src1), i32)),
2811 (i64 (SXTW (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_loreg))))>;
2813 // Map from Rdd = sign_extend_inreg(Rss, i16) -> Rdd = SXTW(SXTH(Rss.lo)).
2814 def : Pat <(i64 (sext_inreg (i64 DoubleRegs:$src1), i16)),
2815 (i64 (SXTW (i32 (A2_sxth (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
2816 subreg_loreg))))))>;
2818 // Map from Rdd = sign_extend_inreg(Rss, i8) -> Rdd = SXTW(SXTB(Rss.lo)).
2819 def : Pat <(i64 (sext_inreg (i64 DoubleRegs:$src1), i8)),
2820 (i64 (SXTW (i32 (A2_sxtb (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
2821 subreg_loreg))))))>;
2823 // We want to prevent emitting pnot's as much as possible.
2824 // Map brcond with an unsupported setcc to a JMP_f.
2825 def : Pat <(brcond (i1 (setne (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2827 (JMP_f (C2_cmpeq (i32 IntRegs:$src1), (i32 IntRegs:$src2)),
2830 def : Pat <(brcond (i1 (setne (i32 IntRegs:$src1), s10ImmPred:$src2)),
2832 (JMP_f (C2_cmpeqi (i32 IntRegs:$src1), s10ImmPred:$src2), bb:$offset)>;
2834 def : Pat <(brcond (i1 (setne (i1 PredRegs:$src1), (i1 -1))), bb:$offset),
2835 (JMP_f (i1 PredRegs:$src1), bb:$offset)>;
2837 def : Pat <(brcond (i1 (setne (i1 PredRegs:$src1), (i1 0))), bb:$offset),
2838 (JMP_t (i1 PredRegs:$src1), bb:$offset)>;
2840 // cmp.lt(Rs, Imm) -> !cmp.ge(Rs, Imm) -> !cmp.gt(Rs, Imm-1)
2841 def : Pat <(brcond (i1 (setlt (i32 IntRegs:$src1), s8ImmPred:$src2)),
2843 (JMP_f (C2_cmpgti (i32 IntRegs:$src1),
2844 (DEC_CONST_SIGNED s8ImmPred:$src2)), bb:$offset)>;
2846 // cmp.lt(r0, r1) -> cmp.gt(r1, r0)
2847 def : Pat <(brcond (i1 (setlt (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2849 (JMP_t (C2_cmpgt (i32 IntRegs:$src2), (i32 IntRegs:$src1)), bb:$offset)>;
2851 def : Pat <(brcond (i1 (setuge (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2853 (JMP_f (C2_cmpgtup (i64 DoubleRegs:$src2), (i64 DoubleRegs:$src1)),
2856 def : Pat <(brcond (i1 (setule (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2858 (JMP_f (C2_cmpgtu (i32 IntRegs:$src1), (i32 IntRegs:$src2)),
2861 def : Pat <(brcond (i1 (setule (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2863 (JMP_f (C2_cmpgtup (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2)),
2866 // Map from a 64-bit select to an emulated 64-bit mux.
2867 // Hexagon does not support 64-bit MUXes; so emulate with combines.
2868 def : Pat <(select (i1 PredRegs:$src1), (i64 DoubleRegs:$src2),
2869 (i64 DoubleRegs:$src3)),
2870 (i64 (COMBINE_rr (i32 (C2_mux (i1 PredRegs:$src1),
2871 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
2873 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src3),
2875 (i32 (C2_mux (i1 PredRegs:$src1),
2876 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
2878 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src3),
2879 subreg_loreg))))))>;
2881 // Map from a 1-bit select to logical ops.
2882 // From LegalizeDAG.cpp: (B1 ? B2 : B3) <=> (B1 & B2)|(!B1&B3).
2883 def : Pat <(select (i1 PredRegs:$src1), (i1 PredRegs:$src2),
2884 (i1 PredRegs:$src3)),
2885 (C2_or (C2_and (i1 PredRegs:$src1), (i1 PredRegs:$src2)),
2886 (C2_and (C2_not (i1 PredRegs:$src1)), (i1 PredRegs:$src3)))>;
2888 // Map Pd = load(addr) -> Rs = load(addr); Pd = Rs.
2889 def : Pat<(i1 (load ADDRriS11_2:$addr)),
2890 (i1 (C2_tfrrp (i32 (LDrib ADDRriS11_2:$addr))))>;
2892 // Map for truncating from 64 immediates to 32 bit immediates.
2893 def : Pat<(i32 (trunc (i64 DoubleRegs:$src))),
2894 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src), subreg_loreg))>;
2896 // Map for truncating from i64 immediates to i1 bit immediates.
2897 def : Pat<(i1 (trunc (i64 DoubleRegs:$src))),
2898 (i1 (C2_tfrrp (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
2901 // Map memb(Rs) = Rdd -> memb(Rs) = Rt.
2902 def : Pat<(truncstorei8 (i64 DoubleRegs:$src), ADDRriS11_0:$addr),
2903 (STrib ADDRriS11_0:$addr, (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
2906 // Map memh(Rs) = Rdd -> memh(Rs) = Rt.
2907 def : Pat<(truncstorei16 (i64 DoubleRegs:$src), ADDRriS11_0:$addr),
2908 (STrih ADDRriS11_0:$addr, (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
2910 // Map memw(Rs) = Rdd -> memw(Rs) = Rt
2911 def : Pat<(truncstorei32 (i64 DoubleRegs:$src), ADDRriS11_0:$addr),
2912 (STriw ADDRriS11_0:$addr, (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
2915 // Map memw(Rs) = Rdd -> memw(Rs) = Rt.
2916 def : Pat<(truncstorei32 (i64 DoubleRegs:$src), ADDRriS11_0:$addr),
2917 (STriw ADDRriS11_0:$addr, (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
2920 // Map from i1 = constant<-1>; memw(addr) = i1 -> r0 = 1; memw(addr) = r0.
2921 def : Pat<(store (i1 -1), ADDRriS11_2:$addr),
2922 (STrib ADDRriS11_2:$addr, (TFRI 1))>;
2925 // Map from i1 = constant<-1>; store i1 -> r0 = 1; store r0.
2926 def : Pat<(store (i1 -1), ADDRriS11_2:$addr),
2927 (STrib ADDRriS11_2:$addr, (TFRI 1))>;
2929 // Map from memb(Rs) = Pd -> Rt = mux(Pd, #0, #1); store Rt.
2930 def : Pat<(store (i1 PredRegs:$src1), ADDRriS11_2:$addr),
2931 (STrib ADDRriS11_2:$addr, (i32 (C2_muxii (i1 PredRegs:$src1), 1, 0)) )>;
2933 // Map Rdd = anyext(Rs) -> Rdd = sxtw(Rs).
2934 // Hexagon_TODO: We can probably use combine but that will cost 2 instructions.
2935 // Better way to do this?
2936 def : Pat<(i64 (anyext (i32 IntRegs:$src1))),
2937 (i64 (SXTW (i32 IntRegs:$src1)))>;
2939 // Map cmple -> cmpgt.
2940 // rs <= rt -> !(rs > rt).
2941 def : Pat<(i1 (setle (i32 IntRegs:$src1), s10ExtPred:$src2)),
2942 (i1 (C2_not (C2_cmpgti (i32 IntRegs:$src1), s10ExtPred:$src2)))>;
2944 // rs <= rt -> !(rs > rt).
2945 def : Pat<(i1 (setle (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2946 (i1 (C2_not (C2_cmpgt (i32 IntRegs:$src1), (i32 IntRegs:$src2))))>;
2948 // Rss <= Rtt -> !(Rss > Rtt).
2949 def : Pat<(i1 (setle (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2950 (i1 (C2_not (C2_cmpgtp (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))))>;
2952 // Map cmpne -> cmpeq.
2953 // Hexagon_TODO: We should improve on this.
2954 // rs != rt -> !(rs == rt).
2955 def : Pat <(i1 (setne (i32 IntRegs:$src1), s10ExtPred:$src2)),
2956 (i1 (C2_not(i1 (C2_cmpeqi (i32 IntRegs:$src1), s10ExtPred:$src2))))>;
2958 // Map cmpne(Rs) -> !cmpeqe(Rs).
2959 // rs != rt -> !(rs == rt).
2960 def : Pat <(i1 (setne (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2961 (i1 (C2_not (i1 (C2_cmpeq (i32 IntRegs:$src1), (i32 IntRegs:$src2)))))>;
2963 // Convert setne back to xor for hexagon since we compute w/ pred registers.
2964 def : Pat <(i1 (setne (i1 PredRegs:$src1), (i1 PredRegs:$src2))),
2965 (i1 (C2_xor (i1 PredRegs:$src1), (i1 PredRegs:$src2)))>;
2967 // Map cmpne(Rss) -> !cmpew(Rss).
2968 // rs != rt -> !(rs == rt).
2969 def : Pat <(i1 (setne (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2970 (i1 (C2_not (i1 (C2_cmpeqp (i64 DoubleRegs:$src1),
2971 (i64 DoubleRegs:$src2)))))>;
2973 // Map cmpge(Rs, Rt) -> !(cmpgt(Rs, Rt).
2974 // rs >= rt -> !(rt > rs).
2975 def : Pat <(i1 (setge (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2976 (i1 (C2_not (i1 (C2_cmpgt (i32 IntRegs:$src2), (i32 IntRegs:$src1)))))>;
2978 // cmpge(Rs, Imm) -> cmpgt(Rs, Imm-1)
2979 def : Pat <(i1 (setge (i32 IntRegs:$src1), s8ExtPred:$src2)),
2980 (i1 (C2_cmpgti (i32 IntRegs:$src1), (DEC_CONST_SIGNED s8ExtPred:$src2)))>;
2982 // Map cmpge(Rss, Rtt) -> !cmpgt(Rtt, Rss).
2983 // rss >= rtt -> !(rtt > rss).
2984 def : Pat <(i1 (setge (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2985 (i1 (C2_not (i1 (C2_cmpgtp (i64 DoubleRegs:$src2),
2986 (i64 DoubleRegs:$src1)))))>;
2988 // Map cmplt(Rs, Imm) -> !cmpge(Rs, Imm).
2989 // !cmpge(Rs, Imm) -> !cmpgt(Rs, Imm-1).
2990 // rs < rt -> !(rs >= rt).
2991 def : Pat <(i1 (setlt (i32 IntRegs:$src1), s8ExtPred:$src2)),
2992 (i1 (C2_not (C2_cmpgti (i32 IntRegs:$src1), (DEC_CONST_SIGNED s8ExtPred:$src2))))>;
2994 // Map cmplt(Rs, Rt) -> cmpgt(Rt, Rs).
2995 // rs < rt -> rt > rs.
2996 // We can let assembler map it, or we can do in the compiler itself.
2997 def : Pat <(i1 (setlt (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2998 (i1 (C2_cmpgt (i32 IntRegs:$src2), (i32 IntRegs:$src1)))>;
3000 // Map cmplt(Rss, Rtt) -> cmpgt(Rtt, Rss).
3001 // rss < rtt -> (rtt > rss).
3002 def : Pat <(i1 (setlt (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
3003 (i1 (C2_cmpgtp (i64 DoubleRegs:$src2), (i64 DoubleRegs:$src1)))>;
3005 // Map from cmpltu(Rs, Rd) -> cmpgtu(Rd, Rs)
3006 // rs < rt -> rt > rs.
3007 // We can let assembler map it, or we can do in the compiler itself.
3008 def : Pat <(i1 (setult (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
3009 (i1 (C2_cmpgtu (i32 IntRegs:$src2), (i32 IntRegs:$src1)))>;
3011 // Map from cmpltu(Rss, Rdd) -> cmpgtu(Rdd, Rss).
3012 // rs < rt -> rt > rs.
3013 def : Pat <(i1 (setult (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
3014 (i1 (C2_cmpgtup (i64 DoubleRegs:$src2), (i64 DoubleRegs:$src1)))>;
3016 // Generate cmpgeu(Rs, #0) -> cmpeq(Rs, Rs)
3017 def : Pat <(i1 (setuge (i32 IntRegs:$src1), 0)),
3018 (i1 (C2_cmpeq (i32 IntRegs:$src1), (i32 IntRegs:$src1)))>;
3020 // Generate cmpgeu(Rs, #u8) -> cmpgtu(Rs, #u8 -1)
3021 def : Pat <(i1 (setuge (i32 IntRegs:$src1), u8ExtPred:$src2)),
3022 (i1 (C2_cmpgtui (i32 IntRegs:$src1), (DEC_CONST_UNSIGNED u8ExtPred:$src2)))>;
3024 // Generate cmpgtu(Rs, #u9)
3025 def : Pat <(i1 (setugt (i32 IntRegs:$src1), u9ExtPred:$src2)),
3026 (i1 (C2_cmpgtui (i32 IntRegs:$src1), u9ExtPred:$src2))>;
3028 // Map from Rs >= Rt -> !(Rt > Rs).
3029 // rs >= rt -> !(rt > rs).
3030 def : Pat <(i1 (setuge (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
3031 (i1 (C2_not (C2_cmpgtu (i32 IntRegs:$src2), (i32 IntRegs:$src1))))>;
3033 // Map from Rs >= Rt -> !(Rt > Rs).
3034 // rs >= rt -> !(rt > rs).
3035 def : Pat <(i1 (setuge (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
3036 (i1 (C2_not (C2_cmpgtup (i64 DoubleRegs:$src2), (i64 DoubleRegs:$src1))))>;
3038 // Map from cmpleu(Rs, Rt) -> !cmpgtu(Rs, Rt).
3039 // Map from (Rs <= Rt) -> !(Rs > Rt).
3040 def : Pat <(i1 (setule (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
3041 (i1 (C2_not (C2_cmpgtu (i32 IntRegs:$src1), (i32 IntRegs:$src2))))>;
3043 // Map from cmpleu(Rss, Rtt) -> !cmpgtu(Rss, Rtt-1).
3044 // Map from (Rs <= Rt) -> !(Rs > Rt).
3045 def : Pat <(i1 (setule (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
3046 (i1 (C2_not (C2_cmpgtup (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))))>;
3050 def : Pat <(i32 (sext (i1 PredRegs:$src1))),
3051 (i32 (C2_muxii (i1 PredRegs:$src1), -1, 0))>;
3054 def : Pat <(i64 (sext (i1 PredRegs:$src1))),
3055 (i64 (COMBINE_rr (TFRI -1), (C2_muxii (i1 PredRegs:$src1), -1, 0)))>;
3057 // Convert sign-extended load back to load and sign extend.
3059 def: Pat <(i64 (sextloadi8 ADDRriS11_0:$src1)),
3060 (i64 (SXTW (LDrib ADDRriS11_0:$src1)))>;
3062 // Convert any-extended load back to load and sign extend.
3064 def: Pat <(i64 (extloadi8 ADDRriS11_0:$src1)),
3065 (i64 (SXTW (LDrib ADDRriS11_0:$src1)))>;
3067 // Convert sign-extended load back to load and sign extend.
3069 def: Pat <(i64 (sextloadi16 ADDRriS11_1:$src1)),
3070 (i64 (SXTW (LDrih ADDRriS11_1:$src1)))>;
3072 // Convert sign-extended load back to load and sign extend.
3074 def: Pat <(i64 (sextloadi32 ADDRriS11_2:$src1)),
3075 (i64 (SXTW (LDriw ADDRriS11_2:$src1)))>;
3080 def : Pat <(i32 (zext (i1 PredRegs:$src1))),
3081 (i32 (C2_muxii (i1 PredRegs:$src1), 1, 0))>;
3084 def : Pat <(i64 (zext (i1 PredRegs:$src1))),
3085 (i64 (COMBINE_rr (TFRI 0), (C2_muxii (i1 PredRegs:$src1), 1, 0)))>,
3089 def : Pat <(i64 (zext (i32 IntRegs:$src1))),
3090 (i64 (COMBINE_rr (TFRI 0), (i32 IntRegs:$src1)))>,
3094 def: Pat <(i64 (zextloadi8 ADDRriS11_0:$src1)),
3095 (i64 (COMBINE_rr (TFRI 0), (LDriub ADDRriS11_0:$src1)))>,
3098 let AddedComplexity = 20 in
3099 def: Pat <(i64 (zextloadi8 (add (i32 IntRegs:$src1),
3100 s11_0ExtPred:$offset))),
3101 (i64 (COMBINE_rr (TFRI 0), (LDriub_indexed IntRegs:$src1,
3102 s11_0ExtPred:$offset)))>,
3106 def: Pat <(i64 (zextloadi1 ADDRriS11_0:$src1)),
3107 (i64 (COMBINE_rr (TFRI 0), (LDriub ADDRriS11_0:$src1)))>,
3110 let AddedComplexity = 20 in
3111 def: Pat <(i64 (zextloadi1 (add (i32 IntRegs:$src1),
3112 s11_0ExtPred:$offset))),
3113 (i64 (COMBINE_rr (TFRI 0), (LDriub_indexed IntRegs:$src1,
3114 s11_0ExtPred:$offset)))>,
3118 def: Pat <(i64 (zextloadi16 ADDRriS11_1:$src1)),
3119 (i64 (COMBINE_rr (TFRI 0), (LDriuh ADDRriS11_1:$src1)))>,
3122 let AddedComplexity = 20 in
3123 def: Pat <(i64 (zextloadi16 (add (i32 IntRegs:$src1),
3124 s11_1ExtPred:$offset))),
3125 (i64 (COMBINE_rr (TFRI 0), (LDriuh_indexed IntRegs:$src1,
3126 s11_1ExtPred:$offset)))>,
3130 def: Pat <(i64 (zextloadi32 ADDRriS11_2:$src1)),
3131 (i64 (COMBINE_rr (TFRI 0), (LDriw ADDRriS11_2:$src1)))>,
3134 let AddedComplexity = 100 in
3135 def: Pat <(i64 (zextloadi32 (i32 (add IntRegs:$src1, s11_2ExtPred:$offset)))),
3136 (i64 (COMBINE_rr (TFRI 0), (LDriw_indexed IntRegs:$src1,
3137 s11_2ExtPred:$offset)))>,
3140 let AddedComplexity = 10 in
3141 def: Pat <(i32 (zextloadi1 ADDRriS11_0:$src1)),
3142 (i32 (LDriw ADDRriS11_0:$src1))>;
3144 // Map from Rs = Pd to Pd = mux(Pd, #1, #0)
3145 def : Pat <(i32 (zext (i1 PredRegs:$src1))),
3146 (i32 (C2_muxii (i1 PredRegs:$src1), 1, 0))>;
3148 // Map from Rs = Pd to Pd = mux(Pd, #1, #0)
3149 def : Pat <(i32 (anyext (i1 PredRegs:$src1))),
3150 (i32 (C2_muxii (i1 PredRegs:$src1), 1, 0))>;
3152 // Map from Rss = Pd to Rdd = sxtw (mux(Pd, #1, #0))
3153 def : Pat <(i64 (anyext (i1 PredRegs:$src1))),
3154 (i64 (SXTW (i32 (C2_muxii (i1 PredRegs:$src1), 1, 0))))>;
3157 let AddedComplexity = 100 in
3158 def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh),
3160 (i64 (zextloadi32 (i32 (add IntRegs:$src2,
3161 s11_2ExtPred:$offset2)))))),
3162 (i64 (COMBINE_rr (EXTRACT_SUBREG (i64 DoubleRegs:$srcHigh), subreg_loreg),
3163 (LDriw_indexed IntRegs:$src2,
3164 s11_2ExtPred:$offset2)))>;
3166 def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh),
3168 (i64 (zextloadi32 ADDRriS11_2:$srcLow)))),
3169 (i64 (COMBINE_rr (EXTRACT_SUBREG (i64 DoubleRegs:$srcHigh), subreg_loreg),
3170 (LDriw ADDRriS11_2:$srcLow)))>;
3172 def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh),
3174 (i64 (zext (i32 IntRegs:$srcLow))))),
3175 (i64 (COMBINE_rr (EXTRACT_SUBREG (i64 DoubleRegs:$srcHigh), subreg_loreg),
3178 let AddedComplexity = 100 in
3179 def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh),
3181 (i64 (zextloadi32 (i32 (add IntRegs:$src2,
3182 s11_2ExtPred:$offset2)))))),
3183 (i64 (COMBINE_rr (EXTRACT_SUBREG (i64 DoubleRegs:$srcHigh), subreg_loreg),
3184 (LDriw_indexed IntRegs:$src2,
3185 s11_2ExtPred:$offset2)))>;
3187 def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh),
3189 (i64 (zextloadi32 ADDRriS11_2:$srcLow)))),
3190 (i64 (COMBINE_rr (EXTRACT_SUBREG (i64 DoubleRegs:$srcHigh), subreg_loreg),
3191 (LDriw ADDRriS11_2:$srcLow)))>;
3193 def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh),
3195 (i64 (zext (i32 IntRegs:$srcLow))))),
3196 (i64 (COMBINE_rr (EXTRACT_SUBREG (i64 DoubleRegs:$srcHigh), subreg_loreg),
3199 // Any extended 64-bit load.
3200 // anyext i32 -> i64
3201 def: Pat <(i64 (extloadi32 ADDRriS11_2:$src1)),
3202 (i64 (COMBINE_rr (TFRI 0), (LDriw ADDRriS11_2:$src1)))>,
3205 // When there is an offset we should prefer the pattern below over the pattern above.
3206 // The complexity of the above is 13 (gleaned from HexagonGenDAGIsel.inc)
3207 // So this complexity below is comfortably higher to allow for choosing the below.
3208 // If this is not done then we generate addresses such as
3209 // ********************************************
3210 // r1 = add (r0, #4)
3211 // r1 = memw(r1 + #0)
3213 // r1 = memw(r0 + #4)
3214 // ********************************************
3215 let AddedComplexity = 100 in
3216 def: Pat <(i64 (extloadi32 (i32 (add IntRegs:$src1, s11_2ExtPred:$offset)))),
3217 (i64 (COMBINE_rr (TFRI 0), (LDriw_indexed IntRegs:$src1,
3218 s11_2ExtPred:$offset)))>,
3221 // anyext i16 -> i64.
3222 def: Pat <(i64 (extloadi16 ADDRriS11_2:$src1)),
3223 (i64 (COMBINE_rr (TFRI 0), (LDrih ADDRriS11_2:$src1)))>,
3226 let AddedComplexity = 20 in
3227 def: Pat <(i64 (extloadi16 (add (i32 IntRegs:$src1),
3228 s11_1ExtPred:$offset))),
3229 (i64 (COMBINE_rr (TFRI 0), (LDrih_indexed IntRegs:$src1,
3230 s11_1ExtPred:$offset)))>,
3233 // Map from Rdd = zxtw(Rs) -> Rdd = combine(0, Rs).
3234 def : Pat<(i64 (zext (i32 IntRegs:$src1))),
3235 (i64 (COMBINE_rr (TFRI 0), (i32 IntRegs:$src1)))>,
3238 // Multiply 64-bit unsigned and use upper result.
3239 def : Pat <(mulhu (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2)),
3254 (COMBINE_rr (TFRI 0),
3260 (MPYU64 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
3262 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
3263 subreg_loreg)))), 32)),
3265 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg)),
3266 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_loreg)))),
3267 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_loreg)),
3268 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg)))),
3269 32)), subreg_loreg)))),
3270 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg)),
3271 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg))))>;
3273 // Multiply 64-bit signed and use upper result.
3274 def : Pat <(mulhs (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2)),
3278 (COMBINE_rr (TFRI 0),
3288 (COMBINE_rr (TFRI 0),
3294 (MPYU64 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
3296 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
3297 subreg_loreg)))), 32)),
3299 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg)),
3300 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_loreg)))),
3301 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_loreg)),
3302 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg)))),
3303 32)), subreg_loreg)))),
3304 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg)),
3305 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg))))>;
3307 // Hexagon specific ISD nodes.
3308 //def SDTHexagonADJDYNALLOC : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>]>;
3309 def SDTHexagonADJDYNALLOC : SDTypeProfile<1, 2,
3310 [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
3311 def Hexagon_ADJDYNALLOC : SDNode<"HexagonISD::ADJDYNALLOC",
3312 SDTHexagonADJDYNALLOC>;
3313 // Needed to tag these instructions for stack layout.
3314 let usesCustomInserter = 1 in
3315 def ADJDYNALLOC : ALU32_ri<(outs IntRegs:$dst), (ins IntRegs:$src1,
3317 "$dst = add($src1, #$src2)",
3318 [(set (i32 IntRegs:$dst),
3319 (Hexagon_ADJDYNALLOC (i32 IntRegs:$src1),
3320 s16ImmPred:$src2))]>;
3322 def SDTHexagonARGEXTEND : SDTypeProfile<1, 1, [SDTCisVT<0, i32>]>;
3323 def Hexagon_ARGEXTEND : SDNode<"HexagonISD::ARGEXTEND", SDTHexagonARGEXTEND>;
3324 def ARGEXTEND : ALU32_rr <(outs IntRegs:$dst), (ins IntRegs:$src1),
3326 [(set (i32 IntRegs:$dst),
3327 (Hexagon_ARGEXTEND (i32 IntRegs:$src1)))]>;
3329 let AddedComplexity = 100 in
3330 def : Pat<(i32 (sext_inreg (Hexagon_ARGEXTEND (i32 IntRegs:$src1)), i16)),
3331 (COPY (i32 IntRegs:$src1))>;
3333 def HexagonWrapperJT: SDNode<"HexagonISD::WrapperJT", SDTIntUnaryOp>;
3335 def : Pat<(HexagonWrapperJT tjumptable:$dst),
3336 (i32 (CONST32_set_jt tjumptable:$dst))>;
3340 // Multi-class for logical operators :
3341 // Shift by immediate/register and accumulate/logical
3342 multiclass xtype_imm<string OpcStr, SDNode OpNode1, SDNode OpNode2> {
3343 def _ri : SInst_acc<(outs IntRegs:$dst),
3344 (ins IntRegs:$src1, IntRegs:$src2, u5Imm:$src3),
3345 !strconcat("$dst ", !strconcat(OpcStr, "($src2, #$src3)")),
3346 [(set (i32 IntRegs:$dst),
3347 (OpNode2 (i32 IntRegs:$src1),
3348 (OpNode1 (i32 IntRegs:$src2),
3349 u5ImmPred:$src3)))],
3352 def d_ri : SInst_acc<(outs DoubleRegs:$dst),
3353 (ins DoubleRegs:$src1, DoubleRegs:$src2, u6Imm:$src3),
3354 !strconcat("$dst ", !strconcat(OpcStr, "($src2, #$src3)")),
3355 [(set (i64 DoubleRegs:$dst), (OpNode2 (i64 DoubleRegs:$src1),
3356 (OpNode1 (i64 DoubleRegs:$src2), u6ImmPred:$src3)))],
3360 // Multi-class for logical operators :
3361 // Shift by register and accumulate/logical (32/64 bits)
3362 multiclass xtype_reg<string OpcStr, SDNode OpNode1, SDNode OpNode2> {
3363 def _rr : SInst_acc<(outs IntRegs:$dst),
3364 (ins IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
3365 !strconcat("$dst ", !strconcat(OpcStr, "($src2, $src3)")),
3366 [(set (i32 IntRegs:$dst),
3367 (OpNode2 (i32 IntRegs:$src1),
3368 (OpNode1 (i32 IntRegs:$src2),
3369 (i32 IntRegs:$src3))))],
3372 def d_rr : SInst_acc<(outs DoubleRegs:$dst),
3373 (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
3374 !strconcat("$dst ", !strconcat(OpcStr, "($src2, $src3)")),
3375 [(set (i64 DoubleRegs:$dst),
3376 (OpNode2 (i64 DoubleRegs:$src1),
3377 (OpNode1 (i64 DoubleRegs:$src2),
3378 (i32 IntRegs:$src3))))],
3383 multiclass basic_xtype_imm<string OpcStr, SDNode OpNode> {
3384 let AddedComplexity = 100 in
3385 defm _ADD : xtype_imm< !strconcat("+= ", OpcStr), OpNode, add>;
3386 defm _SUB : xtype_imm< !strconcat("-= ", OpcStr), OpNode, sub>;
3387 defm _AND : xtype_imm< !strconcat("&= ", OpcStr), OpNode, and>;
3388 defm _OR : xtype_imm< !strconcat("|= ", OpcStr), OpNode, or>;
3391 multiclass basic_xtype_reg<string OpcStr, SDNode OpNode> {
3392 let AddedComplexity = 100 in
3393 defm _ADD : xtype_reg< !strconcat("+= ", OpcStr), OpNode, add>;
3394 defm _SUB : xtype_reg< !strconcat("-= ", OpcStr), OpNode, sub>;
3395 defm _AND : xtype_reg< !strconcat("&= ", OpcStr), OpNode, and>;
3396 defm _OR : xtype_reg< !strconcat("|= ", OpcStr), OpNode, or>;
3399 multiclass xtype_xor_imm<string OpcStr, SDNode OpNode> {
3400 let AddedComplexity = 100 in
3401 defm _XOR : xtype_imm< !strconcat("^= ", OpcStr), OpNode, xor>;
3404 defm ASL : basic_xtype_imm<"asl", shl>, basic_xtype_reg<"asl", shl>,
3405 xtype_xor_imm<"asl", shl>;
3407 defm LSR : basic_xtype_imm<"lsr", srl>, basic_xtype_reg<"lsr", srl>,
3408 xtype_xor_imm<"lsr", srl>;
3410 defm ASR : basic_xtype_imm<"asr", sra>, basic_xtype_reg<"asr", sra>;
3411 defm LSL : basic_xtype_reg<"lsl", shl>;
3413 // Change the sign of the immediate for Rd=-mpyi(Rs,#u8)
3414 def : Pat <(mul (i32 IntRegs:$src1), (ineg n8ImmPred:$src2)),
3415 (i32 (MPYI_rin (i32 IntRegs:$src1), u8ImmPred:$src2))>;
3417 //===----------------------------------------------------------------------===//
3418 // V3 Instructions +
3419 //===----------------------------------------------------------------------===//
3421 include "HexagonInstrInfoV3.td"
3423 //===----------------------------------------------------------------------===//
3424 // V3 Instructions -
3425 //===----------------------------------------------------------------------===//
3427 //===----------------------------------------------------------------------===//
3428 // V4 Instructions +
3429 //===----------------------------------------------------------------------===//
3431 include "HexagonInstrInfoV4.td"
3433 //===----------------------------------------------------------------------===//
3434 // V4 Instructions -
3435 //===----------------------------------------------------------------------===//
3437 //===----------------------------------------------------------------------===//
3438 // V5 Instructions +
3439 //===----------------------------------------------------------------------===//
3441 include "HexagonInstrInfoV5.td"
3443 //===----------------------------------------------------------------------===//
3444 // V5 Instructions -
3445 //===----------------------------------------------------------------------===//