1 //==- HexagonInstrInfo.td - Target Description for Hexagon -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Hexagon instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 include "HexagonInstrFormats.td"
15 include "HexagonOperands.td"
17 //===----------------------------------------------------------------------===//
19 // Multi-class for logical operators.
20 multiclass ALU32_rr_ri<string OpcStr, SDNode OpNode> {
21 def rr : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
22 !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
23 [(set (i32 IntRegs:$dst), (OpNode (i32 IntRegs:$b),
25 def ri : ALU32_ri<(outs IntRegs:$dst), (ins s10Imm:$b, IntRegs:$c),
26 !strconcat("$dst = ", !strconcat(OpcStr, "(#$b, $c)")),
27 [(set (i32 IntRegs:$dst), (OpNode s10Imm:$b,
31 // Multi-class for compare ops.
32 let isCompare = 1 in {
33 multiclass CMP64_rr<string OpcStr, PatFrag OpNode> {
34 def rr : ALU64_rr<(outs PredRegs:$dst), (ins DoubleRegs:$b, DoubleRegs:$c),
35 !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
36 [(set (i1 PredRegs:$dst),
37 (OpNode (i64 DoubleRegs:$b), (i64 DoubleRegs:$c)))]>;
40 multiclass CMP32_rr_ri_s10<string OpcStr, string CextOp, PatFrag OpNode> {
41 let CextOpcode = CextOp in {
42 let InputType = "reg" in
43 def rr : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
44 !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
45 [(set (i1 PredRegs:$dst),
46 (OpNode (i32 IntRegs:$b), (i32 IntRegs:$c)))]>;
48 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1,
49 opExtentBits = 10, InputType = "imm" in
50 def ri : ALU32_ri<(outs PredRegs:$dst), (ins IntRegs:$b, s10Ext:$c),
51 !strconcat("$dst = ", !strconcat(OpcStr, "($b, #$c)")),
52 [(set (i1 PredRegs:$dst),
53 (OpNode (i32 IntRegs:$b), s10ExtPred:$c))]>;
57 multiclass CMP32_rr_ri_u9<string OpcStr, string CextOp, PatFrag OpNode> {
58 let CextOpcode = CextOp in {
59 let InputType = "reg" in
60 def rr : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
61 !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
62 [(set (i1 PredRegs:$dst),
63 (OpNode (i32 IntRegs:$b), (i32 IntRegs:$c)))]>;
65 let isExtendable = 1, opExtendable = 2, isExtentSigned = 0,
66 opExtentBits = 9, InputType = "imm" in
67 def ri : ALU32_ri<(outs PredRegs:$dst), (ins IntRegs:$b, u9Ext:$c),
68 !strconcat("$dst = ", !strconcat(OpcStr, "($b, #$c)")),
69 [(set (i1 PredRegs:$dst),
70 (OpNode (i32 IntRegs:$b), u9ExtPred:$c))]>;
74 multiclass CMP32_ri_s8<string OpcStr, PatFrag OpNode> {
75 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 8 in
76 def ri : ALU32_ri<(outs PredRegs:$dst), (ins IntRegs:$b, s8Ext:$c),
77 !strconcat("$dst = ", !strconcat(OpcStr, "($b, #$c)")),
78 [(set (i1 PredRegs:$dst), (OpNode (i32 IntRegs:$b),
83 //===----------------------------------------------------------------------===//
84 // ALU32/ALU (Instructions with register-register form)
85 //===----------------------------------------------------------------------===//
86 def SDTHexagonI64I32I32 : SDTypeProfile<1, 2,
87 [SDTCisVT<0, i64>, SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
89 def HexagonWrapperCombineII :
90 SDNode<"HexagonISD::WrapperCombineII", SDTHexagonI64I32I32>;
92 def HexagonWrapperCombineRR :
93 SDNode<"HexagonISD::WrapperCombineRR", SDTHexagonI64I32I32>;
95 multiclass ALU32_Pbase<string mnemonic, RegisterClass RC, bit isNot,
97 let isPredicatedNew = isPredNew in
98 def NAME : ALU32_rr<(outs RC:$dst),
99 (ins PredRegs:$src1, IntRegs:$src2, IntRegs: $src3),
100 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew,".new) $dst = ",
101 ") $dst = ")#mnemonic#"($src2, $src3)",
105 multiclass ALU32_Pred<string mnemonic, RegisterClass RC, bit PredNot> {
106 let isPredicatedFalse = PredNot in {
107 defm _c#NAME : ALU32_Pbase<mnemonic, RC, PredNot, 0>;
109 defm _cdn#NAME : ALU32_Pbase<mnemonic, RC, PredNot, 1>;
113 let InputType = "reg" in
114 multiclass ALU32_base<string mnemonic, string CextOp, SDNode OpNode> {
115 let CextOpcode = CextOp, BaseOpcode = CextOp#_rr in {
116 let isPredicable = 1 in
117 def NAME : ALU32_rr<(outs IntRegs:$dst),
118 (ins IntRegs:$src1, IntRegs:$src2),
119 "$dst = "#mnemonic#"($src1, $src2)",
120 [(set (i32 IntRegs:$dst), (OpNode (i32 IntRegs:$src1),
121 (i32 IntRegs:$src2)))]>;
123 let neverHasSideEffects = 1, isPredicated = 1 in {
124 defm Pt : ALU32_Pred<mnemonic, IntRegs, 0>;
125 defm NotPt : ALU32_Pred<mnemonic, IntRegs, 1>;
130 let isCommutable = 1 in {
131 defm ADD_rr : ALU32_base<"add", "ADD", add>, ImmRegRel, PredNewRel;
132 defm AND_rr : ALU32_base<"and", "AND", and>, ImmRegRel, PredNewRel;
133 defm XOR_rr : ALU32_base<"xor", "XOR", xor>, ImmRegRel, PredNewRel;
134 defm OR_rr : ALU32_base<"or", "OR", or>, ImmRegRel, PredNewRel;
137 defm SUB_rr : ALU32_base<"sub", "SUB", sub>, ImmRegRel, PredNewRel;
139 // Combines the two integer registers SRC1 and SRC2 into a double register.
140 let isPredicable = 1 in
141 class T_Combine : ALU32_rr<(outs DoubleRegs:$dst),
142 (ins IntRegs:$src1, IntRegs:$src2),
143 "$dst = combine($src1, $src2)",
144 [(set (i64 DoubleRegs:$dst),
145 (i64 (HexagonWrapperCombineRR (i32 IntRegs:$src1),
146 (i32 IntRegs:$src2))))]>;
148 multiclass Combine_base {
149 let BaseOpcode = "combine" in {
150 def NAME : T_Combine;
151 let neverHasSideEffects = 1, isPredicated = 1 in {
152 defm Pt : ALU32_Pred<"combine", DoubleRegs, 0>;
153 defm NotPt : ALU32_Pred<"combine", DoubleRegs, 1>;
158 defm COMBINE_rr : Combine_base, PredNewRel;
160 // Combines the two immediates SRC1 and SRC2 into a double register.
161 class COMBINE_imm<Operand imm1, Operand imm2, PatLeaf pat1, PatLeaf pat2> :
162 ALU32_ii<(outs DoubleRegs:$dst), (ins imm1:$src1, imm2:$src2),
163 "$dst = combine(#$src1, #$src2)",
164 [(set (i64 DoubleRegs:$dst),
165 (i64 (HexagonWrapperCombineII (i32 pat1:$src1), (i32 pat2:$src2))))]>;
167 let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 8 in
168 def COMBINE_Ii : COMBINE_imm<s8Ext, s8Imm, s8ExtPred, s8ImmPred>;
170 //===----------------------------------------------------------------------===//
171 // ALU32/ALU (ADD with register-immediate form)
172 //===----------------------------------------------------------------------===//
173 multiclass ALU32ri_Pbase<string mnemonic, bit isNot, bit isPredNew> {
174 let isPredicatedNew = isPredNew in
175 def NAME : ALU32_ri<(outs IntRegs:$dst),
176 (ins PredRegs:$src1, IntRegs:$src2, s8Ext: $src3),
177 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew,".new) $dst = ",
178 ") $dst = ")#mnemonic#"($src2, #$src3)",
182 multiclass ALU32ri_Pred<string mnemonic, bit PredNot> {
183 let isPredicatedFalse = PredNot in {
184 defm _c#NAME : ALU32ri_Pbase<mnemonic, PredNot, 0>;
186 defm _cdn#NAME : ALU32ri_Pbase<mnemonic, PredNot, 1>;
190 let isExtendable = 1, InputType = "imm" in
191 multiclass ALU32ri_base<string mnemonic, string CextOp, SDNode OpNode> {
192 let CextOpcode = CextOp, BaseOpcode = CextOp#_ri in {
193 let opExtendable = 2, isExtentSigned = 1, opExtentBits = 16,
195 def NAME : ALU32_ri<(outs IntRegs:$dst),
196 (ins IntRegs:$src1, s16Ext:$src2),
197 "$dst = "#mnemonic#"($src1, #$src2)",
198 [(set (i32 IntRegs:$dst), (OpNode (i32 IntRegs:$src1),
199 (s16ExtPred:$src2)))]>;
201 let opExtendable = 3, isExtentSigned = 1, opExtentBits = 8,
202 neverHasSideEffects = 1, isPredicated = 1 in {
203 defm Pt : ALU32ri_Pred<mnemonic, 0>;
204 defm NotPt : ALU32ri_Pred<mnemonic, 1>;
209 defm ADD_ri : ALU32ri_base<"add", "ADD", add>, ImmRegRel, PredNewRel;
211 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 10,
212 CextOpcode = "OR", InputType = "imm" in
213 def OR_ri : ALU32_ri<(outs IntRegs:$dst),
214 (ins IntRegs:$src1, s10Ext:$src2),
215 "$dst = or($src1, #$src2)",
216 [(set (i32 IntRegs:$dst), (or (i32 IntRegs:$src1),
217 s10ExtPred:$src2))]>, ImmRegRel;
219 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 10,
220 InputType = "imm", CextOpcode = "AND" in
221 def AND_ri : ALU32_ri<(outs IntRegs:$dst),
222 (ins IntRegs:$src1, s10Ext:$src2),
223 "$dst = and($src1, #$src2)",
224 [(set (i32 IntRegs:$dst), (and (i32 IntRegs:$src1),
225 s10ExtPred:$src2))]>, ImmRegRel;
228 let neverHasSideEffects = 1 in
229 def NOP : ALU32_rr<(outs), (ins),
233 // Rd32=sub(#s10,Rs32)
234 let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 10,
235 CextOpcode = "SUB", InputType = "imm" in
236 def SUB_ri : ALU32_ri<(outs IntRegs:$dst),
237 (ins s10Ext:$src1, IntRegs:$src2),
238 "$dst = sub(#$src1, $src2)",
239 [(set IntRegs:$dst, (sub s10ExtPred:$src1, IntRegs:$src2))]>,
242 // Rd = not(Rs) gets mapped to Rd=sub(#-1, Rs).
243 def : Pat<(not (i32 IntRegs:$src1)),
244 (SUB_ri -1, (i32 IntRegs:$src1))>;
246 // Rd = neg(Rs) gets mapped to Rd=sub(#0, Rs).
247 // Pattern definition for 'neg' was not necessary.
249 multiclass TFR_Pred<bit PredNot> {
250 let isPredicatedFalse = PredNot in {
251 def _c#NAME : ALU32_rr<(outs IntRegs:$dst),
252 (ins PredRegs:$src1, IntRegs:$src2),
253 !if(PredNot, "if (!$src1", "if ($src1")#") $dst = $src2",
256 let isPredicatedNew = 1 in
257 def _cdn#NAME : ALU32_rr<(outs IntRegs:$dst),
258 (ins PredRegs:$src1, IntRegs:$src2),
259 !if(PredNot, "if (!$src1", "if ($src1")#".new) $dst = $src2",
264 let InputType = "reg", neverHasSideEffects = 1 in
265 multiclass TFR_base<string CextOp> {
266 let CextOpcode = CextOp, BaseOpcode = CextOp in {
267 let isPredicable = 1 in
268 def NAME : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
272 let isPredicated = 1 in {
273 defm Pt : TFR_Pred<0>;
274 defm NotPt : TFR_Pred<1>;
279 class T_TFR64_Pred<bit PredNot, bit isPredNew>
280 : ALU32_rr<(outs DoubleRegs:$dst),
281 (ins PredRegs:$src1, DoubleRegs:$src2),
282 !if(PredNot, "if (!$src1", "if ($src1")#
283 !if(isPredNew, ".new) ", ") ")#"$dst = $src2", []>
290 let Inst{27-24} = 0b1101;
291 let Inst{13} = isPredNew;
292 let Inst{7} = PredNot;
294 let Inst{6-5} = src1;
295 let Inst{20-17} = src2{4-1};
297 let Inst{12-9} = src2{4-1};
301 multiclass TFR64_Pred<bit PredNot> {
302 let isPredicatedFalse = PredNot in {
303 def _c#NAME : T_TFR64_Pred<PredNot, 0>;
305 let isPredicatedNew = 1 in
306 def _cdn#NAME : T_TFR64_Pred<PredNot, 1>; // Predicate new
310 let neverHasSideEffects = 1 in
311 multiclass TFR64_base<string BaseName> {
312 let BaseOpcode = BaseName in {
313 let isPredicable = 1 in
314 def NAME : ALU32Inst <(outs DoubleRegs:$dst),
315 (ins DoubleRegs:$src1),
321 let Inst{27-23} = 0b01010;
323 let Inst{20-17} = src1{4-1};
325 let Inst{12-9} = src1{4-1};
329 let isPredicated = 1 in {
330 defm Pt : TFR64_Pred<0>;
331 defm NotPt : TFR64_Pred<1>;
336 multiclass TFRI_Pred<bit PredNot> {
337 let isMoveImm = 1, isPredicatedFalse = PredNot in {
338 def _c#NAME : ALU32_ri<(outs IntRegs:$dst),
339 (ins PredRegs:$src1, s12Ext:$src2),
340 !if(PredNot, "if (!$src1", "if ($src1")#") $dst = #$src2",
344 let isPredicatedNew = 1 in
345 def _cdn#NAME : ALU32_rr<(outs IntRegs:$dst),
346 (ins PredRegs:$src1, s12Ext:$src2),
347 !if(PredNot, "if (!$src1", "if ($src1")#".new) $dst = #$src2",
352 let InputType = "imm", isExtendable = 1, isExtentSigned = 1 in
353 multiclass TFRI_base<string CextOp> {
354 let CextOpcode = CextOp, BaseOpcode = CextOp#I in {
355 let isAsCheapAsAMove = 1 , opExtendable = 1, opExtentBits = 16,
356 isMoveImm = 1, isPredicable = 1, isReMaterializable = 1 in
357 def NAME : ALU32_ri<(outs IntRegs:$dst), (ins s16Ext:$src1),
359 [(set (i32 IntRegs:$dst), s16ExtPred:$src1)]>;
361 let opExtendable = 2, opExtentBits = 12, neverHasSideEffects = 1,
362 isPredicated = 1 in {
363 defm Pt : TFRI_Pred<0>;
364 defm NotPt : TFRI_Pred<1>;
369 defm TFRI : TFRI_base<"TFR">, ImmRegRel, PredNewRel;
370 defm TFR : TFR_base<"TFR">, ImmRegRel, PredNewRel;
371 defm TFR64 : TFR64_base<"TFR64">, PredNewRel;
373 // Transfer control register.
374 let neverHasSideEffects = 1 in
375 def TFCR : CRInst<(outs CRRegs:$dst), (ins IntRegs:$src1),
378 //===----------------------------------------------------------------------===//
380 //===----------------------------------------------------------------------===//
383 //===----------------------------------------------------------------------===//
385 //===----------------------------------------------------------------------===//
388 def VMUX_prr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins PredRegs:$src1,
391 "$dst = vmux($src1, $src2, $src3)",
394 let CextOpcode = "MUX", InputType = "reg" in
395 def MUX_rr : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1,
396 IntRegs:$src2, IntRegs:$src3),
397 "$dst = mux($src1, $src2, $src3)",
398 [(set (i32 IntRegs:$dst),
399 (i32 (select (i1 PredRegs:$src1), (i32 IntRegs:$src2),
400 (i32 IntRegs:$src3))))]>, ImmRegRel;
402 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 8,
403 CextOpcode = "MUX", InputType = "imm" in
404 def MUX_ir : ALU32_ir<(outs IntRegs:$dst), (ins PredRegs:$src1, s8Ext:$src2,
406 "$dst = mux($src1, #$src2, $src3)",
407 [(set (i32 IntRegs:$dst),
408 (i32 (select (i1 PredRegs:$src1), s8ExtPred:$src2,
409 (i32 IntRegs:$src3))))]>, ImmRegRel;
411 let isExtendable = 1, opExtendable = 3, isExtentSigned = 1, opExtentBits = 8,
412 CextOpcode = "MUX", InputType = "imm" in
413 def MUX_ri : ALU32_ri<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2,
415 "$dst = mux($src1, $src2, #$src3)",
416 [(set (i32 IntRegs:$dst),
417 (i32 (select (i1 PredRegs:$src1), (i32 IntRegs:$src2),
418 s8ExtPred:$src3)))]>, ImmRegRel;
420 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 8 in
421 def MUX_ii : ALU32_ii<(outs IntRegs:$dst), (ins PredRegs:$src1, s8Ext:$src2,
423 "$dst = mux($src1, #$src2, #$src3)",
424 [(set (i32 IntRegs:$dst), (i32 (select (i1 PredRegs:$src1),
426 s8ImmPred:$src3)))]>;
428 // ALU32 - aslh, asrh, sxtb, sxth, zxtb, zxth
429 multiclass ALU32_2op_Pbase<string mnemonic, bit isNot, bit isPredNew> {
430 let isPredicatedNew = isPredNew in
431 def NAME : ALU32Inst<(outs IntRegs:$dst),
432 (ins PredRegs:$src1, IntRegs:$src2),
433 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew,".new) $dst = ",
434 ") $dst = ")#mnemonic#"($src2)">,
438 multiclass ALU32_2op_Pred<string mnemonic, bit PredNot> {
439 let isPredicatedFalse = PredNot in {
440 defm _c#NAME : ALU32_2op_Pbase<mnemonic, PredNot, 0>;
442 defm _cdn#NAME : ALU32_2op_Pbase<mnemonic, PredNot, 1>;
446 multiclass ALU32_2op_base<string mnemonic> {
447 let BaseOpcode = mnemonic in {
448 let isPredicable = 1, neverHasSideEffects = 1 in
449 def NAME : ALU32Inst<(outs IntRegs:$dst),
451 "$dst = "#mnemonic#"($src1)">;
453 let Predicates = [HasV4T], validSubTargets = HasV4SubT, isPredicated = 1,
454 neverHasSideEffects = 1 in {
455 defm Pt_V4 : ALU32_2op_Pred<mnemonic, 0>;
456 defm NotPt_V4 : ALU32_2op_Pred<mnemonic, 1>;
461 defm ASLH : ALU32_2op_base<"aslh">, PredNewRel;
462 defm ASRH : ALU32_2op_base<"asrh">, PredNewRel;
463 defm SXTB : ALU32_2op_base<"sxtb">, PredNewRel;
464 defm SXTH : ALU32_2op_base<"sxth">, PredNewRel;
465 defm ZXTB : ALU32_2op_base<"zxtb">, PredNewRel;
466 defm ZXTH : ALU32_2op_base<"zxth">, PredNewRel;
468 def : Pat <(shl (i32 IntRegs:$src1), (i32 16)),
469 (ASLH IntRegs:$src1)>;
471 def : Pat <(sra (i32 IntRegs:$src1), (i32 16)),
472 (ASRH IntRegs:$src1)>;
474 def : Pat <(sext_inreg (i32 IntRegs:$src1), i8),
475 (SXTB IntRegs:$src1)>;
477 def : Pat <(sext_inreg (i32 IntRegs:$src1), i16),
478 (SXTH IntRegs:$src1)>;
480 //===----------------------------------------------------------------------===//
482 //===----------------------------------------------------------------------===//
485 //===----------------------------------------------------------------------===//
487 //===----------------------------------------------------------------------===//
490 defm CMPGTU : CMP32_rr_ri_u9<"cmp.gtu", "CMPGTU", setugt>, ImmRegRel;
491 defm CMPGT : CMP32_rr_ri_s10<"cmp.gt", "CMPGT", setgt>, ImmRegRel;
492 defm CMPEQ : CMP32_rr_ri_s10<"cmp.eq", "CMPEQ", seteq>, ImmRegRel;
494 // SDNode for converting immediate C to C-1.
495 def DEC_CONST_SIGNED : SDNodeXForm<imm, [{
496 // Return the byte immediate const-1 as an SDNode.
497 int32_t imm = N->getSExtValue();
498 return XformSToSM1Imm(imm);
501 // SDNode for converting immediate C to C-1.
502 def DEC_CONST_UNSIGNED : SDNodeXForm<imm, [{
503 // Return the byte immediate const-1 as an SDNode.
504 uint32_t imm = N->getZExtValue();
505 return XformUToUM1Imm(imm);
508 def CTLZ_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1),
510 [(set (i32 IntRegs:$dst), (ctlz (i32 IntRegs:$src1)))]>;
512 def CTTZ_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1),
514 [(set (i32 IntRegs:$dst), (cttz (i32 IntRegs:$src1)))]>;
516 def CTLZ64_rr : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1),
518 [(set (i32 IntRegs:$dst), (i32 (trunc (ctlz (i64 DoubleRegs:$src1)))))]>;
520 def CTTZ64_rr : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1),
522 [(set (i32 IntRegs:$dst), (i32 (trunc (cttz (i64 DoubleRegs:$src1)))))]>;
524 def TSTBIT_rr : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
525 "$dst = tstbit($src1, $src2)",
526 [(set (i1 PredRegs:$dst),
527 (setne (and (shl 1, (i32 IntRegs:$src2)), (i32 IntRegs:$src1)), 0))]>;
529 def TSTBIT_ri : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
530 "$dst = tstbit($src1, $src2)",
531 [(set (i1 PredRegs:$dst),
532 (setne (and (shl 1, (u5ImmPred:$src2)), (i32 IntRegs:$src1)), 0))]>;
534 //===----------------------------------------------------------------------===//
536 //===----------------------------------------------------------------------===//
539 //===----------------------------------------------------------------------===//
541 //===----------------------------------------------------------------------===//
543 def ADD64_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
545 "$dst = add($src1, $src2)",
546 [(set (i64 DoubleRegs:$dst), (add (i64 DoubleRegs:$src1),
547 (i64 DoubleRegs:$src2)))]>;
552 defm CMPEHexagon4 : CMP64_rr<"cmp.eq", seteq>;
553 defm CMPGT64 : CMP64_rr<"cmp.gt", setgt>;
554 defm CMPGTU64 : CMP64_rr<"cmp.gtu", setugt>;
556 // Logical operations.
557 def AND_rr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
559 "$dst = and($src1, $src2)",
560 [(set (i64 DoubleRegs:$dst), (and (i64 DoubleRegs:$src1),
561 (i64 DoubleRegs:$src2)))]>;
563 def OR_rr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
565 "$dst = or($src1, $src2)",
566 [(set (i64 DoubleRegs:$dst), (or (i64 DoubleRegs:$src1),
567 (i64 DoubleRegs:$src2)))]>;
569 def XOR_rr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
571 "$dst = xor($src1, $src2)",
572 [(set (i64 DoubleRegs:$dst), (xor (i64 DoubleRegs:$src1),
573 (i64 DoubleRegs:$src2)))]>;
576 def MAXw_rr : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
577 "$dst = max($src2, $src1)",
578 [(set (i32 IntRegs:$dst),
579 (i32 (select (i1 (setlt (i32 IntRegs:$src2),
580 (i32 IntRegs:$src1))),
581 (i32 IntRegs:$src1), (i32 IntRegs:$src2))))]>;
583 def MAXUw_rr : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
584 "$dst = maxu($src2, $src1)",
585 [(set (i32 IntRegs:$dst),
586 (i32 (select (i1 (setult (i32 IntRegs:$src2),
587 (i32 IntRegs:$src1))),
588 (i32 IntRegs:$src1), (i32 IntRegs:$src2))))]>;
590 def MAXd_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
592 "$dst = max($src2, $src1)",
593 [(set (i64 DoubleRegs:$dst),
594 (i64 (select (i1 (setlt (i64 DoubleRegs:$src2),
595 (i64 DoubleRegs:$src1))),
596 (i64 DoubleRegs:$src1),
597 (i64 DoubleRegs:$src2))))]>;
599 def MAXUd_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
601 "$dst = maxu($src2, $src1)",
602 [(set (i64 DoubleRegs:$dst),
603 (i64 (select (i1 (setult (i64 DoubleRegs:$src2),
604 (i64 DoubleRegs:$src1))),
605 (i64 DoubleRegs:$src1),
606 (i64 DoubleRegs:$src2))))]>;
609 def MINw_rr : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
610 "$dst = min($src2, $src1)",
611 [(set (i32 IntRegs:$dst),
612 (i32 (select (i1 (setgt (i32 IntRegs:$src2),
613 (i32 IntRegs:$src1))),
614 (i32 IntRegs:$src1), (i32 IntRegs:$src2))))]>;
616 def MINUw_rr : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
617 "$dst = minu($src2, $src1)",
618 [(set (i32 IntRegs:$dst),
619 (i32 (select (i1 (setugt (i32 IntRegs:$src2),
620 (i32 IntRegs:$src1))),
621 (i32 IntRegs:$src1), (i32 IntRegs:$src2))))]>;
623 def MINd_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
625 "$dst = min($src2, $src1)",
626 [(set (i64 DoubleRegs:$dst),
627 (i64 (select (i1 (setgt (i64 DoubleRegs:$src2),
628 (i64 DoubleRegs:$src1))),
629 (i64 DoubleRegs:$src1),
630 (i64 DoubleRegs:$src2))))]>;
632 def MINUd_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
634 "$dst = minu($src2, $src1)",
635 [(set (i64 DoubleRegs:$dst),
636 (i64 (select (i1 (setugt (i64 DoubleRegs:$src2),
637 (i64 DoubleRegs:$src1))),
638 (i64 DoubleRegs:$src1),
639 (i64 DoubleRegs:$src2))))]>;
642 def SUB64_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
644 "$dst = sub($src1, $src2)",
645 [(set (i64 DoubleRegs:$dst), (sub (i64 DoubleRegs:$src1),
646 (i64 DoubleRegs:$src2)))]>;
648 // Subtract halfword.
650 //===----------------------------------------------------------------------===//
652 //===----------------------------------------------------------------------===//
654 //===----------------------------------------------------------------------===//
656 //===----------------------------------------------------------------------===//
658 //===----------------------------------------------------------------------===//
660 //===----------------------------------------------------------------------===//
662 //===----------------------------------------------------------------------===//
664 //===----------------------------------------------------------------------===//
666 //===----------------------------------------------------------------------===//
668 //===----------------------------------------------------------------------===//
670 //===----------------------------------------------------------------------===//
672 //===----------------------------------------------------------------------===//
673 // Logical reductions on predicates.
675 // Looping instructions.
677 // Pipelined looping instructions.
679 // Logical operations on predicates.
680 def AND_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1, PredRegs:$src2),
681 "$dst = and($src1, $src2)",
682 [(set (i1 PredRegs:$dst), (and (i1 PredRegs:$src1),
683 (i1 PredRegs:$src2)))]>;
685 let neverHasSideEffects = 1 in
686 def AND_pnotp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1,
688 "$dst = and($src1, !$src2)",
691 def ANY_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1),
692 "$dst = any8($src1)",
695 def ALL_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1),
696 "$dst = all8($src1)",
699 def VITPACK_pp : SInst<(outs IntRegs:$dst), (ins PredRegs:$src1,
701 "$dst = vitpack($src1, $src2)",
704 def VALIGN_rrp : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
707 "$dst = valignb($src1, $src2, $src3)",
710 def VSPLICE_rrp : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
713 "$dst = vspliceb($src1, $src2, $src3)",
716 def MASK_p : SInst<(outs DoubleRegs:$dst), (ins PredRegs:$src1),
717 "$dst = mask($src1)",
720 def NOT_p : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1),
722 [(set (i1 PredRegs:$dst), (not (i1 PredRegs:$src1)))]>;
724 def OR_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1, PredRegs:$src2),
725 "$dst = or($src1, $src2)",
726 [(set (i1 PredRegs:$dst), (or (i1 PredRegs:$src1),
727 (i1 PredRegs:$src2)))]>;
729 def XOR_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1, PredRegs:$src2),
730 "$dst = xor($src1, $src2)",
731 [(set (i1 PredRegs:$dst), (xor (i1 PredRegs:$src1),
732 (i1 PredRegs:$src2)))]>;
735 // User control register transfer.
736 //===----------------------------------------------------------------------===//
738 //===----------------------------------------------------------------------===//
741 //===----------------------------------------------------------------------===//
743 //===----------------------------------------------------------------------===//
745 let isBranch = 1, isTerminator=1, isBarrier = 1, isPredicable = 1 in {
746 def JMP : JInst< (outs),
747 (ins brtarget:$offset),
753 let isBranch = 1, isTerminator=1, Defs = [PC],
754 isPredicated = 1 in {
755 def JMP_c : JInst< (outs),
756 (ins PredRegs:$src, brtarget:$offset),
757 "if ($src) jump $offset",
758 [(brcond (i1 PredRegs:$src), bb:$offset)]>;
762 let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC],
763 isPredicated = 1 in {
764 def JMP_cNot : JInst< (outs),
765 (ins PredRegs:$src, brtarget:$offset),
766 "if (!$src) jump $offset",
770 let isTerminator = 1, isBranch = 1, neverHasSideEffects = 1, Defs = [PC],
771 isPredicated = 1 in {
772 def BRCOND : JInst < (outs), (ins PredRegs:$pred, brtarget:$dst),
773 "if ($pred) jump $dst",
777 // Jump to address conditioned on new predicate.
779 let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC],
780 isPredicated = 1 in {
781 def JMP_cdnPt : JInst< (outs),
782 (ins PredRegs:$src, brtarget:$offset),
783 "if ($src.new) jump:t $offset",
788 let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC],
789 isPredicated = 1 in {
790 def JMP_cdnNotPt : JInst< (outs),
791 (ins PredRegs:$src, brtarget:$offset),
792 "if (!$src.new) jump:t $offset",
797 let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC],
798 isPredicated = 1 in {
799 def JMP_cdnPnt : JInst< (outs),
800 (ins PredRegs:$src, brtarget:$offset),
801 "if ($src.new) jump:nt $offset",
806 let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC],
807 isPredicated = 1 in {
808 def JMP_cdnNotPnt : JInst< (outs),
809 (ins PredRegs:$src, brtarget:$offset),
810 "if (!$src.new) jump:nt $offset",
813 //===----------------------------------------------------------------------===//
815 //===----------------------------------------------------------------------===//
817 //===----------------------------------------------------------------------===//
819 //===----------------------------------------------------------------------===//
820 def retflag : SDNode<"HexagonISD::RET_FLAG", SDTNone,
821 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
823 // Jump to address from register.
824 let isPredicable =1, isReturn = 1, isTerminator = 1, isBarrier = 1,
825 Defs = [PC], Uses = [R31] in {
826 def JMPR: JRInst<(outs), (ins),
831 // Jump to address from register.
832 let isReturn = 1, isTerminator = 1, isBarrier = 1, isPredicated = 1,
833 Defs = [PC], Uses = [R31] in {
834 def JMPR_cPt: JRInst<(outs), (ins PredRegs:$src1),
835 "if ($src1) jumpr r31",
839 // Jump to address from register.
840 let isReturn = 1, isTerminator = 1, isBarrier = 1, isPredicated = 1,
841 Defs = [PC], Uses = [R31] in {
842 def JMPR_cNotPt: JRInst<(outs), (ins PredRegs:$src1),
843 "if (!$src1) jumpr r31",
847 //===----------------------------------------------------------------------===//
849 //===----------------------------------------------------------------------===//
851 //===----------------------------------------------------------------------===//
853 //===----------------------------------------------------------------------===//
855 // Load -- MEMri operand
856 multiclass LD_MEMri_Pbase<string mnemonic, RegisterClass RC,
857 bit isNot, bit isPredNew> {
858 let isPredicatedNew = isPredNew in
859 def NAME : LDInst2<(outs RC:$dst),
860 (ins PredRegs:$src1, MEMri:$addr),
861 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
862 ") ")#"$dst = "#mnemonic#"($addr)",
866 multiclass LD_MEMri_Pred<string mnemonic, RegisterClass RC, bit PredNot> {
867 let isPredicatedFalse = PredNot in {
868 defm _c#NAME : LD_MEMri_Pbase<mnemonic, RC, PredNot, 0>;
870 defm _cdn#NAME : LD_MEMri_Pbase<mnemonic, RC, PredNot, 1>;
874 let isExtendable = 1, neverHasSideEffects = 1 in
875 multiclass LD_MEMri<string mnemonic, string CextOp, RegisterClass RC,
876 bits<5> ImmBits, bits<5> PredImmBits> {
878 let CextOpcode = CextOp, BaseOpcode = CextOp in {
879 let opExtendable = 2, isExtentSigned = 1, opExtentBits = ImmBits,
881 def NAME : LDInst2<(outs RC:$dst), (ins MEMri:$addr),
882 "$dst = "#mnemonic#"($addr)",
885 let opExtendable = 3, isExtentSigned = 0, opExtentBits = PredImmBits,
886 isPredicated = 1 in {
887 defm Pt : LD_MEMri_Pred<mnemonic, RC, 0 >;
888 defm NotPt : LD_MEMri_Pred<mnemonic, RC, 1 >;
893 let addrMode = BaseImmOffset, isMEMri = "true" in {
894 defm LDrib: LD_MEMri < "memb", "LDrib", IntRegs, 11, 6>, AddrModeRel;
895 defm LDriub: LD_MEMri < "memub" , "LDriub", IntRegs, 11, 6>, AddrModeRel;
896 defm LDrih: LD_MEMri < "memh", "LDrih", IntRegs, 12, 7>, AddrModeRel;
897 defm LDriuh: LD_MEMri < "memuh", "LDriuh", IntRegs, 12, 7>, AddrModeRel;
898 defm LDriw: LD_MEMri < "memw", "LDriw", IntRegs, 13, 8>, AddrModeRel;
899 defm LDrid: LD_MEMri < "memd", "LDrid", DoubleRegs, 14, 9>, AddrModeRel;
902 def : Pat < (i32 (sextloadi8 ADDRriS11_0:$addr)),
903 (LDrib ADDRriS11_0:$addr) >;
905 def : Pat < (i32 (zextloadi8 ADDRriS11_0:$addr)),
906 (LDriub ADDRriS11_0:$addr) >;
908 def : Pat < (i32 (sextloadi16 ADDRriS11_1:$addr)),
909 (LDrih ADDRriS11_1:$addr) >;
911 def : Pat < (i32 (zextloadi16 ADDRriS11_1:$addr)),
912 (LDriuh ADDRriS11_1:$addr) >;
914 def : Pat < (i32 (load ADDRriS11_2:$addr)),
915 (LDriw ADDRriS11_2:$addr) >;
917 def : Pat < (i64 (load ADDRriS11_3:$addr)),
918 (LDrid ADDRriS11_3:$addr) >;
921 // Load - Base with Immediate offset addressing mode
922 multiclass LD_Idxd_Pbase<string mnemonic, RegisterClass RC, Operand predImmOp,
923 bit isNot, bit isPredNew> {
924 let isPredicatedNew = isPredNew in
925 def NAME : LDInst2<(outs RC:$dst),
926 (ins PredRegs:$src1, IntRegs:$src2, predImmOp:$src3),
927 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
928 ") ")#"$dst = "#mnemonic#"($src2+#$src3)",
932 multiclass LD_Idxd_Pred<string mnemonic, RegisterClass RC, Operand predImmOp,
934 let isPredicatedFalse = PredNot in {
935 defm _c#NAME : LD_Idxd_Pbase<mnemonic, RC, predImmOp, PredNot, 0>;
937 defm _cdn#NAME : LD_Idxd_Pbase<mnemonic, RC, predImmOp, PredNot, 1>;
941 let isExtendable = 1, neverHasSideEffects = 1 in
942 multiclass LD_Idxd<string mnemonic, string CextOp, RegisterClass RC,
943 Operand ImmOp, Operand predImmOp, bits<5> ImmBits,
944 bits<5> PredImmBits> {
946 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed in {
947 let opExtendable = 2, isExtentSigned = 1, opExtentBits = ImmBits,
948 isPredicable = 1, AddedComplexity = 20 in
949 def NAME : LDInst2<(outs RC:$dst), (ins IntRegs:$src1, ImmOp:$offset),
950 "$dst = "#mnemonic#"($src1+#$offset)",
953 let opExtendable = 3, isExtentSigned = 0, opExtentBits = PredImmBits,
954 isPredicated = 1 in {
955 defm Pt : LD_Idxd_Pred<mnemonic, RC, predImmOp, 0 >;
956 defm NotPt : LD_Idxd_Pred<mnemonic, RC, predImmOp, 1 >;
961 let addrMode = BaseImmOffset in {
962 defm LDrib_indexed: LD_Idxd <"memb", "LDrib", IntRegs, s11_0Ext, u6_0Ext,
964 defm LDriub_indexed: LD_Idxd <"memub" , "LDriub", IntRegs, s11_0Ext, u6_0Ext,
966 defm LDrih_indexed: LD_Idxd <"memh", "LDrih", IntRegs, s11_1Ext, u6_1Ext,
968 defm LDriuh_indexed: LD_Idxd <"memuh", "LDriuh", IntRegs, s11_1Ext, u6_1Ext,
970 defm LDriw_indexed: LD_Idxd <"memw", "LDriw", IntRegs, s11_2Ext, u6_2Ext,
972 defm LDrid_indexed: LD_Idxd <"memd", "LDrid", DoubleRegs, s11_3Ext, u6_3Ext,
976 let AddedComplexity = 20 in {
977 def : Pat < (i32 (sextloadi8 (add IntRegs:$src1, s11_0ExtPred:$offset))),
978 (LDrib_indexed IntRegs:$src1, s11_0ExtPred:$offset) >;
980 def : Pat < (i32 (zextloadi8 (add IntRegs:$src1, s11_0ExtPred:$offset))),
981 (LDriub_indexed IntRegs:$src1, s11_0ExtPred:$offset) >;
983 def : Pat < (i32 (sextloadi16 (add IntRegs:$src1, s11_1ExtPred:$offset))),
984 (LDrih_indexed IntRegs:$src1, s11_1ExtPred:$offset) >;
986 def : Pat < (i32 (zextloadi16 (add IntRegs:$src1, s11_1ExtPred:$offset))),
987 (LDriuh_indexed IntRegs:$src1, s11_1ExtPred:$offset) >;
989 def : Pat < (i32 (load (add IntRegs:$src1, s11_2ExtPred:$offset))),
990 (LDriw_indexed IntRegs:$src1, s11_2ExtPred:$offset) >;
992 def : Pat < (i64 (load (add IntRegs:$src1, s11_3ExtPred:$offset))),
993 (LDrid_indexed IntRegs:$src1, s11_3ExtPred:$offset) >;
996 //===----------------------------------------------------------------------===//
997 // Post increment load
998 // Make sure that in post increment load, the first operand is always the post
999 // increment operand.
1000 //===----------------------------------------------------------------------===//
1002 multiclass LD_PostInc_Pbase<string mnemonic, RegisterClass RC, Operand ImmOp,
1003 bit isNot, bit isPredNew> {
1004 let isPredicatedNew = isPredNew in
1005 def NAME : LDInst2PI<(outs RC:$dst, IntRegs:$dst2),
1006 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset),
1007 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1008 ") ")#"$dst = "#mnemonic#"($src2++#$offset)",
1013 multiclass LD_PostInc_Pred<string mnemonic, RegisterClass RC,
1014 Operand ImmOp, bit PredNot> {
1015 let isPredicatedFalse = PredNot in {
1016 defm _c#NAME : LD_PostInc_Pbase<mnemonic, RC, ImmOp, PredNot, 0>;
1018 let Predicates = [HasV4T], validSubTargets = HasV4SubT in
1019 defm _cdn#NAME#_V4 : LD_PostInc_Pbase<mnemonic, RC, ImmOp, PredNot, 1>;
1023 multiclass LD_PostInc<string mnemonic, string BaseOp, RegisterClass RC,
1026 let BaseOpcode = "POST_"#BaseOp in {
1027 let isPredicable = 1 in
1028 def NAME : LDInst2PI<(outs RC:$dst, IntRegs:$dst2),
1029 (ins IntRegs:$src1, ImmOp:$offset),
1030 "$dst = "#mnemonic#"($src1++#$offset)",
1034 let isPredicated = 1 in {
1035 defm Pt : LD_PostInc_Pred<mnemonic, RC, ImmOp, 0 >;
1036 defm NotPt : LD_PostInc_Pred<mnemonic, RC, ImmOp, 1 >;
1041 let hasCtrlDep = 1, neverHasSideEffects = 1 in {
1042 defm POST_LDrib : LD_PostInc<"memb", "LDrib", IntRegs, s4_0Imm>,
1044 defm POST_LDriub : LD_PostInc<"memub", "LDriub", IntRegs, s4_0Imm>,
1046 defm POST_LDrih : LD_PostInc<"memh", "LDrih", IntRegs, s4_1Imm>,
1048 defm POST_LDriuh : LD_PostInc<"memuh", "LDriuh", IntRegs, s4_1Imm>,
1050 defm POST_LDriw : LD_PostInc<"memw", "LDriw", IntRegs, s4_2Imm>,
1052 defm POST_LDrid : LD_PostInc<"memd", "LDrid", DoubleRegs, s4_3Imm>,
1056 def : Pat< (i32 (extloadi1 ADDRriS11_0:$addr)),
1057 (i32 (LDrib ADDRriS11_0:$addr)) >;
1059 // Load byte any-extend.
1060 def : Pat < (i32 (extloadi8 ADDRriS11_0:$addr)),
1061 (i32 (LDrib ADDRriS11_0:$addr)) >;
1063 // Indexed load byte any-extend.
1064 let AddedComplexity = 20 in
1065 def : Pat < (i32 (extloadi8 (add IntRegs:$src1, s11_0ImmPred:$offset))),
1066 (i32 (LDrib_indexed IntRegs:$src1, s11_0ImmPred:$offset)) >;
1068 def : Pat < (i32 (extloadi16 ADDRriS11_1:$addr)),
1069 (i32 (LDrih ADDRriS11_1:$addr))>;
1071 let AddedComplexity = 20 in
1072 def : Pat < (i32 (extloadi16 (add IntRegs:$src1, s11_1ImmPred:$offset))),
1073 (i32 (LDrih_indexed IntRegs:$src1, s11_1ImmPred:$offset)) >;
1075 let AddedComplexity = 10 in
1076 def : Pat < (i32 (zextloadi1 ADDRriS11_0:$addr)),
1077 (i32 (LDriub ADDRriS11_0:$addr))>;
1079 let AddedComplexity = 20 in
1080 def : Pat < (i32 (zextloadi1 (add IntRegs:$src1, s11_0ImmPred:$offset))),
1081 (i32 (LDriub_indexed IntRegs:$src1, s11_0ImmPred:$offset))>;
1084 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 13,
1085 isPseudo = 1, Defs = [R10,R11,D5], neverHasSideEffects = 1 in
1086 def LDriw_pred : LDInst2<(outs PredRegs:$dst),
1088 "Error; should not emit",
1091 // Deallocate stack frame.
1092 let Defs = [R29, R30, R31], Uses = [R29], neverHasSideEffects = 1 in {
1093 def DEALLOCFRAME : LDInst2<(outs), (ins),
1098 // Load and unpack bytes to halfwords.
1099 //===----------------------------------------------------------------------===//
1101 //===----------------------------------------------------------------------===//
1103 //===----------------------------------------------------------------------===//
1105 //===----------------------------------------------------------------------===//
1106 //===----------------------------------------------------------------------===//
1108 //===----------------------------------------------------------------------===//
1110 //===----------------------------------------------------------------------===//
1112 //===----------------------------------------------------------------------===//
1113 //===----------------------------------------------------------------------===//
1115 //===----------------------------------------------------------------------===//
1117 //===----------------------------------------------------------------------===//
1119 //===----------------------------------------------------------------------===//
1120 // Multiply and use lower result.
1122 let isExtendable = 1, opExtendable = 2, isExtentSigned = 0, opExtentBits = 8 in
1123 def MPYI_riu : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u8Ext:$src2),
1124 "$dst =+ mpyi($src1, #$src2)",
1125 [(set (i32 IntRegs:$dst), (mul (i32 IntRegs:$src1),
1126 u8ExtPred:$src2))]>;
1129 def MPYI_rin : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u8Imm:$src2),
1130 "$dst =- mpyi($src1, #$src2)",
1131 [(set (i32 IntRegs:$dst), (ineg (mul (i32 IntRegs:$src1),
1132 u8ImmPred:$src2)))]>;
1135 // s9 is NOT the same as m9 - but it works.. so far.
1136 // Assembler maps to either Rd=+mpyi(Rs,#u8 or Rd=-mpyi(Rs,#u8)
1137 // depending on the value of m9. See Arch Spec.
1138 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 9,
1139 CextOpcode = "MPYI", InputType = "imm" in
1140 def MPYI_ri : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, s9Ext:$src2),
1141 "$dst = mpyi($src1, #$src2)",
1142 [(set (i32 IntRegs:$dst), (mul (i32 IntRegs:$src1),
1143 s9ExtPred:$src2))]>, ImmRegRel;
1146 let CextOpcode = "MPYI", InputType = "reg" in
1147 def MPYI : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1148 "$dst = mpyi($src1, $src2)",
1149 [(set (i32 IntRegs:$dst), (mul (i32 IntRegs:$src1),
1150 (i32 IntRegs:$src2)))]>, ImmRegRel;
1153 let isExtendable = 1, opExtendable = 3, isExtentSigned = 0, opExtentBits = 8,
1154 CextOpcode = "MPYI_acc", InputType = "imm" in
1155 def MPYI_acc_ri : MInst_acc<(outs IntRegs:$dst),
1156 (ins IntRegs:$src1, IntRegs:$src2, u8Ext:$src3),
1157 "$dst += mpyi($src2, #$src3)",
1158 [(set (i32 IntRegs:$dst),
1159 (add (mul (i32 IntRegs:$src2), u8ExtPred:$src3),
1160 (i32 IntRegs:$src1)))],
1161 "$src1 = $dst">, ImmRegRel;
1164 let CextOpcode = "MPYI_acc", InputType = "reg" in
1165 def MPYI_acc_rr : MInst_acc<(outs IntRegs:$dst),
1166 (ins IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
1167 "$dst += mpyi($src2, $src3)",
1168 [(set (i32 IntRegs:$dst),
1169 (add (mul (i32 IntRegs:$src2), (i32 IntRegs:$src3)),
1170 (i32 IntRegs:$src1)))],
1171 "$src1 = $dst">, ImmRegRel;
1174 let isExtendable = 1, opExtendable = 3, isExtentSigned = 0, opExtentBits = 8 in
1175 def MPYI_sub_ri : MInst_acc<(outs IntRegs:$dst),
1176 (ins IntRegs:$src1, IntRegs:$src2, u8Ext:$src3),
1177 "$dst -= mpyi($src2, #$src3)",
1178 [(set (i32 IntRegs:$dst),
1179 (sub (i32 IntRegs:$src1), (mul (i32 IntRegs:$src2),
1180 u8ExtPred:$src3)))],
1183 // Multiply and use upper result.
1184 // Rd=mpy(Rs,Rt.H):<<1:rnd:sat
1185 // Rd=mpy(Rs,Rt.L):<<1:rnd:sat
1187 def MPY : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1188 "$dst = mpy($src1, $src2)",
1189 [(set (i32 IntRegs:$dst), (mulhs (i32 IntRegs:$src1),
1190 (i32 IntRegs:$src2)))]>;
1192 // Rd=mpy(Rs,Rt):rnd
1194 def MPYU : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1195 "$dst = mpyu($src1, $src2)",
1196 [(set (i32 IntRegs:$dst), (mulhu (i32 IntRegs:$src1),
1197 (i32 IntRegs:$src2)))]>;
1199 // Multiply and use full result.
1201 def MPYU64 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1202 "$dst = mpyu($src1, $src2)",
1203 [(set (i64 DoubleRegs:$dst),
1204 (mul (i64 (anyext (i32 IntRegs:$src1))),
1205 (i64 (anyext (i32 IntRegs:$src2)))))]>;
1208 def MPY64 : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1209 "$dst = mpy($src1, $src2)",
1210 [(set (i64 DoubleRegs:$dst),
1211 (mul (i64 (sext (i32 IntRegs:$src1))),
1212 (i64 (sext (i32 IntRegs:$src2)))))]>;
1214 // Multiply and accumulate, use full result.
1215 // Rxx[+-]=mpy(Rs,Rt)
1217 def MPY64_acc : MInst_acc<(outs DoubleRegs:$dst),
1218 (ins DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),
1219 "$dst += mpy($src2, $src3)",
1220 [(set (i64 DoubleRegs:$dst),
1221 (add (mul (i64 (sext (i32 IntRegs:$src2))),
1222 (i64 (sext (i32 IntRegs:$src3)))),
1223 (i64 DoubleRegs:$src1)))],
1227 def MPY64_sub : MInst_acc<(outs DoubleRegs:$dst),
1228 (ins DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),
1229 "$dst -= mpy($src2, $src3)",
1230 [(set (i64 DoubleRegs:$dst),
1231 (sub (i64 DoubleRegs:$src1),
1232 (mul (i64 (sext (i32 IntRegs:$src2))),
1233 (i64 (sext (i32 IntRegs:$src3))))))],
1236 // Rxx[+-]=mpyu(Rs,Rt)
1238 def MPYU64_acc : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
1239 IntRegs:$src2, IntRegs:$src3),
1240 "$dst += mpyu($src2, $src3)",
1241 [(set (i64 DoubleRegs:$dst),
1242 (add (mul (i64 (anyext (i32 IntRegs:$src2))),
1243 (i64 (anyext (i32 IntRegs:$src3)))),
1244 (i64 DoubleRegs:$src1)))], "$src1 = $dst">;
1247 def MPYU64_sub : MInst_acc<(outs DoubleRegs:$dst),
1248 (ins DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),
1249 "$dst -= mpyu($src2, $src3)",
1250 [(set (i64 DoubleRegs:$dst),
1251 (sub (i64 DoubleRegs:$src1),
1252 (mul (i64 (anyext (i32 IntRegs:$src2))),
1253 (i64 (anyext (i32 IntRegs:$src3))))))],
1257 let InputType = "reg", CextOpcode = "ADD_acc" in
1258 def ADDrr_acc : MInst_acc<(outs IntRegs: $dst), (ins IntRegs:$src1,
1259 IntRegs:$src2, IntRegs:$src3),
1260 "$dst += add($src2, $src3)",
1261 [(set (i32 IntRegs:$dst), (add (add (i32 IntRegs:$src2),
1262 (i32 IntRegs:$src3)),
1263 (i32 IntRegs:$src1)))],
1264 "$src1 = $dst">, ImmRegRel;
1266 let isExtendable = 1, opExtendable = 3, isExtentSigned = 1, opExtentBits = 8,
1267 InputType = "imm", CextOpcode = "ADD_acc" in
1268 def ADDri_acc : MInst_acc<(outs IntRegs: $dst), (ins IntRegs:$src1,
1269 IntRegs:$src2, s8Ext:$src3),
1270 "$dst += add($src2, #$src3)",
1271 [(set (i32 IntRegs:$dst), (add (add (i32 IntRegs:$src2),
1272 s8_16ExtPred:$src3),
1273 (i32 IntRegs:$src1)))],
1274 "$src1 = $dst">, ImmRegRel;
1276 let CextOpcode = "SUB_acc", InputType = "reg" in
1277 def SUBrr_acc : MInst_acc<(outs IntRegs: $dst), (ins IntRegs:$src1,
1278 IntRegs:$src2, IntRegs:$src3),
1279 "$dst -= add($src2, $src3)",
1280 [(set (i32 IntRegs:$dst),
1281 (sub (i32 IntRegs:$src1), (add (i32 IntRegs:$src2),
1282 (i32 IntRegs:$src3))))],
1283 "$src1 = $dst">, ImmRegRel;
1285 let isExtendable = 1, opExtendable = 3, isExtentSigned = 1, opExtentBits = 8,
1286 CextOpcode = "SUB_acc", InputType = "imm" in
1287 def SUBri_acc : MInst_acc<(outs IntRegs: $dst), (ins IntRegs:$src1,
1288 IntRegs:$src2, s8Ext:$src3),
1289 "$dst -= add($src2, #$src3)",
1290 [(set (i32 IntRegs:$dst), (sub (i32 IntRegs:$src1),
1291 (add (i32 IntRegs:$src2),
1292 s8_16ExtPred:$src3)))],
1293 "$src1 = $dst">, ImmRegRel;
1295 //===----------------------------------------------------------------------===//
1297 //===----------------------------------------------------------------------===//
1299 //===----------------------------------------------------------------------===//
1301 //===----------------------------------------------------------------------===//
1302 //===----------------------------------------------------------------------===//
1304 //===----------------------------------------------------------------------===//
1306 //===----------------------------------------------------------------------===//
1308 //===----------------------------------------------------------------------===//
1309 //===----------------------------------------------------------------------===//
1311 //===----------------------------------------------------------------------===//
1313 //===----------------------------------------------------------------------===//
1315 //===----------------------------------------------------------------------===//
1316 //===----------------------------------------------------------------------===//
1318 //===----------------------------------------------------------------------===//
1320 //===----------------------------------------------------------------------===//
1322 //===----------------------------------------------------------------------===//
1324 // Store doubleword.
1326 //===----------------------------------------------------------------------===//
1327 // Post increment store
1328 //===----------------------------------------------------------------------===//
1330 multiclass ST_PostInc_Pbase<string mnemonic, RegisterClass RC, Operand ImmOp,
1331 bit isNot, bit isPredNew> {
1332 let isPredicatedNew = isPredNew in
1333 def NAME : STInst2PI<(outs IntRegs:$dst),
1334 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset, RC:$src3),
1335 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1336 ") ")#mnemonic#"($src2++#$offset) = $src3",
1341 multiclass ST_PostInc_Pred<string mnemonic, RegisterClass RC,
1342 Operand ImmOp, bit PredNot> {
1343 let isPredicatedFalse = PredNot in {
1344 defm _c#NAME# : ST_PostInc_Pbase<mnemonic, RC, ImmOp, PredNot, 0>;
1346 let Predicates = [HasV4T], validSubTargets = HasV4SubT in
1347 defm _cdn#NAME#_V4 : ST_PostInc_Pbase<mnemonic, RC, ImmOp, PredNot, 1>;
1351 let hasCtrlDep = 1, isNVStorable = 1, neverHasSideEffects = 1 in
1352 multiclass ST_PostInc<string mnemonic, string BaseOp, RegisterClass RC,
1355 let hasCtrlDep = 1, BaseOpcode = "POST_"#BaseOp in {
1356 let isPredicable = 1 in
1357 def NAME : STInst2PI<(outs IntRegs:$dst),
1358 (ins IntRegs:$src1, ImmOp:$offset, RC:$src2),
1359 #mnemonic#"($src1++#$offset) = $src2",
1363 let isPredicated = 1 in {
1364 defm Pt : ST_PostInc_Pred<mnemonic, RC, ImmOp, 0 >;
1365 defm NotPt : ST_PostInc_Pred<mnemonic, RC, ImmOp, 1 >;
1370 defm POST_STbri: ST_PostInc <"memb", "STrib", IntRegs, s4_0Imm>, AddrModeRel;
1371 defm POST_SThri: ST_PostInc <"memh", "STrih", IntRegs, s4_1Imm>, AddrModeRel;
1372 defm POST_STwri: ST_PostInc <"memw", "STriw", IntRegs, s4_2Imm>, AddrModeRel;
1374 let isNVStorable = 0 in
1375 defm POST_STdri: ST_PostInc <"memd", "STrid", DoubleRegs, s4_3Imm>, AddrModeRel;
1377 def : Pat<(post_truncsti8 (i32 IntRegs:$src1), IntRegs:$src2,
1378 s4_3ImmPred:$offset),
1379 (POST_STbri IntRegs:$src2, s4_0ImmPred:$offset, IntRegs:$src1)>;
1381 def : Pat<(post_truncsti16 (i32 IntRegs:$src1), IntRegs:$src2,
1382 s4_3ImmPred:$offset),
1383 (POST_SThri IntRegs:$src2, s4_1ImmPred:$offset, IntRegs:$src1)>;
1385 def : Pat<(post_store (i32 IntRegs:$src1), IntRegs:$src2, s4_2ImmPred:$offset),
1386 (POST_STwri IntRegs:$src2, s4_1ImmPred:$offset, IntRegs:$src1)>;
1388 def : Pat<(post_store (i64 DoubleRegs:$src1), IntRegs:$src2,
1389 s4_3ImmPred:$offset),
1390 (POST_STdri IntRegs:$src2, s4_3ImmPred:$offset, DoubleRegs:$src1)>;
1392 //===----------------------------------------------------------------------===//
1393 // multiclass for the store instructions with MEMri operand.
1394 //===----------------------------------------------------------------------===//
1395 multiclass ST_MEMri_Pbase<string mnemonic, RegisterClass RC, bit isNot,
1397 let isPredicatedNew = isPredNew in
1398 def NAME : STInst2<(outs),
1399 (ins PredRegs:$src1, MEMri:$addr, RC: $src2),
1400 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1401 ") ")#mnemonic#"($addr) = $src2",
1405 multiclass ST_MEMri_Pred<string mnemonic, RegisterClass RC, bit PredNot> {
1406 let isPredicatedFalse = PredNot in {
1407 defm _c#NAME : ST_MEMri_Pbase<mnemonic, RC, PredNot, 0>;
1410 let validSubTargets = HasV4SubT, Predicates = [HasV4T] in
1411 defm _cdn#NAME#_V4 : ST_MEMri_Pbase<mnemonic, RC, PredNot, 1>;
1415 let isExtendable = 1, isNVStorable = 1, neverHasSideEffects = 1 in
1416 multiclass ST_MEMri<string mnemonic, string CextOp, RegisterClass RC,
1417 bits<5> ImmBits, bits<5> PredImmBits> {
1419 let CextOpcode = CextOp, BaseOpcode = CextOp in {
1420 let opExtendable = 1, isExtentSigned = 1, opExtentBits = ImmBits,
1422 def NAME : STInst2<(outs),
1423 (ins MEMri:$addr, RC:$src),
1424 mnemonic#"($addr) = $src",
1427 let opExtendable = 2, isExtentSigned = 0, opExtentBits = PredImmBits,
1428 isPredicated = 1 in {
1429 defm Pt : ST_MEMri_Pred<mnemonic, RC, 0>;
1430 defm NotPt : ST_MEMri_Pred<mnemonic, RC, 1>;
1435 let addrMode = BaseImmOffset, isMEMri = "true" in {
1436 defm STrib: ST_MEMri < "memb", "STrib", IntRegs, 11, 6>, AddrModeRel;
1437 defm STrih: ST_MEMri < "memh", "STrih", IntRegs, 12, 7>, AddrModeRel;
1438 defm STriw: ST_MEMri < "memw", "STriw", IntRegs, 13, 8>, AddrModeRel;
1440 let isNVStorable = 0 in
1441 defm STrid: ST_MEMri < "memd", "STrid", DoubleRegs, 14, 9>, AddrModeRel;
1444 def : Pat<(truncstorei8 (i32 IntRegs:$src1), ADDRriS11_0:$addr),
1445 (STrib ADDRriS11_0:$addr, (i32 IntRegs:$src1))>;
1447 def : Pat<(truncstorei16 (i32 IntRegs:$src1), ADDRriS11_1:$addr),
1448 (STrih ADDRriS11_1:$addr, (i32 IntRegs:$src1))>;
1450 def : Pat<(store (i32 IntRegs:$src1), ADDRriS11_2:$addr),
1451 (STriw ADDRriS11_2:$addr, (i32 IntRegs:$src1))>;
1453 def : Pat<(store (i64 DoubleRegs:$src1), ADDRriS11_3:$addr),
1454 (STrid ADDRriS11_3:$addr, (i64 DoubleRegs:$src1))>;
1457 //===----------------------------------------------------------------------===//
1458 // multiclass for the store instructions with base+immediate offset
1460 //===----------------------------------------------------------------------===//
1461 multiclass ST_Idxd_Pbase<string mnemonic, RegisterClass RC, Operand predImmOp,
1462 bit isNot, bit isPredNew> {
1463 let isPredicatedNew = isPredNew in
1464 def NAME : STInst2<(outs),
1465 (ins PredRegs:$src1, IntRegs:$src2, predImmOp:$src3, RC: $src4),
1466 !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
1467 ") ")#mnemonic#"($src2+#$src3) = $src4",
1471 multiclass ST_Idxd_Pred<string mnemonic, RegisterClass RC, Operand predImmOp,
1473 let isPredicatedFalse = PredNot, isPredicated = 1 in {
1474 defm _c#NAME : ST_Idxd_Pbase<mnemonic, RC, predImmOp, PredNot, 0>;
1477 let validSubTargets = HasV4SubT, Predicates = [HasV4T] in
1478 defm _cdn#NAME#_V4 : ST_Idxd_Pbase<mnemonic, RC, predImmOp, PredNot, 1>;
1482 let isExtendable = 1, isNVStorable = 1, neverHasSideEffects = 1 in
1483 multiclass ST_Idxd<string mnemonic, string CextOp, RegisterClass RC,
1484 Operand ImmOp, Operand predImmOp, bits<5> ImmBits,
1485 bits<5> PredImmBits> {
1487 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed in {
1488 let opExtendable = 1, isExtentSigned = 1, opExtentBits = ImmBits,
1490 def NAME : STInst2<(outs),
1491 (ins IntRegs:$src1, ImmOp:$src2, RC:$src3),
1492 mnemonic#"($src1+#$src2) = $src3",
1495 let opExtendable = 2, isExtentSigned = 0, opExtentBits = PredImmBits in {
1496 defm Pt : ST_Idxd_Pred<mnemonic, RC, predImmOp, 0>;
1497 defm NotPt : ST_Idxd_Pred<mnemonic, RC, predImmOp, 1>;
1502 let addrMode = BaseImmOffset, InputType = "reg" in {
1503 defm STrib_indexed: ST_Idxd < "memb", "STrib", IntRegs, s11_0Ext,
1504 u6_0Ext, 11, 6>, AddrModeRel, ImmRegRel;
1505 defm STrih_indexed: ST_Idxd < "memh", "STrih", IntRegs, s11_1Ext,
1506 u6_1Ext, 12, 7>, AddrModeRel, ImmRegRel;
1507 defm STriw_indexed: ST_Idxd < "memw", "STriw", IntRegs, s11_2Ext,
1508 u6_2Ext, 13, 8>, AddrModeRel, ImmRegRel;
1509 let isNVStorable = 0 in
1510 defm STrid_indexed: ST_Idxd < "memd", "STrid", DoubleRegs, s11_3Ext,
1511 u6_3Ext, 14, 9>, AddrModeRel;
1514 let AddedComplexity = 10 in {
1515 def : Pat<(truncstorei8 (i32 IntRegs:$src1), (add IntRegs:$src2,
1516 s11_0ExtPred:$offset)),
1517 (STrib_indexed IntRegs:$src2, s11_0ImmPred:$offset,
1518 (i32 IntRegs:$src1))>;
1520 def : Pat<(truncstorei16 (i32 IntRegs:$src1), (add IntRegs:$src2,
1521 s11_1ExtPred:$offset)),
1522 (STrih_indexed IntRegs:$src2, s11_1ImmPred:$offset,
1523 (i32 IntRegs:$src1))>;
1525 def : Pat<(store (i32 IntRegs:$src1), (add IntRegs:$src2,
1526 s11_2ExtPred:$offset)),
1527 (STriw_indexed IntRegs:$src2, s11_2ImmPred:$offset,
1528 (i32 IntRegs:$src1))>;
1530 def : Pat<(store (i64 DoubleRegs:$src1), (add IntRegs:$src2,
1531 s11_3ExtPred:$offset)),
1532 (STrid_indexed IntRegs:$src2, s11_3ImmPred:$offset,
1533 (i64 DoubleRegs:$src1))>;
1536 // memh(Rx++#s4:1)=Rt.H
1540 let Defs = [R10,R11,D5], neverHasSideEffects = 1 in
1541 def STriw_pred : STInst2<(outs),
1542 (ins MEMri:$addr, PredRegs:$src1),
1543 "Error; should not emit",
1546 // Allocate stack frame.
1547 let Defs = [R29, R30], Uses = [R31, R30], neverHasSideEffects = 1 in {
1548 def ALLOCFRAME : STInst2<(outs),
1550 "allocframe(#$amt)",
1553 //===----------------------------------------------------------------------===//
1555 //===----------------------------------------------------------------------===//
1557 //===----------------------------------------------------------------------===//
1559 //===----------------------------------------------------------------------===//
1561 def NOT_rr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1),
1562 "$dst = not($src1)",
1563 [(set (i64 DoubleRegs:$dst), (not (i64 DoubleRegs:$src1)))]>;
1566 // Sign extend word to doubleword.
1567 def SXTW : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src1),
1568 "$dst = sxtw($src1)",
1569 [(set (i64 DoubleRegs:$dst), (sext (i32 IntRegs:$src1)))]>;
1570 //===----------------------------------------------------------------------===//
1572 //===----------------------------------------------------------------------===//
1574 //===----------------------------------------------------------------------===//
1576 //===----------------------------------------------------------------------===//
1578 def CLRBIT : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1579 "$dst = clrbit($src1, #$src2)",
1580 [(set (i32 IntRegs:$dst), (and (i32 IntRegs:$src1),
1582 (shl 1, u5ImmPred:$src2))))]>;
1584 def CLRBIT_31 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1585 "$dst = clrbit($src1, #$src2)",
1588 // Map from r0 = and(r1, 2147483647) to r0 = clrbit(r1, #31).
1589 def : Pat <(and (i32 IntRegs:$src1), 2147483647),
1590 (CLRBIT_31 (i32 IntRegs:$src1), 31)>;
1593 def SETBIT : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1594 "$dst = setbit($src1, #$src2)",
1595 [(set (i32 IntRegs:$dst), (or (i32 IntRegs:$src1),
1596 (shl 1, u5ImmPred:$src2)))]>;
1598 // Map from r0 = or(r1, -2147483648) to r0 = setbit(r1, #31).
1599 def SETBIT_31 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1600 "$dst = setbit($src1, #$src2)",
1603 def : Pat <(or (i32 IntRegs:$src1), -2147483648),
1604 (SETBIT_31 (i32 IntRegs:$src1), 31)>;
1607 def TOGBIT : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1608 "$dst = setbit($src1, #$src2)",
1609 [(set (i32 IntRegs:$dst), (xor (i32 IntRegs:$src1),
1610 (shl 1, u5ImmPred:$src2)))]>;
1612 // Map from r0 = xor(r1, -2147483648) to r0 = togglebit(r1, #31).
1613 def TOGBIT_31 : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1614 "$dst = togglebit($src1, #$src2)",
1617 def : Pat <(xor (i32 IntRegs:$src1), -2147483648),
1618 (TOGBIT_31 (i32 IntRegs:$src1), 31)>;
1620 // Predicate transfer.
1621 let neverHasSideEffects = 1 in
1622 def TFR_RsPd : SInst<(outs IntRegs:$dst), (ins PredRegs:$src1),
1623 "$dst = $src1 /* Should almost never emit this. */",
1626 def TFR_PdRs : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1),
1627 "$dst = $src1 /* Should almost never emit this. */",
1628 [(set (i1 PredRegs:$dst), (trunc (i32 IntRegs:$src1)))]>;
1629 //===----------------------------------------------------------------------===//
1631 //===----------------------------------------------------------------------===//
1633 //===----------------------------------------------------------------------===//
1635 //===----------------------------------------------------------------------===//
1636 // Shift by immediate.
1637 def ASR_ri : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1638 "$dst = asr($src1, #$src2)",
1639 [(set (i32 IntRegs:$dst), (sra (i32 IntRegs:$src1),
1640 u5ImmPred:$src2))]>;
1642 def ASRd_ri : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u6Imm:$src2),
1643 "$dst = asr($src1, #$src2)",
1644 [(set (i64 DoubleRegs:$dst), (sra (i64 DoubleRegs:$src1),
1645 u6ImmPred:$src2))]>;
1647 def ASL : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1648 "$dst = asl($src1, #$src2)",
1649 [(set (i32 IntRegs:$dst), (shl (i32 IntRegs:$src1),
1650 u5ImmPred:$src2))]>;
1652 def ASLd_ri : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u6Imm:$src2),
1653 "$dst = asl($src1, #$src2)",
1654 [(set (i64 DoubleRegs:$dst), (shl (i64 DoubleRegs:$src1),
1655 u6ImmPred:$src2))]>;
1657 def LSR_ri : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
1658 "$dst = lsr($src1, #$src2)",
1659 [(set (i32 IntRegs:$dst), (srl (i32 IntRegs:$src1),
1660 u5ImmPred:$src2))]>;
1662 def LSRd_ri : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u6Imm:$src2),
1663 "$dst = lsr($src1, #$src2)",
1664 [(set (i64 DoubleRegs:$dst), (srl (i64 DoubleRegs:$src1),
1665 u6ImmPred:$src2))]>;
1667 // Shift by immediate and add.
1668 let AddedComplexity = 100 in
1669 def ADDASL : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2,
1671 "$dst = addasl($src1, $src2, #$src3)",
1672 [(set (i32 IntRegs:$dst), (add (i32 IntRegs:$src1),
1673 (shl (i32 IntRegs:$src2),
1674 u3ImmPred:$src3)))]>;
1676 // Shift by register.
1677 def ASL_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1678 "$dst = asl($src1, $src2)",
1679 [(set (i32 IntRegs:$dst), (shl (i32 IntRegs:$src1),
1680 (i32 IntRegs:$src2)))]>;
1682 def ASR_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1683 "$dst = asr($src1, $src2)",
1684 [(set (i32 IntRegs:$dst), (sra (i32 IntRegs:$src1),
1685 (i32 IntRegs:$src2)))]>;
1687 def LSL_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1688 "$dst = lsl($src1, $src2)",
1689 [(set (i32 IntRegs:$dst), (shl (i32 IntRegs:$src1),
1690 (i32 IntRegs:$src2)))]>;
1692 def LSR_rr : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1693 "$dst = lsr($src1, $src2)",
1694 [(set (i32 IntRegs:$dst), (srl (i32 IntRegs:$src1),
1695 (i32 IntRegs:$src2)))]>;
1697 def ASLd : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
1698 "$dst = asl($src1, $src2)",
1699 [(set (i64 DoubleRegs:$dst), (shl (i64 DoubleRegs:$src1),
1700 (i32 IntRegs:$src2)))]>;
1702 def LSLd : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
1703 "$dst = lsl($src1, $src2)",
1704 [(set (i64 DoubleRegs:$dst), (shl (i64 DoubleRegs:$src1),
1705 (i32 IntRegs:$src2)))]>;
1707 def ASRd_rr : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
1709 "$dst = asr($src1, $src2)",
1710 [(set (i64 DoubleRegs:$dst), (sra (i64 DoubleRegs:$src1),
1711 (i32 IntRegs:$src2)))]>;
1713 def LSRd_rr : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
1715 "$dst = lsr($src1, $src2)",
1716 [(set (i64 DoubleRegs:$dst), (srl (i64 DoubleRegs:$src1),
1717 (i32 IntRegs:$src2)))]>;
1719 //===----------------------------------------------------------------------===//
1721 //===----------------------------------------------------------------------===//
1723 //===----------------------------------------------------------------------===//
1725 //===----------------------------------------------------------------------===//
1726 //===----------------------------------------------------------------------===//
1728 //===----------------------------------------------------------------------===//
1730 //===----------------------------------------------------------------------===//
1732 //===----------------------------------------------------------------------===//
1733 //===----------------------------------------------------------------------===//
1735 //===----------------------------------------------------------------------===//
1737 //===----------------------------------------------------------------------===//
1739 //===----------------------------------------------------------------------===//
1741 //===----------------------------------------------------------------------===//
1743 //===----------------------------------------------------------------------===//
1744 def SDHexagonBARRIER: SDTypeProfile<0, 0, []>;
1745 def HexagonBARRIER: SDNode<"HexagonISD::BARRIER", SDHexagonBARRIER,
1748 let hasSideEffects = 1, isSolo = 1 in
1749 def BARRIER : SYSInst<(outs), (ins),
1751 [(HexagonBARRIER)]>;
1753 //===----------------------------------------------------------------------===//
1755 //===----------------------------------------------------------------------===//
1757 // TFRI64 - assembly mapped.
1758 let isReMaterializable = 1 in
1759 def TFRI64 : ALU64_rr<(outs DoubleRegs:$dst), (ins s8Imm64:$src1),
1761 [(set (i64 DoubleRegs:$dst), s8Imm64Pred:$src1)]>;
1763 // Pseudo instruction to encode a set of conditional transfers.
1764 // This instruction is used instead of a mux and trades-off codesize
1765 // for performance. We conduct this transformation optimistically in
1766 // the hope that these instructions get promoted to dot-new transfers.
1767 let AddedComplexity = 100, isPredicated = 1 in
1768 def TFR_condset_rr : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1,
1771 "Error; should not emit",
1772 [(set (i32 IntRegs:$dst),
1773 (i32 (select (i1 PredRegs:$src1),
1774 (i32 IntRegs:$src2),
1775 (i32 IntRegs:$src3))))]>;
1776 let AddedComplexity = 100, isPredicated = 1 in
1777 def TFR_condset_ri : ALU32_rr<(outs IntRegs:$dst),
1778 (ins PredRegs:$src1, IntRegs:$src2, s12Imm:$src3),
1779 "Error; should not emit",
1780 [(set (i32 IntRegs:$dst),
1781 (i32 (select (i1 PredRegs:$src1), (i32 IntRegs:$src2),
1782 s12ImmPred:$src3)))]>;
1784 let AddedComplexity = 100, isPredicated = 1 in
1785 def TFR_condset_ir : ALU32_rr<(outs IntRegs:$dst),
1786 (ins PredRegs:$src1, s12Imm:$src2, IntRegs:$src3),
1787 "Error; should not emit",
1788 [(set (i32 IntRegs:$dst),
1789 (i32 (select (i1 PredRegs:$src1), s12ImmPred:$src2,
1790 (i32 IntRegs:$src3))))]>;
1792 let AddedComplexity = 100, isPredicated = 1 in
1793 def TFR_condset_ii : ALU32_rr<(outs IntRegs:$dst),
1794 (ins PredRegs:$src1, s12Imm:$src2, s12Imm:$src3),
1795 "Error; should not emit",
1796 [(set (i32 IntRegs:$dst),
1797 (i32 (select (i1 PredRegs:$src1), s12ImmPred:$src2,
1798 s12ImmPred:$src3)))]>;
1800 // Generate frameindex addresses.
1801 let isReMaterializable = 1 in
1802 def TFR_FI : ALU32_ri<(outs IntRegs:$dst), (ins FrameIndex:$src1),
1803 "$dst = add($src1)",
1804 [(set (i32 IntRegs:$dst), ADDRri:$src1)]>;
1809 let neverHasSideEffects = 1, Defs = [SA0, LC0] in {
1810 def LOOP0_i : CRInst<(outs), (ins brtarget:$offset, u10Imm:$src2),
1811 "loop0($offset, #$src2)",
1815 let neverHasSideEffects = 1, Defs = [SA0, LC0] in {
1816 def LOOP0_r : CRInst<(outs), (ins brtarget:$offset, IntRegs:$src2),
1817 "loop0($offset, $src2)",
1821 let isBranch = 1, isTerminator = 1, neverHasSideEffects = 1,
1822 Defs = [PC, LC0], Uses = [SA0, LC0] in {
1823 def ENDLOOP0 : Endloop<(outs), (ins brtarget:$offset),
1828 // Support for generating global address.
1829 // Taken from X86InstrInfo.td.
1830 def SDTHexagonCONST32 : SDTypeProfile<1, 1, [
1834 def HexagonCONST32 : SDNode<"HexagonISD::CONST32", SDTHexagonCONST32>;
1835 def HexagonCONST32_GP : SDNode<"HexagonISD::CONST32_GP", SDTHexagonCONST32>;
1837 // HI/LO Instructions
1838 let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
1839 def LO : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$global),
1840 "$dst.l = #LO($global)",
1843 let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
1844 def HI : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$global),
1845 "$dst.h = #HI($global)",
1848 let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
1849 def LOi : ALU32_ri<(outs IntRegs:$dst), (ins i32imm:$imm_value),
1850 "$dst.l = #LO($imm_value)",
1854 let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
1855 def HIi : ALU32_ri<(outs IntRegs:$dst), (ins i32imm:$imm_value),
1856 "$dst.h = #HI($imm_value)",
1859 let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
1860 def LO_jt : ALU32_ri<(outs IntRegs:$dst), (ins jumptablebase:$jt),
1861 "$dst.l = #LO($jt)",
1864 let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
1865 def HI_jt : ALU32_ri<(outs IntRegs:$dst), (ins jumptablebase:$jt),
1866 "$dst.h = #HI($jt)",
1870 let isReMaterializable = 1, isMoveImm = 1, neverHasSideEffects = 1 in
1871 def LO_label : ALU32_ri<(outs IntRegs:$dst), (ins bblabel:$label),
1872 "$dst.l = #LO($label)",
1875 let isReMaterializable = 1, isMoveImm = 1 , neverHasSideEffects = 1 in
1876 def HI_label : ALU32_ri<(outs IntRegs:$dst), (ins bblabel:$label),
1877 "$dst.h = #HI($label)",
1880 // This pattern is incorrect. When we add small data, we should change
1881 // this pattern to use memw(#foo).
1882 // This is for sdata.
1883 let isMoveImm = 1 in
1884 def CONST32 : LDInst<(outs IntRegs:$dst), (ins globaladdress:$global),
1885 "$dst = CONST32(#$global)",
1886 [(set (i32 IntRegs:$dst),
1887 (load (HexagonCONST32 tglobaltlsaddr:$global)))]>;
1889 // This is for non-sdata.
1890 let isReMaterializable = 1, isMoveImm = 1 in
1891 def CONST32_set : LDInst2<(outs IntRegs:$dst), (ins globaladdress:$global),
1892 "$dst = CONST32(#$global)",
1893 [(set (i32 IntRegs:$dst),
1894 (HexagonCONST32 tglobaladdr:$global))]>;
1896 let isReMaterializable = 1, isMoveImm = 1 in
1897 def CONST32_set_jt : LDInst2<(outs IntRegs:$dst), (ins jumptablebase:$jt),
1898 "$dst = CONST32(#$jt)",
1899 [(set (i32 IntRegs:$dst),
1900 (HexagonCONST32 tjumptable:$jt))]>;
1902 let isReMaterializable = 1, isMoveImm = 1 in
1903 def CONST32GP_set : LDInst2<(outs IntRegs:$dst), (ins globaladdress:$global),
1904 "$dst = CONST32(#$global)",
1905 [(set (i32 IntRegs:$dst),
1906 (HexagonCONST32_GP tglobaladdr:$global))]>;
1908 let isReMaterializable = 1, isMoveImm = 1 in
1909 def CONST32_Int_Real : LDInst2<(outs IntRegs:$dst), (ins i32imm:$global),
1910 "$dst = CONST32(#$global)",
1911 [(set (i32 IntRegs:$dst), imm:$global) ]>;
1913 // Map BlockAddress lowering to CONST32_Int_Real
1914 def : Pat<(HexagonCONST32_GP tblockaddress:$addr),
1915 (CONST32_Int_Real tblockaddress:$addr)>;
1917 let isReMaterializable = 1, isMoveImm = 1 in
1918 def CONST32_Label : LDInst2<(outs IntRegs:$dst), (ins bblabel:$label),
1919 "$dst = CONST32($label)",
1920 [(set (i32 IntRegs:$dst), (HexagonCONST32 bbl:$label))]>;
1922 let isReMaterializable = 1, isMoveImm = 1 in
1923 def CONST64_Int_Real : LDInst2<(outs DoubleRegs:$dst), (ins i64imm:$global),
1924 "$dst = CONST64(#$global)",
1925 [(set (i64 DoubleRegs:$dst), imm:$global) ]>;
1927 def TFR_PdFalse : SInst<(outs PredRegs:$dst), (ins),
1928 "$dst = xor($dst, $dst)",
1929 [(set (i1 PredRegs:$dst), 0)]>;
1931 def MPY_trsext : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1932 "$dst = mpy($src1, $src2)",
1933 [(set (i32 IntRegs:$dst),
1934 (trunc (i64 (srl (i64 (mul (i64 (sext (i32 IntRegs:$src1))),
1935 (i64 (sext (i32 IntRegs:$src2))))),
1938 // Pseudo instructions.
1939 def SDT_SPCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
1941 def SDT_SPCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
1942 SDTCisVT<1, i32> ]>;
1944 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeqEnd,
1945 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
1947 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeqStart,
1948 [SDNPHasChain, SDNPOutGlue]>;
1950 def SDT_SPCall : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
1952 def call : SDNode<"HexagonISD::CALL", SDT_SPCall,
1953 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, SDNPVariadic]>;
1955 // For tailcalls a HexagonTCRet SDNode has 3 SDNode Properties - a chain,
1956 // Optional Flag and Variable Arguments.
1957 // Its 1 Operand has pointer type.
1958 def HexagonTCRet : SDNode<"HexagonISD::TC_RETURN", SDT_SPCall,
1959 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
1961 let Defs = [R29, R30], Uses = [R31, R30, R29] in {
1962 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
1963 "Should never be emitted",
1964 [(callseq_start timm:$amt)]>;
1967 let Defs = [R29, R30, R31], Uses = [R29] in {
1968 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
1969 "Should never be emitted",
1970 [(callseq_end timm:$amt1, timm:$amt2)]>;
1973 let isCall = 1, neverHasSideEffects = 1,
1974 Defs = [D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10,
1975 R22, R23, R28, R31, P0, P1, P2, P3, LC0, LC1, SA0, SA1] in {
1976 def CALL : JInst<(outs), (ins calltarget:$dst),
1980 // Call subroutine from register.
1981 let isCall = 1, neverHasSideEffects = 1,
1982 Defs = [D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10,
1983 R22, R23, R28, R31, P0, P1, P2, P3, LC0, LC1, SA0, SA1] in {
1984 def CALLR : JRInst<(outs), (ins IntRegs:$dst),
1990 let isCall = 1, isBarrier = 1, isReturn = 1, isTerminator = 1 in {
1991 def TCRETURNtg : JInst<(outs), (ins calltarget:$dst),
1992 "jump $dst // TAILCALL", []>;
1994 let isCall = 1, isBarrier = 1, isReturn = 1, isTerminator = 1 in {
1995 def TCRETURNtext : JInst<(outs), (ins calltarget:$dst),
1996 "jump $dst // TAILCALL", []>;
1999 let isCall = 1, isBarrier = 1, isReturn = 1, isTerminator = 1 in {
2000 def TCRETURNR : JInst<(outs), (ins IntRegs:$dst),
2001 "jumpr $dst // TAILCALL", []>;
2003 // Map call instruction.
2004 def : Pat<(call (i32 IntRegs:$dst)),
2005 (CALLR (i32 IntRegs:$dst))>, Requires<[HasV2TOnly]>;
2006 def : Pat<(call tglobaladdr:$dst),
2007 (CALL tglobaladdr:$dst)>, Requires<[HasV2TOnly]>;
2008 def : Pat<(call texternalsym:$dst),
2009 (CALL texternalsym:$dst)>, Requires<[HasV2TOnly]>;
2011 def : Pat<(HexagonTCRet tglobaladdr:$dst),
2012 (TCRETURNtg tglobaladdr:$dst)>;
2013 def : Pat<(HexagonTCRet texternalsym:$dst),
2014 (TCRETURNtext texternalsym:$dst)>;
2015 def : Pat<(HexagonTCRet (i32 IntRegs:$dst)),
2016 (TCRETURNR (i32 IntRegs:$dst))>;
2018 // Atomic load and store support
2019 // 8 bit atomic load
2020 def : Pat<(atomic_load_8 ADDRriS11_0:$src1),
2021 (i32 (LDriub ADDRriS11_0:$src1))>;
2023 def : Pat<(atomic_load_8 (add (i32 IntRegs:$src1), s11_0ImmPred:$offset)),
2024 (i32 (LDriub_indexed (i32 IntRegs:$src1), s11_0ImmPred:$offset))>;
2026 // 16 bit atomic load
2027 def : Pat<(atomic_load_16 ADDRriS11_1:$src1),
2028 (i32 (LDriuh ADDRriS11_1:$src1))>;
2030 def : Pat<(atomic_load_16 (add (i32 IntRegs:$src1), s11_1ImmPred:$offset)),
2031 (i32 (LDriuh_indexed (i32 IntRegs:$src1), s11_1ImmPred:$offset))>;
2033 def : Pat<(atomic_load_32 ADDRriS11_2:$src1),
2034 (i32 (LDriw ADDRriS11_2:$src1))>;
2036 def : Pat<(atomic_load_32 (add (i32 IntRegs:$src1), s11_2ImmPred:$offset)),
2037 (i32 (LDriw_indexed (i32 IntRegs:$src1), s11_2ImmPred:$offset))>;
2039 // 64 bit atomic load
2040 def : Pat<(atomic_load_64 ADDRriS11_3:$src1),
2041 (i64 (LDrid ADDRriS11_3:$src1))>;
2043 def : Pat<(atomic_load_64 (add (i32 IntRegs:$src1), s11_3ImmPred:$offset)),
2044 (i64 (LDrid_indexed (i32 IntRegs:$src1), s11_3ImmPred:$offset))>;
2047 def : Pat<(atomic_store_8 ADDRriS11_0:$src2, (i32 IntRegs:$src1)),
2048 (STrib ADDRriS11_0:$src2, (i32 IntRegs:$src1))>;
2050 def : Pat<(atomic_store_8 (add (i32 IntRegs:$src2), s11_0ImmPred:$offset),
2051 (i32 IntRegs:$src1)),
2052 (STrib_indexed (i32 IntRegs:$src2), s11_0ImmPred:$offset,
2053 (i32 IntRegs:$src1))>;
2056 def : Pat<(atomic_store_16 ADDRriS11_1:$src2, (i32 IntRegs:$src1)),
2057 (STrih ADDRriS11_1:$src2, (i32 IntRegs:$src1))>;
2059 def : Pat<(atomic_store_16 (i32 IntRegs:$src1),
2060 (add (i32 IntRegs:$src2), s11_1ImmPred:$offset)),
2061 (STrih_indexed (i32 IntRegs:$src2), s11_1ImmPred:$offset,
2062 (i32 IntRegs:$src1))>;
2064 def : Pat<(atomic_store_32 ADDRriS11_2:$src2, (i32 IntRegs:$src1)),
2065 (STriw ADDRriS11_2:$src2, (i32 IntRegs:$src1))>;
2067 def : Pat<(atomic_store_32 (add (i32 IntRegs:$src2), s11_2ImmPred:$offset),
2068 (i32 IntRegs:$src1)),
2069 (STriw_indexed (i32 IntRegs:$src2), s11_2ImmPred:$offset,
2070 (i32 IntRegs:$src1))>;
2075 def : Pat<(atomic_store_64 ADDRriS11_3:$src2, (i64 DoubleRegs:$src1)),
2076 (STrid ADDRriS11_3:$src2, (i64 DoubleRegs:$src1))>;
2078 def : Pat<(atomic_store_64 (add (i32 IntRegs:$src2), s11_3ImmPred:$offset),
2079 (i64 DoubleRegs:$src1)),
2080 (STrid_indexed (i32 IntRegs:$src2), s11_3ImmPred:$offset,
2081 (i64 DoubleRegs:$src1))>;
2083 // Map from r0 = and(r1, 65535) to r0 = zxth(r1)
2084 def : Pat <(and (i32 IntRegs:$src1), 65535),
2085 (ZXTH (i32 IntRegs:$src1))>;
2087 // Map from r0 = and(r1, 255) to r0 = zxtb(r1).
2088 def : Pat <(and (i32 IntRegs:$src1), 255),
2089 (ZXTB (i32 IntRegs:$src1))>;
2091 // Map Add(p1, true) to p1 = not(p1).
2092 // Add(p1, false) should never be produced,
2093 // if it does, it got to be mapped to NOOP.
2094 def : Pat <(add (i1 PredRegs:$src1), -1),
2095 (NOT_p (i1 PredRegs:$src1))>;
2097 // Map from p0 = setlt(r0, r1) r2 = mux(p0, r3, r4) =>
2098 // p0 = cmp.lt(r0, r1), r0 = mux(p0, r2, r1).
2099 // cmp.lt(r0, r1) -> cmp.gt(r1, r0)
2100 def : Pat <(select (i1 (setlt (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2101 (i32 IntRegs:$src3),
2102 (i32 IntRegs:$src4)),
2103 (i32 (TFR_condset_rr (CMPGTrr (i32 IntRegs:$src2), (i32 IntRegs:$src1)),
2104 (i32 IntRegs:$src4), (i32 IntRegs:$src3)))>,
2105 Requires<[HasV2TOnly]>;
2107 // Map from p0 = pnot(p0); r0 = mux(p0, #i, #j) => r0 = mux(p0, #j, #i).
2108 def : Pat <(select (not (i1 PredRegs:$src1)), s8ImmPred:$src2, s8ImmPred:$src3),
2109 (i32 (TFR_condset_ii (i1 PredRegs:$src1), s8ImmPred:$src3,
2112 // Map from p0 = pnot(p0); r0 = select(p0, #i, r1)
2113 // => r0 = TFR_condset_ri(p0, r1, #i)
2114 def : Pat <(select (not (i1 PredRegs:$src1)), s12ImmPred:$src2,
2115 (i32 IntRegs:$src3)),
2116 (i32 (TFR_condset_ri (i1 PredRegs:$src1), (i32 IntRegs:$src3),
2117 s12ImmPred:$src2))>;
2119 // Map from p0 = pnot(p0); r0 = mux(p0, r1, #i)
2120 // => r0 = TFR_condset_ir(p0, #i, r1)
2121 def : Pat <(select (not (i1 PredRegs:$src1)), IntRegs:$src2, s12ImmPred:$src3),
2122 (i32 (TFR_condset_ir (i1 PredRegs:$src1), s12ImmPred:$src3,
2123 (i32 IntRegs:$src2)))>;
2125 // Map from p0 = pnot(p0); if (p0) jump => if (!p0) jump.
2126 def : Pat <(brcond (not (i1 PredRegs:$src1)), bb:$offset),
2127 (JMP_cNot (i1 PredRegs:$src1), bb:$offset)>;
2129 // Map from p2 = pnot(p2); p1 = and(p0, p2) => p1 = and(p0, !p2).
2130 def : Pat <(and (i1 PredRegs:$src1), (not (i1 PredRegs:$src2))),
2131 (i1 (AND_pnotp (i1 PredRegs:$src1), (i1 PredRegs:$src2)))>;
2134 let AddedComplexity = 100 in
2135 def : Pat <(i64 (zextloadi1 (HexagonCONST32 tglobaladdr:$global))),
2136 (i64 (COMBINE_rr (TFRI 0),
2137 (LDriub_indexed (CONST32_set tglobaladdr:$global), 0)))>,
2140 // Map from i1 loads to 32 bits. This assumes that the i1* is byte aligned.
2141 let AddedComplexity = 10 in
2142 def : Pat <(i32 (zextloadi1 ADDRriS11_0:$addr)),
2143 (i32 (AND_rr (i32 (LDrib ADDRriS11_0:$addr)), (TFRI 0x1)))>;
2145 // Map from Rdd = sign_extend_inreg(Rss, i32) -> Rdd = SXTW(Rss.lo).
2146 def : Pat <(i64 (sext_inreg (i64 DoubleRegs:$src1), i32)),
2147 (i64 (SXTW (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_loreg))))>;
2149 // Map from Rdd = sign_extend_inreg(Rss, i16) -> Rdd = SXTW(SXTH(Rss.lo)).
2150 def : Pat <(i64 (sext_inreg (i64 DoubleRegs:$src1), i16)),
2151 (i64 (SXTW (i32 (SXTH (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
2152 subreg_loreg))))))>;
2154 // Map from Rdd = sign_extend_inreg(Rss, i8) -> Rdd = SXTW(SXTB(Rss.lo)).
2155 def : Pat <(i64 (sext_inreg (i64 DoubleRegs:$src1), i8)),
2156 (i64 (SXTW (i32 (SXTB (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
2157 subreg_loreg))))))>;
2159 // We want to prevent emitting pnot's as much as possible.
2160 // Map brcond with an unsupported setcc to a JMP_cNot.
2161 def : Pat <(brcond (i1 (setne (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2163 (JMP_cNot (CMPEQrr (i32 IntRegs:$src1), (i32 IntRegs:$src2)),
2166 def : Pat <(brcond (i1 (setne (i32 IntRegs:$src1), s10ImmPred:$src2)),
2168 (JMP_cNot (CMPEQri (i32 IntRegs:$src1), s10ImmPred:$src2), bb:$offset)>;
2170 def : Pat <(brcond (i1 (setne (i1 PredRegs:$src1), (i1 -1))), bb:$offset),
2171 (JMP_cNot (i1 PredRegs:$src1), bb:$offset)>;
2173 def : Pat <(brcond (i1 (setne (i1 PredRegs:$src1), (i1 0))), bb:$offset),
2174 (JMP_c (i1 PredRegs:$src1), bb:$offset)>;
2176 // cmp.lt(Rs, Imm) -> !cmp.ge(Rs, Imm) -> !cmp.gt(Rs, Imm-1)
2177 def : Pat <(brcond (i1 (setlt (i32 IntRegs:$src1), s8ImmPred:$src2)),
2179 (JMP_cNot (CMPGTri (i32 IntRegs:$src1),
2180 (DEC_CONST_SIGNED s8ImmPred:$src2)), bb:$offset)>;
2182 // cmp.lt(r0, r1) -> cmp.gt(r1, r0)
2183 def : Pat <(brcond (i1 (setlt (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2185 (JMP_c (CMPGTrr (i32 IntRegs:$src2), (i32 IntRegs:$src1)), bb:$offset)>;
2187 def : Pat <(brcond (i1 (setuge (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2189 (JMP_cNot (CMPGTU64rr (i64 DoubleRegs:$src2), (i64 DoubleRegs:$src1)),
2192 def : Pat <(brcond (i1 (setule (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2194 (JMP_cNot (CMPGTUrr (i32 IntRegs:$src1), (i32 IntRegs:$src2)),
2197 def : Pat <(brcond (i1 (setule (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2199 (JMP_cNot (CMPGTU64rr (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2)),
2202 // Map from a 64-bit select to an emulated 64-bit mux.
2203 // Hexagon does not support 64-bit MUXes; so emulate with combines.
2204 def : Pat <(select (i1 PredRegs:$src1), (i64 DoubleRegs:$src2),
2205 (i64 DoubleRegs:$src3)),
2206 (i64 (COMBINE_rr (i32 (MUX_rr (i1 PredRegs:$src1),
2207 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
2209 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src3),
2211 (i32 (MUX_rr (i1 PredRegs:$src1),
2212 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
2214 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src3),
2215 subreg_loreg))))))>;
2217 // Map from a 1-bit select to logical ops.
2218 // From LegalizeDAG.cpp: (B1 ? B2 : B3) <=> (B1 & B2)|(!B1&B3).
2219 def : Pat <(select (i1 PredRegs:$src1), (i1 PredRegs:$src2),
2220 (i1 PredRegs:$src3)),
2221 (OR_pp (AND_pp (i1 PredRegs:$src1), (i1 PredRegs:$src2)),
2222 (AND_pp (NOT_p (i1 PredRegs:$src1)), (i1 PredRegs:$src3)))>;
2224 // Map Pd = load(addr) -> Rs = load(addr); Pd = Rs.
2225 def : Pat<(i1 (load ADDRriS11_2:$addr)),
2226 (i1 (TFR_PdRs (i32 (LDrib ADDRriS11_2:$addr))))>;
2228 // Map for truncating from 64 immediates to 32 bit immediates.
2229 def : Pat<(i32 (trunc (i64 DoubleRegs:$src))),
2230 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src), subreg_loreg))>;
2232 // Map for truncating from i64 immediates to i1 bit immediates.
2233 def : Pat<(i1 (trunc (i64 DoubleRegs:$src))),
2234 (i1 (TFR_PdRs (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
2237 // Map memb(Rs) = Rdd -> memb(Rs) = Rt.
2238 def : Pat<(truncstorei8 (i64 DoubleRegs:$src), ADDRriS11_0:$addr),
2239 (STrib ADDRriS11_0:$addr, (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
2242 // Map memh(Rs) = Rdd -> memh(Rs) = Rt.
2243 def : Pat<(truncstorei16 (i64 DoubleRegs:$src), ADDRriS11_0:$addr),
2244 (STrih ADDRriS11_0:$addr, (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
2246 // Map memw(Rs) = Rdd -> memw(Rs) = Rt
2247 def : Pat<(truncstorei32 (i64 DoubleRegs:$src), ADDRriS11_0:$addr),
2248 (STriw ADDRriS11_0:$addr, (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
2251 // Map memw(Rs) = Rdd -> memw(Rs) = Rt.
2252 def : Pat<(truncstorei32 (i64 DoubleRegs:$src), ADDRriS11_0:$addr),
2253 (STriw ADDRriS11_0:$addr, (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
2256 // Map from i1 = constant<-1>; memw(addr) = i1 -> r0 = 1; memw(addr) = r0.
2257 def : Pat<(store (i1 -1), ADDRriS11_2:$addr),
2258 (STrib ADDRriS11_2:$addr, (TFRI 1))>;
2261 // Map from i1 = constant<-1>; store i1 -> r0 = 1; store r0.
2262 def : Pat<(store (i1 -1), ADDRriS11_2:$addr),
2263 (STrib ADDRriS11_2:$addr, (TFRI 1))>;
2265 // Map from memb(Rs) = Pd -> Rt = mux(Pd, #0, #1); store Rt.
2266 def : Pat<(store (i1 PredRegs:$src1), ADDRriS11_2:$addr),
2267 (STrib ADDRriS11_2:$addr, (i32 (MUX_ii (i1 PredRegs:$src1), 1, 0)) )>;
2269 // Map Rdd = anyext(Rs) -> Rdd = sxtw(Rs).
2270 // Hexagon_TODO: We can probably use combine but that will cost 2 instructions.
2271 // Better way to do this?
2272 def : Pat<(i64 (anyext (i32 IntRegs:$src1))),
2273 (i64 (SXTW (i32 IntRegs:$src1)))>;
2275 // Map cmple -> cmpgt.
2276 // rs <= rt -> !(rs > rt).
2277 def : Pat<(i1 (setle (i32 IntRegs:$src1), s10ExtPred:$src2)),
2278 (i1 (NOT_p (CMPGTri (i32 IntRegs:$src1), s10ExtPred:$src2)))>;
2280 // rs <= rt -> !(rs > rt).
2281 def : Pat<(i1 (setle (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2282 (i1 (NOT_p (CMPGTrr (i32 IntRegs:$src1), (i32 IntRegs:$src2))))>;
2284 // Rss <= Rtt -> !(Rss > Rtt).
2285 def : Pat<(i1 (setle (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2286 (i1 (NOT_p (CMPGT64rr (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))))>;
2288 // Map cmpne -> cmpeq.
2289 // Hexagon_TODO: We should improve on this.
2290 // rs != rt -> !(rs == rt).
2291 def : Pat <(i1 (setne (i32 IntRegs:$src1), s10ExtPred:$src2)),
2292 (i1 (NOT_p(i1 (CMPEQri (i32 IntRegs:$src1), s10ExtPred:$src2))))>;
2294 // Map cmpne(Rs) -> !cmpeqe(Rs).
2295 // rs != rt -> !(rs == rt).
2296 def : Pat <(i1 (setne (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2297 (i1 (NOT_p (i1 (CMPEQrr (i32 IntRegs:$src1), (i32 IntRegs:$src2)))))>;
2299 // Convert setne back to xor for hexagon since we compute w/ pred registers.
2300 def : Pat <(i1 (setne (i1 PredRegs:$src1), (i1 PredRegs:$src2))),
2301 (i1 (XOR_pp (i1 PredRegs:$src1), (i1 PredRegs:$src2)))>;
2303 // Map cmpne(Rss) -> !cmpew(Rss).
2304 // rs != rt -> !(rs == rt).
2305 def : Pat <(i1 (setne (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2306 (i1 (NOT_p (i1 (CMPEHexagon4rr (i64 DoubleRegs:$src1),
2307 (i64 DoubleRegs:$src2)))))>;
2309 // Map cmpge(Rs, Rt) -> !(cmpgt(Rs, Rt).
2310 // rs >= rt -> !(rt > rs).
2311 def : Pat <(i1 (setge (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2312 (i1 (NOT_p (i1 (CMPGTrr (i32 IntRegs:$src2), (i32 IntRegs:$src1)))))>;
2314 // cmpge(Rs, Imm) -> cmpgt(Rs, Imm-1)
2315 def : Pat <(i1 (setge (i32 IntRegs:$src1), s8ExtPred:$src2)),
2316 (i1 (CMPGTri (i32 IntRegs:$src1), (DEC_CONST_SIGNED s8ExtPred:$src2)))>;
2318 // Map cmpge(Rss, Rtt) -> !cmpgt(Rtt, Rss).
2319 // rss >= rtt -> !(rtt > rss).
2320 def : Pat <(i1 (setge (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2321 (i1 (NOT_p (i1 (CMPGT64rr (i64 DoubleRegs:$src2),
2322 (i64 DoubleRegs:$src1)))))>;
2324 // Map cmplt(Rs, Imm) -> !cmpge(Rs, Imm).
2325 // !cmpge(Rs, Imm) -> !cmpgt(Rs, Imm-1).
2326 // rs < rt -> !(rs >= rt).
2327 def : Pat <(i1 (setlt (i32 IntRegs:$src1), s8ExtPred:$src2)),
2328 (i1 (NOT_p (CMPGTri (i32 IntRegs:$src1), (DEC_CONST_SIGNED s8ExtPred:$src2))))>;
2330 // Map cmplt(Rs, Rt) -> cmpgt(Rt, Rs).
2331 // rs < rt -> rt > rs.
2332 // We can let assembler map it, or we can do in the compiler itself.
2333 def : Pat <(i1 (setlt (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2334 (i1 (CMPGTrr (i32 IntRegs:$src2), (i32 IntRegs:$src1)))>;
2336 // Map cmplt(Rss, Rtt) -> cmpgt(Rtt, Rss).
2337 // rss < rtt -> (rtt > rss).
2338 def : Pat <(i1 (setlt (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2339 (i1 (CMPGT64rr (i64 DoubleRegs:$src2), (i64 DoubleRegs:$src1)))>;
2341 // Map from cmpltu(Rs, Rd) -> cmpgtu(Rd, Rs)
2342 // rs < rt -> rt > rs.
2343 // We can let assembler map it, or we can do in the compiler itself.
2344 def : Pat <(i1 (setult (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2345 (i1 (CMPGTUrr (i32 IntRegs:$src2), (i32 IntRegs:$src1)))>;
2347 // Map from cmpltu(Rss, Rdd) -> cmpgtu(Rdd, Rss).
2348 // rs < rt -> rt > rs.
2349 def : Pat <(i1 (setult (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2350 (i1 (CMPGTU64rr (i64 DoubleRegs:$src2), (i64 DoubleRegs:$src1)))>;
2352 // Generate cmpgeu(Rs, #0) -> cmpeq(Rs, Rs)
2353 def : Pat <(i1 (setuge (i32 IntRegs:$src1), 0)),
2354 (i1 (CMPEQrr (i32 IntRegs:$src1), (i32 IntRegs:$src1)))>;
2356 // Generate cmpgeu(Rs, #u8) -> cmpgtu(Rs, #u8 -1)
2357 def : Pat <(i1 (setuge (i32 IntRegs:$src1), u8ExtPred:$src2)),
2358 (i1 (CMPGTUri (i32 IntRegs:$src1), (DEC_CONST_UNSIGNED u8ExtPred:$src2)))>;
2360 // Generate cmpgtu(Rs, #u9)
2361 def : Pat <(i1 (setugt (i32 IntRegs:$src1), u9ExtPred:$src2)),
2362 (i1 (CMPGTUri (i32 IntRegs:$src1), u9ExtPred:$src2))>;
2364 // Map from Rs >= Rt -> !(Rt > Rs).
2365 // rs >= rt -> !(rt > rs).
2366 def : Pat <(i1 (setuge (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2367 (i1 (NOT_p (CMPGTUrr (i32 IntRegs:$src2), (i32 IntRegs:$src1))))>;
2369 // Map from Rs >= Rt -> !(Rt > Rs).
2370 // rs >= rt -> !(rt > rs).
2371 def : Pat <(i1 (setuge (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2372 (i1 (NOT_p (CMPGTU64rr (i64 DoubleRegs:$src2), (i64 DoubleRegs:$src1))))>;
2374 // Map from cmpleu(Rs, Rt) -> !cmpgtu(Rs, Rt).
2375 // Map from (Rs <= Rt) -> !(Rs > Rt).
2376 def : Pat <(i1 (setule (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
2377 (i1 (NOT_p (CMPGTUrr (i32 IntRegs:$src1), (i32 IntRegs:$src2))))>;
2379 // Map from cmpleu(Rss, Rtt) -> !cmpgtu(Rss, Rtt-1).
2380 // Map from (Rs <= Rt) -> !(Rs > Rt).
2381 def : Pat <(i1 (setule (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
2382 (i1 (NOT_p (CMPGTU64rr (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))))>;
2386 def : Pat <(i32 (sext (i1 PredRegs:$src1))),
2387 (i32 (MUX_ii (i1 PredRegs:$src1), -1, 0))>;
2390 def : Pat <(i64 (sext (i1 PredRegs:$src1))),
2391 (i64 (COMBINE_rr (TFRI -1), (MUX_ii (i1 PredRegs:$src1), -1, 0)))>;
2393 // Convert sign-extended load back to load and sign extend.
2395 def: Pat <(i64 (sextloadi8 ADDRriS11_0:$src1)),
2396 (i64 (SXTW (LDrib ADDRriS11_0:$src1)))>;
2398 // Convert any-extended load back to load and sign extend.
2400 def: Pat <(i64 (extloadi8 ADDRriS11_0:$src1)),
2401 (i64 (SXTW (LDrib ADDRriS11_0:$src1)))>;
2403 // Convert sign-extended load back to load and sign extend.
2405 def: Pat <(i64 (sextloadi16 ADDRriS11_1:$src1)),
2406 (i64 (SXTW (LDrih ADDRriS11_1:$src1)))>;
2408 // Convert sign-extended load back to load and sign extend.
2410 def: Pat <(i64 (sextloadi32 ADDRriS11_2:$src1)),
2411 (i64 (SXTW (LDriw ADDRriS11_2:$src1)))>;
2416 def : Pat <(i32 (zext (i1 PredRegs:$src1))),
2417 (i32 (MUX_ii (i1 PredRegs:$src1), 1, 0))>;
2420 def : Pat <(i64 (zext (i1 PredRegs:$src1))),
2421 (i64 (COMBINE_rr (TFRI 0), (MUX_ii (i1 PredRegs:$src1), 1, 0)))>,
2425 def : Pat <(i64 (zext (i32 IntRegs:$src1))),
2426 (i64 (COMBINE_rr (TFRI 0), (i32 IntRegs:$src1)))>,
2430 def: Pat <(i64 (zextloadi8 ADDRriS11_0:$src1)),
2431 (i64 (COMBINE_rr (TFRI 0), (LDriub ADDRriS11_0:$src1)))>,
2434 let AddedComplexity = 20 in
2435 def: Pat <(i64 (zextloadi8 (add (i32 IntRegs:$src1),
2436 s11_0ExtPred:$offset))),
2437 (i64 (COMBINE_rr (TFRI 0), (LDriub_indexed IntRegs:$src1,
2438 s11_0ExtPred:$offset)))>,
2442 def: Pat <(i64 (zextloadi1 ADDRriS11_0:$src1)),
2443 (i64 (COMBINE_rr (TFRI 0), (LDriub ADDRriS11_0:$src1)))>,
2446 let AddedComplexity = 20 in
2447 def: Pat <(i64 (zextloadi1 (add (i32 IntRegs:$src1),
2448 s11_0ExtPred:$offset))),
2449 (i64 (COMBINE_rr (TFRI 0), (LDriub_indexed IntRegs:$src1,
2450 s11_0ExtPred:$offset)))>,
2454 def: Pat <(i64 (zextloadi16 ADDRriS11_1:$src1)),
2455 (i64 (COMBINE_rr (TFRI 0), (LDriuh ADDRriS11_1:$src1)))>,
2458 let AddedComplexity = 20 in
2459 def: Pat <(i64 (zextloadi16 (add (i32 IntRegs:$src1),
2460 s11_1ExtPred:$offset))),
2461 (i64 (COMBINE_rr (TFRI 0), (LDriuh_indexed IntRegs:$src1,
2462 s11_1ExtPred:$offset)))>,
2466 def: Pat <(i64 (zextloadi32 ADDRriS11_2:$src1)),
2467 (i64 (COMBINE_rr (TFRI 0), (LDriw ADDRriS11_2:$src1)))>,
2470 let AddedComplexity = 100 in
2471 def: Pat <(i64 (zextloadi32 (i32 (add IntRegs:$src1, s11_2ExtPred:$offset)))),
2472 (i64 (COMBINE_rr (TFRI 0), (LDriw_indexed IntRegs:$src1,
2473 s11_2ExtPred:$offset)))>,
2476 let AddedComplexity = 10 in
2477 def: Pat <(i32 (zextloadi1 ADDRriS11_0:$src1)),
2478 (i32 (LDriw ADDRriS11_0:$src1))>;
2480 // Map from Rs = Pd to Pd = mux(Pd, #1, #0)
2481 def : Pat <(i32 (zext (i1 PredRegs:$src1))),
2482 (i32 (MUX_ii (i1 PredRegs:$src1), 1, 0))>;
2484 // Map from Rs = Pd to Pd = mux(Pd, #1, #0)
2485 def : Pat <(i32 (anyext (i1 PredRegs:$src1))),
2486 (i32 (MUX_ii (i1 PredRegs:$src1), 1, 0))>;
2488 // Map from Rss = Pd to Rdd = sxtw (mux(Pd, #1, #0))
2489 def : Pat <(i64 (anyext (i1 PredRegs:$src1))),
2490 (i64 (SXTW (i32 (MUX_ii (i1 PredRegs:$src1), 1, 0))))>;
2493 let AddedComplexity = 100 in
2494 def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh),
2496 (i64 (zextloadi32 (i32 (add IntRegs:$src2,
2497 s11_2ExtPred:$offset2)))))),
2498 (i64 (COMBINE_rr (EXTRACT_SUBREG (i64 DoubleRegs:$srcHigh), subreg_loreg),
2499 (LDriw_indexed IntRegs:$src2,
2500 s11_2ExtPred:$offset2)))>;
2502 def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh),
2504 (i64 (zextloadi32 ADDRriS11_2:$srcLow)))),
2505 (i64 (COMBINE_rr (EXTRACT_SUBREG (i64 DoubleRegs:$srcHigh), subreg_loreg),
2506 (LDriw ADDRriS11_2:$srcLow)))>;
2508 def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh),
2510 (i64 (zext (i32 IntRegs:$srcLow))))),
2511 (i64 (COMBINE_rr (EXTRACT_SUBREG (i64 DoubleRegs:$srcHigh), subreg_loreg),
2514 // Any extended 64-bit load.
2515 // anyext i32 -> i64
2516 def: Pat <(i64 (extloadi32 ADDRriS11_2:$src1)),
2517 (i64 (COMBINE_rr (TFRI 0), (LDriw ADDRriS11_2:$src1)))>,
2520 // When there is an offset we should prefer the pattern below over the pattern above.
2521 // The complexity of the above is 13 (gleaned from HexagonGenDAGIsel.inc)
2522 // So this complexity below is comfortably higher to allow for choosing the below.
2523 // If this is not done then we generate addresses such as
2524 // ********************************************
2525 // r1 = add (r0, #4)
2526 // r1 = memw(r1 + #0)
2528 // r1 = memw(r0 + #4)
2529 // ********************************************
2530 let AddedComplexity = 100 in
2531 def: Pat <(i64 (extloadi32 (i32 (add IntRegs:$src1, s11_2ExtPred:$offset)))),
2532 (i64 (COMBINE_rr (TFRI 0), (LDriw_indexed IntRegs:$src1,
2533 s11_2ExtPred:$offset)))>,
2536 // anyext i16 -> i64.
2537 def: Pat <(i64 (extloadi16 ADDRriS11_2:$src1)),
2538 (i64 (COMBINE_rr (TFRI 0), (LDrih ADDRriS11_2:$src1)))>,
2541 let AddedComplexity = 20 in
2542 def: Pat <(i64 (extloadi16 (add (i32 IntRegs:$src1),
2543 s11_1ExtPred:$offset))),
2544 (i64 (COMBINE_rr (TFRI 0), (LDrih_indexed IntRegs:$src1,
2545 s11_1ExtPred:$offset)))>,
2548 // Map from Rdd = zxtw(Rs) -> Rdd = combine(0, Rs).
2549 def : Pat<(i64 (zext (i32 IntRegs:$src1))),
2550 (i64 (COMBINE_rr (TFRI 0), (i32 IntRegs:$src1)))>,
2553 // Multiply 64-bit unsigned and use upper result.
2554 def : Pat <(mulhu (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2)),
2569 (COMBINE_rr (TFRI 0),
2575 (MPYU64 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
2577 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
2578 subreg_loreg)))), 32)),
2580 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg)),
2581 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_loreg)))),
2582 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_loreg)),
2583 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg)))),
2584 32)), subreg_loreg)))),
2585 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg)),
2586 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg))))>;
2588 // Multiply 64-bit signed and use upper result.
2589 def : Pat <(mulhs (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2)),
2593 (COMBINE_rr (TFRI 0),
2603 (COMBINE_rr (TFRI 0),
2609 (MPYU64 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
2611 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
2612 subreg_loreg)))), 32)),
2614 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg)),
2615 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_loreg)))),
2616 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_loreg)),
2617 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg)))),
2618 32)), subreg_loreg)))),
2619 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg)),
2620 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg))))>;
2622 // Hexagon specific ISD nodes.
2623 //def SDTHexagonADJDYNALLOC : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>]>;
2624 def SDTHexagonADJDYNALLOC : SDTypeProfile<1, 2,
2625 [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
2626 def Hexagon_ADJDYNALLOC : SDNode<"HexagonISD::ADJDYNALLOC",
2627 SDTHexagonADJDYNALLOC>;
2628 // Needed to tag these instructions for stack layout.
2629 let usesCustomInserter = 1 in
2630 def ADJDYNALLOC : ALU32_ri<(outs IntRegs:$dst), (ins IntRegs:$src1,
2632 "$dst = add($src1, #$src2)",
2633 [(set (i32 IntRegs:$dst),
2634 (Hexagon_ADJDYNALLOC (i32 IntRegs:$src1),
2635 s16ImmPred:$src2))]>;
2637 def SDTHexagonARGEXTEND : SDTypeProfile<1, 1, [SDTCisVT<0, i32>]>;
2638 def Hexagon_ARGEXTEND : SDNode<"HexagonISD::ARGEXTEND", SDTHexagonARGEXTEND>;
2639 def ARGEXTEND : ALU32_rr <(outs IntRegs:$dst), (ins IntRegs:$src1),
2641 [(set (i32 IntRegs:$dst),
2642 (Hexagon_ARGEXTEND (i32 IntRegs:$src1)))]>;
2644 let AddedComplexity = 100 in
2645 def : Pat<(i32 (sext_inreg (Hexagon_ARGEXTEND (i32 IntRegs:$src1)), i16)),
2646 (COPY (i32 IntRegs:$src1))>;
2648 def SDHexagonBR_JT: SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
2649 def HexagonBR_JT: SDNode<"HexagonISD::BR_JT", SDHexagonBR_JT, [SDNPHasChain]>;
2651 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in
2652 def BR_JT : JRInst<(outs), (ins IntRegs:$src),
2654 [(HexagonBR_JT (i32 IntRegs:$src))]>;
2656 let isBranch=1, isIndirectBranch=1, isTerminator=1 in
2657 def BRIND : JRInst<(outs), (ins IntRegs:$src),
2659 [(brind (i32 IntRegs:$src))]>;
2661 def HexagonWrapperJT: SDNode<"HexagonISD::WrapperJT", SDTIntUnaryOp>;
2663 def : Pat<(HexagonWrapperJT tjumptable:$dst),
2664 (i32 (CONST32_set_jt tjumptable:$dst))>;
2668 // Multi-class for logical operators :
2669 // Shift by immediate/register and accumulate/logical
2670 multiclass xtype_imm<string OpcStr, SDNode OpNode1, SDNode OpNode2> {
2671 def _ri : SInst_acc<(outs IntRegs:$dst),
2672 (ins IntRegs:$src1, IntRegs:$src2, u5Imm:$src3),
2673 !strconcat("$dst ", !strconcat(OpcStr, "($src2, #$src3)")),
2674 [(set (i32 IntRegs:$dst),
2675 (OpNode2 (i32 IntRegs:$src1),
2676 (OpNode1 (i32 IntRegs:$src2),
2677 u5ImmPred:$src3)))],
2680 def d_ri : SInst_acc<(outs DoubleRegs:$dst),
2681 (ins DoubleRegs:$src1, DoubleRegs:$src2, u6Imm:$src3),
2682 !strconcat("$dst ", !strconcat(OpcStr, "($src2, #$src3)")),
2683 [(set (i64 DoubleRegs:$dst), (OpNode2 (i64 DoubleRegs:$src1),
2684 (OpNode1 (i64 DoubleRegs:$src2), u6ImmPred:$src3)))],
2688 // Multi-class for logical operators :
2689 // Shift by register and accumulate/logical (32/64 bits)
2690 multiclass xtype_reg<string OpcStr, SDNode OpNode1, SDNode OpNode2> {
2691 def _rr : SInst_acc<(outs IntRegs:$dst),
2692 (ins IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
2693 !strconcat("$dst ", !strconcat(OpcStr, "($src2, $src3)")),
2694 [(set (i32 IntRegs:$dst),
2695 (OpNode2 (i32 IntRegs:$src1),
2696 (OpNode1 (i32 IntRegs:$src2),
2697 (i32 IntRegs:$src3))))],
2700 def d_rr : SInst_acc<(outs DoubleRegs:$dst),
2701 (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
2702 !strconcat("$dst ", !strconcat(OpcStr, "($src2, $src3)")),
2703 [(set (i64 DoubleRegs:$dst),
2704 (OpNode2 (i64 DoubleRegs:$src1),
2705 (OpNode1 (i64 DoubleRegs:$src2),
2706 (i32 IntRegs:$src3))))],
2711 multiclass basic_xtype_imm<string OpcStr, SDNode OpNode> {
2712 let AddedComplexity = 100 in
2713 defm _ADD : xtype_imm< !strconcat("+= ", OpcStr), OpNode, add>;
2714 defm _SUB : xtype_imm< !strconcat("-= ", OpcStr), OpNode, sub>;
2715 defm _AND : xtype_imm< !strconcat("&= ", OpcStr), OpNode, and>;
2716 defm _OR : xtype_imm< !strconcat("|= ", OpcStr), OpNode, or>;
2719 multiclass basic_xtype_reg<string OpcStr, SDNode OpNode> {
2720 let AddedComplexity = 100 in
2721 defm _ADD : xtype_reg< !strconcat("+= ", OpcStr), OpNode, add>;
2722 defm _SUB : xtype_reg< !strconcat("-= ", OpcStr), OpNode, sub>;
2723 defm _AND : xtype_reg< !strconcat("&= ", OpcStr), OpNode, and>;
2724 defm _OR : xtype_reg< !strconcat("|= ", OpcStr), OpNode, or>;
2727 multiclass xtype_xor_imm<string OpcStr, SDNode OpNode> {
2728 let AddedComplexity = 100 in
2729 defm _XOR : xtype_imm< !strconcat("^= ", OpcStr), OpNode, xor>;
2732 defm ASL : basic_xtype_imm<"asl", shl>, basic_xtype_reg<"asl", shl>,
2733 xtype_xor_imm<"asl", shl>;
2735 defm LSR : basic_xtype_imm<"lsr", srl>, basic_xtype_reg<"lsr", srl>,
2736 xtype_xor_imm<"lsr", srl>;
2738 defm ASR : basic_xtype_imm<"asr", sra>, basic_xtype_reg<"asr", sra>;
2739 defm LSL : basic_xtype_reg<"lsl", shl>;
2741 // Change the sign of the immediate for Rd=-mpyi(Rs,#u8)
2742 def : Pat <(mul (i32 IntRegs:$src1), (ineg n8ImmPred:$src2)),
2743 (i32 (MPYI_rin (i32 IntRegs:$src1), u8ImmPred:$src2))>;
2745 //===----------------------------------------------------------------------===//
2746 // V3 Instructions +
2747 //===----------------------------------------------------------------------===//
2749 include "HexagonInstrInfoV3.td"
2751 //===----------------------------------------------------------------------===//
2752 // V3 Instructions -
2753 //===----------------------------------------------------------------------===//
2755 //===----------------------------------------------------------------------===//
2756 // V4 Instructions +
2757 //===----------------------------------------------------------------------===//
2759 include "HexagonInstrInfoV4.td"
2761 //===----------------------------------------------------------------------===//
2762 // V4 Instructions -
2763 //===----------------------------------------------------------------------===//
2765 //===----------------------------------------------------------------------===//
2766 // V5 Instructions +
2767 //===----------------------------------------------------------------------===//
2769 include "HexagonInstrInfoV5.td"
2771 //===----------------------------------------------------------------------===//
2772 // V5 Instructions -
2773 //===----------------------------------------------------------------------===//