1 //===-- HexagonInstrInfo.cpp - Hexagon Instruction Information ------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Hexagon implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "HexagonInstrInfo.h"
16 #include "HexagonRegisterInfo.h"
17 #include "HexagonSubtarget.h"
18 #include "llvm/ADT/STLExtras.h"
19 #include "llvm/ADT/SmallVector.h"
20 #include "llvm/CodeGen/DFAPacketizer.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineMemOperand.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/PseudoSourceValue.h"
26 #include "llvm/Support/Debug.h"
27 #include "llvm/Support/MathExtras.h"
28 #include "llvm/Support/raw_ostream.h"
32 #define DEBUG_TYPE "hexagon-instrinfo"
34 #define GET_INSTRINFO_CTOR_DTOR
35 #define GET_INSTRMAP_INFO
36 #include "HexagonGenInstrInfo.inc"
37 #include "HexagonGenDFAPacketizer.inc"
40 /// Constants for Hexagon instructions.
42 const int Hexagon_MEMW_OFFSET_MAX = 4095;
43 const int Hexagon_MEMW_OFFSET_MIN = -4096;
44 const int Hexagon_MEMD_OFFSET_MAX = 8191;
45 const int Hexagon_MEMD_OFFSET_MIN = -8192;
46 const int Hexagon_MEMH_OFFSET_MAX = 2047;
47 const int Hexagon_MEMH_OFFSET_MIN = -2048;
48 const int Hexagon_MEMB_OFFSET_MAX = 1023;
49 const int Hexagon_MEMB_OFFSET_MIN = -1024;
50 const int Hexagon_ADDI_OFFSET_MAX = 32767;
51 const int Hexagon_ADDI_OFFSET_MIN = -32768;
52 const int Hexagon_MEMD_AUTOINC_MAX = 56;
53 const int Hexagon_MEMD_AUTOINC_MIN = -64;
54 const int Hexagon_MEMW_AUTOINC_MAX = 28;
55 const int Hexagon_MEMW_AUTOINC_MIN = -32;
56 const int Hexagon_MEMH_AUTOINC_MAX = 14;
57 const int Hexagon_MEMH_AUTOINC_MIN = -16;
58 const int Hexagon_MEMB_AUTOINC_MAX = 7;
59 const int Hexagon_MEMB_AUTOINC_MIN = -8;
61 // Pin the vtable to this file.
62 void HexagonInstrInfo::anchor() {}
64 HexagonInstrInfo::HexagonInstrInfo(HexagonSubtarget &ST)
65 : HexagonGenInstrInfo(Hexagon::ADJCALLSTACKDOWN, Hexagon::ADJCALLSTACKUP),
66 RI(), Subtarget(ST) {}
68 /// isLoadFromStackSlot - If the specified machine instruction is a direct
69 /// load from a stack slot, return the virtual or physical register number of
70 /// the destination along with the FrameIndex of the loaded stack slot. If
71 /// not, return 0. This predicate must return 0 if the instruction has
72 /// any side effects other than loading from the stack slot.
73 unsigned HexagonInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
74 int &FrameIndex) const {
77 switch (MI->getOpcode()) {
79 case Hexagon::L2_loadri_io:
80 case Hexagon::L2_loadrd_io:
81 case Hexagon::L2_loadrh_io:
82 case Hexagon::L2_loadrb_io:
83 case Hexagon::L2_loadrub_io:
84 if (MI->getOperand(2).isFI() &&
85 MI->getOperand(1).isImm() && (MI->getOperand(1).getImm() == 0)) {
86 FrameIndex = MI->getOperand(2).getIndex();
87 return MI->getOperand(0).getReg();
95 /// isStoreToStackSlot - If the specified machine instruction is a direct
96 /// store to a stack slot, return the virtual or physical register number of
97 /// the source reg along with the FrameIndex of the loaded stack slot. If
98 /// not, return 0. This predicate must return 0 if the instruction has
99 /// any side effects other than storing to the stack slot.
100 unsigned HexagonInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
101 int &FrameIndex) const {
102 switch (MI->getOpcode()) {
104 case Hexagon::S2_storeri_io:
105 case Hexagon::S2_storerd_io:
106 case Hexagon::S2_storerh_io:
107 case Hexagon::S2_storerb_io:
108 if (MI->getOperand(2).isFI() &&
109 MI->getOperand(1).isImm() && (MI->getOperand(1).getImm() == 0)) {
110 FrameIndex = MI->getOperand(0).getIndex();
111 return MI->getOperand(2).getReg();
118 // Find the hardware loop instruction used to set-up the specified loop.
119 // On Hexagon, we have two instructions used to set-up the hardware loop
120 // (LOOP0, LOOP1) with corresponding endloop (ENDLOOP0, ENDLOOP1) instructions
121 // to indicate the end of a loop.
122 static MachineInstr *
123 findLoopInstr(MachineBasicBlock *BB, int EndLoopOp,
124 SmallPtrSet<MachineBasicBlock *, 8> &Visited) {
127 if (EndLoopOp == Hexagon::ENDLOOP0) {
128 LOOPi = Hexagon::J2_loop0i;
129 LOOPr = Hexagon::J2_loop0r;
130 } else { // EndLoopOp == Hexagon::EndLOOP1
131 LOOPi = Hexagon::J2_loop1i;
132 LOOPr = Hexagon::J2_loop1r;
135 // The loop set-up instruction will be in a predecessor block
136 for (MachineBasicBlock::pred_iterator PB = BB->pred_begin(),
137 PE = BB->pred_end(); PB != PE; ++PB) {
138 // If this has been visited, already skip it.
139 if (!Visited.insert(*PB).second)
143 for (MachineBasicBlock::reverse_instr_iterator I = (*PB)->instr_rbegin(),
144 E = (*PB)->instr_rend(); I != E; ++I) {
145 int Opc = I->getOpcode();
146 if (Opc == LOOPi || Opc == LOOPr)
148 // We've reached a different loop, which means the loop0 has been removed.
149 if (Opc == EndLoopOp)
152 // Check the predecessors for the LOOP instruction.
153 MachineInstr *loop = findLoopInstr(*PB, EndLoopOp, Visited);
160 unsigned HexagonInstrInfo::InsertBranch(
161 MachineBasicBlock &MBB,MachineBasicBlock *TBB, MachineBasicBlock *FBB,
162 const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const {
164 Opcode_t BOpc = Hexagon::J2_jump;
165 Opcode_t BccOpc = Hexagon::J2_jumpt;
167 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
169 // Check if ReverseBranchCondition has asked to reverse this branch
170 // If we want to reverse the branch an odd number of times, we want
172 if (!Cond.empty() && Cond[0].isImm())
173 BccOpc = Cond[0].getImm();
177 // Due to a bug in TailMerging/CFG Optimization, we need to add a
178 // special case handling of a predicated jump followed by an
179 // unconditional jump. If not, Tail Merging and CFG Optimization go
180 // into an infinite loop.
181 MachineBasicBlock *NewTBB, *NewFBB;
182 SmallVector<MachineOperand, 4> Cond;
183 MachineInstr *Term = MBB.getFirstTerminator();
184 if (Term != MBB.end() && isPredicated(Term) &&
185 !AnalyzeBranch(MBB, NewTBB, NewFBB, Cond, false)) {
186 MachineBasicBlock *NextBB =
187 std::next(MachineFunction::iterator(&MBB));
188 if (NewTBB == NextBB) {
189 ReverseBranchCondition(Cond);
191 return InsertBranch(MBB, TBB, nullptr, Cond, DL);
194 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
195 } else if (isEndLoopN(Cond[0].getImm())) {
196 int EndLoopOp = Cond[0].getImm();
197 assert(Cond[1].isMBB());
198 // Since we're adding an ENDLOOP, there better be a LOOP instruction.
199 // Check for it, and change the BB target if needed.
200 SmallPtrSet<MachineBasicBlock *, 8> VisitedBBs;
201 MachineInstr *Loop = findLoopInstr(TBB, EndLoopOp, VisitedBBs);
202 assert(Loop != 0 && "Inserting an ENDLOOP without a LOOP");
203 Loop->getOperand(0).setMBB(TBB);
204 // Add the ENDLOOP after the finding the LOOP0.
205 BuildMI(&MBB, DL, get(EndLoopOp)).addMBB(TBB);
206 } else if (isNewValueJump(Cond[0].getImm())) {
207 assert((Cond.size() == 3) && "Only supporting rr/ri version of nvjump");
209 // (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset)
210 // (ins IntRegs:$src1, u5Imm:$src2, brtarget:$offset)
211 unsigned Flags1 = getUndefRegState(Cond[1].isUndef());
212 DEBUG(dbgs() << "\nInserting NVJump for BB#" << MBB.getNumber(););
213 if (Cond[2].isReg()) {
214 unsigned Flags2 = getUndefRegState(Cond[2].isUndef());
215 BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[1].getReg(), Flags1).
216 addReg(Cond[2].getReg(), Flags2).addMBB(TBB);
217 } else if(Cond[2].isImm()) {
218 BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[1].getReg(), Flags1).
219 addImm(Cond[2].getImm()).addMBB(TBB);
221 llvm_unreachable("Invalid condition for branching");
223 assert((Cond.size() == 2) && "Malformed cond vector");
224 const MachineOperand &RO = Cond[1];
225 unsigned Flags = getUndefRegState(RO.isUndef());
226 BuildMI(&MBB, DL, get(BccOpc)).addReg(RO.getReg(), Flags).addMBB(TBB);
230 assert((!Cond.empty()) &&
231 "Cond. cannot be empty when multiple branchings are required");
232 assert((!isNewValueJump(Cond[0].getImm())) &&
233 "NV-jump cannot be inserted with another branch");
234 // Special case for hardware loops. The condition is a basic block.
235 if (isEndLoopN(Cond[0].getImm())) {
236 int EndLoopOp = Cond[0].getImm();
237 assert(Cond[1].isMBB());
238 // Since we're adding an ENDLOOP, there better be a LOOP instruction.
239 // Check for it, and change the BB target if needed.
240 SmallPtrSet<MachineBasicBlock *, 8> VisitedBBs;
241 MachineInstr *Loop = findLoopInstr(TBB, EndLoopOp, VisitedBBs);
242 assert(Loop != 0 && "Inserting an ENDLOOP without a LOOP");
243 Loop->getOperand(0).setMBB(TBB);
244 // Add the ENDLOOP after the finding the LOOP0.
245 BuildMI(&MBB, DL, get(EndLoopOp)).addMBB(TBB);
247 const MachineOperand &RO = Cond[1];
248 unsigned Flags = getUndefRegState(RO.isUndef());
249 BuildMI(&MBB, DL, get(BccOpc)).addReg(RO.getReg(), Flags).addMBB(TBB);
251 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
257 /// This function can analyze one/two way branching only and should (mostly) be
258 /// called by target independent side.
259 /// First entry is always the opcode of the branching instruction, except when
260 /// the Cond vector is supposed to be empty, e.g., when AnalyzeBranch fails, a
261 /// BB with only unconditional jump. Subsequent entries depend upon the opcode,
262 /// e.g. Jump_c p will have
266 /// Cond[0] = ENDLOOP
269 /// Cond[0] = Hexagon::CMPEQri_f_Jumpnv_t_V4 -- specific opcode
272 /// @note Related function is \fn findInstrPredicate which fills in
273 /// Cond. vector when a predicated instruction is passed to it.
274 /// We follow same protocol in that case too.
276 bool HexagonInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
277 MachineBasicBlock *&TBB,
278 MachineBasicBlock *&FBB,
279 SmallVectorImpl<MachineOperand> &Cond,
280 bool AllowModify) const {
285 // If the block has no terminators, it just falls into the block after it.
286 MachineBasicBlock::instr_iterator I = MBB.instr_end();
287 if (I == MBB.instr_begin())
290 // A basic block may looks like this:
300 // It has two succs but does not have a terminator
301 // Don't know how to handle it.
305 // Don't analyze EH branches.
307 } while (I != MBB.instr_begin());
312 while (I->isDebugValue()) {
313 if (I == MBB.instr_begin())
318 bool JumpToBlock = I->getOpcode() == Hexagon::J2_jump &&
319 I->getOperand(0).isMBB();
320 // Delete the J2_jump if it's equivalent to a fall-through.
321 if (AllowModify && JumpToBlock &&
322 MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
323 DEBUG(dbgs()<< "\nErasing the jump to successor block\n";);
324 I->eraseFromParent();
326 if (I == MBB.instr_begin())
330 if (!isUnpredicatedTerminator(I))
333 // Get the last instruction in the block.
334 MachineInstr *LastInst = I;
335 MachineInstr *SecondLastInst = nullptr;
336 // Find one more terminator if present.
338 if (&*I != LastInst && !I->isBundle() && isUnpredicatedTerminator(I)) {
342 // This is a third branch.
345 if (I == MBB.instr_begin())
350 int LastOpcode = LastInst->getOpcode();
351 int SecLastOpcode = SecondLastInst ? SecondLastInst->getOpcode() : 0;
352 // If the branch target is not a basic block, it could be a tail call.
353 // (It is, if the target is a function.)
354 if (LastOpcode == Hexagon::J2_jump && !LastInst->getOperand(0).isMBB())
356 if (SecLastOpcode == Hexagon::J2_jump &&
357 !SecondLastInst->getOperand(0).isMBB())
360 bool LastOpcodeHasJMP_c = PredOpcodeHasJMP_c(LastOpcode);
361 bool LastOpcodeHasNVJump = isNewValueJump(LastInst);
363 // If there is only one terminator instruction, process it.
364 if (LastInst && !SecondLastInst) {
365 if (LastOpcode == Hexagon::J2_jump) {
366 TBB = LastInst->getOperand(0).getMBB();
369 if (isEndLoopN(LastOpcode)) {
370 TBB = LastInst->getOperand(0).getMBB();
371 Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
372 Cond.push_back(LastInst->getOperand(0));
375 if (LastOpcodeHasJMP_c) {
376 TBB = LastInst->getOperand(1).getMBB();
377 Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
378 Cond.push_back(LastInst->getOperand(0));
381 // Only supporting rr/ri versions of new-value jumps.
382 if (LastOpcodeHasNVJump && (LastInst->getNumExplicitOperands() == 3)) {
383 TBB = LastInst->getOperand(2).getMBB();
384 Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
385 Cond.push_back(LastInst->getOperand(0));
386 Cond.push_back(LastInst->getOperand(1));
389 DEBUG(dbgs() << "\nCant analyze BB#" << MBB.getNumber()
390 << " with one jump\n";);
391 // Otherwise, don't know what this is.
395 bool SecLastOpcodeHasJMP_c = PredOpcodeHasJMP_c(SecLastOpcode);
396 bool SecLastOpcodeHasNVJump = isNewValueJump(SecondLastInst);
397 if (SecLastOpcodeHasJMP_c && (LastOpcode == Hexagon::J2_jump)) {
398 TBB = SecondLastInst->getOperand(1).getMBB();
399 Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
400 Cond.push_back(SecondLastInst->getOperand(0));
401 FBB = LastInst->getOperand(0).getMBB();
405 // Only supporting rr/ri versions of new-value jumps.
406 if (SecLastOpcodeHasNVJump &&
407 (SecondLastInst->getNumExplicitOperands() == 3) &&
408 (LastOpcode == Hexagon::J2_jump)) {
409 TBB = SecondLastInst->getOperand(2).getMBB();
410 Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
411 Cond.push_back(SecondLastInst->getOperand(0));
412 Cond.push_back(SecondLastInst->getOperand(1));
413 FBB = LastInst->getOperand(0).getMBB();
417 // If the block ends with two Hexagon:JMPs, handle it. The second one is not
418 // executed, so remove it.
419 if (SecLastOpcode == Hexagon::J2_jump && LastOpcode == Hexagon::J2_jump) {
420 TBB = SecondLastInst->getOperand(0).getMBB();
423 I->eraseFromParent();
427 // If the block ends with an ENDLOOP, and J2_jump, handle it.
428 if (isEndLoopN(SecLastOpcode) && LastOpcode == Hexagon::J2_jump) {
429 TBB = SecondLastInst->getOperand(0).getMBB();
430 Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
431 Cond.push_back(SecondLastInst->getOperand(0));
432 FBB = LastInst->getOperand(0).getMBB();
435 DEBUG(dbgs() << "\nCant analyze BB#" << MBB.getNumber()
436 << " with two jumps";);
437 // Otherwise, can't handle this.
441 unsigned HexagonInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
442 DEBUG(dbgs() << "\nRemoving branches out of BB#" << MBB.getNumber());
443 MachineBasicBlock::iterator I = MBB.end();
445 while (I != MBB.begin()) {
447 if (I->isDebugValue())
449 // Only removing branches from end of MBB.
452 if (Count && (I->getOpcode() == Hexagon::J2_jump))
453 llvm_unreachable("Malformed basic block: unconditional branch not last");
454 MBB.erase(&MBB.back());
461 /// \brief For a comparison instruction, return the source registers in
462 /// \p SrcReg and \p SrcReg2 if having two register operands, and the value it
463 /// compares against in CmpValue. Return true if the comparison instruction
465 bool HexagonInstrInfo::analyzeCompare(const MachineInstr *MI,
466 unsigned &SrcReg, unsigned &SrcReg2,
467 int &Mask, int &Value) const {
468 unsigned Opc = MI->getOpcode();
470 // Set mask and the first source register.
472 case Hexagon::C2_cmpeq:
473 case Hexagon::C2_cmpeqp:
474 case Hexagon::C2_cmpgt:
475 case Hexagon::C2_cmpgtp:
476 case Hexagon::C2_cmpgtu:
477 case Hexagon::C2_cmpgtup:
478 case Hexagon::C4_cmpneq:
479 case Hexagon::C4_cmplte:
480 case Hexagon::C4_cmplteu:
481 case Hexagon::C2_cmpeqi:
482 case Hexagon::C2_cmpgti:
483 case Hexagon::C2_cmpgtui:
484 case Hexagon::C4_cmpneqi:
485 case Hexagon::C4_cmplteui:
486 case Hexagon::C4_cmpltei:
487 SrcReg = MI->getOperand(1).getReg();
490 case Hexagon::A4_cmpbeq:
491 case Hexagon::A4_cmpbgt:
492 case Hexagon::A4_cmpbgtu:
493 case Hexagon::A4_cmpbeqi:
494 case Hexagon::A4_cmpbgti:
495 case Hexagon::A4_cmpbgtui:
496 SrcReg = MI->getOperand(1).getReg();
499 case Hexagon::A4_cmpheq:
500 case Hexagon::A4_cmphgt:
501 case Hexagon::A4_cmphgtu:
502 case Hexagon::A4_cmpheqi:
503 case Hexagon::A4_cmphgti:
504 case Hexagon::A4_cmphgtui:
505 SrcReg = MI->getOperand(1).getReg();
510 // Set the value/second source register.
512 case Hexagon::C2_cmpeq:
513 case Hexagon::C2_cmpeqp:
514 case Hexagon::C2_cmpgt:
515 case Hexagon::C2_cmpgtp:
516 case Hexagon::C2_cmpgtu:
517 case Hexagon::C2_cmpgtup:
518 case Hexagon::A4_cmpbeq:
519 case Hexagon::A4_cmpbgt:
520 case Hexagon::A4_cmpbgtu:
521 case Hexagon::A4_cmpheq:
522 case Hexagon::A4_cmphgt:
523 case Hexagon::A4_cmphgtu:
524 case Hexagon::C4_cmpneq:
525 case Hexagon::C4_cmplte:
526 case Hexagon::C4_cmplteu:
527 SrcReg2 = MI->getOperand(2).getReg();
530 case Hexagon::C2_cmpeqi:
531 case Hexagon::C2_cmpgtui:
532 case Hexagon::C2_cmpgti:
533 case Hexagon::C4_cmpneqi:
534 case Hexagon::C4_cmplteui:
535 case Hexagon::C4_cmpltei:
536 case Hexagon::A4_cmpbeqi:
537 case Hexagon::A4_cmpbgti:
538 case Hexagon::A4_cmpbgtui:
539 case Hexagon::A4_cmpheqi:
540 case Hexagon::A4_cmphgti:
541 case Hexagon::A4_cmphgtui:
543 Value = MI->getOperand(2).getImm();
551 void HexagonInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
552 MachineBasicBlock::iterator I, DebugLoc DL,
553 unsigned DestReg, unsigned SrcReg,
554 bool KillSrc) const {
555 if (Hexagon::IntRegsRegClass.contains(SrcReg, DestReg)) {
556 BuildMI(MBB, I, DL, get(Hexagon::A2_tfr), DestReg).addReg(SrcReg);
559 if (Hexagon::DoubleRegsRegClass.contains(SrcReg, DestReg)) {
560 BuildMI(MBB, I, DL, get(Hexagon::A2_tfrp), DestReg).addReg(SrcReg);
563 if (Hexagon::PredRegsRegClass.contains(SrcReg, DestReg)) {
564 // Map Pd = Ps to Pd = or(Ps, Ps).
565 BuildMI(MBB, I, DL, get(Hexagon::C2_or),
566 DestReg).addReg(SrcReg).addReg(SrcReg);
569 if (Hexagon::DoubleRegsRegClass.contains(DestReg) &&
570 Hexagon::IntRegsRegClass.contains(SrcReg)) {
571 // We can have an overlap between single and double reg: r1:0 = r0.
572 if(SrcReg == RI.getSubReg(DestReg, Hexagon::subreg_loreg)) {
574 BuildMI(MBB, I, DL, get(Hexagon::A2_tfrsi), (RI.getSubReg(DestReg,
575 Hexagon::subreg_hireg))).addImm(0);
577 // r1:0 = r1 or no overlap.
578 BuildMI(MBB, I, DL, get(Hexagon::A2_tfr), (RI.getSubReg(DestReg,
579 Hexagon::subreg_loreg))).addReg(SrcReg);
580 BuildMI(MBB, I, DL, get(Hexagon::A2_tfrsi), (RI.getSubReg(DestReg,
581 Hexagon::subreg_hireg))).addImm(0);
585 if (Hexagon::CtrRegsRegClass.contains(DestReg) &&
586 Hexagon::IntRegsRegClass.contains(SrcReg)) {
587 BuildMI(MBB, I, DL, get(Hexagon::A2_tfrrcr), DestReg).addReg(SrcReg);
590 if (Hexagon::PredRegsRegClass.contains(SrcReg) &&
591 Hexagon::IntRegsRegClass.contains(DestReg)) {
592 BuildMI(MBB, I, DL, get(Hexagon::C2_tfrpr), DestReg).
593 addReg(SrcReg, getKillRegState(KillSrc));
596 if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
597 Hexagon::PredRegsRegClass.contains(DestReg)) {
598 BuildMI(MBB, I, DL, get(Hexagon::C2_tfrrp), DestReg).
599 addReg(SrcReg, getKillRegState(KillSrc));
603 llvm_unreachable("Unimplemented");
607 void HexagonInstrInfo::
608 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
609 unsigned SrcReg, bool isKill, int FI,
610 const TargetRegisterClass *RC,
611 const TargetRegisterInfo *TRI) const {
613 DebugLoc DL = MBB.findDebugLoc(I);
614 MachineFunction &MF = *MBB.getParent();
615 MachineFrameInfo &MFI = *MF.getFrameInfo();
616 unsigned Align = MFI.getObjectAlignment(FI);
618 MachineMemOperand *MMO =
619 MF.getMachineMemOperand(
620 MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
621 MachineMemOperand::MOStore,
622 MFI.getObjectSize(FI),
625 if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {
626 BuildMI(MBB, I, DL, get(Hexagon::S2_storeri_io))
627 .addFrameIndex(FI).addImm(0)
628 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
629 } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {
630 BuildMI(MBB, I, DL, get(Hexagon::S2_storerd_io))
631 .addFrameIndex(FI).addImm(0)
632 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
633 } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {
634 BuildMI(MBB, I, DL, get(Hexagon::STriw_pred))
635 .addFrameIndex(FI).addImm(0)
636 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
638 llvm_unreachable("Unimplemented");
643 void HexagonInstrInfo::storeRegToAddr(
644 MachineFunction &MF, unsigned SrcReg,
646 SmallVectorImpl<MachineOperand> &Addr,
647 const TargetRegisterClass *RC,
648 SmallVectorImpl<MachineInstr*> &NewMIs) const
650 llvm_unreachable("Unimplemented");
654 void HexagonInstrInfo::
655 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
656 unsigned DestReg, int FI,
657 const TargetRegisterClass *RC,
658 const TargetRegisterInfo *TRI) const {
659 DebugLoc DL = MBB.findDebugLoc(I);
660 MachineFunction &MF = *MBB.getParent();
661 MachineFrameInfo &MFI = *MF.getFrameInfo();
662 unsigned Align = MFI.getObjectAlignment(FI);
664 MachineMemOperand *MMO =
665 MF.getMachineMemOperand(
666 MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
667 MachineMemOperand::MOLoad,
668 MFI.getObjectSize(FI),
670 if (RC == &Hexagon::IntRegsRegClass) {
671 BuildMI(MBB, I, DL, get(Hexagon::L2_loadri_io), DestReg)
672 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
673 } else if (RC == &Hexagon::DoubleRegsRegClass) {
674 BuildMI(MBB, I, DL, get(Hexagon::L2_loadrd_io), DestReg)
675 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
676 } else if (RC == &Hexagon::PredRegsRegClass) {
677 BuildMI(MBB, I, DL, get(Hexagon::LDriw_pred), DestReg)
678 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
680 llvm_unreachable("Can't store this register to stack slot");
685 void HexagonInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
686 SmallVectorImpl<MachineOperand> &Addr,
687 const TargetRegisterClass *RC,
688 SmallVectorImpl<MachineInstr*> &NewMIs) const {
689 llvm_unreachable("Unimplemented");
692 HexagonInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
693 const HexagonRegisterInfo &TRI = getRegisterInfo();
694 MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
695 MachineBasicBlock &MBB = *MI->getParent();
696 DebugLoc DL = MI->getDebugLoc();
697 unsigned Opc = MI->getOpcode();
700 case Hexagon::ALIGNA:
701 BuildMI(MBB, MI, DL, get(Hexagon::A2_andir), MI->getOperand(0).getReg())
702 .addReg(TRI.getFrameRegister())
703 .addImm(-MI->getOperand(1).getImm());
706 case Hexagon::TFR_PdTrue: {
707 unsigned Reg = MI->getOperand(0).getReg();
708 BuildMI(MBB, MI, DL, get(Hexagon::C2_orn), Reg)
709 .addReg(Reg, RegState::Undef)
710 .addReg(Reg, RegState::Undef);
714 case Hexagon::TFR_PdFalse: {
715 unsigned Reg = MI->getOperand(0).getReg();
716 BuildMI(MBB, MI, DL, get(Hexagon::C2_andn), Reg)
717 .addReg(Reg, RegState::Undef)
718 .addReg(Reg, RegState::Undef);
722 case Hexagon::VMULW: {
723 // Expand a 64-bit vector multiply into 2 32-bit scalar multiplies.
724 unsigned DstReg = MI->getOperand(0).getReg();
725 unsigned Src1Reg = MI->getOperand(1).getReg();
726 unsigned Src2Reg = MI->getOperand(2).getReg();
727 unsigned Src1SubHi = TRI.getSubReg(Src1Reg, Hexagon::subreg_hireg);
728 unsigned Src1SubLo = TRI.getSubReg(Src1Reg, Hexagon::subreg_loreg);
729 unsigned Src2SubHi = TRI.getSubReg(Src2Reg, Hexagon::subreg_hireg);
730 unsigned Src2SubLo = TRI.getSubReg(Src2Reg, Hexagon::subreg_loreg);
731 BuildMI(MBB, MI, MI->getDebugLoc(), get(Hexagon::M2_mpyi),
732 TRI.getSubReg(DstReg, Hexagon::subreg_hireg)).addReg(Src1SubHi)
734 BuildMI(MBB, MI, MI->getDebugLoc(), get(Hexagon::M2_mpyi),
735 TRI.getSubReg(DstReg, Hexagon::subreg_loreg)).addReg(Src1SubLo)
738 MRI.clearKillFlags(Src1SubHi);
739 MRI.clearKillFlags(Src1SubLo);
740 MRI.clearKillFlags(Src2SubHi);
741 MRI.clearKillFlags(Src2SubLo);
744 case Hexagon::VMULW_ACC: {
745 // Expand 64-bit vector multiply with addition into 2 scalar multiplies.
746 unsigned DstReg = MI->getOperand(0).getReg();
747 unsigned Src1Reg = MI->getOperand(1).getReg();
748 unsigned Src2Reg = MI->getOperand(2).getReg();
749 unsigned Src3Reg = MI->getOperand(3).getReg();
750 unsigned Src1SubHi = TRI.getSubReg(Src1Reg, Hexagon::subreg_hireg);
751 unsigned Src1SubLo = TRI.getSubReg(Src1Reg, Hexagon::subreg_loreg);
752 unsigned Src2SubHi = TRI.getSubReg(Src2Reg, Hexagon::subreg_hireg);
753 unsigned Src2SubLo = TRI.getSubReg(Src2Reg, Hexagon::subreg_loreg);
754 unsigned Src3SubHi = TRI.getSubReg(Src3Reg, Hexagon::subreg_hireg);
755 unsigned Src3SubLo = TRI.getSubReg(Src3Reg, Hexagon::subreg_loreg);
756 BuildMI(MBB, MI, MI->getDebugLoc(), get(Hexagon::M2_maci),
757 TRI.getSubReg(DstReg, Hexagon::subreg_hireg)).addReg(Src1SubHi)
758 .addReg(Src2SubHi).addReg(Src3SubHi);
759 BuildMI(MBB, MI, MI->getDebugLoc(), get(Hexagon::M2_maci),
760 TRI.getSubReg(DstReg, Hexagon::subreg_loreg)).addReg(Src1SubLo)
761 .addReg(Src2SubLo).addReg(Src3SubLo);
763 MRI.clearKillFlags(Src1SubHi);
764 MRI.clearKillFlags(Src1SubLo);
765 MRI.clearKillFlags(Src2SubHi);
766 MRI.clearKillFlags(Src2SubLo);
767 MRI.clearKillFlags(Src3SubHi);
768 MRI.clearKillFlags(Src3SubLo);
771 case Hexagon::TCRETURNi:
772 MI->setDesc(get(Hexagon::J2_jump));
774 case Hexagon::TCRETURNr:
775 MI->setDesc(get(Hexagon::J2_jumpr));
782 MachineInstr *HexagonInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
784 ArrayRef<unsigned> Ops,
786 // Hexagon_TODO: Implement.
790 unsigned HexagonInstrInfo::createVR(MachineFunction* MF, MVT VT) const {
792 MachineRegisterInfo &RegInfo = MF->getRegInfo();
793 const TargetRegisterClass *TRC;
795 TRC = &Hexagon::PredRegsRegClass;
796 } else if (VT == MVT::i32 || VT == MVT::f32) {
797 TRC = &Hexagon::IntRegsRegClass;
798 } else if (VT == MVT::i64 || VT == MVT::f64) {
799 TRC = &Hexagon::DoubleRegsRegClass;
801 llvm_unreachable("Cannot handle this register class");
804 unsigned NewReg = RegInfo.createVirtualRegister(TRC);
808 bool HexagonInstrInfo::isExtendable(const MachineInstr *MI) const {
809 const MCInstrDesc &MID = MI->getDesc();
810 const uint64_t F = MID.TSFlags;
811 if ((F >> HexagonII::ExtendablePos) & HexagonII::ExtendableMask)
814 // TODO: This is largely obsolete now. Will need to be removed
815 // in consecutive patches.
816 switch(MI->getOpcode()) {
817 // TFR_FI Remains a special case.
818 case Hexagon::TFR_FI:
826 // This returns true in two cases:
827 // - The OP code itself indicates that this is an extended instruction.
828 // - One of MOs has been marked with HMOTF_ConstExtended flag.
829 bool HexagonInstrInfo::isExtended(const MachineInstr *MI) const {
830 // First check if this is permanently extended op code.
831 const uint64_t F = MI->getDesc().TSFlags;
832 if ((F >> HexagonII::ExtendedPos) & HexagonII::ExtendedMask)
834 // Use MO operand flags to determine if one of MI's operands
835 // has HMOTF_ConstExtended flag set.
836 for (MachineInstr::const_mop_iterator I = MI->operands_begin(),
837 E = MI->operands_end(); I != E; ++I) {
838 if (I->getTargetFlags() && HexagonII::HMOTF_ConstExtended)
844 bool HexagonInstrInfo::isBranch (const MachineInstr *MI) const {
845 return MI->getDesc().isBranch();
848 bool HexagonInstrInfo::isNewValueInst(const MachineInstr *MI) const {
849 if (isNewValueJump(MI))
852 if (isNewValueStore(MI))
858 bool HexagonInstrInfo::isNewValue(const MachineInstr* MI) const {
859 const uint64_t F = MI->getDesc().TSFlags;
860 return ((F >> HexagonII::NewValuePos) & HexagonII::NewValueMask);
863 bool HexagonInstrInfo::isNewValue(Opcode_t Opcode) const {
864 const uint64_t F = get(Opcode).TSFlags;
865 return ((F >> HexagonII::NewValuePos) & HexagonII::NewValueMask);
868 bool HexagonInstrInfo::isSaveCalleeSavedRegsCall(const MachineInstr *MI) const {
869 return MI->getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4;
872 bool HexagonInstrInfo::isPredicable(MachineInstr *MI) const {
873 bool isPred = MI->getDesc().isPredicable();
878 const int Opc = MI->getOpcode();
881 case Hexagon::A2_tfrsi:
882 return (isOperandExtended(MI, 1) && isConstExtended(MI)) || isInt<12>(MI->getOperand(1).getImm());
884 case Hexagon::S2_storerd_io:
885 return isShiftedUInt<6,3>(MI->getOperand(1).getImm());
887 case Hexagon::S2_storeri_io:
888 case Hexagon::S2_storerinew_io:
889 return isShiftedUInt<6,2>(MI->getOperand(1).getImm());
891 case Hexagon::S2_storerh_io:
892 case Hexagon::S2_storerhnew_io:
893 return isShiftedUInt<6,1>(MI->getOperand(1).getImm());
895 case Hexagon::S2_storerb_io:
896 case Hexagon::S2_storerbnew_io:
897 return isUInt<6>(MI->getOperand(1).getImm());
899 case Hexagon::L2_loadrd_io:
900 return isShiftedUInt<6,3>(MI->getOperand(2).getImm());
902 case Hexagon::L2_loadri_io:
903 return isShiftedUInt<6,2>(MI->getOperand(2).getImm());
905 case Hexagon::L2_loadrh_io:
906 case Hexagon::L2_loadruh_io:
907 return isShiftedUInt<6,1>(MI->getOperand(2).getImm());
909 case Hexagon::L2_loadrb_io:
910 case Hexagon::L2_loadrub_io:
911 return isUInt<6>(MI->getOperand(2).getImm());
913 case Hexagon::L2_loadrd_pi:
914 return isShiftedInt<4,3>(MI->getOperand(3).getImm());
916 case Hexagon::L2_loadri_pi:
917 return isShiftedInt<4,2>(MI->getOperand(3).getImm());
919 case Hexagon::L2_loadrh_pi:
920 case Hexagon::L2_loadruh_pi:
921 return isShiftedInt<4,1>(MI->getOperand(3).getImm());
923 case Hexagon::L2_loadrb_pi:
924 case Hexagon::L2_loadrub_pi:
925 return isInt<4>(MI->getOperand(3).getImm());
927 case Hexagon::S4_storeirb_io:
928 case Hexagon::S4_storeirh_io:
929 case Hexagon::S4_storeiri_io:
930 return (isUInt<6>(MI->getOperand(1).getImm()) &&
931 isInt<6>(MI->getOperand(2).getImm()));
933 case Hexagon::A2_addi:
934 return isInt<8>(MI->getOperand(2).getImm());
936 case Hexagon::A2_aslh:
937 case Hexagon::A2_asrh:
938 case Hexagon::A2_sxtb:
939 case Hexagon::A2_sxth:
940 case Hexagon::A2_zxtb:
941 case Hexagon::A2_zxth:
948 // This function performs the following inversiones:
953 unsigned HexagonInstrInfo::getInvertedPredicatedOpcode(const int Opc) const {
955 InvPredOpcode = isPredicatedTrue(Opc) ? Hexagon::getFalsePredOpcode(Opc)
956 : Hexagon::getTruePredOpcode(Opc);
957 if (InvPredOpcode >= 0) // Valid instruction with the inverted predicate.
958 return InvPredOpcode;
961 default: llvm_unreachable("Unexpected predicated instruction");
962 case Hexagon::C2_ccombinewt:
963 return Hexagon::C2_ccombinewf;
964 case Hexagon::C2_ccombinewf:
965 return Hexagon::C2_ccombinewt;
968 case Hexagon::L4_return_t:
969 return Hexagon::L4_return_f;
970 case Hexagon::L4_return_f:
971 return Hexagon::L4_return_t;
975 // New Value Store instructions.
976 bool HexagonInstrInfo::isNewValueStore(const MachineInstr *MI) const {
977 const uint64_t F = MI->getDesc().TSFlags;
979 return ((F >> HexagonII::NVStorePos) & HexagonII::NVStoreMask);
982 bool HexagonInstrInfo::isNewValueStore(unsigned Opcode) const {
983 const uint64_t F = get(Opcode).TSFlags;
985 return ((F >> HexagonII::NVStorePos) & HexagonII::NVStoreMask);
988 int HexagonInstrInfo::getCondOpcode(int Opc, bool invertPredicate) const {
989 enum Hexagon::PredSense inPredSense;
990 inPredSense = invertPredicate ? Hexagon::PredSense_false :
991 Hexagon::PredSense_true;
992 int CondOpcode = Hexagon::getPredOpcode(Opc, inPredSense);
993 if (CondOpcode >= 0) // Valid Conditional opcode/instruction
996 // This switch case will be removed once all the instructions have been
997 // modified to use relation maps.
999 case Hexagon::TFRI_f:
1000 return !invertPredicate ? Hexagon::TFRI_cPt_f :
1001 Hexagon::TFRI_cNotPt_f;
1002 case Hexagon::A2_combinew:
1003 return !invertPredicate ? Hexagon::C2_ccombinewt :
1004 Hexagon::C2_ccombinewf;
1007 case Hexagon::L4_return:
1008 return !invertPredicate ? Hexagon::L4_return_t:
1009 Hexagon::L4_return_f;
1011 llvm_unreachable("Unexpected predicable instruction");
1015 bool HexagonInstrInfo::
1016 PredicateInstruction(MachineInstr *MI,
1017 const SmallVectorImpl<MachineOperand> &Cond) const {
1018 if (Cond.empty() || isEndLoopN(Cond[0].getImm())) {
1019 DEBUG(dbgs() << "\nCannot predicate:"; MI->dump(););
1022 int Opc = MI->getOpcode();
1023 assert (isPredicable(MI) && "Expected predicable instruction");
1024 bool invertJump = predOpcodeHasNot(Cond);
1026 // We have to predicate MI "in place", i.e. after this function returns,
1027 // MI will need to be transformed into a predicated form. To avoid com-
1028 // plicated manipulations with the operands (handling tied operands,
1029 // etc.), build a new temporary instruction, then overwrite MI with it.
1031 MachineBasicBlock &B = *MI->getParent();
1032 DebugLoc DL = MI->getDebugLoc();
1033 unsigned PredOpc = getCondOpcode(Opc, invertJump);
1034 MachineInstrBuilder T = BuildMI(B, MI, DL, get(PredOpc));
1035 unsigned NOp = 0, NumOps = MI->getNumOperands();
1036 while (NOp < NumOps) {
1037 MachineOperand &Op = MI->getOperand(NOp);
1038 if (!Op.isReg() || !Op.isDef() || Op.isImplicit())
1044 unsigned PredReg, PredRegPos, PredRegFlags;
1045 bool GotPredReg = getPredReg(Cond, PredReg, PredRegPos, PredRegFlags);
1048 T.addReg(PredReg, PredRegFlags);
1049 while (NOp < NumOps)
1050 T.addOperand(MI->getOperand(NOp++));
1052 MI->setDesc(get(PredOpc));
1053 while (unsigned n = MI->getNumOperands())
1054 MI->RemoveOperand(n-1);
1055 for (unsigned i = 0, n = T->getNumOperands(); i < n; ++i)
1056 MI->addOperand(T->getOperand(i));
1058 MachineBasicBlock::instr_iterator TI = &*T;
1061 MachineRegisterInfo &MRI = B.getParent()->getRegInfo();
1062 MRI.clearKillFlags(PredReg);
1070 isProfitableToIfCvt(MachineBasicBlock &MBB,
1072 unsigned ExtraPredCycles,
1073 const BranchProbability &Probability) const {
1080 isProfitableToIfCvt(MachineBasicBlock &TMBB,
1081 unsigned NumTCycles,
1082 unsigned ExtraTCycles,
1083 MachineBasicBlock &FMBB,
1084 unsigned NumFCycles,
1085 unsigned ExtraFCycles,
1086 const BranchProbability &Probability) const {
1090 // Returns true if an instruction is predicated irrespective of the predicate
1091 // sense. For example, all of the following will return true.
1092 // if (p0) R1 = add(R2, R3)
1093 // if (!p0) R1 = add(R2, R3)
1094 // if (p0.new) R1 = add(R2, R3)
1095 // if (!p0.new) R1 = add(R2, R3)
1096 bool HexagonInstrInfo::isPredicated(const MachineInstr *MI) const {
1097 const uint64_t F = MI->getDesc().TSFlags;
1099 return ((F >> HexagonII::PredicatedPos) & HexagonII::PredicatedMask);
1102 bool HexagonInstrInfo::isPredicated(unsigned Opcode) const {
1103 const uint64_t F = get(Opcode).TSFlags;
1105 return ((F >> HexagonII::PredicatedPos) & HexagonII::PredicatedMask);
1108 bool HexagonInstrInfo::isPredicatedTrue(const MachineInstr *MI) const {
1109 const uint64_t F = MI->getDesc().TSFlags;
1111 assert(isPredicated(MI));
1112 return (!((F >> HexagonII::PredicatedFalsePos) &
1113 HexagonII::PredicatedFalseMask));
1116 bool HexagonInstrInfo::isPredicatedTrue(unsigned Opcode) const {
1117 const uint64_t F = get(Opcode).TSFlags;
1119 // Make sure that the instruction is predicated.
1120 assert((F>> HexagonII::PredicatedPos) & HexagonII::PredicatedMask);
1121 return (!((F >> HexagonII::PredicatedFalsePos) &
1122 HexagonII::PredicatedFalseMask));
1125 bool HexagonInstrInfo::isPredicatedNew(const MachineInstr *MI) const {
1126 const uint64_t F = MI->getDesc().TSFlags;
1128 assert(isPredicated(MI));
1129 return ((F >> HexagonII::PredicatedNewPos) & HexagonII::PredicatedNewMask);
1132 bool HexagonInstrInfo::isPredicatedNew(unsigned Opcode) const {
1133 const uint64_t F = get(Opcode).TSFlags;
1135 assert(isPredicated(Opcode));
1136 return ((F >> HexagonII::PredicatedNewPos) & HexagonII::PredicatedNewMask);
1139 // Returns true, if a ST insn can be promoted to a new-value store.
1140 bool HexagonInstrInfo::mayBeNewStore(const MachineInstr *MI) const {
1141 const uint64_t F = MI->getDesc().TSFlags;
1143 return ((F >> HexagonII::mayNVStorePos) &
1144 HexagonII::mayNVStoreMask);
1148 HexagonInstrInfo::DefinesPredicate(MachineInstr *MI,
1149 std::vector<MachineOperand> &Pred) const {
1150 for (unsigned oper = 0; oper < MI->getNumOperands(); ++oper) {
1151 MachineOperand MO = MI->getOperand(oper);
1152 if (MO.isReg() && MO.isDef()) {
1153 const TargetRegisterClass* RC = RI.getMinimalPhysRegClass(MO.getReg());
1154 if (RC == &Hexagon::PredRegsRegClass) {
1166 SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
1167 const SmallVectorImpl<MachineOperand> &Pred2) const {
1174 // We indicate that we want to reverse the branch by
1175 // inserting the reversed branching opcode.
1177 bool HexagonInstrInfo::ReverseBranchCondition(
1178 SmallVectorImpl<MachineOperand> &Cond) const {
1181 assert(Cond[0].isImm() && "First entry in the cond vector not imm-val");
1182 Opcode_t opcode = Cond[0].getImm();
1184 assert(get(opcode).isBranch() && "Should be a branching condition.");
1185 if (isEndLoopN(opcode))
1187 Opcode_t NewOpcode = getInvertedPredicatedOpcode(opcode);
1188 Cond[0].setImm(NewOpcode);
1193 bool HexagonInstrInfo::
1194 isProfitableToDupForIfCvt(MachineBasicBlock &MBB,unsigned NumInstrs,
1195 const BranchProbability &Probability) const {
1196 return (NumInstrs <= 4);
1199 bool HexagonInstrInfo::isDeallocRet(const MachineInstr *MI) const {
1200 switch (MI->getOpcode()) {
1201 default: return false;
1202 case Hexagon::L4_return:
1203 case Hexagon::L4_return_t:
1204 case Hexagon::L4_return_f:
1205 case Hexagon::L4_return_tnew_pnt:
1206 case Hexagon::L4_return_fnew_pnt:
1207 case Hexagon::L4_return_tnew_pt:
1208 case Hexagon::L4_return_fnew_pt:
1214 bool HexagonInstrInfo::isValidOffset(unsigned Opcode, int Offset,
1215 bool Extend) const {
1216 // This function is to check whether the "Offset" is in the correct range of
1217 // the given "Opcode". If "Offset" is not in the correct range, "A2_addi" is
1218 // inserted to calculate the final address. Due to this reason, the function
1219 // assumes that the "Offset" has correct alignment.
1220 // We used to assert if the offset was not properly aligned, however,
1221 // there are cases where a misaligned pointer recast can cause this
1222 // problem, and we need to allow for it. The front end warns of such
1223 // misaligns with respect to load size.
1226 case Hexagon::J2_loop0i:
1227 case Hexagon::J2_loop1i:
1228 return isUInt<10>(Offset);
1235 case Hexagon::L2_loadri_io:
1236 case Hexagon::S2_storeri_io:
1237 return (Offset >= Hexagon_MEMW_OFFSET_MIN) &&
1238 (Offset <= Hexagon_MEMW_OFFSET_MAX);
1240 case Hexagon::L2_loadrd_io:
1241 case Hexagon::S2_storerd_io:
1242 return (Offset >= Hexagon_MEMD_OFFSET_MIN) &&
1243 (Offset <= Hexagon_MEMD_OFFSET_MAX);
1245 case Hexagon::L2_loadrh_io:
1246 case Hexagon::L2_loadruh_io:
1247 case Hexagon::S2_storerh_io:
1248 return (Offset >= Hexagon_MEMH_OFFSET_MIN) &&
1249 (Offset <= Hexagon_MEMH_OFFSET_MAX);
1251 case Hexagon::L2_loadrb_io:
1252 case Hexagon::S2_storerb_io:
1253 case Hexagon::L2_loadrub_io:
1254 return (Offset >= Hexagon_MEMB_OFFSET_MIN) &&
1255 (Offset <= Hexagon_MEMB_OFFSET_MAX);
1257 case Hexagon::A2_addi:
1258 return (Offset >= Hexagon_ADDI_OFFSET_MIN) &&
1259 (Offset <= Hexagon_ADDI_OFFSET_MAX);
1261 case Hexagon::L4_iadd_memopw_io:
1262 case Hexagon::L4_isub_memopw_io:
1263 case Hexagon::L4_add_memopw_io:
1264 case Hexagon::L4_sub_memopw_io:
1265 case Hexagon::L4_and_memopw_io:
1266 case Hexagon::L4_or_memopw_io:
1267 return (0 <= Offset && Offset <= 255);
1269 case Hexagon::L4_iadd_memoph_io:
1270 case Hexagon::L4_isub_memoph_io:
1271 case Hexagon::L4_add_memoph_io:
1272 case Hexagon::L4_sub_memoph_io:
1273 case Hexagon::L4_and_memoph_io:
1274 case Hexagon::L4_or_memoph_io:
1275 return (0 <= Offset && Offset <= 127);
1277 case Hexagon::L4_iadd_memopb_io:
1278 case Hexagon::L4_isub_memopb_io:
1279 case Hexagon::L4_add_memopb_io:
1280 case Hexagon::L4_sub_memopb_io:
1281 case Hexagon::L4_and_memopb_io:
1282 case Hexagon::L4_or_memopb_io:
1283 return (0 <= Offset && Offset <= 63);
1285 // LDri_pred and STriw_pred are pseudo operations, so it has to take offset of
1286 // any size. Later pass knows how to handle it.
1287 case Hexagon::STriw_pred:
1288 case Hexagon::LDriw_pred:
1291 case Hexagon::TFR_FI:
1292 case Hexagon::TFR_FIA:
1293 case Hexagon::INLINEASM:
1297 llvm_unreachable("No offset range is defined for this opcode. "
1298 "Please define it in the above switch statement!");
1303 // Check if the Offset is a valid auto-inc imm by Load/Store Type.
1305 bool HexagonInstrInfo::
1306 isValidAutoIncImm(const EVT VT, const int Offset) const {
1308 if (VT == MVT::i64) {
1309 return (Offset >= Hexagon_MEMD_AUTOINC_MIN &&
1310 Offset <= Hexagon_MEMD_AUTOINC_MAX &&
1311 (Offset & 0x7) == 0);
1313 if (VT == MVT::i32) {
1314 return (Offset >= Hexagon_MEMW_AUTOINC_MIN &&
1315 Offset <= Hexagon_MEMW_AUTOINC_MAX &&
1316 (Offset & 0x3) == 0);
1318 if (VT == MVT::i16) {
1319 return (Offset >= Hexagon_MEMH_AUTOINC_MIN &&
1320 Offset <= Hexagon_MEMH_AUTOINC_MAX &&
1321 (Offset & 0x1) == 0);
1323 if (VT == MVT::i8) {
1324 return (Offset >= Hexagon_MEMB_AUTOINC_MIN &&
1325 Offset <= Hexagon_MEMB_AUTOINC_MAX);
1327 llvm_unreachable("Not an auto-inc opc!");
1331 bool HexagonInstrInfo::
1332 isMemOp(const MachineInstr *MI) const {
1333 // return MI->getDesc().mayLoad() && MI->getDesc().mayStore();
1335 switch (MI->getOpcode())
1337 default: return false;
1338 case Hexagon::L4_iadd_memopw_io:
1339 case Hexagon::L4_isub_memopw_io:
1340 case Hexagon::L4_add_memopw_io:
1341 case Hexagon::L4_sub_memopw_io:
1342 case Hexagon::L4_and_memopw_io:
1343 case Hexagon::L4_or_memopw_io:
1344 case Hexagon::L4_iadd_memoph_io:
1345 case Hexagon::L4_isub_memoph_io:
1346 case Hexagon::L4_add_memoph_io:
1347 case Hexagon::L4_sub_memoph_io:
1348 case Hexagon::L4_and_memoph_io:
1349 case Hexagon::L4_or_memoph_io:
1350 case Hexagon::L4_iadd_memopb_io:
1351 case Hexagon::L4_isub_memopb_io:
1352 case Hexagon::L4_add_memopb_io:
1353 case Hexagon::L4_sub_memopb_io:
1354 case Hexagon::L4_and_memopb_io:
1355 case Hexagon::L4_or_memopb_io:
1356 case Hexagon::L4_ior_memopb_io:
1357 case Hexagon::L4_ior_memoph_io:
1358 case Hexagon::L4_ior_memopw_io:
1359 case Hexagon::L4_iand_memopb_io:
1360 case Hexagon::L4_iand_memoph_io:
1361 case Hexagon::L4_iand_memopw_io:
1368 bool HexagonInstrInfo::
1369 isSpillPredRegOp(const MachineInstr *MI) const {
1370 switch (MI->getOpcode()) {
1371 default: return false;
1372 case Hexagon::STriw_pred :
1373 case Hexagon::LDriw_pred :
1378 bool HexagonInstrInfo::isNewValueJumpCandidate(const MachineInstr *MI) const {
1379 switch (MI->getOpcode()) {
1380 default: return false;
1381 case Hexagon::C2_cmpeq:
1382 case Hexagon::C2_cmpeqi:
1383 case Hexagon::C2_cmpgt:
1384 case Hexagon::C2_cmpgti:
1385 case Hexagon::C2_cmpgtu:
1386 case Hexagon::C2_cmpgtui:
1391 bool HexagonInstrInfo::
1392 isConditionalTransfer (const MachineInstr *MI) const {
1393 switch (MI->getOpcode()) {
1394 default: return false;
1395 case Hexagon::A2_tfrt:
1396 case Hexagon::A2_tfrf:
1397 case Hexagon::C2_cmoveit:
1398 case Hexagon::C2_cmoveif:
1399 case Hexagon::A2_tfrtnew:
1400 case Hexagon::A2_tfrfnew:
1401 case Hexagon::C2_cmovenewit:
1402 case Hexagon::C2_cmovenewif:
1407 bool HexagonInstrInfo::isConditionalALU32 (const MachineInstr* MI) const {
1408 switch (MI->getOpcode())
1410 default: return false;
1411 case Hexagon::A2_paddf:
1412 case Hexagon::A2_paddfnew:
1413 case Hexagon::A2_paddt:
1414 case Hexagon::A2_paddtnew:
1415 case Hexagon::A2_pandf:
1416 case Hexagon::A2_pandfnew:
1417 case Hexagon::A2_pandt:
1418 case Hexagon::A2_pandtnew:
1419 case Hexagon::A4_paslhf:
1420 case Hexagon::A4_paslhfnew:
1421 case Hexagon::A4_paslht:
1422 case Hexagon::A4_paslhtnew:
1423 case Hexagon::A4_pasrhf:
1424 case Hexagon::A4_pasrhfnew:
1425 case Hexagon::A4_pasrht:
1426 case Hexagon::A4_pasrhtnew:
1427 case Hexagon::A2_porf:
1428 case Hexagon::A2_porfnew:
1429 case Hexagon::A2_port:
1430 case Hexagon::A2_portnew:
1431 case Hexagon::A2_psubf:
1432 case Hexagon::A2_psubfnew:
1433 case Hexagon::A2_psubt:
1434 case Hexagon::A2_psubtnew:
1435 case Hexagon::A2_pxorf:
1436 case Hexagon::A2_pxorfnew:
1437 case Hexagon::A2_pxort:
1438 case Hexagon::A2_pxortnew:
1439 case Hexagon::A4_psxthf:
1440 case Hexagon::A4_psxthfnew:
1441 case Hexagon::A4_psxtht:
1442 case Hexagon::A4_psxthtnew:
1443 case Hexagon::A4_psxtbf:
1444 case Hexagon::A4_psxtbfnew:
1445 case Hexagon::A4_psxtbt:
1446 case Hexagon::A4_psxtbtnew:
1447 case Hexagon::A4_pzxtbf:
1448 case Hexagon::A4_pzxtbfnew:
1449 case Hexagon::A4_pzxtbt:
1450 case Hexagon::A4_pzxtbtnew:
1451 case Hexagon::A4_pzxthf:
1452 case Hexagon::A4_pzxthfnew:
1453 case Hexagon::A4_pzxtht:
1454 case Hexagon::A4_pzxthtnew:
1455 case Hexagon::A2_paddit:
1456 case Hexagon::A2_paddif:
1457 case Hexagon::C2_ccombinewt:
1458 case Hexagon::C2_ccombinewf:
1463 bool HexagonInstrInfo::
1464 isConditionalLoad (const MachineInstr* MI) const {
1465 switch (MI->getOpcode())
1467 default: return false;
1468 case Hexagon::L2_ploadrdt_io :
1469 case Hexagon::L2_ploadrdf_io:
1470 case Hexagon::L2_ploadrit_io:
1471 case Hexagon::L2_ploadrif_io:
1472 case Hexagon::L2_ploadrht_io:
1473 case Hexagon::L2_ploadrhf_io:
1474 case Hexagon::L2_ploadrbt_io:
1475 case Hexagon::L2_ploadrbf_io:
1476 case Hexagon::L2_ploadruht_io:
1477 case Hexagon::L2_ploadruhf_io:
1478 case Hexagon::L2_ploadrubt_io:
1479 case Hexagon::L2_ploadrubf_io:
1480 case Hexagon::L2_ploadrdt_pi:
1481 case Hexagon::L2_ploadrdf_pi:
1482 case Hexagon::L2_ploadrit_pi:
1483 case Hexagon::L2_ploadrif_pi:
1484 case Hexagon::L2_ploadrht_pi:
1485 case Hexagon::L2_ploadrhf_pi:
1486 case Hexagon::L2_ploadrbt_pi:
1487 case Hexagon::L2_ploadrbf_pi:
1488 case Hexagon::L2_ploadruht_pi:
1489 case Hexagon::L2_ploadruhf_pi:
1490 case Hexagon::L2_ploadrubt_pi:
1491 case Hexagon::L2_ploadrubf_pi:
1492 case Hexagon::L4_ploadrdt_rr:
1493 case Hexagon::L4_ploadrdf_rr:
1494 case Hexagon::L4_ploadrbt_rr:
1495 case Hexagon::L4_ploadrbf_rr:
1496 case Hexagon::L4_ploadrubt_rr:
1497 case Hexagon::L4_ploadrubf_rr:
1498 case Hexagon::L4_ploadrht_rr:
1499 case Hexagon::L4_ploadrhf_rr:
1500 case Hexagon::L4_ploadruht_rr:
1501 case Hexagon::L4_ploadruhf_rr:
1502 case Hexagon::L4_ploadrit_rr:
1503 case Hexagon::L4_ploadrif_rr:
1508 // Returns true if an instruction is a conditional store.
1510 // Note: It doesn't include conditional new-value stores as they can't be
1511 // converted to .new predicate.
1513 // p.new NV store [ if(p0.new)memw(R0+#0)=R2.new ]
1515 // / \ (not OK. it will cause new-value store to be
1516 // / X conditional on p0.new while R2 producer is
1519 // p.new store p.old NV store
1520 // [if(p0.new)memw(R0+#0)=R2] [if(p0)memw(R0+#0)=R2.new]
1526 // [if (p0)memw(R0+#0)=R2]
1528 // The above diagram shows the steps involoved in the conversion of a predicated
1529 // store instruction to its .new predicated new-value form.
1531 // The following set of instructions further explains the scenario where
1532 // conditional new-value store becomes invalid when promoted to .new predicate
1535 // { 1) if (p0) r0 = add(r1, r2)
1536 // 2) p0 = cmp.eq(r3, #0) }
1538 // 3) if (p0) memb(r1+#0) = r0 --> this instruction can't be grouped with
1539 // the first two instructions because in instr 1, r0 is conditional on old value
1540 // of p0 but its use in instr 3 is conditional on p0 modified by instr 2 which
1541 // is not valid for new-value stores.
1542 bool HexagonInstrInfo::
1543 isConditionalStore (const MachineInstr* MI) const {
1544 switch (MI->getOpcode())
1546 default: return false;
1547 case Hexagon::S4_storeirbt_io:
1548 case Hexagon::S4_storeirbf_io:
1549 case Hexagon::S4_pstorerbt_rr:
1550 case Hexagon::S4_pstorerbf_rr:
1551 case Hexagon::S2_pstorerbt_io:
1552 case Hexagon::S2_pstorerbf_io:
1553 case Hexagon::S2_pstorerbt_pi:
1554 case Hexagon::S2_pstorerbf_pi:
1555 case Hexagon::S2_pstorerdt_io:
1556 case Hexagon::S2_pstorerdf_io:
1557 case Hexagon::S4_pstorerdt_rr:
1558 case Hexagon::S4_pstorerdf_rr:
1559 case Hexagon::S2_pstorerdt_pi:
1560 case Hexagon::S2_pstorerdf_pi:
1561 case Hexagon::S2_pstorerht_io:
1562 case Hexagon::S2_pstorerhf_io:
1563 case Hexagon::S4_storeirht_io:
1564 case Hexagon::S4_storeirhf_io:
1565 case Hexagon::S4_pstorerht_rr:
1566 case Hexagon::S4_pstorerhf_rr:
1567 case Hexagon::S2_pstorerht_pi:
1568 case Hexagon::S2_pstorerhf_pi:
1569 case Hexagon::S2_pstorerit_io:
1570 case Hexagon::S2_pstorerif_io:
1571 case Hexagon::S4_storeirit_io:
1572 case Hexagon::S4_storeirif_io:
1573 case Hexagon::S4_pstorerit_rr:
1574 case Hexagon::S4_pstorerif_rr:
1575 case Hexagon::S2_pstorerit_pi:
1576 case Hexagon::S2_pstorerif_pi:
1578 // V4 global address store before promoting to dot new.
1579 case Hexagon::S4_pstorerdt_abs:
1580 case Hexagon::S4_pstorerdf_abs:
1581 case Hexagon::S4_pstorerbt_abs:
1582 case Hexagon::S4_pstorerbf_abs:
1583 case Hexagon::S4_pstorerht_abs:
1584 case Hexagon::S4_pstorerhf_abs:
1585 case Hexagon::S4_pstorerit_abs:
1586 case Hexagon::S4_pstorerif_abs:
1589 // Predicated new value stores (i.e. if (p0) memw(..)=r0.new) are excluded
1590 // from the "Conditional Store" list. Because a predicated new value store
1591 // would NOT be promoted to a double dot new store. See diagram below:
1592 // This function returns yes for those stores that are predicated but not
1593 // yet promoted to predicate dot new instructions.
1595 // +---------------------+
1596 // /-----| if (p0) memw(..)=r0 |---------\~
1597 // || +---------------------+ ||
1598 // promote || /\ /\ || promote
1600 // \||/ demote || \||/
1602 // +-------------------------+ || +-------------------------+
1603 // | if (p0.new) memw(..)=r0 | || | if (p0) memw(..)=r0.new |
1604 // +-------------------------+ || +-------------------------+
1607 // promote || \/ NOT possible
1611 // +-----------------------------+
1612 // | if (p0.new) memw(..)=r0.new |
1613 // +-----------------------------+
1614 // Double Dot New Store
1620 bool HexagonInstrInfo::isNewValueJump(const MachineInstr *MI) const {
1621 if (isNewValue(MI) && isBranch(MI))
1626 bool HexagonInstrInfo::isNewValueJump(Opcode_t Opcode) const {
1627 return isNewValue(Opcode) && get(Opcode).isBranch() && isPredicated(Opcode);
1630 bool HexagonInstrInfo::isPostIncrement (const MachineInstr* MI) const {
1631 return (getAddrMode(MI) == HexagonII::PostInc);
1634 // Returns true, if any one of the operands is a dot new
1635 // insn, whether it is predicated dot new or register dot new.
1636 bool HexagonInstrInfo::isDotNewInst (const MachineInstr* MI) const {
1637 return (isNewValueInst(MI) ||
1638 (isPredicated(MI) && isPredicatedNew(MI)));
1641 // Returns the most basic instruction for the .new predicated instructions and
1642 // new-value stores.
1643 // For example, all of the following instructions will be converted back to the
1644 // same instruction:
1645 // 1) if (p0.new) memw(R0+#0) = R1.new --->
1646 // 2) if (p0) memw(R0+#0)= R1.new -------> if (p0) memw(R0+#0) = R1
1647 // 3) if (p0.new) memw(R0+#0) = R1 --->
1650 int HexagonInstrInfo::GetDotOldOp(const int opc) const {
1652 if (isPredicated(NewOp) && isPredicatedNew(NewOp)) { // Get predicate old form
1653 NewOp = Hexagon::getPredOldOpcode(NewOp);
1654 assert(NewOp >= 0 &&
1655 "Couldn't change predicate new instruction to its old form.");
1658 if (isNewValueStore(NewOp)) { // Convert into non-new-value format
1659 NewOp = Hexagon::getNonNVStore(NewOp);
1660 assert(NewOp >= 0 && "Couldn't change new-value store to its old form.");
1665 // Return the new value instruction for a given store.
1666 int HexagonInstrInfo::GetDotNewOp(const MachineInstr* MI) const {
1667 int NVOpcode = Hexagon::getNewValueOpcode(MI->getOpcode());
1668 if (NVOpcode >= 0) // Valid new-value store instruction.
1671 switch (MI->getOpcode()) {
1672 default: llvm_unreachable("Unknown .new type");
1673 case Hexagon::S4_storerb_ur:
1674 return Hexagon::S4_storerbnew_ur;
1676 case Hexagon::S4_storerh_ur:
1677 return Hexagon::S4_storerhnew_ur;
1679 case Hexagon::S4_storeri_ur:
1680 return Hexagon::S4_storerinew_ur;
1682 case Hexagon::S2_storerb_pci:
1683 return Hexagon::S2_storerb_pci;
1685 case Hexagon::S2_storeri_pci:
1686 return Hexagon::S2_storeri_pci;
1688 case Hexagon::S2_storerh_pci:
1689 return Hexagon::S2_storerh_pci;
1691 case Hexagon::S2_storerd_pci:
1692 return Hexagon::S2_storerd_pci;
1694 case Hexagon::S2_storerf_pci:
1695 return Hexagon::S2_storerf_pci;
1700 // Return .new predicate version for an instruction.
1701 int HexagonInstrInfo::GetDotNewPredOp(MachineInstr *MI,
1702 const MachineBranchProbabilityInfo
1705 int NewOpcode = Hexagon::getPredNewOpcode(MI->getOpcode());
1706 if (NewOpcode >= 0) // Valid predicate new instruction
1709 switch (MI->getOpcode()) {
1710 default: llvm_unreachable("Unknown .new type");
1712 case Hexagon::J2_jumpt:
1713 case Hexagon::J2_jumpf:
1714 return getDotNewPredJumpOp(MI, MBPI);
1716 case Hexagon::J2_jumprt:
1717 return Hexagon::J2_jumptnewpt;
1719 case Hexagon::J2_jumprf:
1720 return Hexagon::J2_jumprfnewpt;
1722 case Hexagon::JMPrett:
1723 return Hexagon::J2_jumprtnewpt;
1725 case Hexagon::JMPretf:
1726 return Hexagon::J2_jumprfnewpt;
1729 // Conditional combine
1730 case Hexagon::C2_ccombinewt:
1731 return Hexagon::C2_ccombinewnewt;
1732 case Hexagon::C2_ccombinewf:
1733 return Hexagon::C2_ccombinewnewf;
1738 unsigned HexagonInstrInfo::getAddrMode(const MachineInstr* MI) const {
1739 const uint64_t F = MI->getDesc().TSFlags;
1741 return((F >> HexagonII::AddrModePos) & HexagonII::AddrModeMask);
1744 /// immediateExtend - Changes the instruction in place to one using an immediate
1746 void HexagonInstrInfo::immediateExtend(MachineInstr *MI) const {
1747 assert((isExtendable(MI)||isConstExtended(MI)) &&
1748 "Instruction must be extendable");
1749 // Find which operand is extendable.
1750 short ExtOpNum = getCExtOpNum(MI);
1751 MachineOperand &MO = MI->getOperand(ExtOpNum);
1752 // This needs to be something we understand.
1753 assert((MO.isMBB() || MO.isImm()) &&
1754 "Branch with unknown extendable field type");
1755 // Mark given operand as extended.
1756 MO.addTargetFlag(HexagonII::HMOTF_ConstExtended);
1759 DFAPacketizer *HexagonInstrInfo::CreateTargetScheduleState(
1760 const TargetSubtargetInfo &STI) const {
1761 const InstrItineraryData *II = STI.getInstrItineraryData();
1762 return static_cast<const HexagonSubtarget &>(STI).createDFAPacketizer(II);
1765 bool HexagonInstrInfo::isSchedulingBoundary(const MachineInstr *MI,
1766 const MachineBasicBlock *MBB,
1767 const MachineFunction &MF) const {
1768 // Debug info is never a scheduling boundary. It's necessary to be explicit
1769 // due to the special treatment of IT instructions below, otherwise a
1770 // dbg_value followed by an IT will result in the IT instruction being
1771 // considered a scheduling hazard, which is wrong. It should be the actual
1772 // instruction preceding the dbg_value instruction(s), just like it is
1773 // when debug info is not present.
1774 if (MI->isDebugValue())
1777 // Terminators and labels can't be scheduled around.
1778 if (MI->getDesc().isTerminator() || MI->isPosition() || MI->isInlineAsm())
1784 bool HexagonInstrInfo::isConstExtended(const MachineInstr *MI) const {
1785 const uint64_t F = MI->getDesc().TSFlags;
1786 unsigned isExtended = (F >> HexagonII::ExtendedPos) & HexagonII::ExtendedMask;
1787 if (isExtended) // Instruction must be extended.
1790 unsigned isExtendable =
1791 (F >> HexagonII::ExtendablePos) & HexagonII::ExtendableMask;
1795 short ExtOpNum = getCExtOpNum(MI);
1796 const MachineOperand &MO = MI->getOperand(ExtOpNum);
1797 // Use MO operand flags to determine if MO
1798 // has the HMOTF_ConstExtended flag set.
1799 if (MO.getTargetFlags() && HexagonII::HMOTF_ConstExtended)
1801 // If this is a Machine BB address we are talking about, and it is
1802 // not marked as extended, say so.
1806 // We could be using an instruction with an extendable immediate and shoehorn
1807 // a global address into it. If it is a global address it will be constant
1808 // extended. We do this for COMBINE.
1809 // We currently only handle isGlobal() because it is the only kind of
1810 // object we are going to end up with here for now.
1811 // In the future we probably should add isSymbol(), etc.
1812 if (MO.isGlobal() || MO.isSymbol() || MO.isBlockAddress() ||
1813 MO.isJTI() || MO.isCPI())
1816 // If the extendable operand is not 'Immediate' type, the instruction should
1817 // have 'isExtended' flag set.
1818 assert(MO.isImm() && "Extendable operand must be Immediate type");
1820 int MinValue = getMinValue(MI);
1821 int MaxValue = getMaxValue(MI);
1822 int ImmValue = MO.getImm();
1824 return (ImmValue < MinValue || ImmValue > MaxValue);
1827 // Return the number of bytes required to encode the instruction.
1828 // Hexagon instructions are fixed length, 4 bytes, unless they
1829 // use a constant extender, which requires another 4 bytes.
1830 // For debug instructions and prolog labels, return 0.
1831 unsigned HexagonInstrInfo::getSize(const MachineInstr *MI) const {
1833 if (MI->isDebugValue() || MI->isPosition())
1836 unsigned Size = MI->getDesc().getSize();
1838 // Assume the default insn size in case it cannot be determined
1839 // for whatever reason.
1840 Size = HEXAGON_INSTR_SIZE;
1842 if (isConstExtended(MI) || isExtended(MI))
1843 Size += HEXAGON_INSTR_SIZE;
1848 // Returns the opcode to use when converting MI, which is a conditional jump,
1849 // into a conditional instruction which uses the .new value of the predicate.
1850 // We also use branch probabilities to add a hint to the jump.
1852 HexagonInstrInfo::getDotNewPredJumpOp(MachineInstr *MI,
1854 MachineBranchProbabilityInfo *MBPI) const {
1856 // We assume that block can have at most two successors.
1858 MachineBasicBlock *Src = MI->getParent();
1859 MachineOperand *BrTarget = &MI->getOperand(1);
1860 MachineBasicBlock *Dst = BrTarget->getMBB();
1862 const BranchProbability Prediction = MBPI->getEdgeProbability(Src, Dst);
1863 if (Prediction >= BranchProbability(1,2))
1866 switch (MI->getOpcode()) {
1867 case Hexagon::J2_jumpt:
1868 return taken ? Hexagon::J2_jumptnewpt : Hexagon::J2_jumptnew;
1869 case Hexagon::J2_jumpf:
1870 return taken ? Hexagon::J2_jumpfnewpt : Hexagon::J2_jumpfnew;
1873 llvm_unreachable("Unexpected jump instruction.");
1876 // Returns true if a particular operand is extendable for an instruction.
1877 bool HexagonInstrInfo::isOperandExtended(const MachineInstr *MI,
1878 unsigned short OperandNum) const {
1879 const uint64_t F = MI->getDesc().TSFlags;
1881 return ((F >> HexagonII::ExtendableOpPos) & HexagonII::ExtendableOpMask)
1885 // Returns Operand Index for the constant extended instruction.
1886 unsigned short HexagonInstrInfo::getCExtOpNum(const MachineInstr *MI) const {
1887 const uint64_t F = MI->getDesc().TSFlags;
1888 return ((F >> HexagonII::ExtendableOpPos) & HexagonII::ExtendableOpMask);
1891 // Returns the min value that doesn't need to be extended.
1892 int HexagonInstrInfo::getMinValue(const MachineInstr *MI) const {
1893 const uint64_t F = MI->getDesc().TSFlags;
1894 unsigned isSigned = (F >> HexagonII::ExtentSignedPos)
1895 & HexagonII::ExtentSignedMask;
1896 unsigned bits = (F >> HexagonII::ExtentBitsPos)
1897 & HexagonII::ExtentBitsMask;
1899 if (isSigned) // if value is signed
1900 return -1U << (bits - 1);
1905 // Returns the max value that doesn't need to be extended.
1906 int HexagonInstrInfo::getMaxValue(const MachineInstr *MI) const {
1907 const uint64_t F = MI->getDesc().TSFlags;
1908 unsigned isSigned = (F >> HexagonII::ExtentSignedPos)
1909 & HexagonII::ExtentSignedMask;
1910 unsigned bits = (F >> HexagonII::ExtentBitsPos)
1911 & HexagonII::ExtentBitsMask;
1913 if (isSigned) // if value is signed
1914 return ~(-1U << (bits - 1));
1916 return ~(-1U << bits);
1919 // Returns true if an instruction can be converted into a non-extended
1920 // equivalent instruction.
1921 bool HexagonInstrInfo::NonExtEquivalentExists (const MachineInstr *MI) const {
1924 // Check if the instruction has a register form that uses register in place
1925 // of the extended operand, if so return that as the non-extended form.
1926 if (Hexagon::getRegForm(MI->getOpcode()) >= 0)
1929 if (MI->getDesc().mayLoad() || MI->getDesc().mayStore()) {
1930 // Check addressing mode and retrieve non-ext equivalent instruction.
1932 switch (getAddrMode(MI)) {
1933 case HexagonII::Absolute :
1934 // Load/store with absolute addressing mode can be converted into
1935 // base+offset mode.
1936 NonExtOpcode = Hexagon::getBasedWithImmOffset(MI->getOpcode());
1938 case HexagonII::BaseImmOffset :
1939 // Load/store with base+offset addressing mode can be converted into
1940 // base+register offset addressing mode. However left shift operand should
1942 NonExtOpcode = Hexagon::getBaseWithRegOffset(MI->getOpcode());
1947 if (NonExtOpcode < 0)
1954 // Returns opcode of the non-extended equivalent instruction.
1955 short HexagonInstrInfo::getNonExtOpcode (const MachineInstr *MI) const {
1957 // Check if the instruction has a register form that uses register in place
1958 // of the extended operand, if so return that as the non-extended form.
1959 short NonExtOpcode = Hexagon::getRegForm(MI->getOpcode());
1960 if (NonExtOpcode >= 0)
1961 return NonExtOpcode;
1963 if (MI->getDesc().mayLoad() || MI->getDesc().mayStore()) {
1964 // Check addressing mode and retrieve non-ext equivalent instruction.
1965 switch (getAddrMode(MI)) {
1966 case HexagonII::Absolute :
1967 return Hexagon::getBasedWithImmOffset(MI->getOpcode());
1968 case HexagonII::BaseImmOffset :
1969 return Hexagon::getBaseWithRegOffset(MI->getOpcode());
1977 bool HexagonInstrInfo::PredOpcodeHasJMP_c(Opcode_t Opcode) const {
1978 return (Opcode == Hexagon::J2_jumpt) ||
1979 (Opcode == Hexagon::J2_jumpf) ||
1980 (Opcode == Hexagon::J2_jumptnewpt) ||
1981 (Opcode == Hexagon::J2_jumpfnewpt) ||
1982 (Opcode == Hexagon::J2_jumpt) ||
1983 (Opcode == Hexagon::J2_jumpf);
1986 bool HexagonInstrInfo::predOpcodeHasNot(
1987 const SmallVectorImpl<MachineOperand> &Cond) const {
1988 if (Cond.empty() || !isPredicated(Cond[0].getImm()))
1990 return !isPredicatedTrue(Cond[0].getImm());
1993 bool HexagonInstrInfo::isEndLoopN(Opcode_t Opcode) const {
1994 return (Opcode == Hexagon::ENDLOOP0 ||
1995 Opcode == Hexagon::ENDLOOP1);
1998 bool HexagonInstrInfo::getPredReg(const SmallVectorImpl<MachineOperand> &Cond,
1999 unsigned &PredReg, unsigned &PredRegPos,
2000 unsigned &PredRegFlags) const {
2003 assert(Cond.size() == 2);
2004 if (isNewValueJump(Cond[0].getImm()) || Cond[1].isMBB()) {
2005 DEBUG(dbgs() << "No predregs for new-value jumps/endloop");
2008 PredReg = Cond[1].getReg();
2010 // See IfConversion.cpp why we add RegState::Implicit | RegState::Undef
2012 if (Cond[1].isImplicit())
2013 PredRegFlags = RegState::Implicit;
2014 if (Cond[1].isUndef())
2015 PredRegFlags |= RegState::Undef;