1 //===-- HexagonInstrInfo.cpp - Hexagon Instruction Information ------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Hexagon implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "HexagonInstrInfo.h"
16 #include "HexagonRegisterInfo.h"
17 #include "HexagonSubtarget.h"
18 #include "llvm/ADT/STLExtras.h"
19 #include "llvm/ADT/SmallVector.h"
20 #include "llvm/CodeGen/DFAPacketizer.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineMemOperand.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/PseudoSourceValue.h"
26 #include "llvm/Support/Debug.h"
27 #include "llvm/Support/MathExtras.h"
28 #include "llvm/Support/raw_ostream.h"
32 #define DEBUG_TYPE "hexagon-instrinfo"
34 #define GET_INSTRINFO_CTOR_DTOR
35 #define GET_INSTRMAP_INFO
36 #include "HexagonGenInstrInfo.inc"
37 #include "HexagonGenDFAPacketizer.inc"
40 /// Constants for Hexagon instructions.
42 const int Hexagon_MEMW_OFFSET_MAX = 4095;
43 const int Hexagon_MEMW_OFFSET_MIN = -4096;
44 const int Hexagon_MEMD_OFFSET_MAX = 8191;
45 const int Hexagon_MEMD_OFFSET_MIN = -8192;
46 const int Hexagon_MEMH_OFFSET_MAX = 2047;
47 const int Hexagon_MEMH_OFFSET_MIN = -2048;
48 const int Hexagon_MEMB_OFFSET_MAX = 1023;
49 const int Hexagon_MEMB_OFFSET_MIN = -1024;
50 const int Hexagon_ADDI_OFFSET_MAX = 32767;
51 const int Hexagon_ADDI_OFFSET_MIN = -32768;
52 const int Hexagon_MEMD_AUTOINC_MAX = 56;
53 const int Hexagon_MEMD_AUTOINC_MIN = -64;
54 const int Hexagon_MEMW_AUTOINC_MAX = 28;
55 const int Hexagon_MEMW_AUTOINC_MIN = -32;
56 const int Hexagon_MEMH_AUTOINC_MAX = 14;
57 const int Hexagon_MEMH_AUTOINC_MIN = -16;
58 const int Hexagon_MEMB_AUTOINC_MAX = 7;
59 const int Hexagon_MEMB_AUTOINC_MIN = -8;
61 // Pin the vtable to this file.
62 void HexagonInstrInfo::anchor() {}
64 HexagonInstrInfo::HexagonInstrInfo(HexagonSubtarget &ST)
65 : HexagonGenInstrInfo(Hexagon::ADJCALLSTACKDOWN, Hexagon::ADJCALLSTACKUP),
66 RI(), Subtarget(ST) {}
68 /// isLoadFromStackSlot - If the specified machine instruction is a direct
69 /// load from a stack slot, return the virtual or physical register number of
70 /// the destination along with the FrameIndex of the loaded stack slot. If
71 /// not, return 0. This predicate must return 0 if the instruction has
72 /// any side effects other than loading from the stack slot.
73 unsigned HexagonInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
74 int &FrameIndex) const {
77 switch (MI->getOpcode()) {
79 case Hexagon::L2_loadri_io:
80 case Hexagon::L2_loadrd_io:
81 case Hexagon::L2_loadrh_io:
82 case Hexagon::L2_loadrb_io:
83 case Hexagon::L2_loadrub_io:
84 if (MI->getOperand(2).isFI() &&
85 MI->getOperand(1).isImm() && (MI->getOperand(1).getImm() == 0)) {
86 FrameIndex = MI->getOperand(2).getIndex();
87 return MI->getOperand(0).getReg();
95 /// isStoreToStackSlot - If the specified machine instruction is a direct
96 /// store to a stack slot, return the virtual or physical register number of
97 /// the source reg along with the FrameIndex of the loaded stack slot. If
98 /// not, return 0. This predicate must return 0 if the instruction has
99 /// any side effects other than storing to the stack slot.
100 unsigned HexagonInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
101 int &FrameIndex) const {
102 switch (MI->getOpcode()) {
104 case Hexagon::S2_storeri_io:
105 case Hexagon::S2_storerd_io:
106 case Hexagon::S2_storerh_io:
107 case Hexagon::S2_storerb_io:
108 if (MI->getOperand(2).isFI() &&
109 MI->getOperand(1).isImm() && (MI->getOperand(1).getImm() == 0)) {
110 FrameIndex = MI->getOperand(0).getIndex();
111 return MI->getOperand(2).getReg();
120 HexagonInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
121 MachineBasicBlock *FBB,
122 const SmallVectorImpl<MachineOperand> &Cond,
125 int BOpc = Hexagon::J2_jump;
126 int BccOpc = Hexagon::J2_jumpt;
128 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
131 // Check if ReverseBranchCondition has asked to reverse this branch
132 // If we want to reverse the branch an odd number of times, we want
134 if (!Cond.empty() && Cond[0].isImm() && Cond[0].getImm() == 0) {
135 BccOpc = Hexagon::J2_jumpf;
141 // Due to a bug in TailMerging/CFG Optimization, we need to add a
142 // special case handling of a predicated jump followed by an
143 // unconditional jump. If not, Tail Merging and CFG Optimization go
144 // into an infinite loop.
145 MachineBasicBlock *NewTBB, *NewFBB;
146 SmallVector<MachineOperand, 4> Cond;
147 MachineInstr *Term = MBB.getFirstTerminator();
148 if (isPredicated(Term) && !AnalyzeBranch(MBB, NewTBB, NewFBB, Cond,
150 MachineBasicBlock *NextBB =
151 std::next(MachineFunction::iterator(&MBB));
152 if (NewTBB == NextBB) {
153 ReverseBranchCondition(Cond);
155 return InsertBranch(MBB, TBB, nullptr, Cond, DL);
158 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
160 // If Cond[0] is a basic block, insert ENDLOOP0.
162 BuildMI(&MBB, DL, get(Hexagon::ENDLOOP0)).addMBB(Cond[0].getMBB());
165 get(BccOpc)).addReg(Cond[regPos].getReg()).addMBB(TBB);
170 // We don't handle ENDLOOP0 with a conditional branch in AnalyzeBranch.
171 BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[regPos].getReg()).addMBB(TBB);
172 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
177 bool HexagonInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
178 MachineBasicBlock *&TBB,
179 MachineBasicBlock *&FBB,
180 SmallVectorImpl<MachineOperand> &Cond,
181 bool AllowModify) const {
185 // If the block has no terminators, it just falls into the block after it.
186 MachineBasicBlock::instr_iterator I = MBB.instr_end();
187 if (I == MBB.instr_begin())
190 // A basic block may looks like this:
200 // It has two succs but does not have a terminator
201 // Don't know how to handle it.
206 } while (I != MBB.instr_begin());
211 while (I->isDebugValue()) {
212 if (I == MBB.instr_begin())
217 bool JumpToBlock = I->getOpcode() == Hexagon::J2_jump &&
218 I->getOperand(0).isMBB();
219 // Delete the JMP if it's equivalent to a fall-through.
220 if (AllowModify && JumpToBlock &&
221 MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
222 DEBUG(dbgs()<< "\nErasing the jump to successor block\n";);
223 I->eraseFromParent();
225 if (I == MBB.instr_begin())
229 if (!isUnpredicatedTerminator(I))
232 // Get the last instruction in the block.
233 MachineInstr *LastInst = I;
234 MachineInstr *SecondLastInst = nullptr;
235 // Find one more terminator if present.
237 if (&*I != LastInst && !I->isBundle() && isUnpredicatedTerminator(I)) {
241 // This is a third branch.
244 if (I == MBB.instr_begin())
249 int LastOpcode = LastInst->getOpcode();
250 int SecLastOpcode = SecondLastInst ? SecondLastInst->getOpcode() : 0;
251 // If the branch target is not a basic block, it could be a tail call.
252 // (It is, if the target is a function.)
253 if (LastOpcode == Hexagon::J2_jump && !LastInst->getOperand(0).isMBB())
255 if (SecLastOpcode == Hexagon::J2_jump &&
256 !SecondLastInst->getOperand(0).isMBB())
259 bool LastOpcodeHasJMP_c = PredOpcodeHasJMP_c(LastOpcode);
260 bool LastOpcodeHasNot = PredOpcodeHasNot(LastOpcode);
262 // If there is only one terminator instruction, process it.
263 if (LastInst && !SecondLastInst) {
264 if (LastOpcode == Hexagon::J2_jump) {
265 TBB = LastInst->getOperand(0).getMBB();
268 if (LastOpcode == Hexagon::ENDLOOP0) {
269 TBB = LastInst->getOperand(0).getMBB();
270 Cond.push_back(LastInst->getOperand(0));
273 if (LastOpcodeHasJMP_c) {
274 TBB = LastInst->getOperand(1).getMBB();
275 if (LastOpcodeHasNot) {
276 Cond.push_back(MachineOperand::CreateImm(0));
278 Cond.push_back(LastInst->getOperand(0));
281 // Otherwise, don't know what this is.
285 bool SecLastOpcodeHasJMP_c = PredOpcodeHasJMP_c(SecLastOpcode);
286 bool SecLastOpcodeHasNot = PredOpcodeHasNot(SecLastOpcode);
287 if (SecLastOpcodeHasJMP_c && (LastOpcode == Hexagon::J2_jump)) {
288 TBB = SecondLastInst->getOperand(1).getMBB();
289 if (SecLastOpcodeHasNot)
290 Cond.push_back(MachineOperand::CreateImm(0));
291 Cond.push_back(SecondLastInst->getOperand(0));
292 FBB = LastInst->getOperand(0).getMBB();
296 // If the block ends with two Hexagon:JMPs, handle it. The second one is not
297 // executed, so remove it.
298 if (SecLastOpcode == Hexagon::J2_jump && LastOpcode == Hexagon::J2_jump) {
299 TBB = SecondLastInst->getOperand(0).getMBB();
302 I->eraseFromParent();
306 // If the block ends with an ENDLOOP, and JMP, handle it.
307 if (SecLastOpcode == Hexagon::ENDLOOP0 &&
308 LastOpcode == Hexagon::J2_jump) {
309 TBB = SecondLastInst->getOperand(0).getMBB();
310 Cond.push_back(SecondLastInst->getOperand(0));
311 FBB = LastInst->getOperand(0).getMBB();
315 // Otherwise, can't handle this.
320 unsigned HexagonInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
321 MachineBasicBlock::iterator I = MBB.end();
322 if (I == MBB.begin()) return 0;
324 unsigned Opc1 = I->getOpcode();
326 case Hexagon::J2_jump:
327 case Hexagon::J2_jumpt:
328 case Hexagon::J2_jumpf:
329 case Hexagon::ENDLOOP0:
330 I->eraseFromParent();
338 if (I == MBB.begin()) return 1;
340 unsigned Opc2 = I->getOpcode();
342 case Hexagon::J2_jumpt:
343 case Hexagon::J2_jumpf:
344 case Hexagon::ENDLOOP0:
345 I->eraseFromParent();
353 /// \brief For a comparison instruction, return the source registers in
354 /// \p SrcReg and \p SrcReg2 if having two register operands, and the value it
355 /// compares against in CmpValue. Return true if the comparison instruction
357 bool HexagonInstrInfo::analyzeCompare(const MachineInstr *MI,
358 unsigned &SrcReg, unsigned &SrcReg2,
359 int &Mask, int &Value) const {
360 unsigned Opc = MI->getOpcode();
362 // Set mask and the first source register.
364 case Hexagon::C2_cmpeqp:
365 case Hexagon::C2_cmpeqi:
366 case Hexagon::C2_cmpeq:
367 case Hexagon::C2_cmpgtp:
368 case Hexagon::C2_cmpgtup:
369 case Hexagon::C2_cmpgtui:
370 case Hexagon::C2_cmpgtu:
371 case Hexagon::C2_cmpgti:
372 case Hexagon::C2_cmpgt:
373 SrcReg = MI->getOperand(1).getReg();
376 case Hexagon::A4_cmpbeqi:
377 case Hexagon::A4_cmpbeq:
378 case Hexagon::A4_cmpbgtui:
379 case Hexagon::A4_cmpbgtu:
380 case Hexagon::A4_cmpbgt:
381 SrcReg = MI->getOperand(1).getReg();
384 case Hexagon::A4_cmpheqi:
385 case Hexagon::A4_cmpheq:
386 case Hexagon::A4_cmphgtui:
387 case Hexagon::A4_cmphgtu:
388 case Hexagon::A4_cmphgt:
389 SrcReg = MI->getOperand(1).getReg();
394 // Set the value/second source register.
396 case Hexagon::C2_cmpeqp:
397 case Hexagon::C2_cmpeq:
398 case Hexagon::C2_cmpgtp:
399 case Hexagon::C2_cmpgtup:
400 case Hexagon::C2_cmpgtu:
401 case Hexagon::C2_cmpgt:
402 case Hexagon::A4_cmpbeq:
403 case Hexagon::A4_cmpbgtu:
404 case Hexagon::A4_cmpbgt:
405 case Hexagon::A4_cmpheq:
406 case Hexagon::A4_cmphgtu:
407 case Hexagon::A4_cmphgt:
408 SrcReg2 = MI->getOperand(2).getReg();
411 case Hexagon::C2_cmpeqi:
412 case Hexagon::C2_cmpgtui:
413 case Hexagon::C2_cmpgti:
414 case Hexagon::A4_cmpbeqi:
415 case Hexagon::A4_cmpbgtui:
416 case Hexagon::A4_cmpheqi:
417 case Hexagon::A4_cmphgtui:
419 Value = MI->getOperand(2).getImm();
427 void HexagonInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
428 MachineBasicBlock::iterator I, DebugLoc DL,
429 unsigned DestReg, unsigned SrcReg,
430 bool KillSrc) const {
431 if (Hexagon::IntRegsRegClass.contains(SrcReg, DestReg)) {
432 BuildMI(MBB, I, DL, get(Hexagon::A2_tfr), DestReg).addReg(SrcReg);
435 if (Hexagon::DoubleRegsRegClass.contains(SrcReg, DestReg)) {
436 BuildMI(MBB, I, DL, get(Hexagon::A2_tfrp), DestReg).addReg(SrcReg);
439 if (Hexagon::PredRegsRegClass.contains(SrcReg, DestReg)) {
440 // Map Pd = Ps to Pd = or(Ps, Ps).
441 BuildMI(MBB, I, DL, get(Hexagon::C2_or),
442 DestReg).addReg(SrcReg).addReg(SrcReg);
445 if (Hexagon::DoubleRegsRegClass.contains(DestReg) &&
446 Hexagon::IntRegsRegClass.contains(SrcReg)) {
447 // We can have an overlap between single and double reg: r1:0 = r0.
448 if(SrcReg == RI.getSubReg(DestReg, Hexagon::subreg_loreg)) {
450 BuildMI(MBB, I, DL, get(Hexagon::A2_tfrsi), (RI.getSubReg(DestReg,
451 Hexagon::subreg_hireg))).addImm(0);
453 // r1:0 = r1 or no overlap.
454 BuildMI(MBB, I, DL, get(Hexagon::A2_tfr), (RI.getSubReg(DestReg,
455 Hexagon::subreg_loreg))).addReg(SrcReg);
456 BuildMI(MBB, I, DL, get(Hexagon::A2_tfrsi), (RI.getSubReg(DestReg,
457 Hexagon::subreg_hireg))).addImm(0);
461 if (Hexagon::CtrRegsRegClass.contains(DestReg) &&
462 Hexagon::IntRegsRegClass.contains(SrcReg)) {
463 BuildMI(MBB, I, DL, get(Hexagon::A2_tfrrcr), DestReg).addReg(SrcReg);
466 if (Hexagon::PredRegsRegClass.contains(SrcReg) &&
467 Hexagon::IntRegsRegClass.contains(DestReg)) {
468 BuildMI(MBB, I, DL, get(Hexagon::C2_tfrpr), DestReg).
469 addReg(SrcReg, getKillRegState(KillSrc));
472 if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
473 Hexagon::PredRegsRegClass.contains(DestReg)) {
474 BuildMI(MBB, I, DL, get(Hexagon::C2_tfrrp), DestReg).
475 addReg(SrcReg, getKillRegState(KillSrc));
479 llvm_unreachable("Unimplemented");
483 void HexagonInstrInfo::
484 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
485 unsigned SrcReg, bool isKill, int FI,
486 const TargetRegisterClass *RC,
487 const TargetRegisterInfo *TRI) const {
489 DebugLoc DL = MBB.findDebugLoc(I);
490 MachineFunction &MF = *MBB.getParent();
491 MachineFrameInfo &MFI = *MF.getFrameInfo();
492 unsigned Align = MFI.getObjectAlignment(FI);
494 MachineMemOperand *MMO =
495 MF.getMachineMemOperand(
496 MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
497 MachineMemOperand::MOStore,
498 MFI.getObjectSize(FI),
501 if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {
502 BuildMI(MBB, I, DL, get(Hexagon::S2_storeri_io))
503 .addFrameIndex(FI).addImm(0)
504 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
505 } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {
506 BuildMI(MBB, I, DL, get(Hexagon::S2_storerd_io))
507 .addFrameIndex(FI).addImm(0)
508 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
509 } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {
510 BuildMI(MBB, I, DL, get(Hexagon::STriw_pred))
511 .addFrameIndex(FI).addImm(0)
512 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
514 llvm_unreachable("Unimplemented");
519 void HexagonInstrInfo::storeRegToAddr(
520 MachineFunction &MF, unsigned SrcReg,
522 SmallVectorImpl<MachineOperand> &Addr,
523 const TargetRegisterClass *RC,
524 SmallVectorImpl<MachineInstr*> &NewMIs) const
526 llvm_unreachable("Unimplemented");
530 void HexagonInstrInfo::
531 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
532 unsigned DestReg, int FI,
533 const TargetRegisterClass *RC,
534 const TargetRegisterInfo *TRI) const {
535 DebugLoc DL = MBB.findDebugLoc(I);
536 MachineFunction &MF = *MBB.getParent();
537 MachineFrameInfo &MFI = *MF.getFrameInfo();
538 unsigned Align = MFI.getObjectAlignment(FI);
540 MachineMemOperand *MMO =
541 MF.getMachineMemOperand(
542 MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
543 MachineMemOperand::MOLoad,
544 MFI.getObjectSize(FI),
546 if (RC == &Hexagon::IntRegsRegClass) {
547 BuildMI(MBB, I, DL, get(Hexagon::L2_loadri_io), DestReg)
548 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
549 } else if (RC == &Hexagon::DoubleRegsRegClass) {
550 BuildMI(MBB, I, DL, get(Hexagon::L2_loadrd_io), DestReg)
551 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
552 } else if (RC == &Hexagon::PredRegsRegClass) {
553 BuildMI(MBB, I, DL, get(Hexagon::LDriw_pred), DestReg)
554 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
556 llvm_unreachable("Can't store this register to stack slot");
561 void HexagonInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
562 SmallVectorImpl<MachineOperand> &Addr,
563 const TargetRegisterClass *RC,
564 SmallVectorImpl<MachineInstr*> &NewMIs) const {
565 llvm_unreachable("Unimplemented");
568 HexagonInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
569 const HexagonRegisterInfo &TRI = getRegisterInfo();
570 MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
571 MachineBasicBlock &MBB = *MI->getParent();
572 DebugLoc DL = MI->getDebugLoc();
573 unsigned Opc = MI->getOpcode();
576 case Hexagon::ALIGNA:
577 BuildMI(MBB, MI, DL, get(Hexagon::A2_andir), MI->getOperand(0).getReg())
578 .addReg(TRI.getFrameRegister())
579 .addImm(-MI->getOperand(1).getImm());
582 case Hexagon::TFR_PdTrue: {
583 unsigned Reg = MI->getOperand(0).getReg();
584 BuildMI(MBB, MI, DL, get(Hexagon::C2_orn), Reg)
585 .addReg(Reg, RegState::Undef)
586 .addReg(Reg, RegState::Undef);
590 case Hexagon::TFR_PdFalse: {
591 unsigned Reg = MI->getOperand(0).getReg();
592 BuildMI(MBB, MI, DL, get(Hexagon::C2_andn), Reg)
593 .addReg(Reg, RegState::Undef)
594 .addReg(Reg, RegState::Undef);
598 case Hexagon::VMULW: {
599 // Expand a 64-bit vector multiply into 2 32-bit scalar multiplies.
600 unsigned DstReg = MI->getOperand(0).getReg();
601 unsigned Src1Reg = MI->getOperand(1).getReg();
602 unsigned Src2Reg = MI->getOperand(2).getReg();
603 unsigned Src1SubHi = TRI.getSubReg(Src1Reg, Hexagon::subreg_hireg);
604 unsigned Src1SubLo = TRI.getSubReg(Src1Reg, Hexagon::subreg_loreg);
605 unsigned Src2SubHi = TRI.getSubReg(Src2Reg, Hexagon::subreg_hireg);
606 unsigned Src2SubLo = TRI.getSubReg(Src2Reg, Hexagon::subreg_loreg);
607 BuildMI(MBB, MI, MI->getDebugLoc(), get(Hexagon::M2_mpyi),
608 TRI.getSubReg(DstReg, Hexagon::subreg_hireg)).addReg(Src1SubHi)
610 BuildMI(MBB, MI, MI->getDebugLoc(), get(Hexagon::M2_mpyi),
611 TRI.getSubReg(DstReg, Hexagon::subreg_loreg)).addReg(Src1SubLo)
614 MRI.clearKillFlags(Src1SubHi);
615 MRI.clearKillFlags(Src1SubLo);
616 MRI.clearKillFlags(Src2SubHi);
617 MRI.clearKillFlags(Src2SubLo);
620 case Hexagon::VMULW_ACC: {
621 // Expand 64-bit vector multiply with addition into 2 scalar multiplies.
622 unsigned DstReg = MI->getOperand(0).getReg();
623 unsigned Src1Reg = MI->getOperand(1).getReg();
624 unsigned Src2Reg = MI->getOperand(2).getReg();
625 unsigned Src3Reg = MI->getOperand(3).getReg();
626 unsigned Src1SubHi = TRI.getSubReg(Src1Reg, Hexagon::subreg_hireg);
627 unsigned Src1SubLo = TRI.getSubReg(Src1Reg, Hexagon::subreg_loreg);
628 unsigned Src2SubHi = TRI.getSubReg(Src2Reg, Hexagon::subreg_hireg);
629 unsigned Src2SubLo = TRI.getSubReg(Src2Reg, Hexagon::subreg_loreg);
630 unsigned Src3SubHi = TRI.getSubReg(Src3Reg, Hexagon::subreg_hireg);
631 unsigned Src3SubLo = TRI.getSubReg(Src3Reg, Hexagon::subreg_loreg);
632 BuildMI(MBB, MI, MI->getDebugLoc(), get(Hexagon::M2_maci),
633 TRI.getSubReg(DstReg, Hexagon::subreg_hireg)).addReg(Src1SubHi)
634 .addReg(Src2SubHi).addReg(Src3SubHi);
635 BuildMI(MBB, MI, MI->getDebugLoc(), get(Hexagon::M2_maci),
636 TRI.getSubReg(DstReg, Hexagon::subreg_loreg)).addReg(Src1SubLo)
637 .addReg(Src2SubLo).addReg(Src3SubLo);
639 MRI.clearKillFlags(Src1SubHi);
640 MRI.clearKillFlags(Src1SubLo);
641 MRI.clearKillFlags(Src2SubHi);
642 MRI.clearKillFlags(Src2SubLo);
643 MRI.clearKillFlags(Src3SubHi);
644 MRI.clearKillFlags(Src3SubLo);
647 case Hexagon::TCRETURNi:
648 MI->setDesc(get(Hexagon::J2_jump));
650 case Hexagon::TCRETURNr:
651 MI->setDesc(get(Hexagon::J2_jumpr));
658 MachineInstr *HexagonInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
660 ArrayRef<unsigned> Ops,
662 // Hexagon_TODO: Implement.
666 unsigned HexagonInstrInfo::createVR(MachineFunction* MF, MVT VT) const {
668 MachineRegisterInfo &RegInfo = MF->getRegInfo();
669 const TargetRegisterClass *TRC;
671 TRC = &Hexagon::PredRegsRegClass;
672 } else if (VT == MVT::i32 || VT == MVT::f32) {
673 TRC = &Hexagon::IntRegsRegClass;
674 } else if (VT == MVT::i64 || VT == MVT::f64) {
675 TRC = &Hexagon::DoubleRegsRegClass;
677 llvm_unreachable("Cannot handle this register class");
680 unsigned NewReg = RegInfo.createVirtualRegister(TRC);
684 bool HexagonInstrInfo::isExtendable(const MachineInstr *MI) const {
685 const MCInstrDesc &MID = MI->getDesc();
686 const uint64_t F = MID.TSFlags;
687 if ((F >> HexagonII::ExtendablePos) & HexagonII::ExtendableMask)
690 // TODO: This is largely obsolete now. Will need to be removed
691 // in consecutive patches.
692 switch(MI->getOpcode()) {
693 // TFR_FI Remains a special case.
694 case Hexagon::TFR_FI:
702 // This returns true in two cases:
703 // - The OP code itself indicates that this is an extended instruction.
704 // - One of MOs has been marked with HMOTF_ConstExtended flag.
705 bool HexagonInstrInfo::isExtended(const MachineInstr *MI) const {
706 // First check if this is permanently extended op code.
707 const uint64_t F = MI->getDesc().TSFlags;
708 if ((F >> HexagonII::ExtendedPos) & HexagonII::ExtendedMask)
710 // Use MO operand flags to determine if one of MI's operands
711 // has HMOTF_ConstExtended flag set.
712 for (MachineInstr::const_mop_iterator I = MI->operands_begin(),
713 E = MI->operands_end(); I != E; ++I) {
714 if (I->getTargetFlags() && HexagonII::HMOTF_ConstExtended)
720 bool HexagonInstrInfo::isBranch (const MachineInstr *MI) const {
721 return MI->getDesc().isBranch();
724 bool HexagonInstrInfo::isNewValueInst(const MachineInstr *MI) const {
725 if (isNewValueJump(MI))
728 if (isNewValueStore(MI))
734 bool HexagonInstrInfo::isSaveCalleeSavedRegsCall(const MachineInstr *MI) const {
735 return MI->getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4;
738 bool HexagonInstrInfo::isPredicable(MachineInstr *MI) const {
739 bool isPred = MI->getDesc().isPredicable();
744 const int Opc = MI->getOpcode();
747 case Hexagon::A2_tfrsi:
748 return (isOperandExtended(MI, 1) && isConstExtended(MI)) || isInt<12>(MI->getOperand(1).getImm());
750 case Hexagon::S2_storerd_io:
751 return isShiftedUInt<6,3>(MI->getOperand(1).getImm());
753 case Hexagon::S2_storeri_io:
754 case Hexagon::S2_storerinew_io:
755 return isShiftedUInt<6,2>(MI->getOperand(1).getImm());
757 case Hexagon::S2_storerh_io:
758 case Hexagon::S2_storerhnew_io:
759 return isShiftedUInt<6,1>(MI->getOperand(1).getImm());
761 case Hexagon::S2_storerb_io:
762 case Hexagon::S2_storerbnew_io:
763 return isUInt<6>(MI->getOperand(1).getImm());
765 case Hexagon::L2_loadrd_io:
766 return isShiftedUInt<6,3>(MI->getOperand(2).getImm());
768 case Hexagon::L2_loadri_io:
769 return isShiftedUInt<6,2>(MI->getOperand(2).getImm());
771 case Hexagon::L2_loadrh_io:
772 case Hexagon::L2_loadruh_io:
773 return isShiftedUInt<6,1>(MI->getOperand(2).getImm());
775 case Hexagon::L2_loadrb_io:
776 case Hexagon::L2_loadrub_io:
777 return isUInt<6>(MI->getOperand(2).getImm());
779 case Hexagon::L2_loadrd_pi:
780 return isShiftedInt<4,3>(MI->getOperand(3).getImm());
782 case Hexagon::L2_loadri_pi:
783 return isShiftedInt<4,2>(MI->getOperand(3).getImm());
785 case Hexagon::L2_loadrh_pi:
786 case Hexagon::L2_loadruh_pi:
787 return isShiftedInt<4,1>(MI->getOperand(3).getImm());
789 case Hexagon::L2_loadrb_pi:
790 case Hexagon::L2_loadrub_pi:
791 return isInt<4>(MI->getOperand(3).getImm());
793 case Hexagon::S4_storeirb_io:
794 case Hexagon::S4_storeirh_io:
795 case Hexagon::S4_storeiri_io:
796 return (isUInt<6>(MI->getOperand(1).getImm()) &&
797 isInt<6>(MI->getOperand(2).getImm()));
799 case Hexagon::A2_addi:
800 return isInt<8>(MI->getOperand(2).getImm());
802 case Hexagon::A2_aslh:
803 case Hexagon::A2_asrh:
804 case Hexagon::A2_sxtb:
805 case Hexagon::A2_sxth:
806 case Hexagon::A2_zxtb:
807 case Hexagon::A2_zxth:
814 // This function performs the following inversiones:
819 unsigned HexagonInstrInfo::getInvertedPredicatedOpcode(const int Opc) const {
821 InvPredOpcode = isPredicatedTrue(Opc) ? Hexagon::getFalsePredOpcode(Opc)
822 : Hexagon::getTruePredOpcode(Opc);
823 if (InvPredOpcode >= 0) // Valid instruction with the inverted predicate.
824 return InvPredOpcode;
827 default: llvm_unreachable("Unexpected predicated instruction");
828 case Hexagon::C2_ccombinewt:
829 return Hexagon::C2_ccombinewf;
830 case Hexagon::C2_ccombinewf:
831 return Hexagon::C2_ccombinewt;
834 case Hexagon::L4_return_t:
835 return Hexagon::L4_return_f;
836 case Hexagon::L4_return_f:
837 return Hexagon::L4_return_t;
841 // New Value Store instructions.
842 bool HexagonInstrInfo::isNewValueStore(const MachineInstr *MI) const {
843 const uint64_t F = MI->getDesc().TSFlags;
845 return ((F >> HexagonII::NVStorePos) & HexagonII::NVStoreMask);
848 bool HexagonInstrInfo::isNewValueStore(unsigned Opcode) const {
849 const uint64_t F = get(Opcode).TSFlags;
851 return ((F >> HexagonII::NVStorePos) & HexagonII::NVStoreMask);
854 int HexagonInstrInfo::getCondOpcode(int Opc, bool invertPredicate) const {
855 enum Hexagon::PredSense inPredSense;
856 inPredSense = invertPredicate ? Hexagon::PredSense_false :
857 Hexagon::PredSense_true;
858 int CondOpcode = Hexagon::getPredOpcode(Opc, inPredSense);
859 if (CondOpcode >= 0) // Valid Conditional opcode/instruction
862 // This switch case will be removed once all the instructions have been
863 // modified to use relation maps.
865 case Hexagon::TFRI_f:
866 return !invertPredicate ? Hexagon::TFRI_cPt_f :
867 Hexagon::TFRI_cNotPt_f;
868 case Hexagon::A2_combinew:
869 return !invertPredicate ? Hexagon::C2_ccombinewt :
870 Hexagon::C2_ccombinewf;
873 case Hexagon::L4_return:
874 return !invertPredicate ? Hexagon::L4_return_t:
875 Hexagon::L4_return_f;
877 llvm_unreachable("Unexpected predicable instruction");
881 bool HexagonInstrInfo::
882 PredicateInstruction(MachineInstr *MI,
883 const SmallVectorImpl<MachineOperand> &Cond) const {
884 int Opc = MI->getOpcode();
885 assert (isPredicable(MI) && "Expected predicable instruction");
886 bool invertJump = (!Cond.empty() && Cond[0].isImm() &&
887 (Cond[0].getImm() == 0));
889 // This will change MI's opcode to its predicate version.
890 // However, its operand list is still the old one, i.e. the
891 // non-predicate one.
892 MI->setDesc(get(getCondOpcode(Opc, invertJump)));
895 unsigned int GAIdx = 0;
897 // Indicates whether the current MI has a GlobalAddress operand
898 bool hasGAOpnd = false;
899 std::vector<MachineOperand> tmpOpnds;
901 // Indicates whether we need to shift operands to right.
902 bool needShift = true;
904 // The predicate is ALWAYS the FIRST input operand !!!
905 if (MI->getNumOperands() == 0) {
906 // The non-predicate version of MI does not take any operands,
907 // i.e. no outs and no ins. In this condition, the predicate
908 // operand will be directly placed at Operands[0]. No operand
914 else if ( MI->getOperand(MI->getNumOperands()-1).isReg()
915 && MI->getOperand(MI->getNumOperands()-1).isDef()
916 && !MI->getOperand(MI->getNumOperands()-1).isImplicit()) {
917 // The non-predicate version of MI does not have any input operands.
918 // In this condition, we extend the length of Operands[] by one and
919 // copy the original last operand to the newly allocated slot.
920 // At this moment, it is just a place holder. Later, we will put
921 // predicate operand directly into it. No operand shift is needed.
922 // Example: r0=BARRIER (this is a faked insn used here for illustration)
923 MI->addOperand(MI->getOperand(MI->getNumOperands()-1));
925 oper = MI->getNumOperands() - 2;
928 // We need to right shift all input operands by one. Duplicate the
929 // last operand into the newly allocated slot.
930 MI->addOperand(MI->getOperand(MI->getNumOperands()-1));
935 // Operands[ MI->getNumOperands() - 2 ] has been copied into
936 // Operands[ MI->getNumOperands() - 1 ], so we start from
937 // Operands[ MI->getNumOperands() - 3 ].
938 // oper is a signed int.
939 // It is ok if "MI->getNumOperands()-3" is -3, -2, or -1.
940 for (oper = MI->getNumOperands() - 3; oper >= 0; --oper)
942 MachineOperand &MO = MI->getOperand(oper);
944 // Opnd[0] Opnd[1] Opnd[2] Opnd[3] Opnd[4] Opnd[5] Opnd[6] Opnd[7]
945 // <Def0> <Def1> <Use0> <Use1> <ImpDef0> <ImpDef1> <ImpUse0> <ImpUse1>
949 // Predicate Operand here
950 if (MO.isReg() && !MO.isUse() && !MO.isImplicit()) {
954 MI->getOperand(oper+1).ChangeToRegister(MO.getReg(), MO.isDef(),
955 MO.isImplicit(), MO.isKill(),
956 MO.isDead(), MO.isUndef(),
959 else if (MO.isImm()) {
960 MI->getOperand(oper+1).ChangeToImmediate(MO.getImm());
962 else if (MO.isGlobal()) {
963 // MI can not have more than one GlobalAddress operand.
964 assert(hasGAOpnd == false && "MI can only have one GlobalAddress opnd");
966 // There is no member function called "ChangeToGlobalAddress" in the
967 // MachineOperand class (not like "ChangeToRegister" and
968 // "ChangeToImmediate"). So we have to remove them from Operands[] list
969 // first, and then add them back after we have inserted the predicate
970 // operand. tmpOpnds[] is to remember these operands before we remove
972 tmpOpnds.push_back(MO);
974 // Operands[oper] is a GlobalAddress operand;
975 // Operands[oper+1] has been copied into Operands[oper+2];
981 llvm_unreachable("Unexpected operand type");
986 int regPos = invertJump ? 1 : 0;
987 MachineOperand PredMO = Cond[regPos];
989 // [oper] now points to the last explicit Def. Predicate operand must be
990 // located at [oper+1]. See diagram above.
991 // This assumes that the predicate is always the first operand,
992 // i.e. Operands[0+numResults], in the set of inputs
993 // It is better to have an assert here to check this. But I don't know how
994 // to write this assert because findFirstPredOperandIdx() would return -1
995 if (oper < -1) oper = -1;
997 MI->getOperand(oper+1).ChangeToRegister(PredMO.getReg(), PredMO.isDef(),
998 PredMO.isImplicit(), false,
999 PredMO.isDead(), PredMO.isUndef(),
1002 MachineRegisterInfo &RegInfo = MI->getParent()->getParent()->getRegInfo();
1003 RegInfo.clearKillFlags(PredMO.getReg());
1009 // Operands[GAIdx] is the original GlobalAddress operand, which is
1010 // already copied into tmpOpnds[0].
1011 // Operands[GAIdx] now stores a copy of Operands[GAIdx-1]
1012 // Operands[GAIdx+1] has already been copied into Operands[GAIdx+2],
1013 // so we start from [GAIdx+2]
1014 for (i = GAIdx + 2; i < MI->getNumOperands(); ++i)
1015 tmpOpnds.push_back(MI->getOperand(i));
1017 // Remove all operands in range [ (GAIdx+1) ... (MI->getNumOperands()-1) ]
1018 // It is very important that we always remove from the end of Operands[]
1019 // MI->getNumOperands() is at least 2 if program goes to here.
1020 for (i = MI->getNumOperands() - 1; i > GAIdx; --i)
1021 MI->RemoveOperand(i);
1023 for (i = 0; i < tmpOpnds.size(); ++i)
1024 MI->addOperand(tmpOpnds[i]);
1033 isProfitableToIfCvt(MachineBasicBlock &MBB,
1035 unsigned ExtraPredCycles,
1036 const BranchProbability &Probability) const {
1043 isProfitableToIfCvt(MachineBasicBlock &TMBB,
1044 unsigned NumTCycles,
1045 unsigned ExtraTCycles,
1046 MachineBasicBlock &FMBB,
1047 unsigned NumFCycles,
1048 unsigned ExtraFCycles,
1049 const BranchProbability &Probability) const {
1053 // Returns true if an instruction is predicated irrespective of the predicate
1054 // sense. For example, all of the following will return true.
1055 // if (p0) R1 = add(R2, R3)
1056 // if (!p0) R1 = add(R2, R3)
1057 // if (p0.new) R1 = add(R2, R3)
1058 // if (!p0.new) R1 = add(R2, R3)
1059 bool HexagonInstrInfo::isPredicated(const MachineInstr *MI) const {
1060 const uint64_t F = MI->getDesc().TSFlags;
1062 return ((F >> HexagonII::PredicatedPos) & HexagonII::PredicatedMask);
1065 bool HexagonInstrInfo::isPredicated(unsigned Opcode) const {
1066 const uint64_t F = get(Opcode).TSFlags;
1068 return ((F >> HexagonII::PredicatedPos) & HexagonII::PredicatedMask);
1071 bool HexagonInstrInfo::isPredicatedTrue(const MachineInstr *MI) const {
1072 const uint64_t F = MI->getDesc().TSFlags;
1074 assert(isPredicated(MI));
1075 return (!((F >> HexagonII::PredicatedFalsePos) &
1076 HexagonII::PredicatedFalseMask));
1079 bool HexagonInstrInfo::isPredicatedTrue(unsigned Opcode) const {
1080 const uint64_t F = get(Opcode).TSFlags;
1082 // Make sure that the instruction is predicated.
1083 assert((F>> HexagonII::PredicatedPos) & HexagonII::PredicatedMask);
1084 return (!((F >> HexagonII::PredicatedFalsePos) &
1085 HexagonII::PredicatedFalseMask));
1088 bool HexagonInstrInfo::isPredicatedNew(const MachineInstr *MI) const {
1089 const uint64_t F = MI->getDesc().TSFlags;
1091 assert(isPredicated(MI));
1092 return ((F >> HexagonII::PredicatedNewPos) & HexagonII::PredicatedNewMask);
1095 bool HexagonInstrInfo::isPredicatedNew(unsigned Opcode) const {
1096 const uint64_t F = get(Opcode).TSFlags;
1098 assert(isPredicated(Opcode));
1099 return ((F >> HexagonII::PredicatedNewPos) & HexagonII::PredicatedNewMask);
1102 // Returns true, if a ST insn can be promoted to a new-value store.
1103 bool HexagonInstrInfo::mayBeNewStore(const MachineInstr *MI) const {
1104 const uint64_t F = MI->getDesc().TSFlags;
1106 return ((F >> HexagonII::mayNVStorePos) &
1107 HexagonII::mayNVStoreMask);
1111 HexagonInstrInfo::DefinesPredicate(MachineInstr *MI,
1112 std::vector<MachineOperand> &Pred) const {
1113 for (unsigned oper = 0; oper < MI->getNumOperands(); ++oper) {
1114 MachineOperand MO = MI->getOperand(oper);
1115 if (MO.isReg() && MO.isDef()) {
1116 const TargetRegisterClass* RC = RI.getMinimalPhysRegClass(MO.getReg());
1117 if (RC == &Hexagon::PredRegsRegClass) {
1129 SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
1130 const SmallVectorImpl<MachineOperand> &Pred2) const {
1137 // We indicate that we want to reverse the branch by
1138 // inserting a 0 at the beginning of the Cond vector.
1140 bool HexagonInstrInfo::
1141 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
1142 if (!Cond.empty() && Cond[0].isMBB())
1144 if (!Cond.empty() && Cond[0].isImm() && Cond[0].getImm() == 0) {
1145 Cond.erase(Cond.begin());
1147 Cond.insert(Cond.begin(), MachineOperand::CreateImm(0));
1153 bool HexagonInstrInfo::
1154 isProfitableToDupForIfCvt(MachineBasicBlock &MBB,unsigned NumInstrs,
1155 const BranchProbability &Probability) const {
1156 return (NumInstrs <= 4);
1159 bool HexagonInstrInfo::isDeallocRet(const MachineInstr *MI) const {
1160 switch (MI->getOpcode()) {
1161 default: return false;
1162 case Hexagon::L4_return:
1163 case Hexagon::L4_return_t:
1164 case Hexagon::L4_return_f:
1165 case Hexagon::L4_return_tnew_pnt:
1166 case Hexagon::L4_return_fnew_pnt:
1167 case Hexagon::L4_return_tnew_pt:
1168 case Hexagon::L4_return_fnew_pt:
1174 bool HexagonInstrInfo::isValidOffset(unsigned Opcode, int Offset,
1175 bool Extend) const {
1176 // This function is to check whether the "Offset" is in the correct range of
1177 // the given "Opcode". If "Offset" is not in the correct range, "A2_addi" is
1178 // inserted to calculate the final address. Due to this reason, the function
1179 // assumes that the "Offset" has correct alignment.
1180 // We used to assert if the offset was not properly aligned, however,
1181 // there are cases where a misaligned pointer recast can cause this
1182 // problem, and we need to allow for it. The front end warns of such
1183 // misaligns with respect to load size.
1186 case Hexagon::J2_loop0i:
1187 case Hexagon::J2_loop1i:
1188 return isUInt<10>(Offset);
1195 case Hexagon::L2_loadri_io:
1196 case Hexagon::S2_storeri_io:
1197 return (Offset >= Hexagon_MEMW_OFFSET_MIN) &&
1198 (Offset <= Hexagon_MEMW_OFFSET_MAX);
1200 case Hexagon::L2_loadrd_io:
1201 case Hexagon::S2_storerd_io:
1202 return (Offset >= Hexagon_MEMD_OFFSET_MIN) &&
1203 (Offset <= Hexagon_MEMD_OFFSET_MAX);
1205 case Hexagon::L2_loadrh_io:
1206 case Hexagon::L2_loadruh_io:
1207 case Hexagon::S2_storerh_io:
1208 return (Offset >= Hexagon_MEMH_OFFSET_MIN) &&
1209 (Offset <= Hexagon_MEMH_OFFSET_MAX);
1211 case Hexagon::L2_loadrb_io:
1212 case Hexagon::S2_storerb_io:
1213 case Hexagon::L2_loadrub_io:
1214 return (Offset >= Hexagon_MEMB_OFFSET_MIN) &&
1215 (Offset <= Hexagon_MEMB_OFFSET_MAX);
1217 case Hexagon::A2_addi:
1218 return (Offset >= Hexagon_ADDI_OFFSET_MIN) &&
1219 (Offset <= Hexagon_ADDI_OFFSET_MAX);
1221 case Hexagon::L4_iadd_memopw_io:
1222 case Hexagon::L4_isub_memopw_io:
1223 case Hexagon::L4_add_memopw_io:
1224 case Hexagon::L4_sub_memopw_io:
1225 case Hexagon::L4_and_memopw_io:
1226 case Hexagon::L4_or_memopw_io:
1227 return (0 <= Offset && Offset <= 255);
1229 case Hexagon::L4_iadd_memoph_io:
1230 case Hexagon::L4_isub_memoph_io:
1231 case Hexagon::L4_add_memoph_io:
1232 case Hexagon::L4_sub_memoph_io:
1233 case Hexagon::L4_and_memoph_io:
1234 case Hexagon::L4_or_memoph_io:
1235 return (0 <= Offset && Offset <= 127);
1237 case Hexagon::L4_iadd_memopb_io:
1238 case Hexagon::L4_isub_memopb_io:
1239 case Hexagon::L4_add_memopb_io:
1240 case Hexagon::L4_sub_memopb_io:
1241 case Hexagon::L4_and_memopb_io:
1242 case Hexagon::L4_or_memopb_io:
1243 return (0 <= Offset && Offset <= 63);
1245 // LDri_pred and STriw_pred are pseudo operations, so it has to take offset of
1246 // any size. Later pass knows how to handle it.
1247 case Hexagon::STriw_pred:
1248 case Hexagon::LDriw_pred:
1251 case Hexagon::TFR_FI:
1252 case Hexagon::TFR_FIA:
1253 case Hexagon::INLINEASM:
1257 llvm_unreachable("No offset range is defined for this opcode. "
1258 "Please define it in the above switch statement!");
1263 // Check if the Offset is a valid auto-inc imm by Load/Store Type.
1265 bool HexagonInstrInfo::
1266 isValidAutoIncImm(const EVT VT, const int Offset) const {
1268 if (VT == MVT::i64) {
1269 return (Offset >= Hexagon_MEMD_AUTOINC_MIN &&
1270 Offset <= Hexagon_MEMD_AUTOINC_MAX &&
1271 (Offset & 0x7) == 0);
1273 if (VT == MVT::i32) {
1274 return (Offset >= Hexagon_MEMW_AUTOINC_MIN &&
1275 Offset <= Hexagon_MEMW_AUTOINC_MAX &&
1276 (Offset & 0x3) == 0);
1278 if (VT == MVT::i16) {
1279 return (Offset >= Hexagon_MEMH_AUTOINC_MIN &&
1280 Offset <= Hexagon_MEMH_AUTOINC_MAX &&
1281 (Offset & 0x1) == 0);
1283 if (VT == MVT::i8) {
1284 return (Offset >= Hexagon_MEMB_AUTOINC_MIN &&
1285 Offset <= Hexagon_MEMB_AUTOINC_MAX);
1287 llvm_unreachable("Not an auto-inc opc!");
1291 bool HexagonInstrInfo::
1292 isMemOp(const MachineInstr *MI) const {
1293 // return MI->getDesc().mayLoad() && MI->getDesc().mayStore();
1295 switch (MI->getOpcode())
1297 default: return false;
1298 case Hexagon::L4_iadd_memopw_io:
1299 case Hexagon::L4_isub_memopw_io:
1300 case Hexagon::L4_add_memopw_io:
1301 case Hexagon::L4_sub_memopw_io:
1302 case Hexagon::L4_and_memopw_io:
1303 case Hexagon::L4_or_memopw_io:
1304 case Hexagon::L4_iadd_memoph_io:
1305 case Hexagon::L4_isub_memoph_io:
1306 case Hexagon::L4_add_memoph_io:
1307 case Hexagon::L4_sub_memoph_io:
1308 case Hexagon::L4_and_memoph_io:
1309 case Hexagon::L4_or_memoph_io:
1310 case Hexagon::L4_iadd_memopb_io:
1311 case Hexagon::L4_isub_memopb_io:
1312 case Hexagon::L4_add_memopb_io:
1313 case Hexagon::L4_sub_memopb_io:
1314 case Hexagon::L4_and_memopb_io:
1315 case Hexagon::L4_or_memopb_io:
1316 case Hexagon::L4_ior_memopb_io:
1317 case Hexagon::L4_ior_memoph_io:
1318 case Hexagon::L4_ior_memopw_io:
1319 case Hexagon::L4_iand_memopb_io:
1320 case Hexagon::L4_iand_memoph_io:
1321 case Hexagon::L4_iand_memopw_io:
1328 bool HexagonInstrInfo::
1329 isSpillPredRegOp(const MachineInstr *MI) const {
1330 switch (MI->getOpcode()) {
1331 default: return false;
1332 case Hexagon::STriw_pred :
1333 case Hexagon::LDriw_pred :
1338 bool HexagonInstrInfo::isNewValueJumpCandidate(const MachineInstr *MI) const {
1339 switch (MI->getOpcode()) {
1340 default: return false;
1341 case Hexagon::C2_cmpeq:
1342 case Hexagon::C2_cmpeqi:
1343 case Hexagon::C2_cmpgt:
1344 case Hexagon::C2_cmpgti:
1345 case Hexagon::C2_cmpgtu:
1346 case Hexagon::C2_cmpgtui:
1351 bool HexagonInstrInfo::
1352 isConditionalTransfer (const MachineInstr *MI) const {
1353 switch (MI->getOpcode()) {
1354 default: return false;
1355 case Hexagon::A2_tfrt:
1356 case Hexagon::A2_tfrf:
1357 case Hexagon::C2_cmoveit:
1358 case Hexagon::C2_cmoveif:
1359 case Hexagon::A2_tfrtnew:
1360 case Hexagon::A2_tfrfnew:
1361 case Hexagon::C2_cmovenewit:
1362 case Hexagon::C2_cmovenewif:
1367 bool HexagonInstrInfo::isConditionalALU32 (const MachineInstr* MI) const {
1368 switch (MI->getOpcode())
1370 default: return false;
1371 case Hexagon::A2_paddf:
1372 case Hexagon::A2_paddfnew:
1373 case Hexagon::A2_paddt:
1374 case Hexagon::A2_paddtnew:
1375 case Hexagon::A2_pandf:
1376 case Hexagon::A2_pandfnew:
1377 case Hexagon::A2_pandt:
1378 case Hexagon::A2_pandtnew:
1379 case Hexagon::A4_paslhf:
1380 case Hexagon::A4_paslhfnew:
1381 case Hexagon::A4_paslht:
1382 case Hexagon::A4_paslhtnew:
1383 case Hexagon::A4_pasrhf:
1384 case Hexagon::A4_pasrhfnew:
1385 case Hexagon::A4_pasrht:
1386 case Hexagon::A4_pasrhtnew:
1387 case Hexagon::A2_porf:
1388 case Hexagon::A2_porfnew:
1389 case Hexagon::A2_port:
1390 case Hexagon::A2_portnew:
1391 case Hexagon::A2_psubf:
1392 case Hexagon::A2_psubfnew:
1393 case Hexagon::A2_psubt:
1394 case Hexagon::A2_psubtnew:
1395 case Hexagon::A2_pxorf:
1396 case Hexagon::A2_pxorfnew:
1397 case Hexagon::A2_pxort:
1398 case Hexagon::A2_pxortnew:
1399 case Hexagon::A4_psxthf:
1400 case Hexagon::A4_psxthfnew:
1401 case Hexagon::A4_psxtht:
1402 case Hexagon::A4_psxthtnew:
1403 case Hexagon::A4_psxtbf:
1404 case Hexagon::A4_psxtbfnew:
1405 case Hexagon::A4_psxtbt:
1406 case Hexagon::A4_psxtbtnew:
1407 case Hexagon::A4_pzxtbf:
1408 case Hexagon::A4_pzxtbfnew:
1409 case Hexagon::A4_pzxtbt:
1410 case Hexagon::A4_pzxtbtnew:
1411 case Hexagon::A4_pzxthf:
1412 case Hexagon::A4_pzxthfnew:
1413 case Hexagon::A4_pzxtht:
1414 case Hexagon::A4_pzxthtnew:
1415 case Hexagon::A2_paddit:
1416 case Hexagon::A2_paddif:
1417 case Hexagon::C2_ccombinewt:
1418 case Hexagon::C2_ccombinewf:
1423 bool HexagonInstrInfo::
1424 isConditionalLoad (const MachineInstr* MI) const {
1425 switch (MI->getOpcode())
1427 default: return false;
1428 case Hexagon::L2_ploadrdt_io :
1429 case Hexagon::L2_ploadrdf_io:
1430 case Hexagon::L2_ploadrit_io:
1431 case Hexagon::L2_ploadrif_io:
1432 case Hexagon::L2_ploadrht_io:
1433 case Hexagon::L2_ploadrhf_io:
1434 case Hexagon::L2_ploadrbt_io:
1435 case Hexagon::L2_ploadrbf_io:
1436 case Hexagon::L2_ploadruht_io:
1437 case Hexagon::L2_ploadruhf_io:
1438 case Hexagon::L2_ploadrubt_io:
1439 case Hexagon::L2_ploadrubf_io:
1440 case Hexagon::L2_ploadrdt_pi:
1441 case Hexagon::L2_ploadrdf_pi:
1442 case Hexagon::L2_ploadrit_pi:
1443 case Hexagon::L2_ploadrif_pi:
1444 case Hexagon::L2_ploadrht_pi:
1445 case Hexagon::L2_ploadrhf_pi:
1446 case Hexagon::L2_ploadrbt_pi:
1447 case Hexagon::L2_ploadrbf_pi:
1448 case Hexagon::L2_ploadruht_pi:
1449 case Hexagon::L2_ploadruhf_pi:
1450 case Hexagon::L2_ploadrubt_pi:
1451 case Hexagon::L2_ploadrubf_pi:
1452 case Hexagon::L4_ploadrdt_rr:
1453 case Hexagon::L4_ploadrdf_rr:
1454 case Hexagon::L4_ploadrbt_rr:
1455 case Hexagon::L4_ploadrbf_rr:
1456 case Hexagon::L4_ploadrubt_rr:
1457 case Hexagon::L4_ploadrubf_rr:
1458 case Hexagon::L4_ploadrht_rr:
1459 case Hexagon::L4_ploadrhf_rr:
1460 case Hexagon::L4_ploadruht_rr:
1461 case Hexagon::L4_ploadruhf_rr:
1462 case Hexagon::L4_ploadrit_rr:
1463 case Hexagon::L4_ploadrif_rr:
1468 // Returns true if an instruction is a conditional store.
1470 // Note: It doesn't include conditional new-value stores as they can't be
1471 // converted to .new predicate.
1473 // p.new NV store [ if(p0.new)memw(R0+#0)=R2.new ]
1475 // / \ (not OK. it will cause new-value store to be
1476 // / X conditional on p0.new while R2 producer is
1479 // p.new store p.old NV store
1480 // [if(p0.new)memw(R0+#0)=R2] [if(p0)memw(R0+#0)=R2.new]
1486 // [if (p0)memw(R0+#0)=R2]
1488 // The above diagram shows the steps involoved in the conversion of a predicated
1489 // store instruction to its .new predicated new-value form.
1491 // The following set of instructions further explains the scenario where
1492 // conditional new-value store becomes invalid when promoted to .new predicate
1495 // { 1) if (p0) r0 = add(r1, r2)
1496 // 2) p0 = cmp.eq(r3, #0) }
1498 // 3) if (p0) memb(r1+#0) = r0 --> this instruction can't be grouped with
1499 // the first two instructions because in instr 1, r0 is conditional on old value
1500 // of p0 but its use in instr 3 is conditional on p0 modified by instr 2 which
1501 // is not valid for new-value stores.
1502 bool HexagonInstrInfo::
1503 isConditionalStore (const MachineInstr* MI) const {
1504 switch (MI->getOpcode())
1506 default: return false;
1507 case Hexagon::S4_storeirbt_io:
1508 case Hexagon::S4_storeirbf_io:
1509 case Hexagon::S4_pstorerbt_rr:
1510 case Hexagon::S4_pstorerbf_rr:
1511 case Hexagon::S2_pstorerbt_io:
1512 case Hexagon::S2_pstorerbf_io:
1513 case Hexagon::S2_pstorerbt_pi:
1514 case Hexagon::S2_pstorerbf_pi:
1515 case Hexagon::S2_pstorerdt_io:
1516 case Hexagon::S2_pstorerdf_io:
1517 case Hexagon::S4_pstorerdt_rr:
1518 case Hexagon::S4_pstorerdf_rr:
1519 case Hexagon::S2_pstorerdt_pi:
1520 case Hexagon::S2_pstorerdf_pi:
1521 case Hexagon::S2_pstorerht_io:
1522 case Hexagon::S2_pstorerhf_io:
1523 case Hexagon::S4_storeirht_io:
1524 case Hexagon::S4_storeirhf_io:
1525 case Hexagon::S4_pstorerht_rr:
1526 case Hexagon::S4_pstorerhf_rr:
1527 case Hexagon::S2_pstorerht_pi:
1528 case Hexagon::S2_pstorerhf_pi:
1529 case Hexagon::S2_pstorerit_io:
1530 case Hexagon::S2_pstorerif_io:
1531 case Hexagon::S4_storeirit_io:
1532 case Hexagon::S4_storeirif_io:
1533 case Hexagon::S4_pstorerit_rr:
1534 case Hexagon::S4_pstorerif_rr:
1535 case Hexagon::S2_pstorerit_pi:
1536 case Hexagon::S2_pstorerif_pi:
1538 // V4 global address store before promoting to dot new.
1539 case Hexagon::S4_pstorerdt_abs:
1540 case Hexagon::S4_pstorerdf_abs:
1541 case Hexagon::S4_pstorerbt_abs:
1542 case Hexagon::S4_pstorerbf_abs:
1543 case Hexagon::S4_pstorerht_abs:
1544 case Hexagon::S4_pstorerhf_abs:
1545 case Hexagon::S4_pstorerit_abs:
1546 case Hexagon::S4_pstorerif_abs:
1549 // Predicated new value stores (i.e. if (p0) memw(..)=r0.new) are excluded
1550 // from the "Conditional Store" list. Because a predicated new value store
1551 // would NOT be promoted to a double dot new store. See diagram below:
1552 // This function returns yes for those stores that are predicated but not
1553 // yet promoted to predicate dot new instructions.
1555 // +---------------------+
1556 // /-----| if (p0) memw(..)=r0 |---------\~
1557 // || +---------------------+ ||
1558 // promote || /\ /\ || promote
1560 // \||/ demote || \||/
1562 // +-------------------------+ || +-------------------------+
1563 // | if (p0.new) memw(..)=r0 | || | if (p0) memw(..)=r0.new |
1564 // +-------------------------+ || +-------------------------+
1567 // promote || \/ NOT possible
1571 // +-----------------------------+
1572 // | if (p0.new) memw(..)=r0.new |
1573 // +-----------------------------+
1574 // Double Dot New Store
1580 bool HexagonInstrInfo::isNewValueJump(const MachineInstr *MI) const {
1581 if (isNewValue(MI) && isBranch(MI))
1586 bool HexagonInstrInfo::isPostIncrement (const MachineInstr* MI) const {
1587 return (getAddrMode(MI) == HexagonII::PostInc);
1590 bool HexagonInstrInfo::isNewValue(const MachineInstr* MI) const {
1591 const uint64_t F = MI->getDesc().TSFlags;
1592 return ((F >> HexagonII::NewValuePos) & HexagonII::NewValueMask);
1595 // Returns true, if any one of the operands is a dot new
1596 // insn, whether it is predicated dot new or register dot new.
1597 bool HexagonInstrInfo::isDotNewInst (const MachineInstr* MI) const {
1598 return (isNewValueInst(MI) ||
1599 (isPredicated(MI) && isPredicatedNew(MI)));
1602 // Returns the most basic instruction for the .new predicated instructions and
1603 // new-value stores.
1604 // For example, all of the following instructions will be converted back to the
1605 // same instruction:
1606 // 1) if (p0.new) memw(R0+#0) = R1.new --->
1607 // 2) if (p0) memw(R0+#0)= R1.new -------> if (p0) memw(R0+#0) = R1
1608 // 3) if (p0.new) memw(R0+#0) = R1 --->
1611 int HexagonInstrInfo::GetDotOldOp(const int opc) const {
1613 if (isPredicated(NewOp) && isPredicatedNew(NewOp)) { // Get predicate old form
1614 NewOp = Hexagon::getPredOldOpcode(NewOp);
1615 assert(NewOp >= 0 &&
1616 "Couldn't change predicate new instruction to its old form.");
1619 if (isNewValueStore(NewOp)) { // Convert into non-new-value format
1620 NewOp = Hexagon::getNonNVStore(NewOp);
1621 assert(NewOp >= 0 && "Couldn't change new-value store to its old form.");
1626 // Return the new value instruction for a given store.
1627 int HexagonInstrInfo::GetDotNewOp(const MachineInstr* MI) const {
1628 int NVOpcode = Hexagon::getNewValueOpcode(MI->getOpcode());
1629 if (NVOpcode >= 0) // Valid new-value store instruction.
1632 switch (MI->getOpcode()) {
1633 default: llvm_unreachable("Unknown .new type");
1634 case Hexagon::S4_storerb_ur:
1635 return Hexagon::S4_storerbnew_ur;
1637 case Hexagon::S4_storerh_ur:
1638 return Hexagon::S4_storerhnew_ur;
1640 case Hexagon::S4_storeri_ur:
1641 return Hexagon::S4_storerinew_ur;
1643 case Hexagon::S2_storerb_pci:
1644 return Hexagon::S2_storerb_pci;
1646 case Hexagon::S2_storeri_pci:
1647 return Hexagon::S2_storeri_pci;
1649 case Hexagon::S2_storerh_pci:
1650 return Hexagon::S2_storerh_pci;
1652 case Hexagon::S2_storerd_pci:
1653 return Hexagon::S2_storerd_pci;
1655 case Hexagon::S2_storerf_pci:
1656 return Hexagon::S2_storerf_pci;
1661 // Return .new predicate version for an instruction.
1662 int HexagonInstrInfo::GetDotNewPredOp(MachineInstr *MI,
1663 const MachineBranchProbabilityInfo
1666 int NewOpcode = Hexagon::getPredNewOpcode(MI->getOpcode());
1667 if (NewOpcode >= 0) // Valid predicate new instruction
1670 switch (MI->getOpcode()) {
1671 default: llvm_unreachable("Unknown .new type");
1673 case Hexagon::J2_jumpt:
1674 case Hexagon::J2_jumpf:
1675 return getDotNewPredJumpOp(MI, MBPI);
1677 case Hexagon::J2_jumprt:
1678 return Hexagon::J2_jumptnewpt;
1680 case Hexagon::J2_jumprf:
1681 return Hexagon::J2_jumprfnewpt;
1683 case Hexagon::JMPrett:
1684 return Hexagon::J2_jumprtnewpt;
1686 case Hexagon::JMPretf:
1687 return Hexagon::J2_jumprfnewpt;
1690 // Conditional combine
1691 case Hexagon::C2_ccombinewt:
1692 return Hexagon::C2_ccombinewnewt;
1693 case Hexagon::C2_ccombinewf:
1694 return Hexagon::C2_ccombinewnewf;
1699 unsigned HexagonInstrInfo::getAddrMode(const MachineInstr* MI) const {
1700 const uint64_t F = MI->getDesc().TSFlags;
1702 return((F >> HexagonII::AddrModePos) & HexagonII::AddrModeMask);
1705 /// immediateExtend - Changes the instruction in place to one using an immediate
1707 void HexagonInstrInfo::immediateExtend(MachineInstr *MI) const {
1708 assert((isExtendable(MI)||isConstExtended(MI)) &&
1709 "Instruction must be extendable");
1710 // Find which operand is extendable.
1711 short ExtOpNum = getCExtOpNum(MI);
1712 MachineOperand &MO = MI->getOperand(ExtOpNum);
1713 // This needs to be something we understand.
1714 assert((MO.isMBB() || MO.isImm()) &&
1715 "Branch with unknown extendable field type");
1716 // Mark given operand as extended.
1717 MO.addTargetFlag(HexagonII::HMOTF_ConstExtended);
1720 DFAPacketizer *HexagonInstrInfo::CreateTargetScheduleState(
1721 const TargetSubtargetInfo &STI) const {
1722 const InstrItineraryData *II = STI.getInstrItineraryData();
1723 return static_cast<const HexagonSubtarget &>(STI).createDFAPacketizer(II);
1726 bool HexagonInstrInfo::isSchedulingBoundary(const MachineInstr *MI,
1727 const MachineBasicBlock *MBB,
1728 const MachineFunction &MF) const {
1729 // Debug info is never a scheduling boundary. It's necessary to be explicit
1730 // due to the special treatment of IT instructions below, otherwise a
1731 // dbg_value followed by an IT will result in the IT instruction being
1732 // considered a scheduling hazard, which is wrong. It should be the actual
1733 // instruction preceding the dbg_value instruction(s), just like it is
1734 // when debug info is not present.
1735 if (MI->isDebugValue())
1738 // Terminators and labels can't be scheduled around.
1739 if (MI->getDesc().isTerminator() || MI->isPosition() || MI->isInlineAsm())
1745 bool HexagonInstrInfo::isConstExtended(MachineInstr *MI) const {
1746 const uint64_t F = MI->getDesc().TSFlags;
1747 unsigned isExtended = (F >> HexagonII::ExtendedPos) & HexagonII::ExtendedMask;
1748 if (isExtended) // Instruction must be extended.
1751 unsigned isExtendable = (F >> HexagonII::ExtendablePos)
1752 & HexagonII::ExtendableMask;
1756 short ExtOpNum = getCExtOpNum(MI);
1757 const MachineOperand &MO = MI->getOperand(ExtOpNum);
1758 // Use MO operand flags to determine if MO
1759 // has the HMOTF_ConstExtended flag set.
1760 if (MO.getTargetFlags() && HexagonII::HMOTF_ConstExtended)
1762 // If this is a Machine BB address we are talking about, and it is
1763 // not marked as extended, say so.
1767 // We could be using an instruction with an extendable immediate and shoehorn
1768 // a global address into it. If it is a global address it will be constant
1769 // extended. We do this for COMBINE.
1770 // We currently only handle isGlobal() because it is the only kind of
1771 // object we are going to end up with here for now.
1772 // In the future we probably should add isSymbol(), etc.
1773 if (MO.isGlobal() || MO.isSymbol() || MO.isBlockAddress())
1776 // If the extendable operand is not 'Immediate' type, the instruction should
1777 // have 'isExtended' flag set.
1778 assert(MO.isImm() && "Extendable operand must be Immediate type");
1780 int MinValue = getMinValue(MI);
1781 int MaxValue = getMaxValue(MI);
1782 int ImmValue = MO.getImm();
1784 return (ImmValue < MinValue || ImmValue > MaxValue);
1787 // Returns the opcode to use when converting MI, which is a conditional jump,
1788 // into a conditional instruction which uses the .new value of the predicate.
1789 // We also use branch probabilities to add a hint to the jump.
1791 HexagonInstrInfo::getDotNewPredJumpOp(MachineInstr *MI,
1793 MachineBranchProbabilityInfo *MBPI) const {
1795 // We assume that block can have at most two successors.
1797 MachineBasicBlock *Src = MI->getParent();
1798 MachineOperand *BrTarget = &MI->getOperand(1);
1799 MachineBasicBlock *Dst = BrTarget->getMBB();
1801 const BranchProbability Prediction = MBPI->getEdgeProbability(Src, Dst);
1802 if (Prediction >= BranchProbability(1,2))
1805 switch (MI->getOpcode()) {
1806 case Hexagon::J2_jumpt:
1807 return taken ? Hexagon::J2_jumptnewpt : Hexagon::J2_jumptnew;
1808 case Hexagon::J2_jumpf:
1809 return taken ? Hexagon::J2_jumpfnewpt : Hexagon::J2_jumpfnew;
1812 llvm_unreachable("Unexpected jump instruction.");
1815 // Returns true if a particular operand is extendable for an instruction.
1816 bool HexagonInstrInfo::isOperandExtended(const MachineInstr *MI,
1817 unsigned short OperandNum) const {
1818 const uint64_t F = MI->getDesc().TSFlags;
1820 return ((F >> HexagonII::ExtendableOpPos) & HexagonII::ExtendableOpMask)
1824 // Returns Operand Index for the constant extended instruction.
1825 unsigned short HexagonInstrInfo::getCExtOpNum(const MachineInstr *MI) const {
1826 const uint64_t F = MI->getDesc().TSFlags;
1827 return ((F >> HexagonII::ExtendableOpPos) & HexagonII::ExtendableOpMask);
1830 // Returns the min value that doesn't need to be extended.
1831 int HexagonInstrInfo::getMinValue(const MachineInstr *MI) const {
1832 const uint64_t F = MI->getDesc().TSFlags;
1833 unsigned isSigned = (F >> HexagonII::ExtentSignedPos)
1834 & HexagonII::ExtentSignedMask;
1835 unsigned bits = (F >> HexagonII::ExtentBitsPos)
1836 & HexagonII::ExtentBitsMask;
1838 if (isSigned) // if value is signed
1839 return -1U << (bits - 1);
1844 // Returns the max value that doesn't need to be extended.
1845 int HexagonInstrInfo::getMaxValue(const MachineInstr *MI) const {
1846 const uint64_t F = MI->getDesc().TSFlags;
1847 unsigned isSigned = (F >> HexagonII::ExtentSignedPos)
1848 & HexagonII::ExtentSignedMask;
1849 unsigned bits = (F >> HexagonII::ExtentBitsPos)
1850 & HexagonII::ExtentBitsMask;
1852 if (isSigned) // if value is signed
1853 return ~(-1U << (bits - 1));
1855 return ~(-1U << bits);
1858 // Returns true if an instruction can be converted into a non-extended
1859 // equivalent instruction.
1860 bool HexagonInstrInfo::NonExtEquivalentExists (const MachineInstr *MI) const {
1863 // Check if the instruction has a register form that uses register in place
1864 // of the extended operand, if so return that as the non-extended form.
1865 if (Hexagon::getRegForm(MI->getOpcode()) >= 0)
1868 if (MI->getDesc().mayLoad() || MI->getDesc().mayStore()) {
1869 // Check addressing mode and retrieve non-ext equivalent instruction.
1871 switch (getAddrMode(MI)) {
1872 case HexagonII::Absolute :
1873 // Load/store with absolute addressing mode can be converted into
1874 // base+offset mode.
1875 NonExtOpcode = Hexagon::getBasedWithImmOffset(MI->getOpcode());
1877 case HexagonII::BaseImmOffset :
1878 // Load/store with base+offset addressing mode can be converted into
1879 // base+register offset addressing mode. However left shift operand should
1881 NonExtOpcode = Hexagon::getBaseWithRegOffset(MI->getOpcode());
1886 if (NonExtOpcode < 0)
1893 // Returns opcode of the non-extended equivalent instruction.
1894 short HexagonInstrInfo::getNonExtOpcode (const MachineInstr *MI) const {
1896 // Check if the instruction has a register form that uses register in place
1897 // of the extended operand, if so return that as the non-extended form.
1898 short NonExtOpcode = Hexagon::getRegForm(MI->getOpcode());
1899 if (NonExtOpcode >= 0)
1900 return NonExtOpcode;
1902 if (MI->getDesc().mayLoad() || MI->getDesc().mayStore()) {
1903 // Check addressing mode and retrieve non-ext equivalent instruction.
1904 switch (getAddrMode(MI)) {
1905 case HexagonII::Absolute :
1906 return Hexagon::getBasedWithImmOffset(MI->getOpcode());
1907 case HexagonII::BaseImmOffset :
1908 return Hexagon::getBaseWithRegOffset(MI->getOpcode());
1916 bool HexagonInstrInfo::PredOpcodeHasJMP_c(Opcode_t Opcode) const {
1917 return (Opcode == Hexagon::J2_jumpt) ||
1918 (Opcode == Hexagon::J2_jumpf) ||
1919 (Opcode == Hexagon::J2_jumptnewpt) ||
1920 (Opcode == Hexagon::J2_jumpfnewpt) ||
1921 (Opcode == Hexagon::J2_jumpt) ||
1922 (Opcode == Hexagon::J2_jumpf);
1925 bool HexagonInstrInfo::PredOpcodeHasNot(Opcode_t Opcode) const {
1926 return (Opcode == Hexagon::J2_jumpf) ||
1927 (Opcode == Hexagon::J2_jumpfnewpt) ||
1928 (Opcode == Hexagon::J2_jumpfnew);