1 //===-- HexagonInstrInfo.cpp - Hexagon Instruction Information ------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Hexagon implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "HexagonInstrInfo.h"
16 #include "HexagonRegisterInfo.h"
17 #include "HexagonSubtarget.h"
18 #include "llvm/ADT/STLExtras.h"
19 #include "llvm/ADT/SmallVector.h"
20 #include "llvm/CodeGen/DFAPacketizer.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineMemOperand.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/PseudoSourceValue.h"
26 #include "llvm/MC/MCAsmInfo.h"
27 #include "llvm/Support/Debug.h"
28 #include "llvm/Support/MathExtras.h"
29 #include "llvm/Support/raw_ostream.h"
34 #define DEBUG_TYPE "hexagon-instrinfo"
36 #define GET_INSTRINFO_CTOR_DTOR
37 #define GET_INSTRMAP_INFO
38 #include "HexagonGenInstrInfo.inc"
39 #include "HexagonGenDFAPacketizer.inc"
43 static cl::opt<bool> ScheduleInlineAsm("hexagon-sched-inline-asm", cl::Hidden,
44 cl::init(false), cl::desc("Do not consider inline-asm a scheduling/"
45 "packetization boundary."));
47 static cl::opt<bool> EnableBranchPrediction("hexagon-enable-branch-prediction",
48 cl::Hidden, cl::init(true), cl::desc("Enable branch prediction"));
50 static cl::opt<bool> EnableTimingClassLatency(
51 "enable-timing-class-latency", cl::Hidden, cl::init(false),
52 cl::desc("Enable timing class latency"));
54 static cl::opt<bool> EnableALUForwarding(
55 "enable-alu-forwarding", cl::Hidden, cl::init(true),
56 cl::desc("Enable vec alu forwarding"));
58 static cl::opt<bool> EnableACCForwarding(
59 "enable-acc-forwarding", cl::Hidden, cl::init(true),
60 cl::desc("Enable vec acc forwarding"));
62 static cl::opt<bool> BranchRelaxAsmLarge("branch-relax-asm-large",
63 cl::init(true), cl::Hidden, cl::ZeroOrMore, cl::desc("branch relax asm"));
66 /// Constants for Hexagon instructions.
68 const int Hexagon_MEMV_OFFSET_MAX_128B = 2047; // #s7
69 const int Hexagon_MEMV_OFFSET_MIN_128B = -2048; // #s7
70 const int Hexagon_MEMV_OFFSET_MAX = 1023; // #s6
71 const int Hexagon_MEMV_OFFSET_MIN = -1024; // #s6
72 const int Hexagon_MEMW_OFFSET_MAX = 4095;
73 const int Hexagon_MEMW_OFFSET_MIN = -4096;
74 const int Hexagon_MEMD_OFFSET_MAX = 8191;
75 const int Hexagon_MEMD_OFFSET_MIN = -8192;
76 const int Hexagon_MEMH_OFFSET_MAX = 2047;
77 const int Hexagon_MEMH_OFFSET_MIN = -2048;
78 const int Hexagon_MEMB_OFFSET_MAX = 1023;
79 const int Hexagon_MEMB_OFFSET_MIN = -1024;
80 const int Hexagon_ADDI_OFFSET_MAX = 32767;
81 const int Hexagon_ADDI_OFFSET_MIN = -32768;
82 const int Hexagon_MEMD_AUTOINC_MAX = 56;
83 const int Hexagon_MEMD_AUTOINC_MIN = -64;
84 const int Hexagon_MEMW_AUTOINC_MAX = 28;
85 const int Hexagon_MEMW_AUTOINC_MIN = -32;
86 const int Hexagon_MEMH_AUTOINC_MAX = 14;
87 const int Hexagon_MEMH_AUTOINC_MIN = -16;
88 const int Hexagon_MEMB_AUTOINC_MAX = 7;
89 const int Hexagon_MEMB_AUTOINC_MIN = -8;
90 const int Hexagon_MEMV_AUTOINC_MAX = 192;
91 const int Hexagon_MEMV_AUTOINC_MIN = -256;
92 const int Hexagon_MEMV_AUTOINC_MAX_128B = 384;
93 const int Hexagon_MEMV_AUTOINC_MIN_128B = -512;
95 // Pin the vtable to this file.
96 void HexagonInstrInfo::anchor() {}
98 HexagonInstrInfo::HexagonInstrInfo(HexagonSubtarget &ST)
99 : HexagonGenInstrInfo(Hexagon::ADJCALLSTACKDOWN, Hexagon::ADJCALLSTACKUP),
103 static bool isIntRegForSubInst(unsigned Reg) {
104 return (Reg >= Hexagon::R0 && Reg <= Hexagon::R7) ||
105 (Reg >= Hexagon::R16 && Reg <= Hexagon::R23);
109 static bool isDblRegForSubInst(unsigned Reg, const HexagonRegisterInfo &HRI) {
110 return isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::subreg_loreg)) &&
111 isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::subreg_hireg));
115 /// Calculate number of instructions excluding the debug instructions.
116 static unsigned nonDbgMICount(MachineBasicBlock::const_instr_iterator MIB,
117 MachineBasicBlock::const_instr_iterator MIE) {
119 for (; MIB != MIE; ++MIB) {
120 if (!MIB->isDebugValue())
127 /// Find the hardware loop instruction used to set-up the specified loop.
128 /// On Hexagon, we have two instructions used to set-up the hardware loop
129 /// (LOOP0, LOOP1) with corresponding endloop (ENDLOOP0, ENDLOOP1) instructions
130 /// to indicate the end of a loop.
131 static MachineInstr *findLoopInstr(MachineBasicBlock *BB, int EndLoopOp,
132 SmallPtrSet<MachineBasicBlock *, 8> &Visited) {
135 if (EndLoopOp == Hexagon::ENDLOOP0) {
136 LOOPi = Hexagon::J2_loop0i;
137 LOOPr = Hexagon::J2_loop0r;
138 } else { // EndLoopOp == Hexagon::EndLOOP1
139 LOOPi = Hexagon::J2_loop1i;
140 LOOPr = Hexagon::J2_loop1r;
143 // The loop set-up instruction will be in a predecessor block
144 for (MachineBasicBlock::pred_iterator PB = BB->pred_begin(),
145 PE = BB->pred_end(); PB != PE; ++PB) {
146 // If this has been visited, already skip it.
147 if (!Visited.insert(*PB).second)
151 for (MachineBasicBlock::reverse_instr_iterator I = (*PB)->instr_rbegin(),
152 E = (*PB)->instr_rend(); I != E; ++I) {
153 int Opc = I->getOpcode();
154 if (Opc == LOOPi || Opc == LOOPr)
156 // We've reached a different loop, which means the loop0 has been removed.
157 if (Opc == EndLoopOp)
160 // Check the predecessors for the LOOP instruction.
161 MachineInstr *loop = findLoopInstr(*PB, EndLoopOp, Visited);
169 /// Gather register def/uses from MI.
170 /// This treats possible (predicated) defs as actually happening ones
171 /// (conservatively).
172 static inline void parseOperands(const MachineInstr *MI,
173 SmallVector<unsigned, 4> &Defs, SmallVector<unsigned, 8> &Uses) {
177 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
178 const MachineOperand &MO = MI->getOperand(i);
183 unsigned Reg = MO.getReg();
188 Uses.push_back(MO.getReg());
191 Defs.push_back(MO.getReg());
196 // Position dependent, so check twice for swap.
197 static bool isDuplexPairMatch(unsigned Ga, unsigned Gb) {
199 case HexagonII::HSIG_None:
202 case HexagonII::HSIG_L1:
203 return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_A);
204 case HexagonII::HSIG_L2:
205 return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_L2 ||
206 Gb == HexagonII::HSIG_A);
207 case HexagonII::HSIG_S1:
208 return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_L2 ||
209 Gb == HexagonII::HSIG_S1 || Gb == HexagonII::HSIG_A);
210 case HexagonII::HSIG_S2:
211 return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_L2 ||
212 Gb == HexagonII::HSIG_S1 || Gb == HexagonII::HSIG_S2 ||
213 Gb == HexagonII::HSIG_A);
214 case HexagonII::HSIG_A:
215 return (Gb == HexagonII::HSIG_A);
216 case HexagonII::HSIG_Compound:
217 return (Gb == HexagonII::HSIG_Compound);
224 /// isLoadFromStackSlot - If the specified machine instruction is a direct
225 /// load from a stack slot, return the virtual or physical register number of
226 /// the destination along with the FrameIndex of the loaded stack slot. If
227 /// not, return 0. This predicate must return 0 if the instruction has
228 /// any side effects other than loading from the stack slot.
229 unsigned HexagonInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
230 int &FrameIndex) const {
231 switch (MI->getOpcode()) {
233 case Hexagon::L2_loadri_io:
234 case Hexagon::L2_loadrd_io:
235 case Hexagon::L2_loadrh_io:
236 case Hexagon::L2_loadrb_io:
237 case Hexagon::L2_loadrub_io:
238 if (MI->getOperand(2).isFI() &&
239 MI->getOperand(1).isImm() && (MI->getOperand(1).getImm() == 0)) {
240 FrameIndex = MI->getOperand(2).getIndex();
241 return MI->getOperand(0).getReg();
249 /// isStoreToStackSlot - If the specified machine instruction is a direct
250 /// store to a stack slot, return the virtual or physical register number of
251 /// the source reg along with the FrameIndex of the loaded stack slot. If
252 /// not, return 0. This predicate must return 0 if the instruction has
253 /// any side effects other than storing to the stack slot.
254 unsigned HexagonInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
255 int &FrameIndex) const {
256 switch (MI->getOpcode()) {
258 case Hexagon::S2_storeri_io:
259 case Hexagon::S2_storerd_io:
260 case Hexagon::S2_storerh_io:
261 case Hexagon::S2_storerb_io:
262 if (MI->getOperand(2).isFI() &&
263 MI->getOperand(1).isImm() && (MI->getOperand(1).getImm() == 0)) {
264 FrameIndex = MI->getOperand(0).getIndex();
265 return MI->getOperand(2).getReg();
273 /// This function can analyze one/two way branching only and should (mostly) be
274 /// called by target independent side.
275 /// First entry is always the opcode of the branching instruction, except when
276 /// the Cond vector is supposed to be empty, e.g., when AnalyzeBranch fails, a
277 /// BB with only unconditional jump. Subsequent entries depend upon the opcode,
278 /// e.g. Jump_c p will have
282 /// Cond[0] = ENDLOOP
285 /// Cond[0] = Hexagon::CMPEQri_f_Jumpnv_t_V4 -- specific opcode
289 bool HexagonInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
290 MachineBasicBlock *&TBB,
291 MachineBasicBlock *&FBB,
292 SmallVectorImpl<MachineOperand> &Cond,
293 bool AllowModify) const {
298 // If the block has no terminators, it just falls into the block after it.
299 MachineBasicBlock::instr_iterator I = MBB.instr_end();
300 if (I == MBB.instr_begin())
303 // A basic block may looks like this:
313 // It has two succs but does not have a terminator
314 // Don't know how to handle it.
318 // Don't analyze EH branches.
320 } while (I != MBB.instr_begin());
325 while (I->isDebugValue()) {
326 if (I == MBB.instr_begin())
331 bool JumpToBlock = I->getOpcode() == Hexagon::J2_jump &&
332 I->getOperand(0).isMBB();
333 // Delete the J2_jump if it's equivalent to a fall-through.
334 if (AllowModify && JumpToBlock &&
335 MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
336 DEBUG(dbgs()<< "\nErasing the jump to successor block\n";);
337 I->eraseFromParent();
339 if (I == MBB.instr_begin())
343 if (!isUnpredicatedTerminator(&*I))
346 // Get the last instruction in the block.
347 MachineInstr *LastInst = &*I;
348 MachineInstr *SecondLastInst = nullptr;
349 // Find one more terminator if present.
351 if (&*I != LastInst && !I->isBundle() && isUnpredicatedTerminator(&*I)) {
353 SecondLastInst = &*I;
355 // This is a third branch.
358 if (I == MBB.instr_begin())
363 int LastOpcode = LastInst->getOpcode();
364 int SecLastOpcode = SecondLastInst ? SecondLastInst->getOpcode() : 0;
365 // If the branch target is not a basic block, it could be a tail call.
366 // (It is, if the target is a function.)
367 if (LastOpcode == Hexagon::J2_jump && !LastInst->getOperand(0).isMBB())
369 if (SecLastOpcode == Hexagon::J2_jump &&
370 !SecondLastInst->getOperand(0).isMBB())
373 bool LastOpcodeHasJMP_c = PredOpcodeHasJMP_c(LastOpcode);
374 bool LastOpcodeHasNVJump = isNewValueJump(LastInst);
376 // If there is only one terminator instruction, process it.
377 if (LastInst && !SecondLastInst) {
378 if (LastOpcode == Hexagon::J2_jump) {
379 TBB = LastInst->getOperand(0).getMBB();
382 if (isEndLoopN(LastOpcode)) {
383 TBB = LastInst->getOperand(0).getMBB();
384 Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
385 Cond.push_back(LastInst->getOperand(0));
388 if (LastOpcodeHasJMP_c) {
389 TBB = LastInst->getOperand(1).getMBB();
390 Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
391 Cond.push_back(LastInst->getOperand(0));
394 // Only supporting rr/ri versions of new-value jumps.
395 if (LastOpcodeHasNVJump && (LastInst->getNumExplicitOperands() == 3)) {
396 TBB = LastInst->getOperand(2).getMBB();
397 Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
398 Cond.push_back(LastInst->getOperand(0));
399 Cond.push_back(LastInst->getOperand(1));
402 DEBUG(dbgs() << "\nCant analyze BB#" << MBB.getNumber()
403 << " with one jump\n";);
404 // Otherwise, don't know what this is.
408 bool SecLastOpcodeHasJMP_c = PredOpcodeHasJMP_c(SecLastOpcode);
409 bool SecLastOpcodeHasNVJump = isNewValueJump(SecondLastInst);
410 if (SecLastOpcodeHasJMP_c && (LastOpcode == Hexagon::J2_jump)) {
411 TBB = SecondLastInst->getOperand(1).getMBB();
412 Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
413 Cond.push_back(SecondLastInst->getOperand(0));
414 FBB = LastInst->getOperand(0).getMBB();
418 // Only supporting rr/ri versions of new-value jumps.
419 if (SecLastOpcodeHasNVJump &&
420 (SecondLastInst->getNumExplicitOperands() == 3) &&
421 (LastOpcode == Hexagon::J2_jump)) {
422 TBB = SecondLastInst->getOperand(2).getMBB();
423 Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
424 Cond.push_back(SecondLastInst->getOperand(0));
425 Cond.push_back(SecondLastInst->getOperand(1));
426 FBB = LastInst->getOperand(0).getMBB();
430 // If the block ends with two Hexagon:JMPs, handle it. The second one is not
431 // executed, so remove it.
432 if (SecLastOpcode == Hexagon::J2_jump && LastOpcode == Hexagon::J2_jump) {
433 TBB = SecondLastInst->getOperand(0).getMBB();
434 I = LastInst->getIterator();
436 I->eraseFromParent();
440 // If the block ends with an ENDLOOP, and J2_jump, handle it.
441 if (isEndLoopN(SecLastOpcode) && LastOpcode == Hexagon::J2_jump) {
442 TBB = SecondLastInst->getOperand(0).getMBB();
443 Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
444 Cond.push_back(SecondLastInst->getOperand(0));
445 FBB = LastInst->getOperand(0).getMBB();
448 DEBUG(dbgs() << "\nCant analyze BB#" << MBB.getNumber()
449 << " with two jumps";);
450 // Otherwise, can't handle this.
455 unsigned HexagonInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
456 DEBUG(dbgs() << "\nRemoving branches out of BB#" << MBB.getNumber());
457 MachineBasicBlock::iterator I = MBB.end();
459 while (I != MBB.begin()) {
461 if (I->isDebugValue())
463 // Only removing branches from end of MBB.
466 if (Count && (I->getOpcode() == Hexagon::J2_jump))
467 llvm_unreachable("Malformed basic block: unconditional branch not last");
468 MBB.erase(&MBB.back());
476 unsigned HexagonInstrInfo::InsertBranch(MachineBasicBlock &MBB,
477 MachineBasicBlock *TBB, MachineBasicBlock *FBB,
478 ArrayRef<MachineOperand> Cond, DebugLoc DL) const {
479 unsigned BOpc = Hexagon::J2_jump;
480 unsigned BccOpc = Hexagon::J2_jumpt;
481 assert(validateBranchCond(Cond) && "Invalid branching condition");
482 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
484 // Check if ReverseBranchCondition has asked to reverse this branch
485 // If we want to reverse the branch an odd number of times, we want
487 if (!Cond.empty() && Cond[0].isImm())
488 BccOpc = Cond[0].getImm();
492 // Due to a bug in TailMerging/CFG Optimization, we need to add a
493 // special case handling of a predicated jump followed by an
494 // unconditional jump. If not, Tail Merging and CFG Optimization go
495 // into an infinite loop.
496 MachineBasicBlock *NewTBB, *NewFBB;
497 SmallVector<MachineOperand, 4> Cond;
498 MachineInstr *Term = MBB.getFirstTerminator();
499 if (Term != MBB.end() && isPredicated(Term) &&
500 !AnalyzeBranch(MBB, NewTBB, NewFBB, Cond, false)) {
501 MachineBasicBlock *NextBB = &*++MBB.getIterator();
502 if (NewTBB == NextBB) {
503 ReverseBranchCondition(Cond);
505 return InsertBranch(MBB, TBB, nullptr, Cond, DL);
508 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
509 } else if (isEndLoopN(Cond[0].getImm())) {
510 int EndLoopOp = Cond[0].getImm();
511 assert(Cond[1].isMBB());
512 // Since we're adding an ENDLOOP, there better be a LOOP instruction.
513 // Check for it, and change the BB target if needed.
514 SmallPtrSet<MachineBasicBlock *, 8> VisitedBBs;
515 MachineInstr *Loop = findLoopInstr(TBB, EndLoopOp, VisitedBBs);
516 assert(Loop != 0 && "Inserting an ENDLOOP without a LOOP");
517 Loop->getOperand(0).setMBB(TBB);
518 // Add the ENDLOOP after the finding the LOOP0.
519 BuildMI(&MBB, DL, get(EndLoopOp)).addMBB(TBB);
520 } else if (isNewValueJump(Cond[0].getImm())) {
521 assert((Cond.size() == 3) && "Only supporting rr/ri version of nvjump");
523 // (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset)
524 // (ins IntRegs:$src1, u5Imm:$src2, brtarget:$offset)
525 unsigned Flags1 = getUndefRegState(Cond[1].isUndef());
526 DEBUG(dbgs() << "\nInserting NVJump for BB#" << MBB.getNumber(););
527 if (Cond[2].isReg()) {
528 unsigned Flags2 = getUndefRegState(Cond[2].isUndef());
529 BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[1].getReg(), Flags1).
530 addReg(Cond[2].getReg(), Flags2).addMBB(TBB);
531 } else if(Cond[2].isImm()) {
532 BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[1].getReg(), Flags1).
533 addImm(Cond[2].getImm()).addMBB(TBB);
535 llvm_unreachable("Invalid condition for branching");
537 assert((Cond.size() == 2) && "Malformed cond vector");
538 const MachineOperand &RO = Cond[1];
539 unsigned Flags = getUndefRegState(RO.isUndef());
540 BuildMI(&MBB, DL, get(BccOpc)).addReg(RO.getReg(), Flags).addMBB(TBB);
544 assert((!Cond.empty()) &&
545 "Cond. cannot be empty when multiple branchings are required");
546 assert((!isNewValueJump(Cond[0].getImm())) &&
547 "NV-jump cannot be inserted with another branch");
548 // Special case for hardware loops. The condition is a basic block.
549 if (isEndLoopN(Cond[0].getImm())) {
550 int EndLoopOp = Cond[0].getImm();
551 assert(Cond[1].isMBB());
552 // Since we're adding an ENDLOOP, there better be a LOOP instruction.
553 // Check for it, and change the BB target if needed.
554 SmallPtrSet<MachineBasicBlock *, 8> VisitedBBs;
555 MachineInstr *Loop = findLoopInstr(TBB, EndLoopOp, VisitedBBs);
556 assert(Loop != 0 && "Inserting an ENDLOOP without a LOOP");
557 Loop->getOperand(0).setMBB(TBB);
558 // Add the ENDLOOP after the finding the LOOP0.
559 BuildMI(&MBB, DL, get(EndLoopOp)).addMBB(TBB);
561 const MachineOperand &RO = Cond[1];
562 unsigned Flags = getUndefRegState(RO.isUndef());
563 BuildMI(&MBB, DL, get(BccOpc)).addReg(RO.getReg(), Flags).addMBB(TBB);
565 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
571 bool HexagonInstrInfo::isProfitableToIfCvt(MachineBasicBlock &MBB,
572 unsigned NumCycles, unsigned ExtraPredCycles,
573 BranchProbability Probability) const {
574 return nonDbgBBSize(&MBB) <= 3;
578 bool HexagonInstrInfo::isProfitableToIfCvt(MachineBasicBlock &TMBB,
579 unsigned NumTCycles, unsigned ExtraTCycles, MachineBasicBlock &FMBB,
580 unsigned NumFCycles, unsigned ExtraFCycles, BranchProbability Probability)
582 return nonDbgBBSize(&TMBB) <= 3 && nonDbgBBSize(&FMBB) <= 3;
586 bool HexagonInstrInfo::isProfitableToDupForIfCvt(MachineBasicBlock &MBB,
587 unsigned NumInstrs, BranchProbability Probability) const {
588 return NumInstrs <= 4;
592 void HexagonInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
593 MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg,
594 unsigned SrcReg, bool KillSrc) const {
595 auto &HRI = getRegisterInfo();
596 if (Hexagon::IntRegsRegClass.contains(SrcReg, DestReg)) {
597 BuildMI(MBB, I, DL, get(Hexagon::A2_tfr), DestReg).addReg(SrcReg);
600 if (Hexagon::DoubleRegsRegClass.contains(SrcReg, DestReg)) {
601 BuildMI(MBB, I, DL, get(Hexagon::A2_tfrp), DestReg).addReg(SrcReg);
604 if (Hexagon::PredRegsRegClass.contains(SrcReg, DestReg)) {
605 // Map Pd = Ps to Pd = or(Ps, Ps).
606 BuildMI(MBB, I, DL, get(Hexagon::C2_or),
607 DestReg).addReg(SrcReg).addReg(SrcReg);
610 if (Hexagon::DoubleRegsRegClass.contains(DestReg) &&
611 Hexagon::IntRegsRegClass.contains(SrcReg)) {
612 // We can have an overlap between single and double reg: r1:0 = r0.
613 if(SrcReg == RI.getSubReg(DestReg, Hexagon::subreg_loreg)) {
615 BuildMI(MBB, I, DL, get(Hexagon::A2_tfrsi), (RI.getSubReg(DestReg,
616 Hexagon::subreg_hireg))).addImm(0);
618 // r1:0 = r1 or no overlap.
619 BuildMI(MBB, I, DL, get(Hexagon::A2_tfr), (RI.getSubReg(DestReg,
620 Hexagon::subreg_loreg))).addReg(SrcReg);
621 BuildMI(MBB, I, DL, get(Hexagon::A2_tfrsi), (RI.getSubReg(DestReg,
622 Hexagon::subreg_hireg))).addImm(0);
626 if (Hexagon::CtrRegsRegClass.contains(DestReg) &&
627 Hexagon::IntRegsRegClass.contains(SrcReg)) {
628 BuildMI(MBB, I, DL, get(Hexagon::A2_tfrrcr), DestReg).addReg(SrcReg);
631 if (Hexagon::PredRegsRegClass.contains(SrcReg) &&
632 Hexagon::IntRegsRegClass.contains(DestReg)) {
633 BuildMI(MBB, I, DL, get(Hexagon::C2_tfrpr), DestReg).
634 addReg(SrcReg, getKillRegState(KillSrc));
637 if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
638 Hexagon::PredRegsRegClass.contains(DestReg)) {
639 BuildMI(MBB, I, DL, get(Hexagon::C2_tfrrp), DestReg).
640 addReg(SrcReg, getKillRegState(KillSrc));
643 if (Hexagon::PredRegsRegClass.contains(SrcReg) &&
644 Hexagon::IntRegsRegClass.contains(DestReg)) {
645 BuildMI(MBB, I, DL, get(Hexagon::C2_tfrpr), DestReg).
646 addReg(SrcReg, getKillRegState(KillSrc));
649 if (Hexagon::VectorRegsRegClass.contains(SrcReg, DestReg)) {
650 BuildMI(MBB, I, DL, get(Hexagon::V6_vassign), DestReg).
651 addReg(SrcReg, getKillRegState(KillSrc));
654 if (Hexagon::VecDblRegsRegClass.contains(SrcReg, DestReg)) {
655 BuildMI(MBB, I, DL, get(Hexagon::V6_vcombine), DestReg).
656 addReg(HRI.getSubReg(SrcReg, Hexagon::subreg_hireg),
657 getKillRegState(KillSrc)).
658 addReg(HRI.getSubReg(SrcReg, Hexagon::subreg_loreg),
659 getKillRegState(KillSrc));
662 if (Hexagon::VecPredRegsRegClass.contains(SrcReg, DestReg)) {
663 BuildMI(MBB, I, DL, get(Hexagon::V6_pred_and), DestReg).
665 addReg(SrcReg, getKillRegState(KillSrc));
668 if (Hexagon::VecPredRegsRegClass.contains(SrcReg) &&
669 Hexagon::VectorRegsRegClass.contains(DestReg)) {
670 llvm_unreachable("Unimplemented pred to vec");
673 if (Hexagon::VecPredRegsRegClass.contains(DestReg) &&
674 Hexagon::VectorRegsRegClass.contains(SrcReg)) {
675 llvm_unreachable("Unimplemented vec to pred");
678 if (Hexagon::VecPredRegs128BRegClass.contains(SrcReg, DestReg)) {
679 BuildMI(MBB, I, DL, get(Hexagon::V6_pred_and),
680 HRI.getSubReg(DestReg, Hexagon::subreg_hireg)).
681 addReg(HRI.getSubReg(SrcReg, Hexagon::subreg_hireg),
682 getKillRegState(KillSrc));
683 BuildMI(MBB, I, DL, get(Hexagon::V6_pred_and),
684 HRI.getSubReg(DestReg, Hexagon::subreg_loreg)).
685 addReg(HRI.getSubReg(SrcReg, Hexagon::subreg_loreg),
686 getKillRegState(KillSrc));
691 // Show the invalid registers to ease debugging.
692 dbgs() << "Invalid registers for copy in BB#" << MBB.getNumber()
693 << ": " << PrintReg(DestReg, &HRI)
694 << " = " << PrintReg(SrcReg, &HRI) << '\n';
696 llvm_unreachable("Unimplemented");
700 void HexagonInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
701 MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FI,
702 const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const {
703 DebugLoc DL = MBB.findDebugLoc(I);
704 MachineFunction &MF = *MBB.getParent();
705 MachineFrameInfo &MFI = *MF.getFrameInfo();
706 unsigned Align = MFI.getObjectAlignment(FI);
708 MachineMemOperand *MMO = MF.getMachineMemOperand(
709 MachinePointerInfo::getFixedStack(MF, FI), MachineMemOperand::MOStore,
710 MFI.getObjectSize(FI), Align);
712 if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {
713 BuildMI(MBB, I, DL, get(Hexagon::S2_storeri_io))
714 .addFrameIndex(FI).addImm(0)
715 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
716 } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {
717 BuildMI(MBB, I, DL, get(Hexagon::S2_storerd_io))
718 .addFrameIndex(FI).addImm(0)
719 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
720 } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {
721 BuildMI(MBB, I, DL, get(Hexagon::STriw_pred))
722 .addFrameIndex(FI).addImm(0)
723 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
725 llvm_unreachable("Unimplemented");
730 void HexagonInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
731 MachineBasicBlock::iterator I, unsigned DestReg, int FI,
732 const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const {
733 DebugLoc DL = MBB.findDebugLoc(I);
734 MachineFunction &MF = *MBB.getParent();
735 MachineFrameInfo &MFI = *MF.getFrameInfo();
736 unsigned Align = MFI.getObjectAlignment(FI);
738 MachineMemOperand *MMO = MF.getMachineMemOperand(
739 MachinePointerInfo::getFixedStack(MF, FI), MachineMemOperand::MOLoad,
740 MFI.getObjectSize(FI), Align);
741 if (RC == &Hexagon::IntRegsRegClass) {
742 BuildMI(MBB, I, DL, get(Hexagon::L2_loadri_io), DestReg)
743 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
744 } else if (RC == &Hexagon::DoubleRegsRegClass) {
745 BuildMI(MBB, I, DL, get(Hexagon::L2_loadrd_io), DestReg)
746 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
747 } else if (RC == &Hexagon::PredRegsRegClass) {
748 BuildMI(MBB, I, DL, get(Hexagon::LDriw_pred), DestReg)
749 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
751 llvm_unreachable("Can't store this register to stack slot");
756 /// expandPostRAPseudo - This function is called for all pseudo instructions
757 /// that remain after register allocation. Many pseudo instructions are
758 /// created to help register allocation. This is the place to convert them
759 /// into real instructions. The target can edit MI in place, or it can insert
760 /// new instructions and erase MI. The function should return true if
761 /// anything was changed.
762 bool HexagonInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI)
764 const HexagonRegisterInfo &HRI = getRegisterInfo();
765 MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
766 MachineBasicBlock &MBB = *MI->getParent();
767 DebugLoc DL = MI->getDebugLoc();
768 unsigned Opc = MI->getOpcode();
769 const unsigned VecOffset = 1;
773 case Hexagon::ALIGNA:
774 BuildMI(MBB, MI, DL, get(Hexagon::A2_andir), MI->getOperand(0).getReg())
775 .addReg(HRI.getFrameRegister())
776 .addImm(-MI->getOperand(1).getImm());
779 case Hexagon::HEXAGON_V6_vassignp_128B:
780 case Hexagon::HEXAGON_V6_vassignp: {
781 unsigned SrcReg = MI->getOperand(1).getReg();
782 unsigned DstReg = MI->getOperand(0).getReg();
783 if (SrcReg != DstReg)
784 copyPhysReg(MBB, MI, DL, DstReg, SrcReg, MI->getOperand(1).isKill());
788 case Hexagon::HEXAGON_V6_lo_128B:
789 case Hexagon::HEXAGON_V6_lo: {
790 unsigned SrcReg = MI->getOperand(1).getReg();
791 unsigned DstReg = MI->getOperand(0).getReg();
792 unsigned SrcSubLo = HRI.getSubReg(SrcReg, Hexagon::subreg_loreg);
793 copyPhysReg(MBB, MI, DL, DstReg, SrcSubLo, MI->getOperand(1).isKill());
795 MRI.clearKillFlags(SrcSubLo);
798 case Hexagon::HEXAGON_V6_hi_128B:
799 case Hexagon::HEXAGON_V6_hi: {
800 unsigned SrcReg = MI->getOperand(1).getReg();
801 unsigned DstReg = MI->getOperand(0).getReg();
802 unsigned SrcSubHi = HRI.getSubReg(SrcReg, Hexagon::subreg_hireg);
803 copyPhysReg(MBB, MI, DL, DstReg, SrcSubHi, MI->getOperand(1).isKill());
805 MRI.clearKillFlags(SrcSubHi);
808 case Hexagon::STrivv_indexed_128B:
810 case Hexagon::STrivv_indexed: {
811 unsigned SrcReg = MI->getOperand(2).getReg();
812 unsigned SrcSubHi = HRI.getSubReg(SrcReg, Hexagon::subreg_hireg);
813 unsigned SrcSubLo = HRI.getSubReg(SrcReg, Hexagon::subreg_loreg);
814 unsigned NewOpcd = Is128B ? Hexagon::V6_vS32b_ai_128B
815 : Hexagon::V6_vS32b_ai;
816 unsigned Offset = Is128B ? VecOffset << 7 : VecOffset << 6;
817 MachineInstr *MI1New = BuildMI(MBB, MI, DL, get(NewOpcd))
818 .addOperand(MI->getOperand(0))
819 .addImm(MI->getOperand(1).getImm())
821 .setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
822 MI1New->getOperand(0).setIsKill(false);
823 BuildMI(MBB, MI, DL, get(NewOpcd))
824 .addOperand(MI->getOperand(0))
825 // The Vectors are indexed in multiples of vector size.
826 .addImm(MI->getOperand(1).getImm()+Offset)
828 .setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
832 case Hexagon::LDrivv_pseudo_V6_128B:
833 case Hexagon::LDrivv_indexed_128B:
835 case Hexagon::LDrivv_pseudo_V6:
836 case Hexagon::LDrivv_indexed: {
837 unsigned NewOpcd = Is128B ? Hexagon::V6_vL32b_ai_128B
838 : Hexagon::V6_vL32b_ai;
839 unsigned DstReg = MI->getOperand(0).getReg();
840 unsigned Offset = Is128B ? VecOffset << 7 : VecOffset << 6;
841 MachineInstr *MI1New =
842 BuildMI(MBB, MI, DL, get(NewOpcd),
843 HRI.getSubReg(DstReg, Hexagon::subreg_loreg))
844 .addOperand(MI->getOperand(1))
845 .addImm(MI->getOperand(2).getImm());
846 MI1New->getOperand(1).setIsKill(false);
847 BuildMI(MBB, MI, DL, get(NewOpcd),
848 HRI.getSubReg(DstReg, Hexagon::subreg_hireg))
849 .addOperand(MI->getOperand(1))
850 // The Vectors are indexed in multiples of vector size.
851 .addImm(MI->getOperand(2).getImm() + Offset)
852 .setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
856 case Hexagon::LDriv_pseudo_V6_128B:
858 case Hexagon::LDriv_pseudo_V6: {
859 unsigned DstReg = MI->getOperand(0).getReg();
860 unsigned NewOpc = Is128B ? Hexagon::V6_vL32b_ai_128B
861 : Hexagon::V6_vL32b_ai;
862 int32_t Off = MI->getOperand(2).getImm();
864 BuildMI(MBB, MI, DL, get(NewOpc), DstReg)
865 .addOperand(MI->getOperand(1))
867 .setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
871 case Hexagon::STriv_pseudo_V6_128B:
873 case Hexagon::STriv_pseudo_V6: {
874 unsigned NewOpc = Is128B ? Hexagon::V6_vS32b_ai_128B
875 : Hexagon::V6_vS32b_ai;
876 int32_t Off = MI->getOperand(1).getImm();
877 int32_t Idx = Is128B ? (Off >> 7) : (Off >> 6);
878 BuildMI(MBB, MI, DL, get(NewOpc))
879 .addOperand(MI->getOperand(0))
881 .addOperand(MI->getOperand(2))
882 .setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
886 case Hexagon::TFR_PdTrue: {
887 unsigned Reg = MI->getOperand(0).getReg();
888 BuildMI(MBB, MI, DL, get(Hexagon::C2_orn), Reg)
889 .addReg(Reg, RegState::Undef)
890 .addReg(Reg, RegState::Undef);
894 case Hexagon::TFR_PdFalse: {
895 unsigned Reg = MI->getOperand(0).getReg();
896 BuildMI(MBB, MI, DL, get(Hexagon::C2_andn), Reg)
897 .addReg(Reg, RegState::Undef)
898 .addReg(Reg, RegState::Undef);
902 case Hexagon::VMULW: {
903 // Expand a 64-bit vector multiply into 2 32-bit scalar multiplies.
904 unsigned DstReg = MI->getOperand(0).getReg();
905 unsigned Src1Reg = MI->getOperand(1).getReg();
906 unsigned Src2Reg = MI->getOperand(2).getReg();
907 unsigned Src1SubHi = HRI.getSubReg(Src1Reg, Hexagon::subreg_hireg);
908 unsigned Src1SubLo = HRI.getSubReg(Src1Reg, Hexagon::subreg_loreg);
909 unsigned Src2SubHi = HRI.getSubReg(Src2Reg, Hexagon::subreg_hireg);
910 unsigned Src2SubLo = HRI.getSubReg(Src2Reg, Hexagon::subreg_loreg);
911 BuildMI(MBB, MI, MI->getDebugLoc(), get(Hexagon::M2_mpyi),
912 HRI.getSubReg(DstReg, Hexagon::subreg_hireg)).addReg(Src1SubHi)
914 BuildMI(MBB, MI, MI->getDebugLoc(), get(Hexagon::M2_mpyi),
915 HRI.getSubReg(DstReg, Hexagon::subreg_loreg)).addReg(Src1SubLo)
918 MRI.clearKillFlags(Src1SubHi);
919 MRI.clearKillFlags(Src1SubLo);
920 MRI.clearKillFlags(Src2SubHi);
921 MRI.clearKillFlags(Src2SubLo);
924 case Hexagon::VMULW_ACC: {
925 // Expand 64-bit vector multiply with addition into 2 scalar multiplies.
926 unsigned DstReg = MI->getOperand(0).getReg();
927 unsigned Src1Reg = MI->getOperand(1).getReg();
928 unsigned Src2Reg = MI->getOperand(2).getReg();
929 unsigned Src3Reg = MI->getOperand(3).getReg();
930 unsigned Src1SubHi = HRI.getSubReg(Src1Reg, Hexagon::subreg_hireg);
931 unsigned Src1SubLo = HRI.getSubReg(Src1Reg, Hexagon::subreg_loreg);
932 unsigned Src2SubHi = HRI.getSubReg(Src2Reg, Hexagon::subreg_hireg);
933 unsigned Src2SubLo = HRI.getSubReg(Src2Reg, Hexagon::subreg_loreg);
934 unsigned Src3SubHi = HRI.getSubReg(Src3Reg, Hexagon::subreg_hireg);
935 unsigned Src3SubLo = HRI.getSubReg(Src3Reg, Hexagon::subreg_loreg);
936 BuildMI(MBB, MI, MI->getDebugLoc(), get(Hexagon::M2_maci),
937 HRI.getSubReg(DstReg, Hexagon::subreg_hireg)).addReg(Src1SubHi)
938 .addReg(Src2SubHi).addReg(Src3SubHi);
939 BuildMI(MBB, MI, MI->getDebugLoc(), get(Hexagon::M2_maci),
940 HRI.getSubReg(DstReg, Hexagon::subreg_loreg)).addReg(Src1SubLo)
941 .addReg(Src2SubLo).addReg(Src3SubLo);
943 MRI.clearKillFlags(Src1SubHi);
944 MRI.clearKillFlags(Src1SubLo);
945 MRI.clearKillFlags(Src2SubHi);
946 MRI.clearKillFlags(Src2SubLo);
947 MRI.clearKillFlags(Src3SubHi);
948 MRI.clearKillFlags(Src3SubLo);
951 case Hexagon::MUX64_rr: {
952 const MachineOperand &Op0 = MI->getOperand(0);
953 const MachineOperand &Op1 = MI->getOperand(1);
954 const MachineOperand &Op2 = MI->getOperand(2);
955 const MachineOperand &Op3 = MI->getOperand(3);
956 unsigned Rd = Op0.getReg();
957 unsigned Pu = Op1.getReg();
958 unsigned Rs = Op2.getReg();
959 unsigned Rt = Op3.getReg();
960 DebugLoc DL = MI->getDebugLoc();
961 unsigned K1 = getKillRegState(Op1.isKill());
962 unsigned K2 = getKillRegState(Op2.isKill());
963 unsigned K3 = getKillRegState(Op3.isKill());
965 BuildMI(MBB, MI, DL, get(Hexagon::A2_tfrpt), Rd)
966 .addReg(Pu, (Rd == Rt) ? K1 : 0)
969 BuildMI(MBB, MI, DL, get(Hexagon::A2_tfrpf), Rd)
975 case Hexagon::TCRETURNi:
976 MI->setDesc(get(Hexagon::J2_jump));
978 case Hexagon::TCRETURNr:
979 MI->setDesc(get(Hexagon::J2_jumpr));
981 case Hexagon::TFRI_f:
982 case Hexagon::TFRI_cPt_f:
983 case Hexagon::TFRI_cNotPt_f: {
984 unsigned Opx = (Opc == Hexagon::TFRI_f) ? 1 : 2;
985 APFloat FVal = MI->getOperand(Opx).getFPImm()->getValueAPF();
986 APInt IVal = FVal.bitcastToAPInt();
987 MI->RemoveOperand(Opx);
988 unsigned NewOpc = (Opc == Hexagon::TFRI_f) ? Hexagon::A2_tfrsi :
989 (Opc == Hexagon::TFRI_cPt_f) ? Hexagon::C2_cmoveit :
991 MI->setDesc(get(NewOpc));
992 MI->addOperand(MachineOperand::CreateImm(IVal.getZExtValue()));
1001 // We indicate that we want to reverse the branch by
1002 // inserting the reversed branching opcode.
1003 bool HexagonInstrInfo::ReverseBranchCondition(
1004 SmallVectorImpl<MachineOperand> &Cond) const {
1007 assert(Cond[0].isImm() && "First entry in the cond vector not imm-val");
1008 unsigned opcode = Cond[0].getImm();
1010 assert(get(opcode).isBranch() && "Should be a branching condition.");
1011 if (isEndLoopN(opcode))
1013 unsigned NewOpcode = getInvertedPredicatedOpcode(opcode);
1014 Cond[0].setImm(NewOpcode);
1019 void HexagonInstrInfo::insertNoop(MachineBasicBlock &MBB,
1020 MachineBasicBlock::iterator MI) const {
1022 BuildMI(MBB, MI, DL, get(Hexagon::A2_nop));
1026 // Returns true if an instruction is predicated irrespective of the predicate
1027 // sense. For example, all of the following will return true.
1028 // if (p0) R1 = add(R2, R3)
1029 // if (!p0) R1 = add(R2, R3)
1030 // if (p0.new) R1 = add(R2, R3)
1031 // if (!p0.new) R1 = add(R2, R3)
1032 // Note: New-value stores are not included here as in the current
1033 // implementation, we don't need to check their predicate sense.
1034 bool HexagonInstrInfo::isPredicated(const MachineInstr *MI) const {
1035 const uint64_t F = MI->getDesc().TSFlags;
1036 return (F >> HexagonII::PredicatedPos) & HexagonII::PredicatedMask;
1040 bool HexagonInstrInfo::PredicateInstruction(MachineInstr *MI,
1041 ArrayRef<MachineOperand> Cond) const {
1042 if (Cond.empty() || isNewValueJump(Cond[0].getImm()) ||
1043 isEndLoopN(Cond[0].getImm())) {
1044 DEBUG(dbgs() << "\nCannot predicate:"; MI->dump(););
1047 int Opc = MI->getOpcode();
1048 assert (isPredicable(MI) && "Expected predicable instruction");
1049 bool invertJump = predOpcodeHasNot(Cond);
1051 // We have to predicate MI "in place", i.e. after this function returns,
1052 // MI will need to be transformed into a predicated form. To avoid com-
1053 // plicated manipulations with the operands (handling tied operands,
1054 // etc.), build a new temporary instruction, then overwrite MI with it.
1056 MachineBasicBlock &B = *MI->getParent();
1057 DebugLoc DL = MI->getDebugLoc();
1058 unsigned PredOpc = getCondOpcode(Opc, invertJump);
1059 MachineInstrBuilder T = BuildMI(B, MI, DL, get(PredOpc));
1060 unsigned NOp = 0, NumOps = MI->getNumOperands();
1061 while (NOp < NumOps) {
1062 MachineOperand &Op = MI->getOperand(NOp);
1063 if (!Op.isReg() || !Op.isDef() || Op.isImplicit())
1069 unsigned PredReg, PredRegPos, PredRegFlags;
1070 bool GotPredReg = getPredReg(Cond, PredReg, PredRegPos, PredRegFlags);
1073 T.addReg(PredReg, PredRegFlags);
1074 while (NOp < NumOps)
1075 T.addOperand(MI->getOperand(NOp++));
1077 MI->setDesc(get(PredOpc));
1078 while (unsigned n = MI->getNumOperands())
1079 MI->RemoveOperand(n-1);
1080 for (unsigned i = 0, n = T->getNumOperands(); i < n; ++i)
1081 MI->addOperand(T->getOperand(i));
1083 MachineBasicBlock::instr_iterator TI = T->getIterator();
1086 MachineRegisterInfo &MRI = B.getParent()->getRegInfo();
1087 MRI.clearKillFlags(PredReg);
1092 bool HexagonInstrInfo::SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
1093 ArrayRef<MachineOperand> Pred2) const {
1099 bool HexagonInstrInfo::DefinesPredicate(MachineInstr *MI,
1100 std::vector<MachineOperand> &Pred) const {
1101 auto &HRI = getRegisterInfo();
1102 for (unsigned oper = 0; oper < MI->getNumOperands(); ++oper) {
1103 MachineOperand MO = MI->getOperand(oper);
1104 if (MO.isReg() && MO.isDef()) {
1105 const TargetRegisterClass* RC = HRI.getMinimalPhysRegClass(MO.getReg());
1106 if (RC == &Hexagon::PredRegsRegClass) {
1115 bool HexagonInstrInfo::isPredicable(MachineInstr *MI) const {
1116 bool isPred = MI->getDesc().isPredicable();
1121 const int Opc = MI->getOpcode();
1122 int NumOperands = MI->getNumOperands();
1124 // Keep a flag for upto 4 operands in the instructions, to indicate if
1125 // that operand has been constant extended.
1126 bool OpCExtended[4];
1127 if (NumOperands > 4)
1130 for (int i = 0; i < NumOperands; i++)
1131 OpCExtended[i] = (isOperandExtended(MI, i) && isConstExtended(MI));
1134 case Hexagon::A2_tfrsi:
1135 return (isOperandExtended(MI, 1) && isConstExtended(MI)) ||
1136 isInt<12>(MI->getOperand(1).getImm());
1138 case Hexagon::S2_storerd_io:
1139 return isShiftedUInt<6,3>(MI->getOperand(1).getImm());
1141 case Hexagon::S2_storeri_io:
1142 case Hexagon::S2_storerinew_io:
1143 return isShiftedUInt<6,2>(MI->getOperand(1).getImm());
1145 case Hexagon::S2_storerh_io:
1146 case Hexagon::S2_storerhnew_io:
1147 return isShiftedUInt<6,1>(MI->getOperand(1).getImm());
1149 case Hexagon::S2_storerb_io:
1150 case Hexagon::S2_storerbnew_io:
1151 return isUInt<6>(MI->getOperand(1).getImm());
1153 case Hexagon::L2_loadrd_io:
1154 return isShiftedUInt<6,3>(MI->getOperand(2).getImm());
1156 case Hexagon::L2_loadri_io:
1157 return isShiftedUInt<6,2>(MI->getOperand(2).getImm());
1159 case Hexagon::L2_loadrh_io:
1160 case Hexagon::L2_loadruh_io:
1161 return isShiftedUInt<6,1>(MI->getOperand(2).getImm());
1163 case Hexagon::L2_loadrb_io:
1164 case Hexagon::L2_loadrub_io:
1165 return isUInt<6>(MI->getOperand(2).getImm());
1167 case Hexagon::L2_loadrd_pi:
1168 return isShiftedInt<4,3>(MI->getOperand(3).getImm());
1170 case Hexagon::L2_loadri_pi:
1171 return isShiftedInt<4,2>(MI->getOperand(3).getImm());
1173 case Hexagon::L2_loadrh_pi:
1174 case Hexagon::L2_loadruh_pi:
1175 return isShiftedInt<4,1>(MI->getOperand(3).getImm());
1177 case Hexagon::L2_loadrb_pi:
1178 case Hexagon::L2_loadrub_pi:
1179 return isInt<4>(MI->getOperand(3).getImm());
1181 case Hexagon::S4_storeirb_io:
1182 case Hexagon::S4_storeirh_io:
1183 case Hexagon::S4_storeiri_io:
1184 return (OpCExtended[1] || isUInt<6>(MI->getOperand(1).getImm())) &&
1185 (OpCExtended[2] || isInt<6>(MI->getOperand(2).getImm()));
1187 case Hexagon::A2_addi:
1188 return isInt<8>(MI->getOperand(2).getImm());
1190 case Hexagon::A2_aslh:
1191 case Hexagon::A2_asrh:
1192 case Hexagon::A2_sxtb:
1193 case Hexagon::A2_sxth:
1194 case Hexagon::A2_zxtb:
1195 case Hexagon::A2_zxth:
1203 bool HexagonInstrInfo::isSchedulingBoundary(const MachineInstr *MI,
1204 const MachineBasicBlock *MBB, const MachineFunction &MF) const {
1205 // Debug info is never a scheduling boundary. It's necessary to be explicit
1206 // due to the special treatment of IT instructions below, otherwise a
1207 // dbg_value followed by an IT will result in the IT instruction being
1208 // considered a scheduling hazard, which is wrong. It should be the actual
1209 // instruction preceding the dbg_value instruction(s), just like it is
1210 // when debug info is not present.
1211 if (MI->isDebugValue())
1214 // Throwing call is a boundary.
1216 // If any of the block's successors is a landing pad, this could be a
1218 for (auto I : MBB->successors())
1223 // Don't mess around with no return calls.
1224 if (MI->getOpcode() == Hexagon::CALLv3nr)
1227 // Terminators and labels can't be scheduled around.
1228 if (MI->getDesc().isTerminator() || MI->isPosition())
1231 if (MI->isInlineAsm() && !ScheduleInlineAsm)
1238 /// Measure the specified inline asm to determine an approximation of its
1240 /// Comments (which run till the next SeparatorString or newline) do not
1241 /// count as an instruction.
1242 /// Any other non-whitespace text is considered an instruction, with
1243 /// multiple instructions separated by SeparatorString or newlines.
1244 /// Variable-length instructions are not handled here; this function
1245 /// may be overloaded in the target code to do that.
1246 /// Hexagon counts the number of ##'s and adjust for that many
1247 /// constant exenders.
1248 unsigned HexagonInstrInfo::getInlineAsmLength(const char *Str,
1249 const MCAsmInfo &MAI) const {
1250 StringRef AStr(Str);
1251 // Count the number of instructions in the asm.
1252 bool atInsnStart = true;
1253 unsigned Length = 0;
1254 for (; *Str; ++Str) {
1255 if (*Str == '\n' || strncmp(Str, MAI.getSeparatorString(),
1256 strlen(MAI.getSeparatorString())) == 0)
1258 if (atInsnStart && !std::isspace(static_cast<unsigned char>(*Str))) {
1259 Length += MAI.getMaxInstLength();
1260 atInsnStart = false;
1262 if (atInsnStart && strncmp(Str, MAI.getCommentString(),
1263 strlen(MAI.getCommentString())) == 0)
1264 atInsnStart = false;
1267 // Add to size number of constant extenders seen * 4.
1268 StringRef Occ("##");
1269 Length += AStr.count(Occ)*4;
1274 ScheduleHazardRecognizer*
1275 HexagonInstrInfo::CreateTargetPostRAHazardRecognizer(
1276 const InstrItineraryData *II, const ScheduleDAG *DAG) const {
1277 return TargetInstrInfo::CreateTargetPostRAHazardRecognizer(II, DAG);
1281 /// \brief For a comparison instruction, return the source registers in
1282 /// \p SrcReg and \p SrcReg2 if having two register operands, and the value it
1283 /// compares against in CmpValue. Return true if the comparison instruction
1284 /// can be analyzed.
1285 bool HexagonInstrInfo::analyzeCompare(const MachineInstr *MI,
1286 unsigned &SrcReg, unsigned &SrcReg2, int &Mask, int &Value) const {
1287 unsigned Opc = MI->getOpcode();
1289 // Set mask and the first source register.
1291 case Hexagon::C2_cmpeq:
1292 case Hexagon::C2_cmpeqp:
1293 case Hexagon::C2_cmpgt:
1294 case Hexagon::C2_cmpgtp:
1295 case Hexagon::C2_cmpgtu:
1296 case Hexagon::C2_cmpgtup:
1297 case Hexagon::C4_cmpneq:
1298 case Hexagon::C4_cmplte:
1299 case Hexagon::C4_cmplteu:
1300 case Hexagon::C2_cmpeqi:
1301 case Hexagon::C2_cmpgti:
1302 case Hexagon::C2_cmpgtui:
1303 case Hexagon::C4_cmpneqi:
1304 case Hexagon::C4_cmplteui:
1305 case Hexagon::C4_cmpltei:
1306 SrcReg = MI->getOperand(1).getReg();
1309 case Hexagon::A4_cmpbeq:
1310 case Hexagon::A4_cmpbgt:
1311 case Hexagon::A4_cmpbgtu:
1312 case Hexagon::A4_cmpbeqi:
1313 case Hexagon::A4_cmpbgti:
1314 case Hexagon::A4_cmpbgtui:
1315 SrcReg = MI->getOperand(1).getReg();
1318 case Hexagon::A4_cmpheq:
1319 case Hexagon::A4_cmphgt:
1320 case Hexagon::A4_cmphgtu:
1321 case Hexagon::A4_cmpheqi:
1322 case Hexagon::A4_cmphgti:
1323 case Hexagon::A4_cmphgtui:
1324 SrcReg = MI->getOperand(1).getReg();
1329 // Set the value/second source register.
1331 case Hexagon::C2_cmpeq:
1332 case Hexagon::C2_cmpeqp:
1333 case Hexagon::C2_cmpgt:
1334 case Hexagon::C2_cmpgtp:
1335 case Hexagon::C2_cmpgtu:
1336 case Hexagon::C2_cmpgtup:
1337 case Hexagon::A4_cmpbeq:
1338 case Hexagon::A4_cmpbgt:
1339 case Hexagon::A4_cmpbgtu:
1340 case Hexagon::A4_cmpheq:
1341 case Hexagon::A4_cmphgt:
1342 case Hexagon::A4_cmphgtu:
1343 case Hexagon::C4_cmpneq:
1344 case Hexagon::C4_cmplte:
1345 case Hexagon::C4_cmplteu:
1346 SrcReg2 = MI->getOperand(2).getReg();
1349 case Hexagon::C2_cmpeqi:
1350 case Hexagon::C2_cmpgtui:
1351 case Hexagon::C2_cmpgti:
1352 case Hexagon::C4_cmpneqi:
1353 case Hexagon::C4_cmplteui:
1354 case Hexagon::C4_cmpltei:
1355 case Hexagon::A4_cmpbeqi:
1356 case Hexagon::A4_cmpbgti:
1357 case Hexagon::A4_cmpbgtui:
1358 case Hexagon::A4_cmpheqi:
1359 case Hexagon::A4_cmphgti:
1360 case Hexagon::A4_cmphgtui:
1362 Value = MI->getOperand(2).getImm();
1370 unsigned HexagonInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
1371 const MachineInstr *MI, unsigned *PredCost) const {
1372 return getInstrTimingClassLatency(ItinData, MI);
1376 DFAPacketizer *HexagonInstrInfo::CreateTargetScheduleState(
1377 const TargetSubtargetInfo &STI) const {
1378 const InstrItineraryData *II = STI.getInstrItineraryData();
1379 return static_cast<const HexagonSubtarget&>(STI).createDFAPacketizer(II);
1383 // Inspired by this pair:
1384 // %R13<def> = L2_loadri_io %R29, 136; mem:LD4[FixedStack0]
1385 // S2_storeri_io %R29, 132, %R1<kill>; flags: mem:ST4[FixedStack1]
1386 // Currently AA considers the addresses in these instructions to be aliasing.
1387 bool HexagonInstrInfo::areMemAccessesTriviallyDisjoint(MachineInstr *MIa,
1388 MachineInstr *MIb, AliasAnalysis *AA) const {
1389 int OffsetA = 0, OffsetB = 0;
1390 unsigned SizeA = 0, SizeB = 0;
1392 if (MIa->hasUnmodeledSideEffects() || MIb->hasUnmodeledSideEffects() ||
1393 MIa->hasOrderedMemoryRef() || MIa->hasOrderedMemoryRef())
1396 // Instructions that are pure loads, not loads and stores like memops are not
1398 if (MIa->mayLoad() && !isMemOp(MIa) && MIb->mayLoad() && !isMemOp(MIb))
1401 // Get base, offset, and access size in MIa.
1402 unsigned BaseRegA = getBaseAndOffset(MIa, OffsetA, SizeA);
1403 if (!BaseRegA || !SizeA)
1406 // Get base, offset, and access size in MIb.
1407 unsigned BaseRegB = getBaseAndOffset(MIb, OffsetB, SizeB);
1408 if (!BaseRegB || !SizeB)
1411 if (BaseRegA != BaseRegB)
1414 // This is a mem access with the same base register and known offsets from it.
1416 if (OffsetA > OffsetB) {
1417 uint64_t offDiff = (uint64_t)((int64_t)OffsetA - (int64_t)OffsetB);
1418 return (SizeB <= offDiff);
1419 } else if (OffsetA < OffsetB) {
1420 uint64_t offDiff = (uint64_t)((int64_t)OffsetB - (int64_t)OffsetA);
1421 return (SizeA <= offDiff);
1428 unsigned HexagonInstrInfo::createVR(MachineFunction* MF, MVT VT) const {
1429 MachineRegisterInfo &MRI = MF->getRegInfo();
1430 const TargetRegisterClass *TRC;
1431 if (VT == MVT::i1) {
1432 TRC = &Hexagon::PredRegsRegClass;
1433 } else if (VT == MVT::i32 || VT == MVT::f32) {
1434 TRC = &Hexagon::IntRegsRegClass;
1435 } else if (VT == MVT::i64 || VT == MVT::f64) {
1436 TRC = &Hexagon::DoubleRegsRegClass;
1438 llvm_unreachable("Cannot handle this register class");
1441 unsigned NewReg = MRI.createVirtualRegister(TRC);
1446 bool HexagonInstrInfo::isAbsoluteSet(const MachineInstr* MI) const {
1447 return (getAddrMode(MI) == HexagonII::AbsoluteSet);
1451 bool HexagonInstrInfo::isAccumulator(const MachineInstr *MI) const {
1452 const uint64_t F = MI->getDesc().TSFlags;
1453 return((F >> HexagonII::AccumulatorPos) & HexagonII::AccumulatorMask);
1457 bool HexagonInstrInfo::isComplex(const MachineInstr *MI) const {
1458 const MachineFunction *MF = MI->getParent()->getParent();
1459 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
1460 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
1463 && !(QII->isTC2Early(MI))
1464 && !(MI->getDesc().mayLoad())
1465 && !(MI->getDesc().mayStore())
1466 && (MI->getDesc().getOpcode() != Hexagon::S2_allocframe)
1467 && (MI->getDesc().getOpcode() != Hexagon::L2_deallocframe)
1468 && !(QII->isMemOp(MI))
1469 && !(MI->isBranch())
1470 && !(MI->isReturn())
1478 // Return true if the the instruction is a compund branch instruction.
1479 bool HexagonInstrInfo::isCompoundBranchInstr(const MachineInstr *MI) const {
1480 return (getType(MI) == HexagonII::TypeCOMPOUND && MI->isBranch());
1484 bool HexagonInstrInfo::isCondInst(const MachineInstr *MI) const {
1485 return (MI->isBranch() && isPredicated(MI)) ||
1486 isConditionalTransfer(MI) ||
1487 isConditionalALU32(MI) ||
1488 isConditionalLoad(MI) ||
1489 // Predicated stores which don't have a .new on any operands.
1490 (MI->mayStore() && isPredicated(MI) && !isNewValueStore(MI) &&
1491 !isPredicatedNew(MI));
1495 bool HexagonInstrInfo::isConditionalALU32(const MachineInstr* MI) const {
1496 switch (MI->getOpcode()) {
1497 case Hexagon::A2_paddf:
1498 case Hexagon::A2_paddfnew:
1499 case Hexagon::A2_paddif:
1500 case Hexagon::A2_paddifnew:
1501 case Hexagon::A2_paddit:
1502 case Hexagon::A2_padditnew:
1503 case Hexagon::A2_paddt:
1504 case Hexagon::A2_paddtnew:
1505 case Hexagon::A2_pandf:
1506 case Hexagon::A2_pandfnew:
1507 case Hexagon::A2_pandt:
1508 case Hexagon::A2_pandtnew:
1509 case Hexagon::A2_porf:
1510 case Hexagon::A2_porfnew:
1511 case Hexagon::A2_port:
1512 case Hexagon::A2_portnew:
1513 case Hexagon::A2_psubf:
1514 case Hexagon::A2_psubfnew:
1515 case Hexagon::A2_psubt:
1516 case Hexagon::A2_psubtnew:
1517 case Hexagon::A2_pxorf:
1518 case Hexagon::A2_pxorfnew:
1519 case Hexagon::A2_pxort:
1520 case Hexagon::A2_pxortnew:
1521 case Hexagon::A4_paslhf:
1522 case Hexagon::A4_paslhfnew:
1523 case Hexagon::A4_paslht:
1524 case Hexagon::A4_paslhtnew:
1525 case Hexagon::A4_pasrhf:
1526 case Hexagon::A4_pasrhfnew:
1527 case Hexagon::A4_pasrht:
1528 case Hexagon::A4_pasrhtnew:
1529 case Hexagon::A4_psxtbf:
1530 case Hexagon::A4_psxtbfnew:
1531 case Hexagon::A4_psxtbt:
1532 case Hexagon::A4_psxtbtnew:
1533 case Hexagon::A4_psxthf:
1534 case Hexagon::A4_psxthfnew:
1535 case Hexagon::A4_psxtht:
1536 case Hexagon::A4_psxthtnew:
1537 case Hexagon::A4_pzxtbf:
1538 case Hexagon::A4_pzxtbfnew:
1539 case Hexagon::A4_pzxtbt:
1540 case Hexagon::A4_pzxtbtnew:
1541 case Hexagon::A4_pzxthf:
1542 case Hexagon::A4_pzxthfnew:
1543 case Hexagon::A4_pzxtht:
1544 case Hexagon::A4_pzxthtnew:
1545 case Hexagon::C2_ccombinewf:
1546 case Hexagon::C2_ccombinewt:
1553 // FIXME - Function name and it's functionality don't match.
1554 // It should be renamed to hasPredNewOpcode()
1555 bool HexagonInstrInfo::isConditionalLoad(const MachineInstr* MI) const {
1556 if (!MI->getDesc().mayLoad() || !isPredicated(MI))
1559 int PNewOpcode = Hexagon::getPredNewOpcode(MI->getOpcode());
1560 // Instruction with valid predicated-new opcode can be promoted to .new.
1561 return PNewOpcode >= 0;
1565 // Returns true if an instruction is a conditional store.
1567 // Note: It doesn't include conditional new-value stores as they can't be
1568 // converted to .new predicate.
1569 bool HexagonInstrInfo::isConditionalStore(const MachineInstr* MI) const {
1570 switch (MI->getOpcode()) {
1571 default: return false;
1572 case Hexagon::S4_storeirbt_io:
1573 case Hexagon::S4_storeirbf_io:
1574 case Hexagon::S4_pstorerbt_rr:
1575 case Hexagon::S4_pstorerbf_rr:
1576 case Hexagon::S2_pstorerbt_io:
1577 case Hexagon::S2_pstorerbf_io:
1578 case Hexagon::S2_pstorerbt_pi:
1579 case Hexagon::S2_pstorerbf_pi:
1580 case Hexagon::S2_pstorerdt_io:
1581 case Hexagon::S2_pstorerdf_io:
1582 case Hexagon::S4_pstorerdt_rr:
1583 case Hexagon::S4_pstorerdf_rr:
1584 case Hexagon::S2_pstorerdt_pi:
1585 case Hexagon::S2_pstorerdf_pi:
1586 case Hexagon::S2_pstorerht_io:
1587 case Hexagon::S2_pstorerhf_io:
1588 case Hexagon::S4_storeirht_io:
1589 case Hexagon::S4_storeirhf_io:
1590 case Hexagon::S4_pstorerht_rr:
1591 case Hexagon::S4_pstorerhf_rr:
1592 case Hexagon::S2_pstorerht_pi:
1593 case Hexagon::S2_pstorerhf_pi:
1594 case Hexagon::S2_pstorerit_io:
1595 case Hexagon::S2_pstorerif_io:
1596 case Hexagon::S4_storeirit_io:
1597 case Hexagon::S4_storeirif_io:
1598 case Hexagon::S4_pstorerit_rr:
1599 case Hexagon::S4_pstorerif_rr:
1600 case Hexagon::S2_pstorerit_pi:
1601 case Hexagon::S2_pstorerif_pi:
1603 // V4 global address store before promoting to dot new.
1604 case Hexagon::S4_pstorerdt_abs:
1605 case Hexagon::S4_pstorerdf_abs:
1606 case Hexagon::S4_pstorerbt_abs:
1607 case Hexagon::S4_pstorerbf_abs:
1608 case Hexagon::S4_pstorerht_abs:
1609 case Hexagon::S4_pstorerhf_abs:
1610 case Hexagon::S4_pstorerit_abs:
1611 case Hexagon::S4_pstorerif_abs:
1614 // Predicated new value stores (i.e. if (p0) memw(..)=r0.new) are excluded
1615 // from the "Conditional Store" list. Because a predicated new value store
1616 // would NOT be promoted to a double dot new store.
1617 // This function returns yes for those stores that are predicated but not
1618 // yet promoted to predicate dot new instructions.
1623 bool HexagonInstrInfo::isConditionalTransfer(const MachineInstr *MI) const {
1624 switch (MI->getOpcode()) {
1625 case Hexagon::A2_tfrt:
1626 case Hexagon::A2_tfrf:
1627 case Hexagon::C2_cmoveit:
1628 case Hexagon::C2_cmoveif:
1629 case Hexagon::A2_tfrtnew:
1630 case Hexagon::A2_tfrfnew:
1631 case Hexagon::C2_cmovenewit:
1632 case Hexagon::C2_cmovenewif:
1633 case Hexagon::A2_tfrpt:
1634 case Hexagon::A2_tfrpf:
1644 // TODO: In order to have isExtendable for fpimm/f32Ext, we need to handle
1645 // isFPImm and later getFPImm as well.
1646 bool HexagonInstrInfo::isConstExtended(const MachineInstr *MI) const {
1647 const uint64_t F = MI->getDesc().TSFlags;
1648 unsigned isExtended = (F >> HexagonII::ExtendedPos) & HexagonII::ExtendedMask;
1649 if (isExtended) // Instruction must be extended.
1652 unsigned isExtendable =
1653 (F >> HexagonII::ExtendablePos) & HexagonII::ExtendableMask;
1660 short ExtOpNum = getCExtOpNum(MI);
1661 const MachineOperand &MO = MI->getOperand(ExtOpNum);
1662 // Use MO operand flags to determine if MO
1663 // has the HMOTF_ConstExtended flag set.
1664 if (MO.getTargetFlags() && HexagonII::HMOTF_ConstExtended)
1666 // If this is a Machine BB address we are talking about, and it is
1667 // not marked as extended, say so.
1671 // We could be using an instruction with an extendable immediate and shoehorn
1672 // a global address into it. If it is a global address it will be constant
1673 // extended. We do this for COMBINE.
1674 // We currently only handle isGlobal() because it is the only kind of
1675 // object we are going to end up with here for now.
1676 // In the future we probably should add isSymbol(), etc.
1677 if (MO.isGlobal() || MO.isSymbol() || MO.isBlockAddress() ||
1678 MO.isJTI() || MO.isCPI())
1681 // If the extendable operand is not 'Immediate' type, the instruction should
1682 // have 'isExtended' flag set.
1683 assert(MO.isImm() && "Extendable operand must be Immediate type");
1685 int MinValue = getMinValue(MI);
1686 int MaxValue = getMaxValue(MI);
1687 int ImmValue = MO.getImm();
1689 return (ImmValue < MinValue || ImmValue > MaxValue);
1693 bool HexagonInstrInfo::isDeallocRet(const MachineInstr *MI) const {
1694 switch (MI->getOpcode()) {
1695 case Hexagon::L4_return :
1696 case Hexagon::L4_return_t :
1697 case Hexagon::L4_return_f :
1698 case Hexagon::L4_return_tnew_pnt :
1699 case Hexagon::L4_return_fnew_pnt :
1700 case Hexagon::L4_return_tnew_pt :
1701 case Hexagon::L4_return_fnew_pt :
1708 // Return true when ConsMI uses a register defined by ProdMI.
1709 bool HexagonInstrInfo::isDependent(const MachineInstr *ProdMI,
1710 const MachineInstr *ConsMI) const {
1711 const MCInstrDesc &ProdMCID = ProdMI->getDesc();
1712 if (!ProdMCID.getNumDefs())
1715 auto &HRI = getRegisterInfo();
1717 SmallVector<unsigned, 4> DefsA;
1718 SmallVector<unsigned, 4> DefsB;
1719 SmallVector<unsigned, 8> UsesA;
1720 SmallVector<unsigned, 8> UsesB;
1722 parseOperands(ProdMI, DefsA, UsesA);
1723 parseOperands(ConsMI, DefsB, UsesB);
1725 for (auto &RegA : DefsA)
1726 for (auto &RegB : UsesB) {
1727 // True data dependency.
1731 if (Hexagon::DoubleRegsRegClass.contains(RegA))
1732 for (MCSubRegIterator SubRegs(RegA, &HRI); SubRegs.isValid(); ++SubRegs)
1733 if (RegB == *SubRegs)
1736 if (Hexagon::DoubleRegsRegClass.contains(RegB))
1737 for (MCSubRegIterator SubRegs(RegB, &HRI); SubRegs.isValid(); ++SubRegs)
1738 if (RegA == *SubRegs)
1746 // Returns true if the instruction is alread a .cur.
1747 bool HexagonInstrInfo::isDotCurInst(const MachineInstr* MI) const {
1748 switch (MI->getOpcode()) {
1749 case Hexagon::V6_vL32b_cur_pi:
1750 case Hexagon::V6_vL32b_cur_ai:
1751 case Hexagon::V6_vL32b_cur_pi_128B:
1752 case Hexagon::V6_vL32b_cur_ai_128B:
1759 // Returns true, if any one of the operands is a dot new
1760 // insn, whether it is predicated dot new or register dot new.
1761 bool HexagonInstrInfo::isDotNewInst(const MachineInstr* MI) const {
1762 if (isNewValueInst(MI) ||
1763 (isPredicated(MI) && isPredicatedNew(MI)))
1770 /// Symmetrical. See if these two instructions are fit for duplex pair.
1771 bool HexagonInstrInfo::isDuplexPair(const MachineInstr *MIa,
1772 const MachineInstr *MIb) const {
1773 HexagonII::SubInstructionGroup MIaG = getDuplexCandidateGroup(MIa);
1774 HexagonII::SubInstructionGroup MIbG = getDuplexCandidateGroup(MIb);
1775 return (isDuplexPairMatch(MIaG, MIbG) || isDuplexPairMatch(MIbG, MIaG));
1779 bool HexagonInstrInfo::isEarlySourceInstr(MachineInstr *MI) const {
1783 if (MI->mayLoad() || MI->mayStore() || MI->isCompare())
1787 unsigned SchedClass = MI->getDesc().getSchedClass();
1788 if (SchedClass == Hexagon::Sched::M_tc_3or4x_SLOT23)
1794 bool HexagonInstrInfo::isEndLoopN(unsigned Opcode) const {
1795 return (Opcode == Hexagon::ENDLOOP0 ||
1796 Opcode == Hexagon::ENDLOOP1);
1800 bool HexagonInstrInfo::isExpr(unsigned OpType) const {
1802 case MachineOperand::MO_MachineBasicBlock:
1803 case MachineOperand::MO_GlobalAddress:
1804 case MachineOperand::MO_ExternalSymbol:
1805 case MachineOperand::MO_JumpTableIndex:
1806 case MachineOperand::MO_ConstantPoolIndex:
1807 case MachineOperand::MO_BlockAddress:
1815 bool HexagonInstrInfo::isExtendable(const MachineInstr *MI) const {
1816 const MCInstrDesc &MID = MI->getDesc();
1817 const uint64_t F = MID.TSFlags;
1818 if ((F >> HexagonII::ExtendablePos) & HexagonII::ExtendableMask)
1821 // TODO: This is largely obsolete now. Will need to be removed
1822 // in consecutive patches.
1823 switch(MI->getOpcode()) {
1824 // TFR_FI Remains a special case.
1825 case Hexagon::TFR_FI:
1834 // This returns true in two cases:
1835 // - The OP code itself indicates that this is an extended instruction.
1836 // - One of MOs has been marked with HMOTF_ConstExtended flag.
1837 bool HexagonInstrInfo::isExtended(const MachineInstr *MI) const {
1838 // First check if this is permanently extended op code.
1839 const uint64_t F = MI->getDesc().TSFlags;
1840 if ((F >> HexagonII::ExtendedPos) & HexagonII::ExtendedMask)
1842 // Use MO operand flags to determine if one of MI's operands
1843 // has HMOTF_ConstExtended flag set.
1844 for (MachineInstr::const_mop_iterator I = MI->operands_begin(),
1845 E = MI->operands_end(); I != E; ++I) {
1846 if (I->getTargetFlags() && HexagonII::HMOTF_ConstExtended)
1853 bool HexagonInstrInfo::isFloat(MachineInstr *MI) const {
1854 unsigned Opcode = MI->getOpcode();
1855 const uint64_t F = get(Opcode).TSFlags;
1856 return (F >> HexagonII::FPPos) & HexagonII::FPMask;
1860 bool HexagonInstrInfo::isIndirectCall(const MachineInstr *MI) const {
1861 switch (MI->getOpcode()) {
1862 case Hexagon::J2_callr :
1863 case Hexagon::J2_callrf :
1864 case Hexagon::J2_callrt :
1871 bool HexagonInstrInfo::isIndirectL4Return(const MachineInstr *MI) const {
1872 switch (MI->getOpcode()) {
1873 case Hexagon::L4_return :
1874 case Hexagon::L4_return_t :
1875 case Hexagon::L4_return_f :
1876 case Hexagon::L4_return_fnew_pnt :
1877 case Hexagon::L4_return_fnew_pt :
1878 case Hexagon::L4_return_tnew_pnt :
1879 case Hexagon::L4_return_tnew_pt :
1886 bool HexagonInstrInfo::isJumpR(const MachineInstr *MI) const {
1887 switch (MI->getOpcode()) {
1888 case Hexagon::J2_jumpr :
1889 case Hexagon::J2_jumprt :
1890 case Hexagon::J2_jumprf :
1891 case Hexagon::J2_jumprtnewpt :
1892 case Hexagon::J2_jumprfnewpt :
1893 case Hexagon::J2_jumprtnew :
1894 case Hexagon::J2_jumprfnew :
1901 // Return true if a given MI can accomodate given offset.
1902 // Use abs estimate as oppose to the exact number.
1903 // TODO: This will need to be changed to use MC level
1904 // definition of instruction extendable field size.
1905 bool HexagonInstrInfo::isJumpWithinBranchRange(const MachineInstr *MI,
1906 unsigned offset) const {
1907 // This selection of jump instructions matches to that what
1908 // AnalyzeBranch can parse, plus NVJ.
1909 if (isNewValueJump(MI)) // r9:2
1910 return isInt<11>(offset);
1912 switch (MI->getOpcode()) {
1913 // Still missing Jump to address condition on register value.
1916 case Hexagon::J2_jump: // bits<24> dst; // r22:2
1917 case Hexagon::J2_call:
1918 case Hexagon::CALLv3nr:
1919 return isInt<24>(offset);
1920 case Hexagon::J2_jumpt: //bits<17> dst; // r15:2
1921 case Hexagon::J2_jumpf:
1922 case Hexagon::J2_jumptnew:
1923 case Hexagon::J2_jumptnewpt:
1924 case Hexagon::J2_jumpfnew:
1925 case Hexagon::J2_jumpfnewpt:
1926 case Hexagon::J2_callt:
1927 case Hexagon::J2_callf:
1928 return isInt<17>(offset);
1929 case Hexagon::J2_loop0i:
1930 case Hexagon::J2_loop0iext:
1931 case Hexagon::J2_loop0r:
1932 case Hexagon::J2_loop0rext:
1933 case Hexagon::J2_loop1i:
1934 case Hexagon::J2_loop1iext:
1935 case Hexagon::J2_loop1r:
1936 case Hexagon::J2_loop1rext:
1937 return isInt<9>(offset);
1938 // TODO: Add all the compound branches here. Can we do this in Relation model?
1939 case Hexagon::J4_cmpeqi_tp0_jump_nt:
1940 case Hexagon::J4_cmpeqi_tp1_jump_nt:
1941 return isInt<11>(offset);
1946 bool HexagonInstrInfo::isLateInstrFeedsEarlyInstr(MachineInstr *LRMI,
1947 MachineInstr *ESMI) const {
1951 bool isLate = isLateResultInstr(LRMI);
1952 bool isEarly = isEarlySourceInstr(ESMI);
1954 DEBUG(dbgs() << "V60" << (isLate ? "-LR " : " -- "));
1955 DEBUG(LRMI->dump());
1956 DEBUG(dbgs() << "V60" << (isEarly ? "-ES " : " -- "));
1957 DEBUG(ESMI->dump());
1959 if (isLate && isEarly) {
1960 DEBUG(dbgs() << "++Is Late Result feeding Early Source\n");
1968 bool HexagonInstrInfo::isLateResultInstr(MachineInstr *MI) const {
1972 switch (MI->getOpcode()) {
1973 case TargetOpcode::EXTRACT_SUBREG:
1974 case TargetOpcode::INSERT_SUBREG:
1975 case TargetOpcode::SUBREG_TO_REG:
1976 case TargetOpcode::REG_SEQUENCE:
1977 case TargetOpcode::IMPLICIT_DEF:
1978 case TargetOpcode::COPY:
1979 case TargetOpcode::INLINEASM:
1980 case TargetOpcode::PHI:
1986 unsigned SchedClass = MI->getDesc().getSchedClass();
1988 switch (SchedClass) {
1989 case Hexagon::Sched::ALU32_2op_tc_1_SLOT0123:
1990 case Hexagon::Sched::ALU32_3op_tc_1_SLOT0123:
1991 case Hexagon::Sched::ALU32_ADDI_tc_1_SLOT0123:
1992 case Hexagon::Sched::ALU64_tc_1_SLOT23:
1993 case Hexagon::Sched::EXTENDER_tc_1_SLOT0123:
1994 case Hexagon::Sched::S_2op_tc_1_SLOT23:
1995 case Hexagon::Sched::S_3op_tc_1_SLOT23:
1996 case Hexagon::Sched::V2LDST_tc_ld_SLOT01:
1997 case Hexagon::Sched::V2LDST_tc_st_SLOT0:
1998 case Hexagon::Sched::V2LDST_tc_st_SLOT01:
1999 case Hexagon::Sched::V4LDST_tc_ld_SLOT01:
2000 case Hexagon::Sched::V4LDST_tc_st_SLOT0:
2001 case Hexagon::Sched::V4LDST_tc_st_SLOT01:
2008 bool HexagonInstrInfo::isLateSourceInstr(const MachineInstr *MI) const {
2012 // Instructions with iclass A_CVI_VX and attribute A_CVI_LATE uses a multiply
2013 // resource, but all operands can be received late like an ALU instruction.
2014 return MI->getDesc().getSchedClass() == Hexagon::Sched::CVI_VX_LATE;
2018 bool HexagonInstrInfo::isLoopN(unsigned Opcode) const {
2019 return (Opcode == Hexagon::J2_loop0i ||
2020 Opcode == Hexagon::J2_loop0r ||
2021 Opcode == Hexagon::J2_loop0iext ||
2022 Opcode == Hexagon::J2_loop0rext ||
2023 Opcode == Hexagon::J2_loop1i ||
2024 Opcode == Hexagon::J2_loop1r ||
2025 Opcode == Hexagon::J2_loop1iext ||
2026 Opcode == Hexagon::J2_loop1rext);
2030 bool HexagonInstrInfo::isMemOp(const MachineInstr *MI) const {
2031 switch (MI->getOpcode()) {
2032 default: return false;
2033 case Hexagon::L4_iadd_memopw_io :
2034 case Hexagon::L4_isub_memopw_io :
2035 case Hexagon::L4_add_memopw_io :
2036 case Hexagon::L4_sub_memopw_io :
2037 case Hexagon::L4_and_memopw_io :
2038 case Hexagon::L4_or_memopw_io :
2039 case Hexagon::L4_iadd_memoph_io :
2040 case Hexagon::L4_isub_memoph_io :
2041 case Hexagon::L4_add_memoph_io :
2042 case Hexagon::L4_sub_memoph_io :
2043 case Hexagon::L4_and_memoph_io :
2044 case Hexagon::L4_or_memoph_io :
2045 case Hexagon::L4_iadd_memopb_io :
2046 case Hexagon::L4_isub_memopb_io :
2047 case Hexagon::L4_add_memopb_io :
2048 case Hexagon::L4_sub_memopb_io :
2049 case Hexagon::L4_and_memopb_io :
2050 case Hexagon::L4_or_memopb_io :
2051 case Hexagon::L4_ior_memopb_io:
2052 case Hexagon::L4_ior_memoph_io:
2053 case Hexagon::L4_ior_memopw_io:
2054 case Hexagon::L4_iand_memopb_io:
2055 case Hexagon::L4_iand_memoph_io:
2056 case Hexagon::L4_iand_memopw_io:
2063 bool HexagonInstrInfo::isNewValue(const MachineInstr* MI) const {
2064 const uint64_t F = MI->getDesc().TSFlags;
2065 return (F >> HexagonII::NewValuePos) & HexagonII::NewValueMask;
2069 bool HexagonInstrInfo::isNewValue(unsigned Opcode) const {
2070 const uint64_t F = get(Opcode).TSFlags;
2071 return (F >> HexagonII::NewValuePos) & HexagonII::NewValueMask;
2075 bool HexagonInstrInfo::isNewValueInst(const MachineInstr *MI) const {
2076 return isNewValueJump(MI) || isNewValueStore(MI);
2080 bool HexagonInstrInfo::isNewValueJump(const MachineInstr *MI) const {
2081 return isNewValue(MI) && MI->isBranch();
2085 bool HexagonInstrInfo::isNewValueJump(unsigned Opcode) const {
2086 return isNewValue(Opcode) && get(Opcode).isBranch() && isPredicated(Opcode);
2090 bool HexagonInstrInfo::isNewValueStore(const MachineInstr *MI) const {
2091 const uint64_t F = MI->getDesc().TSFlags;
2092 return (F >> HexagonII::NVStorePos) & HexagonII::NVStoreMask;
2096 bool HexagonInstrInfo::isNewValueStore(unsigned Opcode) const {
2097 const uint64_t F = get(Opcode).TSFlags;
2098 return (F >> HexagonII::NVStorePos) & HexagonII::NVStoreMask;
2102 // Returns true if a particular operand is extendable for an instruction.
2103 bool HexagonInstrInfo::isOperandExtended(const MachineInstr *MI,
2104 unsigned OperandNum) const {
2105 const uint64_t F = MI->getDesc().TSFlags;
2106 return ((F >> HexagonII::ExtendableOpPos) & HexagonII::ExtendableOpMask)
2111 bool HexagonInstrInfo::isPostIncrement(const MachineInstr* MI) const {
2112 return getAddrMode(MI) == HexagonII::PostInc;
2116 bool HexagonInstrInfo::isPredicatedNew(const MachineInstr *MI) const {
2117 const uint64_t F = MI->getDesc().TSFlags;
2118 assert(isPredicated(MI));
2119 return (F >> HexagonII::PredicatedNewPos) & HexagonII::PredicatedNewMask;
2123 bool HexagonInstrInfo::isPredicatedNew(unsigned Opcode) const {
2124 const uint64_t F = get(Opcode).TSFlags;
2125 assert(isPredicated(Opcode));
2126 return (F >> HexagonII::PredicatedNewPos) & HexagonII::PredicatedNewMask;
2130 bool HexagonInstrInfo::isPredicatedTrue(const MachineInstr *MI) const {
2131 const uint64_t F = MI->getDesc().TSFlags;
2132 return !((F >> HexagonII::PredicatedFalsePos) &
2133 HexagonII::PredicatedFalseMask);
2137 bool HexagonInstrInfo::isPredicatedTrue(unsigned Opcode) const {
2138 const uint64_t F = get(Opcode).TSFlags;
2139 // Make sure that the instruction is predicated.
2140 assert((F>> HexagonII::PredicatedPos) & HexagonII::PredicatedMask);
2141 return !((F >> HexagonII::PredicatedFalsePos) &
2142 HexagonII::PredicatedFalseMask);
2146 bool HexagonInstrInfo::isPredicated(unsigned Opcode) const {
2147 const uint64_t F = get(Opcode).TSFlags;
2148 return (F >> HexagonII::PredicatedPos) & HexagonII::PredicatedMask;
2152 bool HexagonInstrInfo::isPredicateLate(unsigned Opcode) const {
2153 const uint64_t F = get(Opcode).TSFlags;
2154 return ~(F >> HexagonII::PredicateLatePos) & HexagonII::PredicateLateMask;
2158 bool HexagonInstrInfo::isPredictedTaken(unsigned Opcode) const {
2159 const uint64_t F = get(Opcode).TSFlags;
2160 assert(get(Opcode).isBranch() &&
2161 (isPredicatedNew(Opcode) || isNewValue(Opcode)));
2162 return (F >> HexagonII::TakenPos) & HexagonII::TakenMask;
2166 bool HexagonInstrInfo::isSaveCalleeSavedRegsCall(const MachineInstr *MI) const {
2167 return MI->getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4 ||
2168 MI->getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_EXT;
2172 bool HexagonInstrInfo::isSolo(const MachineInstr* MI) const {
2173 const uint64_t F = MI->getDesc().TSFlags;
2174 return (F >> HexagonII::SoloPos) & HexagonII::SoloMask;
2178 bool HexagonInstrInfo::isSpillPredRegOp(const MachineInstr *MI) const {
2179 switch (MI->getOpcode()) {
2180 case Hexagon::STriw_pred :
2181 case Hexagon::LDriw_pred :
2189 // Returns true when SU has a timing class TC1.
2190 bool HexagonInstrInfo::isTC1(const MachineInstr *MI) const {
2191 unsigned SchedClass = MI->getDesc().getSchedClass();
2192 switch (SchedClass) {
2193 case Hexagon::Sched::ALU32_2op_tc_1_SLOT0123:
2194 case Hexagon::Sched::ALU32_3op_tc_1_SLOT0123:
2195 case Hexagon::Sched::ALU32_ADDI_tc_1_SLOT0123:
2196 case Hexagon::Sched::ALU64_tc_1_SLOT23:
2197 case Hexagon::Sched::EXTENDER_tc_1_SLOT0123:
2198 //case Hexagon::Sched::M_tc_1_SLOT23:
2199 case Hexagon::Sched::S_2op_tc_1_SLOT23:
2200 case Hexagon::Sched::S_3op_tc_1_SLOT23:
2209 bool HexagonInstrInfo::isTC2(const MachineInstr *MI) const {
2210 unsigned SchedClass = MI->getDesc().getSchedClass();
2211 switch (SchedClass) {
2212 case Hexagon::Sched::ALU32_3op_tc_2_SLOT0123:
2213 case Hexagon::Sched::ALU64_tc_2_SLOT23:
2214 case Hexagon::Sched::CR_tc_2_SLOT3:
2215 case Hexagon::Sched::M_tc_2_SLOT23:
2216 case Hexagon::Sched::S_2op_tc_2_SLOT23:
2217 case Hexagon::Sched::S_3op_tc_2_SLOT23:
2226 bool HexagonInstrInfo::isTC2Early(const MachineInstr *MI) const {
2227 unsigned SchedClass = MI->getDesc().getSchedClass();
2228 switch (SchedClass) {
2229 case Hexagon::Sched::ALU32_2op_tc_2early_SLOT0123:
2230 case Hexagon::Sched::ALU32_3op_tc_2early_SLOT0123:
2231 case Hexagon::Sched::ALU64_tc_2early_SLOT23:
2232 case Hexagon::Sched::CR_tc_2early_SLOT23:
2233 case Hexagon::Sched::CR_tc_2early_SLOT3:
2234 case Hexagon::Sched::J_tc_2early_SLOT0123:
2235 case Hexagon::Sched::J_tc_2early_SLOT2:
2236 case Hexagon::Sched::J_tc_2early_SLOT23:
2237 case Hexagon::Sched::S_2op_tc_2early_SLOT23:
2238 case Hexagon::Sched::S_3op_tc_2early_SLOT23:
2247 bool HexagonInstrInfo::isTC4x(const MachineInstr *MI) const {
2251 unsigned SchedClass = MI->getDesc().getSchedClass();
2252 return SchedClass == Hexagon::Sched::M_tc_3or4x_SLOT23;
2256 bool HexagonInstrInfo::isV60VectorInstruction(const MachineInstr *MI) const {
2260 const uint64_t V = getType(MI);
2261 return HexagonII::TypeCVI_FIRST <= V && V <= HexagonII::TypeCVI_LAST;
2265 // Check if the Offset is a valid auto-inc imm by Load/Store Type.
2267 bool HexagonInstrInfo::isValidAutoIncImm(const EVT VT, const int Offset) const {
2268 if (VT == MVT::v16i32 || VT == MVT::v8i64 ||
2269 VT == MVT::v32i16 || VT == MVT::v64i8) {
2270 return (Offset >= Hexagon_MEMV_AUTOINC_MIN &&
2271 Offset <= Hexagon_MEMV_AUTOINC_MAX &&
2272 (Offset & 0x3f) == 0);
2275 if (VT == MVT::v32i32 || VT == MVT::v16i64 ||
2276 VT == MVT::v64i16 || VT == MVT::v128i8) {
2277 return (Offset >= Hexagon_MEMV_AUTOINC_MIN_128B &&
2278 Offset <= Hexagon_MEMV_AUTOINC_MAX_128B &&
2279 (Offset & 0x7f) == 0);
2281 if (VT == MVT::i64) {
2282 return (Offset >= Hexagon_MEMD_AUTOINC_MIN &&
2283 Offset <= Hexagon_MEMD_AUTOINC_MAX &&
2284 (Offset & 0x7) == 0);
2286 if (VT == MVT::i32) {
2287 return (Offset >= Hexagon_MEMW_AUTOINC_MIN &&
2288 Offset <= Hexagon_MEMW_AUTOINC_MAX &&
2289 (Offset & 0x3) == 0);
2291 if (VT == MVT::i16) {
2292 return (Offset >= Hexagon_MEMH_AUTOINC_MIN &&
2293 Offset <= Hexagon_MEMH_AUTOINC_MAX &&
2294 (Offset & 0x1) == 0);
2296 if (VT == MVT::i8) {
2297 return (Offset >= Hexagon_MEMB_AUTOINC_MIN &&
2298 Offset <= Hexagon_MEMB_AUTOINC_MAX);
2300 llvm_unreachable("Not an auto-inc opc!");
2304 bool HexagonInstrInfo::isValidOffset(unsigned Opcode, int Offset,
2305 bool Extend) const {
2306 // This function is to check whether the "Offset" is in the correct range of
2307 // the given "Opcode". If "Offset" is not in the correct range, "A2_addi" is
2308 // inserted to calculate the final address. Due to this reason, the function
2309 // assumes that the "Offset" has correct alignment.
2310 // We used to assert if the offset was not properly aligned, however,
2311 // there are cases where a misaligned pointer recast can cause this
2312 // problem, and we need to allow for it. The front end warns of such
2313 // misaligns with respect to load size.
2316 case Hexagon::STriq_pred_V6:
2317 case Hexagon::STriq_pred_vec_V6:
2318 case Hexagon::STriv_pseudo_V6:
2319 case Hexagon::STrivv_pseudo_V6:
2320 case Hexagon::LDriq_pred_V6:
2321 case Hexagon::LDriq_pred_vec_V6:
2322 case Hexagon::LDriv_pseudo_V6:
2323 case Hexagon::LDrivv_pseudo_V6:
2324 case Hexagon::LDrivv_indexed:
2325 case Hexagon::STrivv_indexed:
2326 case Hexagon::V6_vL32b_ai:
2327 case Hexagon::V6_vS32b_ai:
2328 case Hexagon::V6_vL32Ub_ai:
2329 case Hexagon::V6_vS32Ub_ai:
2330 return (Offset >= Hexagon_MEMV_OFFSET_MIN) &&
2331 (Offset <= Hexagon_MEMV_OFFSET_MAX);
2333 case Hexagon::STriq_pred_V6_128B:
2334 case Hexagon::STriq_pred_vec_V6_128B:
2335 case Hexagon::STriv_pseudo_V6_128B:
2336 case Hexagon::STrivv_pseudo_V6_128B:
2337 case Hexagon::LDriq_pred_V6_128B:
2338 case Hexagon::LDriq_pred_vec_V6_128B:
2339 case Hexagon::LDriv_pseudo_V6_128B:
2340 case Hexagon::LDrivv_pseudo_V6_128B:
2341 case Hexagon::LDrivv_indexed_128B:
2342 case Hexagon::STrivv_indexed_128B:
2343 case Hexagon::V6_vL32b_ai_128B:
2344 case Hexagon::V6_vS32b_ai_128B:
2345 case Hexagon::V6_vL32Ub_ai_128B:
2346 case Hexagon::V6_vS32Ub_ai_128B:
2347 return (Offset >= Hexagon_MEMV_OFFSET_MIN_128B) &&
2348 (Offset <= Hexagon_MEMV_OFFSET_MAX_128B);
2350 case Hexagon::J2_loop0i:
2351 case Hexagon::J2_loop1i:
2352 return isUInt<10>(Offset);
2359 case Hexagon::L2_loadri_io:
2360 case Hexagon::S2_storeri_io:
2361 return (Offset >= Hexagon_MEMW_OFFSET_MIN) &&
2362 (Offset <= Hexagon_MEMW_OFFSET_MAX);
2364 case Hexagon::L2_loadrd_io:
2365 case Hexagon::S2_storerd_io:
2366 return (Offset >= Hexagon_MEMD_OFFSET_MIN) &&
2367 (Offset <= Hexagon_MEMD_OFFSET_MAX);
2369 case Hexagon::L2_loadrh_io:
2370 case Hexagon::L2_loadruh_io:
2371 case Hexagon::S2_storerh_io:
2372 return (Offset >= Hexagon_MEMH_OFFSET_MIN) &&
2373 (Offset <= Hexagon_MEMH_OFFSET_MAX);
2375 case Hexagon::L2_loadrb_io:
2376 case Hexagon::L2_loadrub_io:
2377 case Hexagon::S2_storerb_io:
2378 return (Offset >= Hexagon_MEMB_OFFSET_MIN) &&
2379 (Offset <= Hexagon_MEMB_OFFSET_MAX);
2381 case Hexagon::A2_addi:
2382 return (Offset >= Hexagon_ADDI_OFFSET_MIN) &&
2383 (Offset <= Hexagon_ADDI_OFFSET_MAX);
2385 case Hexagon::L4_iadd_memopw_io :
2386 case Hexagon::L4_isub_memopw_io :
2387 case Hexagon::L4_add_memopw_io :
2388 case Hexagon::L4_sub_memopw_io :
2389 case Hexagon::L4_and_memopw_io :
2390 case Hexagon::L4_or_memopw_io :
2391 return (0 <= Offset && Offset <= 255);
2393 case Hexagon::L4_iadd_memoph_io :
2394 case Hexagon::L4_isub_memoph_io :
2395 case Hexagon::L4_add_memoph_io :
2396 case Hexagon::L4_sub_memoph_io :
2397 case Hexagon::L4_and_memoph_io :
2398 case Hexagon::L4_or_memoph_io :
2399 return (0 <= Offset && Offset <= 127);
2401 case Hexagon::L4_iadd_memopb_io :
2402 case Hexagon::L4_isub_memopb_io :
2403 case Hexagon::L4_add_memopb_io :
2404 case Hexagon::L4_sub_memopb_io :
2405 case Hexagon::L4_and_memopb_io :
2406 case Hexagon::L4_or_memopb_io :
2407 return (0 <= Offset && Offset <= 63);
2409 // LDri_pred and STriw_pred are pseudo operations, so it has to take offset of
2410 // any size. Later pass knows how to handle it.
2411 case Hexagon::STriw_pred:
2412 case Hexagon::LDriw_pred:
2415 case Hexagon::TFR_FI:
2416 case Hexagon::TFR_FIA:
2417 case Hexagon::INLINEASM:
2420 case Hexagon::L2_ploadrbt_io:
2421 case Hexagon::L2_ploadrbf_io:
2422 case Hexagon::L2_ploadrubt_io:
2423 case Hexagon::L2_ploadrubf_io:
2424 case Hexagon::S2_pstorerbt_io:
2425 case Hexagon::S2_pstorerbf_io:
2426 case Hexagon::S4_storeirb_io:
2427 case Hexagon::S4_storeirbt_io:
2428 case Hexagon::S4_storeirbf_io:
2429 return isUInt<6>(Offset);
2431 case Hexagon::L2_ploadrht_io:
2432 case Hexagon::L2_ploadrhf_io:
2433 case Hexagon::L2_ploadruht_io:
2434 case Hexagon::L2_ploadruhf_io:
2435 case Hexagon::S2_pstorerht_io:
2436 case Hexagon::S2_pstorerhf_io:
2437 case Hexagon::S4_storeirh_io:
2438 case Hexagon::S4_storeirht_io:
2439 case Hexagon::S4_storeirhf_io:
2440 return isShiftedUInt<6,1>(Offset);
2442 case Hexagon::L2_ploadrit_io:
2443 case Hexagon::L2_ploadrif_io:
2444 case Hexagon::S2_pstorerit_io:
2445 case Hexagon::S2_pstorerif_io:
2446 case Hexagon::S4_storeiri_io:
2447 case Hexagon::S4_storeirit_io:
2448 case Hexagon::S4_storeirif_io:
2449 return isShiftedUInt<6,2>(Offset);
2451 case Hexagon::L2_ploadrdt_io:
2452 case Hexagon::L2_ploadrdf_io:
2453 case Hexagon::S2_pstorerdt_io:
2454 case Hexagon::S2_pstorerdf_io:
2455 return isShiftedUInt<6,3>(Offset);
2458 llvm_unreachable("No offset range is defined for this opcode. "
2459 "Please define it in the above switch statement!");
2463 bool HexagonInstrInfo::isVecAcc(const MachineInstr *MI) const {
2464 return MI && isV60VectorInstruction(MI) && isAccumulator(MI);
2468 bool HexagonInstrInfo::isVecALU(const MachineInstr *MI) const {
2471 const uint64_t F = get(MI->getOpcode()).TSFlags;
2472 const uint64_t V = ((F >> HexagonII::TypePos) & HexagonII::TypeMask);
2474 V == HexagonII::TypeCVI_VA ||
2475 V == HexagonII::TypeCVI_VA_DV;
2479 bool HexagonInstrInfo::isVecUsableNextPacket(const MachineInstr *ProdMI,
2480 const MachineInstr *ConsMI) const {
2481 if (EnableACCForwarding && isVecAcc(ProdMI) && isVecAcc(ConsMI))
2484 if (EnableALUForwarding && (isVecALU(ConsMI) || isLateSourceInstr(ConsMI)))
2487 if (mayBeNewStore(ConsMI))
2494 bool HexagonInstrInfo::hasEHLabel(const MachineBasicBlock *B) const {
2502 // Returns true if an instruction can be converted into a non-extended
2503 // equivalent instruction.
2504 bool HexagonInstrInfo::hasNonExtEquivalent(const MachineInstr *MI) const {
2506 // Check if the instruction has a register form that uses register in place
2507 // of the extended operand, if so return that as the non-extended form.
2508 if (Hexagon::getRegForm(MI->getOpcode()) >= 0)
2511 if (MI->getDesc().mayLoad() || MI->getDesc().mayStore()) {
2512 // Check addressing mode and retrieve non-ext equivalent instruction.
2514 switch (getAddrMode(MI)) {
2515 case HexagonII::Absolute :
2516 // Load/store with absolute addressing mode can be converted into
2517 // base+offset mode.
2518 NonExtOpcode = Hexagon::getBaseWithImmOffset(MI->getOpcode());
2520 case HexagonII::BaseImmOffset :
2521 // Load/store with base+offset addressing mode can be converted into
2522 // base+register offset addressing mode. However left shift operand should
2524 NonExtOpcode = Hexagon::getBaseWithRegOffset(MI->getOpcode());
2526 case HexagonII::BaseLongOffset:
2527 NonExtOpcode = Hexagon::getRegShlForm(MI->getOpcode());
2532 if (NonExtOpcode < 0)
2540 bool HexagonInstrInfo::hasPseudoInstrPair(MachineInstr *MI) const {
2541 return Hexagon::getRealHWInstr(MI->getOpcode(),
2542 Hexagon::InstrType_Pseudo) >= 0;
2546 bool HexagonInstrInfo::hasUncondBranch(const MachineBasicBlock *B)
2548 MachineBasicBlock::const_iterator I = B->getFirstTerminator(), E = B->end();
2558 // Returns true, if a LD insn can be promoted to a cur load.
2559 bool HexagonInstrInfo::mayBeCurLoad(const MachineInstr *MI) const {
2560 auto &HST = MI->getParent()->getParent()->getSubtarget<HexagonSubtarget>();
2561 const uint64_t F = MI->getDesc().TSFlags;
2562 return ((F >> HexagonII::mayCVLoadPos) & HexagonII::mayCVLoadMask) &&
2567 // Returns true, if a ST insn can be promoted to a new-value store.
2568 bool HexagonInstrInfo::mayBeNewStore(const MachineInstr *MI) const {
2569 const uint64_t F = MI->getDesc().TSFlags;
2570 return (F >> HexagonII::mayNVStorePos) & HexagonII::mayNVStoreMask;
2574 bool HexagonInstrInfo::producesStall(const MachineInstr *ProdMI,
2575 const MachineInstr *ConsMI) const {
2576 // There is no stall when ProdMI is not a V60 vector.
2577 if (!isV60VectorInstruction(ProdMI))
2580 // There is no stall when ProdMI and ConsMI are not dependent.
2581 if (!isDependent(ProdMI, ConsMI))
2584 // When Forward Scheduling is enabled, there is no stall if ProdMI and ConsMI
2585 // are scheduled in consecutive packets.
2586 if (isVecUsableNextPacket(ProdMI, ConsMI))
2593 bool HexagonInstrInfo::producesStall(const MachineInstr *MI,
2594 MachineBasicBlock::const_instr_iterator BII) const {
2595 // There is no stall when I is not a V60 vector.
2596 if (!isV60VectorInstruction(MI))
2599 MachineBasicBlock::const_instr_iterator MII = BII;
2600 MachineBasicBlock::const_instr_iterator MIE = MII->getParent()->instr_end();
2602 if (!(*MII).isBundle()) {
2603 const MachineInstr *J = &*MII;
2604 if (!isV60VectorInstruction(J))
2606 else if (isVecUsableNextPacket(J, MI))
2611 for (++MII; MII != MIE && MII->isInsideBundle(); ++MII) {
2612 const MachineInstr *J = &*MII;
2613 if (producesStall(J, MI))
2620 bool HexagonInstrInfo::predCanBeUsedAsDotNew(MachineInstr *MI,
2621 unsigned PredReg) const {
2622 for (unsigned opNum = 0; opNum < MI->getNumOperands(); opNum++) {
2623 MachineOperand &MO = MI->getOperand(opNum);
2624 if (MO.isReg() && MO.isDef() && MO.isImplicit() && (MO.getReg() == PredReg))
2625 return false; // Predicate register must be explicitly defined.
2628 // Hexagon Programmer's Reference says that decbin, memw_locked, and
2629 // memd_locked cannot be used as .new as well,
2630 // but we don't seem to have these instructions defined.
2631 return MI->getOpcode() != Hexagon::A4_tlbmatch;
2635 bool HexagonInstrInfo::PredOpcodeHasJMP_c(unsigned Opcode) const {
2636 return (Opcode == Hexagon::J2_jumpt) ||
2637 (Opcode == Hexagon::J2_jumpf) ||
2638 (Opcode == Hexagon::J2_jumptnew) ||
2639 (Opcode == Hexagon::J2_jumpfnew) ||
2640 (Opcode == Hexagon::J2_jumptnewpt) ||
2641 (Opcode == Hexagon::J2_jumpfnewpt);
2645 bool HexagonInstrInfo::predOpcodeHasNot(ArrayRef<MachineOperand> Cond) const {
2646 if (Cond.empty() || !isPredicated(Cond[0].getImm()))
2648 return !isPredicatedTrue(Cond[0].getImm());
2652 unsigned HexagonInstrInfo::getAddrMode(const MachineInstr* MI) const {
2653 const uint64_t F = MI->getDesc().TSFlags;
2654 return (F >> HexagonII::AddrModePos) & HexagonII::AddrModeMask;
2658 // Returns the base register in a memory access (load/store). The offset is
2659 // returned in Offset and the access size is returned in AccessSize.
2660 unsigned HexagonInstrInfo::getBaseAndOffset(const MachineInstr *MI,
2661 int &Offset, unsigned &AccessSize) const {
2662 // Return if it is not a base+offset type instruction or a MemOp.
2663 if (getAddrMode(MI) != HexagonII::BaseImmOffset &&
2664 getAddrMode(MI) != HexagonII::BaseLongOffset &&
2665 !isMemOp(MI) && !isPostIncrement(MI))
2668 // Since it is a memory access instruction, getMemAccessSize() should never
2670 assert (getMemAccessSize(MI) &&
2671 "BaseImmOffset or BaseLongOffset or MemOp without accessSize");
2673 // Return Values of getMemAccessSize() are
2674 // 0 - Checked in the assert above.
2675 // 1, 2, 3, 4 & 7, 8 - The statement below is correct for all these.
2676 // MemAccessSize is represented as 1+log2(N) where N is size in bits.
2677 AccessSize = (1U << (getMemAccessSize(MI) - 1));
2679 unsigned basePos = 0, offsetPos = 0;
2680 if (!getBaseAndOffsetPosition(MI, basePos, offsetPos))
2683 // Post increment updates its EA after the mem access,
2684 // so we need to treat its offset as zero.
2685 if (isPostIncrement(MI))
2688 Offset = MI->getOperand(offsetPos).getImm();
2691 return MI->getOperand(basePos).getReg();
2695 /// Return the position of the base and offset operands for this instruction.
2696 bool HexagonInstrInfo::getBaseAndOffsetPosition(const MachineInstr *MI,
2697 unsigned &BasePos, unsigned &OffsetPos) const {
2698 // Deal with memops first.
2700 assert (MI->getOperand(0).isReg() && MI->getOperand(1).isImm() &&
2704 } else if (MI->mayStore()) {
2707 } else if (MI->mayLoad()) {
2713 if (isPredicated(MI)) {
2717 if (isPostIncrement(MI)) {
2722 if (!MI->getOperand(BasePos).isReg() || !MI->getOperand(OffsetPos).isImm())
2729 // Inserts branching instructions in reverse order of their occurence.
2730 // e.g. jump_t t1 (i1)
2732 // Jumpers = {i2, i1}
2733 SmallVector<MachineInstr*, 2> HexagonInstrInfo::getBranchingInstrs(
2734 MachineBasicBlock& MBB) const {
2735 SmallVector<MachineInstr*, 2> Jumpers;
2736 // If the block has no terminators, it just falls into the block after it.
2737 MachineBasicBlock::instr_iterator I = MBB.instr_end();
2738 if (I == MBB.instr_begin())
2741 // A basic block may looks like this:
2751 // It has two succs but does not have a terminator
2752 // Don't know how to handle it.
2757 } while (I != MBB.instr_begin());
2759 I = MBB.instr_end();
2762 while (I->isDebugValue()) {
2763 if (I == MBB.instr_begin())
2767 if (!isUnpredicatedTerminator(&*I))
2770 // Get the last instruction in the block.
2771 MachineInstr *LastInst = &*I;
2772 Jumpers.push_back(LastInst);
2773 MachineInstr *SecondLastInst = nullptr;
2774 // Find one more terminator if present.
2776 if (&*I != LastInst && !I->isBundle() && isUnpredicatedTerminator(&*I)) {
2777 if (!SecondLastInst) {
2778 SecondLastInst = &*I;
2779 Jumpers.push_back(SecondLastInst);
2780 } else // This is a third branch.
2783 if (I == MBB.instr_begin())
2791 // Returns Operand Index for the constant extended instruction.
2792 unsigned HexagonInstrInfo::getCExtOpNum(const MachineInstr *MI) const {
2793 const uint64_t F = MI->getDesc().TSFlags;
2794 return (F >> HexagonII::ExtendableOpPos) & HexagonII::ExtendableOpMask;
2797 // See if instruction could potentially be a duplex candidate.
2798 // If so, return its group. Zero otherwise.
2799 HexagonII::CompoundGroup HexagonInstrInfo::getCompoundCandidateGroup(
2800 const MachineInstr *MI) const {
2801 unsigned DstReg, SrcReg, Src1Reg, Src2Reg;
2803 switch (MI->getOpcode()) {
2805 return HexagonII::HCG_None;
2808 // "p0=cmp.eq(Rs16,Rt16); if (p0.new) jump:nt #r9:2"
2809 // "Rd16=#U6 ; jump #r9:2"
2810 // "Rd16=Rs16 ; jump #r9:2"
2812 case Hexagon::C2_cmpeq:
2813 case Hexagon::C2_cmpgt:
2814 case Hexagon::C2_cmpgtu:
2815 DstReg = MI->getOperand(0).getReg();
2816 Src1Reg = MI->getOperand(1).getReg();
2817 Src2Reg = MI->getOperand(2).getReg();
2818 if (Hexagon::PredRegsRegClass.contains(DstReg) &&
2819 (Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
2820 isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg))
2821 return HexagonII::HCG_A;
2823 case Hexagon::C2_cmpeqi:
2824 case Hexagon::C2_cmpgti:
2825 case Hexagon::C2_cmpgtui:
2826 // P0 = cmp.eq(Rs,#u2)
2827 DstReg = MI->getOperand(0).getReg();
2828 SrcReg = MI->getOperand(1).getReg();
2829 if (Hexagon::PredRegsRegClass.contains(DstReg) &&
2830 (Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
2831 isIntRegForSubInst(SrcReg) && MI->getOperand(2).isImm() &&
2832 ((isUInt<5>(MI->getOperand(2).getImm())) ||
2833 (MI->getOperand(2).getImm() == -1)))
2834 return HexagonII::HCG_A;
2836 case Hexagon::A2_tfr:
2838 DstReg = MI->getOperand(0).getReg();
2839 SrcReg = MI->getOperand(1).getReg();
2840 if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg))
2841 return HexagonII::HCG_A;
2843 case Hexagon::A2_tfrsi:
2845 // Do not test for #u6 size since the const is getting extended
2846 // regardless and compound could be formed.
2847 DstReg = MI->getOperand(0).getReg();
2848 if (isIntRegForSubInst(DstReg))
2849 return HexagonII::HCG_A;
2851 case Hexagon::S2_tstbit_i:
2852 DstReg = MI->getOperand(0).getReg();
2853 Src1Reg = MI->getOperand(1).getReg();
2854 if (Hexagon::PredRegsRegClass.contains(DstReg) &&
2855 (Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
2856 MI->getOperand(2).isImm() &&
2857 isIntRegForSubInst(Src1Reg) && (MI->getOperand(2).getImm() == 0))
2858 return HexagonII::HCG_A;
2860 // The fact that .new form is used pretty much guarantees
2861 // that predicate register will match. Nevertheless,
2862 // there could be some false positives without additional
2864 case Hexagon::J2_jumptnew:
2865 case Hexagon::J2_jumpfnew:
2866 case Hexagon::J2_jumptnewpt:
2867 case Hexagon::J2_jumpfnewpt:
2868 Src1Reg = MI->getOperand(0).getReg();
2869 if (Hexagon::PredRegsRegClass.contains(Src1Reg) &&
2870 (Hexagon::P0 == Src1Reg || Hexagon::P1 == Src1Reg))
2871 return HexagonII::HCG_B;
2873 // Transfer and jump:
2874 // Rd=#U6 ; jump #r9:2
2875 // Rd=Rs ; jump #r9:2
2876 // Do not test for jump range here.
2877 case Hexagon::J2_jump:
2878 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4:
2879 return HexagonII::HCG_C;
2883 return HexagonII::HCG_None;
2887 // Returns -1 when there is no opcode found.
2888 unsigned HexagonInstrInfo::getCompoundOpcode(const MachineInstr *GA,
2889 const MachineInstr *GB) const {
2890 assert(getCompoundCandidateGroup(GA) == HexagonII::HCG_A);
2891 assert(getCompoundCandidateGroup(GB) == HexagonII::HCG_B);
2892 if ((GA->getOpcode() != Hexagon::C2_cmpeqi) ||
2893 (GB->getOpcode() != Hexagon::J2_jumptnew))
2895 unsigned DestReg = GA->getOperand(0).getReg();
2896 if (!GB->readsRegister(DestReg))
2898 if (DestReg == Hexagon::P0)
2899 return Hexagon::J4_cmpeqi_tp0_jump_nt;
2900 if (DestReg == Hexagon::P1)
2901 return Hexagon::J4_cmpeqi_tp1_jump_nt;
2906 int HexagonInstrInfo::getCondOpcode(int Opc, bool invertPredicate) const {
2907 enum Hexagon::PredSense inPredSense;
2908 inPredSense = invertPredicate ? Hexagon::PredSense_false :
2909 Hexagon::PredSense_true;
2910 int CondOpcode = Hexagon::getPredOpcode(Opc, inPredSense);
2911 if (CondOpcode >= 0) // Valid Conditional opcode/instruction
2914 // This switch case will be removed once all the instructions have been
2915 // modified to use relation maps.
2917 case Hexagon::TFRI_f:
2918 return !invertPredicate ? Hexagon::TFRI_cPt_f :
2919 Hexagon::TFRI_cNotPt_f;
2922 llvm_unreachable("Unexpected predicable instruction");
2926 // Return the cur value instruction for a given store.
2927 int HexagonInstrInfo::getDotCurOp(const MachineInstr* MI) const {
2928 switch (MI->getOpcode()) {
2929 default: llvm_unreachable("Unknown .cur type");
2930 case Hexagon::V6_vL32b_pi:
2931 return Hexagon::V6_vL32b_cur_pi;
2932 case Hexagon::V6_vL32b_ai:
2933 return Hexagon::V6_vL32b_cur_ai;
2935 case Hexagon::V6_vL32b_pi_128B:
2936 return Hexagon::V6_vL32b_cur_pi_128B;
2937 case Hexagon::V6_vL32b_ai_128B:
2938 return Hexagon::V6_vL32b_cur_ai_128B;
2945 // The diagram below shows the steps involved in the conversion of a predicated
2946 // store instruction to its .new predicated new-value form.
2948 // p.new NV store [ if(p0.new)memw(R0+#0)=R2.new ]
2950 // / \ (not OK. it will cause new-value store to be
2951 // / X conditional on p0.new while R2 producer is
2954 // p.new store p.old NV store
2955 // [if(p0.new)memw(R0+#0)=R2] [if(p0)memw(R0+#0)=R2.new]
2961 // [if (p0)memw(R0+#0)=R2]
2964 // The following set of instructions further explains the scenario where
2965 // conditional new-value store becomes invalid when promoted to .new predicate
2968 // { 1) if (p0) r0 = add(r1, r2)
2969 // 2) p0 = cmp.eq(r3, #0) }
2971 // 3) if (p0) memb(r1+#0) = r0 --> this instruction can't be grouped with
2972 // the first two instructions because in instr 1, r0 is conditional on old value
2973 // of p0 but its use in instr 3 is conditional on p0 modified by instr 2 which
2974 // is not valid for new-value stores.
2975 // Predicated new value stores (i.e. if (p0) memw(..)=r0.new) are excluded
2976 // from the "Conditional Store" list. Because a predicated new value store
2977 // would NOT be promoted to a double dot new store. See diagram below:
2978 // This function returns yes for those stores that are predicated but not
2979 // yet promoted to predicate dot new instructions.
2981 // +---------------------+
2982 // /-----| if (p0) memw(..)=r0 |---------\~
2983 // || +---------------------+ ||
2984 // promote || /\ /\ || promote
2986 // \||/ demote || \||/
2988 // +-------------------------+ || +-------------------------+
2989 // | if (p0.new) memw(..)=r0 | || | if (p0) memw(..)=r0.new |
2990 // +-------------------------+ || +-------------------------+
2993 // promote || \/ NOT possible
2997 // +-----------------------------+
2998 // | if (p0.new) memw(..)=r0.new |
2999 // +-----------------------------+
3000 // Double Dot New Store
3002 // Returns the most basic instruction for the .new predicated instructions and
3003 // new-value stores.
3004 // For example, all of the following instructions will be converted back to the
3005 // same instruction:
3006 // 1) if (p0.new) memw(R0+#0) = R1.new --->
3007 // 2) if (p0) memw(R0+#0)= R1.new -------> if (p0) memw(R0+#0) = R1
3008 // 3) if (p0.new) memw(R0+#0) = R1 --->
3010 // To understand the translation of instruction 1 to its original form, consider
3011 // a packet with 3 instructions.
3012 // { p0 = cmp.eq(R0,R1)
3013 // if (p0.new) R2 = add(R3, R4)
3014 // R5 = add (R3, R1)
3016 // if (p0) memw(R5+#0) = R2 <--- trying to include it in the previous packet
3018 // This instruction can be part of the previous packet only if both p0 and R2
3019 // are promoted to .new values. This promotion happens in steps, first
3020 // predicate register is promoted to .new and in the next iteration R2 is
3021 // promoted. Therefore, in case of dependence check failure (due to R5) during
3022 // next iteration, it should be converted back to its most basic form.
3025 // Return the new value instruction for a given store.
3026 int HexagonInstrInfo::getDotNewOp(const MachineInstr* MI) const {
3027 int NVOpcode = Hexagon::getNewValueOpcode(MI->getOpcode());
3028 if (NVOpcode >= 0) // Valid new-value store instruction.
3031 switch (MI->getOpcode()) {
3032 default: llvm_unreachable("Unknown .new type");
3033 case Hexagon::S4_storerb_ur:
3034 return Hexagon::S4_storerbnew_ur;
3036 case Hexagon::S2_storerb_pci:
3037 return Hexagon::S2_storerb_pci;
3039 case Hexagon::S2_storeri_pci:
3040 return Hexagon::S2_storeri_pci;
3042 case Hexagon::S2_storerh_pci:
3043 return Hexagon::S2_storerh_pci;
3045 case Hexagon::S2_storerd_pci:
3046 return Hexagon::S2_storerd_pci;
3048 case Hexagon::S2_storerf_pci:
3049 return Hexagon::S2_storerf_pci;
3051 case Hexagon::V6_vS32b_ai:
3052 return Hexagon::V6_vS32b_new_ai;
3054 case Hexagon::V6_vS32b_pi:
3055 return Hexagon::V6_vS32b_new_pi;
3058 case Hexagon::V6_vS32b_ai_128B:
3059 return Hexagon::V6_vS32b_new_ai_128B;
3061 case Hexagon::V6_vS32b_pi_128B:
3062 return Hexagon::V6_vS32b_new_pi_128B;
3067 // Returns the opcode to use when converting MI, which is a conditional jump,
3068 // into a conditional instruction which uses the .new value of the predicate.
3069 // We also use branch probabilities to add a hint to the jump.
3070 int HexagonInstrInfo::getDotNewPredJumpOp(MachineInstr *MI,
3071 const MachineBranchProbabilityInfo *MBPI) const {
3072 // We assume that block can have at most two successors.
3074 MachineBasicBlock *Src = MI->getParent();
3075 MachineOperand *BrTarget = &MI->getOperand(1);
3076 MachineBasicBlock *Dst = BrTarget->getMBB();
3078 const BranchProbability Prediction = MBPI->getEdgeProbability(Src, Dst);
3079 if (Prediction >= BranchProbability(1,2))
3082 switch (MI->getOpcode()) {
3083 case Hexagon::J2_jumpt:
3084 return taken ? Hexagon::J2_jumptnewpt : Hexagon::J2_jumptnew;
3085 case Hexagon::J2_jumpf:
3086 return taken ? Hexagon::J2_jumpfnewpt : Hexagon::J2_jumpfnew;
3089 llvm_unreachable("Unexpected jump instruction.");
3094 // Return .new predicate version for an instruction.
3095 int HexagonInstrInfo::getDotNewPredOp(MachineInstr *MI,
3096 const MachineBranchProbabilityInfo *MBPI) const {
3097 int NewOpcode = Hexagon::getPredNewOpcode(MI->getOpcode());
3098 if (NewOpcode >= 0) // Valid predicate new instruction
3101 switch (MI->getOpcode()) {
3103 case Hexagon::J2_jumpt:
3104 case Hexagon::J2_jumpf:
3105 return getDotNewPredJumpOp(MI, MBPI);
3108 assert(0 && "Unknown .new type");
3114 int HexagonInstrInfo::getDotOldOp(const int opc) const {
3116 if (isPredicated(NewOp) && isPredicatedNew(NewOp)) { // Get predicate old form
3117 NewOp = Hexagon::getPredOldOpcode(NewOp);
3118 assert(NewOp >= 0 &&
3119 "Couldn't change predicate new instruction to its old form.");
3122 if (isNewValueStore(NewOp)) { // Convert into non-new-value format
3123 NewOp = Hexagon::getNonNVStore(NewOp);
3124 assert(NewOp >= 0 && "Couldn't change new-value store to its old form.");
3130 // See if instruction could potentially be a duplex candidate.
3131 // If so, return its group. Zero otherwise.
3132 HexagonII::SubInstructionGroup HexagonInstrInfo::getDuplexCandidateGroup(
3133 const MachineInstr *MI) const {
3134 unsigned DstReg, SrcReg, Src1Reg, Src2Reg;
3135 auto &HRI = getRegisterInfo();
3137 switch (MI->getOpcode()) {
3139 return HexagonII::HSIG_None;
3143 // Rd = memw(Rs+#u4:2)
3144 // Rd = memub(Rs+#u4:0)
3145 case Hexagon::L2_loadri_io:
3146 DstReg = MI->getOperand(0).getReg();
3147 SrcReg = MI->getOperand(1).getReg();
3148 // Special case this one from Group L2.
3149 // Rd = memw(r29+#u5:2)
3150 if (isIntRegForSubInst(DstReg)) {
3151 if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
3152 HRI.getStackRegister() == SrcReg &&
3153 MI->getOperand(2).isImm() &&
3154 isShiftedUInt<5,2>(MI->getOperand(2).getImm()))
3155 return HexagonII::HSIG_L2;
3156 // Rd = memw(Rs+#u4:2)
3157 if (isIntRegForSubInst(SrcReg) &&
3158 (MI->getOperand(2).isImm() &&
3159 isShiftedUInt<4,2>(MI->getOperand(2).getImm())))
3160 return HexagonII::HSIG_L1;
3163 case Hexagon::L2_loadrub_io:
3164 // Rd = memub(Rs+#u4:0)
3165 DstReg = MI->getOperand(0).getReg();
3166 SrcReg = MI->getOperand(1).getReg();
3167 if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg) &&
3168 MI->getOperand(2).isImm() && isUInt<4>(MI->getOperand(2).getImm()))
3169 return HexagonII::HSIG_L1;
3174 // Rd = memh/memuh(Rs+#u3:1)
3175 // Rd = memb(Rs+#u3:0)
3176 // Rd = memw(r29+#u5:2) - Handled above.
3177 // Rdd = memd(r29+#u5:3)
3179 // [if ([!]p0[.new])] dealloc_return
3180 // [if ([!]p0[.new])] jumpr r31
3181 case Hexagon::L2_loadrh_io:
3182 case Hexagon::L2_loadruh_io:
3183 // Rd = memh/memuh(Rs+#u3:1)
3184 DstReg = MI->getOperand(0).getReg();
3185 SrcReg = MI->getOperand(1).getReg();
3186 if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg) &&
3187 MI->getOperand(2).isImm() &&
3188 isShiftedUInt<3,1>(MI->getOperand(2).getImm()))
3189 return HexagonII::HSIG_L2;
3191 case Hexagon::L2_loadrb_io:
3192 // Rd = memb(Rs+#u3:0)
3193 DstReg = MI->getOperand(0).getReg();
3194 SrcReg = MI->getOperand(1).getReg();
3195 if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg) &&
3196 MI->getOperand(2).isImm() &&
3197 isUInt<3>(MI->getOperand(2).getImm()))
3198 return HexagonII::HSIG_L2;
3200 case Hexagon::L2_loadrd_io:
3201 // Rdd = memd(r29+#u5:3)
3202 DstReg = MI->getOperand(0).getReg();
3203 SrcReg = MI->getOperand(1).getReg();
3204 if (isDblRegForSubInst(DstReg, HRI) &&
3205 Hexagon::IntRegsRegClass.contains(SrcReg) &&
3206 HRI.getStackRegister() == SrcReg &&
3207 MI->getOperand(2).isImm() &&
3208 isShiftedUInt<5,3>(MI->getOperand(2).getImm()))
3209 return HexagonII::HSIG_L2;
3211 // dealloc_return is not documented in Hexagon Manual, but marked
3212 // with A_SUBINSN attribute in iset_v4classic.py.
3213 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4:
3214 case Hexagon::L4_return:
3215 case Hexagon::L2_deallocframe:
3216 return HexagonII::HSIG_L2;
3217 case Hexagon::EH_RETURN_JMPR:
3218 case Hexagon::JMPret :
3220 // Actual form JMPR %PC<imp-def>, %R31<imp-use>, %R0<imp-use,internal>.
3221 DstReg = MI->getOperand(0).getReg();
3222 if (Hexagon::IntRegsRegClass.contains(DstReg) && (Hexagon::R31 == DstReg))
3223 return HexagonII::HSIG_L2;
3225 case Hexagon::JMPrett:
3226 case Hexagon::JMPretf:
3227 case Hexagon::JMPrettnewpt:
3228 case Hexagon::JMPretfnewpt :
3229 case Hexagon::JMPrettnew :
3230 case Hexagon::JMPretfnew :
3231 DstReg = MI->getOperand(1).getReg();
3232 SrcReg = MI->getOperand(0).getReg();
3233 // [if ([!]p0[.new])] jumpr r31
3234 if ((Hexagon::PredRegsRegClass.contains(SrcReg) &&
3235 (Hexagon::P0 == SrcReg)) &&
3236 (Hexagon::IntRegsRegClass.contains(DstReg) && (Hexagon::R31 == DstReg)))
3237 return HexagonII::HSIG_L2;
3239 case Hexagon::L4_return_t :
3240 case Hexagon::L4_return_f :
3241 case Hexagon::L4_return_tnew_pnt :
3242 case Hexagon::L4_return_fnew_pnt :
3243 case Hexagon::L4_return_tnew_pt :
3244 case Hexagon::L4_return_fnew_pt :
3245 // [if ([!]p0[.new])] dealloc_return
3246 SrcReg = MI->getOperand(0).getReg();
3247 if (Hexagon::PredRegsRegClass.contains(SrcReg) && (Hexagon::P0 == SrcReg))
3248 return HexagonII::HSIG_L2;
3253 // memw(Rs+#u4:2) = Rt
3254 // memb(Rs+#u4:0) = Rt
3255 case Hexagon::S2_storeri_io:
3256 // Special case this one from Group S2.
3257 // memw(r29+#u5:2) = Rt
3258 Src1Reg = MI->getOperand(0).getReg();
3259 Src2Reg = MI->getOperand(2).getReg();
3260 if (Hexagon::IntRegsRegClass.contains(Src1Reg) &&
3261 isIntRegForSubInst(Src2Reg) &&
3262 HRI.getStackRegister() == Src1Reg && MI->getOperand(1).isImm() &&
3263 isShiftedUInt<5,2>(MI->getOperand(1).getImm()))
3264 return HexagonII::HSIG_S2;
3265 // memw(Rs+#u4:2) = Rt
3266 if (isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg) &&
3267 MI->getOperand(1).isImm() &&
3268 isShiftedUInt<4,2>(MI->getOperand(1).getImm()))
3269 return HexagonII::HSIG_S1;
3271 case Hexagon::S2_storerb_io:
3272 // memb(Rs+#u4:0) = Rt
3273 Src1Reg = MI->getOperand(0).getReg();
3274 Src2Reg = MI->getOperand(2).getReg();
3275 if (isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg) &&
3276 MI->getOperand(1).isImm() && isUInt<4>(MI->getOperand(1).getImm()))
3277 return HexagonII::HSIG_S1;
3282 // memh(Rs+#u3:1) = Rt
3283 // memw(r29+#u5:2) = Rt
3284 // memd(r29+#s6:3) = Rtt
3285 // memw(Rs+#u4:2) = #U1
3286 // memb(Rs+#u4) = #U1
3287 // allocframe(#u5:3)
3288 case Hexagon::S2_storerh_io:
3289 // memh(Rs+#u3:1) = Rt
3290 Src1Reg = MI->getOperand(0).getReg();
3291 Src2Reg = MI->getOperand(2).getReg();
3292 if (isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg) &&
3293 MI->getOperand(1).isImm() &&
3294 isShiftedUInt<3,1>(MI->getOperand(1).getImm()))
3295 return HexagonII::HSIG_S1;
3297 case Hexagon::S2_storerd_io:
3298 // memd(r29+#s6:3) = Rtt
3299 Src1Reg = MI->getOperand(0).getReg();
3300 Src2Reg = MI->getOperand(2).getReg();
3301 if (isDblRegForSubInst(Src2Reg, HRI) &&
3302 Hexagon::IntRegsRegClass.contains(Src1Reg) &&
3303 HRI.getStackRegister() == Src1Reg && MI->getOperand(1).isImm() &&
3304 isShiftedInt<6,3>(MI->getOperand(1).getImm()))
3305 return HexagonII::HSIG_S2;
3307 case Hexagon::S4_storeiri_io:
3308 // memw(Rs+#u4:2) = #U1
3309 Src1Reg = MI->getOperand(0).getReg();
3310 if (isIntRegForSubInst(Src1Reg) && MI->getOperand(1).isImm() &&
3311 isShiftedUInt<4,2>(MI->getOperand(1).getImm()) &&
3312 MI->getOperand(2).isImm() && isUInt<1>(MI->getOperand(2).getImm()))
3313 return HexagonII::HSIG_S2;
3315 case Hexagon::S4_storeirb_io:
3316 // memb(Rs+#u4) = #U1
3317 Src1Reg = MI->getOperand(0).getReg();
3318 if (isIntRegForSubInst(Src1Reg) && MI->getOperand(1).isImm() &&
3319 isUInt<4>(MI->getOperand(1).getImm()) && MI->getOperand(2).isImm() &&
3320 MI->getOperand(2).isImm() && isUInt<1>(MI->getOperand(2).getImm()))
3321 return HexagonII::HSIG_S2;
3323 case Hexagon::S2_allocframe:
3324 if (MI->getOperand(0).isImm() &&
3325 isShiftedUInt<5,3>(MI->getOperand(0).getImm()))
3326 return HexagonII::HSIG_S1;
3335 // if ([!]P0[.new]) Rd = #0
3336 // Rd = add(r29,#u6:2)
3338 // P0 = cmp.eq(Rs,#u2)
3339 // Rdd = combine(#0,Rs)
3340 // Rdd = combine(Rs,#0)
3341 // Rdd = combine(#u2,#U2)
3344 // Rd = sxth/sxtb/zxtb/zxth(Rs)
3346 case Hexagon::A2_addi:
3347 DstReg = MI->getOperand(0).getReg();
3348 SrcReg = MI->getOperand(1).getReg();
3349 if (isIntRegForSubInst(DstReg)) {
3350 // Rd = add(r29,#u6:2)
3351 if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
3352 HRI.getStackRegister() == SrcReg && MI->getOperand(2).isImm() &&
3353 isShiftedUInt<6,2>(MI->getOperand(2).getImm()))
3354 return HexagonII::HSIG_A;
3356 if ((DstReg == SrcReg) && MI->getOperand(2).isImm() &&
3357 isInt<7>(MI->getOperand(2).getImm()))
3358 return HexagonII::HSIG_A;
3361 if (isIntRegForSubInst(SrcReg) && MI->getOperand(2).isImm() &&
3362 ((MI->getOperand(2).getImm() == 1) ||
3363 (MI->getOperand(2).getImm() == -1)))
3364 return HexagonII::HSIG_A;
3367 case Hexagon::A2_add:
3369 DstReg = MI->getOperand(0).getReg();
3370 Src1Reg = MI->getOperand(1).getReg();
3371 Src2Reg = MI->getOperand(2).getReg();
3372 if (isIntRegForSubInst(DstReg) && (DstReg == Src1Reg) &&
3373 isIntRegForSubInst(Src2Reg))
3374 return HexagonII::HSIG_A;
3376 case Hexagon::A2_andir:
3378 // Rd16=and(Rs16,#255)
3379 // Rd16=and(Rs16,#1)
3380 DstReg = MI->getOperand(0).getReg();
3381 SrcReg = MI->getOperand(1).getReg();
3382 if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg) &&
3383 MI->getOperand(2).isImm() &&
3384 ((MI->getOperand(2).getImm() == 1) ||
3385 (MI->getOperand(2).getImm() == 255)))
3386 return HexagonII::HSIG_A;
3388 case Hexagon::A2_tfr:
3390 DstReg = MI->getOperand(0).getReg();
3391 SrcReg = MI->getOperand(1).getReg();
3392 if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg))
3393 return HexagonII::HSIG_A;
3395 case Hexagon::A2_tfrsi:
3397 // Do not test for #u6 size since the const is getting extended
3398 // regardless and compound could be formed.
3400 DstReg = MI->getOperand(0).getReg();
3401 if (isIntRegForSubInst(DstReg))
3402 return HexagonII::HSIG_A;
3404 case Hexagon::C2_cmoveit:
3405 case Hexagon::C2_cmovenewit:
3406 case Hexagon::C2_cmoveif:
3407 case Hexagon::C2_cmovenewif:
3408 // if ([!]P0[.new]) Rd = #0
3410 // %R16<def> = C2_cmovenewit %P0<internal>, 0, %R16<imp-use,undef>;
3411 DstReg = MI->getOperand(0).getReg();
3412 SrcReg = MI->getOperand(1).getReg();
3413 if (isIntRegForSubInst(DstReg) &&
3414 Hexagon::PredRegsRegClass.contains(SrcReg) && Hexagon::P0 == SrcReg &&
3415 MI->getOperand(2).isImm() && MI->getOperand(2).getImm() == 0)
3416 return HexagonII::HSIG_A;
3418 case Hexagon::C2_cmpeqi:
3419 // P0 = cmp.eq(Rs,#u2)
3420 DstReg = MI->getOperand(0).getReg();
3421 SrcReg = MI->getOperand(1).getReg();
3422 if (Hexagon::PredRegsRegClass.contains(DstReg) &&
3423 Hexagon::P0 == DstReg && isIntRegForSubInst(SrcReg) &&
3424 MI->getOperand(2).isImm() && isUInt<2>(MI->getOperand(2).getImm()))
3425 return HexagonII::HSIG_A;
3427 case Hexagon::A2_combineii:
3428 case Hexagon::A4_combineii:
3429 // Rdd = combine(#u2,#U2)
3430 DstReg = MI->getOperand(0).getReg();
3431 if (isDblRegForSubInst(DstReg, HRI) &&
3432 ((MI->getOperand(1).isImm() && isUInt<2>(MI->getOperand(1).getImm())) ||
3433 (MI->getOperand(1).isGlobal() &&
3434 isUInt<2>(MI->getOperand(1).getOffset()))) &&
3435 ((MI->getOperand(2).isImm() && isUInt<2>(MI->getOperand(2).getImm())) ||
3436 (MI->getOperand(2).isGlobal() &&
3437 isUInt<2>(MI->getOperand(2).getOffset()))))
3438 return HexagonII::HSIG_A;
3440 case Hexagon::A4_combineri:
3441 // Rdd = combine(Rs,#0)
3442 DstReg = MI->getOperand(0).getReg();
3443 SrcReg = MI->getOperand(1).getReg();
3444 if (isDblRegForSubInst(DstReg, HRI) && isIntRegForSubInst(SrcReg) &&
3445 ((MI->getOperand(2).isImm() && MI->getOperand(2).getImm() == 0) ||
3446 (MI->getOperand(2).isGlobal() && MI->getOperand(2).getOffset() == 0)))
3447 return HexagonII::HSIG_A;
3449 case Hexagon::A4_combineir:
3450 // Rdd = combine(#0,Rs)
3451 DstReg = MI->getOperand(0).getReg();
3452 SrcReg = MI->getOperand(2).getReg();
3453 if (isDblRegForSubInst(DstReg, HRI) && isIntRegForSubInst(SrcReg) &&
3454 ((MI->getOperand(1).isImm() && MI->getOperand(1).getImm() == 0) ||
3455 (MI->getOperand(1).isGlobal() && MI->getOperand(1).getOffset() == 0)))
3456 return HexagonII::HSIG_A;
3458 case Hexagon::A2_sxtb:
3459 case Hexagon::A2_sxth:
3460 case Hexagon::A2_zxtb:
3461 case Hexagon::A2_zxth:
3462 // Rd = sxth/sxtb/zxtb/zxth(Rs)
3463 DstReg = MI->getOperand(0).getReg();
3464 SrcReg = MI->getOperand(1).getReg();
3465 if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg))
3466 return HexagonII::HSIG_A;
3470 return HexagonII::HSIG_None;
3474 short HexagonInstrInfo::getEquivalentHWInstr(MachineInstr *MI) const {
3475 return Hexagon::getRealHWInstr(MI->getOpcode(), Hexagon::InstrType_Real);
3479 // Return first non-debug instruction in the basic block.
3480 MachineInstr *HexagonInstrInfo::getFirstNonDbgInst(MachineBasicBlock *BB)
3482 for (auto MII = BB->instr_begin(), End = BB->instr_end(); MII != End; MII++) {
3483 MachineInstr *MI = &*MII;
3484 if (MI->isDebugValue())
3492 unsigned HexagonInstrInfo::getInstrTimingClassLatency(
3493 const InstrItineraryData *ItinData, const MachineInstr *MI) const {
3494 // Default to one cycle for no itinerary. However, an "empty" itinerary may
3495 // still have a MinLatency property, which getStageLatency checks.
3497 return getInstrLatency(ItinData, MI);
3499 // Get the latency embedded in the itinerary. If we're not using timing class
3500 // latencies or if we using BSB scheduling, then restrict the maximum latency
3501 // to 1 (that is, either 0 or 1).
3502 if (MI->isTransient())
3504 unsigned Latency = ItinData->getStageLatency(MI->getDesc().getSchedClass());
3505 if (!EnableTimingClassLatency ||
3506 MI->getParent()->getParent()->getSubtarget<HexagonSubtarget>().
3514 // inverts the predication logic.
3517 bool HexagonInstrInfo::getInvertedPredSense(
3518 SmallVectorImpl<MachineOperand> &Cond) const {
3521 unsigned Opc = getInvertedPredicatedOpcode(Cond[0].getImm());
3522 Cond[0].setImm(Opc);
3527 unsigned HexagonInstrInfo::getInvertedPredicatedOpcode(const int Opc) const {
3529 InvPredOpcode = isPredicatedTrue(Opc) ? Hexagon::getFalsePredOpcode(Opc)
3530 : Hexagon::getTruePredOpcode(Opc);
3531 if (InvPredOpcode >= 0) // Valid instruction with the inverted predicate.
3532 return InvPredOpcode;
3534 llvm_unreachable("Unexpected predicated instruction");
3538 // Returns the max value that doesn't need to be extended.
3539 int HexagonInstrInfo::getMaxValue(const MachineInstr *MI) const {
3540 const uint64_t F = MI->getDesc().TSFlags;
3541 unsigned isSigned = (F >> HexagonII::ExtentSignedPos)
3542 & HexagonII::ExtentSignedMask;
3543 unsigned bits = (F >> HexagonII::ExtentBitsPos)
3544 & HexagonII::ExtentBitsMask;
3546 if (isSigned) // if value is signed
3547 return ~(-1U << (bits - 1));
3549 return ~(-1U << bits);
3553 unsigned HexagonInstrInfo::getMemAccessSize(const MachineInstr* MI) const {
3554 const uint64_t F = MI->getDesc().TSFlags;
3555 return (F >> HexagonII::MemAccessSizePos) & HexagonII::MemAccesSizeMask;
3559 // Returns the min value that doesn't need to be extended.
3560 int HexagonInstrInfo::getMinValue(const MachineInstr *MI) const {
3561 const uint64_t F = MI->getDesc().TSFlags;
3562 unsigned isSigned = (F >> HexagonII::ExtentSignedPos)
3563 & HexagonII::ExtentSignedMask;
3564 unsigned bits = (F >> HexagonII::ExtentBitsPos)
3565 & HexagonII::ExtentBitsMask;
3567 if (isSigned) // if value is signed
3568 return -1U << (bits - 1);
3574 // Returns opcode of the non-extended equivalent instruction.
3575 short HexagonInstrInfo::getNonExtOpcode(const MachineInstr *MI) const {
3576 // Check if the instruction has a register form that uses register in place
3577 // of the extended operand, if so return that as the non-extended form.
3578 short NonExtOpcode = Hexagon::getRegForm(MI->getOpcode());
3579 if (NonExtOpcode >= 0)
3580 return NonExtOpcode;
3582 if (MI->getDesc().mayLoad() || MI->getDesc().mayStore()) {
3583 // Check addressing mode and retrieve non-ext equivalent instruction.
3584 switch (getAddrMode(MI)) {
3585 case HexagonII::Absolute :
3586 return Hexagon::getBaseWithImmOffset(MI->getOpcode());
3587 case HexagonII::BaseImmOffset :
3588 return Hexagon::getBaseWithRegOffset(MI->getOpcode());
3589 case HexagonII::BaseLongOffset:
3590 return Hexagon::getRegShlForm(MI->getOpcode());
3600 bool HexagonInstrInfo::getPredReg(ArrayRef<MachineOperand> Cond,
3601 unsigned &PredReg, unsigned &PredRegPos, unsigned &PredRegFlags) const {
3604 assert(Cond.size() == 2);
3605 if (isNewValueJump(Cond[0].getImm()) || Cond[1].isMBB()) {
3606 DEBUG(dbgs() << "No predregs for new-value jumps/endloop");
3609 PredReg = Cond[1].getReg();
3611 // See IfConversion.cpp why we add RegState::Implicit | RegState::Undef
3613 if (Cond[1].isImplicit())
3614 PredRegFlags = RegState::Implicit;
3615 if (Cond[1].isUndef())
3616 PredRegFlags |= RegState::Undef;
3621 short HexagonInstrInfo::getPseudoInstrPair(MachineInstr *MI) const {
3622 return Hexagon::getRealHWInstr(MI->getOpcode(), Hexagon::InstrType_Pseudo);
3626 short HexagonInstrInfo::getRegForm(const MachineInstr *MI) const {
3627 return Hexagon::getRegForm(MI->getOpcode());
3631 // Return the number of bytes required to encode the instruction.
3632 // Hexagon instructions are fixed length, 4 bytes, unless they
3633 // use a constant extender, which requires another 4 bytes.
3634 // For debug instructions and prolog labels, return 0.
3635 unsigned HexagonInstrInfo::getSize(const MachineInstr *MI) const {
3636 if (MI->isDebugValue() || MI->isPosition())
3639 unsigned Size = MI->getDesc().getSize();
3641 // Assume the default insn size in case it cannot be determined
3642 // for whatever reason.
3643 Size = HEXAGON_INSTR_SIZE;
3645 if (isConstExtended(MI) || isExtended(MI))
3646 Size += HEXAGON_INSTR_SIZE;
3648 // Try and compute number of instructions in asm.
3649 if (BranchRelaxAsmLarge && MI->getOpcode() == Hexagon::INLINEASM) {
3650 const MachineBasicBlock &MBB = *MI->getParent();
3651 const MachineFunction *MF = MBB.getParent();
3652 const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
3654 // Count the number of register definitions to find the asm string.
3655 unsigned NumDefs = 0;
3656 for (; MI->getOperand(NumDefs).isReg() && MI->getOperand(NumDefs).isDef();
3658 assert(NumDefs != MI->getNumOperands()-2 && "No asm string?");
3660 assert(MI->getOperand(NumDefs).isSymbol() && "No asm string?");
3661 // Disassemble the AsmStr and approximate number of instructions.
3662 const char *AsmStr = MI->getOperand(NumDefs).getSymbolName();
3663 Size = getInlineAsmLength(AsmStr, *MAI);
3670 uint64_t HexagonInstrInfo::getType(const MachineInstr* MI) const {
3671 const uint64_t F = MI->getDesc().TSFlags;
3672 return (F >> HexagonII::TypePos) & HexagonII::TypeMask;
3676 unsigned HexagonInstrInfo::getUnits(const MachineInstr* MI) const {
3677 const TargetSubtargetInfo &ST = MI->getParent()->getParent()->getSubtarget();
3678 const InstrItineraryData &II = *ST.getInstrItineraryData();
3679 const InstrStage &IS = *II.beginStage(MI->getDesc().getSchedClass());
3681 return IS.getUnits();
3685 unsigned HexagonInstrInfo::getValidSubTargets(const unsigned Opcode) const {
3686 const uint64_t F = get(Opcode).TSFlags;
3687 return (F >> HexagonII::validSubTargetPos) & HexagonII::validSubTargetMask;
3691 // Calculate size of the basic block without debug instructions.
3692 unsigned HexagonInstrInfo::nonDbgBBSize(const MachineBasicBlock *BB) const {
3693 return nonDbgMICount(BB->instr_begin(), BB->instr_end());
3697 unsigned HexagonInstrInfo::nonDbgBundleSize(
3698 MachineBasicBlock::const_iterator BundleHead) const {
3699 assert(BundleHead->isBundle() && "Not a bundle header");
3700 auto MII = BundleHead.getInstrIterator();
3701 // Skip the bundle header.
3702 return nonDbgMICount(++MII, getBundleEnd(BundleHead));
3706 /// immediateExtend - Changes the instruction in place to one using an immediate
3708 void HexagonInstrInfo::immediateExtend(MachineInstr *MI) const {
3709 assert((isExtendable(MI)||isConstExtended(MI)) &&
3710 "Instruction must be extendable");
3711 // Find which operand is extendable.
3712 short ExtOpNum = getCExtOpNum(MI);
3713 MachineOperand &MO = MI->getOperand(ExtOpNum);
3714 // This needs to be something we understand.
3715 assert((MO.isMBB() || MO.isImm()) &&
3716 "Branch with unknown extendable field type");
3717 // Mark given operand as extended.
3718 MO.addTargetFlag(HexagonII::HMOTF_ConstExtended);
3722 bool HexagonInstrInfo::invertAndChangeJumpTarget(
3723 MachineInstr* MI, MachineBasicBlock* NewTarget) const {
3724 DEBUG(dbgs() << "\n[invertAndChangeJumpTarget] to BB#"
3725 << NewTarget->getNumber(); MI->dump(););
3726 assert(MI->isBranch());
3727 unsigned NewOpcode = getInvertedPredicatedOpcode(MI->getOpcode());
3728 int TargetPos = MI->getNumOperands() - 1;
3729 // In general branch target is the last operand,
3730 // but some implicit defs added at the end might change it.
3731 while ((TargetPos > -1) && !MI->getOperand(TargetPos).isMBB())
3733 assert((TargetPos >= 0) && MI->getOperand(TargetPos).isMBB());
3734 MI->getOperand(TargetPos).setMBB(NewTarget);
3735 if (EnableBranchPrediction && isPredicatedNew(MI)) {
3736 NewOpcode = reversePrediction(NewOpcode);
3738 MI->setDesc(get(NewOpcode));
3743 void HexagonInstrInfo::genAllInsnTimingClasses(MachineFunction &MF) const {
3744 /* +++ The code below is used to generate complete set of Hexagon Insn +++ */
3745 MachineFunction::iterator A = MF.begin();
3746 MachineBasicBlock &B = *A;
3747 MachineBasicBlock::iterator I = B.begin();
3748 MachineInstr *MI = &*I;
3749 DebugLoc DL = MI->getDebugLoc();
3750 MachineInstr *NewMI;
3752 for (unsigned insn = TargetOpcode::GENERIC_OP_END+1;
3753 insn < Hexagon::INSTRUCTION_LIST_END; ++insn) {
3754 NewMI = BuildMI(B, MI, DL, get(insn));
3755 DEBUG(dbgs() << "\n" << getName(NewMI->getOpcode()) <<
3756 " Class: " << NewMI->getDesc().getSchedClass());
3757 NewMI->eraseFromParent();
3759 /* --- The code above is used to generate complete set of Hexagon Insn --- */
3763 // inverts the predication logic.
3766 bool HexagonInstrInfo::reversePredSense(MachineInstr* MI) const {
3767 DEBUG(dbgs() << "\nTrying to reverse pred. sense of:"; MI->dump());
3768 MI->setDesc(get(getInvertedPredicatedOpcode(MI->getOpcode())));
3773 // Reverse the branch prediction.
3774 unsigned HexagonInstrInfo::reversePrediction(unsigned Opcode) const {
3775 int PredRevOpcode = -1;
3776 if (isPredictedTaken(Opcode))
3777 PredRevOpcode = Hexagon::notTakenBranchPrediction(Opcode);
3779 PredRevOpcode = Hexagon::takenBranchPrediction(Opcode);
3780 assert(PredRevOpcode > 0);
3781 return PredRevOpcode;
3785 // TODO: Add more rigorous validation.
3786 bool HexagonInstrInfo::validateBranchCond(const ArrayRef<MachineOperand> &Cond)
3788 return Cond.empty() || (Cond[0].isImm() && (Cond.size() != 1));