1 //===-- HexagonInstrInfo.cpp - Hexagon Instruction Information ------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Hexagon implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "HexagonInstrInfo.h"
16 #include "HexagonRegisterInfo.h"
17 #include "HexagonSubtarget.h"
18 #include "llvm/ADT/STLExtras.h"
19 #include "llvm/ADT/SmallVector.h"
20 #include "llvm/CodeGen/DFAPacketizer.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineMemOperand.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/PseudoSourceValue.h"
26 #include "llvm/Support/Debug.h"
27 #include "llvm/Support/MathExtras.h"
28 #include "llvm/Support/raw_ostream.h"
32 #define DEBUG_TYPE "hexagon-instrinfo"
34 #define GET_INSTRINFO_CTOR_DTOR
35 #define GET_INSTRMAP_INFO
36 #include "HexagonGenInstrInfo.inc"
37 #include "HexagonGenDFAPacketizer.inc"
40 /// Constants for Hexagon instructions.
42 const int Hexagon_MEMW_OFFSET_MAX = 4095;
43 const int Hexagon_MEMW_OFFSET_MIN = -4096;
44 const int Hexagon_MEMD_OFFSET_MAX = 8191;
45 const int Hexagon_MEMD_OFFSET_MIN = -8192;
46 const int Hexagon_MEMH_OFFSET_MAX = 2047;
47 const int Hexagon_MEMH_OFFSET_MIN = -2048;
48 const int Hexagon_MEMB_OFFSET_MAX = 1023;
49 const int Hexagon_MEMB_OFFSET_MIN = -1024;
50 const int Hexagon_ADDI_OFFSET_MAX = 32767;
51 const int Hexagon_ADDI_OFFSET_MIN = -32768;
52 const int Hexagon_MEMD_AUTOINC_MAX = 56;
53 const int Hexagon_MEMD_AUTOINC_MIN = -64;
54 const int Hexagon_MEMW_AUTOINC_MAX = 28;
55 const int Hexagon_MEMW_AUTOINC_MIN = -32;
56 const int Hexagon_MEMH_AUTOINC_MAX = 14;
57 const int Hexagon_MEMH_AUTOINC_MIN = -16;
58 const int Hexagon_MEMB_AUTOINC_MAX = 7;
59 const int Hexagon_MEMB_AUTOINC_MIN = -8;
61 // Pin the vtable to this file.
62 void HexagonInstrInfo::anchor() {}
64 HexagonInstrInfo::HexagonInstrInfo(HexagonSubtarget &ST)
65 : HexagonGenInstrInfo(Hexagon::ADJCALLSTACKDOWN, Hexagon::ADJCALLSTACKUP),
66 RI(), Subtarget(ST) {}
68 /// isLoadFromStackSlot - If the specified machine instruction is a direct
69 /// load from a stack slot, return the virtual or physical register number of
70 /// the destination along with the FrameIndex of the loaded stack slot. If
71 /// not, return 0. This predicate must return 0 if the instruction has
72 /// any side effects other than loading from the stack slot.
73 unsigned HexagonInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
74 int &FrameIndex) const {
77 switch (MI->getOpcode()) {
79 case Hexagon::L2_loadri_io:
80 case Hexagon::L2_loadrd_io:
81 case Hexagon::L2_loadrh_io:
82 case Hexagon::L2_loadrb_io:
83 case Hexagon::L2_loadrub_io:
84 if (MI->getOperand(2).isFI() &&
85 MI->getOperand(1).isImm() && (MI->getOperand(1).getImm() == 0)) {
86 FrameIndex = MI->getOperand(2).getIndex();
87 return MI->getOperand(0).getReg();
95 /// isStoreToStackSlot - If the specified machine instruction is a direct
96 /// store to a stack slot, return the virtual or physical register number of
97 /// the source reg along with the FrameIndex of the loaded stack slot. If
98 /// not, return 0. This predicate must return 0 if the instruction has
99 /// any side effects other than storing to the stack slot.
100 unsigned HexagonInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
101 int &FrameIndex) const {
102 switch (MI->getOpcode()) {
104 case Hexagon::S2_storeri_io:
105 case Hexagon::S2_storerd_io:
106 case Hexagon::S2_storerh_io:
107 case Hexagon::S2_storerb_io:
108 if (MI->getOperand(2).isFI() &&
109 MI->getOperand(1).isImm() && (MI->getOperand(1).getImm() == 0)) {
110 FrameIndex = MI->getOperand(0).getIndex();
111 return MI->getOperand(2).getReg();
118 // Find the hardware loop instruction used to set-up the specified loop.
119 // On Hexagon, we have two instructions used to set-up the hardware loop
120 // (LOOP0, LOOP1) with corresponding endloop (ENDLOOP0, ENDLOOP1) instructions
121 // to indicate the end of a loop.
122 static MachineInstr *
123 findLoopInstr(MachineBasicBlock *BB, int EndLoopOp,
124 SmallPtrSet<MachineBasicBlock *, 8> &Visited) {
127 if (EndLoopOp == Hexagon::ENDLOOP0) {
128 LOOPi = Hexagon::J2_loop0i;
129 LOOPr = Hexagon::J2_loop0r;
130 } else { // EndLoopOp == Hexagon::EndLOOP1
131 LOOPi = Hexagon::J2_loop1i;
132 LOOPr = Hexagon::J2_loop1r;
135 // The loop set-up instruction will be in a predecessor block
136 for (MachineBasicBlock::pred_iterator PB = BB->pred_begin(),
137 PE = BB->pred_end(); PB != PE; ++PB) {
138 // If this has been visited, already skip it.
139 if (!Visited.insert(*PB).second)
143 for (MachineBasicBlock::reverse_instr_iterator I = (*PB)->instr_rbegin(),
144 E = (*PB)->instr_rend(); I != E; ++I) {
145 int Opc = I->getOpcode();
146 if (Opc == LOOPi || Opc == LOOPr)
148 // We've reached a different loop, which means the loop0 has been removed.
149 if (Opc == EndLoopOp)
152 // Check the predecessors for the LOOP instruction.
153 MachineInstr *loop = findLoopInstr(*PB, EndLoopOp, Visited);
160 unsigned HexagonInstrInfo::InsertBranch(
161 MachineBasicBlock &MBB,MachineBasicBlock *TBB, MachineBasicBlock *FBB,
162 ArrayRef<MachineOperand> Cond, DebugLoc DL) const {
164 Opcode_t BOpc = Hexagon::J2_jump;
165 Opcode_t BccOpc = Hexagon::J2_jumpt;
167 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
169 // Check if ReverseBranchCondition has asked to reverse this branch
170 // If we want to reverse the branch an odd number of times, we want
172 if (!Cond.empty() && Cond[0].isImm())
173 BccOpc = Cond[0].getImm();
177 // Due to a bug in TailMerging/CFG Optimization, we need to add a
178 // special case handling of a predicated jump followed by an
179 // unconditional jump. If not, Tail Merging and CFG Optimization go
180 // into an infinite loop.
181 MachineBasicBlock *NewTBB, *NewFBB;
182 SmallVector<MachineOperand, 4> Cond;
183 MachineInstr *Term = MBB.getFirstTerminator();
184 if (Term != MBB.end() && isPredicated(Term) &&
185 !AnalyzeBranch(MBB, NewTBB, NewFBB, Cond, false)) {
186 MachineBasicBlock *NextBB =
187 std::next(MachineFunction::iterator(&MBB));
188 if (NewTBB == NextBB) {
189 ReverseBranchCondition(Cond);
191 return InsertBranch(MBB, TBB, nullptr, Cond, DL);
194 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
195 } else if (isEndLoopN(Cond[0].getImm())) {
196 int EndLoopOp = Cond[0].getImm();
197 assert(Cond[1].isMBB());
198 // Since we're adding an ENDLOOP, there better be a LOOP instruction.
199 // Check for it, and change the BB target if needed.
200 SmallPtrSet<MachineBasicBlock *, 8> VisitedBBs;
201 MachineInstr *Loop = findLoopInstr(TBB, EndLoopOp, VisitedBBs);
202 assert(Loop != 0 && "Inserting an ENDLOOP without a LOOP");
203 Loop->getOperand(0).setMBB(TBB);
204 // Add the ENDLOOP after the finding the LOOP0.
205 BuildMI(&MBB, DL, get(EndLoopOp)).addMBB(TBB);
206 } else if (isNewValueJump(Cond[0].getImm())) {
207 assert((Cond.size() == 3) && "Only supporting rr/ri version of nvjump");
209 // (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset)
210 // (ins IntRegs:$src1, u5Imm:$src2, brtarget:$offset)
211 unsigned Flags1 = getUndefRegState(Cond[1].isUndef());
212 DEBUG(dbgs() << "\nInserting NVJump for BB#" << MBB.getNumber(););
213 if (Cond[2].isReg()) {
214 unsigned Flags2 = getUndefRegState(Cond[2].isUndef());
215 BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[1].getReg(), Flags1).
216 addReg(Cond[2].getReg(), Flags2).addMBB(TBB);
217 } else if(Cond[2].isImm()) {
218 BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[1].getReg(), Flags1).
219 addImm(Cond[2].getImm()).addMBB(TBB);
221 llvm_unreachable("Invalid condition for branching");
223 assert((Cond.size() == 2) && "Malformed cond vector");
224 const MachineOperand &RO = Cond[1];
225 unsigned Flags = getUndefRegState(RO.isUndef());
226 BuildMI(&MBB, DL, get(BccOpc)).addReg(RO.getReg(), Flags).addMBB(TBB);
230 assert((!Cond.empty()) &&
231 "Cond. cannot be empty when multiple branchings are required");
232 assert((!isNewValueJump(Cond[0].getImm())) &&
233 "NV-jump cannot be inserted with another branch");
234 // Special case for hardware loops. The condition is a basic block.
235 if (isEndLoopN(Cond[0].getImm())) {
236 int EndLoopOp = Cond[0].getImm();
237 assert(Cond[1].isMBB());
238 // Since we're adding an ENDLOOP, there better be a LOOP instruction.
239 // Check for it, and change the BB target if needed.
240 SmallPtrSet<MachineBasicBlock *, 8> VisitedBBs;
241 MachineInstr *Loop = findLoopInstr(TBB, EndLoopOp, VisitedBBs);
242 assert(Loop != 0 && "Inserting an ENDLOOP without a LOOP");
243 Loop->getOperand(0).setMBB(TBB);
244 // Add the ENDLOOP after the finding the LOOP0.
245 BuildMI(&MBB, DL, get(EndLoopOp)).addMBB(TBB);
247 const MachineOperand &RO = Cond[1];
248 unsigned Flags = getUndefRegState(RO.isUndef());
249 BuildMI(&MBB, DL, get(BccOpc)).addReg(RO.getReg(), Flags).addMBB(TBB);
251 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
257 /// This function can analyze one/two way branching only and should (mostly) be
258 /// called by target independent side.
259 /// First entry is always the opcode of the branching instruction, except when
260 /// the Cond vector is supposed to be empty, e.g., when AnalyzeBranch fails, a
261 /// BB with only unconditional jump. Subsequent entries depend upon the opcode,
262 /// e.g. Jump_c p will have
266 /// Cond[0] = ENDLOOP
269 /// Cond[0] = Hexagon::CMPEQri_f_Jumpnv_t_V4 -- specific opcode
272 /// @note Related function is \fn findInstrPredicate which fills in
273 /// Cond. vector when a predicated instruction is passed to it.
274 /// We follow same protocol in that case too.
276 bool HexagonInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
277 MachineBasicBlock *&TBB,
278 MachineBasicBlock *&FBB,
279 SmallVectorImpl<MachineOperand> &Cond,
280 bool AllowModify) const {
285 // If the block has no terminators, it just falls into the block after it.
286 MachineBasicBlock::instr_iterator I = MBB.instr_end();
287 if (I == MBB.instr_begin())
290 // A basic block may looks like this:
300 // It has two succs but does not have a terminator
301 // Don't know how to handle it.
305 // Don't analyze EH branches.
307 } while (I != MBB.instr_begin());
312 while (I->isDebugValue()) {
313 if (I == MBB.instr_begin())
318 bool JumpToBlock = I->getOpcode() == Hexagon::J2_jump &&
319 I->getOperand(0).isMBB();
320 // Delete the J2_jump if it's equivalent to a fall-through.
321 if (AllowModify && JumpToBlock &&
322 MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
323 DEBUG(dbgs()<< "\nErasing the jump to successor block\n";);
324 I->eraseFromParent();
326 if (I == MBB.instr_begin())
330 if (!isUnpredicatedTerminator(I))
333 // Get the last instruction in the block.
334 MachineInstr *LastInst = I;
335 MachineInstr *SecondLastInst = nullptr;
336 // Find one more terminator if present.
338 if (&*I != LastInst && !I->isBundle() && isUnpredicatedTerminator(I)) {
342 // This is a third branch.
345 if (I == MBB.instr_begin())
350 int LastOpcode = LastInst->getOpcode();
351 int SecLastOpcode = SecondLastInst ? SecondLastInst->getOpcode() : 0;
352 // If the branch target is not a basic block, it could be a tail call.
353 // (It is, if the target is a function.)
354 if (LastOpcode == Hexagon::J2_jump && !LastInst->getOperand(0).isMBB())
356 if (SecLastOpcode == Hexagon::J2_jump &&
357 !SecondLastInst->getOperand(0).isMBB())
360 bool LastOpcodeHasJMP_c = PredOpcodeHasJMP_c(LastOpcode);
361 bool LastOpcodeHasNVJump = isNewValueJump(LastInst);
363 // If there is only one terminator instruction, process it.
364 if (LastInst && !SecondLastInst) {
365 if (LastOpcode == Hexagon::J2_jump) {
366 TBB = LastInst->getOperand(0).getMBB();
369 if (isEndLoopN(LastOpcode)) {
370 TBB = LastInst->getOperand(0).getMBB();
371 Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
372 Cond.push_back(LastInst->getOperand(0));
375 if (LastOpcodeHasJMP_c) {
376 TBB = LastInst->getOperand(1).getMBB();
377 Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
378 Cond.push_back(LastInst->getOperand(0));
381 // Only supporting rr/ri versions of new-value jumps.
382 if (LastOpcodeHasNVJump && (LastInst->getNumExplicitOperands() == 3)) {
383 TBB = LastInst->getOperand(2).getMBB();
384 Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
385 Cond.push_back(LastInst->getOperand(0));
386 Cond.push_back(LastInst->getOperand(1));
389 DEBUG(dbgs() << "\nCant analyze BB#" << MBB.getNumber()
390 << " with one jump\n";);
391 // Otherwise, don't know what this is.
395 bool SecLastOpcodeHasJMP_c = PredOpcodeHasJMP_c(SecLastOpcode);
396 bool SecLastOpcodeHasNVJump = isNewValueJump(SecondLastInst);
397 if (SecLastOpcodeHasJMP_c && (LastOpcode == Hexagon::J2_jump)) {
398 TBB = SecondLastInst->getOperand(1).getMBB();
399 Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
400 Cond.push_back(SecondLastInst->getOperand(0));
401 FBB = LastInst->getOperand(0).getMBB();
405 // Only supporting rr/ri versions of new-value jumps.
406 if (SecLastOpcodeHasNVJump &&
407 (SecondLastInst->getNumExplicitOperands() == 3) &&
408 (LastOpcode == Hexagon::J2_jump)) {
409 TBB = SecondLastInst->getOperand(2).getMBB();
410 Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
411 Cond.push_back(SecondLastInst->getOperand(0));
412 Cond.push_back(SecondLastInst->getOperand(1));
413 FBB = LastInst->getOperand(0).getMBB();
417 // If the block ends with two Hexagon:JMPs, handle it. The second one is not
418 // executed, so remove it.
419 if (SecLastOpcode == Hexagon::J2_jump && LastOpcode == Hexagon::J2_jump) {
420 TBB = SecondLastInst->getOperand(0).getMBB();
423 I->eraseFromParent();
427 // If the block ends with an ENDLOOP, and J2_jump, handle it.
428 if (isEndLoopN(SecLastOpcode) && LastOpcode == Hexagon::J2_jump) {
429 TBB = SecondLastInst->getOperand(0).getMBB();
430 Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
431 Cond.push_back(SecondLastInst->getOperand(0));
432 FBB = LastInst->getOperand(0).getMBB();
435 DEBUG(dbgs() << "\nCant analyze BB#" << MBB.getNumber()
436 << " with two jumps";);
437 // Otherwise, can't handle this.
441 unsigned HexagonInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
442 DEBUG(dbgs() << "\nRemoving branches out of BB#" << MBB.getNumber());
443 MachineBasicBlock::iterator I = MBB.end();
445 while (I != MBB.begin()) {
447 if (I->isDebugValue())
449 // Only removing branches from end of MBB.
452 if (Count && (I->getOpcode() == Hexagon::J2_jump))
453 llvm_unreachable("Malformed basic block: unconditional branch not last");
454 MBB.erase(&MBB.back());
461 /// \brief For a comparison instruction, return the source registers in
462 /// \p SrcReg and \p SrcReg2 if having two register operands, and the value it
463 /// compares against in CmpValue. Return true if the comparison instruction
465 bool HexagonInstrInfo::analyzeCompare(const MachineInstr *MI,
466 unsigned &SrcReg, unsigned &SrcReg2,
467 int &Mask, int &Value) const {
468 unsigned Opc = MI->getOpcode();
470 // Set mask and the first source register.
472 case Hexagon::C2_cmpeq:
473 case Hexagon::C2_cmpeqp:
474 case Hexagon::C2_cmpgt:
475 case Hexagon::C2_cmpgtp:
476 case Hexagon::C2_cmpgtu:
477 case Hexagon::C2_cmpgtup:
478 case Hexagon::C4_cmpneq:
479 case Hexagon::C4_cmplte:
480 case Hexagon::C4_cmplteu:
481 case Hexagon::C2_cmpeqi:
482 case Hexagon::C2_cmpgti:
483 case Hexagon::C2_cmpgtui:
484 case Hexagon::C4_cmpneqi:
485 case Hexagon::C4_cmplteui:
486 case Hexagon::C4_cmpltei:
487 SrcReg = MI->getOperand(1).getReg();
490 case Hexagon::A4_cmpbeq:
491 case Hexagon::A4_cmpbgt:
492 case Hexagon::A4_cmpbgtu:
493 case Hexagon::A4_cmpbeqi:
494 case Hexagon::A4_cmpbgti:
495 case Hexagon::A4_cmpbgtui:
496 SrcReg = MI->getOperand(1).getReg();
499 case Hexagon::A4_cmpheq:
500 case Hexagon::A4_cmphgt:
501 case Hexagon::A4_cmphgtu:
502 case Hexagon::A4_cmpheqi:
503 case Hexagon::A4_cmphgti:
504 case Hexagon::A4_cmphgtui:
505 SrcReg = MI->getOperand(1).getReg();
510 // Set the value/second source register.
512 case Hexagon::C2_cmpeq:
513 case Hexagon::C2_cmpeqp:
514 case Hexagon::C2_cmpgt:
515 case Hexagon::C2_cmpgtp:
516 case Hexagon::C2_cmpgtu:
517 case Hexagon::C2_cmpgtup:
518 case Hexagon::A4_cmpbeq:
519 case Hexagon::A4_cmpbgt:
520 case Hexagon::A4_cmpbgtu:
521 case Hexagon::A4_cmpheq:
522 case Hexagon::A4_cmphgt:
523 case Hexagon::A4_cmphgtu:
524 case Hexagon::C4_cmpneq:
525 case Hexagon::C4_cmplte:
526 case Hexagon::C4_cmplteu:
527 SrcReg2 = MI->getOperand(2).getReg();
530 case Hexagon::C2_cmpeqi:
531 case Hexagon::C2_cmpgtui:
532 case Hexagon::C2_cmpgti:
533 case Hexagon::C4_cmpneqi:
534 case Hexagon::C4_cmplteui:
535 case Hexagon::C4_cmpltei:
536 case Hexagon::A4_cmpbeqi:
537 case Hexagon::A4_cmpbgti:
538 case Hexagon::A4_cmpbgtui:
539 case Hexagon::A4_cmpheqi:
540 case Hexagon::A4_cmphgti:
541 case Hexagon::A4_cmphgtui:
543 Value = MI->getOperand(2).getImm();
551 void HexagonInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
552 MachineBasicBlock::iterator I, DebugLoc DL,
553 unsigned DestReg, unsigned SrcReg,
554 bool KillSrc) const {
555 if (Hexagon::IntRegsRegClass.contains(SrcReg, DestReg)) {
556 BuildMI(MBB, I, DL, get(Hexagon::A2_tfr), DestReg).addReg(SrcReg);
559 if (Hexagon::DoubleRegsRegClass.contains(SrcReg, DestReg)) {
560 BuildMI(MBB, I, DL, get(Hexagon::A2_tfrp), DestReg).addReg(SrcReg);
563 if (Hexagon::PredRegsRegClass.contains(SrcReg, DestReg)) {
564 // Map Pd = Ps to Pd = or(Ps, Ps).
565 BuildMI(MBB, I, DL, get(Hexagon::C2_or),
566 DestReg).addReg(SrcReg).addReg(SrcReg);
569 if (Hexagon::DoubleRegsRegClass.contains(DestReg) &&
570 Hexagon::IntRegsRegClass.contains(SrcReg)) {
571 // We can have an overlap between single and double reg: r1:0 = r0.
572 if(SrcReg == RI.getSubReg(DestReg, Hexagon::subreg_loreg)) {
574 BuildMI(MBB, I, DL, get(Hexagon::A2_tfrsi), (RI.getSubReg(DestReg,
575 Hexagon::subreg_hireg))).addImm(0);
577 // r1:0 = r1 or no overlap.
578 BuildMI(MBB, I, DL, get(Hexagon::A2_tfr), (RI.getSubReg(DestReg,
579 Hexagon::subreg_loreg))).addReg(SrcReg);
580 BuildMI(MBB, I, DL, get(Hexagon::A2_tfrsi), (RI.getSubReg(DestReg,
581 Hexagon::subreg_hireg))).addImm(0);
585 if (Hexagon::CtrRegsRegClass.contains(DestReg) &&
586 Hexagon::IntRegsRegClass.contains(SrcReg)) {
587 BuildMI(MBB, I, DL, get(Hexagon::A2_tfrrcr), DestReg).addReg(SrcReg);
590 if (Hexagon::PredRegsRegClass.contains(SrcReg) &&
591 Hexagon::IntRegsRegClass.contains(DestReg)) {
592 BuildMI(MBB, I, DL, get(Hexagon::C2_tfrpr), DestReg).
593 addReg(SrcReg, getKillRegState(KillSrc));
596 if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
597 Hexagon::PredRegsRegClass.contains(DestReg)) {
598 BuildMI(MBB, I, DL, get(Hexagon::C2_tfrrp), DestReg).
599 addReg(SrcReg, getKillRegState(KillSrc));
603 llvm_unreachable("Unimplemented");
607 void HexagonInstrInfo::
608 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
609 unsigned SrcReg, bool isKill, int FI,
610 const TargetRegisterClass *RC,
611 const TargetRegisterInfo *TRI) const {
613 DebugLoc DL = MBB.findDebugLoc(I);
614 MachineFunction &MF = *MBB.getParent();
615 MachineFrameInfo &MFI = *MF.getFrameInfo();
616 unsigned Align = MFI.getObjectAlignment(FI);
618 MachineMemOperand *MMO = MF.getMachineMemOperand(
619 MachinePointerInfo::getFixedStack(MF, FI), MachineMemOperand::MOStore,
620 MFI.getObjectSize(FI), Align);
622 if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {
623 BuildMI(MBB, I, DL, get(Hexagon::S2_storeri_io))
624 .addFrameIndex(FI).addImm(0)
625 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
626 } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {
627 BuildMI(MBB, I, DL, get(Hexagon::S2_storerd_io))
628 .addFrameIndex(FI).addImm(0)
629 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
630 } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {
631 BuildMI(MBB, I, DL, get(Hexagon::STriw_pred))
632 .addFrameIndex(FI).addImm(0)
633 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
635 llvm_unreachable("Unimplemented");
640 void HexagonInstrInfo::storeRegToAddr(
641 MachineFunction &MF, unsigned SrcReg,
643 SmallVectorImpl<MachineOperand> &Addr,
644 const TargetRegisterClass *RC,
645 SmallVectorImpl<MachineInstr*> &NewMIs) const
647 llvm_unreachable("Unimplemented");
651 void HexagonInstrInfo::
652 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
653 unsigned DestReg, int FI,
654 const TargetRegisterClass *RC,
655 const TargetRegisterInfo *TRI) const {
656 DebugLoc DL = MBB.findDebugLoc(I);
657 MachineFunction &MF = *MBB.getParent();
658 MachineFrameInfo &MFI = *MF.getFrameInfo();
659 unsigned Align = MFI.getObjectAlignment(FI);
661 MachineMemOperand *MMO = MF.getMachineMemOperand(
662 MachinePointerInfo::getFixedStack(MF, FI), MachineMemOperand::MOLoad,
663 MFI.getObjectSize(FI), Align);
664 if (RC == &Hexagon::IntRegsRegClass) {
665 BuildMI(MBB, I, DL, get(Hexagon::L2_loadri_io), DestReg)
666 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
667 } else if (RC == &Hexagon::DoubleRegsRegClass) {
668 BuildMI(MBB, I, DL, get(Hexagon::L2_loadrd_io), DestReg)
669 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
670 } else if (RC == &Hexagon::PredRegsRegClass) {
671 BuildMI(MBB, I, DL, get(Hexagon::LDriw_pred), DestReg)
672 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
674 llvm_unreachable("Can't store this register to stack slot");
679 void HexagonInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
680 SmallVectorImpl<MachineOperand> &Addr,
681 const TargetRegisterClass *RC,
682 SmallVectorImpl<MachineInstr*> &NewMIs) const {
683 llvm_unreachable("Unimplemented");
686 HexagonInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
687 const HexagonRegisterInfo &HRI = getRegisterInfo();
688 MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
689 MachineBasicBlock &MBB = *MI->getParent();
690 DebugLoc DL = MI->getDebugLoc();
691 unsigned Opc = MI->getOpcode();
694 case Hexagon::ALIGNA:
695 BuildMI(MBB, MI, DL, get(Hexagon::A2_andir), MI->getOperand(0).getReg())
696 .addReg(HRI.getFrameRegister())
697 .addImm(-MI->getOperand(1).getImm());
700 case Hexagon::TFR_PdTrue: {
701 unsigned Reg = MI->getOperand(0).getReg();
702 BuildMI(MBB, MI, DL, get(Hexagon::C2_orn), Reg)
703 .addReg(Reg, RegState::Undef)
704 .addReg(Reg, RegState::Undef);
708 case Hexagon::TFR_PdFalse: {
709 unsigned Reg = MI->getOperand(0).getReg();
710 BuildMI(MBB, MI, DL, get(Hexagon::C2_andn), Reg)
711 .addReg(Reg, RegState::Undef)
712 .addReg(Reg, RegState::Undef);
716 case Hexagon::VMULW: {
717 // Expand a 64-bit vector multiply into 2 32-bit scalar multiplies.
718 unsigned DstReg = MI->getOperand(0).getReg();
719 unsigned Src1Reg = MI->getOperand(1).getReg();
720 unsigned Src2Reg = MI->getOperand(2).getReg();
721 unsigned Src1SubHi = HRI.getSubReg(Src1Reg, Hexagon::subreg_hireg);
722 unsigned Src1SubLo = HRI.getSubReg(Src1Reg, Hexagon::subreg_loreg);
723 unsigned Src2SubHi = HRI.getSubReg(Src2Reg, Hexagon::subreg_hireg);
724 unsigned Src2SubLo = HRI.getSubReg(Src2Reg, Hexagon::subreg_loreg);
725 BuildMI(MBB, MI, MI->getDebugLoc(), get(Hexagon::M2_mpyi),
726 HRI.getSubReg(DstReg, Hexagon::subreg_hireg)).addReg(Src1SubHi)
728 BuildMI(MBB, MI, MI->getDebugLoc(), get(Hexagon::M2_mpyi),
729 HRI.getSubReg(DstReg, Hexagon::subreg_loreg)).addReg(Src1SubLo)
732 MRI.clearKillFlags(Src1SubHi);
733 MRI.clearKillFlags(Src1SubLo);
734 MRI.clearKillFlags(Src2SubHi);
735 MRI.clearKillFlags(Src2SubLo);
738 case Hexagon::VMULW_ACC: {
739 // Expand 64-bit vector multiply with addition into 2 scalar multiplies.
740 unsigned DstReg = MI->getOperand(0).getReg();
741 unsigned Src1Reg = MI->getOperand(1).getReg();
742 unsigned Src2Reg = MI->getOperand(2).getReg();
743 unsigned Src3Reg = MI->getOperand(3).getReg();
744 unsigned Src1SubHi = HRI.getSubReg(Src1Reg, Hexagon::subreg_hireg);
745 unsigned Src1SubLo = HRI.getSubReg(Src1Reg, Hexagon::subreg_loreg);
746 unsigned Src2SubHi = HRI.getSubReg(Src2Reg, Hexagon::subreg_hireg);
747 unsigned Src2SubLo = HRI.getSubReg(Src2Reg, Hexagon::subreg_loreg);
748 unsigned Src3SubHi = HRI.getSubReg(Src3Reg, Hexagon::subreg_hireg);
749 unsigned Src3SubLo = HRI.getSubReg(Src3Reg, Hexagon::subreg_loreg);
750 BuildMI(MBB, MI, MI->getDebugLoc(), get(Hexagon::M2_maci),
751 HRI.getSubReg(DstReg, Hexagon::subreg_hireg)).addReg(Src1SubHi)
752 .addReg(Src2SubHi).addReg(Src3SubHi);
753 BuildMI(MBB, MI, MI->getDebugLoc(), get(Hexagon::M2_maci),
754 HRI.getSubReg(DstReg, Hexagon::subreg_loreg)).addReg(Src1SubLo)
755 .addReg(Src2SubLo).addReg(Src3SubLo);
757 MRI.clearKillFlags(Src1SubHi);
758 MRI.clearKillFlags(Src1SubLo);
759 MRI.clearKillFlags(Src2SubHi);
760 MRI.clearKillFlags(Src2SubLo);
761 MRI.clearKillFlags(Src3SubHi);
762 MRI.clearKillFlags(Src3SubLo);
765 case Hexagon::MUX64_rr: {
766 const MachineOperand &Op0 = MI->getOperand(0);
767 const MachineOperand &Op1 = MI->getOperand(1);
768 const MachineOperand &Op2 = MI->getOperand(2);
769 const MachineOperand &Op3 = MI->getOperand(3);
770 unsigned Rd = Op0.getReg();
771 unsigned Pu = Op1.getReg();
772 unsigned Rs = Op2.getReg();
773 unsigned Rt = Op3.getReg();
774 DebugLoc DL = MI->getDebugLoc();
775 unsigned K1 = getKillRegState(Op1.isKill());
776 unsigned K2 = getKillRegState(Op2.isKill());
777 unsigned K3 = getKillRegState(Op3.isKill());
779 BuildMI(MBB, MI, DL, get(Hexagon::A2_tfrpt), Rd)
780 .addReg(Pu, (Rd == Rt) ? K1 : 0)
783 BuildMI(MBB, MI, DL, get(Hexagon::A2_tfrpf), Rd)
789 case Hexagon::TCRETURNi:
790 MI->setDesc(get(Hexagon::J2_jump));
792 case Hexagon::TCRETURNr:
793 MI->setDesc(get(Hexagon::J2_jumpr));
800 MachineInstr *HexagonInstrInfo::foldMemoryOperandImpl(
801 MachineFunction &MF, MachineInstr *MI, ArrayRef<unsigned> Ops,
802 MachineBasicBlock::iterator InsertPt, int FI) const {
803 // Hexagon_TODO: Implement.
807 unsigned HexagonInstrInfo::createVR(MachineFunction* MF, MVT VT) const {
809 MachineRegisterInfo &RegInfo = MF->getRegInfo();
810 const TargetRegisterClass *TRC;
812 TRC = &Hexagon::PredRegsRegClass;
813 } else if (VT == MVT::i32 || VT == MVT::f32) {
814 TRC = &Hexagon::IntRegsRegClass;
815 } else if (VT == MVT::i64 || VT == MVT::f64) {
816 TRC = &Hexagon::DoubleRegsRegClass;
818 llvm_unreachable("Cannot handle this register class");
821 unsigned NewReg = RegInfo.createVirtualRegister(TRC);
825 bool HexagonInstrInfo::isExtendable(const MachineInstr *MI) const {
826 const MCInstrDesc &MID = MI->getDesc();
827 const uint64_t F = MID.TSFlags;
828 if ((F >> HexagonII::ExtendablePos) & HexagonII::ExtendableMask)
831 // TODO: This is largely obsolete now. Will need to be removed
832 // in consecutive patches.
833 switch(MI->getOpcode()) {
834 // TFR_FI Remains a special case.
835 case Hexagon::TFR_FI:
843 // This returns true in two cases:
844 // - The OP code itself indicates that this is an extended instruction.
845 // - One of MOs has been marked with HMOTF_ConstExtended flag.
846 bool HexagonInstrInfo::isExtended(const MachineInstr *MI) const {
847 // First check if this is permanently extended op code.
848 const uint64_t F = MI->getDesc().TSFlags;
849 if ((F >> HexagonII::ExtendedPos) & HexagonII::ExtendedMask)
851 // Use MO operand flags to determine if one of MI's operands
852 // has HMOTF_ConstExtended flag set.
853 for (MachineInstr::const_mop_iterator I = MI->operands_begin(),
854 E = MI->operands_end(); I != E; ++I) {
855 if (I->getTargetFlags() && HexagonII::HMOTF_ConstExtended)
861 bool HexagonInstrInfo::isBranch (const MachineInstr *MI) const {
862 return MI->getDesc().isBranch();
865 bool HexagonInstrInfo::isNewValueInst(const MachineInstr *MI) const {
866 if (isNewValueJump(MI))
869 if (isNewValueStore(MI))
875 bool HexagonInstrInfo::isNewValue(const MachineInstr* MI) const {
876 const uint64_t F = MI->getDesc().TSFlags;
877 return ((F >> HexagonII::NewValuePos) & HexagonII::NewValueMask);
880 bool HexagonInstrInfo::isNewValue(Opcode_t Opcode) const {
881 const uint64_t F = get(Opcode).TSFlags;
882 return ((F >> HexagonII::NewValuePos) & HexagonII::NewValueMask);
885 bool HexagonInstrInfo::isSaveCalleeSavedRegsCall(const MachineInstr *MI) const {
886 return MI->getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4;
889 bool HexagonInstrInfo::isPredicable(MachineInstr *MI) const {
890 bool isPred = MI->getDesc().isPredicable();
895 const int Opc = MI->getOpcode();
898 case Hexagon::A2_tfrsi:
899 return (isOperandExtended(MI, 1) && isConstExtended(MI)) || isInt<12>(MI->getOperand(1).getImm());
901 case Hexagon::S2_storerd_io:
902 return isShiftedUInt<6,3>(MI->getOperand(1).getImm());
904 case Hexagon::S2_storeri_io:
905 case Hexagon::S2_storerinew_io:
906 return isShiftedUInt<6,2>(MI->getOperand(1).getImm());
908 case Hexagon::S2_storerh_io:
909 case Hexagon::S2_storerhnew_io:
910 return isShiftedUInt<6,1>(MI->getOperand(1).getImm());
912 case Hexagon::S2_storerb_io:
913 case Hexagon::S2_storerbnew_io:
914 return isUInt<6>(MI->getOperand(1).getImm());
916 case Hexagon::L2_loadrd_io:
917 return isShiftedUInt<6,3>(MI->getOperand(2).getImm());
919 case Hexagon::L2_loadri_io:
920 return isShiftedUInt<6,2>(MI->getOperand(2).getImm());
922 case Hexagon::L2_loadrh_io:
923 case Hexagon::L2_loadruh_io:
924 return isShiftedUInt<6,1>(MI->getOperand(2).getImm());
926 case Hexagon::L2_loadrb_io:
927 case Hexagon::L2_loadrub_io:
928 return isUInt<6>(MI->getOperand(2).getImm());
930 case Hexagon::L2_loadrd_pi:
931 return isShiftedInt<4,3>(MI->getOperand(3).getImm());
933 case Hexagon::L2_loadri_pi:
934 return isShiftedInt<4,2>(MI->getOperand(3).getImm());
936 case Hexagon::L2_loadrh_pi:
937 case Hexagon::L2_loadruh_pi:
938 return isShiftedInt<4,1>(MI->getOperand(3).getImm());
940 case Hexagon::L2_loadrb_pi:
941 case Hexagon::L2_loadrub_pi:
942 return isInt<4>(MI->getOperand(3).getImm());
944 case Hexagon::S4_storeirb_io:
945 case Hexagon::S4_storeirh_io:
946 case Hexagon::S4_storeiri_io:
947 return (isUInt<6>(MI->getOperand(1).getImm()) &&
948 isInt<6>(MI->getOperand(2).getImm()));
950 case Hexagon::A2_addi:
951 return isInt<8>(MI->getOperand(2).getImm());
953 case Hexagon::A2_aslh:
954 case Hexagon::A2_asrh:
955 case Hexagon::A2_sxtb:
956 case Hexagon::A2_sxth:
957 case Hexagon::A2_zxtb:
958 case Hexagon::A2_zxth:
965 // This function performs the following inversiones:
970 unsigned HexagonInstrInfo::getInvertedPredicatedOpcode(const int Opc) const {
972 InvPredOpcode = isPredicatedTrue(Opc) ? Hexagon::getFalsePredOpcode(Opc)
973 : Hexagon::getTruePredOpcode(Opc);
974 if (InvPredOpcode >= 0) // Valid instruction with the inverted predicate.
975 return InvPredOpcode;
978 default: llvm_unreachable("Unexpected predicated instruction");
979 case Hexagon::C2_ccombinewt:
980 return Hexagon::C2_ccombinewf;
981 case Hexagon::C2_ccombinewf:
982 return Hexagon::C2_ccombinewt;
985 case Hexagon::L4_return_t:
986 return Hexagon::L4_return_f;
987 case Hexagon::L4_return_f:
988 return Hexagon::L4_return_t;
992 // New Value Store instructions.
993 bool HexagonInstrInfo::isNewValueStore(const MachineInstr *MI) const {
994 const uint64_t F = MI->getDesc().TSFlags;
996 return ((F >> HexagonII::NVStorePos) & HexagonII::NVStoreMask);
999 bool HexagonInstrInfo::isNewValueStore(unsigned Opcode) const {
1000 const uint64_t F = get(Opcode).TSFlags;
1002 return ((F >> HexagonII::NVStorePos) & HexagonII::NVStoreMask);
1005 int HexagonInstrInfo::getCondOpcode(int Opc, bool invertPredicate) const {
1006 enum Hexagon::PredSense inPredSense;
1007 inPredSense = invertPredicate ? Hexagon::PredSense_false :
1008 Hexagon::PredSense_true;
1009 int CondOpcode = Hexagon::getPredOpcode(Opc, inPredSense);
1010 if (CondOpcode >= 0) // Valid Conditional opcode/instruction
1013 // This switch case will be removed once all the instructions have been
1014 // modified to use relation maps.
1016 case Hexagon::TFRI_f:
1017 return !invertPredicate ? Hexagon::TFRI_cPt_f :
1018 Hexagon::TFRI_cNotPt_f;
1019 case Hexagon::A2_combinew:
1020 return !invertPredicate ? Hexagon::C2_ccombinewt :
1021 Hexagon::C2_ccombinewf;
1024 case Hexagon::L4_return:
1025 return !invertPredicate ? Hexagon::L4_return_t:
1026 Hexagon::L4_return_f;
1028 llvm_unreachable("Unexpected predicable instruction");
1032 bool HexagonInstrInfo::
1033 PredicateInstruction(MachineInstr *MI,
1034 ArrayRef<MachineOperand> Cond) const {
1035 if (Cond.empty() || isEndLoopN(Cond[0].getImm())) {
1036 DEBUG(dbgs() << "\nCannot predicate:"; MI->dump(););
1039 int Opc = MI->getOpcode();
1040 assert (isPredicable(MI) && "Expected predicable instruction");
1041 bool invertJump = predOpcodeHasNot(Cond);
1043 // We have to predicate MI "in place", i.e. after this function returns,
1044 // MI will need to be transformed into a predicated form. To avoid com-
1045 // plicated manipulations with the operands (handling tied operands,
1046 // etc.), build a new temporary instruction, then overwrite MI with it.
1048 MachineBasicBlock &B = *MI->getParent();
1049 DebugLoc DL = MI->getDebugLoc();
1050 unsigned PredOpc = getCondOpcode(Opc, invertJump);
1051 MachineInstrBuilder T = BuildMI(B, MI, DL, get(PredOpc));
1052 unsigned NOp = 0, NumOps = MI->getNumOperands();
1053 while (NOp < NumOps) {
1054 MachineOperand &Op = MI->getOperand(NOp);
1055 if (!Op.isReg() || !Op.isDef() || Op.isImplicit())
1061 unsigned PredReg, PredRegPos, PredRegFlags;
1062 bool GotPredReg = getPredReg(Cond, PredReg, PredRegPos, PredRegFlags);
1065 T.addReg(PredReg, PredRegFlags);
1066 while (NOp < NumOps)
1067 T.addOperand(MI->getOperand(NOp++));
1069 MI->setDesc(get(PredOpc));
1070 while (unsigned n = MI->getNumOperands())
1071 MI->RemoveOperand(n-1);
1072 for (unsigned i = 0, n = T->getNumOperands(); i < n; ++i)
1073 MI->addOperand(T->getOperand(i));
1075 MachineBasicBlock::instr_iterator TI = &*T;
1078 MachineRegisterInfo &MRI = B.getParent()->getRegInfo();
1079 MRI.clearKillFlags(PredReg);
1087 isProfitableToIfCvt(MachineBasicBlock &MBB,
1089 unsigned ExtraPredCycles,
1090 BranchProbability Probability) const {
1097 isProfitableToIfCvt(MachineBasicBlock &TMBB,
1098 unsigned NumTCycles,
1099 unsigned ExtraTCycles,
1100 MachineBasicBlock &FMBB,
1101 unsigned NumFCycles,
1102 unsigned ExtraFCycles,
1103 BranchProbability Probability) const {
1107 // Returns true if an instruction is predicated irrespective of the predicate
1108 // sense. For example, all of the following will return true.
1109 // if (p0) R1 = add(R2, R3)
1110 // if (!p0) R1 = add(R2, R3)
1111 // if (p0.new) R1 = add(R2, R3)
1112 // if (!p0.new) R1 = add(R2, R3)
1113 bool HexagonInstrInfo::isPredicated(const MachineInstr *MI) const {
1114 const uint64_t F = MI->getDesc().TSFlags;
1116 return ((F >> HexagonII::PredicatedPos) & HexagonII::PredicatedMask);
1119 bool HexagonInstrInfo::isPredicated(unsigned Opcode) const {
1120 const uint64_t F = get(Opcode).TSFlags;
1122 return ((F >> HexagonII::PredicatedPos) & HexagonII::PredicatedMask);
1125 bool HexagonInstrInfo::isPredicatedTrue(const MachineInstr *MI) const {
1126 const uint64_t F = MI->getDesc().TSFlags;
1128 assert(isPredicated(MI));
1129 return (!((F >> HexagonII::PredicatedFalsePos) &
1130 HexagonII::PredicatedFalseMask));
1133 bool HexagonInstrInfo::isPredicatedTrue(unsigned Opcode) const {
1134 const uint64_t F = get(Opcode).TSFlags;
1136 // Make sure that the instruction is predicated.
1137 assert((F>> HexagonII::PredicatedPos) & HexagonII::PredicatedMask);
1138 return (!((F >> HexagonII::PredicatedFalsePos) &
1139 HexagonII::PredicatedFalseMask));
1142 bool HexagonInstrInfo::isPredicatedNew(const MachineInstr *MI) const {
1143 const uint64_t F = MI->getDesc().TSFlags;
1145 assert(isPredicated(MI));
1146 return ((F >> HexagonII::PredicatedNewPos) & HexagonII::PredicatedNewMask);
1149 bool HexagonInstrInfo::isPredicatedNew(unsigned Opcode) const {
1150 const uint64_t F = get(Opcode).TSFlags;
1152 assert(isPredicated(Opcode));
1153 return ((F >> HexagonII::PredicatedNewPos) & HexagonII::PredicatedNewMask);
1156 // Returns true, if a ST insn can be promoted to a new-value store.
1157 bool HexagonInstrInfo::mayBeNewStore(const MachineInstr *MI) const {
1158 const uint64_t F = MI->getDesc().TSFlags;
1160 return ((F >> HexagonII::mayNVStorePos) &
1161 HexagonII::mayNVStoreMask);
1165 HexagonInstrInfo::DefinesPredicate(MachineInstr *MI,
1166 std::vector<MachineOperand> &Pred) const {
1167 for (unsigned oper = 0; oper < MI->getNumOperands(); ++oper) {
1168 MachineOperand MO = MI->getOperand(oper);
1169 if (MO.isReg() && MO.isDef()) {
1170 const TargetRegisterClass* RC = RI.getMinimalPhysRegClass(MO.getReg());
1171 if (RC == &Hexagon::PredRegsRegClass) {
1183 SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
1184 ArrayRef<MachineOperand> Pred2) const {
1191 // We indicate that we want to reverse the branch by
1192 // inserting the reversed branching opcode.
1194 bool HexagonInstrInfo::ReverseBranchCondition(
1195 SmallVectorImpl<MachineOperand> &Cond) const {
1198 assert(Cond[0].isImm() && "First entry in the cond vector not imm-val");
1199 Opcode_t opcode = Cond[0].getImm();
1201 assert(get(opcode).isBranch() && "Should be a branching condition.");
1202 if (isEndLoopN(opcode))
1204 Opcode_t NewOpcode = getInvertedPredicatedOpcode(opcode);
1205 Cond[0].setImm(NewOpcode);
1210 bool HexagonInstrInfo::
1211 isProfitableToDupForIfCvt(MachineBasicBlock &MBB,unsigned NumInstrs,
1212 BranchProbability Probability) const {
1213 return (NumInstrs <= 4);
1216 bool HexagonInstrInfo::isDeallocRet(const MachineInstr *MI) const {
1217 switch (MI->getOpcode()) {
1218 default: return false;
1219 case Hexagon::L4_return:
1220 case Hexagon::L4_return_t:
1221 case Hexagon::L4_return_f:
1222 case Hexagon::L4_return_tnew_pnt:
1223 case Hexagon::L4_return_fnew_pnt:
1224 case Hexagon::L4_return_tnew_pt:
1225 case Hexagon::L4_return_fnew_pt:
1231 bool HexagonInstrInfo::isValidOffset(unsigned Opcode, int Offset,
1232 bool Extend) const {
1233 // This function is to check whether the "Offset" is in the correct range of
1234 // the given "Opcode". If "Offset" is not in the correct range, "A2_addi" is
1235 // inserted to calculate the final address. Due to this reason, the function
1236 // assumes that the "Offset" has correct alignment.
1237 // We used to assert if the offset was not properly aligned, however,
1238 // there are cases where a misaligned pointer recast can cause this
1239 // problem, and we need to allow for it. The front end warns of such
1240 // misaligns with respect to load size.
1243 case Hexagon::J2_loop0i:
1244 case Hexagon::J2_loop1i:
1245 return isUInt<10>(Offset);
1252 case Hexagon::L2_loadri_io:
1253 case Hexagon::S2_storeri_io:
1254 return (Offset >= Hexagon_MEMW_OFFSET_MIN) &&
1255 (Offset <= Hexagon_MEMW_OFFSET_MAX);
1257 case Hexagon::L2_loadrd_io:
1258 case Hexagon::S2_storerd_io:
1259 return (Offset >= Hexagon_MEMD_OFFSET_MIN) &&
1260 (Offset <= Hexagon_MEMD_OFFSET_MAX);
1262 case Hexagon::L2_loadrh_io:
1263 case Hexagon::L2_loadruh_io:
1264 case Hexagon::S2_storerh_io:
1265 return (Offset >= Hexagon_MEMH_OFFSET_MIN) &&
1266 (Offset <= Hexagon_MEMH_OFFSET_MAX);
1268 case Hexagon::L2_loadrb_io:
1269 case Hexagon::S2_storerb_io:
1270 case Hexagon::L2_loadrub_io:
1271 return (Offset >= Hexagon_MEMB_OFFSET_MIN) &&
1272 (Offset <= Hexagon_MEMB_OFFSET_MAX);
1274 case Hexagon::A2_addi:
1275 return (Offset >= Hexagon_ADDI_OFFSET_MIN) &&
1276 (Offset <= Hexagon_ADDI_OFFSET_MAX);
1278 case Hexagon::L4_iadd_memopw_io:
1279 case Hexagon::L4_isub_memopw_io:
1280 case Hexagon::L4_add_memopw_io:
1281 case Hexagon::L4_sub_memopw_io:
1282 case Hexagon::L4_and_memopw_io:
1283 case Hexagon::L4_or_memopw_io:
1284 return (0 <= Offset && Offset <= 255);
1286 case Hexagon::L4_iadd_memoph_io:
1287 case Hexagon::L4_isub_memoph_io:
1288 case Hexagon::L4_add_memoph_io:
1289 case Hexagon::L4_sub_memoph_io:
1290 case Hexagon::L4_and_memoph_io:
1291 case Hexagon::L4_or_memoph_io:
1292 return (0 <= Offset && Offset <= 127);
1294 case Hexagon::L4_iadd_memopb_io:
1295 case Hexagon::L4_isub_memopb_io:
1296 case Hexagon::L4_add_memopb_io:
1297 case Hexagon::L4_sub_memopb_io:
1298 case Hexagon::L4_and_memopb_io:
1299 case Hexagon::L4_or_memopb_io:
1300 return (0 <= Offset && Offset <= 63);
1302 // LDri_pred and STriw_pred are pseudo operations, so it has to take offset of
1303 // any size. Later pass knows how to handle it.
1304 case Hexagon::STriw_pred:
1305 case Hexagon::LDriw_pred:
1308 case Hexagon::TFR_FI:
1309 case Hexagon::TFR_FIA:
1310 case Hexagon::INLINEASM:
1313 case Hexagon::L2_ploadrbt_io:
1314 case Hexagon::L2_ploadrbf_io:
1315 case Hexagon::L2_ploadrubt_io:
1316 case Hexagon::L2_ploadrubf_io:
1317 case Hexagon::S2_pstorerbt_io:
1318 case Hexagon::S2_pstorerbf_io:
1319 case Hexagon::S4_storeirb_io:
1320 case Hexagon::S4_storeirbt_io:
1321 case Hexagon::S4_storeirbf_io:
1322 return isUInt<6>(Offset);
1324 case Hexagon::L2_ploadrht_io:
1325 case Hexagon::L2_ploadrhf_io:
1326 case Hexagon::L2_ploadruht_io:
1327 case Hexagon::L2_ploadruhf_io:
1328 case Hexagon::S2_pstorerht_io:
1329 case Hexagon::S2_pstorerhf_io:
1330 case Hexagon::S4_storeirh_io:
1331 case Hexagon::S4_storeirht_io:
1332 case Hexagon::S4_storeirhf_io:
1333 return isShiftedUInt<6,1>(Offset);
1335 case Hexagon::L2_ploadrit_io:
1336 case Hexagon::L2_ploadrif_io:
1337 case Hexagon::S2_pstorerit_io:
1338 case Hexagon::S2_pstorerif_io:
1339 case Hexagon::S4_storeiri_io:
1340 case Hexagon::S4_storeirit_io:
1341 case Hexagon::S4_storeirif_io:
1342 return isShiftedUInt<6,2>(Offset);
1344 case Hexagon::L2_ploadrdt_io:
1345 case Hexagon::L2_ploadrdf_io:
1346 case Hexagon::S2_pstorerdt_io:
1347 case Hexagon::S2_pstorerdf_io:
1348 return isShiftedUInt<6,3>(Offset);
1351 llvm_unreachable("No offset range is defined for this opcode. "
1352 "Please define it in the above switch statement!");
1357 // Check if the Offset is a valid auto-inc imm by Load/Store Type.
1359 bool HexagonInstrInfo::
1360 isValidAutoIncImm(const EVT VT, const int Offset) const {
1362 if (VT == MVT::i64) {
1363 return (Offset >= Hexagon_MEMD_AUTOINC_MIN &&
1364 Offset <= Hexagon_MEMD_AUTOINC_MAX &&
1365 (Offset & 0x7) == 0);
1367 if (VT == MVT::i32) {
1368 return (Offset >= Hexagon_MEMW_AUTOINC_MIN &&
1369 Offset <= Hexagon_MEMW_AUTOINC_MAX &&
1370 (Offset & 0x3) == 0);
1372 if (VT == MVT::i16) {
1373 return (Offset >= Hexagon_MEMH_AUTOINC_MIN &&
1374 Offset <= Hexagon_MEMH_AUTOINC_MAX &&
1375 (Offset & 0x1) == 0);
1377 if (VT == MVT::i8) {
1378 return (Offset >= Hexagon_MEMB_AUTOINC_MIN &&
1379 Offset <= Hexagon_MEMB_AUTOINC_MAX);
1381 llvm_unreachable("Not an auto-inc opc!");
1385 bool HexagonInstrInfo::
1386 isMemOp(const MachineInstr *MI) const {
1387 // return MI->getDesc().mayLoad() && MI->getDesc().mayStore();
1389 switch (MI->getOpcode())
1391 default: return false;
1392 case Hexagon::L4_iadd_memopw_io:
1393 case Hexagon::L4_isub_memopw_io:
1394 case Hexagon::L4_add_memopw_io:
1395 case Hexagon::L4_sub_memopw_io:
1396 case Hexagon::L4_and_memopw_io:
1397 case Hexagon::L4_or_memopw_io:
1398 case Hexagon::L4_iadd_memoph_io:
1399 case Hexagon::L4_isub_memoph_io:
1400 case Hexagon::L4_add_memoph_io:
1401 case Hexagon::L4_sub_memoph_io:
1402 case Hexagon::L4_and_memoph_io:
1403 case Hexagon::L4_or_memoph_io:
1404 case Hexagon::L4_iadd_memopb_io:
1405 case Hexagon::L4_isub_memopb_io:
1406 case Hexagon::L4_add_memopb_io:
1407 case Hexagon::L4_sub_memopb_io:
1408 case Hexagon::L4_and_memopb_io:
1409 case Hexagon::L4_or_memopb_io:
1410 case Hexagon::L4_ior_memopb_io:
1411 case Hexagon::L4_ior_memoph_io:
1412 case Hexagon::L4_ior_memopw_io:
1413 case Hexagon::L4_iand_memopb_io:
1414 case Hexagon::L4_iand_memoph_io:
1415 case Hexagon::L4_iand_memopw_io:
1422 bool HexagonInstrInfo::
1423 isSpillPredRegOp(const MachineInstr *MI) const {
1424 switch (MI->getOpcode()) {
1425 default: return false;
1426 case Hexagon::STriw_pred :
1427 case Hexagon::LDriw_pred :
1432 bool HexagonInstrInfo::isNewValueJumpCandidate(const MachineInstr *MI) const {
1433 switch (MI->getOpcode()) {
1434 default: return false;
1435 case Hexagon::C2_cmpeq:
1436 case Hexagon::C2_cmpeqi:
1437 case Hexagon::C2_cmpgt:
1438 case Hexagon::C2_cmpgti:
1439 case Hexagon::C2_cmpgtu:
1440 case Hexagon::C2_cmpgtui:
1445 bool HexagonInstrInfo::
1446 isConditionalTransfer (const MachineInstr *MI) const {
1447 switch (MI->getOpcode()) {
1448 default: return false;
1449 case Hexagon::A2_tfrt:
1450 case Hexagon::A2_tfrf:
1451 case Hexagon::C2_cmoveit:
1452 case Hexagon::C2_cmoveif:
1453 case Hexagon::A2_tfrtnew:
1454 case Hexagon::A2_tfrfnew:
1455 case Hexagon::C2_cmovenewit:
1456 case Hexagon::C2_cmovenewif:
1461 bool HexagonInstrInfo::isConditionalALU32 (const MachineInstr* MI) const {
1462 switch (MI->getOpcode())
1464 default: return false;
1465 case Hexagon::A2_paddf:
1466 case Hexagon::A2_paddfnew:
1467 case Hexagon::A2_paddt:
1468 case Hexagon::A2_paddtnew:
1469 case Hexagon::A2_pandf:
1470 case Hexagon::A2_pandfnew:
1471 case Hexagon::A2_pandt:
1472 case Hexagon::A2_pandtnew:
1473 case Hexagon::A4_paslhf:
1474 case Hexagon::A4_paslhfnew:
1475 case Hexagon::A4_paslht:
1476 case Hexagon::A4_paslhtnew:
1477 case Hexagon::A4_pasrhf:
1478 case Hexagon::A4_pasrhfnew:
1479 case Hexagon::A4_pasrht:
1480 case Hexagon::A4_pasrhtnew:
1481 case Hexagon::A2_porf:
1482 case Hexagon::A2_porfnew:
1483 case Hexagon::A2_port:
1484 case Hexagon::A2_portnew:
1485 case Hexagon::A2_psubf:
1486 case Hexagon::A2_psubfnew:
1487 case Hexagon::A2_psubt:
1488 case Hexagon::A2_psubtnew:
1489 case Hexagon::A2_pxorf:
1490 case Hexagon::A2_pxorfnew:
1491 case Hexagon::A2_pxort:
1492 case Hexagon::A2_pxortnew:
1493 case Hexagon::A4_psxthf:
1494 case Hexagon::A4_psxthfnew:
1495 case Hexagon::A4_psxtht:
1496 case Hexagon::A4_psxthtnew:
1497 case Hexagon::A4_psxtbf:
1498 case Hexagon::A4_psxtbfnew:
1499 case Hexagon::A4_psxtbt:
1500 case Hexagon::A4_psxtbtnew:
1501 case Hexagon::A4_pzxtbf:
1502 case Hexagon::A4_pzxtbfnew:
1503 case Hexagon::A4_pzxtbt:
1504 case Hexagon::A4_pzxtbtnew:
1505 case Hexagon::A4_pzxthf:
1506 case Hexagon::A4_pzxthfnew:
1507 case Hexagon::A4_pzxtht:
1508 case Hexagon::A4_pzxthtnew:
1509 case Hexagon::A2_paddit:
1510 case Hexagon::A2_paddif:
1511 case Hexagon::C2_ccombinewt:
1512 case Hexagon::C2_ccombinewf:
1517 bool HexagonInstrInfo::
1518 isConditionalLoad (const MachineInstr* MI) const {
1519 switch (MI->getOpcode())
1521 default: return false;
1522 case Hexagon::L2_ploadrdt_io :
1523 case Hexagon::L2_ploadrdf_io:
1524 case Hexagon::L2_ploadrit_io:
1525 case Hexagon::L2_ploadrif_io:
1526 case Hexagon::L2_ploadrht_io:
1527 case Hexagon::L2_ploadrhf_io:
1528 case Hexagon::L2_ploadrbt_io:
1529 case Hexagon::L2_ploadrbf_io:
1530 case Hexagon::L2_ploadruht_io:
1531 case Hexagon::L2_ploadruhf_io:
1532 case Hexagon::L2_ploadrubt_io:
1533 case Hexagon::L2_ploadrubf_io:
1534 case Hexagon::L2_ploadrdt_pi:
1535 case Hexagon::L2_ploadrdf_pi:
1536 case Hexagon::L2_ploadrit_pi:
1537 case Hexagon::L2_ploadrif_pi:
1538 case Hexagon::L2_ploadrht_pi:
1539 case Hexagon::L2_ploadrhf_pi:
1540 case Hexagon::L2_ploadrbt_pi:
1541 case Hexagon::L2_ploadrbf_pi:
1542 case Hexagon::L2_ploadruht_pi:
1543 case Hexagon::L2_ploadruhf_pi:
1544 case Hexagon::L2_ploadrubt_pi:
1545 case Hexagon::L2_ploadrubf_pi:
1546 case Hexagon::L4_ploadrdt_rr:
1547 case Hexagon::L4_ploadrdf_rr:
1548 case Hexagon::L4_ploadrbt_rr:
1549 case Hexagon::L4_ploadrbf_rr:
1550 case Hexagon::L4_ploadrubt_rr:
1551 case Hexagon::L4_ploadrubf_rr:
1552 case Hexagon::L4_ploadrht_rr:
1553 case Hexagon::L4_ploadrhf_rr:
1554 case Hexagon::L4_ploadruht_rr:
1555 case Hexagon::L4_ploadruhf_rr:
1556 case Hexagon::L4_ploadrit_rr:
1557 case Hexagon::L4_ploadrif_rr:
1562 // Returns true if an instruction is a conditional store.
1564 // Note: It doesn't include conditional new-value stores as they can't be
1565 // converted to .new predicate.
1567 // p.new NV store [ if(p0.new)memw(R0+#0)=R2.new ]
1569 // / \ (not OK. it will cause new-value store to be
1570 // / X conditional on p0.new while R2 producer is
1573 // p.new store p.old NV store
1574 // [if(p0.new)memw(R0+#0)=R2] [if(p0)memw(R0+#0)=R2.new]
1580 // [if (p0)memw(R0+#0)=R2]
1582 // The above diagram shows the steps involoved in the conversion of a predicated
1583 // store instruction to its .new predicated new-value form.
1585 // The following set of instructions further explains the scenario where
1586 // conditional new-value store becomes invalid when promoted to .new predicate
1589 // { 1) if (p0) r0 = add(r1, r2)
1590 // 2) p0 = cmp.eq(r3, #0) }
1592 // 3) if (p0) memb(r1+#0) = r0 --> this instruction can't be grouped with
1593 // the first two instructions because in instr 1, r0 is conditional on old value
1594 // of p0 but its use in instr 3 is conditional on p0 modified by instr 2 which
1595 // is not valid for new-value stores.
1596 bool HexagonInstrInfo::
1597 isConditionalStore (const MachineInstr* MI) const {
1598 switch (MI->getOpcode())
1600 default: return false;
1601 case Hexagon::S4_storeirbt_io:
1602 case Hexagon::S4_storeirbf_io:
1603 case Hexagon::S4_pstorerbt_rr:
1604 case Hexagon::S4_pstorerbf_rr:
1605 case Hexagon::S2_pstorerbt_io:
1606 case Hexagon::S2_pstorerbf_io:
1607 case Hexagon::S2_pstorerbt_pi:
1608 case Hexagon::S2_pstorerbf_pi:
1609 case Hexagon::S2_pstorerdt_io:
1610 case Hexagon::S2_pstorerdf_io:
1611 case Hexagon::S4_pstorerdt_rr:
1612 case Hexagon::S4_pstorerdf_rr:
1613 case Hexagon::S2_pstorerdt_pi:
1614 case Hexagon::S2_pstorerdf_pi:
1615 case Hexagon::S2_pstorerht_io:
1616 case Hexagon::S2_pstorerhf_io:
1617 case Hexagon::S4_storeirht_io:
1618 case Hexagon::S4_storeirhf_io:
1619 case Hexagon::S4_pstorerht_rr:
1620 case Hexagon::S4_pstorerhf_rr:
1621 case Hexagon::S2_pstorerht_pi:
1622 case Hexagon::S2_pstorerhf_pi:
1623 case Hexagon::S2_pstorerit_io:
1624 case Hexagon::S2_pstorerif_io:
1625 case Hexagon::S4_storeirit_io:
1626 case Hexagon::S4_storeirif_io:
1627 case Hexagon::S4_pstorerit_rr:
1628 case Hexagon::S4_pstorerif_rr:
1629 case Hexagon::S2_pstorerit_pi:
1630 case Hexagon::S2_pstorerif_pi:
1632 // V4 global address store before promoting to dot new.
1633 case Hexagon::S4_pstorerdt_abs:
1634 case Hexagon::S4_pstorerdf_abs:
1635 case Hexagon::S4_pstorerbt_abs:
1636 case Hexagon::S4_pstorerbf_abs:
1637 case Hexagon::S4_pstorerht_abs:
1638 case Hexagon::S4_pstorerhf_abs:
1639 case Hexagon::S4_pstorerit_abs:
1640 case Hexagon::S4_pstorerif_abs:
1643 // Predicated new value stores (i.e. if (p0) memw(..)=r0.new) are excluded
1644 // from the "Conditional Store" list. Because a predicated new value store
1645 // would NOT be promoted to a double dot new store. See diagram below:
1646 // This function returns yes for those stores that are predicated but not
1647 // yet promoted to predicate dot new instructions.
1649 // +---------------------+
1650 // /-----| if (p0) memw(..)=r0 |---------\~
1651 // || +---------------------+ ||
1652 // promote || /\ /\ || promote
1654 // \||/ demote || \||/
1656 // +-------------------------+ || +-------------------------+
1657 // | if (p0.new) memw(..)=r0 | || | if (p0) memw(..)=r0.new |
1658 // +-------------------------+ || +-------------------------+
1661 // promote || \/ NOT possible
1665 // +-----------------------------+
1666 // | if (p0.new) memw(..)=r0.new |
1667 // +-----------------------------+
1668 // Double Dot New Store
1674 bool HexagonInstrInfo::isNewValueJump(const MachineInstr *MI) const {
1675 if (isNewValue(MI) && isBranch(MI))
1680 bool HexagonInstrInfo::isNewValueJump(Opcode_t Opcode) const {
1681 return isNewValue(Opcode) && get(Opcode).isBranch() && isPredicated(Opcode);
1684 bool HexagonInstrInfo::isPostIncrement (const MachineInstr* MI) const {
1685 return (getAddrMode(MI) == HexagonII::PostInc);
1688 // Returns true, if any one of the operands is a dot new
1689 // insn, whether it is predicated dot new or register dot new.
1690 bool HexagonInstrInfo::isDotNewInst (const MachineInstr* MI) const {
1691 return (isNewValueInst(MI) ||
1692 (isPredicated(MI) && isPredicatedNew(MI)));
1695 // Returns the most basic instruction for the .new predicated instructions and
1696 // new-value stores.
1697 // For example, all of the following instructions will be converted back to the
1698 // same instruction:
1699 // 1) if (p0.new) memw(R0+#0) = R1.new --->
1700 // 2) if (p0) memw(R0+#0)= R1.new -------> if (p0) memw(R0+#0) = R1
1701 // 3) if (p0.new) memw(R0+#0) = R1 --->
1704 int HexagonInstrInfo::GetDotOldOp(const int opc) const {
1706 if (isPredicated(NewOp) && isPredicatedNew(NewOp)) { // Get predicate old form
1707 NewOp = Hexagon::getPredOldOpcode(NewOp);
1708 assert(NewOp >= 0 &&
1709 "Couldn't change predicate new instruction to its old form.");
1712 if (isNewValueStore(NewOp)) { // Convert into non-new-value format
1713 NewOp = Hexagon::getNonNVStore(NewOp);
1714 assert(NewOp >= 0 && "Couldn't change new-value store to its old form.");
1719 // Return the new value instruction for a given store.
1720 int HexagonInstrInfo::GetDotNewOp(const MachineInstr* MI) const {
1721 int NVOpcode = Hexagon::getNewValueOpcode(MI->getOpcode());
1722 if (NVOpcode >= 0) // Valid new-value store instruction.
1725 switch (MI->getOpcode()) {
1726 default: llvm_unreachable("Unknown .new type");
1727 case Hexagon::S4_storerb_ur:
1728 return Hexagon::S4_storerbnew_ur;
1730 case Hexagon::S4_storerh_ur:
1731 return Hexagon::S4_storerhnew_ur;
1733 case Hexagon::S4_storeri_ur:
1734 return Hexagon::S4_storerinew_ur;
1736 case Hexagon::S2_storerb_pci:
1737 return Hexagon::S2_storerb_pci;
1739 case Hexagon::S2_storeri_pci:
1740 return Hexagon::S2_storeri_pci;
1742 case Hexagon::S2_storerh_pci:
1743 return Hexagon::S2_storerh_pci;
1745 case Hexagon::S2_storerd_pci:
1746 return Hexagon::S2_storerd_pci;
1748 case Hexagon::S2_storerf_pci:
1749 return Hexagon::S2_storerf_pci;
1754 // Return .new predicate version for an instruction.
1755 int HexagonInstrInfo::GetDotNewPredOp(MachineInstr *MI,
1756 const MachineBranchProbabilityInfo
1759 int NewOpcode = Hexagon::getPredNewOpcode(MI->getOpcode());
1760 if (NewOpcode >= 0) // Valid predicate new instruction
1763 switch (MI->getOpcode()) {
1764 default: llvm_unreachable("Unknown .new type");
1766 case Hexagon::J2_jumpt:
1767 case Hexagon::J2_jumpf:
1768 return getDotNewPredJumpOp(MI, MBPI);
1770 case Hexagon::J2_jumprt:
1771 return Hexagon::J2_jumptnewpt;
1773 case Hexagon::J2_jumprf:
1774 return Hexagon::J2_jumprfnewpt;
1776 case Hexagon::JMPrett:
1777 return Hexagon::J2_jumprtnewpt;
1779 case Hexagon::JMPretf:
1780 return Hexagon::J2_jumprfnewpt;
1783 // Conditional combine
1784 case Hexagon::C2_ccombinewt:
1785 return Hexagon::C2_ccombinewnewt;
1786 case Hexagon::C2_ccombinewf:
1787 return Hexagon::C2_ccombinewnewf;
1792 unsigned HexagonInstrInfo::getAddrMode(const MachineInstr* MI) const {
1793 const uint64_t F = MI->getDesc().TSFlags;
1795 return((F >> HexagonII::AddrModePos) & HexagonII::AddrModeMask);
1798 /// immediateExtend - Changes the instruction in place to one using an immediate
1800 void HexagonInstrInfo::immediateExtend(MachineInstr *MI) const {
1801 assert((isExtendable(MI)||isConstExtended(MI)) &&
1802 "Instruction must be extendable");
1803 // Find which operand is extendable.
1804 short ExtOpNum = getCExtOpNum(MI);
1805 MachineOperand &MO = MI->getOperand(ExtOpNum);
1806 // This needs to be something we understand.
1807 assert((MO.isMBB() || MO.isImm()) &&
1808 "Branch with unknown extendable field type");
1809 // Mark given operand as extended.
1810 MO.addTargetFlag(HexagonII::HMOTF_ConstExtended);
1813 DFAPacketizer *HexagonInstrInfo::CreateTargetScheduleState(
1814 const TargetSubtargetInfo &STI) const {
1815 const InstrItineraryData *II = STI.getInstrItineraryData();
1816 return static_cast<const HexagonSubtarget &>(STI).createDFAPacketizer(II);
1819 bool HexagonInstrInfo::isSchedulingBoundary(const MachineInstr *MI,
1820 const MachineBasicBlock *MBB,
1821 const MachineFunction &MF) const {
1822 // Debug info is never a scheduling boundary. It's necessary to be explicit
1823 // due to the special treatment of IT instructions below, otherwise a
1824 // dbg_value followed by an IT will result in the IT instruction being
1825 // considered a scheduling hazard, which is wrong. It should be the actual
1826 // instruction preceding the dbg_value instruction(s), just like it is
1827 // when debug info is not present.
1828 if (MI->isDebugValue())
1831 // Terminators and labels can't be scheduled around.
1832 if (MI->getDesc().isTerminator() || MI->isPosition() || MI->isInlineAsm())
1838 bool HexagonInstrInfo::isConstExtended(const MachineInstr *MI) const {
1839 const uint64_t F = MI->getDesc().TSFlags;
1840 unsigned isExtended = (F >> HexagonII::ExtendedPos) & HexagonII::ExtendedMask;
1841 if (isExtended) // Instruction must be extended.
1844 unsigned isExtendable =
1845 (F >> HexagonII::ExtendablePos) & HexagonII::ExtendableMask;
1849 short ExtOpNum = getCExtOpNum(MI);
1850 const MachineOperand &MO = MI->getOperand(ExtOpNum);
1851 // Use MO operand flags to determine if MO
1852 // has the HMOTF_ConstExtended flag set.
1853 if (MO.getTargetFlags() && HexagonII::HMOTF_ConstExtended)
1855 // If this is a Machine BB address we are talking about, and it is
1856 // not marked as extended, say so.
1860 // We could be using an instruction with an extendable immediate and shoehorn
1861 // a global address into it. If it is a global address it will be constant
1862 // extended. We do this for COMBINE.
1863 // We currently only handle isGlobal() because it is the only kind of
1864 // object we are going to end up with here for now.
1865 // In the future we probably should add isSymbol(), etc.
1866 if (MO.isGlobal() || MO.isSymbol() || MO.isBlockAddress() ||
1867 MO.isJTI() || MO.isCPI())
1870 // If the extendable operand is not 'Immediate' type, the instruction should
1871 // have 'isExtended' flag set.
1872 assert(MO.isImm() && "Extendable operand must be Immediate type");
1874 int MinValue = getMinValue(MI);
1875 int MaxValue = getMaxValue(MI);
1876 int ImmValue = MO.getImm();
1878 return (ImmValue < MinValue || ImmValue > MaxValue);
1881 // Return the number of bytes required to encode the instruction.
1882 // Hexagon instructions are fixed length, 4 bytes, unless they
1883 // use a constant extender, which requires another 4 bytes.
1884 // For debug instructions and prolog labels, return 0.
1885 unsigned HexagonInstrInfo::getSize(const MachineInstr *MI) const {
1887 if (MI->isDebugValue() || MI->isPosition())
1890 unsigned Size = MI->getDesc().getSize();
1892 // Assume the default insn size in case it cannot be determined
1893 // for whatever reason.
1894 Size = HEXAGON_INSTR_SIZE;
1896 if (isConstExtended(MI) || isExtended(MI))
1897 Size += HEXAGON_INSTR_SIZE;
1902 // Returns the opcode to use when converting MI, which is a conditional jump,
1903 // into a conditional instruction which uses the .new value of the predicate.
1904 // We also use branch probabilities to add a hint to the jump.
1906 HexagonInstrInfo::getDotNewPredJumpOp(MachineInstr *MI,
1908 MachineBranchProbabilityInfo *MBPI) const {
1910 // We assume that block can have at most two successors.
1912 MachineBasicBlock *Src = MI->getParent();
1913 MachineOperand *BrTarget = &MI->getOperand(1);
1914 MachineBasicBlock *Dst = BrTarget->getMBB();
1916 const BranchProbability Prediction = MBPI->getEdgeProbability(Src, Dst);
1917 if (Prediction >= BranchProbability(1,2))
1920 switch (MI->getOpcode()) {
1921 case Hexagon::J2_jumpt:
1922 return taken ? Hexagon::J2_jumptnewpt : Hexagon::J2_jumptnew;
1923 case Hexagon::J2_jumpf:
1924 return taken ? Hexagon::J2_jumpfnewpt : Hexagon::J2_jumpfnew;
1927 llvm_unreachable("Unexpected jump instruction.");
1930 // Returns true if a particular operand is extendable for an instruction.
1931 bool HexagonInstrInfo::isOperandExtended(const MachineInstr *MI,
1932 unsigned short OperandNum) const {
1933 const uint64_t F = MI->getDesc().TSFlags;
1935 return ((F >> HexagonII::ExtendableOpPos) & HexagonII::ExtendableOpMask)
1939 // Returns Operand Index for the constant extended instruction.
1940 unsigned short HexagonInstrInfo::getCExtOpNum(const MachineInstr *MI) const {
1941 const uint64_t F = MI->getDesc().TSFlags;
1942 return ((F >> HexagonII::ExtendableOpPos) & HexagonII::ExtendableOpMask);
1945 // Returns the min value that doesn't need to be extended.
1946 int HexagonInstrInfo::getMinValue(const MachineInstr *MI) const {
1947 const uint64_t F = MI->getDesc().TSFlags;
1948 unsigned isSigned = (F >> HexagonII::ExtentSignedPos)
1949 & HexagonII::ExtentSignedMask;
1950 unsigned bits = (F >> HexagonII::ExtentBitsPos)
1951 & HexagonII::ExtentBitsMask;
1953 if (isSigned) // if value is signed
1954 return -1U << (bits - 1);
1959 // Returns the max value that doesn't need to be extended.
1960 int HexagonInstrInfo::getMaxValue(const MachineInstr *MI) const {
1961 const uint64_t F = MI->getDesc().TSFlags;
1962 unsigned isSigned = (F >> HexagonII::ExtentSignedPos)
1963 & HexagonII::ExtentSignedMask;
1964 unsigned bits = (F >> HexagonII::ExtentBitsPos)
1965 & HexagonII::ExtentBitsMask;
1967 if (isSigned) // if value is signed
1968 return ~(-1U << (bits - 1));
1970 return ~(-1U << bits);
1973 // Returns true if an instruction can be converted into a non-extended
1974 // equivalent instruction.
1975 bool HexagonInstrInfo::NonExtEquivalentExists (const MachineInstr *MI) const {
1978 // Check if the instruction has a register form that uses register in place
1979 // of the extended operand, if so return that as the non-extended form.
1980 if (Hexagon::getRegForm(MI->getOpcode()) >= 0)
1983 if (MI->getDesc().mayLoad() || MI->getDesc().mayStore()) {
1984 // Check addressing mode and retrieve non-ext equivalent instruction.
1986 switch (getAddrMode(MI)) {
1987 case HexagonII::Absolute :
1988 // Load/store with absolute addressing mode can be converted into
1989 // base+offset mode.
1990 NonExtOpcode = Hexagon::getBasedWithImmOffset(MI->getOpcode());
1992 case HexagonII::BaseImmOffset :
1993 // Load/store with base+offset addressing mode can be converted into
1994 // base+register offset addressing mode. However left shift operand should
1996 NonExtOpcode = Hexagon::getBaseWithRegOffset(MI->getOpcode());
2001 if (NonExtOpcode < 0)
2008 // Returns opcode of the non-extended equivalent instruction.
2009 short HexagonInstrInfo::getNonExtOpcode (const MachineInstr *MI) const {
2011 // Check if the instruction has a register form that uses register in place
2012 // of the extended operand, if so return that as the non-extended form.
2013 short NonExtOpcode = Hexagon::getRegForm(MI->getOpcode());
2014 if (NonExtOpcode >= 0)
2015 return NonExtOpcode;
2017 if (MI->getDesc().mayLoad() || MI->getDesc().mayStore()) {
2018 // Check addressing mode and retrieve non-ext equivalent instruction.
2019 switch (getAddrMode(MI)) {
2020 case HexagonII::Absolute :
2021 return Hexagon::getBasedWithImmOffset(MI->getOpcode());
2022 case HexagonII::BaseImmOffset :
2023 return Hexagon::getBaseWithRegOffset(MI->getOpcode());
2031 bool HexagonInstrInfo::PredOpcodeHasJMP_c(Opcode_t Opcode) const {
2032 return (Opcode == Hexagon::J2_jumpt) ||
2033 (Opcode == Hexagon::J2_jumpf) ||
2034 (Opcode == Hexagon::J2_jumptnewpt) ||
2035 (Opcode == Hexagon::J2_jumpfnewpt) ||
2036 (Opcode == Hexagon::J2_jumpt) ||
2037 (Opcode == Hexagon::J2_jumpf);
2040 bool HexagonInstrInfo::predOpcodeHasNot(ArrayRef<MachineOperand> Cond) const {
2041 if (Cond.empty() || !isPredicated(Cond[0].getImm()))
2043 return !isPredicatedTrue(Cond[0].getImm());
2046 bool HexagonInstrInfo::isEndLoopN(Opcode_t Opcode) const {
2047 return (Opcode == Hexagon::ENDLOOP0 ||
2048 Opcode == Hexagon::ENDLOOP1);
2051 bool HexagonInstrInfo::getPredReg(ArrayRef<MachineOperand> Cond,
2052 unsigned &PredReg, unsigned &PredRegPos,
2053 unsigned &PredRegFlags) const {
2056 assert(Cond.size() == 2);
2057 if (isNewValueJump(Cond[0].getImm()) || Cond[1].isMBB()) {
2058 DEBUG(dbgs() << "No predregs for new-value jumps/endloop");
2061 PredReg = Cond[1].getReg();
2063 // See IfConversion.cpp why we add RegState::Implicit | RegState::Undef
2065 if (Cond[1].isImplicit())
2066 PredRegFlags = RegState::Implicit;
2067 if (Cond[1].isUndef())
2068 PredRegFlags |= RegState::Undef;