1 //===-- HexagonInstrInfo.cpp - Hexagon Instruction Information ------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Hexagon implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "HexagonInstrInfo.h"
16 #include "HexagonRegisterInfo.h"
17 #include "HexagonSubtarget.h"
18 #include "llvm/ADT/STLExtras.h"
19 #include "llvm/ADT/SmallVector.h"
20 #include "llvm/CodeGen/DFAPacketizer.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineMemOperand.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/PseudoSourceValue.h"
26 #include "llvm/Support/MathExtras.h"
27 #define GET_INSTRINFO_CTOR
28 #define GET_INSTRMAP_INFO
29 #include "HexagonGenInstrInfo.inc"
30 #include "HexagonGenDFAPacketizer.inc"
35 /// Constants for Hexagon instructions.
37 const int Hexagon_MEMW_OFFSET_MAX = 4095;
38 const int Hexagon_MEMW_OFFSET_MIN = -4096;
39 const int Hexagon_MEMD_OFFSET_MAX = 8191;
40 const int Hexagon_MEMD_OFFSET_MIN = -8192;
41 const int Hexagon_MEMH_OFFSET_MAX = 2047;
42 const int Hexagon_MEMH_OFFSET_MIN = -2048;
43 const int Hexagon_MEMB_OFFSET_MAX = 1023;
44 const int Hexagon_MEMB_OFFSET_MIN = -1024;
45 const int Hexagon_ADDI_OFFSET_MAX = 32767;
46 const int Hexagon_ADDI_OFFSET_MIN = -32768;
47 const int Hexagon_MEMD_AUTOINC_MAX = 56;
48 const int Hexagon_MEMD_AUTOINC_MIN = -64;
49 const int Hexagon_MEMW_AUTOINC_MAX = 28;
50 const int Hexagon_MEMW_AUTOINC_MIN = -32;
51 const int Hexagon_MEMH_AUTOINC_MAX = 14;
52 const int Hexagon_MEMH_AUTOINC_MIN = -16;
53 const int Hexagon_MEMB_AUTOINC_MAX = 7;
54 const int Hexagon_MEMB_AUTOINC_MIN = -8;
57 HexagonInstrInfo::HexagonInstrInfo(HexagonSubtarget &ST)
58 : HexagonGenInstrInfo(Hexagon::ADJCALLSTACKDOWN, Hexagon::ADJCALLSTACKUP),
59 RI(ST, *this), Subtarget(ST) {
63 /// isLoadFromStackSlot - If the specified machine instruction is a direct
64 /// load from a stack slot, return the virtual or physical register number of
65 /// the destination along with the FrameIndex of the loaded stack slot. If
66 /// not, return 0. This predicate must return 0 if the instruction has
67 /// any side effects other than loading from the stack slot.
68 unsigned HexagonInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
69 int &FrameIndex) const {
72 switch (MI->getOpcode()) {
79 if (MI->getOperand(2).isFI() &&
80 MI->getOperand(1).isImm() && (MI->getOperand(1).getImm() == 0)) {
81 FrameIndex = MI->getOperand(2).getIndex();
82 return MI->getOperand(0).getReg();
90 /// isStoreToStackSlot - If the specified machine instruction is a direct
91 /// store to a stack slot, return the virtual or physical register number of
92 /// the source reg along with the FrameIndex of the loaded stack slot. If
93 /// not, return 0. This predicate must return 0 if the instruction has
94 /// any side effects other than storing to the stack slot.
95 unsigned HexagonInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
96 int &FrameIndex) const {
97 switch (MI->getOpcode()) {
103 if (MI->getOperand(2).isFI() &&
104 MI->getOperand(1).isImm() && (MI->getOperand(1).getImm() == 0)) {
105 FrameIndex = MI->getOperand(0).getIndex();
106 return MI->getOperand(2).getReg();
115 HexagonInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
116 MachineBasicBlock *FBB,
117 const SmallVectorImpl<MachineOperand> &Cond,
120 int BOpc = Hexagon::JMP;
121 int BccOpc = Hexagon::JMP_c;
123 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
126 // Check if ReverseBranchCondition has asked to reverse this branch
127 // If we want to reverse the branch an odd number of times, we want
129 if (!Cond.empty() && Cond[0].isImm() && Cond[0].getImm() == 0) {
130 BccOpc = Hexagon::JMP_cNot;
136 // Due to a bug in TailMerging/CFG Optimization, we need to add a
137 // special case handling of a predicated jump followed by an
138 // unconditional jump. If not, Tail Merging and CFG Optimization go
139 // into an infinite loop.
140 MachineBasicBlock *NewTBB, *NewFBB;
141 SmallVector<MachineOperand, 4> Cond;
142 MachineInstr *Term = MBB.getFirstTerminator();
143 if (isPredicated(Term) && !AnalyzeBranch(MBB, NewTBB, NewFBB, Cond,
145 MachineBasicBlock *NextBB =
146 llvm::next(MachineFunction::iterator(&MBB));
147 if (NewTBB == NextBB) {
148 ReverseBranchCondition(Cond);
150 return InsertBranch(MBB, TBB, 0, Cond, DL);
153 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
156 get(BccOpc)).addReg(Cond[regPos].getReg()).addMBB(TBB);
161 BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[regPos].getReg()).addMBB(TBB);
162 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
168 bool HexagonInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
169 MachineBasicBlock *&TBB,
170 MachineBasicBlock *&FBB,
171 SmallVectorImpl<MachineOperand> &Cond,
172 bool AllowModify) const {
176 // If the block has no terminators, it just falls into the block after it.
177 MachineBasicBlock::iterator I = MBB.end();
178 if (I == MBB.begin())
181 // A basic block may looks like this:
191 // It has two succs but does not have a terminator
192 // Don't know how to handle it.
197 } while (I != MBB.begin());
202 while (I->isDebugValue()) {
203 if (I == MBB.begin())
207 if (!isUnpredicatedTerminator(I))
210 // Get the last instruction in the block.
211 MachineInstr *LastInst = I;
213 // If there is only one terminator instruction, process it.
214 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
215 if (LastInst->getOpcode() == Hexagon::JMP) {
216 TBB = LastInst->getOperand(0).getMBB();
219 if (LastInst->getOpcode() == Hexagon::JMP_c) {
220 // Block ends with fall-through true condbranch.
221 TBB = LastInst->getOperand(1).getMBB();
222 Cond.push_back(LastInst->getOperand(0));
225 if (LastInst->getOpcode() == Hexagon::JMP_cNot) {
226 // Block ends with fall-through false condbranch.
227 TBB = LastInst->getOperand(1).getMBB();
228 Cond.push_back(MachineOperand::CreateImm(0));
229 Cond.push_back(LastInst->getOperand(0));
232 // Otherwise, don't know what this is.
236 // Get the instruction before it if it's a terminator.
237 MachineInstr *SecondLastInst = I;
239 // If there are three terminators, we don't know what sort of block this is.
240 if (SecondLastInst && I != MBB.begin() &&
241 isUnpredicatedTerminator(--I))
244 // If the block ends with Hexagon::BRCOND and Hexagon:JMP, handle it.
245 if (((SecondLastInst->getOpcode() == Hexagon::BRCOND) ||
246 (SecondLastInst->getOpcode() == Hexagon::JMP_c)) &&
247 LastInst->getOpcode() == Hexagon::JMP) {
248 TBB = SecondLastInst->getOperand(1).getMBB();
249 Cond.push_back(SecondLastInst->getOperand(0));
250 FBB = LastInst->getOperand(0).getMBB();
254 // If the block ends with Hexagon::JMP_cNot and Hexagon:JMP, handle it.
255 if ((SecondLastInst->getOpcode() == Hexagon::JMP_cNot) &&
256 LastInst->getOpcode() == Hexagon::JMP) {
257 TBB = SecondLastInst->getOperand(1).getMBB();
258 Cond.push_back(MachineOperand::CreateImm(0));
259 Cond.push_back(SecondLastInst->getOperand(0));
260 FBB = LastInst->getOperand(0).getMBB();
264 // If the block ends with two Hexagon:JMPs, handle it. The second one is not
265 // executed, so remove it.
266 if (SecondLastInst->getOpcode() == Hexagon::JMP &&
267 LastInst->getOpcode() == Hexagon::JMP) {
268 TBB = SecondLastInst->getOperand(0).getMBB();
271 I->eraseFromParent();
275 // Otherwise, can't handle this.
280 unsigned HexagonInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
281 int BOpc = Hexagon::JMP;
282 int BccOpc = Hexagon::JMP_c;
283 int BccOpcNot = Hexagon::JMP_cNot;
285 MachineBasicBlock::iterator I = MBB.end();
286 if (I == MBB.begin()) return 0;
288 if (I->getOpcode() != BOpc && I->getOpcode() != BccOpc &&
289 I->getOpcode() != BccOpcNot)
292 // Remove the branch.
293 I->eraseFromParent();
297 if (I == MBB.begin()) return 1;
299 if (I->getOpcode() != BccOpc && I->getOpcode() != BccOpcNot)
302 // Remove the branch.
303 I->eraseFromParent();
308 /// \brief For a comparison instruction, return the source registers in
309 /// \p SrcReg and \p SrcReg2 if having two register operands, and the value it
310 /// compares against in CmpValue. Return true if the comparison instruction
312 bool HexagonInstrInfo::analyzeCompare(const MachineInstr *MI,
313 unsigned &SrcReg, unsigned &SrcReg2,
314 int &Mask, int &Value) const {
315 unsigned Opc = MI->getOpcode();
317 // Set mask and the first source register.
319 case Hexagon::CMPEHexagon4rr:
320 case Hexagon::CMPEQri:
321 case Hexagon::CMPEQrr:
322 case Hexagon::CMPGT64rr:
323 case Hexagon::CMPGTU64rr:
324 case Hexagon::CMPGTUri:
325 case Hexagon::CMPGTUrr:
326 case Hexagon::CMPGTri:
327 case Hexagon::CMPGTrr:
328 case Hexagon::CMPLTUrr:
329 case Hexagon::CMPLTrr:
330 SrcReg = MI->getOperand(1).getReg();
333 case Hexagon::CMPbEQri_V4:
334 case Hexagon::CMPbEQrr_sbsb_V4:
335 case Hexagon::CMPbEQrr_ubub_V4:
336 case Hexagon::CMPbGTUri_V4:
337 case Hexagon::CMPbGTUrr_V4:
338 case Hexagon::CMPbGTrr_V4:
339 SrcReg = MI->getOperand(1).getReg();
342 case Hexagon::CMPhEQri_V4:
343 case Hexagon::CMPhEQrr_shl_V4:
344 case Hexagon::CMPhEQrr_xor_V4:
345 case Hexagon::CMPhGTUri_V4:
346 case Hexagon::CMPhGTUrr_V4:
347 case Hexagon::CMPhGTrr_shl_V4:
348 SrcReg = MI->getOperand(1).getReg();
353 // Set the value/second source register.
355 case Hexagon::CMPEHexagon4rr:
356 case Hexagon::CMPEQrr:
357 case Hexagon::CMPGT64rr:
358 case Hexagon::CMPGTU64rr:
359 case Hexagon::CMPGTUrr:
360 case Hexagon::CMPGTrr:
361 case Hexagon::CMPbEQrr_sbsb_V4:
362 case Hexagon::CMPbEQrr_ubub_V4:
363 case Hexagon::CMPbGTUrr_V4:
364 case Hexagon::CMPbGTrr_V4:
365 case Hexagon::CMPhEQrr_shl_V4:
366 case Hexagon::CMPhEQrr_xor_V4:
367 case Hexagon::CMPhGTUrr_V4:
368 case Hexagon::CMPhGTrr_shl_V4:
369 case Hexagon::CMPLTUrr:
370 case Hexagon::CMPLTrr:
371 SrcReg2 = MI->getOperand(2).getReg();
374 case Hexagon::CMPEQri:
375 case Hexagon::CMPGTUri:
376 case Hexagon::CMPGTri:
377 case Hexagon::CMPbEQri_V4:
378 case Hexagon::CMPbGTUri_V4:
379 case Hexagon::CMPhEQri_V4:
380 case Hexagon::CMPhGTUri_V4:
382 Value = MI->getOperand(2).getImm();
390 void HexagonInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
391 MachineBasicBlock::iterator I, DebugLoc DL,
392 unsigned DestReg, unsigned SrcReg,
393 bool KillSrc) const {
394 if (Hexagon::IntRegsRegClass.contains(SrcReg, DestReg)) {
395 BuildMI(MBB, I, DL, get(Hexagon::TFR), DestReg).addReg(SrcReg);
398 if (Hexagon::DoubleRegsRegClass.contains(SrcReg, DestReg)) {
399 BuildMI(MBB, I, DL, get(Hexagon::TFR64), DestReg).addReg(SrcReg);
402 if (Hexagon::PredRegsRegClass.contains(SrcReg, DestReg)) {
403 // Map Pd = Ps to Pd = or(Ps, Ps).
404 BuildMI(MBB, I, DL, get(Hexagon::OR_pp),
405 DestReg).addReg(SrcReg).addReg(SrcReg);
408 if (Hexagon::DoubleRegsRegClass.contains(DestReg) &&
409 Hexagon::IntRegsRegClass.contains(SrcReg)) {
410 // We can have an overlap between single and double reg: r1:0 = r0.
411 if(SrcReg == RI.getSubReg(DestReg, Hexagon::subreg_loreg)) {
413 BuildMI(MBB, I, DL, get(Hexagon::TFRI), (RI.getSubReg(DestReg,
414 Hexagon::subreg_hireg))).addImm(0);
416 // r1:0 = r1 or no overlap.
417 BuildMI(MBB, I, DL, get(Hexagon::TFR), (RI.getSubReg(DestReg,
418 Hexagon::subreg_loreg))).addReg(SrcReg);
419 BuildMI(MBB, I, DL, get(Hexagon::TFRI), (RI.getSubReg(DestReg,
420 Hexagon::subreg_hireg))).addImm(0);
424 if (Hexagon::CRRegsRegClass.contains(DestReg) &&
425 Hexagon::IntRegsRegClass.contains(SrcReg)) {
426 BuildMI(MBB, I, DL, get(Hexagon::TFCR), DestReg).addReg(SrcReg);
430 llvm_unreachable("Unimplemented");
434 void HexagonInstrInfo::
435 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
436 unsigned SrcReg, bool isKill, int FI,
437 const TargetRegisterClass *RC,
438 const TargetRegisterInfo *TRI) const {
440 DebugLoc DL = MBB.findDebugLoc(I);
441 MachineFunction &MF = *MBB.getParent();
442 MachineFrameInfo &MFI = *MF.getFrameInfo();
443 unsigned Align = MFI.getObjectAlignment(FI);
445 MachineMemOperand *MMO =
446 MF.getMachineMemOperand(
447 MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
448 MachineMemOperand::MOStore,
449 MFI.getObjectSize(FI),
452 if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {
453 BuildMI(MBB, I, DL, get(Hexagon::STriw))
454 .addFrameIndex(FI).addImm(0)
455 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
456 } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {
457 BuildMI(MBB, I, DL, get(Hexagon::STrid))
458 .addFrameIndex(FI).addImm(0)
459 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
460 } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {
461 BuildMI(MBB, I, DL, get(Hexagon::STriw_pred))
462 .addFrameIndex(FI).addImm(0)
463 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
465 llvm_unreachable("Unimplemented");
470 void HexagonInstrInfo::storeRegToAddr(
471 MachineFunction &MF, unsigned SrcReg,
473 SmallVectorImpl<MachineOperand> &Addr,
474 const TargetRegisterClass *RC,
475 SmallVectorImpl<MachineInstr*> &NewMIs) const
477 llvm_unreachable("Unimplemented");
481 void HexagonInstrInfo::
482 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
483 unsigned DestReg, int FI,
484 const TargetRegisterClass *RC,
485 const TargetRegisterInfo *TRI) const {
486 DebugLoc DL = MBB.findDebugLoc(I);
487 MachineFunction &MF = *MBB.getParent();
488 MachineFrameInfo &MFI = *MF.getFrameInfo();
489 unsigned Align = MFI.getObjectAlignment(FI);
491 MachineMemOperand *MMO =
492 MF.getMachineMemOperand(
493 MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
494 MachineMemOperand::MOLoad,
495 MFI.getObjectSize(FI),
497 if (RC == &Hexagon::IntRegsRegClass) {
498 BuildMI(MBB, I, DL, get(Hexagon::LDriw), DestReg)
499 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
500 } else if (RC == &Hexagon::DoubleRegsRegClass) {
501 BuildMI(MBB, I, DL, get(Hexagon::LDrid), DestReg)
502 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
503 } else if (RC == &Hexagon::PredRegsRegClass) {
504 BuildMI(MBB, I, DL, get(Hexagon::LDriw_pred), DestReg)
505 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
507 llvm_unreachable("Can't store this register to stack slot");
512 void HexagonInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
513 SmallVectorImpl<MachineOperand> &Addr,
514 const TargetRegisterClass *RC,
515 SmallVectorImpl<MachineInstr*> &NewMIs) const {
516 llvm_unreachable("Unimplemented");
520 MachineInstr *HexagonInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
522 const SmallVectorImpl<unsigned> &Ops,
524 // Hexagon_TODO: Implement.
529 unsigned HexagonInstrInfo::createVR(MachineFunction* MF, MVT VT) const {
531 MachineRegisterInfo &RegInfo = MF->getRegInfo();
532 const TargetRegisterClass *TRC;
534 TRC = &Hexagon::PredRegsRegClass;
535 } else if (VT == MVT::i32 || VT == MVT::f32) {
536 TRC = &Hexagon::IntRegsRegClass;
537 } else if (VT == MVT::i64 || VT == MVT::f64) {
538 TRC = &Hexagon::DoubleRegsRegClass;
540 llvm_unreachable("Cannot handle this register class");
543 unsigned NewReg = RegInfo.createVirtualRegister(TRC);
547 bool HexagonInstrInfo::isExtendable(const MachineInstr *MI) const {
548 switch(MI->getOpcode()) {
549 default: return false;
551 case Hexagon::JMP_EQriPt_nv_V4:
552 case Hexagon::JMP_EQriPnt_nv_V4:
553 case Hexagon::JMP_EQriNotPt_nv_V4:
554 case Hexagon::JMP_EQriNotPnt_nv_V4:
556 // JMP_EQri - with -1
557 case Hexagon::JMP_EQriPtneg_nv_V4:
558 case Hexagon::JMP_EQriPntneg_nv_V4:
559 case Hexagon::JMP_EQriNotPtneg_nv_V4:
560 case Hexagon::JMP_EQriNotPntneg_nv_V4:
563 case Hexagon::JMP_EQrrPt_nv_V4:
564 case Hexagon::JMP_EQrrPnt_nv_V4:
565 case Hexagon::JMP_EQrrNotPt_nv_V4:
566 case Hexagon::JMP_EQrrNotPnt_nv_V4:
569 case Hexagon::JMP_GTriPt_nv_V4:
570 case Hexagon::JMP_GTriPnt_nv_V4:
571 case Hexagon::JMP_GTriNotPt_nv_V4:
572 case Hexagon::JMP_GTriNotPnt_nv_V4:
574 // JMP_GTri - with -1
575 case Hexagon::JMP_GTriPtneg_nv_V4:
576 case Hexagon::JMP_GTriPntneg_nv_V4:
577 case Hexagon::JMP_GTriNotPtneg_nv_V4:
578 case Hexagon::JMP_GTriNotPntneg_nv_V4:
581 case Hexagon::JMP_GTrrPt_nv_V4:
582 case Hexagon::JMP_GTrrPnt_nv_V4:
583 case Hexagon::JMP_GTrrNotPt_nv_V4:
584 case Hexagon::JMP_GTrrNotPnt_nv_V4:
587 case Hexagon::JMP_GTrrdnPt_nv_V4:
588 case Hexagon::JMP_GTrrdnPnt_nv_V4:
589 case Hexagon::JMP_GTrrdnNotPt_nv_V4:
590 case Hexagon::JMP_GTrrdnNotPnt_nv_V4:
593 case Hexagon::JMP_GTUriPt_nv_V4:
594 case Hexagon::JMP_GTUriPnt_nv_V4:
595 case Hexagon::JMP_GTUriNotPt_nv_V4:
596 case Hexagon::JMP_GTUriNotPnt_nv_V4:
599 case Hexagon::JMP_GTUrrPt_nv_V4:
600 case Hexagon::JMP_GTUrrPnt_nv_V4:
601 case Hexagon::JMP_GTUrrNotPt_nv_V4:
602 case Hexagon::JMP_GTUrrNotPnt_nv_V4:
605 case Hexagon::JMP_GTUrrdnPt_nv_V4:
606 case Hexagon::JMP_GTUrrdnPnt_nv_V4:
607 case Hexagon::JMP_GTUrrdnNotPt_nv_V4:
608 case Hexagon::JMP_GTUrrdnNotPnt_nv_V4:
611 case Hexagon::TFR_FI:
616 bool HexagonInstrInfo::isExtended(const MachineInstr *MI) const {
617 switch(MI->getOpcode()) {
618 default: return false;
620 case Hexagon::JMP_EQriPt_ie_nv_V4:
621 case Hexagon::JMP_EQriPnt_ie_nv_V4:
622 case Hexagon::JMP_EQriNotPt_ie_nv_V4:
623 case Hexagon::JMP_EQriNotPnt_ie_nv_V4:
625 // JMP_EQri - with -1
626 case Hexagon::JMP_EQriPtneg_ie_nv_V4:
627 case Hexagon::JMP_EQriPntneg_ie_nv_V4:
628 case Hexagon::JMP_EQriNotPtneg_ie_nv_V4:
629 case Hexagon::JMP_EQriNotPntneg_ie_nv_V4:
632 case Hexagon::JMP_EQrrPt_ie_nv_V4:
633 case Hexagon::JMP_EQrrPnt_ie_nv_V4:
634 case Hexagon::JMP_EQrrNotPt_ie_nv_V4:
635 case Hexagon::JMP_EQrrNotPnt_ie_nv_V4:
638 case Hexagon::JMP_GTriPt_ie_nv_V4:
639 case Hexagon::JMP_GTriPnt_ie_nv_V4:
640 case Hexagon::JMP_GTriNotPt_ie_nv_V4:
641 case Hexagon::JMP_GTriNotPnt_ie_nv_V4:
643 // JMP_GTri - with -1
644 case Hexagon::JMP_GTriPtneg_ie_nv_V4:
645 case Hexagon::JMP_GTriPntneg_ie_nv_V4:
646 case Hexagon::JMP_GTriNotPtneg_ie_nv_V4:
647 case Hexagon::JMP_GTriNotPntneg_ie_nv_V4:
650 case Hexagon::JMP_GTrrPt_ie_nv_V4:
651 case Hexagon::JMP_GTrrPnt_ie_nv_V4:
652 case Hexagon::JMP_GTrrNotPt_ie_nv_V4:
653 case Hexagon::JMP_GTrrNotPnt_ie_nv_V4:
656 case Hexagon::JMP_GTrrdnPt_ie_nv_V4:
657 case Hexagon::JMP_GTrrdnPnt_ie_nv_V4:
658 case Hexagon::JMP_GTrrdnNotPt_ie_nv_V4:
659 case Hexagon::JMP_GTrrdnNotPnt_ie_nv_V4:
662 case Hexagon::JMP_GTUriPt_ie_nv_V4:
663 case Hexagon::JMP_GTUriPnt_ie_nv_V4:
664 case Hexagon::JMP_GTUriNotPt_ie_nv_V4:
665 case Hexagon::JMP_GTUriNotPnt_ie_nv_V4:
668 case Hexagon::JMP_GTUrrPt_ie_nv_V4:
669 case Hexagon::JMP_GTUrrPnt_ie_nv_V4:
670 case Hexagon::JMP_GTUrrNotPt_ie_nv_V4:
671 case Hexagon::JMP_GTUrrNotPnt_ie_nv_V4:
674 case Hexagon::JMP_GTUrrdnPt_ie_nv_V4:
675 case Hexagon::JMP_GTUrrdnPnt_ie_nv_V4:
676 case Hexagon::JMP_GTUrrdnNotPt_ie_nv_V4:
677 case Hexagon::JMP_GTUrrdnNotPnt_ie_nv_V4:
679 // V4 absolute set addressing.
680 case Hexagon::LDrid_abs_setimm_V4:
681 case Hexagon::LDriw_abs_setimm_V4:
682 case Hexagon::LDrih_abs_setimm_V4:
683 case Hexagon::LDrib_abs_setimm_V4:
684 case Hexagon::LDriuh_abs_setimm_V4:
685 case Hexagon::LDriub_abs_setimm_V4:
687 case Hexagon::STrid_abs_setimm_V4:
688 case Hexagon::STrib_abs_setimm_V4:
689 case Hexagon::STrih_abs_setimm_V4:
690 case Hexagon::STriw_abs_setimm_V4:
692 // V4 global address load.
693 case Hexagon::LDrid_GP_cPt_V4 :
694 case Hexagon::LDrid_GP_cNotPt_V4 :
695 case Hexagon::LDrid_GP_cdnPt_V4 :
696 case Hexagon::LDrid_GP_cdnNotPt_V4 :
697 case Hexagon::LDrib_GP_cPt_V4 :
698 case Hexagon::LDrib_GP_cNotPt_V4 :
699 case Hexagon::LDrib_GP_cdnPt_V4 :
700 case Hexagon::LDrib_GP_cdnNotPt_V4 :
701 case Hexagon::LDriub_GP_cPt_V4 :
702 case Hexagon::LDriub_GP_cNotPt_V4 :
703 case Hexagon::LDriub_GP_cdnPt_V4 :
704 case Hexagon::LDriub_GP_cdnNotPt_V4 :
705 case Hexagon::LDrih_GP_cPt_V4 :
706 case Hexagon::LDrih_GP_cNotPt_V4 :
707 case Hexagon::LDrih_GP_cdnPt_V4 :
708 case Hexagon::LDrih_GP_cdnNotPt_V4 :
709 case Hexagon::LDriuh_GP_cPt_V4 :
710 case Hexagon::LDriuh_GP_cNotPt_V4 :
711 case Hexagon::LDriuh_GP_cdnPt_V4 :
712 case Hexagon::LDriuh_GP_cdnNotPt_V4 :
713 case Hexagon::LDriw_GP_cPt_V4 :
714 case Hexagon::LDriw_GP_cNotPt_V4 :
715 case Hexagon::LDriw_GP_cdnPt_V4 :
716 case Hexagon::LDriw_GP_cdnNotPt_V4 :
717 case Hexagon::LDd_GP_cPt_V4 :
718 case Hexagon::LDd_GP_cNotPt_V4 :
719 case Hexagon::LDd_GP_cdnPt_V4 :
720 case Hexagon::LDd_GP_cdnNotPt_V4 :
721 case Hexagon::LDb_GP_cPt_V4 :
722 case Hexagon::LDb_GP_cNotPt_V4 :
723 case Hexagon::LDb_GP_cdnPt_V4 :
724 case Hexagon::LDb_GP_cdnNotPt_V4 :
725 case Hexagon::LDub_GP_cPt_V4 :
726 case Hexagon::LDub_GP_cNotPt_V4 :
727 case Hexagon::LDub_GP_cdnPt_V4 :
728 case Hexagon::LDub_GP_cdnNotPt_V4 :
729 case Hexagon::LDh_GP_cPt_V4 :
730 case Hexagon::LDh_GP_cNotPt_V4 :
731 case Hexagon::LDh_GP_cdnPt_V4 :
732 case Hexagon::LDh_GP_cdnNotPt_V4 :
733 case Hexagon::LDuh_GP_cPt_V4 :
734 case Hexagon::LDuh_GP_cNotPt_V4 :
735 case Hexagon::LDuh_GP_cdnPt_V4 :
736 case Hexagon::LDuh_GP_cdnNotPt_V4 :
737 case Hexagon::LDw_GP_cPt_V4 :
738 case Hexagon::LDw_GP_cNotPt_V4 :
739 case Hexagon::LDw_GP_cdnPt_V4 :
740 case Hexagon::LDw_GP_cdnNotPt_V4 :
742 // V4 global address store.
743 case Hexagon::STrid_GP_cPt_V4 :
744 case Hexagon::STrid_GP_cNotPt_V4 :
745 case Hexagon::STrid_GP_cdnPt_V4 :
746 case Hexagon::STrid_GP_cdnNotPt_V4 :
747 case Hexagon::STrib_GP_cPt_V4 :
748 case Hexagon::STrib_GP_cNotPt_V4 :
749 case Hexagon::STrib_GP_cdnPt_V4 :
750 case Hexagon::STrib_GP_cdnNotPt_V4 :
751 case Hexagon::STrih_GP_cPt_V4 :
752 case Hexagon::STrih_GP_cNotPt_V4 :
753 case Hexagon::STrih_GP_cdnPt_V4 :
754 case Hexagon::STrih_GP_cdnNotPt_V4 :
755 case Hexagon::STriw_GP_cPt_V4 :
756 case Hexagon::STriw_GP_cNotPt_V4 :
757 case Hexagon::STriw_GP_cdnPt_V4 :
758 case Hexagon::STriw_GP_cdnNotPt_V4 :
759 case Hexagon::STd_GP_cPt_V4 :
760 case Hexagon::STd_GP_cNotPt_V4 :
761 case Hexagon::STd_GP_cdnPt_V4 :
762 case Hexagon::STd_GP_cdnNotPt_V4 :
763 case Hexagon::STb_GP_cPt_V4 :
764 case Hexagon::STb_GP_cNotPt_V4 :
765 case Hexagon::STb_GP_cdnPt_V4 :
766 case Hexagon::STb_GP_cdnNotPt_V4 :
767 case Hexagon::STh_GP_cPt_V4 :
768 case Hexagon::STh_GP_cNotPt_V4 :
769 case Hexagon::STh_GP_cdnPt_V4 :
770 case Hexagon::STh_GP_cdnNotPt_V4 :
771 case Hexagon::STw_GP_cPt_V4 :
772 case Hexagon::STw_GP_cNotPt_V4 :
773 case Hexagon::STw_GP_cdnPt_V4 :
774 case Hexagon::STw_GP_cdnNotPt_V4 :
776 // V4 predicated global address new value store.
777 case Hexagon::STrib_GP_cPt_nv_V4 :
778 case Hexagon::STrib_GP_cNotPt_nv_V4 :
779 case Hexagon::STrib_GP_cdnPt_nv_V4 :
780 case Hexagon::STrib_GP_cdnNotPt_nv_V4 :
781 case Hexagon::STrih_GP_cPt_nv_V4 :
782 case Hexagon::STrih_GP_cNotPt_nv_V4 :
783 case Hexagon::STrih_GP_cdnPt_nv_V4 :
784 case Hexagon::STrih_GP_cdnNotPt_nv_V4 :
785 case Hexagon::STriw_GP_cPt_nv_V4 :
786 case Hexagon::STriw_GP_cNotPt_nv_V4 :
787 case Hexagon::STriw_GP_cdnPt_nv_V4 :
788 case Hexagon::STriw_GP_cdnNotPt_nv_V4 :
789 case Hexagon::STb_GP_cPt_nv_V4 :
790 case Hexagon::STb_GP_cNotPt_nv_V4 :
791 case Hexagon::STb_GP_cdnPt_nv_V4 :
792 case Hexagon::STb_GP_cdnNotPt_nv_V4 :
793 case Hexagon::STh_GP_cPt_nv_V4 :
794 case Hexagon::STh_GP_cNotPt_nv_V4 :
795 case Hexagon::STh_GP_cdnPt_nv_V4 :
796 case Hexagon::STh_GP_cdnNotPt_nv_V4 :
797 case Hexagon::STw_GP_cPt_nv_V4 :
798 case Hexagon::STw_GP_cNotPt_nv_V4 :
799 case Hexagon::STw_GP_cdnPt_nv_V4 :
800 case Hexagon::STw_GP_cdnNotPt_nv_V4 :
803 case Hexagon::TFR_FI_immext_V4:
806 case Hexagon::TFRI_f:
807 case Hexagon::TFRI_cPt_f:
808 case Hexagon::TFRI_cNotPt_f:
809 case Hexagon::CONST64_Float_Real:
814 bool HexagonInstrInfo::isNewValueJump(const MachineInstr *MI) const {
815 switch (MI->getOpcode()) {
816 default: return false;
818 case Hexagon::JMP_EQriPt_nv_V4:
819 case Hexagon::JMP_EQriPnt_nv_V4:
820 case Hexagon::JMP_EQriNotPt_nv_V4:
821 case Hexagon::JMP_EQriNotPnt_nv_V4:
822 case Hexagon::JMP_EQriPt_ie_nv_V4:
823 case Hexagon::JMP_EQriPnt_ie_nv_V4:
824 case Hexagon::JMP_EQriNotPt_ie_nv_V4:
825 case Hexagon::JMP_EQriNotPnt_ie_nv_V4:
827 // JMP_EQri - with -1
828 case Hexagon::JMP_EQriPtneg_nv_V4:
829 case Hexagon::JMP_EQriPntneg_nv_V4:
830 case Hexagon::JMP_EQriNotPtneg_nv_V4:
831 case Hexagon::JMP_EQriNotPntneg_nv_V4:
832 case Hexagon::JMP_EQriPtneg_ie_nv_V4:
833 case Hexagon::JMP_EQriPntneg_ie_nv_V4:
834 case Hexagon::JMP_EQriNotPtneg_ie_nv_V4:
835 case Hexagon::JMP_EQriNotPntneg_ie_nv_V4:
838 case Hexagon::JMP_EQrrPt_nv_V4:
839 case Hexagon::JMP_EQrrPnt_nv_V4:
840 case Hexagon::JMP_EQrrNotPt_nv_V4:
841 case Hexagon::JMP_EQrrNotPnt_nv_V4:
842 case Hexagon::JMP_EQrrPt_ie_nv_V4:
843 case Hexagon::JMP_EQrrPnt_ie_nv_V4:
844 case Hexagon::JMP_EQrrNotPt_ie_nv_V4:
845 case Hexagon::JMP_EQrrNotPnt_ie_nv_V4:
848 case Hexagon::JMP_GTriPt_nv_V4:
849 case Hexagon::JMP_GTriPnt_nv_V4:
850 case Hexagon::JMP_GTriNotPt_nv_V4:
851 case Hexagon::JMP_GTriNotPnt_nv_V4:
852 case Hexagon::JMP_GTriPt_ie_nv_V4:
853 case Hexagon::JMP_GTriPnt_ie_nv_V4:
854 case Hexagon::JMP_GTriNotPt_ie_nv_V4:
855 case Hexagon::JMP_GTriNotPnt_ie_nv_V4:
857 // JMP_GTri - with -1
858 case Hexagon::JMP_GTriPtneg_nv_V4:
859 case Hexagon::JMP_GTriPntneg_nv_V4:
860 case Hexagon::JMP_GTriNotPtneg_nv_V4:
861 case Hexagon::JMP_GTriNotPntneg_nv_V4:
862 case Hexagon::JMP_GTriPtneg_ie_nv_V4:
863 case Hexagon::JMP_GTriPntneg_ie_nv_V4:
864 case Hexagon::JMP_GTriNotPtneg_ie_nv_V4:
865 case Hexagon::JMP_GTriNotPntneg_ie_nv_V4:
868 case Hexagon::JMP_GTrrPt_nv_V4:
869 case Hexagon::JMP_GTrrPnt_nv_V4:
870 case Hexagon::JMP_GTrrNotPt_nv_V4:
871 case Hexagon::JMP_GTrrNotPnt_nv_V4:
872 case Hexagon::JMP_GTrrPt_ie_nv_V4:
873 case Hexagon::JMP_GTrrPnt_ie_nv_V4:
874 case Hexagon::JMP_GTrrNotPt_ie_nv_V4:
875 case Hexagon::JMP_GTrrNotPnt_ie_nv_V4:
878 case Hexagon::JMP_GTrrdnPt_nv_V4:
879 case Hexagon::JMP_GTrrdnPnt_nv_V4:
880 case Hexagon::JMP_GTrrdnNotPt_nv_V4:
881 case Hexagon::JMP_GTrrdnNotPnt_nv_V4:
882 case Hexagon::JMP_GTrrdnPt_ie_nv_V4:
883 case Hexagon::JMP_GTrrdnPnt_ie_nv_V4:
884 case Hexagon::JMP_GTrrdnNotPt_ie_nv_V4:
885 case Hexagon::JMP_GTrrdnNotPnt_ie_nv_V4:
888 case Hexagon::JMP_GTUriPt_nv_V4:
889 case Hexagon::JMP_GTUriPnt_nv_V4:
890 case Hexagon::JMP_GTUriNotPt_nv_V4:
891 case Hexagon::JMP_GTUriNotPnt_nv_V4:
892 case Hexagon::JMP_GTUriPt_ie_nv_V4:
893 case Hexagon::JMP_GTUriPnt_ie_nv_V4:
894 case Hexagon::JMP_GTUriNotPt_ie_nv_V4:
895 case Hexagon::JMP_GTUriNotPnt_ie_nv_V4:
898 case Hexagon::JMP_GTUrrPt_nv_V4:
899 case Hexagon::JMP_GTUrrPnt_nv_V4:
900 case Hexagon::JMP_GTUrrNotPt_nv_V4:
901 case Hexagon::JMP_GTUrrNotPnt_nv_V4:
902 case Hexagon::JMP_GTUrrPt_ie_nv_V4:
903 case Hexagon::JMP_GTUrrPnt_ie_nv_V4:
904 case Hexagon::JMP_GTUrrNotPt_ie_nv_V4:
905 case Hexagon::JMP_GTUrrNotPnt_ie_nv_V4:
908 case Hexagon::JMP_GTUrrdnPt_nv_V4:
909 case Hexagon::JMP_GTUrrdnPnt_nv_V4:
910 case Hexagon::JMP_GTUrrdnNotPt_nv_V4:
911 case Hexagon::JMP_GTUrrdnNotPnt_nv_V4:
912 case Hexagon::JMP_GTUrrdnPt_ie_nv_V4:
913 case Hexagon::JMP_GTUrrdnPnt_ie_nv_V4:
914 case Hexagon::JMP_GTUrrdnNotPt_ie_nv_V4:
915 case Hexagon::JMP_GTUrrdnNotPnt_ie_nv_V4:
920 unsigned HexagonInstrInfo::getImmExtForm(const MachineInstr* MI) const {
921 switch(MI->getOpcode()) {
922 default: llvm_unreachable("Unknown type of instruction.");
924 case Hexagon::JMP_EQriPt_nv_V4:
925 return Hexagon::JMP_EQriPt_ie_nv_V4;
926 case Hexagon::JMP_EQriNotPt_nv_V4:
927 return Hexagon::JMP_EQriNotPt_ie_nv_V4;
928 case Hexagon::JMP_EQriPnt_nv_V4:
929 return Hexagon::JMP_EQriPnt_ie_nv_V4;
930 case Hexagon::JMP_EQriNotPnt_nv_V4:
931 return Hexagon::JMP_EQriNotPnt_ie_nv_V4;
933 // JMP_EQri -- with -1
934 case Hexagon::JMP_EQriPtneg_nv_V4:
935 return Hexagon::JMP_EQriPtneg_ie_nv_V4;
936 case Hexagon::JMP_EQriNotPtneg_nv_V4:
937 return Hexagon::JMP_EQriNotPtneg_ie_nv_V4;
938 case Hexagon::JMP_EQriPntneg_nv_V4:
939 return Hexagon::JMP_EQriPntneg_ie_nv_V4;
940 case Hexagon::JMP_EQriNotPntneg_nv_V4:
941 return Hexagon::JMP_EQriNotPntneg_ie_nv_V4;
944 case Hexagon::JMP_EQrrPt_nv_V4:
945 return Hexagon::JMP_EQrrPt_ie_nv_V4;
946 case Hexagon::JMP_EQrrNotPt_nv_V4:
947 return Hexagon::JMP_EQrrNotPt_ie_nv_V4;
948 case Hexagon::JMP_EQrrPnt_nv_V4:
949 return Hexagon::JMP_EQrrPnt_ie_nv_V4;
950 case Hexagon::JMP_EQrrNotPnt_nv_V4:
951 return Hexagon::JMP_EQrrNotPnt_ie_nv_V4;
954 case Hexagon::JMP_GTriPt_nv_V4:
955 return Hexagon::JMP_GTriPt_ie_nv_V4;
956 case Hexagon::JMP_GTriNotPt_nv_V4:
957 return Hexagon::JMP_GTriNotPt_ie_nv_V4;
958 case Hexagon::JMP_GTriPnt_nv_V4:
959 return Hexagon::JMP_GTriPnt_ie_nv_V4;
960 case Hexagon::JMP_GTriNotPnt_nv_V4:
961 return Hexagon::JMP_GTriNotPnt_ie_nv_V4;
963 // JMP_GTri -- with -1
964 case Hexagon::JMP_GTriPtneg_nv_V4:
965 return Hexagon::JMP_GTriPtneg_ie_nv_V4;
966 case Hexagon::JMP_GTriNotPtneg_nv_V4:
967 return Hexagon::JMP_GTriNotPtneg_ie_nv_V4;
968 case Hexagon::JMP_GTriPntneg_nv_V4:
969 return Hexagon::JMP_GTriPntneg_ie_nv_V4;
970 case Hexagon::JMP_GTriNotPntneg_nv_V4:
971 return Hexagon::JMP_GTriNotPntneg_ie_nv_V4;
974 case Hexagon::JMP_GTrrPt_nv_V4:
975 return Hexagon::JMP_GTrrPt_ie_nv_V4;
976 case Hexagon::JMP_GTrrNotPt_nv_V4:
977 return Hexagon::JMP_GTrrNotPt_ie_nv_V4;
978 case Hexagon::JMP_GTrrPnt_nv_V4:
979 return Hexagon::JMP_GTrrPnt_ie_nv_V4;
980 case Hexagon::JMP_GTrrNotPnt_nv_V4:
981 return Hexagon::JMP_GTrrNotPnt_ie_nv_V4;
984 case Hexagon::JMP_GTrrdnPt_nv_V4:
985 return Hexagon::JMP_GTrrdnPt_ie_nv_V4;
986 case Hexagon::JMP_GTrrdnNotPt_nv_V4:
987 return Hexagon::JMP_GTrrdnNotPt_ie_nv_V4;
988 case Hexagon::JMP_GTrrdnPnt_nv_V4:
989 return Hexagon::JMP_GTrrdnPnt_ie_nv_V4;
990 case Hexagon::JMP_GTrrdnNotPnt_nv_V4:
991 return Hexagon::JMP_GTrrdnNotPnt_ie_nv_V4;
994 case Hexagon::JMP_GTUriPt_nv_V4:
995 return Hexagon::JMP_GTUriPt_ie_nv_V4;
996 case Hexagon::JMP_GTUriNotPt_nv_V4:
997 return Hexagon::JMP_GTUriNotPt_ie_nv_V4;
998 case Hexagon::JMP_GTUriPnt_nv_V4:
999 return Hexagon::JMP_GTUriPnt_ie_nv_V4;
1000 case Hexagon::JMP_GTUriNotPnt_nv_V4:
1001 return Hexagon::JMP_GTUriNotPnt_ie_nv_V4;
1004 case Hexagon::JMP_GTUrrPt_nv_V4:
1005 return Hexagon::JMP_GTUrrPt_ie_nv_V4;
1006 case Hexagon::JMP_GTUrrNotPt_nv_V4:
1007 return Hexagon::JMP_GTUrrNotPt_ie_nv_V4;
1008 case Hexagon::JMP_GTUrrPnt_nv_V4:
1009 return Hexagon::JMP_GTUrrPnt_ie_nv_V4;
1010 case Hexagon::JMP_GTUrrNotPnt_nv_V4:
1011 return Hexagon::JMP_GTUrrNotPnt_ie_nv_V4;
1014 case Hexagon::JMP_GTUrrdnPt_nv_V4:
1015 return Hexagon::JMP_GTUrrdnPt_ie_nv_V4;
1016 case Hexagon::JMP_GTUrrdnNotPt_nv_V4:
1017 return Hexagon::JMP_GTUrrdnNotPt_ie_nv_V4;
1018 case Hexagon::JMP_GTUrrdnPnt_nv_V4:
1019 return Hexagon::JMP_GTUrrdnPnt_ie_nv_V4;
1020 case Hexagon::JMP_GTUrrdnNotPnt_nv_V4:
1021 return Hexagon::JMP_GTUrrdnNotPnt_ie_nv_V4;
1023 case Hexagon::TFR_FI:
1024 return Hexagon::TFR_FI_immext_V4;
1026 case Hexagon::MEMw_ADDi_indexed_MEM_V4 :
1027 case Hexagon::MEMw_SUBi_indexed_MEM_V4 :
1028 case Hexagon::MEMw_ADDr_indexed_MEM_V4 :
1029 case Hexagon::MEMw_SUBr_indexed_MEM_V4 :
1030 case Hexagon::MEMw_ANDr_indexed_MEM_V4 :
1031 case Hexagon::MEMw_ORr_indexed_MEM_V4 :
1032 case Hexagon::MEMw_ADDi_MEM_V4 :
1033 case Hexagon::MEMw_SUBi_MEM_V4 :
1034 case Hexagon::MEMw_ADDr_MEM_V4 :
1035 case Hexagon::MEMw_SUBr_MEM_V4 :
1036 case Hexagon::MEMw_ANDr_MEM_V4 :
1037 case Hexagon::MEMw_ORr_MEM_V4 :
1038 case Hexagon::MEMh_ADDi_indexed_MEM_V4 :
1039 case Hexagon::MEMh_SUBi_indexed_MEM_V4 :
1040 case Hexagon::MEMh_ADDr_indexed_MEM_V4 :
1041 case Hexagon::MEMh_SUBr_indexed_MEM_V4 :
1042 case Hexagon::MEMh_ANDr_indexed_MEM_V4 :
1043 case Hexagon::MEMh_ORr_indexed_MEM_V4 :
1044 case Hexagon::MEMh_ADDi_MEM_V4 :
1045 case Hexagon::MEMh_SUBi_MEM_V4 :
1046 case Hexagon::MEMh_ADDr_MEM_V4 :
1047 case Hexagon::MEMh_SUBr_MEM_V4 :
1048 case Hexagon::MEMh_ANDr_MEM_V4 :
1049 case Hexagon::MEMh_ORr_MEM_V4 :
1050 case Hexagon::MEMb_ADDi_indexed_MEM_V4 :
1051 case Hexagon::MEMb_SUBi_indexed_MEM_V4 :
1052 case Hexagon::MEMb_ADDr_indexed_MEM_V4 :
1053 case Hexagon::MEMb_SUBr_indexed_MEM_V4 :
1054 case Hexagon::MEMb_ANDr_indexed_MEM_V4 :
1055 case Hexagon::MEMb_ORr_indexed_MEM_V4 :
1056 case Hexagon::MEMb_ADDi_MEM_V4 :
1057 case Hexagon::MEMb_SUBi_MEM_V4 :
1058 case Hexagon::MEMb_ADDr_MEM_V4 :
1059 case Hexagon::MEMb_SUBr_MEM_V4 :
1060 case Hexagon::MEMb_ANDr_MEM_V4 :
1061 case Hexagon::MEMb_ORr_MEM_V4 :
1062 llvm_unreachable("Needs implementing.");
1066 unsigned HexagonInstrInfo::getNormalBranchForm(const MachineInstr* MI) const {
1067 switch(MI->getOpcode()) {
1068 default: llvm_unreachable("Unknown type of jump instruction.");
1070 case Hexagon::JMP_EQriPt_ie_nv_V4:
1071 return Hexagon::JMP_EQriPt_nv_V4;
1072 case Hexagon::JMP_EQriNotPt_ie_nv_V4:
1073 return Hexagon::JMP_EQriNotPt_nv_V4;
1074 case Hexagon::JMP_EQriPnt_ie_nv_V4:
1075 return Hexagon::JMP_EQriPnt_nv_V4;
1076 case Hexagon::JMP_EQriNotPnt_ie_nv_V4:
1077 return Hexagon::JMP_EQriNotPnt_nv_V4;
1079 // JMP_EQri -- with -1
1080 case Hexagon::JMP_EQriPtneg_ie_nv_V4:
1081 return Hexagon::JMP_EQriPtneg_nv_V4;
1082 case Hexagon::JMP_EQriNotPtneg_ie_nv_V4:
1083 return Hexagon::JMP_EQriNotPtneg_nv_V4;
1084 case Hexagon::JMP_EQriPntneg_ie_nv_V4:
1085 return Hexagon::JMP_EQriPntneg_nv_V4;
1086 case Hexagon::JMP_EQriNotPntneg_ie_nv_V4:
1087 return Hexagon::JMP_EQriNotPntneg_nv_V4;
1090 case Hexagon::JMP_EQrrPt_ie_nv_V4:
1091 return Hexagon::JMP_EQrrPt_nv_V4;
1092 case Hexagon::JMP_EQrrNotPt_ie_nv_V4:
1093 return Hexagon::JMP_EQrrNotPt_nv_V4;
1094 case Hexagon::JMP_EQrrPnt_ie_nv_V4:
1095 return Hexagon::JMP_EQrrPnt_nv_V4;
1096 case Hexagon::JMP_EQrrNotPnt_ie_nv_V4:
1097 return Hexagon::JMP_EQrrNotPnt_nv_V4;
1100 case Hexagon::JMP_GTriPt_ie_nv_V4:
1101 return Hexagon::JMP_GTriPt_nv_V4;
1102 case Hexagon::JMP_GTriNotPt_ie_nv_V4:
1103 return Hexagon::JMP_GTriNotPt_nv_V4;
1104 case Hexagon::JMP_GTriPnt_ie_nv_V4:
1105 return Hexagon::JMP_GTriPnt_nv_V4;
1106 case Hexagon::JMP_GTriNotPnt_ie_nv_V4:
1107 return Hexagon::JMP_GTriNotPnt_nv_V4;
1109 // JMP_GTri -- with -1
1110 case Hexagon::JMP_GTriPtneg_ie_nv_V4:
1111 return Hexagon::JMP_GTriPtneg_nv_V4;
1112 case Hexagon::JMP_GTriNotPtneg_ie_nv_V4:
1113 return Hexagon::JMP_GTriNotPtneg_nv_V4;
1114 case Hexagon::JMP_GTriPntneg_ie_nv_V4:
1115 return Hexagon::JMP_GTriPntneg_nv_V4;
1116 case Hexagon::JMP_GTriNotPntneg_ie_nv_V4:
1117 return Hexagon::JMP_GTriNotPntneg_nv_V4;
1120 case Hexagon::JMP_GTrrPt_ie_nv_V4:
1121 return Hexagon::JMP_GTrrPt_nv_V4;
1122 case Hexagon::JMP_GTrrNotPt_ie_nv_V4:
1123 return Hexagon::JMP_GTrrNotPt_nv_V4;
1124 case Hexagon::JMP_GTrrPnt_ie_nv_V4:
1125 return Hexagon::JMP_GTrrPnt_nv_V4;
1126 case Hexagon::JMP_GTrrNotPnt_ie_nv_V4:
1127 return Hexagon::JMP_GTrrNotPnt_nv_V4;
1130 case Hexagon::JMP_GTrrdnPt_ie_nv_V4:
1131 return Hexagon::JMP_GTrrdnPt_nv_V4;
1132 case Hexagon::JMP_GTrrdnNotPt_ie_nv_V4:
1133 return Hexagon::JMP_GTrrdnNotPt_nv_V4;
1134 case Hexagon::JMP_GTrrdnPnt_ie_nv_V4:
1135 return Hexagon::JMP_GTrrdnPnt_nv_V4;
1136 case Hexagon::JMP_GTrrdnNotPnt_ie_nv_V4:
1137 return Hexagon::JMP_GTrrdnNotPnt_nv_V4;
1140 case Hexagon::JMP_GTUriPt_ie_nv_V4:
1141 return Hexagon::JMP_GTUriPt_nv_V4;
1142 case Hexagon::JMP_GTUriNotPt_ie_nv_V4:
1143 return Hexagon::JMP_GTUriNotPt_nv_V4;
1144 case Hexagon::JMP_GTUriPnt_ie_nv_V4:
1145 return Hexagon::JMP_GTUriPnt_nv_V4;
1146 case Hexagon::JMP_GTUriNotPnt_ie_nv_V4:
1147 return Hexagon::JMP_GTUriNotPnt_nv_V4;
1150 case Hexagon::JMP_GTUrrPt_ie_nv_V4:
1151 return Hexagon::JMP_GTUrrPt_nv_V4;
1152 case Hexagon::JMP_GTUrrNotPt_ie_nv_V4:
1153 return Hexagon::JMP_GTUrrNotPt_nv_V4;
1154 case Hexagon::JMP_GTUrrPnt_ie_nv_V4:
1155 return Hexagon::JMP_GTUrrPnt_nv_V4;
1156 case Hexagon::JMP_GTUrrNotPnt_ie_nv_V4:
1157 return Hexagon::JMP_GTUrrNotPnt_nv_V4;
1160 case Hexagon::JMP_GTUrrdnPt_ie_nv_V4:
1161 return Hexagon::JMP_GTUrrdnPt_nv_V4;
1162 case Hexagon::JMP_GTUrrdnNotPt_ie_nv_V4:
1163 return Hexagon::JMP_GTUrrdnNotPt_nv_V4;
1164 case Hexagon::JMP_GTUrrdnPnt_ie_nv_V4:
1165 return Hexagon::JMP_GTUrrdnPnt_nv_V4;
1166 case Hexagon::JMP_GTUrrdnNotPnt_ie_nv_V4:
1167 return Hexagon::JMP_GTUrrdnNotPnt_nv_V4;
1172 bool HexagonInstrInfo::isNewValueStore(const MachineInstr *MI) const {
1173 switch (MI->getOpcode()) {
1174 default: return false;
1176 case Hexagon::STrib_nv_V4:
1177 case Hexagon::STrib_indexed_nv_V4:
1178 case Hexagon::STrib_indexed_shl_nv_V4:
1179 case Hexagon::STrib_shl_nv_V4:
1180 case Hexagon::STrib_GP_nv_V4:
1181 case Hexagon::STb_GP_nv_V4:
1182 case Hexagon::POST_STbri_nv_V4:
1183 case Hexagon::STrib_cPt_nv_V4:
1184 case Hexagon::STrib_cdnPt_nv_V4:
1185 case Hexagon::STrib_cNotPt_nv_V4:
1186 case Hexagon::STrib_cdnNotPt_nv_V4:
1187 case Hexagon::STrib_indexed_cPt_nv_V4:
1188 case Hexagon::STrib_indexed_cdnPt_nv_V4:
1189 case Hexagon::STrib_indexed_cNotPt_nv_V4:
1190 case Hexagon::STrib_indexed_cdnNotPt_nv_V4:
1191 case Hexagon::STrib_indexed_shl_cPt_nv_V4:
1192 case Hexagon::STrib_indexed_shl_cdnPt_nv_V4:
1193 case Hexagon::STrib_indexed_shl_cNotPt_nv_V4:
1194 case Hexagon::STrib_indexed_shl_cdnNotPt_nv_V4:
1195 case Hexagon::POST_STbri_cPt_nv_V4:
1196 case Hexagon::POST_STbri_cdnPt_nv_V4:
1197 case Hexagon::POST_STbri_cNotPt_nv_V4:
1198 case Hexagon::POST_STbri_cdnNotPt_nv_V4:
1199 case Hexagon::STb_GP_cPt_nv_V4:
1200 case Hexagon::STb_GP_cNotPt_nv_V4:
1201 case Hexagon::STb_GP_cdnPt_nv_V4:
1202 case Hexagon::STb_GP_cdnNotPt_nv_V4:
1203 case Hexagon::STrib_GP_cPt_nv_V4:
1204 case Hexagon::STrib_GP_cNotPt_nv_V4:
1205 case Hexagon::STrib_GP_cdnPt_nv_V4:
1206 case Hexagon::STrib_GP_cdnNotPt_nv_V4:
1207 case Hexagon::STrib_abs_nv_V4:
1208 case Hexagon::STrib_abs_cPt_nv_V4:
1209 case Hexagon::STrib_abs_cdnPt_nv_V4:
1210 case Hexagon::STrib_abs_cNotPt_nv_V4:
1211 case Hexagon::STrib_abs_cdnNotPt_nv_V4:
1212 case Hexagon::STrib_imm_abs_nv_V4:
1213 case Hexagon::STrib_imm_abs_cPt_nv_V4:
1214 case Hexagon::STrib_imm_abs_cdnPt_nv_V4:
1215 case Hexagon::STrib_imm_abs_cNotPt_nv_V4:
1216 case Hexagon::STrib_imm_abs_cdnNotPt_nv_V4:
1219 case Hexagon::STrih_nv_V4:
1220 case Hexagon::STrih_indexed_nv_V4:
1221 case Hexagon::STrih_indexed_shl_nv_V4:
1222 case Hexagon::STrih_shl_nv_V4:
1223 case Hexagon::STrih_GP_nv_V4:
1224 case Hexagon::STh_GP_nv_V4:
1225 case Hexagon::POST_SThri_nv_V4:
1226 case Hexagon::STrih_cPt_nv_V4:
1227 case Hexagon::STrih_cdnPt_nv_V4:
1228 case Hexagon::STrih_cNotPt_nv_V4:
1229 case Hexagon::STrih_cdnNotPt_nv_V4:
1230 case Hexagon::STrih_indexed_cPt_nv_V4:
1231 case Hexagon::STrih_indexed_cdnPt_nv_V4:
1232 case Hexagon::STrih_indexed_cNotPt_nv_V4:
1233 case Hexagon::STrih_indexed_cdnNotPt_nv_V4:
1234 case Hexagon::STrih_indexed_shl_cPt_nv_V4:
1235 case Hexagon::STrih_indexed_shl_cdnPt_nv_V4:
1236 case Hexagon::STrih_indexed_shl_cNotPt_nv_V4:
1237 case Hexagon::STrih_indexed_shl_cdnNotPt_nv_V4:
1238 case Hexagon::POST_SThri_cPt_nv_V4:
1239 case Hexagon::POST_SThri_cdnPt_nv_V4:
1240 case Hexagon::POST_SThri_cNotPt_nv_V4:
1241 case Hexagon::POST_SThri_cdnNotPt_nv_V4:
1242 case Hexagon::STh_GP_cPt_nv_V4:
1243 case Hexagon::STh_GP_cNotPt_nv_V4:
1244 case Hexagon::STh_GP_cdnPt_nv_V4:
1245 case Hexagon::STh_GP_cdnNotPt_nv_V4:
1246 case Hexagon::STrih_GP_cPt_nv_V4:
1247 case Hexagon::STrih_GP_cNotPt_nv_V4:
1248 case Hexagon::STrih_GP_cdnPt_nv_V4:
1249 case Hexagon::STrih_GP_cdnNotPt_nv_V4:
1250 case Hexagon::STrih_abs_nv_V4:
1251 case Hexagon::STrih_abs_cPt_nv_V4:
1252 case Hexagon::STrih_abs_cdnPt_nv_V4:
1253 case Hexagon::STrih_abs_cNotPt_nv_V4:
1254 case Hexagon::STrih_abs_cdnNotPt_nv_V4:
1255 case Hexagon::STrih_imm_abs_nv_V4:
1256 case Hexagon::STrih_imm_abs_cPt_nv_V4:
1257 case Hexagon::STrih_imm_abs_cdnPt_nv_V4:
1258 case Hexagon::STrih_imm_abs_cNotPt_nv_V4:
1259 case Hexagon::STrih_imm_abs_cdnNotPt_nv_V4:
1262 case Hexagon::STriw_nv_V4:
1263 case Hexagon::STriw_indexed_nv_V4:
1264 case Hexagon::STriw_indexed_shl_nv_V4:
1265 case Hexagon::STriw_shl_nv_V4:
1266 case Hexagon::STriw_GP_nv_V4:
1267 case Hexagon::STw_GP_nv_V4:
1268 case Hexagon::POST_STwri_nv_V4:
1269 case Hexagon::STriw_cPt_nv_V4:
1270 case Hexagon::STriw_cdnPt_nv_V4:
1271 case Hexagon::STriw_cNotPt_nv_V4:
1272 case Hexagon::STriw_cdnNotPt_nv_V4:
1273 case Hexagon::STriw_indexed_cPt_nv_V4:
1274 case Hexagon::STriw_indexed_cdnPt_nv_V4:
1275 case Hexagon::STriw_indexed_cNotPt_nv_V4:
1276 case Hexagon::STriw_indexed_cdnNotPt_nv_V4:
1277 case Hexagon::STriw_indexed_shl_cPt_nv_V4:
1278 case Hexagon::STriw_indexed_shl_cdnPt_nv_V4:
1279 case Hexagon::STriw_indexed_shl_cNotPt_nv_V4:
1280 case Hexagon::STriw_indexed_shl_cdnNotPt_nv_V4:
1281 case Hexagon::POST_STwri_cPt_nv_V4:
1282 case Hexagon::POST_STwri_cdnPt_nv_V4:
1283 case Hexagon::POST_STwri_cNotPt_nv_V4:
1284 case Hexagon::POST_STwri_cdnNotPt_nv_V4:
1285 case Hexagon::STw_GP_cPt_nv_V4:
1286 case Hexagon::STw_GP_cNotPt_nv_V4:
1287 case Hexagon::STw_GP_cdnPt_nv_V4:
1288 case Hexagon::STw_GP_cdnNotPt_nv_V4:
1289 case Hexagon::STriw_GP_cPt_nv_V4:
1290 case Hexagon::STriw_GP_cNotPt_nv_V4:
1291 case Hexagon::STriw_GP_cdnPt_nv_V4:
1292 case Hexagon::STriw_GP_cdnNotPt_nv_V4:
1293 case Hexagon::STriw_abs_nv_V4:
1294 case Hexagon::STriw_abs_cPt_nv_V4:
1295 case Hexagon::STriw_abs_cdnPt_nv_V4:
1296 case Hexagon::STriw_abs_cNotPt_nv_V4:
1297 case Hexagon::STriw_abs_cdnNotPt_nv_V4:
1298 case Hexagon::STriw_imm_abs_nv_V4:
1299 case Hexagon::STriw_imm_abs_cPt_nv_V4:
1300 case Hexagon::STriw_imm_abs_cdnPt_nv_V4:
1301 case Hexagon::STriw_imm_abs_cNotPt_nv_V4:
1302 case Hexagon::STriw_imm_abs_cdnNotPt_nv_V4:
1307 bool HexagonInstrInfo::isPostIncrement (const MachineInstr* MI) const {
1308 switch (MI->getOpcode())
1310 default: return false;
1312 case Hexagon::POST_LDrib:
1313 case Hexagon::POST_LDrib_cPt:
1314 case Hexagon::POST_LDrib_cNotPt:
1315 case Hexagon::POST_LDrib_cdnPt_V4:
1316 case Hexagon::POST_LDrib_cdnNotPt_V4:
1318 // Load unsigned byte
1319 case Hexagon::POST_LDriub:
1320 case Hexagon::POST_LDriub_cPt:
1321 case Hexagon::POST_LDriub_cNotPt:
1322 case Hexagon::POST_LDriub_cdnPt_V4:
1323 case Hexagon::POST_LDriub_cdnNotPt_V4:
1326 case Hexagon::POST_LDrih:
1327 case Hexagon::POST_LDrih_cPt:
1328 case Hexagon::POST_LDrih_cNotPt:
1329 case Hexagon::POST_LDrih_cdnPt_V4:
1330 case Hexagon::POST_LDrih_cdnNotPt_V4:
1332 // Load unsigned halfword
1333 case Hexagon::POST_LDriuh:
1334 case Hexagon::POST_LDriuh_cPt:
1335 case Hexagon::POST_LDriuh_cNotPt:
1336 case Hexagon::POST_LDriuh_cdnPt_V4:
1337 case Hexagon::POST_LDriuh_cdnNotPt_V4:
1340 case Hexagon::POST_LDriw:
1341 case Hexagon::POST_LDriw_cPt:
1342 case Hexagon::POST_LDriw_cNotPt:
1343 case Hexagon::POST_LDriw_cdnPt_V4:
1344 case Hexagon::POST_LDriw_cdnNotPt_V4:
1347 case Hexagon::POST_LDrid:
1348 case Hexagon::POST_LDrid_cPt:
1349 case Hexagon::POST_LDrid_cNotPt:
1350 case Hexagon::POST_LDrid_cdnPt_V4:
1351 case Hexagon::POST_LDrid_cdnNotPt_V4:
1354 case Hexagon::POST_STbri:
1355 case Hexagon::POST_STbri_cPt:
1356 case Hexagon::POST_STbri_cNotPt:
1357 case Hexagon::POST_STbri_cdnPt_V4:
1358 case Hexagon::POST_STbri_cdnNotPt_V4:
1361 case Hexagon::POST_SThri:
1362 case Hexagon::POST_SThri_cPt:
1363 case Hexagon::POST_SThri_cNotPt:
1364 case Hexagon::POST_SThri_cdnPt_V4:
1365 case Hexagon::POST_SThri_cdnNotPt_V4:
1368 case Hexagon::POST_STwri:
1369 case Hexagon::POST_STwri_cPt:
1370 case Hexagon::POST_STwri_cNotPt:
1371 case Hexagon::POST_STwri_cdnPt_V4:
1372 case Hexagon::POST_STwri_cdnNotPt_V4:
1374 // Store double word
1375 case Hexagon::POST_STdri:
1376 case Hexagon::POST_STdri_cPt:
1377 case Hexagon::POST_STdri_cNotPt:
1378 case Hexagon::POST_STdri_cdnPt_V4:
1379 case Hexagon::POST_STdri_cdnNotPt_V4:
1384 bool HexagonInstrInfo::isSaveCalleeSavedRegsCall(const MachineInstr *MI) const {
1385 return MI->getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4;
1388 bool HexagonInstrInfo::isPredicable(MachineInstr *MI) const {
1389 bool isPred = MI->getDesc().isPredicable();
1394 const int Opc = MI->getOpcode();
1398 return isInt<12>(MI->getOperand(1).getImm());
1400 case Hexagon::STrid:
1401 case Hexagon::STrid_indexed:
1402 return isShiftedUInt<6,3>(MI->getOperand(1).getImm());
1404 case Hexagon::STriw:
1405 case Hexagon::STriw_indexed:
1406 case Hexagon::STriw_nv_V4:
1407 return isShiftedUInt<6,2>(MI->getOperand(1).getImm());
1409 case Hexagon::STrih:
1410 case Hexagon::STrih_indexed:
1411 case Hexagon::STrih_nv_V4:
1412 return isShiftedUInt<6,1>(MI->getOperand(1).getImm());
1414 case Hexagon::STrib:
1415 case Hexagon::STrib_indexed:
1416 case Hexagon::STrib_nv_V4:
1417 return isUInt<6>(MI->getOperand(1).getImm());
1419 case Hexagon::LDrid:
1420 case Hexagon::LDrid_indexed:
1421 return isShiftedUInt<6,3>(MI->getOperand(2).getImm());
1423 case Hexagon::LDriw:
1424 case Hexagon::LDriw_indexed:
1425 return isShiftedUInt<6,2>(MI->getOperand(2).getImm());
1427 case Hexagon::LDrih:
1428 case Hexagon::LDriuh:
1429 case Hexagon::LDrih_indexed:
1430 case Hexagon::LDriuh_indexed:
1431 return isShiftedUInt<6,1>(MI->getOperand(2).getImm());
1433 case Hexagon::LDrib:
1434 case Hexagon::LDriub:
1435 case Hexagon::LDrib_indexed:
1436 case Hexagon::LDriub_indexed:
1437 return isUInt<6>(MI->getOperand(2).getImm());
1439 case Hexagon::POST_LDrid:
1440 return isShiftedInt<4,3>(MI->getOperand(3).getImm());
1442 case Hexagon::POST_LDriw:
1443 return isShiftedInt<4,2>(MI->getOperand(3).getImm());
1445 case Hexagon::POST_LDrih:
1446 case Hexagon::POST_LDriuh:
1447 return isShiftedInt<4,1>(MI->getOperand(3).getImm());
1449 case Hexagon::POST_LDrib:
1450 case Hexagon::POST_LDriub:
1451 return isInt<4>(MI->getOperand(3).getImm());
1453 case Hexagon::STrib_imm_V4:
1454 case Hexagon::STrih_imm_V4:
1455 case Hexagon::STriw_imm_V4:
1456 return (isUInt<6>(MI->getOperand(1).getImm()) &&
1457 isInt<6>(MI->getOperand(2).getImm()));
1459 case Hexagon::ADD_ri:
1460 return isInt<8>(MI->getOperand(2).getImm());
1468 return Subtarget.hasV4TOps();
1477 // This function performs the following inversiones:
1482 // however, these inversiones are NOT included:
1484 // cdnPt -X-> cdnNotPt
1485 // cdnNotPt -X-> cdnPt
1486 // cPt_nv -X-> cNotPt_nv (new value stores)
1487 // cNotPt_nv -X-> cPt_nv (new value stores)
1489 // because only the following transformations are allowed:
1491 // cNotPt ---> cdnNotPt
1493 // cNotPt ---> cNotPt_nv
1495 unsigned HexagonInstrInfo::getInvertedPredicatedOpcode(const int Opc) const {
1497 default: llvm_unreachable("Unexpected predicated instruction");
1498 case Hexagon::TFR_cPt:
1499 return Hexagon::TFR_cNotPt;
1500 case Hexagon::TFR_cNotPt:
1501 return Hexagon::TFR_cPt;
1503 case Hexagon::TFRI_cPt:
1504 return Hexagon::TFRI_cNotPt;
1505 case Hexagon::TFRI_cNotPt:
1506 return Hexagon::TFRI_cPt;
1508 case Hexagon::JMP_c:
1509 return Hexagon::JMP_cNot;
1510 case Hexagon::JMP_cNot:
1511 return Hexagon::JMP_c;
1513 case Hexagon::ADD_ri_cPt:
1514 return Hexagon::ADD_ri_cNotPt;
1515 case Hexagon::ADD_ri_cNotPt:
1516 return Hexagon::ADD_ri_cPt;
1518 case Hexagon::ADD_rr_cPt:
1519 return Hexagon::ADD_rr_cNotPt;
1520 case Hexagon::ADD_rr_cNotPt:
1521 return Hexagon::ADD_rr_cPt;
1523 case Hexagon::XOR_rr_cPt:
1524 return Hexagon::XOR_rr_cNotPt;
1525 case Hexagon::XOR_rr_cNotPt:
1526 return Hexagon::XOR_rr_cPt;
1528 case Hexagon::AND_rr_cPt:
1529 return Hexagon::AND_rr_cNotPt;
1530 case Hexagon::AND_rr_cNotPt:
1531 return Hexagon::AND_rr_cPt;
1533 case Hexagon::OR_rr_cPt:
1534 return Hexagon::OR_rr_cNotPt;
1535 case Hexagon::OR_rr_cNotPt:
1536 return Hexagon::OR_rr_cPt;
1538 case Hexagon::SUB_rr_cPt:
1539 return Hexagon::SUB_rr_cNotPt;
1540 case Hexagon::SUB_rr_cNotPt:
1541 return Hexagon::SUB_rr_cPt;
1543 case Hexagon::COMBINE_rr_cPt:
1544 return Hexagon::COMBINE_rr_cNotPt;
1545 case Hexagon::COMBINE_rr_cNotPt:
1546 return Hexagon::COMBINE_rr_cPt;
1548 case Hexagon::ASLH_cPt_V4:
1549 return Hexagon::ASLH_cNotPt_V4;
1550 case Hexagon::ASLH_cNotPt_V4:
1551 return Hexagon::ASLH_cPt_V4;
1553 case Hexagon::ASRH_cPt_V4:
1554 return Hexagon::ASRH_cNotPt_V4;
1555 case Hexagon::ASRH_cNotPt_V4:
1556 return Hexagon::ASRH_cPt_V4;
1558 case Hexagon::SXTB_cPt_V4:
1559 return Hexagon::SXTB_cNotPt_V4;
1560 case Hexagon::SXTB_cNotPt_V4:
1561 return Hexagon::SXTB_cPt_V4;
1563 case Hexagon::SXTH_cPt_V4:
1564 return Hexagon::SXTH_cNotPt_V4;
1565 case Hexagon::SXTH_cNotPt_V4:
1566 return Hexagon::SXTH_cPt_V4;
1568 case Hexagon::ZXTB_cPt_V4:
1569 return Hexagon::ZXTB_cNotPt_V4;
1570 case Hexagon::ZXTB_cNotPt_V4:
1571 return Hexagon::ZXTB_cPt_V4;
1573 case Hexagon::ZXTH_cPt_V4:
1574 return Hexagon::ZXTH_cNotPt_V4;
1575 case Hexagon::ZXTH_cNotPt_V4:
1576 return Hexagon::ZXTH_cPt_V4;
1579 case Hexagon::JMPR_cPt:
1580 return Hexagon::JMPR_cNotPt;
1581 case Hexagon::JMPR_cNotPt:
1582 return Hexagon::JMPR_cPt;
1584 // V4 indexed+scaled load.
1585 case Hexagon::LDrid_indexed_shl_cPt_V4:
1586 return Hexagon::LDrid_indexed_shl_cNotPt_V4;
1587 case Hexagon::LDrid_indexed_shl_cNotPt_V4:
1588 return Hexagon::LDrid_indexed_shl_cPt_V4;
1590 case Hexagon::LDrib_indexed_shl_cPt_V4:
1591 return Hexagon::LDrib_indexed_shl_cNotPt_V4;
1592 case Hexagon::LDrib_indexed_shl_cNotPt_V4:
1593 return Hexagon::LDrib_indexed_shl_cPt_V4;
1595 case Hexagon::LDriub_indexed_shl_cPt_V4:
1596 return Hexagon::LDriub_indexed_shl_cNotPt_V4;
1597 case Hexagon::LDriub_indexed_shl_cNotPt_V4:
1598 return Hexagon::LDriub_indexed_shl_cPt_V4;
1600 case Hexagon::LDrih_indexed_shl_cPt_V4:
1601 return Hexagon::LDrih_indexed_shl_cNotPt_V4;
1602 case Hexagon::LDrih_indexed_shl_cNotPt_V4:
1603 return Hexagon::LDrih_indexed_shl_cPt_V4;
1605 case Hexagon::LDriuh_indexed_shl_cPt_V4:
1606 return Hexagon::LDriuh_indexed_shl_cNotPt_V4;
1607 case Hexagon::LDriuh_indexed_shl_cNotPt_V4:
1608 return Hexagon::LDriuh_indexed_shl_cPt_V4;
1610 case Hexagon::LDriw_indexed_shl_cPt_V4:
1611 return Hexagon::LDriw_indexed_shl_cNotPt_V4;
1612 case Hexagon::LDriw_indexed_shl_cNotPt_V4:
1613 return Hexagon::LDriw_indexed_shl_cPt_V4;
1616 case Hexagon::POST_STbri_cPt:
1617 return Hexagon::POST_STbri_cNotPt;
1618 case Hexagon::POST_STbri_cNotPt:
1619 return Hexagon::POST_STbri_cPt;
1621 case Hexagon::STrib_cPt:
1622 return Hexagon::STrib_cNotPt;
1623 case Hexagon::STrib_cNotPt:
1624 return Hexagon::STrib_cPt;
1626 case Hexagon::STrib_indexed_cPt:
1627 return Hexagon::STrib_indexed_cNotPt;
1628 case Hexagon::STrib_indexed_cNotPt:
1629 return Hexagon::STrib_indexed_cPt;
1631 case Hexagon::STrib_imm_cPt_V4:
1632 return Hexagon::STrib_imm_cNotPt_V4;
1633 case Hexagon::STrib_imm_cNotPt_V4:
1634 return Hexagon::STrib_imm_cPt_V4;
1636 case Hexagon::STrib_indexed_shl_cPt_V4:
1637 return Hexagon::STrib_indexed_shl_cNotPt_V4;
1638 case Hexagon::STrib_indexed_shl_cNotPt_V4:
1639 return Hexagon::STrib_indexed_shl_cPt_V4;
1642 case Hexagon::POST_SThri_cPt:
1643 return Hexagon::POST_SThri_cNotPt;
1644 case Hexagon::POST_SThri_cNotPt:
1645 return Hexagon::POST_SThri_cPt;
1647 case Hexagon::STrih_cPt:
1648 return Hexagon::STrih_cNotPt;
1649 case Hexagon::STrih_cNotPt:
1650 return Hexagon::STrih_cPt;
1652 case Hexagon::STrih_indexed_cPt:
1653 return Hexagon::STrih_indexed_cNotPt;
1654 case Hexagon::STrih_indexed_cNotPt:
1655 return Hexagon::STrih_indexed_cPt;
1657 case Hexagon::STrih_imm_cPt_V4:
1658 return Hexagon::STrih_imm_cNotPt_V4;
1659 case Hexagon::STrih_imm_cNotPt_V4:
1660 return Hexagon::STrih_imm_cPt_V4;
1662 case Hexagon::STrih_indexed_shl_cPt_V4:
1663 return Hexagon::STrih_indexed_shl_cNotPt_V4;
1664 case Hexagon::STrih_indexed_shl_cNotPt_V4:
1665 return Hexagon::STrih_indexed_shl_cPt_V4;
1668 case Hexagon::POST_STwri_cPt:
1669 return Hexagon::POST_STwri_cNotPt;
1670 case Hexagon::POST_STwri_cNotPt:
1671 return Hexagon::POST_STwri_cPt;
1673 case Hexagon::STriw_cPt:
1674 return Hexagon::STriw_cNotPt;
1675 case Hexagon::STriw_cNotPt:
1676 return Hexagon::STriw_cPt;
1678 case Hexagon::STriw_indexed_cPt:
1679 return Hexagon::STriw_indexed_cNotPt;
1680 case Hexagon::STriw_indexed_cNotPt:
1681 return Hexagon::STriw_indexed_cPt;
1683 case Hexagon::STriw_indexed_shl_cPt_V4:
1684 return Hexagon::STriw_indexed_shl_cNotPt_V4;
1685 case Hexagon::STriw_indexed_shl_cNotPt_V4:
1686 return Hexagon::STriw_indexed_shl_cPt_V4;
1688 case Hexagon::STriw_imm_cPt_V4:
1689 return Hexagon::STriw_imm_cNotPt_V4;
1690 case Hexagon::STriw_imm_cNotPt_V4:
1691 return Hexagon::STriw_imm_cPt_V4;
1694 case Hexagon::POST_STdri_cPt:
1695 return Hexagon::POST_STdri_cNotPt;
1696 case Hexagon::POST_STdri_cNotPt:
1697 return Hexagon::POST_STdri_cPt;
1699 case Hexagon::STrid_cPt:
1700 return Hexagon::STrid_cNotPt;
1701 case Hexagon::STrid_cNotPt:
1702 return Hexagon::STrid_cPt;
1704 case Hexagon::STrid_indexed_cPt:
1705 return Hexagon::STrid_indexed_cNotPt;
1706 case Hexagon::STrid_indexed_cNotPt:
1707 return Hexagon::STrid_indexed_cPt;
1709 case Hexagon::STrid_indexed_shl_cPt_V4:
1710 return Hexagon::STrid_indexed_shl_cNotPt_V4;
1711 case Hexagon::STrid_indexed_shl_cNotPt_V4:
1712 return Hexagon::STrid_indexed_shl_cPt_V4;
1714 // V4 Store to global address.
1715 case Hexagon::STd_GP_cPt_V4:
1716 return Hexagon::STd_GP_cNotPt_V4;
1717 case Hexagon::STd_GP_cNotPt_V4:
1718 return Hexagon::STd_GP_cPt_V4;
1720 case Hexagon::STb_GP_cPt_V4:
1721 return Hexagon::STb_GP_cNotPt_V4;
1722 case Hexagon::STb_GP_cNotPt_V4:
1723 return Hexagon::STb_GP_cPt_V4;
1725 case Hexagon::STh_GP_cPt_V4:
1726 return Hexagon::STh_GP_cNotPt_V4;
1727 case Hexagon::STh_GP_cNotPt_V4:
1728 return Hexagon::STh_GP_cPt_V4;
1730 case Hexagon::STw_GP_cPt_V4:
1731 return Hexagon::STw_GP_cNotPt_V4;
1732 case Hexagon::STw_GP_cNotPt_V4:
1733 return Hexagon::STw_GP_cPt_V4;
1735 case Hexagon::STrid_GP_cPt_V4:
1736 return Hexagon::STrid_GP_cNotPt_V4;
1737 case Hexagon::STrid_GP_cNotPt_V4:
1738 return Hexagon::STrid_GP_cPt_V4;
1740 case Hexagon::STrib_GP_cPt_V4:
1741 return Hexagon::STrib_GP_cNotPt_V4;
1742 case Hexagon::STrib_GP_cNotPt_V4:
1743 return Hexagon::STrib_GP_cPt_V4;
1745 case Hexagon::STrih_GP_cPt_V4:
1746 return Hexagon::STrih_GP_cNotPt_V4;
1747 case Hexagon::STrih_GP_cNotPt_V4:
1748 return Hexagon::STrih_GP_cPt_V4;
1750 case Hexagon::STriw_GP_cPt_V4:
1751 return Hexagon::STriw_GP_cNotPt_V4;
1752 case Hexagon::STriw_GP_cNotPt_V4:
1753 return Hexagon::STriw_GP_cPt_V4;
1756 case Hexagon::LDrid_cPt:
1757 return Hexagon::LDrid_cNotPt;
1758 case Hexagon::LDrid_cNotPt:
1759 return Hexagon::LDrid_cPt;
1761 case Hexagon::LDriw_cPt:
1762 return Hexagon::LDriw_cNotPt;
1763 case Hexagon::LDriw_cNotPt:
1764 return Hexagon::LDriw_cPt;
1766 case Hexagon::LDrih_cPt:
1767 return Hexagon::LDrih_cNotPt;
1768 case Hexagon::LDrih_cNotPt:
1769 return Hexagon::LDrih_cPt;
1771 case Hexagon::LDriuh_cPt:
1772 return Hexagon::LDriuh_cNotPt;
1773 case Hexagon::LDriuh_cNotPt:
1774 return Hexagon::LDriuh_cPt;
1776 case Hexagon::LDrib_cPt:
1777 return Hexagon::LDrib_cNotPt;
1778 case Hexagon::LDrib_cNotPt:
1779 return Hexagon::LDrib_cPt;
1781 case Hexagon::LDriub_cPt:
1782 return Hexagon::LDriub_cNotPt;
1783 case Hexagon::LDriub_cNotPt:
1784 return Hexagon::LDriub_cPt;
1787 case Hexagon::LDrid_indexed_cPt:
1788 return Hexagon::LDrid_indexed_cNotPt;
1789 case Hexagon::LDrid_indexed_cNotPt:
1790 return Hexagon::LDrid_indexed_cPt;
1792 case Hexagon::LDriw_indexed_cPt:
1793 return Hexagon::LDriw_indexed_cNotPt;
1794 case Hexagon::LDriw_indexed_cNotPt:
1795 return Hexagon::LDriw_indexed_cPt;
1797 case Hexagon::LDrih_indexed_cPt:
1798 return Hexagon::LDrih_indexed_cNotPt;
1799 case Hexagon::LDrih_indexed_cNotPt:
1800 return Hexagon::LDrih_indexed_cPt;
1802 case Hexagon::LDriuh_indexed_cPt:
1803 return Hexagon::LDriuh_indexed_cNotPt;
1804 case Hexagon::LDriuh_indexed_cNotPt:
1805 return Hexagon::LDriuh_indexed_cPt;
1807 case Hexagon::LDrib_indexed_cPt:
1808 return Hexagon::LDrib_indexed_cNotPt;
1809 case Hexagon::LDrib_indexed_cNotPt:
1810 return Hexagon::LDrib_indexed_cPt;
1812 case Hexagon::LDriub_indexed_cPt:
1813 return Hexagon::LDriub_indexed_cNotPt;
1814 case Hexagon::LDriub_indexed_cNotPt:
1815 return Hexagon::LDriub_indexed_cPt;
1818 case Hexagon::POST_LDrid_cPt:
1819 return Hexagon::POST_LDrid_cNotPt;
1820 case Hexagon::POST_LDriw_cNotPt:
1821 return Hexagon::POST_LDriw_cPt;
1823 case Hexagon::POST_LDrih_cPt:
1824 return Hexagon::POST_LDrih_cNotPt;
1825 case Hexagon::POST_LDrih_cNotPt:
1826 return Hexagon::POST_LDrih_cPt;
1828 case Hexagon::POST_LDriuh_cPt:
1829 return Hexagon::POST_LDriuh_cNotPt;
1830 case Hexagon::POST_LDriuh_cNotPt:
1831 return Hexagon::POST_LDriuh_cPt;
1833 case Hexagon::POST_LDrib_cPt:
1834 return Hexagon::POST_LDrib_cNotPt;
1835 case Hexagon::POST_LDrib_cNotPt:
1836 return Hexagon::POST_LDrib_cPt;
1838 case Hexagon::POST_LDriub_cPt:
1839 return Hexagon::POST_LDriub_cNotPt;
1840 case Hexagon::POST_LDriub_cNotPt:
1841 return Hexagon::POST_LDriub_cPt;
1844 case Hexagon::DEALLOC_RET_cPt_V4:
1845 return Hexagon::DEALLOC_RET_cNotPt_V4;
1846 case Hexagon::DEALLOC_RET_cNotPt_V4:
1847 return Hexagon::DEALLOC_RET_cPt_V4;
1850 // JMPEQ_ri - with -1.
1851 case Hexagon::JMP_EQriPtneg_nv_V4:
1852 return Hexagon::JMP_EQriNotPtneg_nv_V4;
1853 case Hexagon::JMP_EQriNotPtneg_nv_V4:
1854 return Hexagon::JMP_EQriPtneg_nv_V4;
1856 case Hexagon::JMP_EQriPntneg_nv_V4:
1857 return Hexagon::JMP_EQriNotPntneg_nv_V4;
1858 case Hexagon::JMP_EQriNotPntneg_nv_V4:
1859 return Hexagon::JMP_EQriPntneg_nv_V4;
1862 case Hexagon::JMP_EQriPt_nv_V4:
1863 return Hexagon::JMP_EQriNotPt_nv_V4;
1864 case Hexagon::JMP_EQriNotPt_nv_V4:
1865 return Hexagon::JMP_EQriPt_nv_V4;
1867 case Hexagon::JMP_EQriPnt_nv_V4:
1868 return Hexagon::JMP_EQriNotPnt_nv_V4;
1869 case Hexagon::JMP_EQriNotPnt_nv_V4:
1870 return Hexagon::JMP_EQriPnt_nv_V4;
1873 case Hexagon::JMP_EQrrPt_nv_V4:
1874 return Hexagon::JMP_EQrrNotPt_nv_V4;
1875 case Hexagon::JMP_EQrrNotPt_nv_V4:
1876 return Hexagon::JMP_EQrrPt_nv_V4;
1878 case Hexagon::JMP_EQrrPnt_nv_V4:
1879 return Hexagon::JMP_EQrrNotPnt_nv_V4;
1880 case Hexagon::JMP_EQrrNotPnt_nv_V4:
1881 return Hexagon::JMP_EQrrPnt_nv_V4;
1883 // JMPGT_ri - with -1.
1884 case Hexagon::JMP_GTriPtneg_nv_V4:
1885 return Hexagon::JMP_GTriNotPtneg_nv_V4;
1886 case Hexagon::JMP_GTriNotPtneg_nv_V4:
1887 return Hexagon::JMP_GTriPtneg_nv_V4;
1889 case Hexagon::JMP_GTriPntneg_nv_V4:
1890 return Hexagon::JMP_GTriNotPntneg_nv_V4;
1891 case Hexagon::JMP_GTriNotPntneg_nv_V4:
1892 return Hexagon::JMP_GTriPntneg_nv_V4;
1895 case Hexagon::JMP_GTriPt_nv_V4:
1896 return Hexagon::JMP_GTriNotPt_nv_V4;
1897 case Hexagon::JMP_GTriNotPt_nv_V4:
1898 return Hexagon::JMP_GTriPt_nv_V4;
1900 case Hexagon::JMP_GTriPnt_nv_V4:
1901 return Hexagon::JMP_GTriNotPnt_nv_V4;
1902 case Hexagon::JMP_GTriNotPnt_nv_V4:
1903 return Hexagon::JMP_GTriPnt_nv_V4;
1906 case Hexagon::JMP_GTrrPt_nv_V4:
1907 return Hexagon::JMP_GTrrNotPt_nv_V4;
1908 case Hexagon::JMP_GTrrNotPt_nv_V4:
1909 return Hexagon::JMP_GTrrPt_nv_V4;
1911 case Hexagon::JMP_GTrrPnt_nv_V4:
1912 return Hexagon::JMP_GTrrNotPnt_nv_V4;
1913 case Hexagon::JMP_GTrrNotPnt_nv_V4:
1914 return Hexagon::JMP_GTrrPnt_nv_V4;
1917 case Hexagon::JMP_GTrrdnPt_nv_V4:
1918 return Hexagon::JMP_GTrrdnNotPt_nv_V4;
1919 case Hexagon::JMP_GTrrdnNotPt_nv_V4:
1920 return Hexagon::JMP_GTrrdnPt_nv_V4;
1922 case Hexagon::JMP_GTrrdnPnt_nv_V4:
1923 return Hexagon::JMP_GTrrdnNotPnt_nv_V4;
1924 case Hexagon::JMP_GTrrdnNotPnt_nv_V4:
1925 return Hexagon::JMP_GTrrdnPnt_nv_V4;
1928 case Hexagon::JMP_GTUriPt_nv_V4:
1929 return Hexagon::JMP_GTUriNotPt_nv_V4;
1930 case Hexagon::JMP_GTUriNotPt_nv_V4:
1931 return Hexagon::JMP_GTUriPt_nv_V4;
1933 case Hexagon::JMP_GTUriPnt_nv_V4:
1934 return Hexagon::JMP_GTUriNotPnt_nv_V4;
1935 case Hexagon::JMP_GTUriNotPnt_nv_V4:
1936 return Hexagon::JMP_GTUriPnt_nv_V4;
1939 case Hexagon::JMP_GTUrrPt_nv_V4:
1940 return Hexagon::JMP_GTUrrNotPt_nv_V4;
1941 case Hexagon::JMP_GTUrrNotPt_nv_V4:
1942 return Hexagon::JMP_GTUrrPt_nv_V4;
1944 case Hexagon::JMP_GTUrrPnt_nv_V4:
1945 return Hexagon::JMP_GTUrrNotPnt_nv_V4;
1946 case Hexagon::JMP_GTUrrNotPnt_nv_V4:
1947 return Hexagon::JMP_GTUrrPnt_nv_V4;
1950 case Hexagon::JMP_GTUrrdnPt_nv_V4:
1951 return Hexagon::JMP_GTUrrdnNotPt_nv_V4;
1952 case Hexagon::JMP_GTUrrdnNotPt_nv_V4:
1953 return Hexagon::JMP_GTUrrdnPt_nv_V4;
1955 case Hexagon::JMP_GTUrrdnPnt_nv_V4:
1956 return Hexagon::JMP_GTUrrdnNotPnt_nv_V4;
1957 case Hexagon::JMP_GTUrrdnNotPnt_nv_V4:
1958 return Hexagon::JMP_GTUrrdnPnt_nv_V4;
1963 int HexagonInstrInfo::
1964 getMatchingCondBranchOpcode(int Opc, bool invertPredicate) const {
1965 enum Hexagon::PredSense inPredSense;
1966 inPredSense = invertPredicate ? Hexagon::PredSense_false :
1967 Hexagon::PredSense_true;
1968 int CondOpcode = Hexagon::getPredOpcode(Opc, inPredSense);
1969 if (CondOpcode >= 0) // Valid Conditional opcode/instruction
1972 // This switch case will be removed once all the instructions have been
1973 // modified to use relation maps.
1976 return !invertPredicate ? Hexagon::TFR_cPt :
1977 Hexagon::TFR_cNotPt;
1978 case Hexagon::TFRI_f:
1979 return !invertPredicate ? Hexagon::TFRI_cPt_f :
1980 Hexagon::TFRI_cNotPt_f;
1982 return !invertPredicate ? Hexagon::TFRI_cPt :
1983 Hexagon::TFRI_cNotPt;
1985 return !invertPredicate ? Hexagon::JMP_c :
1987 case Hexagon::JMP_EQrrPt_nv_V4:
1988 return !invertPredicate ? Hexagon::JMP_EQrrPt_nv_V4 :
1989 Hexagon::JMP_EQrrNotPt_nv_V4;
1990 case Hexagon::JMP_EQriPt_nv_V4:
1991 return !invertPredicate ? Hexagon::JMP_EQriPt_nv_V4 :
1992 Hexagon::JMP_EQriNotPt_nv_V4;
1993 case Hexagon::COMBINE_rr:
1994 return !invertPredicate ? Hexagon::COMBINE_rr_cPt :
1995 Hexagon::COMBINE_rr_cNotPt;
1997 return !invertPredicate ? Hexagon::ASLH_cPt_V4 :
1998 Hexagon::ASLH_cNotPt_V4;
2000 return !invertPredicate ? Hexagon::ASRH_cPt_V4 :
2001 Hexagon::ASRH_cNotPt_V4;
2003 return !invertPredicate ? Hexagon::SXTB_cPt_V4 :
2004 Hexagon::SXTB_cNotPt_V4;
2006 return !invertPredicate ? Hexagon::SXTH_cPt_V4 :
2007 Hexagon::SXTH_cNotPt_V4;
2009 return !invertPredicate ? Hexagon::ZXTB_cPt_V4 :
2010 Hexagon::ZXTB_cNotPt_V4;
2012 return !invertPredicate ? Hexagon::ZXTH_cPt_V4 :
2013 Hexagon::ZXTH_cNotPt_V4;
2016 return !invertPredicate ? Hexagon::JMPR_cPt :
2017 Hexagon::JMPR_cNotPt;
2019 // V4 indexed+scaled load.
2020 case Hexagon::LDrid_indexed_shl_V4:
2021 return !invertPredicate ? Hexagon::LDrid_indexed_shl_cPt_V4 :
2022 Hexagon::LDrid_indexed_shl_cNotPt_V4;
2023 case Hexagon::LDrib_indexed_shl_V4:
2024 return !invertPredicate ? Hexagon::LDrib_indexed_shl_cPt_V4 :
2025 Hexagon::LDrib_indexed_shl_cNotPt_V4;
2026 case Hexagon::LDriub_indexed_shl_V4:
2027 return !invertPredicate ? Hexagon::LDriub_indexed_shl_cPt_V4 :
2028 Hexagon::LDriub_indexed_shl_cNotPt_V4;
2029 case Hexagon::LDrih_indexed_shl_V4:
2030 return !invertPredicate ? Hexagon::LDrih_indexed_shl_cPt_V4 :
2031 Hexagon::LDrih_indexed_shl_cNotPt_V4;
2032 case Hexagon::LDriuh_indexed_shl_V4:
2033 return !invertPredicate ? Hexagon::LDriuh_indexed_shl_cPt_V4 :
2034 Hexagon::LDriuh_indexed_shl_cNotPt_V4;
2035 case Hexagon::LDriw_indexed_shl_V4:
2036 return !invertPredicate ? Hexagon::LDriw_indexed_shl_cPt_V4 :
2037 Hexagon::LDriw_indexed_shl_cNotPt_V4;
2039 // V4 Load from global address
2040 case Hexagon::LDrid_GP_V4:
2041 return !invertPredicate ? Hexagon::LDrid_GP_cPt_V4 :
2042 Hexagon::LDrid_GP_cNotPt_V4;
2043 case Hexagon::LDrib_GP_V4:
2044 return !invertPredicate ? Hexagon::LDrib_GP_cPt_V4 :
2045 Hexagon::LDrib_GP_cNotPt_V4;
2046 case Hexagon::LDriub_GP_V4:
2047 return !invertPredicate ? Hexagon::LDriub_GP_cPt_V4 :
2048 Hexagon::LDriub_GP_cNotPt_V4;
2049 case Hexagon::LDrih_GP_V4:
2050 return !invertPredicate ? Hexagon::LDrih_GP_cPt_V4 :
2051 Hexagon::LDrih_GP_cNotPt_V4;
2052 case Hexagon::LDriuh_GP_V4:
2053 return !invertPredicate ? Hexagon::LDriuh_GP_cPt_V4 :
2054 Hexagon::LDriuh_GP_cNotPt_V4;
2055 case Hexagon::LDriw_GP_V4:
2056 return !invertPredicate ? Hexagon::LDriw_GP_cPt_V4 :
2057 Hexagon::LDriw_GP_cNotPt_V4;
2059 case Hexagon::LDd_GP_V4:
2060 return !invertPredicate ? Hexagon::LDd_GP_cPt_V4 :
2061 Hexagon::LDd_GP_cNotPt_V4;
2062 case Hexagon::LDb_GP_V4:
2063 return !invertPredicate ? Hexagon::LDb_GP_cPt_V4 :
2064 Hexagon::LDb_GP_cNotPt_V4;
2065 case Hexagon::LDub_GP_V4:
2066 return !invertPredicate ? Hexagon::LDub_GP_cPt_V4 :
2067 Hexagon::LDub_GP_cNotPt_V4;
2068 case Hexagon::LDh_GP_V4:
2069 return !invertPredicate ? Hexagon::LDh_GP_cPt_V4 :
2070 Hexagon::LDh_GP_cNotPt_V4;
2071 case Hexagon::LDuh_GP_V4:
2072 return !invertPredicate ? Hexagon::LDuh_GP_cPt_V4 :
2073 Hexagon::LDuh_GP_cNotPt_V4;
2074 case Hexagon::LDw_GP_V4:
2075 return !invertPredicate ? Hexagon::LDw_GP_cPt_V4 :
2076 Hexagon::LDw_GP_cNotPt_V4;
2079 case Hexagon::POST_STbri:
2080 return !invertPredicate ? Hexagon::POST_STbri_cPt :
2081 Hexagon::POST_STbri_cNotPt;
2082 case Hexagon::STrib:
2083 return !invertPredicate ? Hexagon::STrib_cPt :
2084 Hexagon::STrib_cNotPt;
2085 case Hexagon::STrib_indexed:
2086 return !invertPredicate ? Hexagon::STrib_indexed_cPt :
2087 Hexagon::STrib_indexed_cNotPt;
2088 case Hexagon::STrib_imm_V4:
2089 return !invertPredicate ? Hexagon::STrib_imm_cPt_V4 :
2090 Hexagon::STrib_imm_cNotPt_V4;
2091 case Hexagon::STrib_indexed_shl_V4:
2092 return !invertPredicate ? Hexagon::STrib_indexed_shl_cPt_V4 :
2093 Hexagon::STrib_indexed_shl_cNotPt_V4;
2095 case Hexagon::POST_SThri:
2096 return !invertPredicate ? Hexagon::POST_SThri_cPt :
2097 Hexagon::POST_SThri_cNotPt;
2098 case Hexagon::STrih:
2099 return !invertPredicate ? Hexagon::STrih_cPt :
2100 Hexagon::STrih_cNotPt;
2101 case Hexagon::STrih_indexed:
2102 return !invertPredicate ? Hexagon::STrih_indexed_cPt :
2103 Hexagon::STrih_indexed_cNotPt;
2104 case Hexagon::STrih_imm_V4:
2105 return !invertPredicate ? Hexagon::STrih_imm_cPt_V4 :
2106 Hexagon::STrih_imm_cNotPt_V4;
2107 case Hexagon::STrih_indexed_shl_V4:
2108 return !invertPredicate ? Hexagon::STrih_indexed_shl_cPt_V4 :
2109 Hexagon::STrih_indexed_shl_cNotPt_V4;
2111 case Hexagon::POST_STwri:
2112 return !invertPredicate ? Hexagon::POST_STwri_cPt :
2113 Hexagon::POST_STwri_cNotPt;
2114 case Hexagon::STriw:
2115 return !invertPredicate ? Hexagon::STriw_cPt :
2116 Hexagon::STriw_cNotPt;
2117 case Hexagon::STriw_indexed:
2118 return !invertPredicate ? Hexagon::STriw_indexed_cPt :
2119 Hexagon::STriw_indexed_cNotPt;
2120 case Hexagon::STriw_indexed_shl_V4:
2121 return !invertPredicate ? Hexagon::STriw_indexed_shl_cPt_V4 :
2122 Hexagon::STriw_indexed_shl_cNotPt_V4;
2123 case Hexagon::STriw_imm_V4:
2124 return !invertPredicate ? Hexagon::STriw_imm_cPt_V4 :
2125 Hexagon::STriw_imm_cNotPt_V4;
2127 case Hexagon::POST_STdri:
2128 return !invertPredicate ? Hexagon::POST_STdri_cPt :
2129 Hexagon::POST_STdri_cNotPt;
2130 case Hexagon::STrid:
2131 return !invertPredicate ? Hexagon::STrid_cPt :
2132 Hexagon::STrid_cNotPt;
2133 case Hexagon::STrid_indexed:
2134 return !invertPredicate ? Hexagon::STrid_indexed_cPt :
2135 Hexagon::STrid_indexed_cNotPt;
2136 case Hexagon::STrid_indexed_shl_V4:
2137 return !invertPredicate ? Hexagon::STrid_indexed_shl_cPt_V4 :
2138 Hexagon::STrid_indexed_shl_cNotPt_V4;
2140 // V4 Store to global address
2141 case Hexagon::STrid_GP_V4:
2142 return !invertPredicate ? Hexagon::STrid_GP_cPt_V4 :
2143 Hexagon::STrid_GP_cNotPt_V4;
2144 case Hexagon::STrib_GP_V4:
2145 return !invertPredicate ? Hexagon::STrib_GP_cPt_V4 :
2146 Hexagon::STrib_GP_cNotPt_V4;
2147 case Hexagon::STrih_GP_V4:
2148 return !invertPredicate ? Hexagon::STrih_GP_cPt_V4 :
2149 Hexagon::STrih_GP_cNotPt_V4;
2150 case Hexagon::STriw_GP_V4:
2151 return !invertPredicate ? Hexagon::STriw_GP_cPt_V4 :
2152 Hexagon::STriw_GP_cNotPt_V4;
2154 case Hexagon::STd_GP_V4:
2155 return !invertPredicate ? Hexagon::STd_GP_cPt_V4 :
2156 Hexagon::STd_GP_cNotPt_V4;
2157 case Hexagon::STb_GP_V4:
2158 return !invertPredicate ? Hexagon::STb_GP_cPt_V4 :
2159 Hexagon::STb_GP_cNotPt_V4;
2160 case Hexagon::STh_GP_V4:
2161 return !invertPredicate ? Hexagon::STh_GP_cPt_V4 :
2162 Hexagon::STh_GP_cNotPt_V4;
2163 case Hexagon::STw_GP_V4:
2164 return !invertPredicate ? Hexagon::STw_GP_cPt_V4 :
2165 Hexagon::STw_GP_cNotPt_V4;
2168 case Hexagon::LDrid:
2169 return !invertPredicate ? Hexagon::LDrid_cPt :
2170 Hexagon::LDrid_cNotPt;
2171 case Hexagon::LDriw:
2172 return !invertPredicate ? Hexagon::LDriw_cPt :
2173 Hexagon::LDriw_cNotPt;
2174 case Hexagon::LDrih:
2175 return !invertPredicate ? Hexagon::LDrih_cPt :
2176 Hexagon::LDrih_cNotPt;
2177 case Hexagon::LDriuh:
2178 return !invertPredicate ? Hexagon::LDriuh_cPt :
2179 Hexagon::LDriuh_cNotPt;
2180 case Hexagon::LDrib:
2181 return !invertPredicate ? Hexagon::LDrib_cPt :
2182 Hexagon::LDrib_cNotPt;
2183 case Hexagon::LDriub:
2184 return !invertPredicate ? Hexagon::LDriub_cPt :
2185 Hexagon::LDriub_cNotPt;
2187 case Hexagon::LDrid_indexed:
2188 return !invertPredicate ? Hexagon::LDrid_indexed_cPt :
2189 Hexagon::LDrid_indexed_cNotPt;
2190 case Hexagon::LDriw_indexed:
2191 return !invertPredicate ? Hexagon::LDriw_indexed_cPt :
2192 Hexagon::LDriw_indexed_cNotPt;
2193 case Hexagon::LDrih_indexed:
2194 return !invertPredicate ? Hexagon::LDrih_indexed_cPt :
2195 Hexagon::LDrih_indexed_cNotPt;
2196 case Hexagon::LDriuh_indexed:
2197 return !invertPredicate ? Hexagon::LDriuh_indexed_cPt :
2198 Hexagon::LDriuh_indexed_cNotPt;
2199 case Hexagon::LDrib_indexed:
2200 return !invertPredicate ? Hexagon::LDrib_indexed_cPt :
2201 Hexagon::LDrib_indexed_cNotPt;
2202 case Hexagon::LDriub_indexed:
2203 return !invertPredicate ? Hexagon::LDriub_indexed_cPt :
2204 Hexagon::LDriub_indexed_cNotPt;
2205 // Post Increment Load.
2206 case Hexagon::POST_LDrid:
2207 return !invertPredicate ? Hexagon::POST_LDrid_cPt :
2208 Hexagon::POST_LDrid_cNotPt;
2209 case Hexagon::POST_LDriw:
2210 return !invertPredicate ? Hexagon::POST_LDriw_cPt :
2211 Hexagon::POST_LDriw_cNotPt;
2212 case Hexagon::POST_LDrih:
2213 return !invertPredicate ? Hexagon::POST_LDrih_cPt :
2214 Hexagon::POST_LDrih_cNotPt;
2215 case Hexagon::POST_LDriuh:
2216 return !invertPredicate ? Hexagon::POST_LDriuh_cPt :
2217 Hexagon::POST_LDriuh_cNotPt;
2218 case Hexagon::POST_LDrib:
2219 return !invertPredicate ? Hexagon::POST_LDrib_cPt :
2220 Hexagon::POST_LDrib_cNotPt;
2221 case Hexagon::POST_LDriub:
2222 return !invertPredicate ? Hexagon::POST_LDriub_cPt :
2223 Hexagon::POST_LDriub_cNotPt;
2225 case Hexagon::DEALLOC_RET_V4:
2226 return !invertPredicate ? Hexagon::DEALLOC_RET_cPt_V4 :
2227 Hexagon::DEALLOC_RET_cNotPt_V4;
2229 llvm_unreachable("Unexpected predicable instruction");
2233 bool HexagonInstrInfo::
2234 PredicateInstruction(MachineInstr *MI,
2235 const SmallVectorImpl<MachineOperand> &Cond) const {
2236 int Opc = MI->getOpcode();
2237 assert (isPredicable(MI) && "Expected predicable instruction");
2238 bool invertJump = (!Cond.empty() && Cond[0].isImm() &&
2239 (Cond[0].getImm() == 0));
2241 // This will change MI's opcode to its predicate version.
2242 // However, its operand list is still the old one, i.e. the
2243 // non-predicate one.
2244 MI->setDesc(get(getMatchingCondBranchOpcode(Opc, invertJump)));
2247 unsigned int GAIdx = 0;
2249 // Indicates whether the current MI has a GlobalAddress operand
2250 bool hasGAOpnd = false;
2251 std::vector<MachineOperand> tmpOpnds;
2253 // Indicates whether we need to shift operands to right.
2254 bool needShift = true;
2256 // The predicate is ALWAYS the FIRST input operand !!!
2257 if (MI->getNumOperands() == 0) {
2258 // The non-predicate version of MI does not take any operands,
2259 // i.e. no outs and no ins. In this condition, the predicate
2260 // operand will be directly placed at Operands[0]. No operand
2266 else if ( MI->getOperand(MI->getNumOperands()-1).isReg()
2267 && MI->getOperand(MI->getNumOperands()-1).isDef()
2268 && !MI->getOperand(MI->getNumOperands()-1).isImplicit()) {
2269 // The non-predicate version of MI does not have any input operands.
2270 // In this condition, we extend the length of Operands[] by one and
2271 // copy the original last operand to the newly allocated slot.
2272 // At this moment, it is just a place holder. Later, we will put
2273 // predicate operand directly into it. No operand shift is needed.
2274 // Example: r0=BARRIER (this is a faked insn used here for illustration)
2275 MI->addOperand(MI->getOperand(MI->getNumOperands()-1));
2277 oper = MI->getNumOperands() - 2;
2280 // We need to right shift all input operands by one. Duplicate the
2281 // last operand into the newly allocated slot.
2282 MI->addOperand(MI->getOperand(MI->getNumOperands()-1));
2287 // Operands[ MI->getNumOperands() - 2 ] has been copied into
2288 // Operands[ MI->getNumOperands() - 1 ], so we start from
2289 // Operands[ MI->getNumOperands() - 3 ].
2290 // oper is a signed int.
2291 // It is ok if "MI->getNumOperands()-3" is -3, -2, or -1.
2292 for (oper = MI->getNumOperands() - 3; oper >= 0; --oper)
2294 MachineOperand &MO = MI->getOperand(oper);
2296 // Opnd[0] Opnd[1] Opnd[2] Opnd[3] Opnd[4] Opnd[5] Opnd[6] Opnd[7]
2297 // <Def0> <Def1> <Use0> <Use1> <ImpDef0> <ImpDef1> <ImpUse0> <ImpUse1>
2301 // Predicate Operand here
2302 if (MO.isReg() && !MO.isUse() && !MO.isImplicit()) {
2306 MI->getOperand(oper+1).ChangeToRegister(MO.getReg(), MO.isDef(),
2307 MO.isImplicit(), MO.isKill(),
2308 MO.isDead(), MO.isUndef(),
2311 else if (MO.isImm()) {
2312 MI->getOperand(oper+1).ChangeToImmediate(MO.getImm());
2314 else if (MO.isGlobal()) {
2315 // MI can not have more than one GlobalAddress operand.
2316 assert(hasGAOpnd == false && "MI can only have one GlobalAddress opnd");
2318 // There is no member function called "ChangeToGlobalAddress" in the
2319 // MachineOperand class (not like "ChangeToRegister" and
2320 // "ChangeToImmediate"). So we have to remove them from Operands[] list
2321 // first, and then add them back after we have inserted the predicate
2322 // operand. tmpOpnds[] is to remember these operands before we remove
2324 tmpOpnds.push_back(MO);
2326 // Operands[oper] is a GlobalAddress operand;
2327 // Operands[oper+1] has been copied into Operands[oper+2];
2333 assert(false && "Unexpected operand type");
2338 int regPos = invertJump ? 1 : 0;
2339 MachineOperand PredMO = Cond[regPos];
2341 // [oper] now points to the last explicit Def. Predicate operand must be
2342 // located at [oper+1]. See diagram above.
2343 // This assumes that the predicate is always the first operand,
2344 // i.e. Operands[0+numResults], in the set of inputs
2345 // It is better to have an assert here to check this. But I don't know how
2346 // to write this assert because findFirstPredOperandIdx() would return -1
2347 if (oper < -1) oper = -1;
2348 MI->getOperand(oper+1).ChangeToRegister(PredMO.getReg(), PredMO.isDef(),
2349 PredMO.isImplicit(), PredMO.isKill(),
2350 PredMO.isDead(), PredMO.isUndef(),
2357 // Operands[GAIdx] is the original GlobalAddress operand, which is
2358 // already copied into tmpOpnds[0].
2359 // Operands[GAIdx] now stores a copy of Operands[GAIdx-1]
2360 // Operands[GAIdx+1] has already been copied into Operands[GAIdx+2],
2361 // so we start from [GAIdx+2]
2362 for (i = GAIdx + 2; i < MI->getNumOperands(); ++i)
2363 tmpOpnds.push_back(MI->getOperand(i));
2365 // Remove all operands in range [ (GAIdx+1) ... (MI->getNumOperands()-1) ]
2366 // It is very important that we always remove from the end of Operands[]
2367 // MI->getNumOperands() is at least 2 if program goes to here.
2368 for (i = MI->getNumOperands() - 1; i > GAIdx; --i)
2369 MI->RemoveOperand(i);
2371 for (i = 0; i < tmpOpnds.size(); ++i)
2372 MI->addOperand(tmpOpnds[i]);
2381 isProfitableToIfCvt(MachineBasicBlock &MBB,
2383 unsigned ExtraPredCycles,
2384 const BranchProbability &Probability) const {
2391 isProfitableToIfCvt(MachineBasicBlock &TMBB,
2392 unsigned NumTCycles,
2393 unsigned ExtraTCycles,
2394 MachineBasicBlock &FMBB,
2395 unsigned NumFCycles,
2396 unsigned ExtraFCycles,
2397 const BranchProbability &Probability) const {
2402 bool HexagonInstrInfo::isPredicated(const MachineInstr *MI) const {
2403 const uint64_t F = MI->getDesc().TSFlags;
2405 return ((F >> HexagonII::PredicatedPos) & HexagonII::PredicatedMask);
2409 HexagonInstrInfo::DefinesPredicate(MachineInstr *MI,
2410 std::vector<MachineOperand> &Pred) const {
2411 for (unsigned oper = 0; oper < MI->getNumOperands(); ++oper) {
2412 MachineOperand MO = MI->getOperand(oper);
2413 if (MO.isReg() && MO.isDef()) {
2414 const TargetRegisterClass* RC = RI.getMinimalPhysRegClass(MO.getReg());
2415 if (RC == &Hexagon::PredRegsRegClass) {
2427 SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
2428 const SmallVectorImpl<MachineOperand> &Pred2) const {
2435 // We indicate that we want to reverse the branch by
2436 // inserting a 0 at the beginning of the Cond vector.
2438 bool HexagonInstrInfo::
2439 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
2440 if (!Cond.empty() && Cond[0].isImm() && Cond[0].getImm() == 0) {
2441 Cond.erase(Cond.begin());
2443 Cond.insert(Cond.begin(), MachineOperand::CreateImm(0));
2449 bool HexagonInstrInfo::
2450 isProfitableToDupForIfCvt(MachineBasicBlock &MBB,unsigned NumInstrs,
2451 const BranchProbability &Probability) const {
2452 return (NumInstrs <= 4);
2455 bool HexagonInstrInfo::isDeallocRet(const MachineInstr *MI) const {
2456 switch (MI->getOpcode()) {
2457 default: return false;
2458 case Hexagon::DEALLOC_RET_V4 :
2459 case Hexagon::DEALLOC_RET_cPt_V4 :
2460 case Hexagon::DEALLOC_RET_cNotPt_V4 :
2461 case Hexagon::DEALLOC_RET_cdnPnt_V4 :
2462 case Hexagon::DEALLOC_RET_cNotdnPnt_V4 :
2463 case Hexagon::DEALLOC_RET_cdnPt_V4 :
2464 case Hexagon::DEALLOC_RET_cNotdnPt_V4 :
2470 bool HexagonInstrInfo::
2471 isValidOffset(const int Opcode, const int Offset) const {
2472 // This function is to check whether the "Offset" is in the correct range of
2473 // the given "Opcode". If "Offset" is not in the correct range, "ADD_ri" is
2474 // inserted to calculate the final address. Due to this reason, the function
2475 // assumes that the "Offset" has correct alignment.
2479 case Hexagon::LDriw:
2480 case Hexagon::LDriw_indexed:
2481 case Hexagon::LDriw_f:
2482 case Hexagon::STriw_indexed:
2483 case Hexagon::STriw:
2484 case Hexagon::STriw_f:
2485 assert((Offset % 4 == 0) && "Offset has incorrect alignment");
2486 return (Offset >= Hexagon_MEMW_OFFSET_MIN) &&
2487 (Offset <= Hexagon_MEMW_OFFSET_MAX);
2489 case Hexagon::LDrid:
2490 case Hexagon::LDrid_indexed:
2491 case Hexagon::LDrid_f:
2492 case Hexagon::STrid:
2493 case Hexagon::STrid_indexed:
2494 case Hexagon::STrid_f:
2495 assert((Offset % 8 == 0) && "Offset has incorrect alignment");
2496 return (Offset >= Hexagon_MEMD_OFFSET_MIN) &&
2497 (Offset <= Hexagon_MEMD_OFFSET_MAX);
2499 case Hexagon::LDrih:
2500 case Hexagon::LDriuh:
2501 case Hexagon::STrih:
2502 assert((Offset % 2 == 0) && "Offset has incorrect alignment");
2503 return (Offset >= Hexagon_MEMH_OFFSET_MIN) &&
2504 (Offset <= Hexagon_MEMH_OFFSET_MAX);
2506 case Hexagon::LDrib:
2507 case Hexagon::STrib:
2508 case Hexagon::LDriub:
2509 return (Offset >= Hexagon_MEMB_OFFSET_MIN) &&
2510 (Offset <= Hexagon_MEMB_OFFSET_MAX);
2512 case Hexagon::ADD_ri:
2513 case Hexagon::TFR_FI:
2514 return (Offset >= Hexagon_ADDI_OFFSET_MIN) &&
2515 (Offset <= Hexagon_ADDI_OFFSET_MAX);
2517 case Hexagon::MEMw_ADDi_indexed_MEM_V4 :
2518 case Hexagon::MEMw_SUBi_indexed_MEM_V4 :
2519 case Hexagon::MEMw_ADDr_indexed_MEM_V4 :
2520 case Hexagon::MEMw_SUBr_indexed_MEM_V4 :
2521 case Hexagon::MEMw_ANDr_indexed_MEM_V4 :
2522 case Hexagon::MEMw_ORr_indexed_MEM_V4 :
2523 case Hexagon::MEMw_ADDi_MEM_V4 :
2524 case Hexagon::MEMw_SUBi_MEM_V4 :
2525 case Hexagon::MEMw_ADDr_MEM_V4 :
2526 case Hexagon::MEMw_SUBr_MEM_V4 :
2527 case Hexagon::MEMw_ANDr_MEM_V4 :
2528 case Hexagon::MEMw_ORr_MEM_V4 :
2529 assert ((Offset % 4) == 0 && "MEMOPw offset is not aligned correctly." );
2530 return (0 <= Offset && Offset <= 255);
2532 case Hexagon::MEMh_ADDi_indexed_MEM_V4 :
2533 case Hexagon::MEMh_SUBi_indexed_MEM_V4 :
2534 case Hexagon::MEMh_ADDr_indexed_MEM_V4 :
2535 case Hexagon::MEMh_SUBr_indexed_MEM_V4 :
2536 case Hexagon::MEMh_ANDr_indexed_MEM_V4 :
2537 case Hexagon::MEMh_ORr_indexed_MEM_V4 :
2538 case Hexagon::MEMh_ADDi_MEM_V4 :
2539 case Hexagon::MEMh_SUBi_MEM_V4 :
2540 case Hexagon::MEMh_ADDr_MEM_V4 :
2541 case Hexagon::MEMh_SUBr_MEM_V4 :
2542 case Hexagon::MEMh_ANDr_MEM_V4 :
2543 case Hexagon::MEMh_ORr_MEM_V4 :
2544 assert ((Offset % 2) == 0 && "MEMOPh offset is not aligned correctly." );
2545 return (0 <= Offset && Offset <= 127);
2547 case Hexagon::MEMb_ADDi_indexed_MEM_V4 :
2548 case Hexagon::MEMb_SUBi_indexed_MEM_V4 :
2549 case Hexagon::MEMb_ADDr_indexed_MEM_V4 :
2550 case Hexagon::MEMb_SUBr_indexed_MEM_V4 :
2551 case Hexagon::MEMb_ANDr_indexed_MEM_V4 :
2552 case Hexagon::MEMb_ORr_indexed_MEM_V4 :
2553 case Hexagon::MEMb_ADDi_MEM_V4 :
2554 case Hexagon::MEMb_SUBi_MEM_V4 :
2555 case Hexagon::MEMb_ADDr_MEM_V4 :
2556 case Hexagon::MEMb_SUBr_MEM_V4 :
2557 case Hexagon::MEMb_ANDr_MEM_V4 :
2558 case Hexagon::MEMb_ORr_MEM_V4 :
2559 return (0 <= Offset && Offset <= 63);
2561 // LDri_pred and STriw_pred are pseudo operations, so it has to take offset of
2562 // any size. Later pass knows how to handle it.
2563 case Hexagon::STriw_pred:
2564 case Hexagon::LDriw_pred:
2567 case Hexagon::LOOP0_i:
2568 return isUInt<10>(Offset);
2570 // INLINEASM is very special.
2571 case Hexagon::INLINEASM:
2575 llvm_unreachable("No offset range is defined for this opcode. "
2576 "Please define it in the above switch statement!");
2581 // Check if the Offset is a valid auto-inc imm by Load/Store Type.
2583 bool HexagonInstrInfo::
2584 isValidAutoIncImm(const EVT VT, const int Offset) const {
2586 if (VT == MVT::i64) {
2587 return (Offset >= Hexagon_MEMD_AUTOINC_MIN &&
2588 Offset <= Hexagon_MEMD_AUTOINC_MAX &&
2589 (Offset & 0x7) == 0);
2591 if (VT == MVT::i32) {
2592 return (Offset >= Hexagon_MEMW_AUTOINC_MIN &&
2593 Offset <= Hexagon_MEMW_AUTOINC_MAX &&
2594 (Offset & 0x3) == 0);
2596 if (VT == MVT::i16) {
2597 return (Offset >= Hexagon_MEMH_AUTOINC_MIN &&
2598 Offset <= Hexagon_MEMH_AUTOINC_MAX &&
2599 (Offset & 0x1) == 0);
2601 if (VT == MVT::i8) {
2602 return (Offset >= Hexagon_MEMB_AUTOINC_MIN &&
2603 Offset <= Hexagon_MEMB_AUTOINC_MAX);
2605 llvm_unreachable("Not an auto-inc opc!");
2609 bool HexagonInstrInfo::
2610 isMemOp(const MachineInstr *MI) const {
2611 switch (MI->getOpcode())
2613 default: return false;
2614 case Hexagon::MEMw_ADDi_indexed_MEM_V4 :
2615 case Hexagon::MEMw_SUBi_indexed_MEM_V4 :
2616 case Hexagon::MEMw_ADDr_indexed_MEM_V4 :
2617 case Hexagon::MEMw_SUBr_indexed_MEM_V4 :
2618 case Hexagon::MEMw_ANDr_indexed_MEM_V4 :
2619 case Hexagon::MEMw_ORr_indexed_MEM_V4 :
2620 case Hexagon::MEMw_ADDi_MEM_V4 :
2621 case Hexagon::MEMw_SUBi_MEM_V4 :
2622 case Hexagon::MEMw_ADDr_MEM_V4 :
2623 case Hexagon::MEMw_SUBr_MEM_V4 :
2624 case Hexagon::MEMw_ANDr_MEM_V4 :
2625 case Hexagon::MEMw_ORr_MEM_V4 :
2626 case Hexagon::MEMh_ADDi_indexed_MEM_V4 :
2627 case Hexagon::MEMh_SUBi_indexed_MEM_V4 :
2628 case Hexagon::MEMh_ADDr_indexed_MEM_V4 :
2629 case Hexagon::MEMh_SUBr_indexed_MEM_V4 :
2630 case Hexagon::MEMh_ANDr_indexed_MEM_V4 :
2631 case Hexagon::MEMh_ORr_indexed_MEM_V4 :
2632 case Hexagon::MEMh_ADDi_MEM_V4 :
2633 case Hexagon::MEMh_SUBi_MEM_V4 :
2634 case Hexagon::MEMh_ADDr_MEM_V4 :
2635 case Hexagon::MEMh_SUBr_MEM_V4 :
2636 case Hexagon::MEMh_ANDr_MEM_V4 :
2637 case Hexagon::MEMh_ORr_MEM_V4 :
2638 case Hexagon::MEMb_ADDi_indexed_MEM_V4 :
2639 case Hexagon::MEMb_SUBi_indexed_MEM_V4 :
2640 case Hexagon::MEMb_ADDr_indexed_MEM_V4 :
2641 case Hexagon::MEMb_SUBr_indexed_MEM_V4 :
2642 case Hexagon::MEMb_ANDr_indexed_MEM_V4 :
2643 case Hexagon::MEMb_ORr_indexed_MEM_V4 :
2644 case Hexagon::MEMb_ADDi_MEM_V4 :
2645 case Hexagon::MEMb_SUBi_MEM_V4 :
2646 case Hexagon::MEMb_ADDr_MEM_V4 :
2647 case Hexagon::MEMb_SUBr_MEM_V4 :
2648 case Hexagon::MEMb_ANDr_MEM_V4 :
2649 case Hexagon::MEMb_ORr_MEM_V4 :
2655 bool HexagonInstrInfo::
2656 isSpillPredRegOp(const MachineInstr *MI) const {
2657 switch (MI->getOpcode()) {
2658 default: return false;
2659 case Hexagon::STriw_pred :
2660 case Hexagon::LDriw_pred :
2665 bool HexagonInstrInfo::isNewValueJumpCandidate(const MachineInstr *MI) const {
2666 switch (MI->getOpcode()) {
2667 default: return false;
2668 case Hexagon::CMPEQrr:
2669 case Hexagon::CMPEQri:
2670 case Hexagon::CMPLTrr:
2671 case Hexagon::CMPGTrr:
2672 case Hexagon::CMPGTri:
2673 case Hexagon::CMPLTUrr:
2674 case Hexagon::CMPGTUrr:
2675 case Hexagon::CMPGTUri:
2676 case Hexagon::CMPGEri:
2677 case Hexagon::CMPGEUri:
2682 bool HexagonInstrInfo::
2683 isConditionalTransfer (const MachineInstr *MI) const {
2684 switch (MI->getOpcode()) {
2685 default: return false;
2686 case Hexagon::TFR_cPt:
2687 case Hexagon::TFR_cNotPt:
2688 case Hexagon::TFRI_cPt:
2689 case Hexagon::TFRI_cNotPt:
2690 case Hexagon::TFR_cdnPt:
2691 case Hexagon::TFR_cdnNotPt:
2692 case Hexagon::TFRI_cdnPt:
2693 case Hexagon::TFRI_cdnNotPt:
2698 bool HexagonInstrInfo::isConditionalALU32 (const MachineInstr* MI) const {
2699 const HexagonRegisterInfo& QRI = getRegisterInfo();
2700 switch (MI->getOpcode())
2702 default: return false;
2703 case Hexagon::ADD_ri_cPt:
2704 case Hexagon::ADD_ri_cNotPt:
2705 case Hexagon::ADD_rr_cPt:
2706 case Hexagon::ADD_rr_cNotPt:
2707 case Hexagon::XOR_rr_cPt:
2708 case Hexagon::XOR_rr_cNotPt:
2709 case Hexagon::AND_rr_cPt:
2710 case Hexagon::AND_rr_cNotPt:
2711 case Hexagon::OR_rr_cPt:
2712 case Hexagon::OR_rr_cNotPt:
2713 case Hexagon::SUB_rr_cPt:
2714 case Hexagon::SUB_rr_cNotPt:
2715 case Hexagon::COMBINE_rr_cPt:
2716 case Hexagon::COMBINE_rr_cNotPt:
2718 case Hexagon::ASLH_cPt_V4:
2719 case Hexagon::ASLH_cNotPt_V4:
2720 case Hexagon::ASRH_cPt_V4:
2721 case Hexagon::ASRH_cNotPt_V4:
2722 case Hexagon::SXTB_cPt_V4:
2723 case Hexagon::SXTB_cNotPt_V4:
2724 case Hexagon::SXTH_cPt_V4:
2725 case Hexagon::SXTH_cNotPt_V4:
2726 case Hexagon::ZXTB_cPt_V4:
2727 case Hexagon::ZXTB_cNotPt_V4:
2728 case Hexagon::ZXTH_cPt_V4:
2729 case Hexagon::ZXTH_cNotPt_V4:
2730 return QRI.Subtarget.hasV4TOps();
2734 bool HexagonInstrInfo::
2735 isConditionalLoad (const MachineInstr* MI) const {
2736 const HexagonRegisterInfo& QRI = getRegisterInfo();
2737 switch (MI->getOpcode())
2739 default: return false;
2740 case Hexagon::LDrid_cPt :
2741 case Hexagon::LDrid_cNotPt :
2742 case Hexagon::LDrid_indexed_cPt :
2743 case Hexagon::LDrid_indexed_cNotPt :
2744 case Hexagon::LDriw_cPt :
2745 case Hexagon::LDriw_cNotPt :
2746 case Hexagon::LDriw_indexed_cPt :
2747 case Hexagon::LDriw_indexed_cNotPt :
2748 case Hexagon::LDrih_cPt :
2749 case Hexagon::LDrih_cNotPt :
2750 case Hexagon::LDrih_indexed_cPt :
2751 case Hexagon::LDrih_indexed_cNotPt :
2752 case Hexagon::LDrib_cPt :
2753 case Hexagon::LDrib_cNotPt :
2754 case Hexagon::LDrib_indexed_cPt :
2755 case Hexagon::LDrib_indexed_cNotPt :
2756 case Hexagon::LDriuh_cPt :
2757 case Hexagon::LDriuh_cNotPt :
2758 case Hexagon::LDriuh_indexed_cPt :
2759 case Hexagon::LDriuh_indexed_cNotPt :
2760 case Hexagon::LDriub_cPt :
2761 case Hexagon::LDriub_cNotPt :
2762 case Hexagon::LDriub_indexed_cPt :
2763 case Hexagon::LDriub_indexed_cNotPt :
2765 case Hexagon::POST_LDrid_cPt :
2766 case Hexagon::POST_LDrid_cNotPt :
2767 case Hexagon::POST_LDriw_cPt :
2768 case Hexagon::POST_LDriw_cNotPt :
2769 case Hexagon::POST_LDrih_cPt :
2770 case Hexagon::POST_LDrih_cNotPt :
2771 case Hexagon::POST_LDrib_cPt :
2772 case Hexagon::POST_LDrib_cNotPt :
2773 case Hexagon::POST_LDriuh_cPt :
2774 case Hexagon::POST_LDriuh_cNotPt :
2775 case Hexagon::POST_LDriub_cPt :
2776 case Hexagon::POST_LDriub_cNotPt :
2777 return QRI.Subtarget.hasV4TOps();
2778 case Hexagon::LDrid_indexed_shl_cPt_V4 :
2779 case Hexagon::LDrid_indexed_shl_cNotPt_V4 :
2780 case Hexagon::LDrib_indexed_shl_cPt_V4 :
2781 case Hexagon::LDrib_indexed_shl_cNotPt_V4 :
2782 case Hexagon::LDriub_indexed_shl_cPt_V4 :
2783 case Hexagon::LDriub_indexed_shl_cNotPt_V4 :
2784 case Hexagon::LDrih_indexed_shl_cPt_V4 :
2785 case Hexagon::LDrih_indexed_shl_cNotPt_V4 :
2786 case Hexagon::LDriuh_indexed_shl_cPt_V4 :
2787 case Hexagon::LDriuh_indexed_shl_cNotPt_V4 :
2788 case Hexagon::LDriw_indexed_shl_cPt_V4 :
2789 case Hexagon::LDriw_indexed_shl_cNotPt_V4 :
2790 return QRI.Subtarget.hasV4TOps();
2794 // Returns true if an instruction is a conditional store.
2796 // Note: It doesn't include conditional new-value stores as they can't be
2797 // converted to .new predicate.
2799 // p.new NV store [ if(p0.new)memw(R0+#0)=R2.new ]
2801 // / \ (not OK. it will cause new-value store to be
2802 // / X conditional on p0.new while R2 producer is
2805 // p.new store p.old NV store
2806 // [if(p0.new)memw(R0+#0)=R2] [if(p0)memw(R0+#0)=R2.new]
2812 // [if (p0)memw(R0+#0)=R2]
2814 // The above diagram shows the steps involoved in the conversion of a predicated
2815 // store instruction to its .new predicated new-value form.
2817 // The following set of instructions further explains the scenario where
2818 // conditional new-value store becomes invalid when promoted to .new predicate
2821 // { 1) if (p0) r0 = add(r1, r2)
2822 // 2) p0 = cmp.eq(r3, #0) }
2824 // 3) if (p0) memb(r1+#0) = r0 --> this instruction can't be grouped with
2825 // the first two instructions because in instr 1, r0 is conditional on old value
2826 // of p0 but its use in instr 3 is conditional on p0 modified by instr 2 which
2827 // is not valid for new-value stores.
2828 bool HexagonInstrInfo::
2829 isConditionalStore (const MachineInstr* MI) const {
2830 const HexagonRegisterInfo& QRI = getRegisterInfo();
2831 switch (MI->getOpcode())
2833 default: return false;
2834 case Hexagon::STrib_imm_cPt_V4 :
2835 case Hexagon::STrib_imm_cNotPt_V4 :
2836 case Hexagon::STrib_indexed_shl_cPt_V4 :
2837 case Hexagon::STrib_indexed_shl_cNotPt_V4 :
2838 case Hexagon::STrib_cPt :
2839 case Hexagon::STrib_cNotPt :
2840 case Hexagon::POST_STbri_cPt :
2841 case Hexagon::POST_STbri_cNotPt :
2842 case Hexagon::STrid_indexed_cPt :
2843 case Hexagon::STrid_indexed_cNotPt :
2844 case Hexagon::STrid_indexed_shl_cPt_V4 :
2845 case Hexagon::POST_STdri_cPt :
2846 case Hexagon::POST_STdri_cNotPt :
2847 case Hexagon::STrih_cPt :
2848 case Hexagon::STrih_cNotPt :
2849 case Hexagon::STrih_indexed_cPt :
2850 case Hexagon::STrih_indexed_cNotPt :
2851 case Hexagon::STrih_imm_cPt_V4 :
2852 case Hexagon::STrih_imm_cNotPt_V4 :
2853 case Hexagon::STrih_indexed_shl_cPt_V4 :
2854 case Hexagon::STrih_indexed_shl_cNotPt_V4 :
2855 case Hexagon::POST_SThri_cPt :
2856 case Hexagon::POST_SThri_cNotPt :
2857 case Hexagon::STriw_cPt :
2858 case Hexagon::STriw_cNotPt :
2859 case Hexagon::STriw_indexed_cPt :
2860 case Hexagon::STriw_indexed_cNotPt :
2861 case Hexagon::STriw_imm_cPt_V4 :
2862 case Hexagon::STriw_imm_cNotPt_V4 :
2863 case Hexagon::STriw_indexed_shl_cPt_V4 :
2864 case Hexagon::STriw_indexed_shl_cNotPt_V4 :
2865 case Hexagon::POST_STwri_cPt :
2866 case Hexagon::POST_STwri_cNotPt :
2867 return QRI.Subtarget.hasV4TOps();
2869 // V4 global address store before promoting to dot new.
2870 case Hexagon::STrid_GP_cPt_V4 :
2871 case Hexagon::STrid_GP_cNotPt_V4 :
2872 case Hexagon::STrib_GP_cPt_V4 :
2873 case Hexagon::STrib_GP_cNotPt_V4 :
2874 case Hexagon::STrih_GP_cPt_V4 :
2875 case Hexagon::STrih_GP_cNotPt_V4 :
2876 case Hexagon::STriw_GP_cPt_V4 :
2877 case Hexagon::STriw_GP_cNotPt_V4 :
2878 case Hexagon::STd_GP_cPt_V4 :
2879 case Hexagon::STd_GP_cNotPt_V4 :
2880 case Hexagon::STb_GP_cPt_V4 :
2881 case Hexagon::STb_GP_cNotPt_V4 :
2882 case Hexagon::STh_GP_cPt_V4 :
2883 case Hexagon::STh_GP_cNotPt_V4 :
2884 case Hexagon::STw_GP_cPt_V4 :
2885 case Hexagon::STw_GP_cNotPt_V4 :
2886 return QRI.Subtarget.hasV4TOps();
2888 // Predicated new value stores (i.e. if (p0) memw(..)=r0.new) are excluded
2889 // from the "Conditional Store" list. Because a predicated new value store
2890 // would NOT be promoted to a double dot new store. See diagram below:
2891 // This function returns yes for those stores that are predicated but not
2892 // yet promoted to predicate dot new instructions.
2894 // +---------------------+
2895 // /-----| if (p0) memw(..)=r0 |---------\~
2896 // || +---------------------+ ||
2897 // promote || /\ /\ || promote
2899 // \||/ demote || \||/
2901 // +-------------------------+ || +-------------------------+
2902 // | if (p0.new) memw(..)=r0 | || | if (p0) memw(..)=r0.new |
2903 // +-------------------------+ || +-------------------------+
2906 // promote || \/ NOT possible
2910 // +-----------------------------+
2911 // | if (p0.new) memw(..)=r0.new |
2912 // +-----------------------------+
2913 // Double Dot New Store
2920 DFAPacketizer *HexagonInstrInfo::
2921 CreateTargetScheduleState(const TargetMachine *TM,
2922 const ScheduleDAG *DAG) const {
2923 const InstrItineraryData *II = TM->getInstrItineraryData();
2924 return TM->getSubtarget<HexagonGenSubtargetInfo>().createDFAPacketizer(II);
2927 bool HexagonInstrInfo::isSchedulingBoundary(const MachineInstr *MI,
2928 const MachineBasicBlock *MBB,
2929 const MachineFunction &MF) const {
2930 // Debug info is never a scheduling boundary. It's necessary to be explicit
2931 // due to the special treatment of IT instructions below, otherwise a
2932 // dbg_value followed by an IT will result in the IT instruction being
2933 // considered a scheduling hazard, which is wrong. It should be the actual
2934 // instruction preceding the dbg_value instruction(s), just like it is
2935 // when debug info is not present.
2936 if (MI->isDebugValue())
2939 // Terminators and labels can't be scheduled around.
2940 if (MI->getDesc().isTerminator() || MI->isLabel() || MI->isInlineAsm())