1 //==- HexagonInstrFormats.td - Hexagon Instruction Formats --*- tablegen -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Hexagon Instruction Flags +
13 // *** Must match HexagonBaseInfo.h ***
14 //===----------------------------------------------------------------------===//
16 class IType<bits<5> t> {
19 def TypePSEUDO : IType<0>;
20 def TypeALU32 : IType<1>;
21 def TypeCR : IType<2>;
22 def TypeJR : IType<3>;
24 def TypeLD : IType<5>;
25 def TypeST : IType<6>;
26 def TypeSYSTEM : IType<7>;
27 def TypeXTYPE : IType<8>;
28 def TypeENDLOOP: IType<31>;
30 // Maintain list of valid subtargets for each instruction.
31 class SubTarget<bits<6> value> {
32 bits<6> Value = value;
35 def HasAnySubT : SubTarget<0x3f>; // 111111
36 def HasV5SubT : SubTarget<0x3e>; // 111110
38 // Addressing modes for load/store instructions
39 class AddrModeType<bits<3> value> {
40 bits<3> Value = value;
43 def NoAddrMode : AddrModeType<0>; // No addressing mode
44 def Absolute : AddrModeType<1>; // Absolute addressing mode
45 def AbsoluteSet : AddrModeType<2>; // Absolute set addressing mode
46 def BaseImmOffset : AddrModeType<3>; // Indirect with offset
47 def BaseLongOffset : AddrModeType<4>; // Indirect with long offset
48 def BaseRegOffset : AddrModeType<5>; // Indirect with register offset
49 def PostInc : AddrModeType<6>; // Post increment addressing mode
51 class MemAccessSize<bits<4> value> {
52 bits<4> Value = value;
55 def NoMemAccess : MemAccessSize<0>;// Not a memory acces instruction.
56 def ByteAccess : MemAccessSize<1>;// Byte access instruction (memb).
57 def HalfWordAccess : MemAccessSize<2>;// Half word access instruction (memh).
58 def WordAccess : MemAccessSize<3>;// Word access instruction (memw).
59 def DoubleWordAccess : MemAccessSize<4>;// Double word access instruction (memd)
62 //===----------------------------------------------------------------------===//
63 // Instruction Class Declaration +
64 //===----------------------------------------------------------------------===//
67 field bits<32> Inst = ?; // Default to an invalid insn.
68 bits<4> IClass = 0; // ICLASS
70 let Inst{31-28} = IClass;
75 class InstHexagon<dag outs, dag ins, string asmstr, list<dag> pattern,
76 string cstr, InstrItinClass itin, IType type>
78 let Namespace = "Hexagon";
80 dag OutOperandList = outs;
81 dag InOperandList = ins;
82 let AsmString = asmstr;
83 let Pattern = pattern;
84 let Constraints = cstr;
88 // SoftFail is a field the disassembler can use to provide a way for
89 // instructions to not match without killing the whole decode process. It is
90 // mainly used for ARM, but Tablegen expects this field to exist or it fails
91 // to build the decode table.
92 field bits<32> SoftFail = 0;
94 // *** Must match MCTargetDesc/HexagonBaseInfo.h ***
96 // Instruction type according to the ISA.
98 let TSFlags{4-0} = Type.Value;
100 // Solo instructions, i.e., those that cannot be in a packet with others.
102 let TSFlags{5} = isSolo;
103 // Packed only with A or X-type instructions.
104 bits<1> isSoloAX = 0;
105 let TSFlags{6} = isSoloAX;
106 // Only A-type instruction in first slot or nothing.
107 bits<1> isSoloAin1 = 0;
108 let TSFlags{7} = isSoloAin1;
110 // Predicated instructions.
111 bits<1> isPredicated = 0;
112 let TSFlags{8} = isPredicated;
113 bits<1> isPredicatedFalse = 0;
114 let TSFlags{9} = isPredicatedFalse;
115 bits<1> isPredicatedNew = 0;
116 let TSFlags{10} = isPredicatedNew;
117 bits<1> isPredicateLate = 0;
118 let TSFlags{11} = isPredicateLate; // Late predicate producer insn.
120 // New-value insn helper fields.
121 bits<1> isNewValue = 0;
122 let TSFlags{12} = isNewValue; // New-value consumer insn.
123 bits<1> hasNewValue = 0;
124 let TSFlags{13} = hasNewValue; // New-value producer insn.
125 bits<3> opNewValue = 0;
126 let TSFlags{16-14} = opNewValue; // New-value produced operand.
127 bits<1> isNVStorable = 0;
128 let TSFlags{17} = isNVStorable; // Store that can become new-value store.
129 bits<1> isNVStore = 0;
130 let TSFlags{18} = isNVStore; // New-value store insn.
131 bits<1> isCVLoadable = 0;
132 let TSFlags{19} = isCVLoadable; // Load that can become cur-value load.
133 bits<1> isCVLoad = 0;
134 let TSFlags{20} = isCVLoad; // Cur-value load insn.
136 // Immediate extender helper fields.
137 bits<1> isExtendable = 0;
138 let TSFlags{21} = isExtendable; // Insn may be extended.
139 bits<1> isExtended = 0;
140 let TSFlags{22} = isExtended; // Insn must be extended.
141 bits<3> opExtendable = 0;
142 let TSFlags{25-23} = opExtendable; // Which operand may be extended.
143 bits<1> isExtentSigned = 0;
144 let TSFlags{26} = isExtentSigned; // Signed or unsigned range.
145 bits<5> opExtentBits = 0;
146 let TSFlags{31-27} = opExtentBits; //Number of bits of range before extending.
147 bits<2> opExtentAlign = 0;
148 let TSFlags{33-32} = opExtentAlign; // Alignment exponent before extending.
150 // If an instruction is valid on a subtarget, set the corresponding
151 // bit from validSubTargets.
152 // By default, instruction is valid on all subtargets.
153 SubTarget validSubTargets = HasAnySubT;
154 let TSFlags{39-34} = validSubTargets.Value;
156 // Addressing mode for load/store instructions.
157 AddrModeType addrMode = NoAddrMode;
158 let TSFlags{42-40} = addrMode.Value;
160 // Memory access size for mem access instructions (load/store)
161 MemAccessSize accessSize = NoMemAccess;
162 let TSFlags{46-43} = accessSize.Value;
165 let TSFlags {47} = isTaken; // Branch prediction.
168 let TSFlags {48} = isFP; // Floating-point.
170 // Fields used for relation models.
171 string BaseOpcode = "";
172 string CextOpcode = "";
173 string PredSense = "";
174 string PNewValue = "";
175 string NValueST = ""; // Set to "true" for new-value stores.
176 string InputType = ""; // Input is "imm" or "reg" type.
177 string isMEMri = "false"; // Set to "true" for load/store with MEMri operand.
178 string isFloat = "false"; // Set to "true" for the floating-point load/store.
179 string isBrTaken = !if(isTaken, "true", "false"); // Set to "true"/"false" for jump instructions
181 let PredSense = !if(isPredicated, !if(isPredicatedFalse, "false", "true"),
183 let PNewValue = !if(isPredicatedNew, "new", "");
184 let NValueST = !if(isNVStore, "true", "false");
186 // *** Must match MCTargetDesc/HexagonBaseInfo.h ***
189 //===----------------------------------------------------------------------===//
190 // Instruction Classes Definitions +
191 //===----------------------------------------------------------------------===//
193 // LD Instruction Class in V2/V3/V4.
194 // Definition of the instruction class NOT CHANGED.
196 class LDInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
197 string cstr = "", InstrItinClass itin = LD_tc_ld_SLOT01>
198 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeLD>, OpcodeHexagon;
201 class LDInst2<dag outs, dag ins, string asmstr, list<dag> pattern = [],
203 : LDInst<outs, ins, asmstr, pattern, cstr>;
205 class CONSTLDInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
207 : LDInst<outs, ins, asmstr, pattern, cstr>;
209 // LD Instruction Class in V2/V3/V4.
210 // Definition of the instruction class NOT CHANGED.
211 class LDInstPost<dag outs, dag ins, string asmstr, list<dag> pattern = [],
213 : LDInst<outs, ins, asmstr, pattern, cstr>;
216 class LD0Inst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
217 string cstr = "", InstrItinClass itin=LD_tc_ld_SLOT0>
218 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeLD>, OpcodeHexagon;
220 // ST Instruction Class in V2/V3 can take SLOT0 only.
221 // ST Instruction Class in V4 can take SLOT0 & SLOT1.
222 // Definition of the instruction class CHANGED from V2/V3 to V4.
224 class STInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
225 string cstr = "", InstrItinClass itin = ST_tc_st_SLOT01>
226 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeST>, OpcodeHexagon;
228 class STInst2<dag outs, dag ins, string asmstr, list<dag> pattern = [],
230 : STInst<outs, ins, asmstr, pattern, cstr>;
233 class ST0Inst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
234 string cstr = "", InstrItinClass itin = ST_tc_ld_SLOT0>
235 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeST>, OpcodeHexagon;
237 // ST Instruction Class in V2/V3 can take SLOT0 only.
238 // ST Instruction Class in V4 can take SLOT0 & SLOT1.
239 // Definition of the instruction class CHANGED from V2/V3 to V4.
240 class STInstPost<dag outs, dag ins, string asmstr, list<dag> pattern = [],
241 string cstr = "", InstrItinClass itin = ST_tc_st_SLOT01>
242 : STInst<outs, ins, asmstr, pattern, cstr, itin>;
244 // SYSTEM Instruction Class in V4 can take SLOT0 only
245 // In V2/V3 we used ST for this but in v4 ST can take SLOT0 or SLOT1.
246 class SYSInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
247 string cstr = "", InstrItinClass itin = ST_tc_3stall_SLOT0>
248 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeSYSTEM>,
251 // ALU32 Instruction Class in V2/V3/V4.
252 // Definition of the instruction class NOT CHANGED.
253 class ALU32Inst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
254 string cstr = "", InstrItinClass itin = ALU32_2op_tc_1_SLOT0123>
255 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeALU32>, OpcodeHexagon;
257 // ALU64 Instruction Class in V2/V3.
258 // XTYPE Instruction Class in V4.
259 // Definition of the instruction class NOT CHANGED.
260 // Name of the Instruction Class changed from ALU64 to XTYPE from V2/V3 to V4.
261 class ALU64Inst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
262 string cstr = "", InstrItinClass itin = ALU64_tc_2_SLOT23>
263 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeXTYPE>,
266 class ALU64_acc<dag outs, dag ins, string asmstr, list<dag> pattern = [],
267 string cstr = "", InstrItinClass itin = ALU64_tc_2_SLOT23>
268 : ALU64Inst<outs, ins, asmstr, pattern, cstr, itin>;
271 // M Instruction Class in V2/V3.
272 // XTYPE Instruction Class in V4.
273 // Definition of the instruction class NOT CHANGED.
274 // Name of the Instruction Class changed from M to XTYPE from V2/V3 to V4.
275 class MInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
276 string cstr = "", InstrItinClass itin = M_tc_3x_SLOT23>
277 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeXTYPE>,
280 // M Instruction Class in V2/V3.
281 // XTYPE Instruction Class in V4.
282 // Definition of the instruction class NOT CHANGED.
283 // Name of the Instruction Class changed from M to XTYPE from V2/V3 to V4.
284 class MInst_acc<dag outs, dag ins, string asmstr, list<dag> pattern = [],
285 string cstr = "", InstrItinClass itin = M_tc_2_SLOT23>
286 : MInst<outs, ins, asmstr, pattern, cstr, itin>;
288 // S Instruction Class in V2/V3.
289 // XTYPE Instruction Class in V4.
290 // Definition of the instruction class NOT CHANGED.
291 // Name of the Instruction Class changed from S to XTYPE from V2/V3 to V4.
292 class SInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
293 string cstr = "", InstrItinClass itin = S_2op_tc_1_SLOT23>
294 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeXTYPE>,
297 // S Instruction Class in V2/V3.
298 // XTYPE Instruction Class in V4.
299 // Definition of the instruction class NOT CHANGED.
300 // Name of the Instruction Class changed from S to XTYPE from V2/V3 to V4.
301 class SInst_acc<dag outs, dag ins, string asmstr, list<dag> pattern = [],
302 string cstr = "", InstrItinClass itin = S_3op_tc_1_SLOT23>
303 : SInst<outs, ins, asmstr, pattern, cstr, itin>;
305 // J Instruction Class in V2/V3/V4.
306 // Definition of the instruction class NOT CHANGED.
307 class JInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
308 string cstr = "", InstrItinClass itin = J_tc_2early_SLOT23>
309 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeJ>, OpcodeHexagon;
311 // JR Instruction Class in V2/V3/V4.
312 // Definition of the instruction class NOT CHANGED.
313 class JRInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
314 string cstr = "", InstrItinClass itin = J_tc_2early_SLOT2>
315 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeJR>, OpcodeHexagon;
317 // CR Instruction Class in V2/V3/V4.
318 // Definition of the instruction class NOT CHANGED.
319 class CRInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
320 string cstr = "", InstrItinClass itin = CR_tc_2early_SLOT3>
321 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCR>, OpcodeHexagon;
323 let isCodeGenOnly = 1, isPseudo = 1 in
324 class Endloop<dag outs, dag ins, string asmstr, list<dag> pattern = [],
325 string cstr = "", InstrItinClass itin = J_tc_2early_SLOT0123>
326 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeENDLOOP>,
329 let isCodeGenOnly = 1, isPseudo = 1 in
330 class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern = [],
332 : InstHexagon<outs, ins, asmstr, pattern, cstr, PSEUDO, TypePSEUDO>,
335 let isCodeGenOnly = 1, isPseudo = 1 in
336 class PseudoM<dag outs, dag ins, string asmstr, list<dag> pattern = [],
338 : InstHexagon<outs, ins, asmstr, pattern, cstr, PSEUDOM, TypePSEUDO>,
341 //===----------------------------------------------------------------------===//
342 // Instruction Classes Definitions -
343 //===----------------------------------------------------------------------===//
349 class ALU32_rr<dag outs, dag ins, string asmstr, list<dag> pattern = [],
350 string cstr = "", InstrItinClass itin = ALU32_2op_tc_1_SLOT0123>
351 : ALU32Inst<outs, ins, asmstr, pattern, cstr, itin>;
353 class ALU32_ir<dag outs, dag ins, string asmstr, list<dag> pattern = [],
354 string cstr = "", InstrItinClass itin = ALU32_2op_tc_1_SLOT0123>
355 : ALU32Inst<outs, ins, asmstr, pattern, cstr, itin>;
357 class ALU32_ri<dag outs, dag ins, string asmstr, list<dag> pattern = [],
358 string cstr = "", InstrItinClass itin = ALU32_2op_tc_1_SLOT0123>
359 : ALU32Inst<outs, ins, asmstr, pattern, cstr, itin>;
361 class ALU32_ii<dag outs, dag ins, string asmstr, list<dag> pattern = [],
362 string cstr = "", InstrItinClass itin = ALU32_2op_tc_1_SLOT0123>
363 : ALU32Inst<outs, ins, asmstr, pattern, cstr, itin>;
368 class ALU64_rr<dag outs, dag ins, string asmstr, list<dag> pattern = [],
369 string cstr = "", InstrItinClass itin = ALU64_tc_1_SLOT23>
370 : ALU64Inst<outs, ins, asmstr, pattern, cstr, itin>;
372 class ALU64_ri<dag outs, dag ins, string asmstr, list<dag> pattern = [],
373 string cstr = "", InstrItinClass itin = ALU64_tc_1_SLOT23>
374 : ALU64Inst<outs, ins, asmstr, pattern, cstr, itin>;
376 // Post increment ST Instruction.
377 class STInstPI<dag outs, dag ins, string asmstr, list<dag> pattern = [],
379 : STInst<outs, ins, asmstr, pattern, cstr>;
382 class STInst2PI<dag outs, dag ins, string asmstr, list<dag> pattern = [],
384 : STInst<outs, ins, asmstr, pattern, cstr>;
386 // Post increment LD Instruction.
387 class LDInstPI<dag outs, dag ins, string asmstr, list<dag> pattern = [],
389 : LDInst<outs, ins, asmstr, pattern, cstr>;
392 class LDInst2PI<dag outs, dag ins, string asmstr, list<dag> pattern = [],
394 : LDInst<outs, ins, asmstr, pattern, cstr>;
396 //===----------------------------------------------------------------------===//
397 // V4 Instruction Format Definitions +
398 //===----------------------------------------------------------------------===//
400 include "HexagonInstrFormatsV4.td"
402 //===----------------------------------------------------------------------===//
403 // V4 Instruction Format Definitions +
404 //===----------------------------------------------------------------------===//