1 //===-- HexagonISelLowering.h - Hexagon DAG Lowering Interface --*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Hexagon uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONISELLOWERING_H
16 #define LLVM_LIB_TARGET_HEXAGON_HEXAGONISELLOWERING_H
19 #include "llvm/CodeGen/CallingConvLower.h"
20 #include "llvm/IR/CallingConv.h"
21 #include "llvm/Target/TargetLowering.h"
25 // Return true when the given node fits in a positive half word.
26 bool isPositiveHalfWord(SDNode *N);
28 namespace HexagonISD {
29 enum NodeType : unsigned {
30 OP_BEGIN = ISD::BUILTIN_OP_END,
33 CONST32_GP, // For marking data present in GP.
42 CALLv3, // A V3+ call instruction.
43 CALLv3nr, // A V3+ call instruction that doesn't return.
46 RET_FLAG, // Return with a flag operand.
47 BR_JT, // Branch through jump table.
48 BARRIER, // Memory barrier.
92 class HexagonSubtarget;
94 class HexagonTargetLowering : public TargetLowering {
95 int VarArgsFrameOffset; // Frame offset to start of varargs area.
97 bool CanReturnSmallStruct(const Function* CalleeFn, unsigned& RetSize)
99 void promoteLdStType(EVT VT, EVT PromotedLdStVT);
100 const HexagonTargetMachine &HTM;
101 const HexagonSubtarget &Subtarget;
104 explicit HexagonTargetLowering(const TargetMachine &TM,
105 const HexagonSubtarget &ST);
107 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
108 /// for tail call optimization. Targets which want to do tail call
109 /// optimization should implement this function.
110 bool IsEligibleForTailCallOptimization(SDValue Callee,
111 CallingConv::ID CalleeCC, bool isVarArg, bool isCalleeStructRet,
112 bool isCallerStructRet, const SmallVectorImpl<ISD::OutputArg> &Outs,
113 const SmallVectorImpl<SDValue> &OutVals,
114 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG& DAG) const;
116 bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
117 bool isTruncateFree(EVT VT1, EVT VT2) const override;
119 bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override;
121 // Should we expand the build vector with shuffles?
122 bool shouldExpandBuildVectorWithShuffles(EVT VT,
123 unsigned DefinedValues) const override;
125 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
126 const char *getTargetNodeName(unsigned Opcode) const override;
127 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
128 SDValue LowerEXTRACT_VECTOR(SDValue Op, SelectionDAG &DAG) const;
129 SDValue LowerINSERT_VECTOR(SDValue Op, SelectionDAG &DAG) const;
130 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
131 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
132 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
133 SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const;
134 SDValue LowerEH_LABEL(SDValue Op, SelectionDAG &DAG) const;
135 SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
136 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
137 bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl,
138 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const override;
139 SDValue LowerGLOBALADDRESS(SDValue Op, SelectionDAG &DAG) const;
140 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
142 SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
143 SmallVectorImpl<SDValue> &InVals) const override;
144 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
145 CallingConv::ID CallConv, bool isVarArg,
146 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl,
147 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals,
148 const SmallVectorImpl<SDValue> &OutVals, SDValue Callee) const;
150 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
151 SDValue LowerVSELECT(SDValue Op, SelectionDAG &DAG) const;
152 SDValue LowerCTPOP(SDValue Op, SelectionDAG &DAG) const;
153 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
154 SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
155 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
156 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
158 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv,
159 bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs,
160 const SmallVectorImpl<SDValue> &OutVals, SDLoc dl,
161 SelectionDAG &DAG) const override;
163 bool mayBeEmittedAsTailCall(CallInst *CI) const override;
164 MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr *MI,
165 MachineBasicBlock *BB) const override;
167 /// If a physical register, this returns the register that receives the
168 /// exception address on entry to an EH pad.
170 getExceptionPointerRegister(const Constant *PersonalityFn) const override {
174 /// If a physical register, this returns the register that receives the
175 /// exception typeid on entry to a landing pad.
177 getExceptionSelectorRegister(const Constant *PersonalityFn) const override {
181 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
182 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
183 EVT getSetCCResultType(const DataLayout &, LLVMContext &C,
184 EVT VT) const override {
188 return EVT::getVectorVT(C, MVT::i1, VT.getVectorNumElements());
191 bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
192 SDValue &Base, SDValue &Offset,
193 ISD::MemIndexedMode &AM,
194 SelectionDAG &DAG) const override;
196 std::pair<unsigned, const TargetRegisterClass *>
197 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
198 StringRef Constraint, MVT VT) const override;
201 getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
202 if (ConstraintCode == "o")
203 return InlineAsm::Constraint_o;
204 else if (ConstraintCode == "v")
205 return InlineAsm::Constraint_v;
206 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
210 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
211 /// isLegalAddressingMode - Return true if the addressing mode represented
212 /// by AM is legal for this target, for a load/store of the specified type.
213 /// The type may be VoidTy, in which case only return true if the addressing
214 /// mode is legal for a load/store of any legal type.
215 /// TODO: Handle pre/postinc as well.
216 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
217 Type *Ty, unsigned AS) const override;
218 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
220 /// isLegalICmpImmediate - Return true if the specified immediate is legal
221 /// icmp immediate, that is the target has icmp instructions which can
222 /// compare a register against the immediate without having to materialize
223 /// the immediate into a register.
224 bool isLegalICmpImmediate(int64_t Imm) const override;
226 // Handling of atomic RMW instructions.
227 Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
228 AtomicOrdering Ord) const override;
229 Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val,
230 Value *Addr, AtomicOrdering Ord) const override;
231 AtomicExpansionKind shouldExpandAtomicLoadInIR(LoadInst *LI) const override;
232 bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
234 shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override {
235 return AtomicExpansionKind::LLSC;
239 std::pair<const TargetRegisterClass*, uint8_t>
240 findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT)
243 } // end namespace llvm
245 #endif // Hexagon_ISELLOWERING_H