1 //===-- HexagonISelLowering.cpp - Hexagon DAG Lowering Implementation -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the interfaces that Hexagon uses to lower LLVM code
11 // into a selection DAG.
13 //===----------------------------------------------------------------------===//
15 #include "HexagonISelLowering.h"
16 #include "HexagonMachineFunctionInfo.h"
17 #include "HexagonSubtarget.h"
18 #include "HexagonTargetMachine.h"
19 #include "HexagonTargetObjectFile.h"
20 #include "llvm/CodeGen/CallingConvLower.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineJumpTableInfo.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/SelectionDAGISel.h"
27 #include "llvm/CodeGen/ValueTypes.h"
28 #include "llvm/IR/CallingConv.h"
29 #include "llvm/IR/DerivedTypes.h"
30 #include "llvm/IR/Function.h"
31 #include "llvm/IR/GlobalAlias.h"
32 #include "llvm/IR/GlobalVariable.h"
33 #include "llvm/IR/InlineAsm.h"
34 #include "llvm/IR/Intrinsics.h"
35 #include "llvm/Support/CommandLine.h"
36 #include "llvm/Support/Debug.h"
37 #include "llvm/Support/ErrorHandling.h"
38 #include "llvm/Support/raw_ostream.h"
42 const unsigned Hexagon_MAX_RET_SIZE = 64;
45 EmitJumpTables("hexagon-emit-jump-tables", cl::init(true), cl::Hidden,
46 cl::desc("Control jump table emission on Hexagon target"));
48 int NumNamedVarArgParams = -1;
50 // Implement calling convention for Hexagon.
52 CC_Hexagon(unsigned ValNo, MVT ValVT,
53 MVT LocVT, CCValAssign::LocInfo LocInfo,
54 ISD::ArgFlagsTy ArgFlags, CCState &State);
57 CC_Hexagon32(unsigned ValNo, MVT ValVT,
58 MVT LocVT, CCValAssign::LocInfo LocInfo,
59 ISD::ArgFlagsTy ArgFlags, CCState &State);
62 CC_Hexagon64(unsigned ValNo, MVT ValVT,
63 MVT LocVT, CCValAssign::LocInfo LocInfo,
64 ISD::ArgFlagsTy ArgFlags, CCState &State);
67 RetCC_Hexagon(unsigned ValNo, MVT ValVT,
68 MVT LocVT, CCValAssign::LocInfo LocInfo,
69 ISD::ArgFlagsTy ArgFlags, CCState &State);
72 RetCC_Hexagon32(unsigned ValNo, MVT ValVT,
73 MVT LocVT, CCValAssign::LocInfo LocInfo,
74 ISD::ArgFlagsTy ArgFlags, CCState &State);
77 RetCC_Hexagon64(unsigned ValNo, MVT ValVT,
78 MVT LocVT, CCValAssign::LocInfo LocInfo,
79 ISD::ArgFlagsTy ArgFlags, CCState &State);
82 CC_Hexagon_VarArg (unsigned ValNo, MVT ValVT,
83 MVT LocVT, CCValAssign::LocInfo LocInfo,
84 ISD::ArgFlagsTy ArgFlags, CCState &State) {
86 // NumNamedVarArgParams can not be zero for a VarArg function.
87 assert ( (NumNamedVarArgParams > 0) &&
88 "NumNamedVarArgParams is not bigger than zero.");
90 if ( (int)ValNo < NumNamedVarArgParams ) {
91 // Deal with named arguments.
92 return CC_Hexagon(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State);
95 // Deal with un-named arguments.
97 if (ArgFlags.isByVal()) {
98 // If pass-by-value, the size allocated on stack is decided
99 // by ArgFlags.getByValSize(), not by the size of LocVT.
100 assert ((ArgFlags.getByValSize() > 8) &&
101 "ByValSize must be bigger than 8 bytes");
102 ofst = State.AllocateStack(ArgFlags.getByValSize(), 4);
103 State.addLoc(CCValAssign::getMem(ValNo, ValVT, ofst, LocVT, LocInfo));
106 if (LocVT == MVT::i1 || LocVT == MVT::i8 || LocVT == MVT::i16) {
109 if (ArgFlags.isSExt())
110 LocInfo = CCValAssign::SExt;
111 else if (ArgFlags.isZExt())
112 LocInfo = CCValAssign::ZExt;
114 LocInfo = CCValAssign::AExt;
116 if (LocVT == MVT::i32 || LocVT == MVT::f32) {
117 ofst = State.AllocateStack(4, 4);
118 State.addLoc(CCValAssign::getMem(ValNo, ValVT, ofst, LocVT, LocInfo));
121 if (LocVT == MVT::i64 || LocVT == MVT::f64) {
122 ofst = State.AllocateStack(8, 8);
123 State.addLoc(CCValAssign::getMem(ValNo, ValVT, ofst, LocVT, LocInfo));
131 CC_Hexagon (unsigned ValNo, MVT ValVT,
132 MVT LocVT, CCValAssign::LocInfo LocInfo,
133 ISD::ArgFlagsTy ArgFlags, CCState &State) {
135 if (ArgFlags.isByVal()) {
137 assert ((ArgFlags.getByValSize() > 8) &&
138 "ByValSize must be bigger than 8 bytes");
139 unsigned Offset = State.AllocateStack(ArgFlags.getByValSize(), 4);
140 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
144 if (LocVT == MVT::i1 || LocVT == MVT::i8 || LocVT == MVT::i16) {
147 if (ArgFlags.isSExt())
148 LocInfo = CCValAssign::SExt;
149 else if (ArgFlags.isZExt())
150 LocInfo = CCValAssign::ZExt;
152 LocInfo = CCValAssign::AExt;
155 if (LocVT == MVT::i32 || LocVT == MVT::f32) {
156 if (!CC_Hexagon32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
160 if (LocVT == MVT::i64 || LocVT == MVT::f64) {
161 if (!CC_Hexagon64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
165 return true; // CC didn't match.
169 static bool CC_Hexagon32(unsigned ValNo, MVT ValVT,
170 MVT LocVT, CCValAssign::LocInfo LocInfo,
171 ISD::ArgFlagsTy ArgFlags, CCState &State) {
173 static const uint16_t RegList[] = {
174 Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4,
177 if (unsigned Reg = State.AllocateReg(RegList, 6)) {
178 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
182 unsigned Offset = State.AllocateStack(4, 4);
183 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
187 static bool CC_Hexagon64(unsigned ValNo, MVT ValVT,
188 MVT LocVT, CCValAssign::LocInfo LocInfo,
189 ISD::ArgFlagsTy ArgFlags, CCState &State) {
191 if (unsigned Reg = State.AllocateReg(Hexagon::D0)) {
192 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
196 static const uint16_t RegList1[] = {
197 Hexagon::D1, Hexagon::D2
199 static const uint16_t RegList2[] = {
200 Hexagon::R1, Hexagon::R3
202 if (unsigned Reg = State.AllocateReg(RegList1, RegList2, 2)) {
203 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
207 unsigned Offset = State.AllocateStack(8, 8, Hexagon::D2);
208 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
212 static bool RetCC_Hexagon(unsigned ValNo, MVT ValVT,
213 MVT LocVT, CCValAssign::LocInfo LocInfo,
214 ISD::ArgFlagsTy ArgFlags, CCState &State) {
217 if (LocVT == MVT::i1 ||
222 if (ArgFlags.isSExt())
223 LocInfo = CCValAssign::SExt;
224 else if (ArgFlags.isZExt())
225 LocInfo = CCValAssign::ZExt;
227 LocInfo = CCValAssign::AExt;
230 if (LocVT == MVT::i32 || LocVT == MVT::f32) {
231 if (!RetCC_Hexagon32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
235 if (LocVT == MVT::i64 || LocVT == MVT::f64) {
236 if (!RetCC_Hexagon64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
240 return true; // CC didn't match.
243 static bool RetCC_Hexagon32(unsigned ValNo, MVT ValVT,
244 MVT LocVT, CCValAssign::LocInfo LocInfo,
245 ISD::ArgFlagsTy ArgFlags, CCState &State) {
247 if (LocVT == MVT::i32 || LocVT == MVT::f32) {
248 if (unsigned Reg = State.AllocateReg(Hexagon::R0)) {
249 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
254 unsigned Offset = State.AllocateStack(4, 4);
255 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
259 static bool RetCC_Hexagon64(unsigned ValNo, MVT ValVT,
260 MVT LocVT, CCValAssign::LocInfo LocInfo,
261 ISD::ArgFlagsTy ArgFlags, CCState &State) {
262 if (LocVT == MVT::i64 || LocVT == MVT::f64) {
263 if (unsigned Reg = State.AllocateReg(Hexagon::D0)) {
264 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
269 unsigned Offset = State.AllocateStack(8, 8);
270 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
275 HexagonTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG)
280 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
281 /// by "Src" to address "Dst" of size "Size". Alignment information is
282 /// specified by the specific parameter attribute. The copy will be passed as
283 /// a byval function parameter. Sometimes what we are copying is the end of a
284 /// larger object, the part that does not fit in registers.
286 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
287 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
290 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
291 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
292 /*isVolatile=*/false, /*AlwaysInline=*/false,
293 MachinePointerInfo(), MachinePointerInfo());
297 // LowerReturn - Lower ISD::RET. If a struct is larger than 8 bytes and is
298 // passed by value, the function prototype is modified to return void and
299 // the value is stored in memory pointed by a pointer passed by caller.
301 HexagonTargetLowering::LowerReturn(SDValue Chain,
302 CallingConv::ID CallConv, bool isVarArg,
303 const SmallVectorImpl<ISD::OutputArg> &Outs,
304 const SmallVectorImpl<SDValue> &OutVals,
305 DebugLoc dl, SelectionDAG &DAG) const {
307 // CCValAssign - represent the assignment of the return value to locations.
308 SmallVector<CCValAssign, 16> RVLocs;
310 // CCState - Info about the registers and stack slot.
311 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
312 getTargetMachine(), RVLocs, *DAG.getContext());
314 // Analyze return values of ISD::RET
315 CCInfo.AnalyzeReturn(Outs, RetCC_Hexagon);
318 SmallVector<SDValue, 4> RetOps(1, Chain);
320 // Copy the result values into the output registers.
321 for (unsigned i = 0; i != RVLocs.size(); ++i) {
322 CCValAssign &VA = RVLocs[i];
324 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag);
326 // Guarantee that all emitted copies are stuck together with flags.
327 Flag = Chain.getValue(1);
328 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
331 RetOps[0] = Chain; // Update chain.
333 // Add the flag if we have it.
335 RetOps.push_back(Flag);
337 return DAG.getNode(HexagonISD::RET_FLAG, dl, MVT::Other,
338 &RetOps[0], RetOps.size());
344 /// LowerCallResult - Lower the result values of an ISD::CALL into the
345 /// appropriate copies out of appropriate physical registers. This assumes that
346 /// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
347 /// being lowered. Returns a SDNode with the same number of values as the
350 HexagonTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
351 CallingConv::ID CallConv, bool isVarArg,
353 SmallVectorImpl<ISD::InputArg> &Ins,
354 DebugLoc dl, SelectionDAG &DAG,
355 SmallVectorImpl<SDValue> &InVals,
356 const SmallVectorImpl<SDValue> &OutVals,
357 SDValue Callee) const {
359 // Assign locations to each value returned by this call.
360 SmallVector<CCValAssign, 16> RVLocs;
362 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
363 getTargetMachine(), RVLocs, *DAG.getContext());
365 CCInfo.AnalyzeCallResult(Ins, RetCC_Hexagon);
367 // Copy all of the result registers out of their specified physreg.
368 for (unsigned i = 0; i != RVLocs.size(); ++i) {
369 Chain = DAG.getCopyFromReg(Chain, dl,
370 RVLocs[i].getLocReg(),
371 RVLocs[i].getValVT(), InFlag).getValue(1);
372 InFlag = Chain.getValue(2);
373 InVals.push_back(Chain.getValue(0));
379 /// LowerCall - Functions arguments are copied from virtual regs to
380 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
382 HexagonTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
383 SmallVectorImpl<SDValue> &InVals) const {
384 SelectionDAG &DAG = CLI.DAG;
385 DebugLoc &dl = CLI.DL;
386 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;
387 SmallVector<SDValue, 32> &OutVals = CLI.OutVals;
388 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins;
389 SDValue Chain = CLI.Chain;
390 SDValue Callee = CLI.Callee;
391 bool &isTailCall = CLI.IsTailCall;
392 CallingConv::ID CallConv = CLI.CallConv;
393 bool isVarArg = CLI.IsVarArg;
395 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
397 // Analyze operands of the call, assigning locations to each operand.
398 SmallVector<CCValAssign, 16> ArgLocs;
399 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
400 getTargetMachine(), ArgLocs, *DAG.getContext());
402 // Check for varargs.
403 NumNamedVarArgParams = -1;
404 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Callee))
406 const Function* CalleeFn = NULL;
407 Callee = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, MVT::i32);
408 if ((CalleeFn = dyn_cast<Function>(GA->getGlobal())))
410 // If a function has zero args and is a vararg function, that's
411 // disallowed so it must be an undeclared function. Do not assume
412 // varargs if the callee is undefined.
413 if (CalleeFn->isVarArg() &&
414 CalleeFn->getFunctionType()->getNumParams() != 0) {
415 NumNamedVarArgParams = CalleeFn->getFunctionType()->getNumParams();
420 if (NumNamedVarArgParams > 0)
421 CCInfo.AnalyzeCallOperands(Outs, CC_Hexagon_VarArg);
423 CCInfo.AnalyzeCallOperands(Outs, CC_Hexagon);
427 bool StructAttrFlag =
428 DAG.getMachineFunction().getFunction()->hasStructRetAttr();
429 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
430 isVarArg, IsStructRet,
432 Outs, OutVals, Ins, DAG);
433 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i){
434 CCValAssign &VA = ArgLocs[i];
441 DEBUG(dbgs () << "Eligible for Tail Call\n");
444 "Argument must be passed on stack. Not eligible for Tail Call\n");
447 // Get a count of how many bytes are to be pushed on the stack.
448 unsigned NumBytes = CCInfo.getNextStackOffset();
449 SmallVector<std::pair<unsigned, SDValue>, 16> RegsToPass;
450 SmallVector<SDValue, 8> MemOpChains;
453 DAG.getCopyFromReg(Chain, dl, TM.getRegisterInfo()->getStackRegister(),
456 // Walk the register/memloc assignments, inserting copies/loads.
457 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
458 CCValAssign &VA = ArgLocs[i];
459 SDValue Arg = OutVals[i];
460 ISD::ArgFlagsTy Flags = Outs[i].Flags;
462 // Promote the value if needed.
463 switch (VA.getLocInfo()) {
465 // Loc info must be one of Full, SExt, ZExt, or AExt.
466 llvm_unreachable("Unknown loc info!");
467 case CCValAssign::Full:
469 case CCValAssign::SExt:
470 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
472 case CCValAssign::ZExt:
473 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
475 case CCValAssign::AExt:
476 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
481 unsigned LocMemOffset = VA.getLocMemOffset();
482 SDValue PtrOff = DAG.getConstant(LocMemOffset, StackPtr.getValueType());
483 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
485 if (Flags.isByVal()) {
486 // The argument is a struct passed by value. According to LLVM, "Arg"
488 MemOpChains.push_back(CreateCopyOfByValArgument(Arg, PtrOff, Chain,
491 // The argument is not passed by value. "Arg" is a buildin type. It is
493 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
494 MachinePointerInfo(),false, false,
500 // Arguments that can be passed on register must be kept at RegsToPass
503 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
507 // Transform all store nodes into one single node because all store
508 // nodes are independent of each other.
509 if (!MemOpChains.empty()) {
510 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &MemOpChains[0],
515 Chain = DAG.getCALLSEQ_START(Chain, DAG.getConstant(NumBytes,
516 getPointerTy(), true));
518 // Build a sequence of copy-to-reg nodes chained together with token
519 // chain and flag operands which copy the outgoing args into registers.
520 // The InFlag in necessary since all emitted instructions must be
524 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
525 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
526 RegsToPass[i].second, InFlag);
527 InFlag = Chain.getValue(1);
531 // For tail calls lower the arguments to the 'real' stack slot.
533 // Force all the incoming stack arguments to be loaded from the stack
534 // before any new outgoing arguments are stored to the stack, because the
535 // outgoing stack slots may alias the incoming argument stack slots, and
536 // the alias isn't otherwise explicit. This is slightly more conservative
537 // than necessary, because it means that each store effectively depends
538 // on every argument instead of just those arguments it would clobber.
540 // Do not flag preceding copytoreg stuff together with the following stuff.
542 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
543 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
544 RegsToPass[i].second, InFlag);
545 InFlag = Chain.getValue(1);
550 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
551 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
552 // node so that legalize doesn't hack it.
553 if (flag_aligned_memcpy) {
554 const char *MemcpyName =
555 "__hexagon_memcpy_likely_aligned_min32bytes_mult8bytes";
557 DAG.getTargetExternalSymbol(MemcpyName, getPointerTy());
558 flag_aligned_memcpy = false;
559 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
560 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, getPointerTy());
561 } else if (ExternalSymbolSDNode *S =
562 dyn_cast<ExternalSymbolSDNode>(Callee)) {
563 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
566 // Returns a chain & a flag for retval copy to use.
567 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
568 SmallVector<SDValue, 8> Ops;
569 Ops.push_back(Chain);
570 Ops.push_back(Callee);
572 // Add argument registers to the end of the list so that they are
573 // known live into the call.
574 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
575 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
576 RegsToPass[i].second.getValueType()));
579 if (InFlag.getNode()) {
580 Ops.push_back(InFlag);
584 return DAG.getNode(HexagonISD::TC_RETURN, dl, NodeTys, &Ops[0], Ops.size());
586 Chain = DAG.getNode(HexagonISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
587 InFlag = Chain.getValue(1);
589 // Create the CALLSEQ_END node.
590 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
591 DAG.getIntPtrConstant(0, true), InFlag);
592 InFlag = Chain.getValue(1);
594 // Handle result values, copying them out of physregs into vregs that we
596 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl, DAG,
597 InVals, OutVals, Callee);
600 static bool getIndexedAddressParts(SDNode *Ptr, EVT VT,
601 bool isSEXTLoad, SDValue &Base,
602 SDValue &Offset, bool &isInc,
604 if (Ptr->getOpcode() != ISD::ADD)
607 if (VT == MVT::i64 || VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) {
608 isInc = (Ptr->getOpcode() == ISD::ADD);
609 Base = Ptr->getOperand(0);
610 Offset = Ptr->getOperand(1);
611 // Ensure that Offset is a constant.
612 return (isa<ConstantSDNode>(Offset));
618 // TODO: Put this function along with the other isS* functions in
619 // HexagonISelDAGToDAG.cpp into a common file. Or better still, use the
620 // functions defined in HexagonOperands.td.
621 static bool Is_PostInc_S4_Offset(SDNode * S, int ShiftAmount) {
622 ConstantSDNode *N = cast<ConstantSDNode>(S);
624 // immS4 predicate - True if the immediate fits in a 4-bit sign extended.
626 int64_t v = (int64_t)N->getSExtValue();
628 if (ShiftAmount > 0) {
630 v = v >> ShiftAmount;
632 return (v <= 7) && (v >= -8) && (m == 0);
635 /// getPostIndexedAddressParts - returns true by value, base pointer and
636 /// offset pointer and addressing mode by reference if this node can be
637 /// combined with a load / store to form a post-indexed load / store.
638 bool HexagonTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
641 ISD::MemIndexedMode &AM,
642 SelectionDAG &DAG) const
646 bool isSEXTLoad = false;
648 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
649 VT = LD->getMemoryVT();
650 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
651 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
652 VT = ST->getMemoryVT();
653 if (ST->getValue().getValueType() == MVT::i64 && ST->isTruncatingStore()) {
661 bool isLegal = getIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
663 // ShiftAmount = number of left-shifted bits in the Hexagon instruction.
664 int ShiftAmount = VT.getSizeInBits() / 16;
665 if (isLegal && Is_PostInc_S4_Offset(Offset.getNode(), ShiftAmount)) {
666 AM = isInc ? ISD::POST_INC : ISD::POST_DEC;
673 SDValue HexagonTargetLowering::LowerINLINEASM(SDValue Op,
674 SelectionDAG &DAG) const {
675 SDNode *Node = Op.getNode();
676 MachineFunction &MF = DAG.getMachineFunction();
677 HexagonMachineFunctionInfo *FuncInfo =
678 MF.getInfo<HexagonMachineFunctionInfo>();
679 switch (Node->getOpcode()) {
680 case ISD::INLINEASM: {
681 unsigned NumOps = Node->getNumOperands();
682 if (Node->getOperand(NumOps-1).getValueType() == MVT::Glue)
683 --NumOps; // Ignore the flag operand.
685 for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
686 if (FuncInfo->hasClobberLR())
689 cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue();
690 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
691 ++i; // Skip the ID value.
693 switch (InlineAsm::getKind(Flags)) {
694 default: llvm_unreachable("Bad flags!");
695 case InlineAsm::Kind_RegDef:
696 case InlineAsm::Kind_RegUse:
697 case InlineAsm::Kind_Imm:
698 case InlineAsm::Kind_Clobber:
699 case InlineAsm::Kind_Mem: {
700 for (; NumVals; --NumVals, ++i) {}
703 case InlineAsm::Kind_RegDefEarlyClobber: {
704 for (; NumVals; --NumVals, ++i) {
706 cast<RegisterSDNode>(Node->getOperand(i))->getReg();
709 if (Reg == TM.getRegisterInfo()->getRARegister()) {
710 FuncInfo->setHasClobberLR(true);
725 // Taken from the XCore backend.
727 SDValue HexagonTargetLowering::
728 LowerBR_JT(SDValue Op, SelectionDAG &DAG) const
730 SDValue Chain = Op.getOperand(0);
731 SDValue Table = Op.getOperand(1);
732 SDValue Index = Op.getOperand(2);
733 DebugLoc dl = Op.getDebugLoc();
734 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
735 unsigned JTI = JT->getIndex();
736 MachineFunction &MF = DAG.getMachineFunction();
737 const MachineJumpTableInfo *MJTI = MF.getJumpTableInfo();
738 SDValue TargetJT = DAG.getTargetJumpTable(JT->getIndex(), MVT::i32);
740 // Mark all jump table targets as address taken.
741 const std::vector<MachineJumpTableEntry> &JTE = MJTI->getJumpTables();
742 const std::vector<MachineBasicBlock*> &JTBBs = JTE[JTI].MBBs;
743 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
744 MachineBasicBlock *MBB = JTBBs[i];
745 MBB->setHasAddressTaken();
746 // This line is needed to set the hasAddressTaken flag on the BasicBlock
748 BlockAddress::get(const_cast<BasicBlock *>(MBB->getBasicBlock()));
751 SDValue JumpTableBase = DAG.getNode(HexagonISD::WrapperJT, dl,
752 getPointerTy(), TargetJT);
753 SDValue ShiftIndex = DAG.getNode(ISD::SHL, dl, MVT::i32, Index,
754 DAG.getConstant(2, MVT::i32));
755 SDValue JTAddress = DAG.getNode(ISD::ADD, dl, MVT::i32, JumpTableBase,
757 SDValue LoadTarget = DAG.getLoad(MVT::i32, dl, Chain, JTAddress,
758 MachinePointerInfo(), false, false, false,
760 return DAG.getNode(HexagonISD::BR_JT, dl, MVT::Other, Chain, LoadTarget);
765 HexagonTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
766 SelectionDAG &DAG) const {
767 SDValue Chain = Op.getOperand(0);
768 SDValue Size = Op.getOperand(1);
769 DebugLoc dl = Op.getDebugLoc();
771 unsigned SPReg = getStackPointerRegisterToSaveRestore();
773 // Get a reference to the stack pointer.
774 SDValue StackPointer = DAG.getCopyFromReg(Chain, dl, SPReg, MVT::i32);
776 // Subtract the dynamic size from the actual stack size to
777 // obtain the new stack size.
778 SDValue Sub = DAG.getNode(ISD::SUB, dl, MVT::i32, StackPointer, Size);
781 // For Hexagon, the outgoing memory arguments area should be on top of the
782 // alloca area on the stack i.e., the outgoing memory arguments should be
783 // at a lower address than the alloca area. Move the alloca area down the
784 // stack by adding back the space reserved for outgoing arguments to SP
787 // We do not know what the size of the outgoing args is at this point.
788 // So, we add a pseudo instruction ADJDYNALLOC that will adjust the
789 // stack pointer. We patch this instruction with the correct, known
790 // offset in emitPrologue().
792 // Use a placeholder immediate (zero) for now. This will be patched up
793 // by emitPrologue().
794 SDValue ArgAdjust = DAG.getNode(HexagonISD::ADJDYNALLOC, dl,
797 DAG.getConstant(0, MVT::i32));
799 // The Sub result contains the new stack start address, so it
800 // must be placed in the stack pointer register.
801 SDValue CopyChain = DAG.getCopyToReg(Chain, dl,
802 TM.getRegisterInfo()->getStackRegister(),
805 SDValue Ops[2] = { ArgAdjust, CopyChain };
806 return DAG.getMergeValues(Ops, 2, dl);
810 HexagonTargetLowering::LowerFormalArguments(SDValue Chain,
811 CallingConv::ID CallConv,
814 SmallVectorImpl<ISD::InputArg> &Ins,
815 DebugLoc dl, SelectionDAG &DAG,
816 SmallVectorImpl<SDValue> &InVals)
819 MachineFunction &MF = DAG.getMachineFunction();
820 MachineFrameInfo *MFI = MF.getFrameInfo();
821 MachineRegisterInfo &RegInfo = MF.getRegInfo();
822 HexagonMachineFunctionInfo *FuncInfo =
823 MF.getInfo<HexagonMachineFunctionInfo>();
826 // Assign locations to all of the incoming arguments.
827 SmallVector<CCValAssign, 16> ArgLocs;
828 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
829 getTargetMachine(), ArgLocs, *DAG.getContext());
831 CCInfo.AnalyzeFormalArguments(Ins, CC_Hexagon);
833 // For LLVM, in the case when returning a struct by value (>8byte),
834 // the first argument is a pointer that points to the location on caller's
835 // stack where the return value will be stored. For Hexagon, the location on
836 // caller's stack is passed only when the struct size is smaller than (and
837 // equal to) 8 bytes. If not, no address will be passed into callee and
838 // callee return the result direclty through R0/R1.
840 SmallVector<SDValue, 4> MemOps;
842 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
843 CCValAssign &VA = ArgLocs[i];
844 ISD::ArgFlagsTy Flags = Ins[i].Flags;
846 unsigned StackLocation;
849 if ( (VA.isRegLoc() && !Flags.isByVal())
850 || (VA.isRegLoc() && Flags.isByVal() && Flags.getByValSize() > 8)) {
851 // Arguments passed in registers
852 // 1. int, long long, ptr args that get allocated in register.
853 // 2. Large struct that gets an register to put its address in.
854 EVT RegVT = VA.getLocVT();
855 if (RegVT == MVT::i8 || RegVT == MVT::i16 ||
856 RegVT == MVT::i32 || RegVT == MVT::f32) {
858 RegInfo.createVirtualRegister(&Hexagon::IntRegsRegClass);
859 RegInfo.addLiveIn(VA.getLocReg(), VReg);
860 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
861 } else if (RegVT == MVT::i64) {
863 RegInfo.createVirtualRegister(&Hexagon::DoubleRegsRegClass);
864 RegInfo.addLiveIn(VA.getLocReg(), VReg);
865 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
869 } else if (VA.isRegLoc() && Flags.isByVal() && Flags.getByValSize() <= 8) {
870 assert (0 && "ByValSize must be bigger than 8 bytes");
873 assert(VA.isMemLoc());
875 if (Flags.isByVal()) {
876 // If it's a byval parameter, then we need to compute the
877 // "real" size, not the size of the pointer.
878 ObjSize = Flags.getByValSize();
880 ObjSize = VA.getLocVT().getStoreSizeInBits() >> 3;
883 StackLocation = HEXAGON_LRFP_SIZE + VA.getLocMemOffset();
884 // Create the frame index object for this incoming parameter...
885 FI = MFI->CreateFixedObject(ObjSize, StackLocation, true);
887 // Create the SelectionDAG nodes cordl, responding to a load
888 // from this parameter.
889 SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
891 if (Flags.isByVal()) {
892 // If it's a pass-by-value aggregate, then do not dereference the stack
893 // location. Instead, we should generate a reference to the stack
895 InVals.push_back(FIN);
897 InVals.push_back(DAG.getLoad(VA.getLocVT(), dl, Chain, FIN,
898 MachinePointerInfo(), false, false,
905 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &MemOps[0],
909 // This will point to the next argument passed via stack.
910 int FrameIndex = MFI->CreateFixedObject(Hexagon_PointerSize,
912 CCInfo.getNextStackOffset(),
914 FuncInfo->setVarArgsFrameIndex(FrameIndex);
921 HexagonTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
922 // VASTART stores the address of the VarArgsFrameIndex slot into the
923 // memory location argument.
924 MachineFunction &MF = DAG.getMachineFunction();
925 HexagonMachineFunctionInfo *QFI = MF.getInfo<HexagonMachineFunctionInfo>();
926 SDValue Addr = DAG.getFrameIndex(QFI->getVarArgsFrameIndex(), MVT::i32);
927 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
928 return DAG.getStore(Op.getOperand(0), Op.getDebugLoc(), Addr,
929 Op.getOperand(1), MachinePointerInfo(SV), false,
934 HexagonTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
935 SDValue LHS = Op.getOperand(0);
936 SDValue RHS = Op.getOperand(1);
937 SDValue CC = Op.getOperand(4);
938 SDValue TrueVal = Op.getOperand(2);
939 SDValue FalseVal = Op.getOperand(3);
940 DebugLoc dl = Op.getDebugLoc();
941 SDNode* OpNode = Op.getNode();
942 EVT SVT = OpNode->getValueType(0);
944 SDValue Cond = DAG.getNode(ISD::SETCC, dl, MVT::i1, LHS, RHS, CC);
945 return DAG.getNode(ISD::SELECT, dl, SVT, Cond, TrueVal, FalseVal);
949 HexagonTargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
950 EVT ValTy = Op.getValueType();
951 DebugLoc dl = Op.getDebugLoc();
952 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
954 if (CP->isMachineConstantPoolEntry())
955 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), ValTy,
958 Res = DAG.getTargetConstantPool(CP->getConstVal(), ValTy,
960 return DAG.getNode(HexagonISD::CONST32, dl, ValTy, Res);
964 HexagonTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const {
965 const TargetRegisterInfo *TRI = TM.getRegisterInfo();
966 MachineFunction &MF = DAG.getMachineFunction();
967 MachineFrameInfo *MFI = MF.getFrameInfo();
968 MFI->setReturnAddressIsTaken(true);
970 EVT VT = Op.getValueType();
971 DebugLoc dl = Op.getDebugLoc();
972 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
974 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
975 SDValue Offset = DAG.getConstant(4, MVT::i32);
976 return DAG.getLoad(VT, dl, DAG.getEntryNode(),
977 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
978 MachinePointerInfo(), false, false, false, 0);
981 // Return LR, which contains the return address. Mark it an implicit live-in.
982 unsigned Reg = MF.addLiveIn(TRI->getRARegister(), getRegClassFor(MVT::i32));
983 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
987 HexagonTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
988 const HexagonRegisterInfo *TRI = TM.getRegisterInfo();
989 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
990 MFI->setFrameAddressIsTaken(true);
992 EVT VT = Op.getValueType();
993 DebugLoc dl = Op.getDebugLoc();
994 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
995 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
996 TRI->getFrameRegister(), VT);
998 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
999 MachinePointerInfo(),
1000 false, false, false, 0);
1004 SDValue HexagonTargetLowering::LowerATOMIC_FENCE(SDValue Op,
1005 SelectionDAG& DAG) const {
1006 DebugLoc dl = Op.getDebugLoc();
1007 return DAG.getNode(HexagonISD::BARRIER, dl, MVT::Other, Op.getOperand(0));
1011 SDValue HexagonTargetLowering::LowerGLOBALADDRESS(SDValue Op,
1012 SelectionDAG &DAG) const {
1014 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1015 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
1016 DebugLoc dl = Op.getDebugLoc();
1017 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
1019 const HexagonTargetObjectFile &TLOF =
1020 static_cast<const HexagonTargetObjectFile &>(getObjFileLowering());
1021 if (TLOF.IsGlobalInSmallSection(GV, getTargetMachine())) {
1022 return DAG.getNode(HexagonISD::CONST32_GP, dl, getPointerTy(), Result);
1025 return DAG.getNode(HexagonISD::CONST32, dl, getPointerTy(), Result);
1029 HexagonTargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
1030 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1031 SDValue BA_SD = DAG.getTargetBlockAddress(BA, MVT::i32);
1032 DebugLoc dl = Op.getDebugLoc();
1033 return DAG.getNode(HexagonISD::CONST32_GP, dl, getPointerTy(), BA_SD);
1036 //===----------------------------------------------------------------------===//
1037 // TargetLowering Implementation
1038 //===----------------------------------------------------------------------===//
1040 HexagonTargetLowering::HexagonTargetLowering(HexagonTargetMachine
1042 : TargetLowering(targetmachine, new HexagonTargetObjectFile()),
1045 const HexagonRegisterInfo* QRI = TM.getRegisterInfo();
1047 // Set up the register classes.
1048 addRegisterClass(MVT::i32, &Hexagon::IntRegsRegClass);
1049 addRegisterClass(MVT::i64, &Hexagon::DoubleRegsRegClass);
1051 if (QRI->Subtarget.hasV5TOps()) {
1052 addRegisterClass(MVT::f32, &Hexagon::IntRegsRegClass);
1053 addRegisterClass(MVT::f64, &Hexagon::DoubleRegsRegClass);
1056 addRegisterClass(MVT::i1, &Hexagon::PredRegsRegClass);
1058 computeRegisterProperties();
1061 setPrefLoopAlignment(4);
1063 // Limits for inline expansion of memcpy/memmove
1064 MaxStoresPerMemcpy = 6;
1065 MaxStoresPerMemmove = 6;
1068 // Library calls for unsupported operations
1071 setLibcallName(RTLIB::SINTTOFP_I128_F64, "__hexagon_floattidf");
1072 setLibcallName(RTLIB::SINTTOFP_I128_F32, "__hexagon_floattisf");
1074 setLibcallName(RTLIB::FPTOUINT_F32_I128, "__hexagon_fixunssfti");
1075 setLibcallName(RTLIB::FPTOUINT_F64_I128, "__hexagon_fixunsdfti");
1077 setLibcallName(RTLIB::FPTOSINT_F32_I128, "__hexagon_fixsfti");
1078 setLibcallName(RTLIB::FPTOSINT_F64_I128, "__hexagon_fixdfti");
1080 setLibcallName(RTLIB::SDIV_I32, "__hexagon_divsi3");
1081 setOperationAction(ISD::SDIV, MVT::i32, Expand);
1082 setLibcallName(RTLIB::SREM_I32, "__hexagon_umodsi3");
1083 setOperationAction(ISD::SREM, MVT::i32, Expand);
1085 setLibcallName(RTLIB::SDIV_I64, "__hexagon_divdi3");
1086 setOperationAction(ISD::SDIV, MVT::i64, Expand);
1087 setLibcallName(RTLIB::SREM_I64, "__hexagon_moddi3");
1088 setOperationAction(ISD::SREM, MVT::i64, Expand);
1090 setLibcallName(RTLIB::UDIV_I32, "__hexagon_udivsi3");
1091 setOperationAction(ISD::UDIV, MVT::i32, Expand);
1093 setLibcallName(RTLIB::UDIV_I64, "__hexagon_udivdi3");
1094 setOperationAction(ISD::UDIV, MVT::i64, Expand);
1096 setLibcallName(RTLIB::UREM_I32, "__hexagon_umodsi3");
1097 setOperationAction(ISD::UREM, MVT::i32, Expand);
1099 setLibcallName(RTLIB::UREM_I64, "__hexagon_umoddi3");
1100 setOperationAction(ISD::UREM, MVT::i64, Expand);
1102 setLibcallName(RTLIB::DIV_F32, "__hexagon_divsf3");
1103 setOperationAction(ISD::FDIV, MVT::f32, Expand);
1105 setLibcallName(RTLIB::DIV_F64, "__hexagon_divdf3");
1106 setOperationAction(ISD::FDIV, MVT::f64, Expand);
1108 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
1109 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
1110 setOperationAction(ISD::FSIN, MVT::f32, Expand);
1111 setOperationAction(ISD::FSIN, MVT::f64, Expand);
1113 if (QRI->Subtarget.hasV5TOps()) {
1114 // Hexagon V5 Support.
1115 setOperationAction(ISD::FADD, MVT::f32, Legal);
1116 setOperationAction(ISD::FADD, MVT::f64, Legal);
1117 setOperationAction(ISD::FP_EXTEND, MVT::f32, Legal);
1118 setCondCodeAction(ISD::SETOEQ, MVT::f32, Legal);
1119 setCondCodeAction(ISD::SETOEQ, MVT::f64, Legal);
1120 setCondCodeAction(ISD::SETUEQ, MVT::f32, Legal);
1121 setCondCodeAction(ISD::SETUEQ, MVT::f64, Legal);
1123 setCondCodeAction(ISD::SETOGE, MVT::f32, Legal);
1124 setCondCodeAction(ISD::SETOGE, MVT::f64, Legal);
1125 setCondCodeAction(ISD::SETUGE, MVT::f32, Legal);
1126 setCondCodeAction(ISD::SETUGE, MVT::f64, Legal);
1128 setCondCodeAction(ISD::SETOGT, MVT::f32, Legal);
1129 setCondCodeAction(ISD::SETOGT, MVT::f64, Legal);
1130 setCondCodeAction(ISD::SETUGT, MVT::f32, Legal);
1131 setCondCodeAction(ISD::SETUGT, MVT::f64, Legal);
1133 setCondCodeAction(ISD::SETOLE, MVT::f32, Legal);
1134 setCondCodeAction(ISD::SETOLE, MVT::f64, Legal);
1135 setCondCodeAction(ISD::SETOLT, MVT::f32, Legal);
1136 setCondCodeAction(ISD::SETOLT, MVT::f64, Legal);
1138 setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
1139 setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
1141 setOperationAction(ISD::FP_TO_UINT, MVT::i1, Promote);
1142 setOperationAction(ISD::FP_TO_SINT, MVT::i1, Promote);
1143 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Promote);
1144 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote);
1146 setOperationAction(ISD::FP_TO_UINT, MVT::i8, Promote);
1147 setOperationAction(ISD::FP_TO_SINT, MVT::i8, Promote);
1148 setOperationAction(ISD::UINT_TO_FP, MVT::i8, Promote);
1149 setOperationAction(ISD::SINT_TO_FP, MVT::i8, Promote);
1151 setOperationAction(ISD::FP_TO_UINT, MVT::i16, Promote);
1152 setOperationAction(ISD::FP_TO_SINT, MVT::i16, Promote);
1153 setOperationAction(ISD::UINT_TO_FP, MVT::i16, Promote);
1154 setOperationAction(ISD::SINT_TO_FP, MVT::i16, Promote);
1156 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1157 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1158 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1159 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1161 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1162 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1163 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1164 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1166 setOperationAction(ISD::FABS, MVT::f32, Legal);
1167 setOperationAction(ISD::FABS, MVT::f64, Expand);
1169 setOperationAction(ISD::FNEG, MVT::f32, Legal);
1170 setOperationAction(ISD::FNEG, MVT::f64, Expand);
1173 // Expand fp<->uint.
1174 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Expand);
1175 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
1177 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
1178 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
1180 setLibcallName(RTLIB::SINTTOFP_I64_F32, "__hexagon_floatdisf");
1181 setLibcallName(RTLIB::UINTTOFP_I64_F32, "__hexagon_floatundisf");
1183 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__hexagon_floatunsisf");
1184 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__hexagon_floatsisf");
1186 setLibcallName(RTLIB::SINTTOFP_I64_F64, "__hexagon_floatdidf");
1187 setLibcallName(RTLIB::UINTTOFP_I64_F64, "__hexagon_floatundidf");
1189 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__hexagon_floatunsidf");
1190 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__hexagon_floatsidf");
1192 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__hexagon_fixunssfsi");
1193 setLibcallName(RTLIB::FPTOUINT_F32_I64, "__hexagon_fixunssfdi");
1195 setLibcallName(RTLIB::FPTOSINT_F64_I64, "__hexagon_fixdfdi");
1196 setLibcallName(RTLIB::FPTOSINT_F32_I64, "__hexagon_fixsfdi");
1198 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__hexagon_fixunsdfsi");
1199 setLibcallName(RTLIB::FPTOUINT_F64_I64, "__hexagon_fixunsdfdi");
1201 setLibcallName(RTLIB::ADD_F64, "__hexagon_adddf3");
1202 setOperationAction(ISD::FADD, MVT::f64, Expand);
1204 setLibcallName(RTLIB::ADD_F32, "__hexagon_addsf3");
1205 setOperationAction(ISD::FADD, MVT::f32, Expand);
1207 setLibcallName(RTLIB::FPEXT_F32_F64, "__hexagon_extendsfdf2");
1208 setOperationAction(ISD::FP_EXTEND, MVT::f32, Expand);
1210 setLibcallName(RTLIB::OEQ_F32, "__hexagon_eqsf2");
1211 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
1213 setLibcallName(RTLIB::OEQ_F64, "__hexagon_eqdf2");
1214 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
1216 setLibcallName(RTLIB::OGE_F32, "__hexagon_gesf2");
1217 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
1219 setLibcallName(RTLIB::OGE_F64, "__hexagon_gedf2");
1220 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
1222 setLibcallName(RTLIB::OGT_F32, "__hexagon_gtsf2");
1223 setCondCodeAction(ISD::SETOGT, MVT::f32, Expand);
1225 setLibcallName(RTLIB::OGT_F64, "__hexagon_gtdf2");
1226 setCondCodeAction(ISD::SETOGT, MVT::f64, Expand);
1228 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__hexagon_fixdfsi");
1229 setOperationAction(ISD::FP_TO_SINT, MVT::f64, Expand);
1231 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__hexagon_fixsfsi");
1232 setOperationAction(ISD::FP_TO_SINT, MVT::f32, Expand);
1234 setLibcallName(RTLIB::OLE_F64, "__hexagon_ledf2");
1235 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
1237 setLibcallName(RTLIB::OLE_F32, "__hexagon_lesf2");
1238 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
1240 setLibcallName(RTLIB::OLT_F64, "__hexagon_ltdf2");
1241 setCondCodeAction(ISD::SETOLT, MVT::f64, Expand);
1243 setLibcallName(RTLIB::OLT_F32, "__hexagon_ltsf2");
1244 setCondCodeAction(ISD::SETOLT, MVT::f32, Expand);
1246 setLibcallName(RTLIB::MUL_F64, "__hexagon_muldf3");
1247 setOperationAction(ISD::FMUL, MVT::f64, Expand);
1249 setLibcallName(RTLIB::MUL_F32, "__hexagon_mulsf3");
1250 setOperationAction(ISD::MUL, MVT::f32, Expand);
1252 setLibcallName(RTLIB::UNE_F64, "__hexagon_nedf2");
1253 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
1255 setLibcallName(RTLIB::UNE_F32, "__hexagon_nesf2");
1257 setLibcallName(RTLIB::SUB_F64, "__hexagon_subdf3");
1258 setOperationAction(ISD::SUB, MVT::f64, Expand);
1260 setLibcallName(RTLIB::SUB_F32, "__hexagon_subsf3");
1261 setOperationAction(ISD::SUB, MVT::f32, Expand);
1263 setLibcallName(RTLIB::FPROUND_F64_F32, "__hexagon_truncdfsf2");
1264 setOperationAction(ISD::FP_ROUND, MVT::f64, Expand);
1266 setLibcallName(RTLIB::UO_F64, "__hexagon_unorddf2");
1267 setCondCodeAction(ISD::SETUO, MVT::f64, Expand);
1269 setLibcallName(RTLIB::O_F64, "__hexagon_unorddf2");
1270 setCondCodeAction(ISD::SETO, MVT::f64, Expand);
1272 setLibcallName(RTLIB::O_F32, "__hexagon_unordsf2");
1273 setCondCodeAction(ISD::SETO, MVT::f32, Expand);
1275 setLibcallName(RTLIB::UO_F32, "__hexagon_unordsf2");
1276 setCondCodeAction(ISD::SETUO, MVT::f32, Expand);
1278 setOperationAction(ISD::FABS, MVT::f32, Expand);
1279 setOperationAction(ISD::FABS, MVT::f64, Expand);
1280 setOperationAction(ISD::FNEG, MVT::f32, Expand);
1281 setOperationAction(ISD::FNEG, MVT::f64, Expand);
1284 setLibcallName(RTLIB::SREM_I32, "__hexagon_modsi3");
1285 setOperationAction(ISD::SREM, MVT::i32, Expand);
1287 setIndexedLoadAction(ISD::POST_INC, MVT::i8, Legal);
1288 setIndexedLoadAction(ISD::POST_INC, MVT::i16, Legal);
1289 setIndexedLoadAction(ISD::POST_INC, MVT::i32, Legal);
1290 setIndexedLoadAction(ISD::POST_INC, MVT::i64, Legal);
1292 setIndexedStoreAction(ISD::POST_INC, MVT::i8, Legal);
1293 setIndexedStoreAction(ISD::POST_INC, MVT::i16, Legal);
1294 setIndexedStoreAction(ISD::POST_INC, MVT::i32, Legal);
1295 setIndexedStoreAction(ISD::POST_INC, MVT::i64, Legal);
1297 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
1299 // Turn FP extload into load/fextend.
1300 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
1301 // Hexagon has a i1 sign extending load.
1302 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Expand);
1303 // Turn FP truncstore into trunc + store.
1304 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
1306 // Custom legalize GlobalAddress nodes into CONST32.
1307 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
1308 setOperationAction(ISD::GlobalAddress, MVT::i8, Custom);
1309 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
1311 setOperationAction(ISD::TRUNCATE, MVT::i64, Expand);
1313 // Hexagon doesn't have sext_inreg, replace them with shl/sra.
1314 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
1316 // Hexagon has no REM or DIVREM operations.
1317 setOperationAction(ISD::UREM, MVT::i32, Expand);
1318 setOperationAction(ISD::SREM, MVT::i32, Expand);
1319 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
1320 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
1321 setOperationAction(ISD::SREM, MVT::i64, Expand);
1322 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
1323 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
1325 setOperationAction(ISD::BSWAP, MVT::i64, Expand);
1327 // Lower SELECT_CC to SETCC and SELECT.
1328 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
1329 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom);
1331 if (QRI->Subtarget.hasV5TOps()) {
1333 // We need to make the operation type of SELECT node to be Custom,
1334 // such that we don't go into the infinite loop of
1335 // select -> setcc -> select_cc -> select loop.
1336 setOperationAction(ISD::SELECT, MVT::f32, Custom);
1337 setOperationAction(ISD::SELECT, MVT::f64, Custom);
1339 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
1340 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
1341 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
1345 // Hexagon has no select or setcc: expand to SELECT_CC.
1346 setOperationAction(ISD::SELECT, MVT::f32, Expand);
1347 setOperationAction(ISD::SELECT, MVT::f64, Expand);
1349 // This is a workaround documented in DAGCombiner.cpp:2892 We don't
1350 // support SELECT_CC on every type.
1351 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
1355 if (EmitJumpTables) {
1356 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
1358 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
1360 // Increase jump tables cutover to 5, was 4.
1361 setMinimumJumpTableEntries(5);
1363 setOperationAction(ISD::BR_CC, MVT::f32, Expand);
1364 setOperationAction(ISD::BR_CC, MVT::f64, Expand);
1365 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1366 setOperationAction(ISD::BR_CC, MVT::i32, Expand);
1367 setOperationAction(ISD::BR_CC, MVT::i64, Expand);
1369 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
1371 setOperationAction(ISD::FSIN , MVT::f64, Expand);
1372 setOperationAction(ISD::FCOS , MVT::f64, Expand);
1373 setOperationAction(ISD::FREM , MVT::f64, Expand);
1374 setOperationAction(ISD::FSIN , MVT::f32, Expand);
1375 setOperationAction(ISD::FCOS , MVT::f32, Expand);
1376 setOperationAction(ISD::FREM , MVT::f32, Expand);
1377 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
1378 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
1380 // In V4, we have double word add/sub with carry. The problem with
1381 // modelling this instruction is that it produces 2 results - Rdd and Px.
1382 // To model update of Px, we will have to use Defs[p0..p3] which will
1383 // cause any predicate live range to spill. So, we pretend we dont't
1384 // have these instructions.
1385 setOperationAction(ISD::ADDE, MVT::i8, Expand);
1386 setOperationAction(ISD::ADDE, MVT::i16, Expand);
1387 setOperationAction(ISD::ADDE, MVT::i32, Expand);
1388 setOperationAction(ISD::ADDE, MVT::i64, Expand);
1389 setOperationAction(ISD::SUBE, MVT::i8, Expand);
1390 setOperationAction(ISD::SUBE, MVT::i16, Expand);
1391 setOperationAction(ISD::SUBE, MVT::i32, Expand);
1392 setOperationAction(ISD::SUBE, MVT::i64, Expand);
1393 setOperationAction(ISD::ADDC, MVT::i8, Expand);
1394 setOperationAction(ISD::ADDC, MVT::i16, Expand);
1395 setOperationAction(ISD::ADDC, MVT::i32, Expand);
1396 setOperationAction(ISD::ADDC, MVT::i64, Expand);
1397 setOperationAction(ISD::SUBC, MVT::i8, Expand);
1398 setOperationAction(ISD::SUBC, MVT::i16, Expand);
1399 setOperationAction(ISD::SUBC, MVT::i32, Expand);
1400 setOperationAction(ISD::SUBC, MVT::i64, Expand);
1402 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
1403 setOperationAction(ISD::CTPOP, MVT::i64, Expand);
1404 setOperationAction(ISD::CTTZ , MVT::i32, Expand);
1405 setOperationAction(ISD::CTTZ , MVT::i64, Expand);
1406 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
1407 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
1408 setOperationAction(ISD::CTLZ , MVT::i32, Expand);
1409 setOperationAction(ISD::CTLZ , MVT::i64, Expand);
1410 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
1411 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
1412 setOperationAction(ISD::ROTL , MVT::i32, Expand);
1413 setOperationAction(ISD::ROTR , MVT::i32, Expand);
1414 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
1415 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
1416 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
1417 setOperationAction(ISD::FPOW , MVT::f64, Expand);
1418 setOperationAction(ISD::FPOW , MVT::f32, Expand);
1420 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
1421 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
1422 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
1424 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
1425 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
1427 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
1428 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
1430 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
1431 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
1432 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
1433 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
1435 setOperationAction(ISD::EH_RETURN, MVT::Other, Custom);
1437 if (TM.getSubtargetImpl()->isSubtargetV2()) {
1438 setExceptionPointerRegister(Hexagon::R20);
1439 setExceptionSelectorRegister(Hexagon::R21);
1441 setExceptionPointerRegister(Hexagon::R0);
1442 setExceptionSelectorRegister(Hexagon::R1);
1445 // VASTART needs to be custom lowered to use the VarArgsFrameIndex.
1446 setOperationAction(ISD::VASTART , MVT::Other, Custom);
1448 // Use the default implementation.
1449 setOperationAction(ISD::VAARG , MVT::Other, Expand);
1450 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
1451 setOperationAction(ISD::VAEND , MVT::Other, Expand);
1452 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
1453 setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand);
1456 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
1457 setOperationAction(ISD::INLINEASM , MVT::Other, Custom);
1459 setMinFunctionAlignment(2);
1461 // Needed for DYNAMIC_STACKALLOC expansion.
1462 unsigned StackRegister = TM.getRegisterInfo()->getStackRegister();
1463 setStackPointerRegisterToSaveRestore(StackRegister);
1464 setSchedulingPreference(Sched::VLIW);
1469 HexagonTargetLowering::getTargetNodeName(unsigned Opcode) const {
1472 case HexagonISD::CONST32: return "HexagonISD::CONST32";
1473 case HexagonISD::CONST32_GP: return "HexagonISD::CONST32_GP";
1474 case HexagonISD::CONST32_Int_Real: return "HexagonISD::CONST32_Int_Real";
1475 case HexagonISD::ADJDYNALLOC: return "HexagonISD::ADJDYNALLOC";
1476 case HexagonISD::CMPICC: return "HexagonISD::CMPICC";
1477 case HexagonISD::CMPFCC: return "HexagonISD::CMPFCC";
1478 case HexagonISD::BRICC: return "HexagonISD::BRICC";
1479 case HexagonISD::BRFCC: return "HexagonISD::BRFCC";
1480 case HexagonISD::SELECT_ICC: return "HexagonISD::SELECT_ICC";
1481 case HexagonISD::SELECT_FCC: return "HexagonISD::SELECT_FCC";
1482 case HexagonISD::Hi: return "HexagonISD::Hi";
1483 case HexagonISD::Lo: return "HexagonISD::Lo";
1484 case HexagonISD::FTOI: return "HexagonISD::FTOI";
1485 case HexagonISD::ITOF: return "HexagonISD::ITOF";
1486 case HexagonISD::CALL: return "HexagonISD::CALL";
1487 case HexagonISD::RET_FLAG: return "HexagonISD::RET_FLAG";
1488 case HexagonISD::BR_JT: return "HexagonISD::BR_JT";
1489 case HexagonISD::TC_RETURN: return "HexagonISD::TC_RETURN";
1490 case HexagonISD::EH_RETURN: return "HexagonISD::EH_RETURN";
1495 HexagonTargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
1496 EVT MTy1 = EVT::getEVT(Ty1);
1497 EVT MTy2 = EVT::getEVT(Ty2);
1498 if (!MTy1.isSimple() || !MTy2.isSimple()) {
1501 return ((MTy1.getSimpleVT() == MVT::i64) && (MTy2.getSimpleVT() == MVT::i32));
1504 bool HexagonTargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
1505 if (!VT1.isSimple() || !VT2.isSimple()) {
1508 return ((VT1.getSimpleVT() == MVT::i64) && (VT2.getSimpleVT() == MVT::i32));
1512 HexagonTargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
1513 SDValue Chain = Op.getOperand(0);
1514 SDValue Offset = Op.getOperand(1);
1515 SDValue Handler = Op.getOperand(2);
1516 DebugLoc dl = Op.getDebugLoc();
1518 // Mark function as containing a call to EH_RETURN.
1519 HexagonMachineFunctionInfo *FuncInfo =
1520 DAG.getMachineFunction().getInfo<HexagonMachineFunctionInfo>();
1521 FuncInfo->setHasEHReturn();
1523 unsigned OffsetReg = Hexagon::R28;
1525 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(),
1526 DAG.getRegister(Hexagon::R30, getPointerTy()),
1527 DAG.getIntPtrConstant(4));
1528 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
1530 Chain = DAG.getCopyToReg(Chain, dl, OffsetReg, Offset);
1532 // Not needed we already use it as explict input to EH_RETURN.
1533 // MF.getRegInfo().addLiveOut(OffsetReg);
1535 return DAG.getNode(HexagonISD::EH_RETURN, dl, MVT::Other, Chain);
1539 HexagonTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
1540 switch (Op.getOpcode()) {
1541 default: llvm_unreachable("Should not custom lower this!");
1542 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
1543 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
1544 // Frame & Return address. Currently unimplemented.
1545 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
1546 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
1547 case ISD::GlobalTLSAddress:
1548 llvm_unreachable("TLS not implemented for Hexagon.");
1549 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG);
1550 case ISD::GlobalAddress: return LowerGLOBALADDRESS(Op, DAG);
1551 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
1552 case ISD::VASTART: return LowerVASTART(Op, DAG);
1553 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
1555 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
1556 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
1557 case ISD::SELECT: return Op;
1558 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
1559 case ISD::INLINEASM: return LowerINLINEASM(Op, DAG);
1566 //===----------------------------------------------------------------------===//
1567 // Hexagon Scheduler Hooks
1568 //===----------------------------------------------------------------------===//
1570 HexagonTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
1571 MachineBasicBlock *BB)
1573 switch (MI->getOpcode()) {
1574 case Hexagon::ADJDYNALLOC: {
1575 MachineFunction *MF = BB->getParent();
1576 HexagonMachineFunctionInfo *FuncInfo =
1577 MF->getInfo<HexagonMachineFunctionInfo>();
1578 FuncInfo->addAllocaAdjustInst(MI);
1581 default: llvm_unreachable("Unexpected instr type to insert");
1585 //===----------------------------------------------------------------------===//
1586 // Inline Assembly Support
1587 //===----------------------------------------------------------------------===//
1589 std::pair<unsigned, const TargetRegisterClass*>
1590 HexagonTargetLowering::getRegForInlineAsmConstraint(const
1591 std::string &Constraint,
1593 if (Constraint.size() == 1) {
1594 switch (Constraint[0]) {
1596 switch (VT.getSimpleVT().SimpleTy) {
1598 llvm_unreachable("getRegForInlineAsmConstraint Unhandled data type");
1603 return std::make_pair(0U, &Hexagon::IntRegsRegClass);
1606 return std::make_pair(0U, &Hexagon::DoubleRegsRegClass);
1609 llvm_unreachable("Unknown asm register class");
1613 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
1616 /// isFPImmLegal - Returns true if the target can instruction select the
1617 /// specified FP immediate natively. If false, the legalizer will
1618 /// materialize the FP immediate as a load from a constant pool.
1619 bool HexagonTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
1620 const HexagonRegisterInfo* QRI = TM.getRegisterInfo();
1621 return QRI->Subtarget.hasV5TOps();
1624 /// isLegalAddressingMode - Return true if the addressing mode represented by
1625 /// AM is legal for this target, for a load/store of the specified type.
1626 bool HexagonTargetLowering::isLegalAddressingMode(const AddrMode &AM,
1628 // Allows a signed-extended 11-bit immediate field.
1629 if (AM.BaseOffs <= -(1LL << 13) || AM.BaseOffs >= (1LL << 13)-1) {
1633 // No global is ever allowed as a base.
1638 int Scale = AM.Scale;
1639 if (Scale < 0) Scale = -Scale;
1641 case 0: // No scale reg, "r+i", "r", or just "i".
1643 default: // No scaled addressing mode.
1649 /// isLegalICmpImmediate - Return true if the specified immediate is legal
1650 /// icmp immediate, that is the target has icmp instructions which can compare
1651 /// a register against the immediate without having to materialize the
1652 /// immediate into a register.
1653 bool HexagonTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
1654 return Imm >= -512 && Imm <= 511;
1657 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
1658 /// for tail call optimization. Targets which want to do tail call
1659 /// optimization should implement this function.
1660 bool HexagonTargetLowering::IsEligibleForTailCallOptimization(
1662 CallingConv::ID CalleeCC,
1664 bool isCalleeStructRet,
1665 bool isCallerStructRet,
1666 const SmallVectorImpl<ISD::OutputArg> &Outs,
1667 const SmallVectorImpl<SDValue> &OutVals,
1668 const SmallVectorImpl<ISD::InputArg> &Ins,
1669 SelectionDAG& DAG) const {
1670 const Function *CallerF = DAG.getMachineFunction().getFunction();
1671 CallingConv::ID CallerCC = CallerF->getCallingConv();
1672 bool CCMatch = CallerCC == CalleeCC;
1674 // ***************************************************************************
1675 // Look for obvious safe cases to perform tail call optimization that do not
1676 // require ABI changes.
1677 // ***************************************************************************
1679 // If this is a tail call via a function pointer, then don't do it!
1680 if (!(dyn_cast<GlobalAddressSDNode>(Callee))
1681 && !(dyn_cast<ExternalSymbolSDNode>(Callee))) {
1685 // Do not optimize if the calling conventions do not match.
1689 // Do not tail call optimize vararg calls.
1693 // Also avoid tail call optimization if either caller or callee uses struct
1694 // return semantics.
1695 if (isCalleeStructRet || isCallerStructRet)
1698 // In addition to the cases above, we also disable Tail Call Optimization if
1699 // the calling convention code that at least one outgoing argument needs to
1700 // go on the stack. We cannot check that here because at this point that
1701 // information is not available.