1 //===-- HexagonISelLowering.cpp - Hexagon DAG Lowering Implementation -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the interfaces that Hexagon uses to lower LLVM code
11 // into a selection DAG.
13 //===----------------------------------------------------------------------===//
15 #include "HexagonISelLowering.h"
16 #include "HexagonMachineFunctionInfo.h"
17 #include "HexagonSubtarget.h"
18 #include "HexagonTargetMachine.h"
19 #include "HexagonTargetObjectFile.h"
20 #include "llvm/CodeGen/CallingConvLower.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineJumpTableInfo.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/SelectionDAGISel.h"
27 #include "llvm/CodeGen/ValueTypes.h"
28 #include "llvm/IR/CallingConv.h"
29 #include "llvm/IR/DerivedTypes.h"
30 #include "llvm/IR/Function.h"
31 #include "llvm/IR/GlobalAlias.h"
32 #include "llvm/IR/GlobalVariable.h"
33 #include "llvm/IR/InlineAsm.h"
34 #include "llvm/IR/Intrinsics.h"
35 #include "llvm/Support/CommandLine.h"
36 #include "llvm/Support/Debug.h"
37 #include "llvm/Support/ErrorHandling.h"
38 #include "llvm/Support/raw_ostream.h"
42 #define DEBUG_TYPE "hexagon-lowering"
45 EmitJumpTables("hexagon-emit-jump-tables", cl::init(true), cl::Hidden,
46 cl::desc("Control jump table emission on Hexagon target"));
48 static cl::opt<bool> EnableHexSDNodeSched("enable-hexagon-sdnode-sched",
49 cl::Hidden, cl::ZeroOrMore, cl::init(false),
50 cl::desc("Enable Hexagon SDNode scheduling"));
52 static cl::opt<bool> EnableFastMath("ffast-math",
53 cl::Hidden, cl::ZeroOrMore, cl::init(false),
54 cl::desc("Enable Fast Math processing"));
56 static cl::opt<int> MinimumJumpTables("minimum-jump-tables",
57 cl::Hidden, cl::ZeroOrMore, cl::init(5),
58 cl::desc("Set minimum jump tables"));
60 static cl::opt<int> MaxStoresPerMemcpyCL("max-store-memcpy",
61 cl::Hidden, cl::ZeroOrMore, cl::init(6),
62 cl::desc("Max #stores to inline memcpy"));
64 static cl::opt<int> MaxStoresPerMemcpyOptSizeCL("max-store-memcpy-Os",
65 cl::Hidden, cl::ZeroOrMore, cl::init(4),
66 cl::desc("Max #stores to inline memcpy"));
68 static cl::opt<int> MaxStoresPerMemmoveCL("max-store-memmove",
69 cl::Hidden, cl::ZeroOrMore, cl::init(6),
70 cl::desc("Max #stores to inline memmove"));
72 static cl::opt<int> MaxStoresPerMemmoveOptSizeCL("max-store-memmove-Os",
73 cl::Hidden, cl::ZeroOrMore, cl::init(4),
74 cl::desc("Max #stores to inline memmove"));
76 static cl::opt<int> MaxStoresPerMemsetCL("max-store-memset",
77 cl::Hidden, cl::ZeroOrMore, cl::init(8),
78 cl::desc("Max #stores to inline memset"));
80 static cl::opt<int> MaxStoresPerMemsetOptSizeCL("max-store-memset-Os",
81 cl::Hidden, cl::ZeroOrMore, cl::init(4),
82 cl::desc("Max #stores to inline memset"));
86 class HexagonCCState : public CCState {
87 unsigned NumNamedVarArgParams;
90 HexagonCCState(CallingConv::ID CC, bool isVarArg, MachineFunction &MF,
91 SmallVectorImpl<CCValAssign> &locs, LLVMContext &C,
92 int NumNamedVarArgParams)
93 : CCState(CC, isVarArg, MF, locs, C),
94 NumNamedVarArgParams(NumNamedVarArgParams) {}
96 unsigned getNumNamedVarArgParams() const { return NumNamedVarArgParams; }
100 // Implement calling convention for Hexagon.
102 CC_Hexagon(unsigned ValNo, MVT ValVT,
103 MVT LocVT, CCValAssign::LocInfo LocInfo,
104 ISD::ArgFlagsTy ArgFlags, CCState &State);
107 CC_Hexagon32(unsigned ValNo, MVT ValVT,
108 MVT LocVT, CCValAssign::LocInfo LocInfo,
109 ISD::ArgFlagsTy ArgFlags, CCState &State);
112 CC_Hexagon64(unsigned ValNo, MVT ValVT,
113 MVT LocVT, CCValAssign::LocInfo LocInfo,
114 ISD::ArgFlagsTy ArgFlags, CCState &State);
117 RetCC_Hexagon(unsigned ValNo, MVT ValVT,
118 MVT LocVT, CCValAssign::LocInfo LocInfo,
119 ISD::ArgFlagsTy ArgFlags, CCState &State);
122 RetCC_Hexagon32(unsigned ValNo, MVT ValVT,
123 MVT LocVT, CCValAssign::LocInfo LocInfo,
124 ISD::ArgFlagsTy ArgFlags, CCState &State);
127 RetCC_Hexagon64(unsigned ValNo, MVT ValVT,
128 MVT LocVT, CCValAssign::LocInfo LocInfo,
129 ISD::ArgFlagsTy ArgFlags, CCState &State);
132 CC_Hexagon_VarArg (unsigned ValNo, MVT ValVT,
133 MVT LocVT, CCValAssign::LocInfo LocInfo,
134 ISD::ArgFlagsTy ArgFlags, CCState &State) {
135 HexagonCCState &HState = static_cast<HexagonCCState &>(State);
137 if (ValNo < HState.getNumNamedVarArgParams()) {
138 // Deal with named arguments.
139 return CC_Hexagon(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State);
142 // Deal with un-named arguments.
144 if (ArgFlags.isByVal()) {
145 // If pass-by-value, the size allocated on stack is decided
146 // by ArgFlags.getByValSize(), not by the size of LocVT.
147 ofst = State.AllocateStack(ArgFlags.getByValSize(),
148 ArgFlags.getByValAlign());
149 State.addLoc(CCValAssign::getMem(ValNo, ValVT, ofst, LocVT, LocInfo));
152 if (LocVT == MVT::i1 || LocVT == MVT::i8 || LocVT == MVT::i16) {
155 if (ArgFlags.isSExt())
156 LocInfo = CCValAssign::SExt;
157 else if (ArgFlags.isZExt())
158 LocInfo = CCValAssign::ZExt;
160 LocInfo = CCValAssign::AExt;
162 if (LocVT == MVT::i32 || LocVT == MVT::f32) {
163 ofst = State.AllocateStack(4, 4);
164 State.addLoc(CCValAssign::getMem(ValNo, ValVT, ofst, LocVT, LocInfo));
167 if (LocVT == MVT::i64 || LocVT == MVT::f64) {
168 ofst = State.AllocateStack(8, 8);
169 State.addLoc(CCValAssign::getMem(ValNo, ValVT, ofst, LocVT, LocInfo));
172 llvm_unreachable(nullptr);
177 CC_Hexagon (unsigned ValNo, MVT ValVT,
178 MVT LocVT, CCValAssign::LocInfo LocInfo,
179 ISD::ArgFlagsTy ArgFlags, CCState &State) {
181 if (ArgFlags.isByVal()) {
183 unsigned Offset = State.AllocateStack(ArgFlags.getByValSize(),
184 ArgFlags.getByValAlign());
185 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
189 if (LocVT == MVT::i1 || LocVT == MVT::i8 || LocVT == MVT::i16) {
192 if (ArgFlags.isSExt())
193 LocInfo = CCValAssign::SExt;
194 else if (ArgFlags.isZExt())
195 LocInfo = CCValAssign::ZExt;
197 LocInfo = CCValAssign::AExt;
198 } else if (LocVT == MVT::v4i8 || LocVT == MVT::v2i16) {
200 LocInfo = CCValAssign::BCvt;
201 } else if (LocVT == MVT::v8i8 || LocVT == MVT::v4i16 || LocVT == MVT::v2i32) {
203 LocInfo = CCValAssign::BCvt;
206 if (LocVT == MVT::i32 || LocVT == MVT::f32) {
207 if (!CC_Hexagon32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
211 if (LocVT == MVT::i64 || LocVT == MVT::f64) {
212 if (!CC_Hexagon64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
216 return true; // CC didn't match.
220 static bool CC_Hexagon32(unsigned ValNo, MVT ValVT,
221 MVT LocVT, CCValAssign::LocInfo LocInfo,
222 ISD::ArgFlagsTy ArgFlags, CCState &State) {
224 static const MCPhysReg RegList[] = {
225 Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4,
228 if (unsigned Reg = State.AllocateReg(RegList)) {
229 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
233 unsigned Offset = State.AllocateStack(4, 4);
234 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
238 static bool CC_Hexagon64(unsigned ValNo, MVT ValVT,
239 MVT LocVT, CCValAssign::LocInfo LocInfo,
240 ISD::ArgFlagsTy ArgFlags, CCState &State) {
242 if (unsigned Reg = State.AllocateReg(Hexagon::D0)) {
243 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
247 static const MCPhysReg RegList1[] = {
248 Hexagon::D1, Hexagon::D2
250 static const MCPhysReg RegList2[] = {
251 Hexagon::R1, Hexagon::R3
253 if (unsigned Reg = State.AllocateReg(RegList1, RegList2)) {
254 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
258 unsigned Offset = State.AllocateStack(8, 8, Hexagon::D2);
259 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
263 static bool RetCC_Hexagon(unsigned ValNo, MVT ValVT,
264 MVT LocVT, CCValAssign::LocInfo LocInfo,
265 ISD::ArgFlagsTy ArgFlags, CCState &State) {
268 if (LocVT == MVT::i1 ||
273 if (ArgFlags.isSExt())
274 LocInfo = CCValAssign::SExt;
275 else if (ArgFlags.isZExt())
276 LocInfo = CCValAssign::ZExt;
278 LocInfo = CCValAssign::AExt;
279 } else if (LocVT == MVT::v4i8 || LocVT == MVT::v2i16) {
281 LocInfo = CCValAssign::BCvt;
282 } else if (LocVT == MVT::v8i8 || LocVT == MVT::v4i16 || LocVT == MVT::v2i32) {
284 LocInfo = CCValAssign::BCvt;
287 if (LocVT == MVT::i32 || LocVT == MVT::f32) {
288 if (!RetCC_Hexagon32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
292 if (LocVT == MVT::i64 || LocVT == MVT::f64) {
293 if (!RetCC_Hexagon64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
297 return true; // CC didn't match.
300 static bool RetCC_Hexagon32(unsigned ValNo, MVT ValVT,
301 MVT LocVT, CCValAssign::LocInfo LocInfo,
302 ISD::ArgFlagsTy ArgFlags, CCState &State) {
304 if (LocVT == MVT::i32 || LocVT == MVT::f32) {
305 if (unsigned Reg = State.AllocateReg(Hexagon::R0)) {
306 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
311 unsigned Offset = State.AllocateStack(4, 4);
312 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
316 static bool RetCC_Hexagon64(unsigned ValNo, MVT ValVT,
317 MVT LocVT, CCValAssign::LocInfo LocInfo,
318 ISD::ArgFlagsTy ArgFlags, CCState &State) {
319 if (LocVT == MVT::i64 || LocVT == MVT::f64) {
320 if (unsigned Reg = State.AllocateReg(Hexagon::D0)) {
321 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
326 unsigned Offset = State.AllocateStack(8, 8);
327 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
332 HexagonTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG)
337 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
338 /// by "Src" to address "Dst" of size "Size". Alignment information is
339 /// specified by the specific parameter attribute. The copy will be passed as
340 /// a byval function parameter. Sometimes what we are copying is the end of a
341 /// larger object, the part that does not fit in registers.
343 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
344 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
347 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32);
348 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
349 /*isVolatile=*/false, /*AlwaysInline=*/false,
350 /*isTailCall=*/false,
351 MachinePointerInfo(), MachinePointerInfo());
355 // LowerReturn - Lower ISD::RET. If a struct is larger than 8 bytes and is
356 // passed by value, the function prototype is modified to return void and
357 // the value is stored in memory pointed by a pointer passed by caller.
359 HexagonTargetLowering::LowerReturn(SDValue Chain,
360 CallingConv::ID CallConv, bool isVarArg,
361 const SmallVectorImpl<ISD::OutputArg> &Outs,
362 const SmallVectorImpl<SDValue> &OutVals,
363 SDLoc dl, SelectionDAG &DAG) const {
365 // CCValAssign - represent the assignment of the return value to locations.
366 SmallVector<CCValAssign, 16> RVLocs;
368 // CCState - Info about the registers and stack slot.
369 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
372 // Analyze return values of ISD::RET
373 CCInfo.AnalyzeReturn(Outs, RetCC_Hexagon);
376 SmallVector<SDValue, 4> RetOps(1, Chain);
378 // Copy the result values into the output registers.
379 for (unsigned i = 0; i != RVLocs.size(); ++i) {
380 CCValAssign &VA = RVLocs[i];
382 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag);
384 // Guarantee that all emitted copies are stuck together with flags.
385 Flag = Chain.getValue(1);
386 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
389 RetOps[0] = Chain; // Update chain.
391 // Add the flag if we have it.
393 RetOps.push_back(Flag);
395 return DAG.getNode(HexagonISD::RET_FLAG, dl, MVT::Other, RetOps);
398 bool HexagonTargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
399 // If either no tail call or told not to tail call at all, don't.
401 CI->getParent()->getParent()->getFnAttribute("disable-tail-calls");
402 if (!CI->isTailCall() || Attr.getValueAsString() == "true")
408 /// LowerCallResult - Lower the result values of an ISD::CALL into the
409 /// appropriate copies out of appropriate physical registers. This assumes that
410 /// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
411 /// being lowered. Returns a SDNode with the same number of values as the
414 HexagonTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
415 CallingConv::ID CallConv, bool isVarArg,
417 SmallVectorImpl<ISD::InputArg> &Ins,
418 SDLoc dl, SelectionDAG &DAG,
419 SmallVectorImpl<SDValue> &InVals,
420 const SmallVectorImpl<SDValue> &OutVals,
421 SDValue Callee) const {
423 // Assign locations to each value returned by this call.
424 SmallVector<CCValAssign, 16> RVLocs;
426 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
429 CCInfo.AnalyzeCallResult(Ins, RetCC_Hexagon);
431 // Copy all of the result registers out of their specified physreg.
432 for (unsigned i = 0; i != RVLocs.size(); ++i) {
433 Chain = DAG.getCopyFromReg(Chain, dl,
434 RVLocs[i].getLocReg(),
435 RVLocs[i].getValVT(), InFlag).getValue(1);
436 InFlag = Chain.getValue(2);
437 InVals.push_back(Chain.getValue(0));
443 /// LowerCall - Functions arguments are copied from virtual regs to
444 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
446 HexagonTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
447 SmallVectorImpl<SDValue> &InVals) const {
448 SelectionDAG &DAG = CLI.DAG;
450 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
451 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
452 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
453 SDValue Chain = CLI.Chain;
454 SDValue Callee = CLI.Callee;
455 bool &isTailCall = CLI.IsTailCall;
456 CallingConv::ID CallConv = CLI.CallConv;
457 bool isVarArg = CLI.IsVarArg;
458 bool doesNotReturn = CLI.DoesNotReturn;
460 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
461 MachineFunction &MF = DAG.getMachineFunction();
462 auto PtrVT = getPointerTy(MF.getDataLayout());
464 // Check for varargs.
465 int NumNamedVarArgParams = -1;
466 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Callee))
468 const Function* CalleeFn = nullptr;
469 Callee = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, MVT::i32);
470 if ((CalleeFn = dyn_cast<Function>(GA->getGlobal())))
472 // If a function has zero args and is a vararg function, that's
473 // disallowed so it must be an undeclared function. Do not assume
474 // varargs if the callee is undefined.
475 if (CalleeFn->isVarArg() &&
476 CalleeFn->getFunctionType()->getNumParams() != 0) {
477 NumNamedVarArgParams = CalleeFn->getFunctionType()->getNumParams();
482 // Analyze operands of the call, assigning locations to each operand.
483 SmallVector<CCValAssign, 16> ArgLocs;
484 HexagonCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
485 *DAG.getContext(), NumNamedVarArgParams);
488 CCInfo.AnalyzeCallOperands(Outs, CC_Hexagon_VarArg);
490 CCInfo.AnalyzeCallOperands(Outs, CC_Hexagon);
492 auto Attr = MF.getFunction()->getFnAttribute("disable-tail-calls");
493 if (Attr.getValueAsString() == "true")
497 bool StructAttrFlag = MF.getFunction()->hasStructRetAttr();
498 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
499 isVarArg, IsStructRet,
501 Outs, OutVals, Ins, DAG);
502 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
503 CCValAssign &VA = ArgLocs[i];
509 DEBUG(dbgs() << (isTailCall ? "Eligible for Tail Call\n"
510 : "Argument must be passed on stack. "
511 "Not eligible for Tail Call\n"));
513 // Get a count of how many bytes are to be pushed on the stack.
514 unsigned NumBytes = CCInfo.getNextStackOffset();
515 SmallVector<std::pair<unsigned, SDValue>, 16> RegsToPass;
516 SmallVector<SDValue, 8> MemOpChains;
518 auto &HRI = *Subtarget.getRegisterInfo();
520 DAG.getCopyFromReg(Chain, dl, HRI.getStackRegister(), PtrVT);
522 // Walk the register/memloc assignments, inserting copies/loads.
523 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
524 CCValAssign &VA = ArgLocs[i];
525 SDValue Arg = OutVals[i];
526 ISD::ArgFlagsTy Flags = Outs[i].Flags;
528 // Promote the value if needed.
529 switch (VA.getLocInfo()) {
531 // Loc info must be one of Full, SExt, ZExt, or AExt.
532 llvm_unreachable("Unknown loc info!");
533 case CCValAssign::BCvt:
534 case CCValAssign::Full:
536 case CCValAssign::SExt:
537 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
539 case CCValAssign::ZExt:
540 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
542 case CCValAssign::AExt:
543 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
548 unsigned LocMemOffset = VA.getLocMemOffset();
549 SDValue MemAddr = DAG.getConstant(LocMemOffset, dl,
550 StackPtr.getValueType());
551 MemAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, MemAddr);
552 if (Flags.isByVal()) {
553 // The argument is a struct passed by value. According to LLVM, "Arg"
555 MemOpChains.push_back(CreateCopyOfByValArgument(Arg, MemAddr, Chain,
558 MachinePointerInfo LocPI = MachinePointerInfo::getStack(
559 DAG.getMachineFunction(), LocMemOffset);
560 SDValue S = DAG.getStore(Chain, dl, Arg, MemAddr, LocPI, false,
562 MemOpChains.push_back(S);
567 // Arguments that can be passed on register must be kept at RegsToPass
570 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
573 // Transform all store nodes into one single node because all store
574 // nodes are independent of each other.
575 if (!MemOpChains.empty())
576 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
579 SDValue C = DAG.getConstant(NumBytes, dl, PtrVT, true);
580 Chain = DAG.getCALLSEQ_START(Chain, C, dl);
583 // Build a sequence of copy-to-reg nodes chained together with token
584 // chain and flag operands which copy the outgoing args into registers.
585 // The InFlag in necessary since all emitted instructions must be
589 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
590 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
591 RegsToPass[i].second, InFlag);
592 InFlag = Chain.getValue(1);
595 // For tail calls lower the arguments to the 'real' stack slot.
597 // Force all the incoming stack arguments to be loaded from the stack
598 // before any new outgoing arguments are stored to the stack, because the
599 // outgoing stack slots may alias the incoming argument stack slots, and
600 // the alias isn't otherwise explicit. This is slightly more conservative
601 // than necessary, because it means that each store effectively depends
602 // on every argument instead of just those arguments it would clobber.
604 // Do not flag preceding copytoreg stuff together with the following stuff.
606 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
607 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
608 RegsToPass[i].second, InFlag);
609 InFlag = Chain.getValue(1);
614 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
615 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
616 // node so that legalize doesn't hack it.
617 if (flag_aligned_memcpy) {
618 const char *MemcpyName =
619 "__hexagon_memcpy_likely_aligned_min32bytes_mult8bytes";
620 Callee = DAG.getTargetExternalSymbol(MemcpyName, PtrVT);
621 flag_aligned_memcpy = false;
622 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
623 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, PtrVT);
624 } else if (ExternalSymbolSDNode *S =
625 dyn_cast<ExternalSymbolSDNode>(Callee)) {
626 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), PtrVT);
629 // Returns a chain & a flag for retval copy to use.
630 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
631 SmallVector<SDValue, 8> Ops;
632 Ops.push_back(Chain);
633 Ops.push_back(Callee);
635 // Add argument registers to the end of the list so that they are
636 // known live into the call.
637 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
638 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
639 RegsToPass[i].second.getValueType()));
642 if (InFlag.getNode())
643 Ops.push_back(InFlag);
646 MF.getFrameInfo()->setHasTailCall();
647 return DAG.getNode(HexagonISD::TC_RETURN, dl, NodeTys, Ops);
650 int OpCode = doesNotReturn ? HexagonISD::CALLv3nr : HexagonISD::CALLv3;
651 Chain = DAG.getNode(OpCode, dl, NodeTys, Ops);
652 InFlag = Chain.getValue(1);
654 // Create the CALLSEQ_END node.
655 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
656 DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
657 InFlag = Chain.getValue(1);
659 // Handle result values, copying them out of physregs into vregs that we
661 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl, DAG,
662 InVals, OutVals, Callee);
665 static bool getIndexedAddressParts(SDNode *Ptr, EVT VT,
666 bool isSEXTLoad, SDValue &Base,
667 SDValue &Offset, bool &isInc,
669 if (Ptr->getOpcode() != ISD::ADD)
672 if (VT == MVT::i64 || VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) {
673 isInc = (Ptr->getOpcode() == ISD::ADD);
674 Base = Ptr->getOperand(0);
675 Offset = Ptr->getOperand(1);
676 // Ensure that Offset is a constant.
677 return (isa<ConstantSDNode>(Offset));
683 // TODO: Put this function along with the other isS* functions in
684 // HexagonISelDAGToDAG.cpp into a common file. Or better still, use the
685 // functions defined in HexagonOperands.td.
686 static bool Is_PostInc_S4_Offset(SDNode * S, int ShiftAmount) {
687 ConstantSDNode *N = cast<ConstantSDNode>(S);
689 // immS4 predicate - True if the immediate fits in a 4-bit sign extended.
691 int64_t v = (int64_t)N->getSExtValue();
693 if (ShiftAmount > 0) {
695 v = v >> ShiftAmount;
697 return (v <= 7) && (v >= -8) && (m == 0);
700 /// getPostIndexedAddressParts - returns true by value, base pointer and
701 /// offset pointer and addressing mode by reference if this node can be
702 /// combined with a load / store to form a post-indexed load / store.
703 bool HexagonTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
706 ISD::MemIndexedMode &AM,
707 SelectionDAG &DAG) const
711 bool isSEXTLoad = false;
713 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
714 VT = LD->getMemoryVT();
715 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
716 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
717 VT = ST->getMemoryVT();
718 if (ST->getValue().getValueType() == MVT::i64 && ST->isTruncatingStore()) {
726 bool isLegal = getIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
728 // ShiftAmount = number of left-shifted bits in the Hexagon instruction.
729 int ShiftAmount = VT.getSizeInBits() / 16;
730 if (isLegal && Is_PostInc_S4_Offset(Offset.getNode(), ShiftAmount)) {
731 AM = isInc ? ISD::POST_INC : ISD::POST_DEC;
738 SDValue HexagonTargetLowering::LowerINLINEASM(SDValue Op,
739 SelectionDAG &DAG) const {
740 SDNode *Node = Op.getNode();
741 MachineFunction &MF = DAG.getMachineFunction();
742 auto &FuncInfo = *MF.getInfo<HexagonMachineFunctionInfo>();
743 switch (Node->getOpcode()) {
744 case ISD::INLINEASM: {
745 unsigned NumOps = Node->getNumOperands();
746 if (Node->getOperand(NumOps-1).getValueType() == MVT::Glue)
747 --NumOps; // Ignore the flag operand.
749 for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
750 if (FuncInfo.hasClobberLR())
753 cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue();
754 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
755 ++i; // Skip the ID value.
757 switch (InlineAsm::getKind(Flags)) {
758 default: llvm_unreachable("Bad flags!");
759 case InlineAsm::Kind_RegDef:
760 case InlineAsm::Kind_RegUse:
761 case InlineAsm::Kind_Imm:
762 case InlineAsm::Kind_Clobber:
763 case InlineAsm::Kind_Mem: {
764 for (; NumVals; --NumVals, ++i) {}
767 case InlineAsm::Kind_RegDefEarlyClobber: {
768 for (; NumVals; --NumVals, ++i) {
770 cast<RegisterSDNode>(Node->getOperand(i))->getReg();
773 const HexagonRegisterInfo *QRI = Subtarget.getRegisterInfo();
774 if (Reg == QRI->getRARegister()) {
775 FuncInfo.setHasClobberLR(true);
790 // Taken from the XCore backend.
792 SDValue HexagonTargetLowering::
793 LowerBR_JT(SDValue Op, SelectionDAG &DAG) const
795 SDValue Chain = Op.getOperand(0);
796 SDValue Table = Op.getOperand(1);
797 SDValue Index = Op.getOperand(2);
799 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
800 unsigned JTI = JT->getIndex();
801 MachineFunction &MF = DAG.getMachineFunction();
802 const MachineJumpTableInfo *MJTI = MF.getJumpTableInfo();
803 SDValue TargetJT = DAG.getTargetJumpTable(JT->getIndex(), MVT::i32);
805 // Mark all jump table targets as address taken.
806 const std::vector<MachineJumpTableEntry> &JTE = MJTI->getJumpTables();
807 const std::vector<MachineBasicBlock*> &JTBBs = JTE[JTI].MBBs;
808 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
809 MachineBasicBlock *MBB = JTBBs[i];
810 MBB->setHasAddressTaken();
811 // This line is needed to set the hasAddressTaken flag on the BasicBlock
813 BlockAddress::get(const_cast<BasicBlock *>(MBB->getBasicBlock()));
816 SDValue JumpTableBase = DAG.getNode(
817 HexagonISD::JT, dl, getPointerTy(DAG.getDataLayout()), TargetJT);
818 SDValue ShiftIndex = DAG.getNode(ISD::SHL, dl, MVT::i32, Index,
819 DAG.getConstant(2, dl, MVT::i32));
820 SDValue JTAddress = DAG.getNode(ISD::ADD, dl, MVT::i32, JumpTableBase,
822 SDValue LoadTarget = DAG.getLoad(MVT::i32, dl, Chain, JTAddress,
823 MachinePointerInfo(), false, false, false,
825 return DAG.getNode(HexagonISD::BR_JT, dl, MVT::Other, Chain, LoadTarget);
830 HexagonTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
831 SelectionDAG &DAG) const {
832 SDValue Chain = Op.getOperand(0);
833 SDValue Size = Op.getOperand(1);
834 SDValue Align = Op.getOperand(2);
837 ConstantSDNode *AlignConst = dyn_cast<ConstantSDNode>(Align);
838 assert(AlignConst && "Non-constant Align in LowerDYNAMIC_STACKALLOC");
840 unsigned A = AlignConst->getSExtValue();
841 auto &HFI = *Subtarget.getFrameLowering();
842 // "Zero" means natural stack alignment.
844 A = HFI.getStackAlignment();
847 dbgs () << LLVM_FUNCTION_NAME << " Align: " << A << " Size: ";
848 Size.getNode()->dump(&DAG);
852 SDValue AC = DAG.getConstant(A, dl, MVT::i32);
853 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::Other);
854 return DAG.getNode(HexagonISD::ALLOCA, dl, VTs, Chain, Size, AC);
858 HexagonTargetLowering::LowerFormalArguments(SDValue Chain,
859 CallingConv::ID CallConv,
862 SmallVectorImpl<ISD::InputArg> &Ins,
863 SDLoc dl, SelectionDAG &DAG,
864 SmallVectorImpl<SDValue> &InVals)
867 MachineFunction &MF = DAG.getMachineFunction();
868 MachineFrameInfo *MFI = MF.getFrameInfo();
869 MachineRegisterInfo &RegInfo = MF.getRegInfo();
870 auto &FuncInfo = *MF.getInfo<HexagonMachineFunctionInfo>();
872 // Assign locations to all of the incoming arguments.
873 SmallVector<CCValAssign, 16> ArgLocs;
874 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
877 CCInfo.AnalyzeFormalArguments(Ins, CC_Hexagon);
879 // For LLVM, in the case when returning a struct by value (>8byte),
880 // the first argument is a pointer that points to the location on caller's
881 // stack where the return value will be stored. For Hexagon, the location on
882 // caller's stack is passed only when the struct size is smaller than (and
883 // equal to) 8 bytes. If not, no address will be passed into callee and
884 // callee return the result direclty through R0/R1.
886 SmallVector<SDValue, 4> MemOps;
888 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
889 CCValAssign &VA = ArgLocs[i];
890 ISD::ArgFlagsTy Flags = Ins[i].Flags;
892 unsigned StackLocation;
895 if ( (VA.isRegLoc() && !Flags.isByVal())
896 || (VA.isRegLoc() && Flags.isByVal() && Flags.getByValSize() > 8)) {
897 // Arguments passed in registers
898 // 1. int, long long, ptr args that get allocated in register.
899 // 2. Large struct that gets an register to put its address in.
900 EVT RegVT = VA.getLocVT();
901 if (RegVT == MVT::i8 || RegVT == MVT::i16 ||
902 RegVT == MVT::i32 || RegVT == MVT::f32) {
904 RegInfo.createVirtualRegister(&Hexagon::IntRegsRegClass);
905 RegInfo.addLiveIn(VA.getLocReg(), VReg);
906 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
907 } else if (RegVT == MVT::i64 || RegVT == MVT::f64) {
909 RegInfo.createVirtualRegister(&Hexagon::DoubleRegsRegClass);
910 RegInfo.addLiveIn(VA.getLocReg(), VReg);
911 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
915 } else if (VA.isRegLoc() && Flags.isByVal() && Flags.getByValSize() <= 8) {
916 assert (0 && "ByValSize must be bigger than 8 bytes");
919 assert(VA.isMemLoc());
921 if (Flags.isByVal()) {
922 // If it's a byval parameter, then we need to compute the
923 // "real" size, not the size of the pointer.
924 ObjSize = Flags.getByValSize();
926 ObjSize = VA.getLocVT().getStoreSizeInBits() >> 3;
929 StackLocation = HEXAGON_LRFP_SIZE + VA.getLocMemOffset();
930 // Create the frame index object for this incoming parameter...
931 FI = MFI->CreateFixedObject(ObjSize, StackLocation, true);
933 // Create the SelectionDAG nodes cordl, responding to a load
934 // from this parameter.
935 SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
937 if (Flags.isByVal()) {
938 // If it's a pass-by-value aggregate, then do not dereference the stack
939 // location. Instead, we should generate a reference to the stack
941 InVals.push_back(FIN);
943 InVals.push_back(DAG.getLoad(VA.getLocVT(), dl, Chain, FIN,
944 MachinePointerInfo(), false, false,
951 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
954 // This will point to the next argument passed via stack.
955 int FrameIndex = MFI->CreateFixedObject(Hexagon_PointerSize,
957 CCInfo.getNextStackOffset(),
959 FuncInfo.setVarArgsFrameIndex(FrameIndex);
966 HexagonTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
967 // VASTART stores the address of the VarArgsFrameIndex slot into the
968 // memory location argument.
969 MachineFunction &MF = DAG.getMachineFunction();
970 HexagonMachineFunctionInfo *QFI = MF.getInfo<HexagonMachineFunctionInfo>();
971 SDValue Addr = DAG.getFrameIndex(QFI->getVarArgsFrameIndex(), MVT::i32);
972 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
973 return DAG.getStore(Op.getOperand(0), SDLoc(Op), Addr,
974 Op.getOperand(1), MachinePointerInfo(SV), false,
978 // Creates a SPLAT instruction for a constant value VAL.
979 static SDValue createSplat(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue Val) {
980 if (VT.getSimpleVT() == MVT::v4i8)
981 return DAG.getNode(HexagonISD::VSPLATB, dl, VT, Val);
983 if (VT.getSimpleVT() == MVT::v4i16)
984 return DAG.getNode(HexagonISD::VSPLATH, dl, VT, Val);
989 static bool isSExtFree(SDValue N) {
990 // A sign-extend of a truncate of a sign-extend is free.
991 if (N.getOpcode() == ISD::TRUNCATE &&
992 N.getOperand(0).getOpcode() == ISD::AssertSext)
994 // We have sign-extended loads.
995 if (N.getOpcode() == ISD::LOAD)
1000 SDValue HexagonTargetLowering::LowerCTPOP(SDValue Op, SelectionDAG &DAG) const {
1002 SDValue InpVal = Op.getOperand(0);
1003 if (isa<ConstantSDNode>(InpVal)) {
1004 uint64_t V = cast<ConstantSDNode>(InpVal)->getZExtValue();
1005 return DAG.getTargetConstant(countPopulation(V), dl, MVT::i64);
1007 SDValue PopOut = DAG.getNode(HexagonISD::POPCOUNT, dl, MVT::i32, InpVal);
1008 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, PopOut);
1011 SDValue HexagonTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
1014 SDValue LHS = Op.getOperand(0);
1015 SDValue RHS = Op.getOperand(1);
1016 SDValue Cmp = Op.getOperand(2);
1017 ISD::CondCode CC = cast<CondCodeSDNode>(Cmp)->get();
1019 EVT VT = Op.getValueType();
1020 EVT LHSVT = LHS.getValueType();
1021 EVT RHSVT = RHS.getValueType();
1023 if (LHSVT == MVT::v2i16) {
1024 assert(ISD::isSignedIntSetCC(CC) || ISD::isUnsignedIntSetCC(CC));
1025 unsigned ExtOpc = ISD::isSignedIntSetCC(CC) ? ISD::SIGN_EXTEND
1027 SDValue LX = DAG.getNode(ExtOpc, dl, MVT::v2i32, LHS);
1028 SDValue RX = DAG.getNode(ExtOpc, dl, MVT::v2i32, RHS);
1029 SDValue SC = DAG.getNode(ISD::SETCC, dl, MVT::v2i1, LX, RX, Cmp);
1033 // Treat all other vector types as legal.
1037 // Equals and not equals should use sign-extend, not zero-extend, since
1038 // we can represent small negative values in the compare instructions.
1039 // The LLVM default is to use zero-extend arbitrarily in these cases.
1040 if ((CC == ISD::SETEQ || CC == ISD::SETNE) &&
1041 (RHSVT == MVT::i8 || RHSVT == MVT::i16) &&
1042 (LHSVT == MVT::i8 || LHSVT == MVT::i16)) {
1043 ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS);
1044 if (C && C->getAPIntValue().isNegative()) {
1045 LHS = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i32, LHS);
1046 RHS = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i32, RHS);
1047 return DAG.getNode(ISD::SETCC, dl, Op.getValueType(),
1048 LHS, RHS, Op.getOperand(2));
1050 if (isSExtFree(LHS) || isSExtFree(RHS)) {
1051 LHS = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i32, LHS);
1052 RHS = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i32, RHS);
1053 return DAG.getNode(ISD::SETCC, dl, Op.getValueType(),
1054 LHS, RHS, Op.getOperand(2));
1060 SDValue HexagonTargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG)
1062 SDValue PredOp = Op.getOperand(0);
1063 SDValue Op1 = Op.getOperand(1), Op2 = Op.getOperand(2);
1064 EVT OpVT = Op1.getValueType();
1067 if (OpVT == MVT::v2i16) {
1068 SDValue X1 = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v2i32, Op1);
1069 SDValue X2 = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v2i32, Op2);
1070 SDValue SL = DAG.getNode(ISD::VSELECT, DL, MVT::v2i32, PredOp, X1, X2);
1071 SDValue TR = DAG.getNode(ISD::TRUNCATE, DL, MVT::v2i16, SL);
1078 // Handle only specific vector loads.
1079 SDValue HexagonTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
1080 EVT VT = Op.getValueType();
1082 LoadSDNode *LoadNode = cast<LoadSDNode>(Op);
1083 SDValue Chain = LoadNode->getChain();
1084 SDValue Ptr = Op.getOperand(1);
1085 SDValue LoweredLoad;
1087 SDValue Base = LoadNode->getBasePtr();
1088 ISD::LoadExtType Ext = LoadNode->getExtensionType();
1089 unsigned Alignment = LoadNode->getAlignment();
1092 if(Ext == ISD::NON_EXTLOAD)
1093 Ext = ISD::ZEXTLOAD;
1095 if (VT == MVT::v4i16) {
1096 if (Alignment == 2) {
1099 Loads[0] = DAG.getExtLoad(Ext, DL, MVT::i32, Chain, Base,
1100 LoadNode->getPointerInfo(), MVT::i16,
1101 LoadNode->isVolatile(),
1102 LoadNode->isNonTemporal(),
1103 LoadNode->isInvariant(),
1106 SDValue Increment = DAG.getConstant(2, DL, MVT::i32);
1107 Ptr = DAG.getNode(ISD::ADD, DL, Base.getValueType(), Base, Increment);
1108 Loads[1] = DAG.getExtLoad(Ext, DL, MVT::i32, Chain, Ptr,
1109 LoadNode->getPointerInfo(), MVT::i16,
1110 LoadNode->isVolatile(),
1111 LoadNode->isNonTemporal(),
1112 LoadNode->isInvariant(),
1114 // SHL 16, then OR base and base+2.
1115 SDValue ShiftAmount = DAG.getConstant(16, DL, MVT::i32);
1116 SDValue Tmp1 = DAG.getNode(ISD::SHL, DL, MVT::i32, Loads[1], ShiftAmount);
1117 SDValue Tmp2 = DAG.getNode(ISD::OR, DL, MVT::i32, Tmp1, Loads[0]);
1119 Increment = DAG.getConstant(4, DL, MVT::i32);
1120 Ptr = DAG.getNode(ISD::ADD, DL, Base.getValueType(), Base, Increment);
1121 Loads[2] = DAG.getExtLoad(Ext, DL, MVT::i32, Chain, Ptr,
1122 LoadNode->getPointerInfo(), MVT::i16,
1123 LoadNode->isVolatile(),
1124 LoadNode->isNonTemporal(),
1125 LoadNode->isInvariant(),
1128 Increment = DAG.getConstant(6, DL, MVT::i32);
1129 Ptr = DAG.getNode(ISD::ADD, DL, Base.getValueType(), Base, Increment);
1130 Loads[3] = DAG.getExtLoad(Ext, DL, MVT::i32, Chain, Ptr,
1131 LoadNode->getPointerInfo(), MVT::i16,
1132 LoadNode->isVolatile(),
1133 LoadNode->isNonTemporal(),
1134 LoadNode->isInvariant(),
1136 // SHL 16, then OR base+4 and base+6.
1137 Tmp1 = DAG.getNode(ISD::SHL, DL, MVT::i32, Loads[3], ShiftAmount);
1138 SDValue Tmp4 = DAG.getNode(ISD::OR, DL, MVT::i32, Tmp1, Loads[2]);
1139 // Combine to i64. This could be optimised out later if we can
1140 // affect reg allocation of this code.
1141 Result = DAG.getNode(HexagonISD::COMBINE, DL, MVT::i64, Tmp4, Tmp2);
1142 LoadChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
1143 Loads[0].getValue(1), Loads[1].getValue(1),
1144 Loads[2].getValue(1), Loads[3].getValue(1));
1146 // Perform default type expansion.
1147 Result = DAG.getLoad(MVT::i64, DL, Chain, Ptr, LoadNode->getPointerInfo(),
1148 LoadNode->isVolatile(), LoadNode->isNonTemporal(),
1149 LoadNode->isInvariant(), LoadNode->getAlignment());
1150 LoadChain = Result.getValue(1);
1153 llvm_unreachable("Custom lowering unsupported load");
1155 Result = DAG.getNode(ISD::BITCAST, DL, VT, Result);
1156 // Since we pretend to lower a load, we need the original chain
1157 // info attached to the result.
1158 SDValue Ops[] = { Result, LoadChain };
1160 return DAG.getMergeValues(Ops, DL);
1165 HexagonTargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
1166 EVT ValTy = Op.getValueType();
1168 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1170 if (CP->isMachineConstantPoolEntry())
1171 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), ValTy,
1172 CP->getAlignment());
1174 Res = DAG.getTargetConstantPool(CP->getConstVal(), ValTy,
1175 CP->getAlignment());
1176 return DAG.getNode(HexagonISD::CP, dl, ValTy, Res);
1180 HexagonTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const {
1181 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
1182 MachineFunction &MF = DAG.getMachineFunction();
1183 MachineFrameInfo &MFI = *MF.getFrameInfo();
1184 MFI.setReturnAddressIsTaken(true);
1186 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
1189 EVT VT = Op.getValueType();
1191 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1193 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
1194 SDValue Offset = DAG.getConstant(4, dl, MVT::i32);
1195 return DAG.getLoad(VT, dl, DAG.getEntryNode(),
1196 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
1197 MachinePointerInfo(), false, false, false, 0);
1200 // Return LR, which contains the return address. Mark it an implicit live-in.
1201 unsigned Reg = MF.addLiveIn(HRI.getRARegister(), getRegClassFor(MVT::i32));
1202 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
1206 HexagonTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
1207 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
1208 MachineFrameInfo &MFI = *DAG.getMachineFunction().getFrameInfo();
1209 MFI.setFrameAddressIsTaken(true);
1211 EVT VT = Op.getValueType();
1213 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1214 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
1215 HRI.getFrameRegister(), VT);
1217 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
1218 MachinePointerInfo(),
1219 false, false, false, 0);
1223 SDValue HexagonTargetLowering::LowerATOMIC_FENCE(SDValue Op,
1224 SelectionDAG& DAG) const {
1226 return DAG.getNode(HexagonISD::BARRIER, dl, MVT::Other, Op.getOperand(0));
1230 SDValue HexagonTargetLowering::LowerGLOBALADDRESS(SDValue Op,
1231 SelectionDAG &DAG) const {
1233 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1234 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
1236 auto PtrVT = getPointerTy(DAG.getDataLayout());
1237 Result = DAG.getTargetGlobalAddress(GV, dl, PtrVT, Offset);
1239 const HexagonTargetObjectFile *TLOF =
1240 static_cast<const HexagonTargetObjectFile *>(
1241 getTargetMachine().getObjFileLowering());
1242 if (TLOF->IsGlobalInSmallSection(GV, getTargetMachine())) {
1243 return DAG.getNode(HexagonISD::CONST32_GP, dl, PtrVT, Result);
1246 return DAG.getNode(HexagonISD::CONST32, dl, PtrVT, Result);
1249 // Specifies that for loads and stores VT can be promoted to PromotedLdStVT.
1250 void HexagonTargetLowering::promoteLdStType(EVT VT, EVT PromotedLdStVT) {
1251 if (VT != PromotedLdStVT) {
1252 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
1253 AddPromotedToType(ISD::LOAD, VT.getSimpleVT(),
1254 PromotedLdStVT.getSimpleVT());
1256 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
1257 AddPromotedToType(ISD::STORE, VT.getSimpleVT(),
1258 PromotedLdStVT.getSimpleVT());
1263 HexagonTargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
1264 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1265 SDValue BA_SD = DAG.getTargetBlockAddress(BA, MVT::i32);
1267 return DAG.getNode(HexagonISD::CONST32_GP, dl,
1268 getPointerTy(DAG.getDataLayout()), BA_SD);
1271 //===----------------------------------------------------------------------===//
1272 // TargetLowering Implementation
1273 //===----------------------------------------------------------------------===//
1275 HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM,
1276 const HexagonSubtarget &STI)
1277 : TargetLowering(TM), HTM(static_cast<const HexagonTargetMachine&>(TM)),
1279 bool IsV4 = !Subtarget.hasV5TOps();
1280 auto &HRI = *Subtarget.getRegisterInfo();
1282 setPrefLoopAlignment(4);
1283 setPrefFunctionAlignment(4);
1284 setMinFunctionAlignment(2);
1285 setInsertFencesForAtomic(false);
1286 setExceptionPointerRegister(Hexagon::R0);
1287 setExceptionSelectorRegister(Hexagon::R1);
1288 setStackPointerRegisterToSaveRestore(HRI.getStackRegister());
1290 if (EnableHexSDNodeSched)
1291 setSchedulingPreference(Sched::VLIW);
1293 setSchedulingPreference(Sched::Source);
1295 // Limits for inline expansion of memcpy/memmove
1296 MaxStoresPerMemcpy = MaxStoresPerMemcpyCL;
1297 MaxStoresPerMemcpyOptSize = MaxStoresPerMemcpyOptSizeCL;
1298 MaxStoresPerMemmove = MaxStoresPerMemmoveCL;
1299 MaxStoresPerMemmoveOptSize = MaxStoresPerMemmoveOptSizeCL;
1300 MaxStoresPerMemset = MaxStoresPerMemsetCL;
1301 MaxStoresPerMemsetOptSize = MaxStoresPerMemsetOptSizeCL;
1304 // Set up register classes.
1307 addRegisterClass(MVT::i1, &Hexagon::PredRegsRegClass);
1308 addRegisterClass(MVT::v2i1, &Hexagon::PredRegsRegClass); // bbbbaaaa
1309 addRegisterClass(MVT::v4i1, &Hexagon::PredRegsRegClass); // ddccbbaa
1310 addRegisterClass(MVT::v8i1, &Hexagon::PredRegsRegClass); // hgfedcba
1311 addRegisterClass(MVT::i32, &Hexagon::IntRegsRegClass);
1312 addRegisterClass(MVT::v4i8, &Hexagon::IntRegsRegClass);
1313 addRegisterClass(MVT::v2i16, &Hexagon::IntRegsRegClass);
1314 addRegisterClass(MVT::i64, &Hexagon::DoubleRegsRegClass);
1315 addRegisterClass(MVT::v8i8, &Hexagon::DoubleRegsRegClass);
1316 addRegisterClass(MVT::v4i16, &Hexagon::DoubleRegsRegClass);
1317 addRegisterClass(MVT::v2i32, &Hexagon::DoubleRegsRegClass);
1319 if (Subtarget.hasV5TOps()) {
1320 addRegisterClass(MVT::f32, &Hexagon::IntRegsRegClass);
1321 addRegisterClass(MVT::f64, &Hexagon::DoubleRegsRegClass);
1325 // Handling of scalar operations.
1327 // All operations default to "legal", except:
1328 // - indexed loads and stores (pre-/post-incremented),
1329 // - ANY_EXTEND_VECTOR_INREG, ATOMIC_CMP_SWAP_WITH_SUCCESS, CONCAT_VECTORS,
1330 // ConstantFP, DEBUGTRAP, FCEIL, FCOPYSIGN, FEXP, FEXP2, FFLOOR, FGETSIGN,
1331 // FLOG, FLOG2, FLOG10, FMAXNUM, FMINNUM, FNEARBYINT, FRINT, FROUND, TRAP,
1332 // FTRUNC, PREFETCH, SIGN_EXTEND_VECTOR_INREG, ZERO_EXTEND_VECTOR_INREG,
1333 // which default to "expand" for at least one type.
1336 setOperationAction(ISD::ConstantFP, MVT::f32, Legal); // Default: expand
1337 setOperationAction(ISD::ConstantFP, MVT::f64, Legal); // Default: expand
1339 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
1340 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
1341 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
1342 setOperationAction(ISD::INLINEASM, MVT::Other, Custom);
1343 setOperationAction(ISD::EH_RETURN, MVT::Other, Custom);
1344 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
1346 // Custom legalize GlobalAddress nodes into CONST32.
1347 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
1348 setOperationAction(ISD::GlobalAddress, MVT::i8, Custom);
1349 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
1351 // Hexagon needs to optimize cases with negative constants.
1352 setOperationAction(ISD::SETCC, MVT::i8, Custom);
1353 setOperationAction(ISD::SETCC, MVT::i16, Custom);
1355 // VASTART needs to be custom lowered to use the VarArgsFrameIndex.
1356 setOperationAction(ISD::VASTART, MVT::Other, Custom);
1357 setOperationAction(ISD::VAEND, MVT::Other, Expand);
1358 setOperationAction(ISD::VAARG, MVT::Other, Expand);
1360 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
1361 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
1362 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
1365 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
1367 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
1368 // Increase jump tables cutover to 5, was 4.
1369 setMinimumJumpTableEntries(MinimumJumpTables);
1371 // Hexagon has instructions for add/sub with carry. The problem with
1372 // modeling these instructions is that they produce 2 results: Rdd and Px.
1373 // To model the update of Px, we will have to use Defs[p0..p3] which will
1374 // cause any predicate live range to spill. So, we pretend we dont't have
1375 // these instructions.
1376 setOperationAction(ISD::ADDE, MVT::i8, Expand);
1377 setOperationAction(ISD::ADDE, MVT::i16, Expand);
1378 setOperationAction(ISD::ADDE, MVT::i32, Expand);
1379 setOperationAction(ISD::ADDE, MVT::i64, Expand);
1380 setOperationAction(ISD::SUBE, MVT::i8, Expand);
1381 setOperationAction(ISD::SUBE, MVT::i16, Expand);
1382 setOperationAction(ISD::SUBE, MVT::i32, Expand);
1383 setOperationAction(ISD::SUBE, MVT::i64, Expand);
1384 setOperationAction(ISD::ADDC, MVT::i8, Expand);
1385 setOperationAction(ISD::ADDC, MVT::i16, Expand);
1386 setOperationAction(ISD::ADDC, MVT::i32, Expand);
1387 setOperationAction(ISD::ADDC, MVT::i64, Expand);
1388 setOperationAction(ISD::SUBC, MVT::i8, Expand);
1389 setOperationAction(ISD::SUBC, MVT::i16, Expand);
1390 setOperationAction(ISD::SUBC, MVT::i32, Expand);
1391 setOperationAction(ISD::SUBC, MVT::i64, Expand);
1393 // Only add and sub that detect overflow are the saturating ones.
1394 for (MVT VT : MVT::integer_valuetypes()) {
1395 setOperationAction(ISD::UADDO, VT, Expand);
1396 setOperationAction(ISD::SADDO, VT, Expand);
1397 setOperationAction(ISD::USUBO, VT, Expand);
1398 setOperationAction(ISD::SSUBO, VT, Expand);
1401 setOperationAction(ISD::CTLZ, MVT::i8, Promote);
1402 setOperationAction(ISD::CTLZ, MVT::i16, Promote);
1403 setOperationAction(ISD::CTTZ, MVT::i8, Promote);
1404 setOperationAction(ISD::CTTZ, MVT::i16, Promote);
1405 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8, Promote);
1406 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16, Promote);
1407 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i8, Promote);
1408 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16, Promote);
1410 // In V5, popcount can count # of 1s in i64 but returns i32.
1411 // On V4 it will be expanded (set later).
1412 setOperationAction(ISD::CTPOP, MVT::i8, Promote);
1413 setOperationAction(ISD::CTPOP, MVT::i16, Promote);
1414 setOperationAction(ISD::CTPOP, MVT::i32, Promote);
1415 setOperationAction(ISD::CTPOP, MVT::i64, Custom);
1417 // We custom lower i64 to i64 mul, so that it is not considered as a legal
1418 // operation. There is a pattern that will match i64 mul and transform it
1419 // to a series of instructions.
1420 setOperationAction(ISD::MUL, MVT::i64, Expand);
1421 setOperationAction(ISD::MULHS, MVT::i64, Expand);
1423 for (unsigned IntExpOp :
1424 {ISD::SDIV, ISD::UDIV, ISD::SREM, ISD::UREM, ISD::SDIVREM, ISD::UDIVREM,
1425 ISD::ROTL, ISD::ROTR, ISD::BSWAP, ISD::SHL_PARTS, ISD::SRA_PARTS,
1426 ISD::SRL_PARTS, ISD::SMUL_LOHI, ISD::UMUL_LOHI}) {
1427 setOperationAction(IntExpOp, MVT::i32, Expand);
1428 setOperationAction(IntExpOp, MVT::i64, Expand);
1431 for (unsigned FPExpOp :
1432 {ISD::FDIV, ISD::FREM, ISD::FSQRT, ISD::FSIN, ISD::FCOS, ISD::FSINCOS,
1433 ISD::FPOW, ISD::FCOPYSIGN}) {
1434 setOperationAction(FPExpOp, MVT::f32, Expand);
1435 setOperationAction(FPExpOp, MVT::f64, Expand);
1438 // No extending loads from i32.
1439 for (MVT VT : MVT::integer_valuetypes()) {
1440 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i32, Expand);
1441 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i32, Expand);
1442 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i32, Expand);
1444 // Turn FP truncstore into trunc + store.
1445 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
1446 // Turn FP extload into load/fextend.
1447 for (MVT VT : MVT::fp_valuetypes())
1448 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
1450 // Expand BR_CC and SELECT_CC for all integer and fp types.
1451 for (MVT VT : MVT::integer_valuetypes()) {
1452 setOperationAction(ISD::BR_CC, VT, Expand);
1453 setOperationAction(ISD::SELECT_CC, VT, Expand);
1455 for (MVT VT : MVT::fp_valuetypes()) {
1456 setOperationAction(ISD::BR_CC, VT, Expand);
1457 setOperationAction(ISD::SELECT_CC, VT, Expand);
1459 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
1462 // Handling of vector operations.
1465 // Custom lower v4i16 load only. Let v4i16 store to be
1466 // promoted for now.
1467 promoteLdStType(MVT::v4i8, MVT::i32);
1468 promoteLdStType(MVT::v2i16, MVT::i32);
1469 promoteLdStType(MVT::v8i8, MVT::i64);
1470 promoteLdStType(MVT::v2i32, MVT::i64);
1472 setOperationAction(ISD::LOAD, MVT::v4i16, Custom);
1473 setOperationAction(ISD::STORE, MVT::v4i16, Promote);
1474 AddPromotedToType(ISD::LOAD, MVT::v4i16, MVT::i64);
1475 AddPromotedToType(ISD::STORE, MVT::v4i16, MVT::i64);
1477 // Set the action for vector operations to "expand", then override it with
1478 // either "custom" or "legal" for specific cases.
1479 static unsigned VectExpOps[] = {
1480 // Integer arithmetic:
1481 ISD::ADD, ISD::SUB, ISD::MUL, ISD::SDIV, ISD::UDIV,
1482 ISD::SREM, ISD::UREM, ISD::SDIVREM, ISD::UDIVREM, ISD::ADDC,
1483 ISD::SUBC, ISD::SADDO, ISD::UADDO, ISD::SSUBO, ISD::USUBO,
1484 ISD::SMUL_LOHI, ISD::UMUL_LOHI,
1486 ISD::AND, ISD::OR, ISD::XOR, ISD::ROTL, ISD::ROTR,
1487 ISD::CTPOP, ISD::CTLZ, ISD::CTTZ, ISD::CTLZ_ZERO_UNDEF,
1488 ISD::CTTZ_ZERO_UNDEF,
1489 // Floating point arithmetic/math functions:
1490 ISD::FADD, ISD::FSUB, ISD::FMUL, ISD::FMA, ISD::FDIV,
1491 ISD::FREM, ISD::FNEG, ISD::FABS, ISD::FSQRT, ISD::FSIN,
1492 ISD::FCOS, ISD::FPOWI, ISD::FPOW, ISD::FLOG, ISD::FLOG2,
1493 ISD::FLOG10, ISD::FEXP, ISD::FEXP2, ISD::FCEIL, ISD::FTRUNC,
1494 ISD::FRINT, ISD::FNEARBYINT, ISD::FROUND, ISD::FFLOOR,
1495 ISD::FMINNUM, ISD::FMAXNUM, ISD::FSINCOS,
1497 ISD::SELECT, ISD::ConstantPool,
1499 ISD::BUILD_VECTOR, ISD::SCALAR_TO_VECTOR,
1500 ISD::EXTRACT_VECTOR_ELT, ISD::INSERT_VECTOR_ELT,
1501 ISD::EXTRACT_SUBVECTOR, ISD::INSERT_SUBVECTOR,
1502 ISD::CONCAT_VECTORS, ISD::VECTOR_SHUFFLE
1505 for (MVT VT : MVT::vector_valuetypes()) {
1506 for (unsigned VectExpOp : VectExpOps)
1507 setOperationAction(VectExpOp, VT, Expand);
1509 // Expand all extended loads and truncating stores:
1510 for (MVT TargetVT : MVT::vector_valuetypes()) {
1511 setLoadExtAction(ISD::EXTLOAD, TargetVT, VT, Expand);
1512 setTruncStoreAction(VT, TargetVT, Expand);
1515 setOperationAction(ISD::SRA, VT, Custom);
1516 setOperationAction(ISD::SHL, VT, Custom);
1517 setOperationAction(ISD::SRL, VT, Custom);
1520 // Types natively supported:
1521 for (MVT NativeVT : {MVT::v2i1, MVT::v4i1, MVT::v8i1, MVT::v32i1, MVT::v64i1,
1522 MVT::v4i8, MVT::v8i8, MVT::v2i16, MVT::v4i16, MVT::v1i32,
1523 MVT::v2i32, MVT::v1i64}) {
1524 setOperationAction(ISD::BUILD_VECTOR, NativeVT, Custom);
1525 setOperationAction(ISD::EXTRACT_VECTOR_ELT, NativeVT, Custom);
1526 setOperationAction(ISD::INSERT_VECTOR_ELT, NativeVT, Custom);
1527 setOperationAction(ISD::EXTRACT_SUBVECTOR, NativeVT, Custom);
1528 setOperationAction(ISD::INSERT_SUBVECTOR, NativeVT, Custom);
1529 setOperationAction(ISD::CONCAT_VECTORS, NativeVT, Custom);
1531 setOperationAction(ISD::ADD, NativeVT, Legal);
1532 setOperationAction(ISD::SUB, NativeVT, Legal);
1533 setOperationAction(ISD::MUL, NativeVT, Legal);
1534 setOperationAction(ISD::AND, NativeVT, Legal);
1535 setOperationAction(ISD::OR, NativeVT, Legal);
1536 setOperationAction(ISD::XOR, NativeVT, Legal);
1539 setOperationAction(ISD::SETCC, MVT::v2i16, Custom);
1540 setOperationAction(ISD::VSELECT, MVT::v2i16, Custom);
1541 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);
1542 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom);
1544 // Subtarget-specific operation actions.
1546 if (Subtarget.hasV5TOps()) {
1547 setOperationAction(ISD::FMA, MVT::f64, Expand);
1548 setOperationAction(ISD::FADD, MVT::f64, Expand);
1549 setOperationAction(ISD::FSUB, MVT::f64, Expand);
1550 setOperationAction(ISD::FMUL, MVT::f64, Expand);
1552 setOperationAction(ISD::FP_TO_UINT, MVT::i1, Promote);
1553 setOperationAction(ISD::FP_TO_UINT, MVT::i8, Promote);
1554 setOperationAction(ISD::FP_TO_UINT, MVT::i16, Promote);
1555 setOperationAction(ISD::FP_TO_SINT, MVT::i1, Promote);
1556 setOperationAction(ISD::FP_TO_SINT, MVT::i8, Promote);
1557 setOperationAction(ISD::FP_TO_SINT, MVT::i16, Promote);
1558 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Promote);
1559 setOperationAction(ISD::UINT_TO_FP, MVT::i8, Promote);
1560 setOperationAction(ISD::UINT_TO_FP, MVT::i16, Promote);
1561 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote);
1562 setOperationAction(ISD::SINT_TO_FP, MVT::i8, Promote);
1563 setOperationAction(ISD::SINT_TO_FP, MVT::i16, Promote);
1566 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
1567 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Expand);
1568 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
1569 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
1570 setOperationAction(ISD::FP_TO_SINT, MVT::f64, Expand);
1571 setOperationAction(ISD::FP_TO_SINT, MVT::f32, Expand);
1572 setOperationAction(ISD::FP_EXTEND, MVT::f32, Expand);
1573 setOperationAction(ISD::FP_ROUND, MVT::f64, Expand);
1574 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
1576 setOperationAction(ISD::CTPOP, MVT::i8, Expand);
1577 setOperationAction(ISD::CTPOP, MVT::i16, Expand);
1578 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
1579 setOperationAction(ISD::CTPOP, MVT::i64, Expand);
1581 // Expand these operations for both f32 and f64:
1582 for (unsigned FPExpOpV4 :
1583 {ISD::FADD, ISD::FSUB, ISD::FMUL, ISD::FABS, ISD::FNEG, ISD::FMA}) {
1584 setOperationAction(FPExpOpV4, MVT::f32, Expand);
1585 setOperationAction(FPExpOpV4, MVT::f64, Expand);
1588 for (ISD::CondCode FPExpCCV4 :
1589 {ISD::SETOEQ, ISD::SETOGT, ISD::SETOLT, ISD::SETOGE, ISD::SETOLE,
1590 ISD::SETUO, ISD::SETO}) {
1591 setCondCodeAction(FPExpCCV4, MVT::f32, Expand);
1592 setCondCodeAction(FPExpCCV4, MVT::f64, Expand);
1596 // Handling of indexed loads/stores: default is "expand".
1598 for (MVT LSXTy : {MVT::i8, MVT::i16, MVT::i32, MVT::i64}) {
1599 setIndexedLoadAction(ISD::POST_INC, LSXTy, Legal);
1600 setIndexedStoreAction(ISD::POST_INC, LSXTy, Legal);
1603 computeRegisterProperties(&HRI);
1606 // Library calls for unsupported operations
1608 bool FastMath = EnableFastMath;
1610 setLibcallName(RTLIB::SDIV_I32, "__hexagon_divsi3");
1611 setLibcallName(RTLIB::SDIV_I64, "__hexagon_divdi3");
1612 setLibcallName(RTLIB::UDIV_I32, "__hexagon_udivsi3");
1613 setLibcallName(RTLIB::UDIV_I64, "__hexagon_udivdi3");
1614 setLibcallName(RTLIB::SREM_I32, "__hexagon_modsi3");
1615 setLibcallName(RTLIB::SREM_I64, "__hexagon_moddi3");
1616 setLibcallName(RTLIB::UREM_I32, "__hexagon_umodsi3");
1617 setLibcallName(RTLIB::UREM_I64, "__hexagon_umoddi3");
1619 setLibcallName(RTLIB::SINTTOFP_I128_F64, "__hexagon_floattidf");
1620 setLibcallName(RTLIB::SINTTOFP_I128_F32, "__hexagon_floattisf");
1621 setLibcallName(RTLIB::FPTOUINT_F32_I128, "__hexagon_fixunssfti");
1622 setLibcallName(RTLIB::FPTOUINT_F64_I128, "__hexagon_fixunsdfti");
1623 setLibcallName(RTLIB::FPTOSINT_F32_I128, "__hexagon_fixsfti");
1624 setLibcallName(RTLIB::FPTOSINT_F64_I128, "__hexagon_fixdfti");
1627 // Handle single-precision floating point operations on V4.
1629 setLibcallName(RTLIB::ADD_F32, "__hexagon_fast_addsf3");
1630 setLibcallName(RTLIB::SUB_F32, "__hexagon_fast_subsf3");
1631 setLibcallName(RTLIB::MUL_F32, "__hexagon_fast_mulsf3");
1632 setLibcallName(RTLIB::OGT_F32, "__hexagon_fast_gtsf2");
1633 setLibcallName(RTLIB::OLT_F32, "__hexagon_fast_ltsf2");
1634 // Double-precision compares.
1635 setLibcallName(RTLIB::OGT_F64, "__hexagon_fast_gtdf2");
1636 setLibcallName(RTLIB::OLT_F64, "__hexagon_fast_ltdf2");
1638 setLibcallName(RTLIB::ADD_F32, "__hexagon_addsf3");
1639 setLibcallName(RTLIB::SUB_F32, "__hexagon_subsf3");
1640 setLibcallName(RTLIB::MUL_F32, "__hexagon_mulsf3");
1641 setLibcallName(RTLIB::OGT_F32, "__hexagon_gtsf2");
1642 setLibcallName(RTLIB::OLT_F32, "__hexagon_ltsf2");
1643 // Double-precision compares.
1644 setLibcallName(RTLIB::OGT_F64, "__hexagon_gtdf2");
1645 setLibcallName(RTLIB::OLT_F64, "__hexagon_ltdf2");
1649 // This is the only fast library function for sqrtd.
1651 setLibcallName(RTLIB::SQRT_F64, "__hexagon_fast2_sqrtdf2");
1653 // Prefix is: nothing for "slow-math",
1654 // "fast2_" for V4 fast-math and V5+ fast-math double-precision
1655 // (actually, keep fast-math and fast-math2 separate for now)
1657 setLibcallName(RTLIB::ADD_F64, "__hexagon_fast_adddf3");
1658 setLibcallName(RTLIB::SUB_F64, "__hexagon_fast_subdf3");
1659 setLibcallName(RTLIB::MUL_F64, "__hexagon_fast_muldf3");
1660 setLibcallName(RTLIB::DIV_F64, "__hexagon_fast_divdf3");
1661 // Calling __hexagon_fast2_divsf3 with fast-math on V5 (ok).
1662 setLibcallName(RTLIB::DIV_F32, "__hexagon_fast_divsf3");
1664 setLibcallName(RTLIB::ADD_F64, "__hexagon_adddf3");
1665 setLibcallName(RTLIB::SUB_F64, "__hexagon_subdf3");
1666 setLibcallName(RTLIB::MUL_F64, "__hexagon_muldf3");
1667 setLibcallName(RTLIB::DIV_F64, "__hexagon_divdf3");
1668 setLibcallName(RTLIB::DIV_F32, "__hexagon_divsf3");
1671 if (Subtarget.hasV5TOps()) {
1673 setLibcallName(RTLIB::SQRT_F32, "__hexagon_fast2_sqrtf");
1675 setLibcallName(RTLIB::SQRT_F32, "__hexagon_sqrtf");
1678 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__hexagon_floatsisf");
1679 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__hexagon_floatsidf");
1680 setLibcallName(RTLIB::SINTTOFP_I64_F32, "__hexagon_floatdisf");
1681 setLibcallName(RTLIB::SINTTOFP_I64_F64, "__hexagon_floatdidf");
1682 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__hexagon_floatunsisf");
1683 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__hexagon_floatunsidf");
1684 setLibcallName(RTLIB::UINTTOFP_I64_F32, "__hexagon_floatundisf");
1685 setLibcallName(RTLIB::UINTTOFP_I64_F64, "__hexagon_floatundidf");
1686 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__hexagon_fixunssfsi");
1687 setLibcallName(RTLIB::FPTOUINT_F32_I64, "__hexagon_fixunssfdi");
1688 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__hexagon_fixunsdfsi");
1689 setLibcallName(RTLIB::FPTOUINT_F64_I64, "__hexagon_fixunsdfdi");
1690 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__hexagon_fixsfsi");
1691 setLibcallName(RTLIB::FPTOSINT_F32_I64, "__hexagon_fixsfdi");
1692 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__hexagon_fixdfsi");
1693 setLibcallName(RTLIB::FPTOSINT_F64_I64, "__hexagon_fixdfdi");
1694 setLibcallName(RTLIB::FPEXT_F32_F64, "__hexagon_extendsfdf2");
1695 setLibcallName(RTLIB::FPROUND_F64_F32, "__hexagon_truncdfsf2");
1696 setLibcallName(RTLIB::OEQ_F32, "__hexagon_eqsf2");
1697 setLibcallName(RTLIB::OEQ_F64, "__hexagon_eqdf2");
1698 setLibcallName(RTLIB::OGE_F32, "__hexagon_gesf2");
1699 setLibcallName(RTLIB::OGE_F64, "__hexagon_gedf2");
1700 setLibcallName(RTLIB::OLE_F32, "__hexagon_lesf2");
1701 setLibcallName(RTLIB::OLE_F64, "__hexagon_ledf2");
1702 setLibcallName(RTLIB::UNE_F32, "__hexagon_nesf2");
1703 setLibcallName(RTLIB::UNE_F64, "__hexagon_nedf2");
1704 setLibcallName(RTLIB::UO_F32, "__hexagon_unordsf2");
1705 setLibcallName(RTLIB::UO_F64, "__hexagon_unorddf2");
1706 setLibcallName(RTLIB::O_F32, "__hexagon_unordsf2");
1707 setLibcallName(RTLIB::O_F64, "__hexagon_unorddf2");
1710 // These cause problems when the shift amount is non-constant.
1711 setLibcallName(RTLIB::SHL_I128, nullptr);
1712 setLibcallName(RTLIB::SRL_I128, nullptr);
1713 setLibcallName(RTLIB::SRA_I128, nullptr);
1717 const char* HexagonTargetLowering::getTargetNodeName(unsigned Opcode) const {
1718 switch ((HexagonISD::NodeType)Opcode) {
1719 case HexagonISD::ALLOCA: return "HexagonISD::ALLOCA";
1720 case HexagonISD::ARGEXTEND: return "HexagonISD::ARGEXTEND";
1721 case HexagonISD::AT_GOT: return "HexagonISD::AT_GOT";
1722 case HexagonISD::AT_PCREL: return "HexagonISD::AT_PCREL";
1723 case HexagonISD::BARRIER: return "HexagonISD::BARRIER";
1724 case HexagonISD::BR_JT: return "HexagonISD::BR_JT";
1725 case HexagonISD::CALLR: return "HexagonISD::CALLR";
1726 case HexagonISD::CALLv3nr: return "HexagonISD::CALLv3nr";
1727 case HexagonISD::CALLv3: return "HexagonISD::CALLv3";
1728 case HexagonISD::COMBINE: return "HexagonISD::COMBINE";
1729 case HexagonISD::CONST32_GP: return "HexagonISD::CONST32_GP";
1730 case HexagonISD::CONST32: return "HexagonISD::CONST32";
1731 case HexagonISD::CP: return "HexagonISD::CP";
1732 case HexagonISD::DCFETCH: return "HexagonISD::DCFETCH";
1733 case HexagonISD::EH_RETURN: return "HexagonISD::EH_RETURN";
1734 case HexagonISD::EXTRACTU: return "HexagonISD::EXTRACTU";
1735 case HexagonISD::EXTRACTURP: return "HexagonISD::EXTRACTURP";
1736 case HexagonISD::FCONST32: return "HexagonISD::FCONST32";
1737 case HexagonISD::INSERT: return "HexagonISD::INSERT";
1738 case HexagonISD::INSERTRP: return "HexagonISD::INSERTRP";
1739 case HexagonISD::JT: return "HexagonISD::JT";
1740 case HexagonISD::PACKHL: return "HexagonISD::PACKHL";
1741 case HexagonISD::PIC_ADD: return "HexagonISD::PIC_ADD";
1742 case HexagonISD::POPCOUNT: return "HexagonISD::POPCOUNT";
1743 case HexagonISD::RET_FLAG: return "HexagonISD::RET_FLAG";
1744 case HexagonISD::SHUFFEB: return "HexagonISD::SHUFFEB";
1745 case HexagonISD::SHUFFEH: return "HexagonISD::SHUFFEH";
1746 case HexagonISD::SHUFFOB: return "HexagonISD::SHUFFOB";
1747 case HexagonISD::SHUFFOH: return "HexagonISD::SHUFFOH";
1748 case HexagonISD::TC_RETURN: return "HexagonISD::TC_RETURN";
1749 case HexagonISD::VCMPBEQ: return "HexagonISD::VCMPBEQ";
1750 case HexagonISD::VCMPBGT: return "HexagonISD::VCMPBGT";
1751 case HexagonISD::VCMPBGTU: return "HexagonISD::VCMPBGTU";
1752 case HexagonISD::VCMPHEQ: return "HexagonISD::VCMPHEQ";
1753 case HexagonISD::VCMPHGT: return "HexagonISD::VCMPHGT";
1754 case HexagonISD::VCMPHGTU: return "HexagonISD::VCMPHGTU";
1755 case HexagonISD::VCMPWEQ: return "HexagonISD::VCMPWEQ";
1756 case HexagonISD::VCMPWGT: return "HexagonISD::VCMPWGT";
1757 case HexagonISD::VCMPWGTU: return "HexagonISD::VCMPWGTU";
1758 case HexagonISD::VSHLH: return "HexagonISD::VSHLH";
1759 case HexagonISD::VSHLW: return "HexagonISD::VSHLW";
1760 case HexagonISD::VSPLATB: return "HexagonISD::VSPLTB";
1761 case HexagonISD::VSPLATH: return "HexagonISD::VSPLATH";
1762 case HexagonISD::VSRAH: return "HexagonISD::VSRAH";
1763 case HexagonISD::VSRAW: return "HexagonISD::VSRAW";
1764 case HexagonISD::VSRLH: return "HexagonISD::VSRLH";
1765 case HexagonISD::VSRLW: return "HexagonISD::VSRLW";
1766 case HexagonISD::VSXTBH: return "HexagonISD::VSXTBH";
1767 case HexagonISD::VSXTBW: return "HexagonISD::VSXTBW";
1768 case HexagonISD::OP_END: break;
1773 bool HexagonTargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
1774 EVT MTy1 = EVT::getEVT(Ty1);
1775 EVT MTy2 = EVT::getEVT(Ty2);
1776 if (!MTy1.isSimple() || !MTy2.isSimple())
1778 return (MTy1.getSimpleVT() == MVT::i64) && (MTy2.getSimpleVT() == MVT::i32);
1781 bool HexagonTargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
1782 if (!VT1.isSimple() || !VT2.isSimple())
1784 return (VT1.getSimpleVT() == MVT::i64) && (VT2.getSimpleVT() == MVT::i32);
1787 // shouldExpandBuildVectorWithShuffles
1788 // Should we expand the build vector with shuffles?
1790 HexagonTargetLowering::shouldExpandBuildVectorWithShuffles(EVT VT,
1791 unsigned DefinedValues) const {
1793 // Hexagon vector shuffle operates on element sizes of bytes or halfwords
1794 EVT EltVT = VT.getVectorElementType();
1795 int EltBits = EltVT.getSizeInBits();
1796 if ((EltBits != 8) && (EltBits != 16))
1799 return TargetLowering::shouldExpandBuildVectorWithShuffles(VT, DefinedValues);
1802 // LowerVECTOR_SHUFFLE - Lower a vector shuffle (V1, V2, V3). V1 and
1803 // V2 are the two vectors to select data from, V3 is the permutation.
1804 static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
1805 const ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op);
1806 SDValue V1 = Op.getOperand(0);
1807 SDValue V2 = Op.getOperand(1);
1809 EVT VT = Op.getValueType();
1811 if (V2.getOpcode() == ISD::UNDEF)
1814 if (SVN->isSplat()) {
1815 int Lane = SVN->getSplatIndex();
1816 if (Lane == -1) Lane = 0;
1818 // Test if V1 is a SCALAR_TO_VECTOR.
1819 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR)
1820 return createSplat(DAG, dl, VT, V1.getOperand(0));
1822 // Test if V1 is a BUILD_VECTOR which is equivalent to a SCALAR_TO_VECTOR
1823 // (and probably will turn into a SCALAR_TO_VECTOR once legalization
1825 if (Lane == 0 && V1.getOpcode() == ISD::BUILD_VECTOR &&
1826 !isa<ConstantSDNode>(V1.getOperand(0))) {
1827 bool IsScalarToVector = true;
1828 for (unsigned i = 1, e = V1.getNumOperands(); i != e; ++i)
1829 if (V1.getOperand(i).getOpcode() != ISD::UNDEF) {
1830 IsScalarToVector = false;
1833 if (IsScalarToVector)
1834 return createSplat(DAG, dl, VT, V1.getOperand(0));
1836 return createSplat(DAG, dl, VT, DAG.getConstant(Lane, dl, MVT::i32));
1839 // FIXME: We need to support more general vector shuffles. See
1840 // below the comment from the ARM backend that deals in the general
1841 // case with the vector shuffles. For now, let expand handle these.
1844 // If the shuffle is not directly supported and it has 4 elements, use
1845 // the PerfectShuffle-generated table to synthesize it from other shuffles.
1848 // If BUILD_VECTOR has same base element repeated several times,
1850 static bool isCommonSplatElement(BuildVectorSDNode *BVN) {
1851 unsigned NElts = BVN->getNumOperands();
1852 SDValue V0 = BVN->getOperand(0);
1854 for (unsigned i = 1, e = NElts; i != e; ++i) {
1855 if (BVN->getOperand(i) != V0)
1861 // LowerVECTOR_SHIFT - Lower a vector shift. Try to convert
1862 // <VT> = SHL/SRA/SRL <VT> by <VT> to Hexagon specific
1863 // <VT> = SHL/SRA/SRL <VT> by <IT/i32>.
1864 static SDValue LowerVECTOR_SHIFT(SDValue Op, SelectionDAG &DAG) {
1865 BuildVectorSDNode *BVN = 0;
1866 SDValue V1 = Op.getOperand(0);
1867 SDValue V2 = Op.getOperand(1);
1870 EVT VT = Op.getValueType();
1872 if ((BVN = dyn_cast<BuildVectorSDNode>(V1.getNode())) &&
1873 isCommonSplatElement(BVN))
1875 else if ((BVN = dyn_cast<BuildVectorSDNode>(V2.getNode())) &&
1876 isCommonSplatElement(BVN))
1881 SDValue CommonSplat = BVN->getOperand(0);
1884 if (VT.getSimpleVT() == MVT::v4i16) {
1885 switch (Op.getOpcode()) {
1887 Result = DAG.getNode(HexagonISD::VSRAH, dl, VT, V3, CommonSplat);
1890 Result = DAG.getNode(HexagonISD::VSHLH, dl, VT, V3, CommonSplat);
1893 Result = DAG.getNode(HexagonISD::VSRLH, dl, VT, V3, CommonSplat);
1898 } else if (VT.getSimpleVT() == MVT::v2i32) {
1899 switch (Op.getOpcode()) {
1901 Result = DAG.getNode(HexagonISD::VSRAW, dl, VT, V3, CommonSplat);
1904 Result = DAG.getNode(HexagonISD::VSHLW, dl, VT, V3, CommonSplat);
1907 Result = DAG.getNode(HexagonISD::VSRLW, dl, VT, V3, CommonSplat);
1916 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
1920 HexagonTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
1921 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
1923 EVT VT = Op.getValueType();
1925 unsigned Size = VT.getSizeInBits();
1927 // A vector larger than 64 bits cannot be represented in Hexagon.
1928 // Expand will split the vector.
1932 APInt APSplatBits, APSplatUndef;
1933 unsigned SplatBitSize;
1935 unsigned NElts = BVN->getNumOperands();
1937 // Try to generate a SPLAT instruction.
1938 if ((VT.getSimpleVT() == MVT::v4i8 || VT.getSimpleVT() == MVT::v4i16) &&
1939 (BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
1940 HasAnyUndefs, 0, true) && SplatBitSize <= 16)) {
1941 unsigned SplatBits = APSplatBits.getZExtValue();
1942 int32_t SextVal = ((int32_t) (SplatBits << (32 - SplatBitSize)) >>
1943 (32 - SplatBitSize));
1944 return createSplat(DAG, dl, VT, DAG.getConstant(SextVal, dl, MVT::i32));
1947 // Try to generate COMBINE to build v2i32 vectors.
1948 if (VT.getSimpleVT() == MVT::v2i32) {
1949 SDValue V0 = BVN->getOperand(0);
1950 SDValue V1 = BVN->getOperand(1);
1952 if (V0.getOpcode() == ISD::UNDEF)
1953 V0 = DAG.getConstant(0, dl, MVT::i32);
1954 if (V1.getOpcode() == ISD::UNDEF)
1955 V1 = DAG.getConstant(0, dl, MVT::i32);
1957 ConstantSDNode *C0 = dyn_cast<ConstantSDNode>(V0);
1958 ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(V1);
1959 // If the element isn't a constant, it is in a register:
1960 // generate a COMBINE Register Register instruction.
1962 return DAG.getNode(HexagonISD::COMBINE, dl, VT, V1, V0);
1964 // If one of the operands is an 8 bit integer constant, generate
1965 // a COMBINE Immediate Immediate instruction.
1966 if (isInt<8>(C0->getSExtValue()) ||
1967 isInt<8>(C1->getSExtValue()))
1968 return DAG.getNode(HexagonISD::COMBINE, dl, VT, V1, V0);
1971 // Try to generate a S2_packhl to build v2i16 vectors.
1972 if (VT.getSimpleVT() == MVT::v2i16) {
1973 for (unsigned i = 0, e = NElts; i != e; ++i) {
1974 if (BVN->getOperand(i).getOpcode() == ISD::UNDEF)
1976 ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(BVN->getOperand(i));
1977 // If the element isn't a constant, it is in a register:
1978 // generate a S2_packhl instruction.
1980 SDValue pack = DAG.getNode(HexagonISD::PACKHL, dl, MVT::v4i16,
1981 BVN->getOperand(1), BVN->getOperand(0));
1983 return DAG.getTargetExtractSubreg(Hexagon::subreg_loreg, dl, MVT::v2i16,
1989 // In the general case, generate a CONST32 or a CONST64 for constant vectors,
1990 // and insert_vector_elt for all the other cases.
1992 unsigned EltSize = Size / NElts;
1994 uint64_t Mask = ~uint64_t(0ULL) >> (64 - EltSize);
1995 bool HasNonConstantElements = false;
1997 for (unsigned i = 0, e = NElts; i != e; ++i) {
1998 // LLVM's BUILD_VECTOR operands are in Little Endian mode, whereas Hexagon's
1999 // combine, const64, etc. are Big Endian.
2000 unsigned OpIdx = NElts - i - 1;
2001 SDValue Operand = BVN->getOperand(OpIdx);
2002 if (Operand.getOpcode() == ISD::UNDEF)
2006 if (ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Operand))
2007 Val = Cst->getSExtValue();
2009 HasNonConstantElements = true;
2012 Res = (Res << EltSize) | Val;
2016 ConstVal = DAG.getConstant(Res, dl, MVT::i64);
2018 ConstVal = DAG.getConstant(Res, dl, MVT::i32);
2020 // When there are non constant operands, add them with INSERT_VECTOR_ELT to
2021 // ConstVal, the constant part of the vector.
2022 if (HasNonConstantElements) {
2023 EVT EltVT = VT.getVectorElementType();
2024 SDValue Width = DAG.getConstant(EltVT.getSizeInBits(), dl, MVT::i64);
2025 SDValue Shifted = DAG.getNode(ISD::SHL, dl, MVT::i64, Width,
2026 DAG.getConstant(32, dl, MVT::i64));
2028 for (unsigned i = 0, e = NElts; i != e; ++i) {
2029 // LLVM's BUILD_VECTOR operands are in Little Endian mode, whereas Hexagon
2031 unsigned OpIdx = NElts - i - 1;
2032 SDValue Operand = BVN->getOperand(OpIdx);
2033 if (isa<ConstantSDNode>(Operand))
2034 // This operand is already in ConstVal.
2037 if (VT.getSizeInBits() == 64 &&
2038 Operand.getValueType().getSizeInBits() == 32) {
2039 SDValue C = DAG.getConstant(0, dl, MVT::i32);
2040 Operand = DAG.getNode(HexagonISD::COMBINE, dl, VT, C, Operand);
2043 SDValue Idx = DAG.getConstant(OpIdx, dl, MVT::i64);
2044 SDValue Offset = DAG.getNode(ISD::MUL, dl, MVT::i64, Idx, Width);
2045 SDValue Combined = DAG.getNode(ISD::OR, dl, MVT::i64, Shifted, Offset);
2046 const SDValue Ops[] = {ConstVal, Operand, Combined};
2048 if (VT.getSizeInBits() == 32)
2049 ConstVal = DAG.getNode(HexagonISD::INSERTRP, dl, MVT::i32, Ops);
2051 ConstVal = DAG.getNode(HexagonISD::INSERTRP, dl, MVT::i64, Ops);
2055 return DAG.getNode(ISD::BITCAST, dl, VT, ConstVal);
2059 HexagonTargetLowering::LowerCONCAT_VECTORS(SDValue Op,
2060 SelectionDAG &DAG) const {
2062 EVT VT = Op.getValueType();
2063 unsigned NElts = Op.getNumOperands();
2064 SDValue Vec = Op.getOperand(0);
2065 EVT VecVT = Vec.getValueType();
2066 SDValue Width = DAG.getConstant(VecVT.getSizeInBits(), dl, MVT::i64);
2067 SDValue Shifted = DAG.getNode(ISD::SHL, dl, MVT::i64, Width,
2068 DAG.getConstant(32, dl, MVT::i64));
2069 SDValue ConstVal = DAG.getConstant(0, dl, MVT::i64);
2071 ConstantSDNode *W = dyn_cast<ConstantSDNode>(Width);
2072 ConstantSDNode *S = dyn_cast<ConstantSDNode>(Shifted);
2074 if ((VecVT.getSimpleVT() == MVT::v2i16) && (NElts == 2) && W && S) {
2075 if ((W->getZExtValue() == 32) && ((S->getZExtValue() >> 32) == 32)) {
2076 // We are trying to concat two v2i16 to a single v4i16.
2077 SDValue Vec0 = Op.getOperand(1);
2078 SDValue Combined = DAG.getNode(HexagonISD::COMBINE, dl, VT, Vec0, Vec);
2079 return DAG.getNode(ISD::BITCAST, dl, VT, Combined);
2083 if ((VecVT.getSimpleVT() == MVT::v4i8) && (NElts == 2) && W && S) {
2084 if ((W->getZExtValue() == 32) && ((S->getZExtValue() >> 32) == 32)) {
2085 // We are trying to concat two v4i8 to a single v8i8.
2086 SDValue Vec0 = Op.getOperand(1);
2087 SDValue Combined = DAG.getNode(HexagonISD::COMBINE, dl, VT, Vec0, Vec);
2088 return DAG.getNode(ISD::BITCAST, dl, VT, Combined);
2092 for (unsigned i = 0, e = NElts; i != e; ++i) {
2093 unsigned OpIdx = NElts - i - 1;
2094 SDValue Operand = Op.getOperand(OpIdx);
2096 if (VT.getSizeInBits() == 64 &&
2097 Operand.getValueType().getSizeInBits() == 32) {
2098 SDValue C = DAG.getConstant(0, dl, MVT::i32);
2099 Operand = DAG.getNode(HexagonISD::COMBINE, dl, VT, C, Operand);
2102 SDValue Idx = DAG.getConstant(OpIdx, dl, MVT::i64);
2103 SDValue Offset = DAG.getNode(ISD::MUL, dl, MVT::i64, Idx, Width);
2104 SDValue Combined = DAG.getNode(ISD::OR, dl, MVT::i64, Shifted, Offset);
2105 const SDValue Ops[] = {ConstVal, Operand, Combined};
2107 if (VT.getSizeInBits() == 32)
2108 ConstVal = DAG.getNode(HexagonISD::INSERTRP, dl, MVT::i32, Ops);
2110 ConstVal = DAG.getNode(HexagonISD::INSERTRP, dl, MVT::i64, Ops);
2113 return DAG.getNode(ISD::BITCAST, dl, VT, ConstVal);
2117 HexagonTargetLowering::LowerEXTRACT_VECTOR(SDValue Op,
2118 SelectionDAG &DAG) const {
2119 EVT VT = Op.getValueType();
2120 int VTN = VT.isVector() ? VT.getVectorNumElements() : 1;
2122 SDValue Idx = Op.getOperand(1);
2123 SDValue Vec = Op.getOperand(0);
2124 EVT VecVT = Vec.getValueType();
2125 EVT EltVT = VecVT.getVectorElementType();
2126 int EltSize = EltVT.getSizeInBits();
2127 SDValue Width = DAG.getConstant(Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT ?
2128 EltSize : VTN * EltSize, dl, MVT::i64);
2130 // Constant element number.
2131 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Idx)) {
2132 uint64_t X = CI->getZExtValue();
2133 SDValue Offset = DAG.getConstant(X * EltSize, dl, MVT::i32);
2134 const SDValue Ops[] = {Vec, Width, Offset};
2136 ConstantSDNode *CW = dyn_cast<ConstantSDNode>(Width);
2137 assert(CW && "Non constant width in LowerEXTRACT_VECTOR");
2140 MVT SVT = VecVT.getSimpleVT();
2141 uint64_t W = CW->getZExtValue();
2144 // Translate this node into EXTRACT_SUBREG.
2145 unsigned Subreg = (X == 0) ? Hexagon::subreg_loreg : 0;
2148 Subreg = Hexagon::subreg_loreg;
2149 else if (SVT == MVT::v2i32 && X == 1)
2150 Subreg = Hexagon::subreg_hireg;
2151 else if (SVT == MVT::v4i16 && X == 2)
2152 Subreg = Hexagon::subreg_hireg;
2153 else if (SVT == MVT::v8i8 && X == 4)
2154 Subreg = Hexagon::subreg_hireg;
2156 llvm_unreachable("Bad offset");
2157 N = DAG.getTargetExtractSubreg(Subreg, dl, MVT::i32, Vec);
2159 } else if (VecVT.getSizeInBits() == 32) {
2160 N = DAG.getNode(HexagonISD::EXTRACTU, dl, MVT::i32, Ops);
2162 N = DAG.getNode(HexagonISD::EXTRACTU, dl, MVT::i64, Ops);
2163 if (VT.getSizeInBits() == 32)
2164 N = DAG.getTargetExtractSubreg(Hexagon::subreg_loreg, dl, MVT::i32, N);
2167 return DAG.getNode(ISD::BITCAST, dl, VT, N);
2170 // Variable element number.
2171 SDValue Offset = DAG.getNode(ISD::MUL, dl, MVT::i32, Idx,
2172 DAG.getConstant(EltSize, dl, MVT::i32));
2173 SDValue Shifted = DAG.getNode(ISD::SHL, dl, MVT::i64, Width,
2174 DAG.getConstant(32, dl, MVT::i64));
2175 SDValue Combined = DAG.getNode(ISD::OR, dl, MVT::i64, Shifted, Offset);
2177 const SDValue Ops[] = {Vec, Combined};
2180 if (VecVT.getSizeInBits() == 32) {
2181 N = DAG.getNode(HexagonISD::EXTRACTURP, dl, MVT::i32, Ops);
2183 N = DAG.getNode(HexagonISD::EXTRACTURP, dl, MVT::i64, Ops);
2184 if (VT.getSizeInBits() == 32)
2185 N = DAG.getTargetExtractSubreg(Hexagon::subreg_loreg, dl, MVT::i32, N);
2187 return DAG.getNode(ISD::BITCAST, dl, VT, N);
2191 HexagonTargetLowering::LowerINSERT_VECTOR(SDValue Op,
2192 SelectionDAG &DAG) const {
2193 EVT VT = Op.getValueType();
2194 int VTN = VT.isVector() ? VT.getVectorNumElements() : 1;
2196 SDValue Vec = Op.getOperand(0);
2197 SDValue Val = Op.getOperand(1);
2198 SDValue Idx = Op.getOperand(2);
2199 EVT VecVT = Vec.getValueType();
2200 EVT EltVT = VecVT.getVectorElementType();
2201 int EltSize = EltVT.getSizeInBits();
2202 SDValue Width = DAG.getConstant(Op.getOpcode() == ISD::INSERT_VECTOR_ELT ?
2203 EltSize : VTN * EltSize, dl, MVT::i64);
2205 if (ConstantSDNode *C = cast<ConstantSDNode>(Idx)) {
2206 SDValue Offset = DAG.getConstant(C->getSExtValue() * EltSize, dl, MVT::i32);
2207 const SDValue Ops[] = {Vec, Val, Width, Offset};
2210 if (VT.getSizeInBits() == 32)
2211 N = DAG.getNode(HexagonISD::INSERT, dl, MVT::i32, Ops);
2213 N = DAG.getNode(HexagonISD::INSERT, dl, MVT::i64, Ops);
2215 return DAG.getNode(ISD::BITCAST, dl, VT, N);
2218 // Variable element number.
2219 SDValue Offset = DAG.getNode(ISD::MUL, dl, MVT::i32, Idx,
2220 DAG.getConstant(EltSize, dl, MVT::i32));
2221 SDValue Shifted = DAG.getNode(ISD::SHL, dl, MVT::i64, Width,
2222 DAG.getConstant(32, dl, MVT::i64));
2223 SDValue Combined = DAG.getNode(ISD::OR, dl, MVT::i64, Shifted, Offset);
2225 if (VT.getSizeInBits() == 64 &&
2226 Val.getValueType().getSizeInBits() == 32) {
2227 SDValue C = DAG.getConstant(0, dl, MVT::i32);
2228 Val = DAG.getNode(HexagonISD::COMBINE, dl, VT, C, Val);
2231 const SDValue Ops[] = {Vec, Val, Combined};
2234 if (VT.getSizeInBits() == 32)
2235 N = DAG.getNode(HexagonISD::INSERTRP, dl, MVT::i32, Ops);
2237 N = DAG.getNode(HexagonISD::INSERTRP, dl, MVT::i64, Ops);
2239 return DAG.getNode(ISD::BITCAST, dl, VT, N);
2243 HexagonTargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
2244 // Assuming the caller does not have either a signext or zeroext modifier, and
2245 // only one value is accepted, any reasonable truncation is allowed.
2246 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
2249 // FIXME: in principle up to 64-bit could be made safe, but it would be very
2250 // fragile at the moment: any support for multiple value returns would be
2251 // liable to disallow tail calls involving i64 -> iN truncation in many cases.
2252 return Ty1->getPrimitiveSizeInBits() <= 32;
2256 HexagonTargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
2257 SDValue Chain = Op.getOperand(0);
2258 SDValue Offset = Op.getOperand(1);
2259 SDValue Handler = Op.getOperand(2);
2261 auto PtrVT = getPointerTy(DAG.getDataLayout());
2263 // Mark function as containing a call to EH_RETURN.
2264 HexagonMachineFunctionInfo *FuncInfo =
2265 DAG.getMachineFunction().getInfo<HexagonMachineFunctionInfo>();
2266 FuncInfo->setHasEHReturn();
2268 unsigned OffsetReg = Hexagon::R28;
2271 DAG.getNode(ISD::ADD, dl, PtrVT, DAG.getRegister(Hexagon::R30, PtrVT),
2272 DAG.getIntPtrConstant(4, dl));
2273 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
2275 Chain = DAG.getCopyToReg(Chain, dl, OffsetReg, Offset);
2277 // Not needed we already use it as explict input to EH_RETURN.
2278 // MF.getRegInfo().addLiveOut(OffsetReg);
2280 return DAG.getNode(HexagonISD::EH_RETURN, dl, MVT::Other, Chain);
2284 HexagonTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
2285 unsigned Opc = Op.getOpcode();
2289 Op.getNode()->dumpr(&DAG);
2290 if (Opc > HexagonISD::OP_BEGIN && Opc < HexagonISD::OP_END)
2291 errs() << "Check for a non-legal type in this operation\n";
2293 llvm_unreachable("Should not custom lower this!");
2294 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
2295 case ISD::INSERT_SUBVECTOR: return LowerINSERT_VECTOR(Op, DAG);
2296 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR(Op, DAG);
2297 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_VECTOR(Op, DAG);
2298 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR(Op, DAG);
2299 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
2300 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
2303 case ISD::SRL: return LowerVECTOR_SHIFT(Op, DAG);
2304 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
2305 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
2306 // Frame & Return address. Currently unimplemented.
2307 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
2308 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
2309 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG);
2310 case ISD::GlobalAddress: return LowerGLOBALADDRESS(Op, DAG);
2311 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
2312 case ISD::VASTART: return LowerVASTART(Op, DAG);
2313 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
2314 // Custom lower some vector loads.
2315 case ISD::LOAD: return LowerLOAD(Op, DAG);
2316 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
2317 case ISD::SETCC: return LowerSETCC(Op, DAG);
2318 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
2319 case ISD::CTPOP: return LowerCTPOP(Op, DAG);
2320 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
2321 case ISD::INLINEASM: return LowerINLINEASM(Op, DAG);
2326 HexagonTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
2327 MachineBasicBlock *BB)
2329 switch (MI->getOpcode()) {
2330 case Hexagon::ALLOCA: {
2331 MachineFunction *MF = BB->getParent();
2332 auto *FuncInfo = MF->getInfo<HexagonMachineFunctionInfo>();
2333 FuncInfo->addAllocaAdjustInst(MI);
2336 default: llvm_unreachable("Unexpected instr type to insert");
2340 //===----------------------------------------------------------------------===//
2341 // Inline Assembly Support
2342 //===----------------------------------------------------------------------===//
2344 std::pair<unsigned, const TargetRegisterClass *>
2345 HexagonTargetLowering::getRegForInlineAsmConstraint(
2346 const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {
2347 if (Constraint.size() == 1) {
2348 switch (Constraint[0]) {
2350 switch (VT.SimpleTy) {
2352 llvm_unreachable("getRegForInlineAsmConstraint Unhandled data type");
2357 return std::make_pair(0U, &Hexagon::IntRegsRegClass);
2360 return std::make_pair(0U, &Hexagon::DoubleRegsRegClass);
2363 llvm_unreachable("Unknown asm register class");
2367 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
2370 /// isFPImmLegal - Returns true if the target can instruction select the
2371 /// specified FP immediate natively. If false, the legalizer will
2372 /// materialize the FP immediate as a load from a constant pool.
2373 bool HexagonTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
2374 return Subtarget.hasV5TOps();
2377 /// isLegalAddressingMode - Return true if the addressing mode represented by
2378 /// AM is legal for this target, for a load/store of the specified type.
2379 bool HexagonTargetLowering::isLegalAddressingMode(const DataLayout &DL,
2380 const AddrMode &AM, Type *Ty,
2381 unsigned AS) const {
2382 // Allows a signed-extended 11-bit immediate field.
2383 if (AM.BaseOffs <= -(1LL << 13) || AM.BaseOffs >= (1LL << 13)-1)
2386 // No global is ever allowed as a base.
2390 int Scale = AM.Scale;
2391 if (Scale < 0) Scale = -Scale;
2393 case 0: // No scale reg, "r+i", "r", or just "i".
2395 default: // No scaled addressing mode.
2401 /// isLegalICmpImmediate - Return true if the specified immediate is legal
2402 /// icmp immediate, that is the target has icmp instructions which can compare
2403 /// a register against the immediate without having to materialize the
2404 /// immediate into a register.
2405 bool HexagonTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
2406 return Imm >= -512 && Imm <= 511;
2409 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2410 /// for tail call optimization. Targets which want to do tail call
2411 /// optimization should implement this function.
2412 bool HexagonTargetLowering::IsEligibleForTailCallOptimization(
2414 CallingConv::ID CalleeCC,
2416 bool isCalleeStructRet,
2417 bool isCallerStructRet,
2418 const SmallVectorImpl<ISD::OutputArg> &Outs,
2419 const SmallVectorImpl<SDValue> &OutVals,
2420 const SmallVectorImpl<ISD::InputArg> &Ins,
2421 SelectionDAG& DAG) const {
2422 const Function *CallerF = DAG.getMachineFunction().getFunction();
2423 CallingConv::ID CallerCC = CallerF->getCallingConv();
2424 bool CCMatch = CallerCC == CalleeCC;
2426 // ***************************************************************************
2427 // Look for obvious safe cases to perform tail call optimization that do not
2428 // require ABI changes.
2429 // ***************************************************************************
2431 // If this is a tail call via a function pointer, then don't do it!
2432 if (!(dyn_cast<GlobalAddressSDNode>(Callee))
2433 && !(dyn_cast<ExternalSymbolSDNode>(Callee))) {
2437 // Do not optimize if the calling conventions do not match.
2441 // Do not tail call optimize vararg calls.
2445 // Also avoid tail call optimization if either caller or callee uses struct
2446 // return semantics.
2447 if (isCalleeStructRet || isCallerStructRet)
2450 // In addition to the cases above, we also disable Tail Call Optimization if
2451 // the calling convention code that at least one outgoing argument needs to
2452 // go on the stack. We cannot check that here because at this point that
2453 // information is not available.
2457 // Return true when the given node fits in a positive half word.
2458 bool llvm::isPositiveHalfWord(SDNode *N) {
2459 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N);
2460 if (CN && CN->getSExtValue() > 0 && isInt<16>(CN->getSExtValue()))
2463 switch (N->getOpcode()) {
2466 case ISD::SIGN_EXTEND_INREG:
2471 Value *HexagonTargetLowering::emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
2472 AtomicOrdering Ord) const {
2473 BasicBlock *BB = Builder.GetInsertBlock();
2474 Module *M = BB->getParent()->getParent();
2475 Type *Ty = cast<PointerType>(Addr->getType())->getElementType();
2476 unsigned SZ = Ty->getPrimitiveSizeInBits();
2477 assert((SZ == 32 || SZ == 64) && "Only 32/64-bit atomic loads supported");
2478 Intrinsic::ID IntID = (SZ == 32) ? Intrinsic::hexagon_L2_loadw_locked
2479 : Intrinsic::hexagon_L4_loadd_locked;
2480 Value *Fn = Intrinsic::getDeclaration(M, IntID);
2481 return Builder.CreateCall(Fn, Addr, "larx");
2484 /// Perform a store-conditional operation to Addr. Return the status of the
2485 /// store. This should be 0 if the store succeeded, non-zero otherwise.
2486 Value *HexagonTargetLowering::emitStoreConditional(IRBuilder<> &Builder,
2487 Value *Val, Value *Addr, AtomicOrdering Ord) const {
2488 BasicBlock *BB = Builder.GetInsertBlock();
2489 Module *M = BB->getParent()->getParent();
2490 Type *Ty = Val->getType();
2491 unsigned SZ = Ty->getPrimitiveSizeInBits();
2492 assert((SZ == 32 || SZ == 64) && "Only 32/64-bit atomic stores supported");
2493 Intrinsic::ID IntID = (SZ == 32) ? Intrinsic::hexagon_S2_storew_locked
2494 : Intrinsic::hexagon_S4_stored_locked;
2495 Value *Fn = Intrinsic::getDeclaration(M, IntID);
2496 Value *Call = Builder.CreateCall(Fn, {Addr, Val}, "stcx");
2497 Value *Cmp = Builder.CreateICmpEQ(Call, Builder.getInt32(0), "");
2498 Value *Ext = Builder.CreateZExt(Cmp, Type::getInt32Ty(M->getContext()));
2502 bool HexagonTargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
2503 // Do not expand loads and stores that don't exceed 64 bits.
2504 return LI->getType()->getPrimitiveSizeInBits() > 64;
2507 bool HexagonTargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
2508 // Do not expand loads and stores that don't exceed 64 bits.
2509 return SI->getValueOperand()->getType()->getPrimitiveSizeInBits() > 64;