1 //===-- HexagonISelLowering.cpp - Hexagon DAG Lowering Implementation -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the interfaces that Hexagon uses to lower LLVM code
11 // into a selection DAG.
13 //===----------------------------------------------------------------------===//
15 #include "HexagonISelLowering.h"
16 #include "HexagonMachineFunctionInfo.h"
17 #include "HexagonSubtarget.h"
18 #include "HexagonTargetMachine.h"
19 #include "HexagonTargetObjectFile.h"
20 #include "llvm/CodeGen/CallingConvLower.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineJumpTableInfo.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/SelectionDAGISel.h"
27 #include "llvm/CodeGen/ValueTypes.h"
28 #include "llvm/IR/CallingConv.h"
29 #include "llvm/IR/DerivedTypes.h"
30 #include "llvm/IR/Function.h"
31 #include "llvm/IR/GlobalAlias.h"
32 #include "llvm/IR/GlobalVariable.h"
33 #include "llvm/IR/InlineAsm.h"
34 #include "llvm/IR/Intrinsics.h"
35 #include "llvm/Support/CommandLine.h"
36 #include "llvm/Support/Debug.h"
37 #include "llvm/Support/ErrorHandling.h"
38 #include "llvm/Support/raw_ostream.h"
42 #define DEBUG_TYPE "hexagon-lowering"
45 EmitJumpTables("hexagon-emit-jump-tables", cl::init(true), cl::Hidden,
46 cl::desc("Control jump table emission on Hexagon target"));
49 class HexagonCCState : public CCState {
50 int NumNamedVarArgParams;
53 HexagonCCState(CallingConv::ID CC, bool isVarArg, MachineFunction &MF,
54 SmallVectorImpl<CCValAssign> &locs, LLVMContext &C,
55 int NumNamedVarArgParams)
56 : CCState(CC, isVarArg, MF, locs, C),
57 NumNamedVarArgParams(NumNamedVarArgParams) {}
59 int getNumNamedVarArgParams() const { return NumNamedVarArgParams; }
63 // Implement calling convention for Hexagon.
65 CC_Hexagon(unsigned ValNo, MVT ValVT,
66 MVT LocVT, CCValAssign::LocInfo LocInfo,
67 ISD::ArgFlagsTy ArgFlags, CCState &State);
70 CC_Hexagon32(unsigned ValNo, MVT ValVT,
71 MVT LocVT, CCValAssign::LocInfo LocInfo,
72 ISD::ArgFlagsTy ArgFlags, CCState &State);
75 CC_Hexagon64(unsigned ValNo, MVT ValVT,
76 MVT LocVT, CCValAssign::LocInfo LocInfo,
77 ISD::ArgFlagsTy ArgFlags, CCState &State);
80 RetCC_Hexagon(unsigned ValNo, MVT ValVT,
81 MVT LocVT, CCValAssign::LocInfo LocInfo,
82 ISD::ArgFlagsTy ArgFlags, CCState &State);
85 RetCC_Hexagon32(unsigned ValNo, MVT ValVT,
86 MVT LocVT, CCValAssign::LocInfo LocInfo,
87 ISD::ArgFlagsTy ArgFlags, CCState &State);
90 RetCC_Hexagon64(unsigned ValNo, MVT ValVT,
91 MVT LocVT, CCValAssign::LocInfo LocInfo,
92 ISD::ArgFlagsTy ArgFlags, CCState &State);
95 CC_Hexagon_VarArg (unsigned ValNo, MVT ValVT,
96 MVT LocVT, CCValAssign::LocInfo LocInfo,
97 ISD::ArgFlagsTy ArgFlags, CCState &State) {
98 HexagonCCState &HState = static_cast<HexagonCCState &>(State);
100 // NumNamedVarArgParams can not be zero for a VarArg function.
101 assert((HState.getNumNamedVarArgParams() > 0) &&
102 "NumNamedVarArgParams is not bigger than zero.");
104 if ((int)ValNo < HState.getNumNamedVarArgParams()) {
105 // Deal with named arguments.
106 return CC_Hexagon(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State);
109 // Deal with un-named arguments.
111 if (ArgFlags.isByVal()) {
112 // If pass-by-value, the size allocated on stack is decided
113 // by ArgFlags.getByValSize(), not by the size of LocVT.
114 assert ((ArgFlags.getByValSize() > 8) &&
115 "ByValSize must be bigger than 8 bytes");
116 ofst = State.AllocateStack(ArgFlags.getByValSize(), 4);
117 State.addLoc(CCValAssign::getMem(ValNo, ValVT, ofst, LocVT, LocInfo));
120 if (LocVT == MVT::i1 || LocVT == MVT::i8 || LocVT == MVT::i16) {
123 if (ArgFlags.isSExt())
124 LocInfo = CCValAssign::SExt;
125 else if (ArgFlags.isZExt())
126 LocInfo = CCValAssign::ZExt;
128 LocInfo = CCValAssign::AExt;
130 if (LocVT == MVT::i32 || LocVT == MVT::f32) {
131 ofst = State.AllocateStack(4, 4);
132 State.addLoc(CCValAssign::getMem(ValNo, ValVT, ofst, LocVT, LocInfo));
135 if (LocVT == MVT::i64 || LocVT == MVT::f64) {
136 ofst = State.AllocateStack(8, 8);
137 State.addLoc(CCValAssign::getMem(ValNo, ValVT, ofst, LocVT, LocInfo));
140 llvm_unreachable(nullptr);
145 CC_Hexagon (unsigned ValNo, MVT ValVT,
146 MVT LocVT, CCValAssign::LocInfo LocInfo,
147 ISD::ArgFlagsTy ArgFlags, CCState &State) {
149 if (ArgFlags.isByVal()) {
151 assert ((ArgFlags.getByValSize() > 8) &&
152 "ByValSize must be bigger than 8 bytes");
153 unsigned Offset = State.AllocateStack(ArgFlags.getByValSize(), 4);
154 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
158 if (LocVT == MVT::i1 || LocVT == MVT::i8 || LocVT == MVT::i16) {
161 if (ArgFlags.isSExt())
162 LocInfo = CCValAssign::SExt;
163 else if (ArgFlags.isZExt())
164 LocInfo = CCValAssign::ZExt;
166 LocInfo = CCValAssign::AExt;
167 } else if (LocVT == MVT::v4i8 || LocVT == MVT::v2i16) {
169 LocInfo = CCValAssign::BCvt;
170 } else if (LocVT == MVT::v8i8 || LocVT == MVT::v4i16 || LocVT == MVT::v2i32) {
172 LocInfo = CCValAssign::BCvt;
175 if (LocVT == MVT::i32 || LocVT == MVT::f32) {
176 if (!CC_Hexagon32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
180 if (LocVT == MVT::i64 || LocVT == MVT::f64) {
181 if (!CC_Hexagon64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
185 return true; // CC didn't match.
189 static bool CC_Hexagon32(unsigned ValNo, MVT ValVT,
190 MVT LocVT, CCValAssign::LocInfo LocInfo,
191 ISD::ArgFlagsTy ArgFlags, CCState &State) {
193 static const MCPhysReg RegList[] = {
194 Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4,
197 if (unsigned Reg = State.AllocateReg(RegList)) {
198 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
202 unsigned Offset = State.AllocateStack(4, 4);
203 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
207 static bool CC_Hexagon64(unsigned ValNo, MVT ValVT,
208 MVT LocVT, CCValAssign::LocInfo LocInfo,
209 ISD::ArgFlagsTy ArgFlags, CCState &State) {
211 if (unsigned Reg = State.AllocateReg(Hexagon::D0)) {
212 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
216 static const MCPhysReg RegList1[] = {
217 Hexagon::D1, Hexagon::D2
219 static const MCPhysReg RegList2[] = {
220 Hexagon::R1, Hexagon::R3
222 if (unsigned Reg = State.AllocateReg(RegList1, RegList2)) {
223 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
227 unsigned Offset = State.AllocateStack(8, 8, Hexagon::D2);
228 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
232 static bool RetCC_Hexagon(unsigned ValNo, MVT ValVT,
233 MVT LocVT, CCValAssign::LocInfo LocInfo,
234 ISD::ArgFlagsTy ArgFlags, CCState &State) {
237 if (LocVT == MVT::i1 ||
242 if (ArgFlags.isSExt())
243 LocInfo = CCValAssign::SExt;
244 else if (ArgFlags.isZExt())
245 LocInfo = CCValAssign::ZExt;
247 LocInfo = CCValAssign::AExt;
248 } else if (LocVT == MVT::v4i8 || LocVT == MVT::v2i16) {
250 LocInfo = CCValAssign::BCvt;
251 } else if (LocVT == MVT::v8i8 || LocVT == MVT::v4i16 || LocVT == MVT::v2i32) {
253 LocInfo = CCValAssign::BCvt;
256 if (LocVT == MVT::i32 || LocVT == MVT::f32) {
257 if (!RetCC_Hexagon32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
261 if (LocVT == MVT::i64 || LocVT == MVT::f64) {
262 if (!RetCC_Hexagon64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
266 return true; // CC didn't match.
269 static bool RetCC_Hexagon32(unsigned ValNo, MVT ValVT,
270 MVT LocVT, CCValAssign::LocInfo LocInfo,
271 ISD::ArgFlagsTy ArgFlags, CCState &State) {
273 if (LocVT == MVT::i32 || LocVT == MVT::f32) {
274 if (unsigned Reg = State.AllocateReg(Hexagon::R0)) {
275 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
280 unsigned Offset = State.AllocateStack(4, 4);
281 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
285 static bool RetCC_Hexagon64(unsigned ValNo, MVT ValVT,
286 MVT LocVT, CCValAssign::LocInfo LocInfo,
287 ISD::ArgFlagsTy ArgFlags, CCState &State) {
288 if (LocVT == MVT::i64 || LocVT == MVT::f64) {
289 if (unsigned Reg = State.AllocateReg(Hexagon::D0)) {
290 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
295 unsigned Offset = State.AllocateStack(8, 8);
296 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
301 HexagonTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG)
306 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
307 /// by "Src" to address "Dst" of size "Size". Alignment information is
308 /// specified by the specific parameter attribute. The copy will be passed as
309 /// a byval function parameter. Sometimes what we are copying is the end of a
310 /// larger object, the part that does not fit in registers.
312 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
313 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
316 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
317 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
318 /*isVolatile=*/false, /*AlwaysInline=*/false,
319 /*isTailCall=*/false,
320 MachinePointerInfo(), MachinePointerInfo());
324 // LowerReturn - Lower ISD::RET. If a struct is larger than 8 bytes and is
325 // passed by value, the function prototype is modified to return void and
326 // the value is stored in memory pointed by a pointer passed by caller.
328 HexagonTargetLowering::LowerReturn(SDValue Chain,
329 CallingConv::ID CallConv, bool isVarArg,
330 const SmallVectorImpl<ISD::OutputArg> &Outs,
331 const SmallVectorImpl<SDValue> &OutVals,
332 SDLoc dl, SelectionDAG &DAG) const {
334 // CCValAssign - represent the assignment of the return value to locations.
335 SmallVector<CCValAssign, 16> RVLocs;
337 // CCState - Info about the registers and stack slot.
338 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
341 // Analyze return values of ISD::RET
342 CCInfo.AnalyzeReturn(Outs, RetCC_Hexagon);
345 SmallVector<SDValue, 4> RetOps(1, Chain);
347 // Copy the result values into the output registers.
348 for (unsigned i = 0; i != RVLocs.size(); ++i) {
349 CCValAssign &VA = RVLocs[i];
351 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag);
353 // Guarantee that all emitted copies are stuck together with flags.
354 Flag = Chain.getValue(1);
355 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
358 RetOps[0] = Chain; // Update chain.
360 // Add the flag if we have it.
362 RetOps.push_back(Flag);
364 return DAG.getNode(HexagonISD::RET_FLAG, dl, MVT::Other, RetOps);
370 /// LowerCallResult - Lower the result values of an ISD::CALL into the
371 /// appropriate copies out of appropriate physical registers. This assumes that
372 /// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
373 /// being lowered. Returns a SDNode with the same number of values as the
376 HexagonTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
377 CallingConv::ID CallConv, bool isVarArg,
379 SmallVectorImpl<ISD::InputArg> &Ins,
380 SDLoc dl, SelectionDAG &DAG,
381 SmallVectorImpl<SDValue> &InVals,
382 const SmallVectorImpl<SDValue> &OutVals,
383 SDValue Callee) const {
385 // Assign locations to each value returned by this call.
386 SmallVector<CCValAssign, 16> RVLocs;
388 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
391 CCInfo.AnalyzeCallResult(Ins, RetCC_Hexagon);
393 // Copy all of the result registers out of their specified physreg.
394 for (unsigned i = 0; i != RVLocs.size(); ++i) {
395 Chain = DAG.getCopyFromReg(Chain, dl,
396 RVLocs[i].getLocReg(),
397 RVLocs[i].getValVT(), InFlag).getValue(1);
398 InFlag = Chain.getValue(2);
399 InVals.push_back(Chain.getValue(0));
405 /// LowerCall - Functions arguments are copied from virtual regs to
406 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
408 HexagonTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
409 SmallVectorImpl<SDValue> &InVals) const {
410 SelectionDAG &DAG = CLI.DAG;
412 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
413 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
414 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
415 SDValue Chain = CLI.Chain;
416 SDValue Callee = CLI.Callee;
417 bool &isTailCall = CLI.IsTailCall;
418 CallingConv::ID CallConv = CLI.CallConv;
419 bool isVarArg = CLI.IsVarArg;
420 bool doesNotReturn = CLI.DoesNotReturn;
422 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
424 // Check for varargs.
425 int NumNamedVarArgParams = -1;
426 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Callee))
428 const Function* CalleeFn = nullptr;
429 Callee = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, MVT::i32);
430 if ((CalleeFn = dyn_cast<Function>(GA->getGlobal())))
432 // If a function has zero args and is a vararg function, that's
433 // disallowed so it must be an undeclared function. Do not assume
434 // varargs if the callee is undefined.
435 if (CalleeFn->isVarArg() &&
436 CalleeFn->getFunctionType()->getNumParams() != 0) {
437 NumNamedVarArgParams = CalleeFn->getFunctionType()->getNumParams();
442 // Analyze operands of the call, assigning locations to each operand.
443 SmallVector<CCValAssign, 16> ArgLocs;
444 HexagonCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
445 *DAG.getContext(), NumNamedVarArgParams);
447 if (NumNamedVarArgParams > 0)
448 CCInfo.AnalyzeCallOperands(Outs, CC_Hexagon_VarArg);
450 CCInfo.AnalyzeCallOperands(Outs, CC_Hexagon);
454 bool StructAttrFlag =
455 DAG.getMachineFunction().getFunction()->hasStructRetAttr();
456 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
457 isVarArg, IsStructRet,
459 Outs, OutVals, Ins, DAG);
460 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i){
461 CCValAssign &VA = ArgLocs[i];
468 DEBUG(dbgs () << "Eligible for Tail Call\n");
471 "Argument must be passed on stack. Not eligible for Tail Call\n");
474 // Get a count of how many bytes are to be pushed on the stack.
475 unsigned NumBytes = CCInfo.getNextStackOffset();
476 SmallVector<std::pair<unsigned, SDValue>, 16> RegsToPass;
477 SmallVector<SDValue, 8> MemOpChains;
479 const HexagonRegisterInfo *QRI = Subtarget->getRegisterInfo();
481 DAG.getCopyFromReg(Chain, dl, QRI->getStackRegister(), getPointerTy());
483 // Walk the register/memloc assignments, inserting copies/loads.
484 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
485 CCValAssign &VA = ArgLocs[i];
486 SDValue Arg = OutVals[i];
487 ISD::ArgFlagsTy Flags = Outs[i].Flags;
489 // Promote the value if needed.
490 switch (VA.getLocInfo()) {
492 // Loc info must be one of Full, SExt, ZExt, or AExt.
493 llvm_unreachable("Unknown loc info!");
494 case CCValAssign::Full:
496 case CCValAssign::SExt:
497 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
499 case CCValAssign::ZExt:
500 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
502 case CCValAssign::AExt:
503 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
508 unsigned LocMemOffset = VA.getLocMemOffset();
509 SDValue PtrOff = DAG.getConstant(LocMemOffset, StackPtr.getValueType());
510 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
512 if (Flags.isByVal()) {
513 // The argument is a struct passed by value. According to LLVM, "Arg"
515 MemOpChains.push_back(CreateCopyOfByValArgument(Arg, PtrOff, Chain,
518 // The argument is not passed by value. "Arg" is a buildin type. It is
520 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
521 MachinePointerInfo(),false, false,
527 // Arguments that can be passed on register must be kept at RegsToPass
530 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
534 // Transform all store nodes into one single node because all store
535 // nodes are independent of each other.
536 if (!MemOpChains.empty()) {
537 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
541 Chain = DAG.getCALLSEQ_START(Chain, DAG.getConstant(NumBytes,
542 getPointerTy(), true),
545 // Build a sequence of copy-to-reg nodes chained together with token
546 // chain and flag operands which copy the outgoing args into registers.
547 // The InFlag in necessary since all emitted instructions must be
551 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
552 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
553 RegsToPass[i].second, InFlag);
554 InFlag = Chain.getValue(1);
558 // For tail calls lower the arguments to the 'real' stack slot.
560 // Force all the incoming stack arguments to be loaded from the stack
561 // before any new outgoing arguments are stored to the stack, because the
562 // outgoing stack slots may alias the incoming argument stack slots, and
563 // the alias isn't otherwise explicit. This is slightly more conservative
564 // than necessary, because it means that each store effectively depends
565 // on every argument instead of just those arguments it would clobber.
567 // Do not flag preceding copytoreg stuff together with the following stuff.
569 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
570 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
571 RegsToPass[i].second, InFlag);
572 InFlag = Chain.getValue(1);
577 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
578 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
579 // node so that legalize doesn't hack it.
580 if (flag_aligned_memcpy) {
581 const char *MemcpyName =
582 "__hexagon_memcpy_likely_aligned_min32bytes_mult8bytes";
584 DAG.getTargetExternalSymbol(MemcpyName, getPointerTy());
585 flag_aligned_memcpy = false;
586 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
587 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, getPointerTy());
588 } else if (ExternalSymbolSDNode *S =
589 dyn_cast<ExternalSymbolSDNode>(Callee)) {
590 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
593 // Returns a chain & a flag for retval copy to use.
594 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
595 SmallVector<SDValue, 8> Ops;
596 Ops.push_back(Chain);
597 Ops.push_back(Callee);
599 // Add argument registers to the end of the list so that they are
600 // known live into the call.
601 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
602 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
603 RegsToPass[i].second.getValueType()));
606 if (InFlag.getNode()) {
607 Ops.push_back(InFlag);
611 return DAG.getNode(HexagonISD::TC_RETURN, dl, NodeTys, Ops);
613 int OpCode = doesNotReturn ? HexagonISD::CALLv3nr : HexagonISD::CALLv3;
614 Chain = DAG.getNode(OpCode, dl, NodeTys, Ops);
615 InFlag = Chain.getValue(1);
617 // Create the CALLSEQ_END node.
618 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
619 DAG.getIntPtrConstant(0, true), InFlag, dl);
620 InFlag = Chain.getValue(1);
622 // Handle result values, copying them out of physregs into vregs that we
624 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl, DAG,
625 InVals, OutVals, Callee);
628 static bool getIndexedAddressParts(SDNode *Ptr, EVT VT,
629 bool isSEXTLoad, SDValue &Base,
630 SDValue &Offset, bool &isInc,
632 if (Ptr->getOpcode() != ISD::ADD)
635 if (VT == MVT::i64 || VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) {
636 isInc = (Ptr->getOpcode() == ISD::ADD);
637 Base = Ptr->getOperand(0);
638 Offset = Ptr->getOperand(1);
639 // Ensure that Offset is a constant.
640 return (isa<ConstantSDNode>(Offset));
646 // TODO: Put this function along with the other isS* functions in
647 // HexagonISelDAGToDAG.cpp into a common file. Or better still, use the
648 // functions defined in HexagonOperands.td.
649 static bool Is_PostInc_S4_Offset(SDNode * S, int ShiftAmount) {
650 ConstantSDNode *N = cast<ConstantSDNode>(S);
652 // immS4 predicate - True if the immediate fits in a 4-bit sign extended.
654 int64_t v = (int64_t)N->getSExtValue();
656 if (ShiftAmount > 0) {
658 v = v >> ShiftAmount;
660 return (v <= 7) && (v >= -8) && (m == 0);
663 /// getPostIndexedAddressParts - returns true by value, base pointer and
664 /// offset pointer and addressing mode by reference if this node can be
665 /// combined with a load / store to form a post-indexed load / store.
666 bool HexagonTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
669 ISD::MemIndexedMode &AM,
670 SelectionDAG &DAG) const
674 bool isSEXTLoad = false;
676 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
677 VT = LD->getMemoryVT();
678 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
679 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
680 VT = ST->getMemoryVT();
681 if (ST->getValue().getValueType() == MVT::i64 && ST->isTruncatingStore()) {
689 bool isLegal = getIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
691 // ShiftAmount = number of left-shifted bits in the Hexagon instruction.
692 int ShiftAmount = VT.getSizeInBits() / 16;
693 if (isLegal && Is_PostInc_S4_Offset(Offset.getNode(), ShiftAmount)) {
694 AM = isInc ? ISD::POST_INC : ISD::POST_DEC;
701 SDValue HexagonTargetLowering::LowerINLINEASM(SDValue Op,
702 SelectionDAG &DAG) const {
703 SDNode *Node = Op.getNode();
704 MachineFunction &MF = DAG.getMachineFunction();
705 HexagonMachineFunctionInfo *FuncInfo =
706 MF.getInfo<HexagonMachineFunctionInfo>();
707 switch (Node->getOpcode()) {
708 case ISD::INLINEASM: {
709 unsigned NumOps = Node->getNumOperands();
710 if (Node->getOperand(NumOps-1).getValueType() == MVT::Glue)
711 --NumOps; // Ignore the flag operand.
713 for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
714 if (FuncInfo->hasClobberLR())
717 cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue();
718 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
719 ++i; // Skip the ID value.
721 switch (InlineAsm::getKind(Flags)) {
722 default: llvm_unreachable("Bad flags!");
723 case InlineAsm::Kind_RegDef:
724 case InlineAsm::Kind_RegUse:
725 case InlineAsm::Kind_Imm:
726 case InlineAsm::Kind_Clobber:
727 case InlineAsm::Kind_Mem: {
728 for (; NumVals; --NumVals, ++i) {}
731 case InlineAsm::Kind_RegDefEarlyClobber: {
732 for (; NumVals; --NumVals, ++i) {
734 cast<RegisterSDNode>(Node->getOperand(i))->getReg();
737 const HexagonRegisterInfo *QRI = Subtarget->getRegisterInfo();
738 if (Reg == QRI->getRARegister()) {
739 FuncInfo->setHasClobberLR(true);
754 // Taken from the XCore backend.
756 SDValue HexagonTargetLowering::
757 LowerBR_JT(SDValue Op, SelectionDAG &DAG) const
759 SDValue Chain = Op.getOperand(0);
760 SDValue Table = Op.getOperand(1);
761 SDValue Index = Op.getOperand(2);
763 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
764 unsigned JTI = JT->getIndex();
765 MachineFunction &MF = DAG.getMachineFunction();
766 const MachineJumpTableInfo *MJTI = MF.getJumpTableInfo();
767 SDValue TargetJT = DAG.getTargetJumpTable(JT->getIndex(), MVT::i32);
769 // Mark all jump table targets as address taken.
770 const std::vector<MachineJumpTableEntry> &JTE = MJTI->getJumpTables();
771 const std::vector<MachineBasicBlock*> &JTBBs = JTE[JTI].MBBs;
772 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
773 MachineBasicBlock *MBB = JTBBs[i];
774 MBB->setHasAddressTaken();
775 // This line is needed to set the hasAddressTaken flag on the BasicBlock
777 BlockAddress::get(const_cast<BasicBlock *>(MBB->getBasicBlock()));
780 SDValue JumpTableBase = DAG.getNode(HexagonISD::JT, dl,
781 getPointerTy(), TargetJT);
782 SDValue ShiftIndex = DAG.getNode(ISD::SHL, dl, MVT::i32, Index,
783 DAG.getConstant(2, MVT::i32));
784 SDValue JTAddress = DAG.getNode(ISD::ADD, dl, MVT::i32, JumpTableBase,
786 SDValue LoadTarget = DAG.getLoad(MVT::i32, dl, Chain, JTAddress,
787 MachinePointerInfo(), false, false, false,
789 return DAG.getNode(HexagonISD::BR_JT, dl, MVT::Other, Chain, LoadTarget);
794 HexagonTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
795 SelectionDAG &DAG) const {
796 SDValue Chain = Op.getOperand(0);
797 SDValue Size = Op.getOperand(1);
800 unsigned SPReg = getStackPointerRegisterToSaveRestore();
802 // Get a reference to the stack pointer.
803 SDValue StackPointer = DAG.getCopyFromReg(Chain, dl, SPReg, MVT::i32);
805 // Subtract the dynamic size from the actual stack size to
806 // obtain the new stack size.
807 SDValue Sub = DAG.getNode(ISD::SUB, dl, MVT::i32, StackPointer, Size);
810 // For Hexagon, the outgoing memory arguments area should be on top of the
811 // alloca area on the stack i.e., the outgoing memory arguments should be
812 // at a lower address than the alloca area. Move the alloca area down the
813 // stack by adding back the space reserved for outgoing arguments to SP
816 // We do not know what the size of the outgoing args is at this point.
817 // So, we add a pseudo instruction ADJDYNALLOC that will adjust the
818 // stack pointer. We patch this instruction with the correct, known
819 // offset in emitPrologue().
821 // Use a placeholder immediate (zero) for now. This will be patched up
822 // by emitPrologue().
823 SDValue ArgAdjust = DAG.getNode(HexagonISD::ADJDYNALLOC, dl,
826 DAG.getConstant(0, MVT::i32));
828 // The Sub result contains the new stack start address, so it
829 // must be placed in the stack pointer register.
830 const HexagonRegisterInfo *QRI = Subtarget->getRegisterInfo();
831 SDValue CopyChain = DAG.getCopyToReg(Chain, dl, QRI->getStackRegister(), Sub);
833 SDValue Ops[2] = { ArgAdjust, CopyChain };
834 return DAG.getMergeValues(Ops, dl);
838 HexagonTargetLowering::LowerFormalArguments(SDValue Chain,
839 CallingConv::ID CallConv,
842 SmallVectorImpl<ISD::InputArg> &Ins,
843 SDLoc dl, SelectionDAG &DAG,
844 SmallVectorImpl<SDValue> &InVals)
847 MachineFunction &MF = DAG.getMachineFunction();
848 MachineFrameInfo *MFI = MF.getFrameInfo();
849 MachineRegisterInfo &RegInfo = MF.getRegInfo();
850 HexagonMachineFunctionInfo *FuncInfo =
851 MF.getInfo<HexagonMachineFunctionInfo>();
854 // Assign locations to all of the incoming arguments.
855 SmallVector<CCValAssign, 16> ArgLocs;
856 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
859 CCInfo.AnalyzeFormalArguments(Ins, CC_Hexagon);
861 // For LLVM, in the case when returning a struct by value (>8byte),
862 // the first argument is a pointer that points to the location on caller's
863 // stack where the return value will be stored. For Hexagon, the location on
864 // caller's stack is passed only when the struct size is smaller than (and
865 // equal to) 8 bytes. If not, no address will be passed into callee and
866 // callee return the result direclty through R0/R1.
868 SmallVector<SDValue, 4> MemOps;
870 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
871 CCValAssign &VA = ArgLocs[i];
872 ISD::ArgFlagsTy Flags = Ins[i].Flags;
874 unsigned StackLocation;
877 if ( (VA.isRegLoc() && !Flags.isByVal())
878 || (VA.isRegLoc() && Flags.isByVal() && Flags.getByValSize() > 8)) {
879 // Arguments passed in registers
880 // 1. int, long long, ptr args that get allocated in register.
881 // 2. Large struct that gets an register to put its address in.
882 EVT RegVT = VA.getLocVT();
883 if (RegVT == MVT::i8 || RegVT == MVT::i16 ||
884 RegVT == MVT::i32 || RegVT == MVT::f32) {
886 RegInfo.createVirtualRegister(&Hexagon::IntRegsRegClass);
887 RegInfo.addLiveIn(VA.getLocReg(), VReg);
888 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
889 } else if (RegVT == MVT::i64 || RegVT == MVT::f64) {
891 RegInfo.createVirtualRegister(&Hexagon::DoubleRegsRegClass);
892 RegInfo.addLiveIn(VA.getLocReg(), VReg);
893 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
897 } else if (VA.isRegLoc() && Flags.isByVal() && Flags.getByValSize() <= 8) {
898 assert (0 && "ByValSize must be bigger than 8 bytes");
901 assert(VA.isMemLoc());
903 if (Flags.isByVal()) {
904 // If it's a byval parameter, then we need to compute the
905 // "real" size, not the size of the pointer.
906 ObjSize = Flags.getByValSize();
908 ObjSize = VA.getLocVT().getStoreSizeInBits() >> 3;
911 StackLocation = HEXAGON_LRFP_SIZE + VA.getLocMemOffset();
912 // Create the frame index object for this incoming parameter...
913 FI = MFI->CreateFixedObject(ObjSize, StackLocation, true);
915 // Create the SelectionDAG nodes cordl, responding to a load
916 // from this parameter.
917 SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
919 if (Flags.isByVal()) {
920 // If it's a pass-by-value aggregate, then do not dereference the stack
921 // location. Instead, we should generate a reference to the stack
923 InVals.push_back(FIN);
925 InVals.push_back(DAG.getLoad(VA.getLocVT(), dl, Chain, FIN,
926 MachinePointerInfo(), false, false,
933 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
936 // This will point to the next argument passed via stack.
937 int FrameIndex = MFI->CreateFixedObject(Hexagon_PointerSize,
939 CCInfo.getNextStackOffset(),
941 FuncInfo->setVarArgsFrameIndex(FrameIndex);
948 HexagonTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
949 // VASTART stores the address of the VarArgsFrameIndex slot into the
950 // memory location argument.
951 MachineFunction &MF = DAG.getMachineFunction();
952 HexagonMachineFunctionInfo *QFI = MF.getInfo<HexagonMachineFunctionInfo>();
953 SDValue Addr = DAG.getFrameIndex(QFI->getVarArgsFrameIndex(), MVT::i32);
954 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
955 return DAG.getStore(Op.getOperand(0), SDLoc(Op), Addr,
956 Op.getOperand(1), MachinePointerInfo(SV), false,
960 // Creates a SPLAT instruction for a constant value VAL.
961 static SDValue createSplat(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue Val) {
962 if (VT.getSimpleVT() == MVT::v4i8)
963 return DAG.getNode(HexagonISD::VSPLATB, dl, VT, Val);
965 if (VT.getSimpleVT() == MVT::v4i16)
966 return DAG.getNode(HexagonISD::VSPLATH, dl, VT, Val);
971 static bool isSExtFree(SDValue N) {
972 // A sign-extend of a truncate of a sign-extend is free.
973 if (N.getOpcode() == ISD::TRUNCATE &&
974 N.getOperand(0).getOpcode() == ISD::AssertSext)
976 // We have sign-extended loads.
977 if (N.getOpcode() == ISD::LOAD)
982 SDValue HexagonTargetLowering::LowerCTPOP(SDValue Op, SelectionDAG &DAG) const {
984 SDValue InpVal = Op.getOperand(0);
985 if (isa<ConstantSDNode>(InpVal)) {
986 uint64_t V = cast<ConstantSDNode>(InpVal)->getZExtValue();
987 return DAG.getTargetConstant(countPopulation(V), MVT::i64);
989 SDValue PopOut = DAG.getNode(HexagonISD::POPCOUNT, dl, MVT::i32, InpVal);
990 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, PopOut);
993 SDValue HexagonTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
996 SDValue LHS = Op.getOperand(0);
997 SDValue RHS = Op.getOperand(1);
998 SDValue Cmp = Op.getOperand(2);
999 ISD::CondCode CC = cast<CondCodeSDNode>(Cmp)->get();
1001 EVT VT = Op.getValueType();
1002 EVT LHSVT = LHS.getValueType();
1003 EVT RHSVT = RHS.getValueType();
1005 if (LHSVT == MVT::v2i16) {
1006 assert(ISD::isSignedIntSetCC(CC) || ISD::isUnsignedIntSetCC(CC));
1007 unsigned ExtOpc = ISD::isSignedIntSetCC(CC) ? ISD::SIGN_EXTEND
1009 SDValue LX = DAG.getNode(ExtOpc, dl, MVT::v2i32, LHS);
1010 SDValue RX = DAG.getNode(ExtOpc, dl, MVT::v2i32, RHS);
1011 SDValue SC = DAG.getNode(ISD::SETCC, dl, MVT::v2i1, LX, RX, Cmp);
1015 // Treat all other vector types as legal.
1019 // Equals and not equals should use sign-extend, not zero-extend, since
1020 // we can represent small negative values in the compare instructions.
1021 // The LLVM default is to use zero-extend arbitrarily in these cases.
1022 if ((CC == ISD::SETEQ || CC == ISD::SETNE) &&
1023 (RHSVT == MVT::i8 || RHSVT == MVT::i16) &&
1024 (LHSVT == MVT::i8 || LHSVT == MVT::i16)) {
1025 ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS);
1026 if (C && C->getAPIntValue().isNegative()) {
1027 LHS = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i32, LHS);
1028 RHS = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i32, RHS);
1029 return DAG.getNode(ISD::SETCC, dl, Op.getValueType(),
1030 LHS, RHS, Op.getOperand(2));
1032 if (isSExtFree(LHS) || isSExtFree(RHS)) {
1033 LHS = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i32, LHS);
1034 RHS = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i32, RHS);
1035 return DAG.getNode(ISD::SETCC, dl, Op.getValueType(),
1036 LHS, RHS, Op.getOperand(2));
1042 SDValue HexagonTargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG)
1044 SDValue PredOp = Op.getOperand(0);
1045 SDValue Op1 = Op.getOperand(1), Op2 = Op.getOperand(2);
1046 EVT OpVT = Op1.getValueType();
1049 if (OpVT == MVT::v2i16) {
1050 SDValue X1 = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v2i32, Op1);
1051 SDValue X2 = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v2i32, Op2);
1052 SDValue SL = DAG.getNode(ISD::VSELECT, DL, MVT::v2i32, PredOp, X1, X2);
1053 SDValue TR = DAG.getNode(ISD::TRUNCATE, DL, MVT::v2i16, SL);
1060 // Handle only specific vector loads.
1061 SDValue HexagonTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
1062 EVT VT = Op.getValueType();
1064 LoadSDNode *LoadNode = cast<LoadSDNode>(Op);
1065 SDValue Chain = LoadNode->getChain();
1066 SDValue Ptr = Op.getOperand(1);
1067 SDValue LoweredLoad;
1069 SDValue Base = LoadNode->getBasePtr();
1070 ISD::LoadExtType Ext = LoadNode->getExtensionType();
1071 unsigned Alignment = LoadNode->getAlignment();
1074 if(Ext == ISD::NON_EXTLOAD)
1075 Ext = ISD::ZEXTLOAD;
1077 if (VT == MVT::v4i16) {
1078 if (Alignment == 2) {
1081 Loads[0] = DAG.getExtLoad(Ext, DL, MVT::i32, Chain, Base,
1082 LoadNode->getPointerInfo(), MVT::i16,
1083 LoadNode->isVolatile(),
1084 LoadNode->isNonTemporal(),
1085 LoadNode->isInvariant(),
1088 SDValue Increment = DAG.getConstant(2, MVT::i32);
1089 Ptr = DAG.getNode(ISD::ADD, DL, Base.getValueType(), Base, Increment);
1090 Loads[1] = DAG.getExtLoad(Ext, DL, MVT::i32, Chain, Ptr,
1091 LoadNode->getPointerInfo(), MVT::i16,
1092 LoadNode->isVolatile(),
1093 LoadNode->isNonTemporal(),
1094 LoadNode->isInvariant(),
1096 // SHL 16, then OR base and base+2.
1097 SDValue ShiftAmount = DAG.getConstant(16, MVT::i32);
1098 SDValue Tmp1 = DAG.getNode(ISD::SHL, DL, MVT::i32, Loads[1], ShiftAmount);
1099 SDValue Tmp2 = DAG.getNode(ISD::OR, DL, MVT::i32, Tmp1, Loads[0]);
1101 Increment = DAG.getConstant(4, MVT::i32);
1102 Ptr = DAG.getNode(ISD::ADD, DL, Base.getValueType(), Base, Increment);
1103 Loads[2] = DAG.getExtLoad(Ext, DL, MVT::i32, Chain, Ptr,
1104 LoadNode->getPointerInfo(), MVT::i16,
1105 LoadNode->isVolatile(),
1106 LoadNode->isNonTemporal(),
1107 LoadNode->isInvariant(),
1110 Increment = DAG.getConstant(6, MVT::i32);
1111 Ptr = DAG.getNode(ISD::ADD, DL, Base.getValueType(), Base, Increment);
1112 Loads[3] = DAG.getExtLoad(Ext, DL, MVT::i32, Chain, Ptr,
1113 LoadNode->getPointerInfo(), MVT::i16,
1114 LoadNode->isVolatile(),
1115 LoadNode->isNonTemporal(),
1116 LoadNode->isInvariant(),
1118 // SHL 16, then OR base+4 and base+6.
1119 Tmp1 = DAG.getNode(ISD::SHL, DL, MVT::i32, Loads[3], ShiftAmount);
1120 SDValue Tmp4 = DAG.getNode(ISD::OR, DL, MVT::i32, Tmp1, Loads[2]);
1121 // Combine to i64. This could be optimised out later if we can
1122 // affect reg allocation of this code.
1123 Result = DAG.getNode(HexagonISD::COMBINE, DL, MVT::i64, Tmp4, Tmp2);
1124 LoadChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
1125 Loads[0].getValue(1), Loads[1].getValue(1),
1126 Loads[2].getValue(1), Loads[3].getValue(1));
1128 // Perform default type expansion.
1129 Result = DAG.getLoad(MVT::i64, DL, Chain, Ptr, LoadNode->getPointerInfo(),
1130 LoadNode->isVolatile(), LoadNode->isNonTemporal(),
1131 LoadNode->isInvariant(), LoadNode->getAlignment());
1132 LoadChain = Result.getValue(1);
1135 llvm_unreachable("Custom lowering unsupported load");
1137 Result = DAG.getNode(ISD::BITCAST, DL, VT, Result);
1138 // Since we pretend to lower a load, we need the original chain
1139 // info attached to the result.
1140 SDValue Ops[] = { Result, LoadChain };
1142 return DAG.getMergeValues(Ops, DL);
1147 HexagonTargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
1148 EVT ValTy = Op.getValueType();
1150 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1152 if (CP->isMachineConstantPoolEntry())
1153 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), ValTy,
1154 CP->getAlignment());
1156 Res = DAG.getTargetConstantPool(CP->getConstVal(), ValTy,
1157 CP->getAlignment());
1158 return DAG.getNode(HexagonISD::CONST32, dl, ValTy, Res);
1162 HexagonTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const {
1163 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
1164 MachineFunction &MF = DAG.getMachineFunction();
1165 MachineFrameInfo *MFI = MF.getFrameInfo();
1166 MFI->setReturnAddressIsTaken(true);
1168 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
1171 EVT VT = Op.getValueType();
1173 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1175 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
1176 SDValue Offset = DAG.getConstant(4, MVT::i32);
1177 return DAG.getLoad(VT, dl, DAG.getEntryNode(),
1178 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
1179 MachinePointerInfo(), false, false, false, 0);
1182 // Return LR, which contains the return address. Mark it an implicit live-in.
1183 unsigned Reg = MF.addLiveIn(TRI->getRARegister(), getRegClassFor(MVT::i32));
1184 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
1188 HexagonTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
1189 const HexagonRegisterInfo *TRI = Subtarget->getRegisterInfo();
1190 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
1191 MFI->setFrameAddressIsTaken(true);
1193 EVT VT = Op.getValueType();
1195 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1196 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
1197 TRI->getFrameRegister(), VT);
1199 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
1200 MachinePointerInfo(),
1201 false, false, false, 0);
1205 SDValue HexagonTargetLowering::LowerATOMIC_FENCE(SDValue Op,
1206 SelectionDAG& DAG) const {
1208 return DAG.getNode(HexagonISD::BARRIER, dl, MVT::Other, Op.getOperand(0));
1212 SDValue HexagonTargetLowering::LowerGLOBALADDRESS(SDValue Op,
1213 SelectionDAG &DAG) const {
1215 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1216 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
1218 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
1220 const HexagonTargetObjectFile *TLOF =
1221 static_cast<const HexagonTargetObjectFile *>(
1222 getTargetMachine().getObjFileLowering());
1223 if (TLOF->IsGlobalInSmallSection(GV, getTargetMachine())) {
1224 return DAG.getNode(HexagonISD::CONST32_GP, dl, getPointerTy(), Result);
1227 return DAG.getNode(HexagonISD::CONST32, dl, getPointerTy(), Result);
1230 // Specifies that for loads and stores VT can be promoted to PromotedLdStVT.
1231 void HexagonTargetLowering::promoteLdStType(EVT VT, EVT PromotedLdStVT) {
1232 if (VT != PromotedLdStVT) {
1233 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
1234 AddPromotedToType(ISD::LOAD, VT.getSimpleVT(),
1235 PromotedLdStVT.getSimpleVT());
1237 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
1238 AddPromotedToType(ISD::STORE, VT.getSimpleVT(),
1239 PromotedLdStVT.getSimpleVT());
1244 HexagonTargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
1245 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1246 SDValue BA_SD = DAG.getTargetBlockAddress(BA, MVT::i32);
1248 return DAG.getNode(HexagonISD::CONST32_GP, dl, getPointerTy(), BA_SD);
1251 //===----------------------------------------------------------------------===//
1252 // TargetLowering Implementation
1253 //===----------------------------------------------------------------------===//
1255 HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM,
1256 const HexagonSubtarget &STI)
1257 : TargetLowering(TM), Subtarget(&STI) {
1259 // Set up the register classes.
1260 addRegisterClass(MVT::v2i1, &Hexagon::PredRegsRegClass); // bbbbaaaa
1261 addRegisterClass(MVT::v4i1, &Hexagon::PredRegsRegClass); // ddccbbaa
1262 addRegisterClass(MVT::v8i1, &Hexagon::PredRegsRegClass); // hgfedcba
1263 addRegisterClass(MVT::i32, &Hexagon::IntRegsRegClass);
1264 addRegisterClass(MVT::v4i8, &Hexagon::IntRegsRegClass);
1265 addRegisterClass(MVT::v2i16, &Hexagon::IntRegsRegClass);
1266 promoteLdStType(MVT::v4i8, MVT::i32);
1267 promoteLdStType(MVT::v2i16, MVT::i32);
1269 if (Subtarget->hasV5TOps()) {
1270 addRegisterClass(MVT::f32, &Hexagon::IntRegsRegClass);
1271 addRegisterClass(MVT::f64, &Hexagon::DoubleRegsRegClass);
1274 addRegisterClass(MVT::i64, &Hexagon::DoubleRegsRegClass);
1275 addRegisterClass(MVT::v8i8, &Hexagon::DoubleRegsRegClass);
1276 addRegisterClass(MVT::v4i16, &Hexagon::DoubleRegsRegClass);
1277 addRegisterClass(MVT::v2i32, &Hexagon::DoubleRegsRegClass);
1278 promoteLdStType(MVT::v8i8, MVT::i64);
1280 // Custom lower v4i16 load only. Let v4i16 store to be
1281 // promoted for now.
1282 setOperationAction(ISD::LOAD, MVT::v4i16, Custom);
1283 AddPromotedToType(ISD::LOAD, MVT::v4i16, MVT::i64);
1284 setOperationAction(ISD::STORE, MVT::v4i16, Promote);
1285 AddPromotedToType(ISD::STORE, MVT::v4i16, MVT::i64);
1286 promoteLdStType(MVT::v2i32, MVT::i64);
1288 for (unsigned i = (unsigned) MVT::FIRST_VECTOR_VALUETYPE;
1289 i <= (unsigned) MVT::LAST_VECTOR_VALUETYPE; ++i) {
1290 MVT::SimpleValueType VT = (MVT::SimpleValueType) i;
1292 // Hexagon does not have support for the following operations,
1293 // so they need to be expanded.
1294 setOperationAction(ISD::SELECT, VT, Expand);
1295 setOperationAction(ISD::SDIV, VT, Expand);
1296 setOperationAction(ISD::SREM, VT, Expand);
1297 setOperationAction(ISD::UDIV, VT, Expand);
1298 setOperationAction(ISD::UREM, VT, Expand);
1299 setOperationAction(ISD::ROTL, VT, Expand);
1300 setOperationAction(ISD::ROTR, VT, Expand);
1301 setOperationAction(ISD::FDIV, VT, Expand);
1302 setOperationAction(ISD::FNEG, VT, Expand);
1303 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
1304 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
1305 setOperationAction(ISD::UDIVREM, VT, Expand);
1306 setOperationAction(ISD::SDIVREM, VT, Expand);
1307 setOperationAction(ISD::FPOW, VT, Expand);
1308 setOperationAction(ISD::CTPOP, VT, Expand);
1309 setOperationAction(ISD::CTLZ, VT, Expand);
1310 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
1311 setOperationAction(ISD::CTTZ, VT, Expand);
1312 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
1314 // Expand all any extend loads.
1315 for (unsigned j = (unsigned) MVT::FIRST_VECTOR_VALUETYPE;
1316 j <= (unsigned) MVT::LAST_VECTOR_VALUETYPE; ++j)
1317 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType) j, VT, Expand);
1319 // Expand all trunc stores.
1320 for (unsigned TargetVT = (unsigned) MVT::FIRST_VECTOR_VALUETYPE;
1321 TargetVT <= (unsigned) MVT::LAST_VECTOR_VALUETYPE; ++TargetVT)
1322 setTruncStoreAction(VT, (MVT::SimpleValueType) TargetVT, Expand);
1324 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
1325 setOperationAction(ISD::ConstantPool, VT, Expand);
1326 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
1327 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);
1328 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
1329 setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
1330 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Expand);
1331 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Expand);
1332 setOperationAction(ISD::CONCAT_VECTORS, VT, Expand);
1333 setOperationAction(ISD::SRA, VT, Custom);
1334 setOperationAction(ISD::SHL, VT, Custom);
1335 setOperationAction(ISD::SRL, VT, Custom);
1337 if (!isTypeLegal(VT))
1340 setOperationAction(ISD::ADD, VT, Legal);
1341 setOperationAction(ISD::SUB, VT, Legal);
1342 setOperationAction(ISD::MUL, VT, Legal);
1344 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1345 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1346 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1347 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1348 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1349 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1352 setOperationAction(ISD::SETCC, MVT::v2i16, Custom);
1353 setOperationAction(ISD::VSELECT, MVT::v2i16, Custom);
1354 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom);
1355 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);
1357 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
1359 addRegisterClass(MVT::i1, &Hexagon::PredRegsRegClass);
1361 computeRegisterProperties(Subtarget->getRegisterInfo());
1364 setPrefLoopAlignment(4);
1366 // Limits for inline expansion of memcpy/memmove
1367 MaxStoresPerMemcpy = 6;
1368 MaxStoresPerMemmove = 6;
1371 // Library calls for unsupported operations
1374 setLibcallName(RTLIB::SINTTOFP_I128_F64, "__hexagon_floattidf");
1375 setLibcallName(RTLIB::SINTTOFP_I128_F32, "__hexagon_floattisf");
1377 setLibcallName(RTLIB::FPTOUINT_F32_I128, "__hexagon_fixunssfti");
1378 setLibcallName(RTLIB::FPTOUINT_F64_I128, "__hexagon_fixunsdfti");
1380 setLibcallName(RTLIB::FPTOSINT_F32_I128, "__hexagon_fixsfti");
1381 setLibcallName(RTLIB::FPTOSINT_F64_I128, "__hexagon_fixdfti");
1383 setLibcallName(RTLIB::SDIV_I32, "__hexagon_divsi3");
1384 setOperationAction(ISD::SDIV, MVT::i32, Expand);
1385 setLibcallName(RTLIB::SREM_I32, "__hexagon_umodsi3");
1386 setOperationAction(ISD::SREM, MVT::i32, Expand);
1388 setLibcallName(RTLIB::SDIV_I64, "__hexagon_divdi3");
1389 setOperationAction(ISD::SDIV, MVT::i64, Expand);
1390 setLibcallName(RTLIB::SREM_I64, "__hexagon_moddi3");
1391 setOperationAction(ISD::SREM, MVT::i64, Expand);
1393 setLibcallName(RTLIB::UDIV_I32, "__hexagon_udivsi3");
1394 setOperationAction(ISD::UDIV, MVT::i32, Expand);
1396 setLibcallName(RTLIB::UDIV_I64, "__hexagon_udivdi3");
1397 setOperationAction(ISD::UDIV, MVT::i64, Expand);
1399 setLibcallName(RTLIB::UREM_I32, "__hexagon_umodsi3");
1400 setOperationAction(ISD::UREM, MVT::i32, Expand);
1402 setLibcallName(RTLIB::UREM_I64, "__hexagon_umoddi3");
1403 setOperationAction(ISD::UREM, MVT::i64, Expand);
1405 setLibcallName(RTLIB::DIV_F32, "__hexagon_divsf3");
1406 setOperationAction(ISD::FDIV, MVT::f32, Expand);
1408 setLibcallName(RTLIB::DIV_F64, "__hexagon_divdf3");
1409 setOperationAction(ISD::FDIV, MVT::f64, Expand);
1411 setLibcallName(RTLIB::ADD_F64, "__hexagon_adddf3");
1412 setLibcallName(RTLIB::SUB_F64, "__hexagon_subdf3");
1413 setLibcallName(RTLIB::MUL_F64, "__hexagon_muldf3");
1415 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
1416 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
1417 setOperationAction(ISD::FSIN, MVT::f32, Expand);
1418 setOperationAction(ISD::FSIN, MVT::f64, Expand);
1420 if (Subtarget->hasV5TOps()) {
1421 // Hexagon V5 Support.
1422 setOperationAction(ISD::FADD, MVT::f32, Legal);
1423 setOperationAction(ISD::FADD, MVT::f64, Expand);
1424 setOperationAction(ISD::FSUB, MVT::f32, Legal);
1425 setOperationAction(ISD::FSUB, MVT::f64, Expand);
1426 setOperationAction(ISD::FMUL, MVT::f64, Expand);
1427 setOperationAction(ISD::FP_EXTEND, MVT::f32, Legal);
1428 setCondCodeAction(ISD::SETOEQ, MVT::f32, Legal);
1429 setCondCodeAction(ISD::SETOEQ, MVT::f64, Legal);
1430 setCondCodeAction(ISD::SETUEQ, MVT::f32, Legal);
1431 setCondCodeAction(ISD::SETUEQ, MVT::f64, Legal);
1433 setCondCodeAction(ISD::SETOGE, MVT::f32, Legal);
1434 setCondCodeAction(ISD::SETOGE, MVT::f64, Legal);
1435 setCondCodeAction(ISD::SETUGE, MVT::f32, Legal);
1436 setCondCodeAction(ISD::SETUGE, MVT::f64, Legal);
1438 setCondCodeAction(ISD::SETOGT, MVT::f32, Legal);
1439 setCondCodeAction(ISD::SETOGT, MVT::f64, Legal);
1440 setCondCodeAction(ISD::SETUGT, MVT::f32, Legal);
1441 setCondCodeAction(ISD::SETUGT, MVT::f64, Legal);
1443 setCondCodeAction(ISD::SETOLE, MVT::f32, Legal);
1444 setCondCodeAction(ISD::SETOLE, MVT::f64, Legal);
1445 setCondCodeAction(ISD::SETOLT, MVT::f32, Legal);
1446 setCondCodeAction(ISD::SETOLT, MVT::f64, Legal);
1448 setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
1449 setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
1451 setOperationAction(ISD::FP_TO_UINT, MVT::i1, Promote);
1452 setOperationAction(ISD::FP_TO_SINT, MVT::i1, Promote);
1453 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Promote);
1454 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote);
1456 setOperationAction(ISD::FP_TO_UINT, MVT::i8, Promote);
1457 setOperationAction(ISD::FP_TO_SINT, MVT::i8, Promote);
1458 setOperationAction(ISD::UINT_TO_FP, MVT::i8, Promote);
1459 setOperationAction(ISD::SINT_TO_FP, MVT::i8, Promote);
1461 setOperationAction(ISD::FP_TO_UINT, MVT::i16, Promote);
1462 setOperationAction(ISD::FP_TO_SINT, MVT::i16, Promote);
1463 setOperationAction(ISD::UINT_TO_FP, MVT::i16, Promote);
1464 setOperationAction(ISD::SINT_TO_FP, MVT::i16, Promote);
1466 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1467 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1468 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1469 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1471 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1472 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1473 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1474 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1476 setOperationAction(ISD::FABS, MVT::f32, Legal);
1477 setOperationAction(ISD::FABS, MVT::f64, Expand);
1479 setOperationAction(ISD::FNEG, MVT::f32, Legal);
1480 setOperationAction(ISD::FNEG, MVT::f64, Expand);
1483 // Expand fp<->uint.
1484 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Expand);
1485 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
1487 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
1488 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
1490 setLibcallName(RTLIB::SINTTOFP_I64_F32, "__hexagon_floatdisf");
1491 setLibcallName(RTLIB::UINTTOFP_I64_F32, "__hexagon_floatundisf");
1493 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__hexagon_floatunsisf");
1494 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__hexagon_floatsisf");
1496 setLibcallName(RTLIB::SINTTOFP_I64_F64, "__hexagon_floatdidf");
1497 setLibcallName(RTLIB::UINTTOFP_I64_F64, "__hexagon_floatundidf");
1499 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__hexagon_floatunsidf");
1500 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__hexagon_floatsidf");
1502 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__hexagon_fixunssfsi");
1503 setLibcallName(RTLIB::FPTOUINT_F32_I64, "__hexagon_fixunssfdi");
1505 setLibcallName(RTLIB::FPTOSINT_F64_I64, "__hexagon_fixdfdi");
1506 setLibcallName(RTLIB::FPTOSINT_F32_I64, "__hexagon_fixsfdi");
1508 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__hexagon_fixunsdfsi");
1509 setLibcallName(RTLIB::FPTOUINT_F64_I64, "__hexagon_fixunsdfdi");
1512 setLibcallName(RTLIB::ADD_F32, "__hexagon_addsf3");
1513 setOperationAction(ISD::FADD, MVT::f32, Expand);
1514 setOperationAction(ISD::FADD, MVT::f64, Expand);
1516 setLibcallName(RTLIB::SUB_F32, "__hexagon_subsf3");
1517 setOperationAction(ISD::FSUB, MVT::f32, Expand);
1518 setOperationAction(ISD::FSUB, MVT::f64, Expand);
1520 setLibcallName(RTLIB::FPEXT_F32_F64, "__hexagon_extendsfdf2");
1521 setOperationAction(ISD::FP_EXTEND, MVT::f32, Expand);
1523 setLibcallName(RTLIB::OEQ_F32, "__hexagon_eqsf2");
1524 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
1526 setLibcallName(RTLIB::OEQ_F64, "__hexagon_eqdf2");
1527 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
1529 setLibcallName(RTLIB::OGE_F32, "__hexagon_gesf2");
1530 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
1532 setLibcallName(RTLIB::OGE_F64, "__hexagon_gedf2");
1533 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
1535 setLibcallName(RTLIB::OGT_F32, "__hexagon_gtsf2");
1536 setCondCodeAction(ISD::SETOGT, MVT::f32, Expand);
1538 setLibcallName(RTLIB::OGT_F64, "__hexagon_gtdf2");
1539 setCondCodeAction(ISD::SETOGT, MVT::f64, Expand);
1541 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__hexagon_fixdfsi");
1542 setOperationAction(ISD::FP_TO_SINT, MVT::f64, Expand);
1544 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__hexagon_fixsfsi");
1545 setOperationAction(ISD::FP_TO_SINT, MVT::f32, Expand);
1547 setLibcallName(RTLIB::OLE_F64, "__hexagon_ledf2");
1548 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
1550 setLibcallName(RTLIB::OLE_F32, "__hexagon_lesf2");
1551 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
1553 setLibcallName(RTLIB::OLT_F64, "__hexagon_ltdf2");
1554 setCondCodeAction(ISD::SETOLT, MVT::f64, Expand);
1556 setLibcallName(RTLIB::OLT_F32, "__hexagon_ltsf2");
1557 setCondCodeAction(ISD::SETOLT, MVT::f32, Expand);
1559 setOperationAction(ISD::FMUL, MVT::f64, Expand);
1561 setLibcallName(RTLIB::MUL_F32, "__hexagon_mulsf3");
1562 setOperationAction(ISD::MUL, MVT::f32, Expand);
1564 setLibcallName(RTLIB::UNE_F64, "__hexagon_nedf2");
1565 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
1567 setLibcallName(RTLIB::UNE_F32, "__hexagon_nesf2");
1569 setLibcallName(RTLIB::SUB_F64, "__hexagon_subdf3");
1570 setOperationAction(ISD::SUB, MVT::f64, Expand);
1572 setLibcallName(RTLIB::SUB_F32, "__hexagon_subsf3");
1573 setOperationAction(ISD::SUB, MVT::f32, Expand);
1575 setLibcallName(RTLIB::FPROUND_F64_F32, "__hexagon_truncdfsf2");
1576 setOperationAction(ISD::FP_ROUND, MVT::f64, Expand);
1578 setLibcallName(RTLIB::UO_F64, "__hexagon_unorddf2");
1579 setCondCodeAction(ISD::SETUO, MVT::f64, Expand);
1581 setLibcallName(RTLIB::O_F64, "__hexagon_unorddf2");
1582 setCondCodeAction(ISD::SETO, MVT::f64, Expand);
1584 setLibcallName(RTLIB::O_F32, "__hexagon_unordsf2");
1585 setCondCodeAction(ISD::SETO, MVT::f32, Expand);
1587 setLibcallName(RTLIB::UO_F32, "__hexagon_unordsf2");
1588 setCondCodeAction(ISD::SETUO, MVT::f32, Expand);
1590 setOperationAction(ISD::FABS, MVT::f32, Expand);
1591 setOperationAction(ISD::FABS, MVT::f64, Expand);
1592 setOperationAction(ISD::FNEG, MVT::f32, Expand);
1593 setOperationAction(ISD::FNEG, MVT::f64, Expand);
1596 setLibcallName(RTLIB::SREM_I32, "__hexagon_modsi3");
1597 setOperationAction(ISD::SREM, MVT::i32, Expand);
1599 setIndexedLoadAction(ISD::POST_INC, MVT::i8, Legal);
1600 setIndexedLoadAction(ISD::POST_INC, MVT::i16, Legal);
1601 setIndexedLoadAction(ISD::POST_INC, MVT::i32, Legal);
1602 setIndexedLoadAction(ISD::POST_INC, MVT::i64, Legal);
1604 setIndexedStoreAction(ISD::POST_INC, MVT::i8, Legal);
1605 setIndexedStoreAction(ISD::POST_INC, MVT::i16, Legal);
1606 setIndexedStoreAction(ISD::POST_INC, MVT::i32, Legal);
1607 setIndexedStoreAction(ISD::POST_INC, MVT::i64, Legal);
1609 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
1611 // Turn FP extload into load/fextend.
1612 for (MVT VT : MVT::fp_valuetypes())
1613 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
1615 // No extending loads from i32.
1616 for (MVT VT : MVT::integer_valuetypes()) {
1617 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i32, Expand);
1618 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i32, Expand);
1619 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i32, Expand);
1622 // Turn FP truncstore into trunc + store.
1623 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
1625 // Custom legalize GlobalAddress nodes into CONST32.
1626 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
1627 setOperationAction(ISD::GlobalAddress, MVT::i8, Custom);
1628 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
1630 setOperationAction(ISD::TRUNCATE, MVT::i64, Expand);
1632 // Hexagon doesn't have sext_inreg, replace them with shl/sra.
1633 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
1635 // Hexagon has no REM or DIVREM operations.
1636 setOperationAction(ISD::UREM, MVT::i32, Expand);
1637 setOperationAction(ISD::SREM, MVT::i32, Expand);
1638 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
1639 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
1640 setOperationAction(ISD::SREM, MVT::i64, Expand);
1641 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
1642 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
1644 setOperationAction(ISD::BSWAP, MVT::i64, Expand);
1646 // Lower SELECT_CC to SETCC and SELECT.
1647 setOperationAction(ISD::SELECT_CC, MVT::i1, Expand);
1648 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
1649 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
1651 if (Subtarget->hasV5TOps()) {
1653 // We need to make the operation type of SELECT node to be Custom,
1654 // such that we don't go into the infinite loop of
1655 // select -> setcc -> select_cc -> select loop.
1656 setOperationAction(ISD::SELECT, MVT::f32, Custom);
1657 setOperationAction(ISD::SELECT, MVT::f64, Custom);
1659 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
1660 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
1664 // Hexagon has no select or setcc: expand to SELECT_CC.
1665 setOperationAction(ISD::SELECT, MVT::f32, Expand);
1666 setOperationAction(ISD::SELECT, MVT::f64, Expand);
1669 // Hexagon needs to optimize cases with negative constants.
1670 setOperationAction(ISD::SETCC, MVT::i16, Custom);
1671 setOperationAction(ISD::SETCC, MVT::i8, Custom);
1673 if (EmitJumpTables) {
1674 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
1676 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
1678 // Increase jump tables cutover to 5, was 4.
1679 setMinimumJumpTableEntries(5);
1681 setOperationAction(ISD::BR_CC, MVT::f32, Expand);
1682 setOperationAction(ISD::BR_CC, MVT::f64, Expand);
1683 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1684 setOperationAction(ISD::BR_CC, MVT::i32, Expand);
1685 setOperationAction(ISD::BR_CC, MVT::i64, Expand);
1687 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
1689 setOperationAction(ISD::FSIN, MVT::f64, Expand);
1690 setOperationAction(ISD::FCOS, MVT::f64, Expand);
1691 setOperationAction(ISD::FREM, MVT::f64, Expand);
1692 setOperationAction(ISD::FSIN, MVT::f32, Expand);
1693 setOperationAction(ISD::FCOS, MVT::f32, Expand);
1694 setOperationAction(ISD::FREM, MVT::f32, Expand);
1695 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
1696 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
1698 // In V4, we have double word add/sub with carry. The problem with
1699 // modelling this instruction is that it produces 2 results - Rdd and Px.
1700 // To model update of Px, we will have to use Defs[p0..p3] which will
1701 // cause any predicate live range to spill. So, we pretend we dont't
1702 // have these instructions.
1703 setOperationAction(ISD::ADDE, MVT::i8, Expand);
1704 setOperationAction(ISD::ADDE, MVT::i16, Expand);
1705 setOperationAction(ISD::ADDE, MVT::i32, Expand);
1706 setOperationAction(ISD::ADDE, MVT::i64, Expand);
1707 setOperationAction(ISD::SUBE, MVT::i8, Expand);
1708 setOperationAction(ISD::SUBE, MVT::i16, Expand);
1709 setOperationAction(ISD::SUBE, MVT::i32, Expand);
1710 setOperationAction(ISD::SUBE, MVT::i64, Expand);
1711 setOperationAction(ISD::ADDC, MVT::i8, Expand);
1712 setOperationAction(ISD::ADDC, MVT::i16, Expand);
1713 setOperationAction(ISD::ADDC, MVT::i32, Expand);
1714 setOperationAction(ISD::ADDC, MVT::i64, Expand);
1715 setOperationAction(ISD::SUBC, MVT::i8, Expand);
1716 setOperationAction(ISD::SUBC, MVT::i16, Expand);
1717 setOperationAction(ISD::SUBC, MVT::i32, Expand);
1718 setOperationAction(ISD::SUBC, MVT::i64, Expand);
1720 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
1721 setOperationAction(ISD::CTPOP, MVT::i64, Expand);
1722 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
1723 setOperationAction(ISD::CTTZ, MVT::i64, Expand);
1724 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
1725 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
1726 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
1727 setOperationAction(ISD::CTLZ, MVT::i64, Expand);
1728 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
1729 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
1731 setOperationAction(ISD::ROTL, MVT::i32, Expand);
1732 setOperationAction(ISD::ROTR, MVT::i32, Expand);
1733 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
1734 setOperationAction(ISD::ROTL, MVT::i64, Expand);
1735 setOperationAction(ISD::ROTR, MVT::i64, Expand);
1736 setOperationAction(ISD::SHL_PARTS, MVT::i64, Expand);
1737 setOperationAction(ISD::SRA_PARTS, MVT::i64, Expand);
1738 setOperationAction(ISD::SRL_PARTS, MVT::i64, Expand);
1739 setOperationAction(ISD::BR_CC, MVT::i64, Expand);
1741 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
1742 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
1743 setOperationAction(ISD::FPOW, MVT::f64, Expand);
1744 setOperationAction(ISD::FPOW, MVT::f32, Expand);
1746 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
1747 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
1748 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
1750 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
1751 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
1753 setOperationAction(ISD::MULHS, MVT::i64, Expand);
1754 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
1755 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
1757 setOperationAction(ISD::EH_RETURN, MVT::Other, Custom);
1759 setExceptionPointerRegister(Hexagon::R0);
1760 setExceptionSelectorRegister(Hexagon::R1);
1762 // VASTART needs to be custom lowered to use the VarArgsFrameIndex.
1763 setOperationAction(ISD::VASTART, MVT::Other, Custom);
1765 // Use the default implementation.
1766 setOperationAction(ISD::VAARG, MVT::Other, Expand);
1767 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
1768 setOperationAction(ISD::VAEND, MVT::Other, Expand);
1769 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
1770 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
1772 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
1773 setOperationAction(ISD::INLINEASM, MVT::Other, Custom);
1775 setMinFunctionAlignment(2);
1777 // Needed for DYNAMIC_STACKALLOC expansion.
1778 const HexagonRegisterInfo *QRI = Subtarget->getRegisterInfo();
1779 setStackPointerRegisterToSaveRestore(QRI->getStackRegister());
1780 setSchedulingPreference(Sched::VLIW);
1784 HexagonTargetLowering::getTargetNodeName(unsigned Opcode) const {
1786 default: return nullptr;
1787 case HexagonISD::CONST32: return "HexagonISD::CONST32";
1788 case HexagonISD::CONST32_GP: return "HexagonISD::CONST32_GP";
1789 case HexagonISD::CONST32_Int_Real: return "HexagonISD::CONST32_Int_Real";
1790 case HexagonISD::ADJDYNALLOC: return "HexagonISD::ADJDYNALLOC";
1791 case HexagonISD::CMPICC: return "HexagonISD::CMPICC";
1792 case HexagonISD::CMPFCC: return "HexagonISD::CMPFCC";
1793 case HexagonISD::BRICC: return "HexagonISD::BRICC";
1794 case HexagonISD::BRFCC: return "HexagonISD::BRFCC";
1795 case HexagonISD::SELECT_ICC: return "HexagonISD::SELECT_ICC";
1796 case HexagonISD::SELECT_FCC: return "HexagonISD::SELECT_FCC";
1797 case HexagonISD::Hi: return "HexagonISD::Hi";
1798 case HexagonISD::Lo: return "HexagonISD::Lo";
1799 case HexagonISD::JT: return "HexagonISD::JT";
1800 case HexagonISD::CP: return "HexagonISD::CP";
1801 case HexagonISD::POPCOUNT: return "HexagonISD::POPCOUNT";
1802 case HexagonISD::COMBINE: return "HexagonISD::COMBINE";
1803 case HexagonISD::PACKHL: return "HexagonISD::PACKHL";
1804 case HexagonISD::VSPLATB: return "HexagonISD::VSPLTB";
1805 case HexagonISD::VSPLATH: return "HexagonISD::VSPLATH";
1806 case HexagonISD::SHUFFEB: return "HexagonISD::SHUFFEB";
1807 case HexagonISD::SHUFFEH: return "HexagonISD::SHUFFEH";
1808 case HexagonISD::SHUFFOB: return "HexagonISD::SHUFFOB";
1809 case HexagonISD::SHUFFOH: return "HexagonISD::SHUFFOH";
1810 case HexagonISD::VSXTBH: return "HexagonISD::VSXTBH";
1811 case HexagonISD::VSXTBW: return "HexagonISD::VSXTBW";
1812 case HexagonISD::VSRAW: return "HexagonISD::VSRAW";
1813 case HexagonISD::VSRAH: return "HexagonISD::VSRAH";
1814 case HexagonISD::VSRLW: return "HexagonISD::VSRLW";
1815 case HexagonISD::VSRLH: return "HexagonISD::VSRLH";
1816 case HexagonISD::VSHLW: return "HexagonISD::VSHLW";
1817 case HexagonISD::VSHLH: return "HexagonISD::VSHLH";
1818 case HexagonISD::VCMPBEQ: return "HexagonISD::VCMPBEQ";
1819 case HexagonISD::VCMPBGT: return "HexagonISD::VCMPBGT";
1820 case HexagonISD::VCMPBGTU: return "HexagonISD::VCMPBGTU";
1821 case HexagonISD::VCMPHEQ: return "HexagonISD::VCMPHEQ";
1822 case HexagonISD::VCMPHGT: return "HexagonISD::VCMPHGT";
1823 case HexagonISD::VCMPHGTU: return "HexagonISD::VCMPHGTU";
1824 case HexagonISD::VCMPWEQ: return "HexagonISD::VCMPWEQ";
1825 case HexagonISD::VCMPWGT: return "HexagonISD::VCMPWGT";
1826 case HexagonISD::VCMPWGTU: return "HexagonISD::VCMPWGTU";
1827 case HexagonISD::INSERT_ri: return "HexagonISD::INSERT_ri";
1828 case HexagonISD::INSERT_rd: return "HexagonISD::INSERT_rd";
1829 case HexagonISD::INSERT_riv: return "HexagonISD::INSERT_riv";
1830 case HexagonISD::INSERT_rdv: return "HexagonISD::INSERT_rdv";
1831 case HexagonISD::EXTRACTU_ri: return "HexagonISD::EXTRACTU_ri";
1832 case HexagonISD::EXTRACTU_rd: return "HexagonISD::EXTRACTU_rd";
1833 case HexagonISD::EXTRACTU_riv: return "HexagonISD::EXTRACTU_riv";
1834 case HexagonISD::EXTRACTU_rdv: return "HexagonISD::EXTRACTU_rdv";
1835 case HexagonISD::FTOI: return "HexagonISD::FTOI";
1836 case HexagonISD::ITOF: return "HexagonISD::ITOF";
1837 case HexagonISD::CALLv3: return "HexagonISD::CALLv3";
1838 case HexagonISD::CALLv3nr: return "HexagonISD::CALLv3nr";
1839 case HexagonISD::CALLR: return "HexagonISD::CALLR";
1840 case HexagonISD::RET_FLAG: return "HexagonISD::RET_FLAG";
1841 case HexagonISD::BR_JT: return "HexagonISD::BR_JT";
1842 case HexagonISD::TC_RETURN: return "HexagonISD::TC_RETURN";
1843 case HexagonISD::EH_RETURN: return "HexagonISD::EH_RETURN";
1848 HexagonTargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
1849 EVT MTy1 = EVT::getEVT(Ty1);
1850 EVT MTy2 = EVT::getEVT(Ty2);
1851 if (!MTy1.isSimple() || !MTy2.isSimple()) {
1854 return ((MTy1.getSimpleVT() == MVT::i64) && (MTy2.getSimpleVT() == MVT::i32));
1857 bool HexagonTargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
1858 if (!VT1.isSimple() || !VT2.isSimple()) {
1861 return ((VT1.getSimpleVT() == MVT::i64) && (VT2.getSimpleVT() == MVT::i32));
1864 // shouldExpandBuildVectorWithShuffles
1865 // Should we expand the build vector with shuffles?
1867 HexagonTargetLowering::shouldExpandBuildVectorWithShuffles(EVT VT,
1868 unsigned DefinedValues) const {
1870 // Hexagon vector shuffle operates on element sizes of bytes or halfwords
1871 EVT EltVT = VT.getVectorElementType();
1872 int EltBits = EltVT.getSizeInBits();
1873 if ((EltBits != 8) && (EltBits != 16))
1876 return TargetLowering::shouldExpandBuildVectorWithShuffles(VT, DefinedValues);
1879 // LowerVECTOR_SHUFFLE - Lower a vector shuffle (V1, V2, V3). V1 and
1880 // V2 are the two vectors to select data from, V3 is the permutation.
1881 static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
1882 const ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op);
1883 SDValue V1 = Op.getOperand(0);
1884 SDValue V2 = Op.getOperand(1);
1886 EVT VT = Op.getValueType();
1888 if (V2.getOpcode() == ISD::UNDEF)
1891 if (SVN->isSplat()) {
1892 int Lane = SVN->getSplatIndex();
1893 if (Lane == -1) Lane = 0;
1895 // Test if V1 is a SCALAR_TO_VECTOR.
1896 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR)
1897 return createSplat(DAG, dl, VT, V1.getOperand(0));
1899 // Test if V1 is a BUILD_VECTOR which is equivalent to a SCALAR_TO_VECTOR
1900 // (and probably will turn into a SCALAR_TO_VECTOR once legalization
1902 if (Lane == 0 && V1.getOpcode() == ISD::BUILD_VECTOR &&
1903 !isa<ConstantSDNode>(V1.getOperand(0))) {
1904 bool IsScalarToVector = true;
1905 for (unsigned i = 1, e = V1.getNumOperands(); i != e; ++i)
1906 if (V1.getOperand(i).getOpcode() != ISD::UNDEF) {
1907 IsScalarToVector = false;
1910 if (IsScalarToVector)
1911 return createSplat(DAG, dl, VT, V1.getOperand(0));
1913 return createSplat(DAG, dl, VT, DAG.getConstant(Lane, MVT::i32));
1916 // FIXME: We need to support more general vector shuffles. See
1917 // below the comment from the ARM backend that deals in the general
1918 // case with the vector shuffles. For now, let expand handle these.
1921 // If the shuffle is not directly supported and it has 4 elements, use
1922 // the PerfectShuffle-generated table to synthesize it from other shuffles.
1925 // If BUILD_VECTOR has same base element repeated several times,
1927 static bool isCommonSplatElement(BuildVectorSDNode *BVN) {
1928 unsigned NElts = BVN->getNumOperands();
1929 SDValue V0 = BVN->getOperand(0);
1931 for (unsigned i = 1, e = NElts; i != e; ++i) {
1932 if (BVN->getOperand(i) != V0)
1938 // LowerVECTOR_SHIFT - Lower a vector shift. Try to convert
1939 // <VT> = SHL/SRA/SRL <VT> by <VT> to Hexagon specific
1940 // <VT> = SHL/SRA/SRL <VT> by <IT/i32>.
1941 static SDValue LowerVECTOR_SHIFT(SDValue Op, SelectionDAG &DAG) {
1942 BuildVectorSDNode *BVN = 0;
1943 SDValue V1 = Op.getOperand(0);
1944 SDValue V2 = Op.getOperand(1);
1947 EVT VT = Op.getValueType();
1949 if ((BVN = dyn_cast<BuildVectorSDNode>(V1.getNode())) &&
1950 isCommonSplatElement(BVN))
1952 else if ((BVN = dyn_cast<BuildVectorSDNode>(V2.getNode())) &&
1953 isCommonSplatElement(BVN))
1958 SDValue CommonSplat = BVN->getOperand(0);
1961 if (VT.getSimpleVT() == MVT::v4i16) {
1962 switch (Op.getOpcode()) {
1964 Result = DAG.getNode(HexagonISD::VSRAH, dl, VT, V3, CommonSplat);
1967 Result = DAG.getNode(HexagonISD::VSHLH, dl, VT, V3, CommonSplat);
1970 Result = DAG.getNode(HexagonISD::VSRLH, dl, VT, V3, CommonSplat);
1975 } else if (VT.getSimpleVT() == MVT::v2i32) {
1976 switch (Op.getOpcode()) {
1978 Result = DAG.getNode(HexagonISD::VSRAW, dl, VT, V3, CommonSplat);
1981 Result = DAG.getNode(HexagonISD::VSHLW, dl, VT, V3, CommonSplat);
1984 Result = DAG.getNode(HexagonISD::VSRLW, dl, VT, V3, CommonSplat);
1993 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
1997 HexagonTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
1998 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
2000 EVT VT = Op.getValueType();
2002 unsigned Size = VT.getSizeInBits();
2004 // A vector larger than 64 bits cannot be represented in Hexagon.
2005 // Expand will split the vector.
2009 APInt APSplatBits, APSplatUndef;
2010 unsigned SplatBitSize;
2012 unsigned NElts = BVN->getNumOperands();
2014 // Try to generate a SPLAT instruction.
2015 if ((VT.getSimpleVT() == MVT::v4i8 || VT.getSimpleVT() == MVT::v4i16) &&
2016 (BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
2017 HasAnyUndefs, 0, true) && SplatBitSize <= 16)) {
2018 unsigned SplatBits = APSplatBits.getZExtValue();
2019 int32_t SextVal = ((int32_t) (SplatBits << (32 - SplatBitSize)) >>
2020 (32 - SplatBitSize));
2021 return createSplat(DAG, dl, VT, DAG.getConstant(SextVal, MVT::i32));
2024 // Try to generate COMBINE to build v2i32 vectors.
2025 if (VT.getSimpleVT() == MVT::v2i32) {
2026 SDValue V0 = BVN->getOperand(0);
2027 SDValue V1 = BVN->getOperand(1);
2029 if (V0.getOpcode() == ISD::UNDEF)
2030 V0 = DAG.getConstant(0, MVT::i32);
2031 if (V1.getOpcode() == ISD::UNDEF)
2032 V1 = DAG.getConstant(0, MVT::i32);
2034 ConstantSDNode *C0 = dyn_cast<ConstantSDNode>(V0);
2035 ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(V1);
2036 // If the element isn't a constant, it is in a register:
2037 // generate a COMBINE Register Register instruction.
2039 return DAG.getNode(HexagonISD::COMBINE, dl, VT, V1, V0);
2041 // If one of the operands is an 8 bit integer constant, generate
2042 // a COMBINE Immediate Immediate instruction.
2043 if (isInt<8>(C0->getSExtValue()) ||
2044 isInt<8>(C1->getSExtValue()))
2045 return DAG.getNode(HexagonISD::COMBINE, dl, VT, V1, V0);
2048 // Try to generate a S2_packhl to build v2i16 vectors.
2049 if (VT.getSimpleVT() == MVT::v2i16) {
2050 for (unsigned i = 0, e = NElts; i != e; ++i) {
2051 if (BVN->getOperand(i).getOpcode() == ISD::UNDEF)
2053 ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(BVN->getOperand(i));
2054 // If the element isn't a constant, it is in a register:
2055 // generate a S2_packhl instruction.
2057 SDValue pack = DAG.getNode(HexagonISD::PACKHL, dl, MVT::v4i16,
2058 BVN->getOperand(1), BVN->getOperand(0));
2060 return DAG.getTargetExtractSubreg(Hexagon::subreg_loreg, dl, MVT::v2i16,
2066 // In the general case, generate a CONST32 or a CONST64 for constant vectors,
2067 // and insert_vector_elt for all the other cases.
2069 unsigned EltSize = Size / NElts;
2071 uint64_t Mask = ~uint64_t(0ULL) >> (64 - EltSize);
2072 bool HasNonConstantElements = false;
2074 for (unsigned i = 0, e = NElts; i != e; ++i) {
2075 // LLVM's BUILD_VECTOR operands are in Little Endian mode, whereas Hexagon's
2076 // combine, const64, etc. are Big Endian.
2077 unsigned OpIdx = NElts - i - 1;
2078 SDValue Operand = BVN->getOperand(OpIdx);
2079 if (Operand.getOpcode() == ISD::UNDEF)
2083 if (ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Operand))
2084 Val = Cst->getSExtValue();
2086 HasNonConstantElements = true;
2089 Res = (Res << EltSize) | Val;
2093 ConstVal = DAG.getConstant(Res, MVT::i64);
2095 ConstVal = DAG.getConstant(Res, MVT::i32);
2097 // When there are non constant operands, add them with INSERT_VECTOR_ELT to
2098 // ConstVal, the constant part of the vector.
2099 if (HasNonConstantElements) {
2100 EVT EltVT = VT.getVectorElementType();
2101 SDValue Width = DAG.getConstant(EltVT.getSizeInBits(), MVT::i64);
2102 SDValue Shifted = DAG.getNode(ISD::SHL, dl, MVT::i64, Width,
2103 DAG.getConstant(32, MVT::i64));
2105 for (unsigned i = 0, e = NElts; i != e; ++i) {
2106 // LLVM's BUILD_VECTOR operands are in Little Endian mode, whereas Hexagon
2108 unsigned OpIdx = NElts - i - 1;
2109 SDValue Operand = BVN->getOperand(OpIdx);
2110 if (isa<ConstantSDNode>(Operand))
2111 // This operand is already in ConstVal.
2114 if (VT.getSizeInBits() == 64 &&
2115 Operand.getValueType().getSizeInBits() == 32) {
2116 SDValue C = DAG.getConstant(0, MVT::i32);
2117 Operand = DAG.getNode(HexagonISD::COMBINE, dl, VT, C, Operand);
2120 SDValue Idx = DAG.getConstant(OpIdx, MVT::i64);
2121 SDValue Offset = DAG.getNode(ISD::MUL, dl, MVT::i64, Idx, Width);
2122 SDValue Combined = DAG.getNode(ISD::OR, dl, MVT::i64, Shifted, Offset);
2123 const SDValue Ops[] = {ConstVal, Operand, Combined};
2125 if (VT.getSizeInBits() == 32)
2126 ConstVal = DAG.getNode(HexagonISD::INSERT_riv, dl, MVT::i32, Ops);
2128 ConstVal = DAG.getNode(HexagonISD::INSERT_rdv, dl, MVT::i64, Ops);
2132 return DAG.getNode(ISD::BITCAST, dl, VT, ConstVal);
2136 HexagonTargetLowering::LowerCONCAT_VECTORS(SDValue Op,
2137 SelectionDAG &DAG) const {
2139 EVT VT = Op.getValueType();
2140 unsigned NElts = Op.getNumOperands();
2141 SDValue Vec = Op.getOperand(0);
2142 EVT VecVT = Vec.getValueType();
2143 SDValue Width = DAG.getConstant(VecVT.getSizeInBits(), MVT::i64);
2144 SDValue Shifted = DAG.getNode(ISD::SHL, dl, MVT::i64, Width,
2145 DAG.getConstant(32, MVT::i64));
2146 SDValue ConstVal = DAG.getConstant(0, MVT::i64);
2148 ConstantSDNode *W = dyn_cast<ConstantSDNode>(Width);
2149 ConstantSDNode *S = dyn_cast<ConstantSDNode>(Shifted);
2151 if ((VecVT.getSimpleVT() == MVT::v2i16) && (NElts == 2) && W && S) {
2152 if ((W->getZExtValue() == 32) && ((S->getZExtValue() >> 32) == 32)) {
2153 // We are trying to concat two v2i16 to a single v4i16.
2154 SDValue Vec0 = Op.getOperand(1);
2155 SDValue Combined = DAG.getNode(HexagonISD::COMBINE, dl, VT, Vec0, Vec);
2156 return DAG.getNode(ISD::BITCAST, dl, VT, Combined);
2160 if ((VecVT.getSimpleVT() == MVT::v4i8) && (NElts == 2) && W && S) {
2161 if ((W->getZExtValue() == 32) && ((S->getZExtValue() >> 32) == 32)) {
2162 // We are trying to concat two v4i8 to a single v8i8.
2163 SDValue Vec0 = Op.getOperand(1);
2164 SDValue Combined = DAG.getNode(HexagonISD::COMBINE, dl, VT, Vec0, Vec);
2165 return DAG.getNode(ISD::BITCAST, dl, VT, Combined);
2169 for (unsigned i = 0, e = NElts; i != e; ++i) {
2170 unsigned OpIdx = NElts - i - 1;
2171 SDValue Operand = Op.getOperand(OpIdx);
2173 if (VT.getSizeInBits() == 64 &&
2174 Operand.getValueType().getSizeInBits() == 32) {
2175 SDValue C = DAG.getConstant(0, MVT::i32);
2176 Operand = DAG.getNode(HexagonISD::COMBINE, dl, VT, C, Operand);
2179 SDValue Idx = DAG.getConstant(OpIdx, MVT::i64);
2180 SDValue Offset = DAG.getNode(ISD::MUL, dl, MVT::i64, Idx, Width);
2181 SDValue Combined = DAG.getNode(ISD::OR, dl, MVT::i64, Shifted, Offset);
2182 const SDValue Ops[] = {ConstVal, Operand, Combined};
2184 if (VT.getSizeInBits() == 32)
2185 ConstVal = DAG.getNode(HexagonISD::INSERT_riv, dl, MVT::i32, Ops);
2187 ConstVal = DAG.getNode(HexagonISD::INSERT_rdv, dl, MVT::i64, Ops);
2190 return DAG.getNode(ISD::BITCAST, dl, VT, ConstVal);
2194 HexagonTargetLowering::LowerEXTRACT_VECTOR(SDValue Op,
2195 SelectionDAG &DAG) const {
2196 EVT VT = Op.getValueType();
2197 int VTN = VT.isVector() ? VT.getVectorNumElements() : 1;
2199 SDValue Idx = Op.getOperand(1);
2200 SDValue Vec = Op.getOperand(0);
2201 EVT VecVT = Vec.getValueType();
2202 EVT EltVT = VecVT.getVectorElementType();
2203 int EltSize = EltVT.getSizeInBits();
2204 SDValue Width = DAG.getConstant(Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT ?
2205 EltSize : VTN * EltSize, MVT::i64);
2207 // Constant element number.
2208 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Idx)) {
2209 SDValue Offset = DAG.getConstant(C->getZExtValue() * EltSize, MVT::i32);
2210 const SDValue Ops[] = {Vec, Width, Offset};
2212 ConstantSDNode *W = dyn_cast<ConstantSDNode>(Width);
2213 assert(W && "Non constant width in LowerEXTRACT_VECTOR");
2216 // For certain extracts, it is a simple _hi/_lo subreg.
2217 if (VecVT.getSimpleVT() == MVT::v2i32) {
2218 // v2i32 -> i32 vselect.
2219 if (C->getZExtValue() == 0)
2220 N = DAG.getTargetExtractSubreg(Hexagon::subreg_loreg, dl,
2222 else if (C->getZExtValue() == 1)
2223 N = DAG.getTargetExtractSubreg(Hexagon::subreg_hireg, dl,
2226 llvm_unreachable("Bad offset");
2227 } else if ((VecVT.getSimpleVT() == MVT::v4i16) &&
2228 (W->getZExtValue() == 32)) {
2229 // v4i16 -> v2i16/i32 vselect.
2230 if (C->getZExtValue() == 0)
2231 N = DAG.getTargetExtractSubreg(Hexagon::subreg_loreg, dl,
2233 else if (C->getZExtValue() == 2)
2234 N = DAG.getTargetExtractSubreg(Hexagon::subreg_hireg, dl,
2237 llvm_unreachable("Bad offset");
2238 } else if ((VecVT.getSimpleVT() == MVT::v8i8) &&
2239 (W->getZExtValue() == 32)) {
2240 // v8i8 -> v4i8/i32 vselect.
2241 if (C->getZExtValue() == 0)
2242 N = DAG.getTargetExtractSubreg(Hexagon::subreg_loreg, dl,
2244 else if (C->getZExtValue() == 4)
2245 N = DAG.getTargetExtractSubreg(Hexagon::subreg_hireg, dl,
2248 llvm_unreachable("Bad offset");
2249 } else if (VecVT.getSizeInBits() == 32) {
2250 N = DAG.getNode(HexagonISD::EXTRACTU_ri, dl, MVT::i32, Ops);
2252 N = DAG.getNode(HexagonISD::EXTRACTU_rd, dl, MVT::i64, Ops);
2253 if (VT.getSizeInBits() == 32)
2254 N = DAG.getTargetExtractSubreg(Hexagon::subreg_loreg, dl, MVT::i32, N);
2257 return DAG.getNode(ISD::BITCAST, dl, VT, N);
2260 // Variable element number.
2261 SDValue Offset = DAG.getNode(ISD::MUL, dl, MVT::i32, Idx,
2262 DAG.getConstant(EltSize, MVT::i32));
2263 SDValue Shifted = DAG.getNode(ISD::SHL, dl, MVT::i64, Width,
2264 DAG.getConstant(32, MVT::i64));
2265 SDValue Combined = DAG.getNode(ISD::OR, dl, MVT::i64, Shifted, Offset);
2267 const SDValue Ops[] = {Vec, Combined};
2270 if (VecVT.getSizeInBits() == 32) {
2271 N = DAG.getNode(HexagonISD::EXTRACTU_riv, dl, MVT::i32, Ops);
2273 N = DAG.getNode(HexagonISD::EXTRACTU_rdv, dl, MVT::i64, Ops);
2274 if (VT.getSizeInBits() == 32)
2275 N = DAG.getTargetExtractSubreg(Hexagon::subreg_loreg, dl, MVT::i32, N);
2277 return DAG.getNode(ISD::BITCAST, dl, VT, N);
2281 HexagonTargetLowering::LowerINSERT_VECTOR(SDValue Op,
2282 SelectionDAG &DAG) const {
2283 EVT VT = Op.getValueType();
2284 int VTN = VT.isVector() ? VT.getVectorNumElements() : 1;
2286 SDValue Vec = Op.getOperand(0);
2287 SDValue Val = Op.getOperand(1);
2288 SDValue Idx = Op.getOperand(2);
2289 EVT VecVT = Vec.getValueType();
2290 EVT EltVT = VecVT.getVectorElementType();
2291 int EltSize = EltVT.getSizeInBits();
2292 SDValue Width = DAG.getConstant(Op.getOpcode() == ISD::INSERT_VECTOR_ELT ?
2293 EltSize : VTN * EltSize, MVT::i64);
2295 if (ConstantSDNode *C = cast<ConstantSDNode>(Idx)) {
2296 SDValue Offset = DAG.getConstant(C->getSExtValue() * EltSize, MVT::i32);
2297 const SDValue Ops[] = {Vec, Val, Width, Offset};
2300 if (VT.getSizeInBits() == 32)
2301 N = DAG.getNode(HexagonISD::INSERT_ri, dl, MVT::i32, Ops);
2303 N = DAG.getNode(HexagonISD::INSERT_rd, dl, MVT::i64, Ops);
2305 return DAG.getNode(ISD::BITCAST, dl, VT, N);
2308 // Variable element number.
2309 SDValue Offset = DAG.getNode(ISD::MUL, dl, MVT::i32, Idx,
2310 DAG.getConstant(EltSize, MVT::i32));
2311 SDValue Shifted = DAG.getNode(ISD::SHL, dl, MVT::i64, Width,
2312 DAG.getConstant(32, MVT::i64));
2313 SDValue Combined = DAG.getNode(ISD::OR, dl, MVT::i64, Shifted, Offset);
2315 if (VT.getSizeInBits() == 64 &&
2316 Val.getValueType().getSizeInBits() == 32) {
2317 SDValue C = DAG.getConstant(0, MVT::i32);
2318 Val = DAG.getNode(HexagonISD::COMBINE, dl, VT, C, Val);
2321 const SDValue Ops[] = {Vec, Val, Combined};
2324 if (VT.getSizeInBits() == 32)
2325 N = DAG.getNode(HexagonISD::INSERT_riv, dl, MVT::i32, Ops);
2327 N = DAG.getNode(HexagonISD::INSERT_rdv, dl, MVT::i64, Ops);
2329 return DAG.getNode(ISD::BITCAST, dl, VT, N);
2333 HexagonTargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
2334 // Assuming the caller does not have either a signext or zeroext modifier, and
2335 // only one value is accepted, any reasonable truncation is allowed.
2336 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
2339 // FIXME: in principle up to 64-bit could be made safe, but it would be very
2340 // fragile at the moment: any support for multiple value returns would be
2341 // liable to disallow tail calls involving i64 -> iN truncation in many cases.
2342 return Ty1->getPrimitiveSizeInBits() <= 32;
2346 HexagonTargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
2347 SDValue Chain = Op.getOperand(0);
2348 SDValue Offset = Op.getOperand(1);
2349 SDValue Handler = Op.getOperand(2);
2352 // Mark function as containing a call to EH_RETURN.
2353 HexagonMachineFunctionInfo *FuncInfo =
2354 DAG.getMachineFunction().getInfo<HexagonMachineFunctionInfo>();
2355 FuncInfo->setHasEHReturn();
2357 unsigned OffsetReg = Hexagon::R28;
2359 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(),
2360 DAG.getRegister(Hexagon::R30, getPointerTy()),
2361 DAG.getIntPtrConstant(4));
2362 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
2364 Chain = DAG.getCopyToReg(Chain, dl, OffsetReg, Offset);
2366 // Not needed we already use it as explict input to EH_RETURN.
2367 // MF.getRegInfo().addLiveOut(OffsetReg);
2369 return DAG.getNode(HexagonISD::EH_RETURN, dl, MVT::Other, Chain);
2373 HexagonTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
2374 switch (Op.getOpcode()) {
2375 default: llvm_unreachable("Should not custom lower this!");
2376 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
2377 case ISD::INSERT_SUBVECTOR: return LowerINSERT_VECTOR(Op, DAG);
2378 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR(Op, DAG);
2379 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_VECTOR(Op, DAG);
2380 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR(Op, DAG);
2381 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
2382 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
2386 return LowerVECTOR_SHIFT(Op, DAG);
2387 case ISD::ConstantPool:
2388 return LowerConstantPool(Op, DAG);
2389 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
2390 // Frame & Return address. Currently unimplemented.
2391 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
2392 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
2393 case ISD::GlobalTLSAddress:
2394 llvm_unreachable("TLS not implemented for Hexagon.");
2395 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG);
2396 case ISD::GlobalAddress: return LowerGLOBALADDRESS(Op, DAG);
2397 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
2398 case ISD::VASTART: return LowerVASTART(Op, DAG);
2399 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
2400 // Custom lower some vector loads.
2401 case ISD::LOAD: return LowerLOAD(Op, DAG);
2403 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
2404 case ISD::SELECT: return Op;
2405 case ISD::SETCC: return LowerSETCC(Op, DAG);
2406 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
2407 case ISD::CTPOP: return LowerCTPOP(Op, DAG);
2408 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
2409 case ISD::INLINEASM: return LowerINLINEASM(Op, DAG);
2416 //===----------------------------------------------------------------------===//
2417 // Hexagon Scheduler Hooks
2418 //===----------------------------------------------------------------------===//
2420 HexagonTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
2421 MachineBasicBlock *BB)
2423 switch (MI->getOpcode()) {
2424 case Hexagon::ADJDYNALLOC: {
2425 MachineFunction *MF = BB->getParent();
2426 HexagonMachineFunctionInfo *FuncInfo =
2427 MF->getInfo<HexagonMachineFunctionInfo>();
2428 FuncInfo->addAllocaAdjustInst(MI);
2431 default: llvm_unreachable("Unexpected instr type to insert");
2435 //===----------------------------------------------------------------------===//
2436 // Inline Assembly Support
2437 //===----------------------------------------------------------------------===//
2439 std::pair<unsigned, const TargetRegisterClass *>
2440 HexagonTargetLowering::getRegForInlineAsmConstraint(
2441 const TargetRegisterInfo *TRI, const std::string &Constraint,
2443 if (Constraint.size() == 1) {
2444 switch (Constraint[0]) {
2446 switch (VT.SimpleTy) {
2448 llvm_unreachable("getRegForInlineAsmConstraint Unhandled data type");
2453 return std::make_pair(0U, &Hexagon::IntRegsRegClass);
2456 return std::make_pair(0U, &Hexagon::DoubleRegsRegClass);
2459 llvm_unreachable("Unknown asm register class");
2463 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
2466 /// isFPImmLegal - Returns true if the target can instruction select the
2467 /// specified FP immediate natively. If false, the legalizer will
2468 /// materialize the FP immediate as a load from a constant pool.
2469 bool HexagonTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
2470 return Subtarget->hasV5TOps();
2473 /// isLegalAddressingMode - Return true if the addressing mode represented by
2474 /// AM is legal for this target, for a load/store of the specified type.
2475 bool HexagonTargetLowering::isLegalAddressingMode(const AddrMode &AM,
2477 // Allows a signed-extended 11-bit immediate field.
2478 if (AM.BaseOffs <= -(1LL << 13) || AM.BaseOffs >= (1LL << 13)-1) {
2482 // No global is ever allowed as a base.
2487 int Scale = AM.Scale;
2488 if (Scale < 0) Scale = -Scale;
2490 case 0: // No scale reg, "r+i", "r", or just "i".
2492 default: // No scaled addressing mode.
2498 /// isLegalICmpImmediate - Return true if the specified immediate is legal
2499 /// icmp immediate, that is the target has icmp instructions which can compare
2500 /// a register against the immediate without having to materialize the
2501 /// immediate into a register.
2502 bool HexagonTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
2503 return Imm >= -512 && Imm <= 511;
2506 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2507 /// for tail call optimization. Targets which want to do tail call
2508 /// optimization should implement this function.
2509 bool HexagonTargetLowering::IsEligibleForTailCallOptimization(
2511 CallingConv::ID CalleeCC,
2513 bool isCalleeStructRet,
2514 bool isCallerStructRet,
2515 const SmallVectorImpl<ISD::OutputArg> &Outs,
2516 const SmallVectorImpl<SDValue> &OutVals,
2517 const SmallVectorImpl<ISD::InputArg> &Ins,
2518 SelectionDAG& DAG) const {
2519 const Function *CallerF = DAG.getMachineFunction().getFunction();
2520 CallingConv::ID CallerCC = CallerF->getCallingConv();
2521 bool CCMatch = CallerCC == CalleeCC;
2523 // ***************************************************************************
2524 // Look for obvious safe cases to perform tail call optimization that do not
2525 // require ABI changes.
2526 // ***************************************************************************
2528 // If this is a tail call via a function pointer, then don't do it!
2529 if (!(dyn_cast<GlobalAddressSDNode>(Callee))
2530 && !(dyn_cast<ExternalSymbolSDNode>(Callee))) {
2534 // Do not optimize if the calling conventions do not match.
2538 // Do not tail call optimize vararg calls.
2542 // Also avoid tail call optimization if either caller or callee uses struct
2543 // return semantics.
2544 if (isCalleeStructRet || isCallerStructRet)
2547 // In addition to the cases above, we also disable Tail Call Optimization if
2548 // the calling convention code that at least one outgoing argument needs to
2549 // go on the stack. We cannot check that here because at this point that
2550 // information is not available.
2554 // Return true when the given node fits in a positive half word.
2555 bool llvm::isPositiveHalfWord(SDNode *N) {
2556 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N);
2557 if (CN && CN->getSExtValue() > 0 && isInt<16>(CN->getSExtValue()))
2560 switch (N->getOpcode()) {
2563 case ISD::SIGN_EXTEND_INREG: