1 //===-- HexagonISelLowering.cpp - Hexagon DAG Lowering Implementation -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the interfaces that Hexagon uses to lower LLVM code
11 // into a selection DAG.
13 //===----------------------------------------------------------------------===//
15 #include "HexagonISelLowering.h"
16 #include "HexagonTargetMachine.h"
17 #include "HexagonMachineFunctionInfo.h"
18 #include "HexagonTargetObjectFile.h"
19 #include "HexagonSubtarget.h"
20 #include "llvm/DerivedTypes.h"
21 #include "llvm/Function.h"
22 #include "llvm/InlineAsm.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/GlobalAlias.h"
25 #include "llvm/Intrinsics.h"
26 #include "llvm/CallingConv.h"
27 #include "llvm/CodeGen/CallingConvLower.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/CodeGen/SelectionDAGISel.h"
33 #include "llvm/CodeGen/ValueTypes.h"
34 #include "llvm/Support/Debug.h"
35 #include "llvm/Support/ErrorHandling.h"
36 #include "llvm/CodeGen/MachineJumpTableInfo.h"
37 #include "HexagonMachineFunctionInfo.h"
38 #include "llvm/Support/CommandLine.h"
40 const unsigned Hexagon_MAX_RET_SIZE = 64;
44 EmitJumpTables("hexagon-emit-jump-tables", cl::init(true), cl::Hidden,
45 cl::desc("Control jump table emission on Hexagon target"));
47 int NumNamedVarArgParams = -1;
49 // Implement calling convention for Hexagon.
51 CC_Hexagon(unsigned ValNo, MVT ValVT,
52 MVT LocVT, CCValAssign::LocInfo LocInfo,
53 ISD::ArgFlagsTy ArgFlags, CCState &State);
56 CC_Hexagon32(unsigned ValNo, MVT ValVT,
57 MVT LocVT, CCValAssign::LocInfo LocInfo,
58 ISD::ArgFlagsTy ArgFlags, CCState &State);
61 CC_Hexagon64(unsigned ValNo, MVT ValVT,
62 MVT LocVT, CCValAssign::LocInfo LocInfo,
63 ISD::ArgFlagsTy ArgFlags, CCState &State);
66 RetCC_Hexagon(unsigned ValNo, MVT ValVT,
67 MVT LocVT, CCValAssign::LocInfo LocInfo,
68 ISD::ArgFlagsTy ArgFlags, CCState &State);
71 RetCC_Hexagon32(unsigned ValNo, MVT ValVT,
72 MVT LocVT, CCValAssign::LocInfo LocInfo,
73 ISD::ArgFlagsTy ArgFlags, CCState &State);
76 RetCC_Hexagon64(unsigned ValNo, MVT ValVT,
77 MVT LocVT, CCValAssign::LocInfo LocInfo,
78 ISD::ArgFlagsTy ArgFlags, CCState &State);
81 CC_Hexagon_VarArg (unsigned ValNo, MVT ValVT,
82 MVT LocVT, CCValAssign::LocInfo LocInfo,
83 ISD::ArgFlagsTy ArgFlags, CCState &State) {
85 // NumNamedVarArgParams can not be zero for a VarArg function.
86 assert ( (NumNamedVarArgParams > 0) &&
87 "NumNamedVarArgParams is not bigger than zero.");
89 if ( (int)ValNo < NumNamedVarArgParams ) {
90 // Deal with named arguments.
91 return CC_Hexagon(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State);
94 // Deal with un-named arguments.
96 if (ArgFlags.isByVal()) {
97 // If pass-by-value, the size allocated on stack is decided
98 // by ArgFlags.getByValSize(), not by the size of LocVT.
99 assert ((ArgFlags.getByValSize() > 8) &&
100 "ByValSize must be bigger than 8 bytes");
101 ofst = State.AllocateStack(ArgFlags.getByValSize(), 4);
102 State.addLoc(CCValAssign::getMem(ValNo, ValVT, ofst, LocVT, LocInfo));
105 if (LocVT == MVT::i32) {
106 ofst = State.AllocateStack(4, 4);
107 State.addLoc(CCValAssign::getMem(ValNo, ValVT, ofst, LocVT, LocInfo));
110 if (LocVT == MVT::i64) {
111 ofst = State.AllocateStack(8, 8);
112 State.addLoc(CCValAssign::getMem(ValNo, ValVT, ofst, LocVT, LocInfo));
122 CC_Hexagon (unsigned ValNo, MVT ValVT,
123 MVT LocVT, CCValAssign::LocInfo LocInfo,
124 ISD::ArgFlagsTy ArgFlags, CCState &State) {
126 if (ArgFlags.isByVal()) {
128 assert ((ArgFlags.getByValSize() > 8) &&
129 "ByValSize must be bigger than 8 bytes");
130 unsigned Offset = State.AllocateStack(ArgFlags.getByValSize(), 4);
131 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
135 if (LocVT == MVT::i1 || LocVT == MVT::i8 || LocVT == MVT::i16) {
138 if (ArgFlags.isSExt())
139 LocInfo = CCValAssign::SExt;
140 else if (ArgFlags.isZExt())
141 LocInfo = CCValAssign::ZExt;
143 LocInfo = CCValAssign::AExt;
146 if (LocVT == MVT::i32) {
147 if (!CC_Hexagon32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
151 if (LocVT == MVT::i64) {
152 if (!CC_Hexagon64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
156 return true; // CC didn't match.
160 static bool CC_Hexagon32(unsigned ValNo, MVT ValVT,
161 MVT LocVT, CCValAssign::LocInfo LocInfo,
162 ISD::ArgFlagsTy ArgFlags, CCState &State) {
164 static const unsigned RegList[] = {
165 Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4,
168 if (unsigned Reg = State.AllocateReg(RegList, 6)) {
169 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
173 unsigned Offset = State.AllocateStack(4, 4);
174 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
178 static bool CC_Hexagon64(unsigned ValNo, MVT ValVT,
179 MVT LocVT, CCValAssign::LocInfo LocInfo,
180 ISD::ArgFlagsTy ArgFlags, CCState &State) {
182 if (unsigned Reg = State.AllocateReg(Hexagon::D0)) {
183 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
187 static const unsigned RegList1[] = {
188 Hexagon::D1, Hexagon::D2
190 static const unsigned RegList2[] = {
191 Hexagon::R1, Hexagon::R3
193 if (unsigned Reg = State.AllocateReg(RegList1, RegList2, 2)) {
194 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
198 unsigned Offset = State.AllocateStack(8, 8, Hexagon::D2);
199 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
203 static bool RetCC_Hexagon(unsigned ValNo, MVT ValVT,
204 MVT LocVT, CCValAssign::LocInfo LocInfo,
205 ISD::ArgFlagsTy ArgFlags, CCState &State) {
208 if (LocVT == MVT::i1 ||
213 if (ArgFlags.isSExt())
214 LocInfo = CCValAssign::SExt;
215 else if (ArgFlags.isZExt())
216 LocInfo = CCValAssign::ZExt;
218 LocInfo = CCValAssign::AExt;
221 if (LocVT == MVT::i32) {
222 if (!RetCC_Hexagon32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
226 if (LocVT == MVT::i64) {
227 if (!RetCC_Hexagon64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
231 return true; // CC didn't match.
234 static bool RetCC_Hexagon32(unsigned ValNo, MVT ValVT,
235 MVT LocVT, CCValAssign::LocInfo LocInfo,
236 ISD::ArgFlagsTy ArgFlags, CCState &State) {
238 if (LocVT == MVT::i32) {
239 if (unsigned Reg = State.AllocateReg(Hexagon::R0)) {
240 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
245 unsigned Offset = State.AllocateStack(4, 4);
246 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
250 static bool RetCC_Hexagon64(unsigned ValNo, MVT ValVT,
251 MVT LocVT, CCValAssign::LocInfo LocInfo,
252 ISD::ArgFlagsTy ArgFlags, CCState &State) {
253 if (LocVT == MVT::i64) {
254 if (unsigned Reg = State.AllocateReg(Hexagon::D0)) {
255 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
260 unsigned Offset = State.AllocateStack(8, 8);
261 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
266 HexagonTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG)
271 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
272 /// by "Src" to address "Dst" of size "Size". Alignment information is
273 /// specified by the specific parameter attribute. The copy will be passed as
274 /// a byval function parameter. Sometimes what we are copying is the end of a
275 /// larger object, the part that does not fit in registers.
277 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
278 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
281 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
282 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
283 /*isVolatile=*/false, /*AlwaysInline=*/false,
284 MachinePointerInfo(), MachinePointerInfo());
288 // LowerReturn - Lower ISD::RET. If a struct is larger than 8 bytes and is
289 // passed by value, the function prototype is modified to return void and
290 // the value is stored in memory pointed by a pointer passed by caller.
292 HexagonTargetLowering::LowerReturn(SDValue Chain,
293 CallingConv::ID CallConv, bool isVarArg,
294 const SmallVectorImpl<ISD::OutputArg> &Outs,
295 const SmallVectorImpl<SDValue> &OutVals,
296 DebugLoc dl, SelectionDAG &DAG) const {
298 // CCValAssign - represent the assignment of the return value to locations.
299 SmallVector<CCValAssign, 16> RVLocs;
301 // CCState - Info about the registers and stack slot.
302 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
303 getTargetMachine(), RVLocs, *DAG.getContext());
305 // Analyze return values of ISD::RET
306 CCInfo.AnalyzeReturn(Outs, RetCC_Hexagon);
308 SDValue StackPtr = DAG.getRegister(TM.getRegisterInfo()->getStackRegister(),
311 // If this is the first return lowered for this function, add the regs to the
312 // liveout set for the function.
313 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
314 for (unsigned i = 0; i != RVLocs.size(); ++i)
315 if (RVLocs[i].isRegLoc())
316 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
320 // Copy the result values into the output registers.
321 for (unsigned i = 0; i != RVLocs.size(); ++i) {
322 CCValAssign &VA = RVLocs[i];
323 SDValue Ret = OutVals[i];
324 ISD::ArgFlagsTy Flags = Outs[i].Flags;
326 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag);
328 // Guarantee that all emitted copies are stuck together with flags.
329 Flag = Chain.getValue(1);
333 return DAG.getNode(HexagonISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
335 return DAG.getNode(HexagonISD::RET_FLAG, dl, MVT::Other, Chain);
341 /// LowerCallResult - Lower the result values of an ISD::CALL into the
342 /// appropriate copies out of appropriate physical registers. This assumes that
343 /// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
344 /// being lowered. Returns a SDNode with the same number of values as the
347 HexagonTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
348 CallingConv::ID CallConv, bool isVarArg,
350 SmallVectorImpl<ISD::InputArg> &Ins,
351 DebugLoc dl, SelectionDAG &DAG,
352 SmallVectorImpl<SDValue> &InVals,
353 const SmallVectorImpl<SDValue> &OutVals,
354 SDValue Callee) const {
356 // Assign locations to each value returned by this call.
357 SmallVector<CCValAssign, 16> RVLocs;
359 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
360 getTargetMachine(), RVLocs, *DAG.getContext());
362 CCInfo.AnalyzeCallResult(Ins, RetCC_Hexagon);
364 // Copy all of the result registers out of their specified physreg.
365 for (unsigned i = 0; i != RVLocs.size(); ++i) {
366 Chain = DAG.getCopyFromReg(Chain, dl,
367 RVLocs[i].getLocReg(),
368 RVLocs[i].getValVT(), InFlag).getValue(1);
369 InFlag = Chain.getValue(2);
370 InVals.push_back(Chain.getValue(0));
376 /// LowerCall - Functions arguments are copied from virtual regs to
377 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
379 HexagonTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
380 CallingConv::ID CallConv, bool isVarArg,
382 const SmallVectorImpl<ISD::OutputArg> &Outs,
383 const SmallVectorImpl<SDValue> &OutVals,
384 const SmallVectorImpl<ISD::InputArg> &Ins,
385 DebugLoc dl, SelectionDAG &DAG,
386 SmallVectorImpl<SDValue> &InVals) const {
388 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
390 // Analyze operands of the call, assigning locations to each operand.
391 SmallVector<CCValAssign, 16> ArgLocs;
392 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
393 getTargetMachine(), ArgLocs, *DAG.getContext());
395 // Check for varargs.
396 NumNamedVarArgParams = -1;
397 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Callee))
399 const Function* CalleeFn = NULL;
400 Callee = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, MVT::i32);
401 if ((CalleeFn = dyn_cast<Function>(GA->getGlobal())))
403 // If a function has zero args and is a vararg function, that's
404 // disallowed so it must be an undeclared function. Do not assume
405 // varargs if the callee is undefined.
406 if (CalleeFn->isVarArg() &&
407 CalleeFn->getFunctionType()->getNumParams() != 0) {
408 NumNamedVarArgParams = CalleeFn->getFunctionType()->getNumParams();
413 if (NumNamedVarArgParams > 0)
414 CCInfo.AnalyzeCallOperands(Outs, CC_Hexagon_VarArg);
416 CCInfo.AnalyzeCallOperands(Outs, CC_Hexagon);
420 bool StructAttrFlag =
421 DAG.getMachineFunction().getFunction()->hasStructRetAttr();
422 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
423 isVarArg, IsStructRet,
425 Outs, OutVals, Ins, DAG);
426 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i){
427 CCValAssign &VA = ArgLocs[i];
434 DEBUG(dbgs () << "Eligible for Tail Call\n");
437 "Argument must be passed on stack. Not eligible for Tail Call\n");
440 // Get a count of how many bytes are to be pushed on the stack.
441 unsigned NumBytes = CCInfo.getNextStackOffset();
442 SmallVector<std::pair<unsigned, SDValue>, 16> RegsToPass;
443 SmallVector<SDValue, 8> MemOpChains;
446 DAG.getCopyFromReg(Chain, dl, TM.getRegisterInfo()->getStackRegister(),
449 // Walk the register/memloc assignments, inserting copies/loads.
450 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
451 CCValAssign &VA = ArgLocs[i];
452 SDValue Arg = OutVals[i];
453 ISD::ArgFlagsTy Flags = Outs[i].Flags;
455 // Promote the value if needed.
456 switch (VA.getLocInfo()) {
458 // Loc info must be one of Full, SExt, ZExt, or AExt.
459 assert(0 && "Unknown loc info!");
460 case CCValAssign::Full:
462 case CCValAssign::SExt:
463 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
465 case CCValAssign::ZExt:
466 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
468 case CCValAssign::AExt:
469 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
474 unsigned LocMemOffset = VA.getLocMemOffset();
475 SDValue PtrOff = DAG.getConstant(LocMemOffset, StackPtr.getValueType());
476 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
478 if (Flags.isByVal()) {
479 // The argument is a struct passed by value. According to LLVM, "Arg"
481 MemOpChains.push_back(CreateCopyOfByValArgument(Arg, PtrOff, Chain,
484 // The argument is not passed by value. "Arg" is a buildin type. It is
486 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
487 MachinePointerInfo(),false, false,
493 // Arguments that can be passed on register must be kept at RegsToPass
496 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
500 // Transform all store nodes into one single node because all store
501 // nodes are independent of each other.
502 if (!MemOpChains.empty()) {
503 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &MemOpChains[0],
508 Chain = DAG.getCALLSEQ_START(Chain, DAG.getConstant(NumBytes,
509 getPointerTy(), true));
511 // Build a sequence of copy-to-reg nodes chained together with token
512 // chain and flag operands which copy the outgoing args into registers.
513 // The InFlag in necessary since all emited instructions must be
517 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
518 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
519 RegsToPass[i].second, InFlag);
520 InFlag = Chain.getValue(1);
524 // For tail calls lower the arguments to the 'real' stack slot.
526 // Force all the incoming stack arguments to be loaded from the stack
527 // before any new outgoing arguments are stored to the stack, because the
528 // outgoing stack slots may alias the incoming argument stack slots, and
529 // the alias isn't otherwise explicit. This is slightly more conservative
530 // than necessary, because it means that each store effectively depends
531 // on every argument instead of just those arguments it would clobber.
533 // Do not flag preceeding copytoreg stuff together with the following stuff.
535 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
536 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
537 RegsToPass[i].second, InFlag);
538 InFlag = Chain.getValue(1);
543 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
544 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
545 // node so that legalize doesn't hack it.
546 if (flag_aligned_memcpy) {
547 const char *MemcpyName =
548 "__hexagon_memcpy_likely_aligned_min32bytes_mult8bytes";
550 DAG.getTargetExternalSymbol(MemcpyName, getPointerTy());
551 flag_aligned_memcpy = false;
552 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
553 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, getPointerTy());
554 } else if (ExternalSymbolSDNode *S =
555 dyn_cast<ExternalSymbolSDNode>(Callee)) {
556 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
559 // Returns a chain & a flag for retval copy to use.
560 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
561 SmallVector<SDValue, 8> Ops;
562 Ops.push_back(Chain);
563 Ops.push_back(Callee);
565 // Add argument registers to the end of the list so that they are
566 // known live into the call.
567 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
568 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
569 RegsToPass[i].second.getValueType()));
572 if (InFlag.getNode()) {
573 Ops.push_back(InFlag);
577 return DAG.getNode(HexagonISD::TC_RETURN, dl, NodeTys, &Ops[0], Ops.size());
579 Chain = DAG.getNode(HexagonISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
580 InFlag = Chain.getValue(1);
582 // Create the CALLSEQ_END node.
583 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
584 DAG.getIntPtrConstant(0, true), InFlag);
585 InFlag = Chain.getValue(1);
587 // Handle result values, copying them out of physregs into vregs that we
589 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl, DAG,
590 InVals, OutVals, Callee);
593 static bool getIndexedAddressParts(SDNode *Ptr, EVT VT,
594 bool isSEXTLoad, SDValue &Base,
595 SDValue &Offset, bool &isInc,
597 if (Ptr->getOpcode() != ISD::ADD)
600 if (VT == MVT::i64 || VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) {
601 isInc = (Ptr->getOpcode() == ISD::ADD);
602 Base = Ptr->getOperand(0);
603 Offset = Ptr->getOperand(1);
604 // Ensure that Offset is a constant.
605 return (isa<ConstantSDNode>(Offset));
611 // TODO: Put this function along with the other isS* functions in
612 // HexagonISelDAGToDAG.cpp into a common file. Or better still, use the
613 // functions defined in HexagonImmediates.td.
614 static bool Is_PostInc_S4_Offset(SDNode * S, int ShiftAmount) {
615 ConstantSDNode *N = cast<ConstantSDNode>(S);
617 // immS4 predicate - True if the immediate fits in a 4-bit sign extended.
619 int64_t v = (int64_t)N->getSExtValue();
621 if (ShiftAmount > 0) {
623 v = v >> ShiftAmount;
625 return (v <= 7) && (v >= -8) && (m == 0);
628 /// getPostIndexedAddressParts - returns true by value, base pointer and
629 /// offset pointer and addressing mode by reference if this node can be
630 /// combined with a load / store to form a post-indexed load / store.
631 bool HexagonTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
634 ISD::MemIndexedMode &AM,
635 SelectionDAG &DAG) const
639 bool isSEXTLoad = false;
641 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
642 VT = LD->getMemoryVT();
643 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
644 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
645 VT = ST->getMemoryVT();
646 if (ST->getValue().getValueType() == MVT::i64 && ST->isTruncatingStore()) {
654 bool isLegal = getIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
656 // ShiftAmount = number of left-shifted bits in the Hexagon instruction.
657 int ShiftAmount = VT.getSizeInBits() / 16;
658 if (isLegal && Is_PostInc_S4_Offset(Offset.getNode(), ShiftAmount)) {
659 AM = isInc ? ISD::POST_INC : ISD::POST_DEC;
666 SDValue HexagonTargetLowering::LowerINLINEASM(SDValue Op,
667 SelectionDAG &DAG) const {
668 SDNode *Node = Op.getNode();
669 MachineFunction &MF = DAG.getMachineFunction();
670 HexagonMachineFunctionInfo *FuncInfo =
671 MF.getInfo<HexagonMachineFunctionInfo>();
672 switch (Node->getOpcode()) {
673 case ISD::INLINEASM: {
674 unsigned NumOps = Node->getNumOperands();
675 if (Node->getOperand(NumOps-1).getValueType() == MVT::Glue)
676 --NumOps; // Ignore the flag operand.
678 for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
679 if (FuncInfo->hasClobberLR())
682 cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue();
683 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
684 ++i; // Skip the ID value.
686 switch (InlineAsm::getKind(Flags)) {
687 default: llvm_unreachable("Bad flags!");
688 case InlineAsm::Kind_RegDef:
689 case InlineAsm::Kind_RegUse:
690 case InlineAsm::Kind_Imm:
691 case InlineAsm::Kind_Clobber:
692 case InlineAsm::Kind_Mem: {
693 for (; NumVals; --NumVals, ++i) {}
696 case InlineAsm::Kind_RegDefEarlyClobber: {
697 for (; NumVals; --NumVals, ++i) {
699 cast<RegisterSDNode>(Node->getOperand(i))->getReg();
702 if (Reg == TM.getRegisterInfo()->getRARegister()) {
703 FuncInfo->setHasClobberLR(true);
718 // Taken from the XCore backend.
720 SDValue HexagonTargetLowering::
721 LowerBR_JT(SDValue Op, SelectionDAG &DAG) const
723 SDValue Chain = Op.getOperand(0);
724 SDValue Table = Op.getOperand(1);
725 SDValue Index = Op.getOperand(2);
726 DebugLoc dl = Op.getDebugLoc();
727 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
728 unsigned JTI = JT->getIndex();
729 MachineFunction &MF = DAG.getMachineFunction();
730 const MachineJumpTableInfo *MJTI = MF.getJumpTableInfo();
731 SDValue TargetJT = DAG.getTargetJumpTable(JT->getIndex(), MVT::i32);
733 // Mark all jump table targets as address taken.
734 const std::vector<MachineJumpTableEntry> &JTE = MJTI->getJumpTables();
735 const std::vector<MachineBasicBlock*> &JTBBs = JTE[JTI].MBBs;
736 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
737 MachineBasicBlock *MBB = JTBBs[i];
738 MBB->setHasAddressTaken();
739 // This line is needed to set the hasAddressTaken flag on the BasicBlock
741 BlockAddress::get(const_cast<BasicBlock *>(MBB->getBasicBlock()));
744 SDValue JumpTableBase = DAG.getNode(HexagonISD::WrapperJT, dl,
745 getPointerTy(), TargetJT);
746 SDValue ShiftIndex = DAG.getNode(ISD::SHL, dl, MVT::i32, Index,
747 DAG.getConstant(2, MVT::i32));
748 SDValue JTAddress = DAG.getNode(ISD::ADD, dl, MVT::i32, JumpTableBase,
750 SDValue LoadTarget = DAG.getLoad(MVT::i32, dl, Chain, JTAddress,
751 MachinePointerInfo(), false, false, false,
753 return DAG.getNode(HexagonISD::BR_JT, dl, MVT::Other, Chain, LoadTarget);
758 HexagonTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
759 SelectionDAG &DAG) const {
760 SDValue Chain = Op.getOperand(0);
761 SDValue Size = Op.getOperand(1);
762 DebugLoc dl = Op.getDebugLoc();
764 unsigned SPReg = getStackPointerRegisterToSaveRestore();
766 // Get a reference to the stack pointer.
767 SDValue StackPointer = DAG.getCopyFromReg(Chain, dl, SPReg, MVT::i32);
769 // Subtract the dynamic size from the actual stack size to
770 // obtain the new stack size.
771 SDValue Sub = DAG.getNode(ISD::SUB, dl, MVT::i32, StackPointer, Size);
774 // For Hexagon, the outgoing memory arguments area should be on top of the
775 // alloca area on the stack i.e., the outgoing memory arguments should be
776 // at a lower address than the alloca area. Move the alloca area down the
777 // stack by adding back the space reserved for outgoing arguments to SP
780 // We do not know what the size of the outgoing args is at this point.
781 // So, we add a pseudo instruction ADJDYNALLOC that will adjust the
782 // stack pointer. We patch this instruction with the correct, known
783 // offset in emitPrologue().
785 // Use a placeholder immediate (zero) for now. This will be patched up
786 // by emitPrologue().
787 SDValue ArgAdjust = DAG.getNode(HexagonISD::ADJDYNALLOC, dl,
790 DAG.getConstant(0, MVT::i32));
792 // The Sub result contains the new stack start address, so it
793 // must be placed in the stack pointer register.
794 SDValue CopyChain = DAG.getCopyToReg(Chain, dl,
795 TM.getRegisterInfo()->getStackRegister(),
798 SDValue Ops[2] = { ArgAdjust, CopyChain };
799 return DAG.getMergeValues(Ops, 2, dl);
803 HexagonTargetLowering::LowerFormalArguments(SDValue Chain,
804 CallingConv::ID CallConv,
807 SmallVectorImpl<ISD::InputArg> &Ins,
808 DebugLoc dl, SelectionDAG &DAG,
809 SmallVectorImpl<SDValue> &InVals)
812 MachineFunction &MF = DAG.getMachineFunction();
813 MachineFrameInfo *MFI = MF.getFrameInfo();
814 MachineRegisterInfo &RegInfo = MF.getRegInfo();
815 HexagonMachineFunctionInfo *FuncInfo =
816 MF.getInfo<HexagonMachineFunctionInfo>();
819 // Assign locations to all of the incoming arguments.
820 SmallVector<CCValAssign, 16> ArgLocs;
821 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
822 getTargetMachine(), ArgLocs, *DAG.getContext());
824 CCInfo.AnalyzeFormalArguments(Ins, CC_Hexagon);
826 // For LLVM, in the case when returning a struct by value (>8byte),
827 // the first argument is a pointer that points to the location on caller's
828 // stack where the return value will be stored. For Hexagon, the location on
829 // caller's stack is passed only when the struct size is smaller than (and
830 // equal to) 8 bytes. If not, no address will be passed into callee and
831 // callee return the result direclty through R0/R1.
833 SmallVector<SDValue, 4> MemOps;
835 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
836 CCValAssign &VA = ArgLocs[i];
837 ISD::ArgFlagsTy Flags = Ins[i].Flags;
839 unsigned StackLocation;
842 if ( (VA.isRegLoc() && !Flags.isByVal())
843 || (VA.isRegLoc() && Flags.isByVal() && Flags.getByValSize() > 8)) {
844 // Arguments passed in registers
845 // 1. int, long long, ptr args that get allocated in register.
846 // 2. Large struct that gets an register to put its address in.
847 EVT RegVT = VA.getLocVT();
848 if (RegVT == MVT::i8 || RegVT == MVT::i16 || RegVT == MVT::i32) {
850 RegInfo.createVirtualRegister(Hexagon::IntRegsRegisterClass);
851 RegInfo.addLiveIn(VA.getLocReg(), VReg);
852 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
853 } else if (RegVT == MVT::i64) {
855 RegInfo.createVirtualRegister(Hexagon::DoubleRegsRegisterClass);
856 RegInfo.addLiveIn(VA.getLocReg(), VReg);
857 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
861 } else if (VA.isRegLoc() && Flags.isByVal() && Flags.getByValSize() <= 8) {
862 assert (0 && "ByValSize must be bigger than 8 bytes");
865 assert(VA.isMemLoc());
867 if (Flags.isByVal()) {
868 // If it's a byval parameter, then we need to compute the
869 // "real" size, not the size of the pointer.
870 ObjSize = Flags.getByValSize();
872 ObjSize = VA.getLocVT().getStoreSizeInBits() >> 3;
875 StackLocation = HEXAGON_LRFP_SIZE + VA.getLocMemOffset();
876 // Create the frame index object for this incoming parameter...
877 FI = MFI->CreateFixedObject(ObjSize, StackLocation, true);
879 // Create the SelectionDAG nodes cordl, responding to a load
880 // from this parameter.
881 SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
883 if (Flags.isByVal()) {
884 // If it's a pass-by-value aggregate, then do not dereference the stack
885 // location. Instead, we should generate a reference to the stack
887 InVals.push_back(FIN);
889 InVals.push_back(DAG.getLoad(VA.getLocVT(), dl, Chain, FIN,
890 MachinePointerInfo(), false, false,
897 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &MemOps[0],
901 // This will point to the next argument passed via stack.
902 int FrameIndex = MFI->CreateFixedObject(Hexagon_PointerSize,
904 CCInfo.getNextStackOffset(),
906 FuncInfo->setVarArgsFrameIndex(FrameIndex);
913 HexagonTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
914 // VASTART stores the address of the VarArgsFrameIndex slot into the
915 // memory location argument.
916 MachineFunction &MF = DAG.getMachineFunction();
917 HexagonMachineFunctionInfo *QFI = MF.getInfo<HexagonMachineFunctionInfo>();
918 SDValue Addr = DAG.getFrameIndex(QFI->getVarArgsFrameIndex(), MVT::i32);
919 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
920 return DAG.getStore(Op.getOperand(0), Op.getDebugLoc(), Addr,
921 Op.getOperand(1), MachinePointerInfo(SV), false,
926 HexagonTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
927 SDNode* OpNode = Op.getNode();
929 SDValue Cond = DAG.getNode(ISD::SETCC, Op.getDebugLoc(), MVT::i1,
930 Op.getOperand(2), Op.getOperand(3),
932 return DAG.getNode(ISD::SELECT, Op.getDebugLoc(), OpNode->getValueType(0),
933 Cond, Op.getOperand(0),
938 HexagonTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const {
939 const TargetRegisterInfo *TRI = TM.getRegisterInfo();
940 MachineFunction &MF = DAG.getMachineFunction();
941 MachineFrameInfo *MFI = MF.getFrameInfo();
942 MFI->setReturnAddressIsTaken(true);
944 EVT VT = Op.getValueType();
945 DebugLoc dl = Op.getDebugLoc();
946 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
948 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
949 SDValue Offset = DAG.getConstant(4, MVT::i32);
950 return DAG.getLoad(VT, dl, DAG.getEntryNode(),
951 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
952 MachinePointerInfo(), false, false, false, 0);
955 // Return LR, which contains the return address. Mark it an implicit live-in.
956 unsigned Reg = MF.addLiveIn(TRI->getRARegister(), getRegClassFor(MVT::i32));
957 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
961 HexagonTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
962 const HexagonRegisterInfo *TRI = TM.getRegisterInfo();
963 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
964 MFI->setFrameAddressIsTaken(true);
966 EVT VT = Op.getValueType();
967 DebugLoc dl = Op.getDebugLoc();
968 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
969 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
970 TRI->getFrameRegister(), VT);
972 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
973 MachinePointerInfo(),
974 false, false, false, 0);
979 SDValue HexagonTargetLowering::LowerMEMBARRIER(SDValue Op,
980 SelectionDAG& DAG) const {
981 DebugLoc dl = Op.getDebugLoc();
982 return DAG.getNode(HexagonISD::BARRIER, dl, MVT::Other, Op.getOperand(0));
986 SDValue HexagonTargetLowering::LowerATOMIC_FENCE(SDValue Op,
987 SelectionDAG& DAG) const {
988 DebugLoc dl = Op.getDebugLoc();
989 return DAG.getNode(HexagonISD::BARRIER, dl, MVT::Other, Op.getOperand(0));
993 SDValue HexagonTargetLowering::LowerGLOBALADDRESS(SDValue Op,
994 SelectionDAG &DAG) const {
996 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
997 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
998 DebugLoc dl = Op.getDebugLoc();
999 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
1001 HexagonTargetObjectFile &TLOF =
1002 (HexagonTargetObjectFile&)getObjFileLowering();
1003 if (TLOF.IsGlobalInSmallSection(GV, getTargetMachine())) {
1004 return DAG.getNode(HexagonISD::CONST32_GP, dl, getPointerTy(), Result);
1007 return DAG.getNode(HexagonISD::CONST32, dl, getPointerTy(), Result);
1010 //===----------------------------------------------------------------------===//
1011 // TargetLowering Implementation
1012 //===----------------------------------------------------------------------===//
1014 HexagonTargetLowering::HexagonTargetLowering(HexagonTargetMachine
1016 : TargetLowering(targetmachine, new HexagonTargetObjectFile()),
1019 // Set up the register classes.
1020 addRegisterClass(MVT::i32, Hexagon::IntRegsRegisterClass);
1021 addRegisterClass(MVT::i64, Hexagon::DoubleRegsRegisterClass);
1023 addRegisterClass(MVT::i1, Hexagon::PredRegsRegisterClass);
1025 computeRegisterProperties();
1028 setPrefLoopAlignment(4);
1030 // Limits for inline expansion of memcpy/memmove
1031 maxStoresPerMemcpy = 6;
1032 maxStoresPerMemmove = 6;
1035 // Library calls for unsupported operations
1037 setLibcallName(RTLIB::OGT_F64, "__hexagon_gtdf2");
1039 setLibcallName(RTLIB::SINTTOFP_I64_F64, "__hexagon_floatdidf");
1040 setLibcallName(RTLIB::SINTTOFP_I128_F64, "__hexagon_floattidf");
1041 setLibcallName(RTLIB::SINTTOFP_I128_F32, "__hexagon_floattisf");
1042 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__hexagon_floatunsisf");
1043 setLibcallName(RTLIB::UINTTOFP_I64_F32, "__hexagon_floatundisf");
1044 setLibcallName(RTLIB::SINTTOFP_I64_F32, "__hexagon_floatdisf");
1045 setLibcallName(RTLIB::UINTTOFP_I64_F64, "__hexagon_floatundidf");
1047 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__hexagon_fixunssfsi");
1048 setLibcallName(RTLIB::FPTOUINT_F32_I64, "__hexagon_fixunssfdi");
1049 setLibcallName(RTLIB::FPTOUINT_F32_I128, "__hexagon_fixunssfti");
1051 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__hexagon_fixunsdfsi");
1052 setLibcallName(RTLIB::FPTOUINT_F64_I64, "__hexagon_fixunsdfdi");
1053 setLibcallName(RTLIB::FPTOUINT_F64_I128, "__hexagon_fixunsdfti");
1055 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__hexagon_floatunsidf");
1056 setLibcallName(RTLIB::FPTOSINT_F32_I64, "__hexagon_fixsfdi");
1057 setLibcallName(RTLIB::FPTOSINT_F32_I128, "__hexagon_fixsfti");
1058 setLibcallName(RTLIB::FPTOSINT_F64_I64, "__hexagon_fixdfdi");
1059 setLibcallName(RTLIB::FPTOSINT_F64_I128, "__hexagon_fixdfti");
1061 setLibcallName(RTLIB::OGT_F64, "__hexagon_gtdf2");
1063 setLibcallName(RTLIB::SDIV_I32, "__hexagon_divsi3");
1064 setOperationAction(ISD::SDIV, MVT::i32, Expand);
1065 setLibcallName(RTLIB::SREM_I32, "__hexagon_umodsi3");
1066 setOperationAction(ISD::SREM, MVT::i32, Expand);
1068 setLibcallName(RTLIB::SDIV_I64, "__hexagon_divdi3");
1069 setOperationAction(ISD::SDIV, MVT::i64, Expand);
1070 setLibcallName(RTLIB::SREM_I64, "__hexagon_moddi3");
1071 setOperationAction(ISD::SREM, MVT::i64, Expand);
1073 setLibcallName(RTLIB::UDIV_I32, "__hexagon_udivsi3");
1074 setOperationAction(ISD::UDIV, MVT::i32, Expand);
1076 setLibcallName(RTLIB::UDIV_I64, "__hexagon_udivdi3");
1077 setOperationAction(ISD::UDIV, MVT::i64, Expand);
1079 setLibcallName(RTLIB::UREM_I32, "__hexagon_umodsi3");
1080 setOperationAction(ISD::UREM, MVT::i32, Expand);
1082 setLibcallName(RTLIB::UREM_I64, "__hexagon_umoddi3");
1083 setOperationAction(ISD::UREM, MVT::i64, Expand);
1085 setLibcallName(RTLIB::DIV_F32, "__hexagon_divsf3");
1086 setOperationAction(ISD::FDIV, MVT::f32, Expand);
1088 setLibcallName(RTLIB::DIV_F64, "__hexagon_divdf3");
1089 setOperationAction(ISD::FDIV, MVT::f64, Expand);
1091 setLibcallName(RTLIB::FPEXT_F32_F64, "__hexagon_extendsfdf2");
1092 setOperationAction(ISD::FP_EXTEND, MVT::f32, Expand);
1094 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__hexagon_floatsisf");
1095 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
1097 setLibcallName(RTLIB::ADD_F64, "__hexagon_adddf3");
1098 setOperationAction(ISD::FADD, MVT::f64, Expand);
1100 setLibcallName(RTLIB::ADD_F32, "__hexagon_addsf3");
1101 setOperationAction(ISD::FADD, MVT::f32, Expand);
1103 setLibcallName(RTLIB::ADD_F32, "__hexagon_addsf3");
1104 setOperationAction(ISD::FADD, MVT::f32, Expand);
1106 setLibcallName(RTLIB::OEQ_F32, "__hexagon_eqsf2");
1107 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
1109 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__hexagon_fixdfsi");
1110 setOperationAction(ISD::FP_TO_SINT, MVT::f64, Expand);
1112 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__hexagon_fixsfsi");
1113 setOperationAction(ISD::FP_TO_SINT, MVT::f32, Expand);
1115 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__hexagon_floatsidf");
1116 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
1118 setLibcallName(RTLIB::OGE_F64, "__hexagon_gedf2");
1119 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
1121 setLibcallName(RTLIB::OGE_F32, "__hexagon_gesf2");
1122 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
1124 setLibcallName(RTLIB::OGT_F32, "__hexagon_gtsf2");
1125 setCondCodeAction(ISD::SETOGT, MVT::f32, Expand);
1127 setLibcallName(RTLIB::OLE_F64, "__hexagon_ledf2");
1128 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
1130 setLibcallName(RTLIB::OLE_F32, "__hexagon_lesf2");
1131 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
1133 setLibcallName(RTLIB::OLT_F64, "__hexagon_ltdf2");
1134 setCondCodeAction(ISD::SETOLT, MVT::f64, Expand);
1136 setLibcallName(RTLIB::OLT_F32, "__hexagon_ltsf2");
1137 setCondCodeAction(ISD::SETOLT, MVT::f32, Expand);
1139 setLibcallName(RTLIB::SREM_I32, "__hexagon_modsi3");
1140 setOperationAction(ISD::SREM, MVT::i32, Expand);
1142 setLibcallName(RTLIB::MUL_F64, "__hexagon_muldf3");
1143 setOperationAction(ISD::FMUL, MVT::f64, Expand);
1145 setLibcallName(RTLIB::MUL_F32, "__hexagon_mulsf3");
1146 setOperationAction(ISD::MUL, MVT::f32, Expand);
1148 setLibcallName(RTLIB::UNE_F64, "__hexagon_nedf2");
1149 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
1151 setLibcallName(RTLIB::UNE_F32, "__hexagon_nesf2");
1154 setLibcallName(RTLIB::SUB_F64, "__hexagon_subdf3");
1155 setOperationAction(ISD::SUB, MVT::f64, Expand);
1157 setLibcallName(RTLIB::SUB_F32, "__hexagon_subsf3");
1158 setOperationAction(ISD::SUB, MVT::f32, Expand);
1160 setLibcallName(RTLIB::FPROUND_F64_F32, "__hexagon_truncdfsf2");
1161 setOperationAction(ISD::FP_ROUND, MVT::f64, Expand);
1163 setLibcallName(RTLIB::UO_F64, "__hexagon_unorddf2");
1164 setCondCodeAction(ISD::SETUO, MVT::f64, Expand);
1166 setLibcallName(RTLIB::O_F64, "__hexagon_unorddf2");
1167 setCondCodeAction(ISD::SETO, MVT::f64, Expand);
1169 setLibcallName(RTLIB::OEQ_F64, "__hexagon_eqdf2");
1170 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
1172 setLibcallName(RTLIB::O_F32, "__hexagon_unordsf2");
1173 setCondCodeAction(ISD::SETO, MVT::f32, Expand);
1175 setLibcallName(RTLIB::UO_F32, "__hexagon_unordsf2");
1176 setCondCodeAction(ISD::SETUO, MVT::f32, Expand);
1178 setIndexedLoadAction(ISD::POST_INC, MVT::i8, Legal);
1179 setIndexedLoadAction(ISD::POST_INC, MVT::i16, Legal);
1180 setIndexedLoadAction(ISD::POST_INC, MVT::i32, Legal);
1181 setIndexedLoadAction(ISD::POST_INC, MVT::i64, Legal);
1183 setIndexedStoreAction(ISD::POST_INC, MVT::i8, Legal);
1184 setIndexedStoreAction(ISD::POST_INC, MVT::i16, Legal);
1185 setIndexedStoreAction(ISD::POST_INC, MVT::i32, Legal);
1186 setIndexedStoreAction(ISD::POST_INC, MVT::i64, Legal);
1188 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
1190 // Turn FP extload into load/fextend.
1191 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
1192 // Hexagon has a i1 sign extending load.
1193 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Expand);
1194 // Turn FP truncstore into trunc + store.
1195 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
1197 // Custom legalize GlobalAddress nodes into CONST32.
1198 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
1199 setOperationAction(ISD::GlobalAddress, MVT::i8, Custom);
1201 setOperationAction(ISD::TRUNCATE, MVT::i64, Expand);
1203 // Hexagon doesn't have sext_inreg, replace them with shl/sra.
1204 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
1206 // Hexagon has no REM or DIVREM operations.
1207 setOperationAction(ISD::UREM, MVT::i32, Expand);
1208 setOperationAction(ISD::SREM, MVT::i32, Expand);
1209 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
1210 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
1211 setOperationAction(ISD::SREM, MVT::i64, Expand);
1212 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
1213 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
1215 setOperationAction(ISD::BSWAP, MVT::i64, Expand);
1217 // Expand fp<->uint.
1218 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
1219 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
1221 // Hexagon has no select or setcc: expand to SELECT_CC.
1222 setOperationAction(ISD::SELECT, MVT::f32, Expand);
1223 setOperationAction(ISD::SELECT, MVT::f64, Expand);
1225 // Lower SELECT_CC to SETCC and SELECT.
1226 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
1227 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom);
1228 // This is a workaround documented in DAGCombiner.cpp:2892 We don't
1229 // support SELECT_CC on every type.
1230 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
1232 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
1233 setOperationAction(ISD::BRIND, MVT::Other, Expand);
1234 if (EmitJumpTables) {
1235 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
1237 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
1240 setOperationAction(ISD::BR_CC, MVT::i32, Expand);
1242 setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom);
1243 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
1245 setOperationAction(ISD::FSIN , MVT::f64, Expand);
1246 setOperationAction(ISD::FCOS , MVT::f64, Expand);
1247 setOperationAction(ISD::FREM , MVT::f64, Expand);
1248 setOperationAction(ISD::FSIN , MVT::f32, Expand);
1249 setOperationAction(ISD::FCOS , MVT::f32, Expand);
1250 setOperationAction(ISD::FREM , MVT::f32, Expand);
1251 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
1252 setOperationAction(ISD::CTTZ , MVT::i32, Expand);
1253 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
1254 setOperationAction(ISD::CTLZ , MVT::i32, Expand);
1255 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
1256 setOperationAction(ISD::ROTL , MVT::i32, Expand);
1257 setOperationAction(ISD::ROTR , MVT::i32, Expand);
1258 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
1259 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
1260 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
1261 setOperationAction(ISD::FPOW , MVT::f64, Expand);
1262 setOperationAction(ISD::FPOW , MVT::f32, Expand);
1264 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
1265 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
1266 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
1268 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
1269 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
1271 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
1272 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
1274 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
1275 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
1276 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
1277 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
1279 setOperationAction(ISD::EH_RETURN, MVT::Other, Expand);
1281 if (TM.getSubtargetImpl()->isSubtargetV2()) {
1282 setExceptionPointerRegister(Hexagon::R20);
1283 setExceptionSelectorRegister(Hexagon::R21);
1285 setExceptionPointerRegister(Hexagon::R0);
1286 setExceptionSelectorRegister(Hexagon::R1);
1289 // VASTART needs to be custom lowered to use the VarArgsFrameIndex.
1290 setOperationAction(ISD::VASTART , MVT::Other, Custom);
1292 // Use the default implementation.
1293 setOperationAction(ISD::VAARG , MVT::Other, Expand);
1294 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
1295 setOperationAction(ISD::VAEND , MVT::Other, Expand);
1296 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
1297 setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand);
1300 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
1301 setOperationAction(ISD::INLINEASM , MVT::Other, Custom);
1303 setMinFunctionAlignment(2);
1305 // Needed for DYNAMIC_STACKALLOC expansion.
1306 unsigned StackRegister = TM.getRegisterInfo()->getStackRegister();
1307 setStackPointerRegisterToSaveRestore(StackRegister);
1312 HexagonTargetLowering::getTargetNodeName(unsigned Opcode) const {
1315 case HexagonISD::CONST32: return "HexagonISD::CONST32";
1316 case HexagonISD::ADJDYNALLOC: return "HexagonISD::ADJDYNALLOC";
1317 case HexagonISD::CMPICC: return "HexagonISD::CMPICC";
1318 case HexagonISD::CMPFCC: return "HexagonISD::CMPFCC";
1319 case HexagonISD::BRICC: return "HexagonISD::BRICC";
1320 case HexagonISD::BRFCC: return "HexagonISD::BRFCC";
1321 case HexagonISD::SELECT_ICC: return "HexagonISD::SELECT_ICC";
1322 case HexagonISD::SELECT_FCC: return "HexagonISD::SELECT_FCC";
1323 case HexagonISD::Hi: return "HexagonISD::Hi";
1324 case HexagonISD::Lo: return "HexagonISD::Lo";
1325 case HexagonISD::FTOI: return "HexagonISD::FTOI";
1326 case HexagonISD::ITOF: return "HexagonISD::ITOF";
1327 case HexagonISD::CALL: return "HexagonISD::CALL";
1328 case HexagonISD::RET_FLAG: return "HexagonISD::RET_FLAG";
1329 case HexagonISD::BR_JT: return "HexagonISD::BR_JT";
1330 case HexagonISD::TC_RETURN: return "HexagonISD::TC_RETURN";
1335 HexagonTargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
1336 EVT MTy1 = EVT::getEVT(Ty1);
1337 EVT MTy2 = EVT::getEVT(Ty2);
1338 if (!MTy1.isSimple() || !MTy2.isSimple()) {
1341 return ((MTy1.getSimpleVT() == MVT::i64) && (MTy2.getSimpleVT() == MVT::i32));
1344 bool HexagonTargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
1345 if (!VT1.isSimple() || !VT2.isSimple()) {
1348 return ((VT1.getSimpleVT() == MVT::i64) && (VT2.getSimpleVT() == MVT::i32));
1352 HexagonTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
1353 switch (Op.getOpcode()) {
1354 default: assert(0 && "Should not custom lower this!");
1355 // Frame & Return address. Currently unimplemented.
1356 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
1357 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
1358 case ISD::GlobalTLSAddress:
1359 assert(0 && "TLS not implemented for Hexagon.");
1360 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, DAG);
1361 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG);
1362 case ISD::GlobalAddress: return LowerGLOBALADDRESS(Op, DAG);
1363 case ISD::VASTART: return LowerVASTART(Op, DAG);
1364 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
1366 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
1367 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
1368 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
1369 case ISD::INLINEASM: return LowerINLINEASM(Op, DAG);
1376 //===----------------------------------------------------------------------===//
1377 // Hexagon Scheduler Hooks
1378 //===----------------------------------------------------------------------===//
1380 HexagonTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
1381 MachineBasicBlock *BB)
1383 switch (MI->getOpcode()) {
1384 case Hexagon::ADJDYNALLOC: {
1385 MachineFunction *MF = BB->getParent();
1386 HexagonMachineFunctionInfo *FuncInfo =
1387 MF->getInfo<HexagonMachineFunctionInfo>();
1388 FuncInfo->addAllocaAdjustInst(MI);
1392 assert(false && "Unexpected instr type to insert");
1397 //===----------------------------------------------------------------------===//
1398 // Inline Assembly Support
1399 //===----------------------------------------------------------------------===//
1401 std::pair<unsigned, const TargetRegisterClass*>
1402 HexagonTargetLowering::getRegForInlineAsmConstraint(const
1403 std::string &Constraint,
1405 if (Constraint.size() == 1) {
1406 switch (Constraint[0]) {
1408 switch (VT.getSimpleVT().SimpleTy) {
1410 assert(0 && "getRegForInlineAsmConstraint Unhandled data type");
1414 return std::make_pair(0U, Hexagon::IntRegsRegisterClass);
1416 return std::make_pair(0U, Hexagon::DoubleRegsRegisterClass);
1419 assert(0 && "Unknown asm register class");
1423 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
1426 /// isLegalAddressingMode - Return true if the addressing mode represented by
1427 /// AM is legal for this target, for a load/store of the specified type.
1428 bool HexagonTargetLowering::isLegalAddressingMode(const AddrMode &AM,
1430 // Allows a signed-extended 11-bit immediate field.
1431 if (AM.BaseOffs <= -(1LL << 13) || AM.BaseOffs >= (1LL << 13)-1) {
1435 // No global is ever allowed as a base.
1440 int Scale = AM.Scale;
1441 if (Scale < 0) Scale = -Scale;
1443 case 0: // No scale reg, "r+i", "r", or just "i".
1445 default: // No scaled addressing mode.
1451 /// isLegalICmpImmediate - Return true if the specified immediate is legal
1452 /// icmp immediate, that is the target has icmp instructions which can compare
1453 /// a register against the immediate without having to materialize the
1454 /// immediate into a register.
1455 bool HexagonTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
1456 return Imm >= -512 && Imm <= 511;
1459 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
1460 /// for tail call optimization. Targets which want to do tail call
1461 /// optimization should implement this function.
1462 bool HexagonTargetLowering::IsEligibleForTailCallOptimization(
1464 CallingConv::ID CalleeCC,
1466 bool isCalleeStructRet,
1467 bool isCallerStructRet,
1468 const SmallVectorImpl<ISD::OutputArg> &Outs,
1469 const SmallVectorImpl<SDValue> &OutVals,
1470 const SmallVectorImpl<ISD::InputArg> &Ins,
1471 SelectionDAG& DAG) const {
1472 const Function *CallerF = DAG.getMachineFunction().getFunction();
1473 CallingConv::ID CallerCC = CallerF->getCallingConv();
1474 bool CCMatch = CallerCC == CalleeCC;
1476 // ***************************************************************************
1477 // Look for obvious safe cases to perform tail call optimization that do not
1478 // require ABI changes.
1479 // ***************************************************************************
1481 // If this is a tail call via a function pointer, then don't do it!
1482 if (!(dyn_cast<GlobalAddressSDNode>(Callee))
1483 && !(dyn_cast<ExternalSymbolSDNode>(Callee))) {
1487 // Do not optimize if the calling conventions do not match.
1491 // Do not tail call optimize vararg calls.
1495 // Also avoid tail call optimization if either caller or callee uses struct
1496 // return semantics.
1497 if (isCalleeStructRet || isCallerStructRet)
1500 // In addition to the cases above, we also disable Tail Call Optimization if
1501 // the calling convention code that at least one outgoing argument needs to
1502 // go on the stack. We cannot check that here because at this point that
1503 // information is not available.