1 //===-- HexagonISelDAGToDAG.cpp - A dag to dag inst selector for Hexagon --===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the Hexagon target.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "hexagon-isel"
15 #include "HexagonISelLowering.h"
16 #include "HexagonTargetMachine.h"
17 #include "llvm/Intrinsics.h"
18 #include "llvm/CodeGen/SelectionDAGISel.h"
19 #include "llvm/Support/Compiler.h"
20 #include "llvm/Support/Debug.h"
25 //===----------------------------------------------------------------------===//
26 // Instruction Selector Implementation
27 //===----------------------------------------------------------------------===//
29 //===--------------------------------------------------------------------===//
30 /// HexagonDAGToDAGISel - Hexagon specific code to select Hexagon machine
31 /// instructions for SelectionDAG operations.
34 class HexagonDAGToDAGISel : public SelectionDAGISel {
35 /// Subtarget - Keep a pointer to the Hexagon Subtarget around so that we can
36 /// make the right decision when generating code for different targets.
37 const HexagonSubtarget &Subtarget;
39 // Keep a reference to HexagonTargetMachine.
40 HexagonTargetMachine& TM;
41 const HexagonInstrInfo *TII;
44 explicit HexagonDAGToDAGISel(HexagonTargetMachine &targetmachine)
45 : SelectionDAGISel(targetmachine),
46 Subtarget(targetmachine.getSubtarget<HexagonSubtarget>()),
48 TII(static_cast<const HexagonInstrInfo*>(TM.getInstrInfo())) {
52 SDNode *Select(SDNode *N);
54 // Complex Pattern Selectors.
55 bool SelectADDRri(SDValue& N, SDValue &R1, SDValue &R2);
56 bool SelectADDRriS11_0(SDValue& N, SDValue &R1, SDValue &R2);
57 bool SelectADDRriS11_1(SDValue& N, SDValue &R1, SDValue &R2);
58 bool SelectADDRriS11_2(SDValue& N, SDValue &R1, SDValue &R2);
59 bool SelectMEMriS11_2(SDValue& Addr, SDValue &Base, SDValue &Offset);
60 bool SelectADDRriS11_3(SDValue& N, SDValue &R1, SDValue &R2);
61 bool SelectADDRrr(SDValue &Addr, SDValue &Base, SDValue &Offset);
62 bool SelectADDRriU6_0(SDValue& N, SDValue &R1, SDValue &R2);
63 bool SelectADDRriU6_1(SDValue& N, SDValue &R1, SDValue &R2);
64 bool SelectADDRriU6_2(SDValue& N, SDValue &R1, SDValue &R2);
66 virtual const char *getPassName() const {
67 return "Hexagon DAG->DAG Pattern Instruction Selection";
70 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
71 /// inline asm expressions.
72 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
74 std::vector<SDValue> &OutOps);
75 bool SelectAddr(SDNode *Op, SDValue Addr, SDValue &Base, SDValue &Offset);
77 SDNode *SelectLoad(SDNode *N);
78 SDNode *SelectBaseOffsetLoad(LoadSDNode *LD, DebugLoc dl);
79 SDNode *SelectIndexedLoad(LoadSDNode *LD, DebugLoc dl);
80 SDNode *SelectIndexedLoadZeroExtend64(LoadSDNode *LD, unsigned Opcode,
82 SDNode *SelectIndexedLoadSignExtend64(LoadSDNode *LD, unsigned Opcode,
84 SDNode *SelectBaseOffsetStore(StoreSDNode *ST, DebugLoc dl);
85 SDNode *SelectIndexedStore(StoreSDNode *ST, DebugLoc dl);
86 SDNode *SelectStore(SDNode *N);
87 SDNode *SelectSHL(SDNode *N);
88 SDNode *SelectSelect(SDNode *N);
89 SDNode *SelectTruncate(SDNode *N);
90 SDNode *SelectMul(SDNode *N);
91 SDNode *SelectZeroExtend(SDNode *N);
92 SDNode *SelectIntrinsicWOChain(SDNode *N);
93 SDNode *SelectIntrinsicWChain(SDNode *N);
94 SDNode *SelectConstant(SDNode *N);
95 SDNode *SelectConstantFP(SDNode *N);
96 SDNode *SelectAdd(SDNode *N);
98 // Include the pieces autogenerated from the target description.
99 #include "HexagonGenDAGISel.inc"
101 } // end anonymous namespace
104 /// createHexagonISelDag - This pass converts a legalized DAG into a
105 /// Hexagon-specific DAG, ready for instruction scheduling.
107 FunctionPass *llvm::createHexagonISelDag(HexagonTargetMachine &TM) {
108 return new HexagonDAGToDAGISel(TM);
111 static bool IsS11_0_Offset(SDNode * S) {
112 ConstantSDNode *N = cast<ConstantSDNode>(S);
114 // immS16 predicate - True if the immediate fits in a 16-bit sign extended
116 int64_t v = (int64_t)N->getSExtValue();
121 static bool IsS11_1_Offset(SDNode * S) {
122 ConstantSDNode *N = cast<ConstantSDNode>(S);
124 // immS16 predicate - True if the immediate fits in a 16-bit sign extended
126 int64_t v = (int64_t)N->getSExtValue();
127 return isShiftedInt<11,1>(v);
131 static bool IsS11_2_Offset(SDNode * S) {
132 ConstantSDNode *N = cast<ConstantSDNode>(S);
134 // immS16 predicate - True if the immediate fits in a 16-bit sign extended
136 int64_t v = (int64_t)N->getSExtValue();
137 return isShiftedInt<11,2>(v);
141 static bool IsS11_3_Offset(SDNode * S) {
142 ConstantSDNode *N = cast<ConstantSDNode>(S);
144 // immS16 predicate - True if the immediate fits in a 16-bit sign extended
146 int64_t v = (int64_t)N->getSExtValue();
147 return isShiftedInt<11,3>(v);
151 static bool IsU6_0_Offset(SDNode * S) {
152 ConstantSDNode *N = cast<ConstantSDNode>(S);
154 // u6 predicate - True if the immediate fits in a 6-bit unsigned extended
156 int64_t v = (int64_t)N->getSExtValue();
161 static bool IsU6_1_Offset(SDNode * S) {
162 ConstantSDNode *N = cast<ConstantSDNode>(S);
164 // u6 predicate - True if the immediate fits in a 6-bit unsigned extended
166 int64_t v = (int64_t)N->getSExtValue();
167 return isShiftedUInt<6,1>(v);
171 static bool IsU6_2_Offset(SDNode * S) {
172 ConstantSDNode *N = cast<ConstantSDNode>(S);
174 // u6 predicate - True if the immediate fits in a 6-bit unsigned extended
176 int64_t v = (int64_t)N->getSExtValue();
177 return isShiftedUInt<6,2>(v);
181 // Intrinsics that return a a predicate.
182 static unsigned doesIntrinsicReturnPredicate(unsigned ID)
187 case Intrinsic::hexagon_C2_cmpeq:
188 case Intrinsic::hexagon_C2_cmpgt:
189 case Intrinsic::hexagon_C2_cmpgtu:
190 case Intrinsic::hexagon_C2_cmpgtup:
191 case Intrinsic::hexagon_C2_cmpgtp:
192 case Intrinsic::hexagon_C2_cmpeqp:
193 case Intrinsic::hexagon_C2_bitsset:
194 case Intrinsic::hexagon_C2_bitsclr:
195 case Intrinsic::hexagon_C2_cmpeqi:
196 case Intrinsic::hexagon_C2_cmpgti:
197 case Intrinsic::hexagon_C2_cmpgtui:
198 case Intrinsic::hexagon_C2_cmpgei:
199 case Intrinsic::hexagon_C2_cmpgeui:
200 case Intrinsic::hexagon_C2_cmplt:
201 case Intrinsic::hexagon_C2_cmpltu:
202 case Intrinsic::hexagon_C2_bitsclri:
203 case Intrinsic::hexagon_C2_and:
204 case Intrinsic::hexagon_C2_or:
205 case Intrinsic::hexagon_C2_xor:
206 case Intrinsic::hexagon_C2_andn:
207 case Intrinsic::hexagon_C2_not:
208 case Intrinsic::hexagon_C2_orn:
209 case Intrinsic::hexagon_C2_pxfer_map:
210 case Intrinsic::hexagon_C2_any8:
211 case Intrinsic::hexagon_C2_all8:
212 case Intrinsic::hexagon_A2_vcmpbeq:
213 case Intrinsic::hexagon_A2_vcmpbgtu:
214 case Intrinsic::hexagon_A2_vcmpheq:
215 case Intrinsic::hexagon_A2_vcmphgt:
216 case Intrinsic::hexagon_A2_vcmphgtu:
217 case Intrinsic::hexagon_A2_vcmpweq:
218 case Intrinsic::hexagon_A2_vcmpwgt:
219 case Intrinsic::hexagon_A2_vcmpwgtu:
220 case Intrinsic::hexagon_C2_tfrrp:
221 case Intrinsic::hexagon_S2_tstbit_i:
222 case Intrinsic::hexagon_S2_tstbit_r:
228 // Intrinsics that have predicate operands.
229 static unsigned doesIntrinsicContainPredicate(unsigned ID)
234 case Intrinsic::hexagon_C2_tfrpr:
235 return Hexagon::TFR_RsPd;
236 case Intrinsic::hexagon_C2_and:
237 return Hexagon::AND_pp;
238 case Intrinsic::hexagon_C2_xor:
239 return Hexagon::XOR_pp;
240 case Intrinsic::hexagon_C2_or:
241 return Hexagon::OR_pp;
242 case Intrinsic::hexagon_C2_not:
243 return Hexagon::NOT_p;
244 case Intrinsic::hexagon_C2_any8:
245 return Hexagon::ANY_pp;
246 case Intrinsic::hexagon_C2_all8:
247 return Hexagon::ALL_pp;
248 case Intrinsic::hexagon_C2_vitpack:
249 return Hexagon::VITPACK_pp;
250 case Intrinsic::hexagon_C2_mask:
251 return Hexagon::MASK_p;
252 case Intrinsic::hexagon_C2_mux:
253 return Hexagon::MUX_rr;
255 // Mapping hexagon_C2_muxir to MUX_pri. This is pretty weird - but
256 // that's how it's mapped in q6protos.h.
257 case Intrinsic::hexagon_C2_muxir:
258 return Hexagon::MUX_ri;
260 // Mapping hexagon_C2_muxri to MUX_pir. This is pretty weird - but
261 // that's how it's mapped in q6protos.h.
262 case Intrinsic::hexagon_C2_muxri:
263 return Hexagon::MUX_ir;
265 case Intrinsic::hexagon_C2_muxii:
266 return Hexagon::MUX_ii;
267 case Intrinsic::hexagon_C2_vmux:
268 return Hexagon::VMUX_prr64;
269 case Intrinsic::hexagon_S2_valignrb:
270 return Hexagon::VALIGN_rrp;
271 case Intrinsic::hexagon_S2_vsplicerb:
272 return Hexagon::VSPLICE_rrp;
277 static bool OffsetFitsS11(EVT MemType, int64_t Offset) {
278 if (MemType == MVT::i64 && isShiftedInt<11,3>(Offset)) {
281 if (MemType == MVT::i32 && isShiftedInt<11,2>(Offset)) {
284 if (MemType == MVT::i16 && isShiftedInt<11,1>(Offset)) {
287 if (MemType == MVT::i8 && isInt<11>(Offset)) {
295 // Try to lower loads of GlobalAdresses into base+offset loads. Custom
296 // lowering for GlobalAddress nodes has already turned it into a
299 SDNode *HexagonDAGToDAGISel::SelectBaseOffsetLoad(LoadSDNode *LD, DebugLoc dl) {
300 SDValue Chain = LD->getChain();
301 SDNode* Const32 = LD->getBasePtr().getNode();
304 if (Const32->getOpcode() == HexagonISD::CONST32 &&
305 ISD::isNormalLoad(LD)) {
306 SDValue Base = Const32->getOperand(0);
307 EVT LoadedVT = LD->getMemoryVT();
308 int64_t Offset = cast<GlobalAddressSDNode>(Base)->getOffset();
309 if (Offset != 0 && OffsetFitsS11(LoadedVT, Offset)) {
310 MVT PointerTy = TLI.getPointerTy();
311 const GlobalValue* GV =
312 cast<GlobalAddressSDNode>(Base)->getGlobal();
314 CurDAG->getTargetGlobalAddress(GV, dl, PointerTy, 0);
315 SDNode* NewBase = CurDAG->getMachineNode(Hexagon::CONST32_set,
318 // Figure out base + offset opcode
319 if (LoadedVT == MVT::i64) Opcode = Hexagon::LDrid_indexed;
320 else if (LoadedVT == MVT::i32) Opcode = Hexagon::LDriw_indexed;
321 else if (LoadedVT == MVT::i16) Opcode = Hexagon::LDrih_indexed;
322 else if (LoadedVT == MVT::i8) Opcode = Hexagon::LDrib_indexed;
323 else if (LoadedVT == MVT::f32) Opcode = Hexagon::LDriw_indexed_f;
324 else if (LoadedVT == MVT::f64) Opcode = Hexagon::LDrid_indexed_f;
325 else assert (0 && "unknown memory type");
327 // Build indexed load.
328 SDValue TargetConstOff = CurDAG->getTargetConstant(Offset, PointerTy);
329 SDNode* Result = CurDAG->getMachineNode(Opcode, dl,
335 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
336 MemOp[0] = LD->getMemOperand();
337 cast<MachineSDNode>(Result)->setMemRefs(MemOp, MemOp + 1);
338 ReplaceUses(LD, Result);
343 return SelectCode(LD);
347 SDNode *HexagonDAGToDAGISel::SelectIndexedLoadSignExtend64(LoadSDNode *LD,
351 SDValue Chain = LD->getChain();
352 EVT LoadedVT = LD->getMemoryVT();
353 SDValue Base = LD->getBasePtr();
354 SDValue Offset = LD->getOffset();
355 SDNode *OffsetNode = Offset.getNode();
356 int32_t Val = cast<ConstantSDNode>(OffsetNode)->getSExtValue();
357 SDValue N1 = LD->getOperand(1);
360 if (SelectADDRriS11_2(N1, CPTmpN1_0, CPTmpN1_1) &&
361 N1.getNode()->getValueType(0) == MVT::i32) {
362 if (TII->isValidAutoIncImm(LoadedVT, Val)) {
363 SDValue TargetConst = CurDAG->getTargetConstant(Val, MVT::i32);
364 SDNode *Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::i32, MVT::i32,
365 MVT::Other, Base, TargetConst,
367 SDNode *Result_2 = CurDAG->getMachineNode(Hexagon::SXTW, dl, MVT::i64,
368 SDValue(Result_1, 0));
369 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
370 MemOp[0] = LD->getMemOperand();
371 cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1);
372 const SDValue Froms[] = { SDValue(LD, 0),
376 const SDValue Tos[] = { SDValue(Result_2, 0),
377 SDValue(Result_1, 1),
380 ReplaceUses(Froms, Tos, 3);
383 SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
384 SDValue TargetConstVal = CurDAG->getTargetConstant(Val, MVT::i32);
385 SDNode *Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::i32,
386 MVT::Other, Base, TargetConst0,
388 SDNode *Result_2 = CurDAG->getMachineNode(Hexagon::SXTW, dl,
389 MVT::i64, SDValue(Result_1, 0));
390 SDNode* Result_3 = CurDAG->getMachineNode(Hexagon::ADD_ri, dl,
391 MVT::i32, Base, TargetConstVal,
392 SDValue(Result_1, 1));
393 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
394 MemOp[0] = LD->getMemOperand();
395 cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1);
396 const SDValue Froms[] = { SDValue(LD, 0),
400 const SDValue Tos[] = { SDValue(Result_2, 0),
401 SDValue(Result_3, 0),
404 ReplaceUses(Froms, Tos, 3);
407 return SelectCode(LD);
411 SDNode *HexagonDAGToDAGISel::SelectIndexedLoadZeroExtend64(LoadSDNode *LD,
415 SDValue Chain = LD->getChain();
416 EVT LoadedVT = LD->getMemoryVT();
417 SDValue Base = LD->getBasePtr();
418 SDValue Offset = LD->getOffset();
419 SDNode *OffsetNode = Offset.getNode();
420 int32_t Val = cast<ConstantSDNode>(OffsetNode)->getSExtValue();
421 SDValue N1 = LD->getOperand(1);
424 if (SelectADDRriS11_2(N1, CPTmpN1_0, CPTmpN1_1) &&
425 N1.getNode()->getValueType(0) == MVT::i32) {
426 if (TII->isValidAutoIncImm(LoadedVT, Val)) {
427 SDValue TargetConstVal = CurDAG->getTargetConstant(Val, MVT::i32);
428 SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
429 SDNode *Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::i32,
430 MVT::i32, MVT::Other, Base,
431 TargetConstVal, Chain);
432 SDNode *Result_2 = CurDAG->getMachineNode(Hexagon::TFRI, dl, MVT::i32,
434 SDNode *Result_3 = CurDAG->getMachineNode(Hexagon::COMBINE_rr, dl,
435 MVT::i64, MVT::Other,
437 SDValue(Result_1,0));
438 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
439 MemOp[0] = LD->getMemOperand();
440 cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1);
441 const SDValue Froms[] = { SDValue(LD, 0),
445 const SDValue Tos[] = { SDValue(Result_3, 0),
446 SDValue(Result_1, 1),
449 ReplaceUses(Froms, Tos, 3);
453 // Generate an indirect load.
454 SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
455 SDValue TargetConstVal = CurDAG->getTargetConstant(Val, MVT::i32);
456 SDNode *Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::i32,
458 Base, TargetConst0, Chain);
459 SDNode *Result_2 = CurDAG->getMachineNode(Hexagon::TFRI, dl, MVT::i32,
461 SDNode *Result_3 = CurDAG->getMachineNode(Hexagon::COMBINE_rr, dl,
462 MVT::i64, MVT::Other,
464 SDValue(Result_1,0));
465 // Add offset to base.
466 SDNode* Result_4 = CurDAG->getMachineNode(Hexagon::ADD_ri, dl, MVT::i32,
467 Base, TargetConstVal,
468 SDValue(Result_1, 1));
469 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
470 MemOp[0] = LD->getMemOperand();
471 cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1);
472 const SDValue Froms[] = { SDValue(LD, 0),
476 const SDValue Tos[] = { SDValue(Result_3, 0), // Load value.
477 SDValue(Result_4, 0), // New address.
480 ReplaceUses(Froms, Tos, 3);
484 return SelectCode(LD);
488 SDNode *HexagonDAGToDAGISel::SelectIndexedLoad(LoadSDNode *LD, DebugLoc dl) {
489 SDValue Chain = LD->getChain();
490 SDValue Base = LD->getBasePtr();
491 SDValue Offset = LD->getOffset();
492 SDNode *OffsetNode = Offset.getNode();
493 // Get the constant value.
494 int32_t Val = cast<ConstantSDNode>(OffsetNode)->getSExtValue();
495 EVT LoadedVT = LD->getMemoryVT();
498 // Check for zero ext loads.
499 bool zextval = (LD->getExtensionType() == ISD::ZEXTLOAD);
501 // Figure out the opcode.
502 if (LoadedVT == MVT::i64) {
503 if (TII->isValidAutoIncImm(LoadedVT, Val))
504 Opcode = Hexagon::POST_LDrid;
506 Opcode = Hexagon::LDrid;
507 } else if (LoadedVT == MVT::i32) {
508 if (TII->isValidAutoIncImm(LoadedVT, Val))
509 Opcode = Hexagon::POST_LDriw;
511 Opcode = Hexagon::LDriw;
512 } else if (LoadedVT == MVT::i16) {
513 if (TII->isValidAutoIncImm(LoadedVT, Val))
514 Opcode = zextval ? Hexagon::POST_LDriuh : Hexagon::POST_LDrih;
516 Opcode = zextval ? Hexagon::LDriuh : Hexagon::LDrih;
517 } else if (LoadedVT == MVT::i8) {
518 if (TII->isValidAutoIncImm(LoadedVT, Val))
519 Opcode = zextval ? Hexagon::POST_LDriub : Hexagon::POST_LDrib;
521 Opcode = zextval ? Hexagon::LDriub : Hexagon::LDrib;
523 assert (0 && "unknown memory type");
525 // For zero ext i64 loads, we need to add combine instructions.
526 if (LD->getValueType(0) == MVT::i64 &&
527 LD->getExtensionType() == ISD::ZEXTLOAD) {
528 return SelectIndexedLoadZeroExtend64(LD, Opcode, dl);
530 if (LD->getValueType(0) == MVT::i64 &&
531 LD->getExtensionType() == ISD::SEXTLOAD) {
532 // Handle sign ext i64 loads.
533 return SelectIndexedLoadSignExtend64(LD, Opcode, dl);
535 if (TII->isValidAutoIncImm(LoadedVT, Val)) {
536 SDValue TargetConstVal = CurDAG->getTargetConstant(Val, MVT::i32);
537 SDNode* Result = CurDAG->getMachineNode(Opcode, dl,
539 MVT::i32, MVT::Other, Base,
540 TargetConstVal, Chain);
541 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
542 MemOp[0] = LD->getMemOperand();
543 cast<MachineSDNode>(Result)->setMemRefs(MemOp, MemOp + 1);
544 const SDValue Froms[] = { SDValue(LD, 0),
548 const SDValue Tos[] = { SDValue(Result, 0),
552 ReplaceUses(Froms, Tos, 3);
555 SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
556 SDValue TargetConstVal = CurDAG->getTargetConstant(Val, MVT::i32);
557 SDNode* Result_1 = CurDAG->getMachineNode(Opcode, dl,
559 MVT::Other, Base, TargetConst0,
561 SDNode* Result_2 = CurDAG->getMachineNode(Hexagon::ADD_ri, dl, MVT::i32,
562 Base, TargetConstVal,
563 SDValue(Result_1, 1));
564 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
565 MemOp[0] = LD->getMemOperand();
566 cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1);
567 const SDValue Froms[] = { SDValue(LD, 0),
571 const SDValue Tos[] = { SDValue(Result_1, 0),
572 SDValue(Result_2, 0),
575 ReplaceUses(Froms, Tos, 3);
581 SDNode *HexagonDAGToDAGISel::SelectLoad(SDNode *N) {
583 DebugLoc dl = N->getDebugLoc();
584 LoadSDNode *LD = cast<LoadSDNode>(N);
585 ISD::MemIndexedMode AM = LD->getAddressingMode();
587 // Handle indexed loads.
588 if (AM != ISD::UNINDEXED) {
589 result = SelectIndexedLoad(LD, dl);
591 result = SelectBaseOffsetLoad(LD, dl);
598 SDNode *HexagonDAGToDAGISel::SelectIndexedStore(StoreSDNode *ST, DebugLoc dl) {
599 SDValue Chain = ST->getChain();
600 SDValue Base = ST->getBasePtr();
601 SDValue Offset = ST->getOffset();
602 SDValue Value = ST->getValue();
603 SDNode *OffsetNode = Offset.getNode();
604 // Get the constant value.
605 int32_t Val = cast<ConstantSDNode>(OffsetNode)->getSExtValue();
606 EVT StoredVT = ST->getMemoryVT();
608 // Offset value must be within representable range
609 // and must have correct alignment properties.
610 if (TII->isValidAutoIncImm(StoredVT, Val)) {
611 SDValue Ops[] = { Value, Base,
612 CurDAG->getTargetConstant(Val, MVT::i32), Chain};
615 // Figure out the post inc version of opcode.
616 if (StoredVT == MVT::i64) Opcode = Hexagon::POST_STdri;
617 else if (StoredVT == MVT::i32) Opcode = Hexagon::POST_STwri;
618 else if (StoredVT == MVT::i16) Opcode = Hexagon::POST_SThri;
619 else if (StoredVT == MVT::i8) Opcode = Hexagon::POST_STbri;
620 else assert (0 && "unknown memory type");
622 // Build post increment store.
623 SDNode* Result = CurDAG->getMachineNode(Opcode, dl, MVT::i32,
625 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
626 MemOp[0] = ST->getMemOperand();
627 cast<MachineSDNode>(Result)->setMemRefs(MemOp, MemOp + 1);
629 ReplaceUses(ST, Result);
630 ReplaceUses(SDValue(ST,1), SDValue(Result,1));
634 // Note: Order of operands matches the def of instruction:
635 // def STrid : STInst<(outs), (ins MEMri:$addr, DoubleRegs:$src1), ...
636 // and it differs for POST_ST* for instance.
637 SDValue Ops[] = { Base, CurDAG->getTargetConstant(0, MVT::i32), Value,
641 // Figure out the opcode.
642 if (StoredVT == MVT::i64) Opcode = Hexagon::STrid;
643 else if (StoredVT == MVT::i32) Opcode = Hexagon::STriw_indexed;
644 else if (StoredVT == MVT::i16) Opcode = Hexagon::STrih;
645 else if (StoredVT == MVT::i8) Opcode = Hexagon::STrib;
646 else assert (0 && "unknown memory type");
648 // Build regular store.
649 SDValue TargetConstVal = CurDAG->getTargetConstant(Val, MVT::i32);
650 SDNode* Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::Other, Ops,
652 // Build splitted incriment instruction.
653 SDNode* Result_2 = CurDAG->getMachineNode(Hexagon::ADD_ri, dl, MVT::i32,
656 SDValue(Result_1, 0));
657 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
658 MemOp[0] = ST->getMemOperand();
659 cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1);
661 ReplaceUses(SDValue(ST,0), SDValue(Result_2,0));
662 ReplaceUses(SDValue(ST,1), SDValue(Result_1,0));
667 SDNode *HexagonDAGToDAGISel::SelectBaseOffsetStore(StoreSDNode *ST,
669 SDValue Chain = ST->getChain();
670 SDNode* Const32 = ST->getBasePtr().getNode();
671 SDValue Value = ST->getValue();
674 // Try to lower stores of GlobalAdresses into indexed stores. Custom
675 // lowering for GlobalAddress nodes has already turned it into a
676 // CONST32. Avoid truncating stores for the moment. Post-inc stores
677 // do the same. Don't think there's a reason for it, so will file a
679 if ((Const32->getOpcode() == HexagonISD::CONST32) &&
680 !(Value.getValueType() == MVT::i64 && ST->isTruncatingStore())) {
681 SDValue Base = Const32->getOperand(0);
682 if (Base.getOpcode() == ISD::TargetGlobalAddress) {
683 EVT StoredVT = ST->getMemoryVT();
684 int64_t Offset = cast<GlobalAddressSDNode>(Base)->getOffset();
685 if (Offset != 0 && OffsetFitsS11(StoredVT, Offset)) {
686 MVT PointerTy = TLI.getPointerTy();
687 const GlobalValue* GV =
688 cast<GlobalAddressSDNode>(Base)->getGlobal();
690 CurDAG->getTargetGlobalAddress(GV, dl, PointerTy, 0);
691 SDNode* NewBase = CurDAG->getMachineNode(Hexagon::CONST32_set,
695 // Figure out base + offset opcode
696 if (StoredVT == MVT::i64) Opcode = Hexagon::STrid_indexed;
697 else if (StoredVT == MVT::i32) Opcode = Hexagon::STriw_indexed;
698 else if (StoredVT == MVT::i16) Opcode = Hexagon::STrih_indexed;
699 else if (StoredVT == MVT::i8) Opcode = Hexagon::STrib_indexed;
700 else if (StoredVT == MVT::f32) Opcode = Hexagon::STriw_indexed_f;
701 else if (StoredVT == MVT::f64) Opcode = Hexagon::STrid_indexed_f;
702 else assert (0 && "unknown memory type");
704 SDValue Ops[] = {SDValue(NewBase,0),
705 CurDAG->getTargetConstant(Offset,PointerTy),
707 // build indexed store
708 SDNode* Result = CurDAG->getMachineNode(Opcode, dl,
710 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
711 MemOp[0] = ST->getMemOperand();
712 cast<MachineSDNode>(Result)->setMemRefs(MemOp, MemOp + 1);
713 ReplaceUses(ST, Result);
719 return SelectCode(ST);
723 SDNode *HexagonDAGToDAGISel::SelectStore(SDNode *N) {
724 DebugLoc dl = N->getDebugLoc();
725 StoreSDNode *ST = cast<StoreSDNode>(N);
726 ISD::MemIndexedMode AM = ST->getAddressingMode();
728 // Handle indexed stores.
729 if (AM != ISD::UNINDEXED) {
730 return SelectIndexedStore(ST, dl);
733 return SelectBaseOffsetStore(ST, dl);
736 SDNode *HexagonDAGToDAGISel::SelectMul(SDNode *N) {
737 DebugLoc dl = N->getDebugLoc();
740 // %conv.i = sext i32 %tmp1 to i64
741 // %conv2.i = sext i32 %add to i64
742 // %mul.i = mul nsw i64 %conv2.i, %conv.i
744 // --- match with the following ---
746 // %mul.i = mpy (%tmp1, %add)
749 if (N->getValueType(0) == MVT::i64) {
750 // Shifting a i64 signed multiply.
751 SDValue MulOp0 = N->getOperand(0);
752 SDValue MulOp1 = N->getOperand(1);
757 // Handle sign_extend and sextload.
758 if (MulOp0.getOpcode() == ISD::SIGN_EXTEND) {
759 SDValue Sext0 = MulOp0.getOperand(0);
760 if (Sext0.getNode()->getValueType(0) != MVT::i32) {
761 return SelectCode(N);
765 } else if (MulOp0.getOpcode() == ISD::LOAD) {
766 LoadSDNode *LD = cast<LoadSDNode>(MulOp0.getNode());
767 if (LD->getMemoryVT() != MVT::i32 ||
768 LD->getExtensionType() != ISD::SEXTLOAD ||
769 LD->getAddressingMode() != ISD::UNINDEXED) {
770 return SelectCode(N);
773 SDValue Chain = LD->getChain();
774 SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
775 OP0 = SDValue (CurDAG->getMachineNode(Hexagon::LDriw, dl, MVT::i32,
777 LD->getBasePtr(), TargetConst0,
780 return SelectCode(N);
783 // Same goes for the second operand.
784 if (MulOp1.getOpcode() == ISD::SIGN_EXTEND) {
785 SDValue Sext1 = MulOp1.getOperand(0);
786 if (Sext1.getNode()->getValueType(0) != MVT::i32) {
787 return SelectCode(N);
791 } else if (MulOp1.getOpcode() == ISD::LOAD) {
792 LoadSDNode *LD = cast<LoadSDNode>(MulOp1.getNode());
793 if (LD->getMemoryVT() != MVT::i32 ||
794 LD->getExtensionType() != ISD::SEXTLOAD ||
795 LD->getAddressingMode() != ISD::UNINDEXED) {
796 return SelectCode(N);
799 SDValue Chain = LD->getChain();
800 SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
801 OP1 = SDValue (CurDAG->getMachineNode(Hexagon::LDriw, dl, MVT::i32,
803 LD->getBasePtr(), TargetConst0,
806 return SelectCode(N);
809 // Generate a mpy instruction.
810 SDNode *Result = CurDAG->getMachineNode(Hexagon::MPY64, dl, MVT::i64,
812 ReplaceUses(N, Result);
816 return SelectCode(N);
820 SDNode *HexagonDAGToDAGISel::SelectSelect(SDNode *N) {
821 DebugLoc dl = N->getDebugLoc();
822 SDValue N0 = N->getOperand(0);
823 if (N0.getOpcode() == ISD::SETCC) {
824 SDValue N00 = N0.getOperand(0);
825 if (N00.getOpcode() == ISD::SIGN_EXTEND_INREG) {
826 SDValue N000 = N00.getOperand(0);
827 SDValue N001 = N00.getOperand(1);
828 if (cast<VTSDNode>(N001)->getVT() == MVT::i16) {
829 SDValue N01 = N0.getOperand(1);
830 SDValue N02 = N0.getOperand(2);
832 // Pattern: (select:i32 (setcc:i1 (sext_inreg:i32 IntRegs:i32:$src2,
833 // i16:Other),IntRegs:i32:$src1, SETLT:Other),IntRegs:i32:$src1,
834 // IntRegs:i32:$src2)
835 // Emits: (MAXh_rr:i32 IntRegs:i32:$src1, IntRegs:i32:$src2)
836 // Pattern complexity = 9 cost = 1 size = 0.
837 if (cast<CondCodeSDNode>(N02)->get() == ISD::SETLT) {
838 SDValue N1 = N->getOperand(1);
840 SDValue N2 = N->getOperand(2);
842 N0.getNode()->getValueType(N0.getResNo()) == MVT::i1 &&
843 N00.getNode()->getValueType(N00.getResNo()) == MVT::i32) {
844 SDNode *SextNode = CurDAG->getMachineNode(Hexagon::SXTH, dl,
846 SDNode *Result = CurDAG->getMachineNode(Hexagon::MAXw_rr, dl,
848 SDValue(SextNode, 0),
850 ReplaceUses(N, Result);
856 // Pattern: (select:i32 (setcc:i1 (sext_inreg:i32 IntRegs:i32:$src2,
857 // i16:Other), IntRegs:i32:$src1, SETGT:Other), IntRegs:i32:$src1,
858 // IntRegs:i32:$src2)
859 // Emits: (MINh_rr:i32 IntRegs:i32:$src1, IntRegs:i32:$src2)
860 // Pattern complexity = 9 cost = 1 size = 0.
861 if (cast<CondCodeSDNode>(N02)->get() == ISD::SETGT) {
862 SDValue N1 = N->getOperand(1);
864 SDValue N2 = N->getOperand(2);
866 N0.getNode()->getValueType(N0.getResNo()) == MVT::i1 &&
867 N00.getNode()->getValueType(N00.getResNo()) == MVT::i32) {
868 SDNode *SextNode = CurDAG->getMachineNode(Hexagon::SXTH, dl,
870 SDNode *Result = CurDAG->getMachineNode(Hexagon::MINw_rr, dl,
872 SDValue(SextNode, 0),
874 ReplaceUses(N, Result);
883 return SelectCode(N);
887 SDNode *HexagonDAGToDAGISel::SelectTruncate(SDNode *N) {
888 DebugLoc dl = N->getDebugLoc();
889 SDValue Shift = N->getOperand(0);
892 // %conv.i = sext i32 %tmp1 to i64
893 // %conv2.i = sext i32 %add to i64
894 // %mul.i = mul nsw i64 %conv2.i, %conv.i
895 // %shr5.i = lshr i64 %mul.i, 32
896 // %conv3.i = trunc i64 %shr5.i to i32
898 // --- match with the following ---
900 // %conv3.i = mpy (%tmp1, %add)
903 if (N->getValueType(0) == MVT::i32) {
905 if (Shift.getNode()->getValueType(0) == MVT::i64) {
906 // Trunc child is logical shift right.
907 if (Shift.getOpcode() != ISD::SRL) {
908 return SelectCode(N);
911 SDValue ShiftOp0 = Shift.getOperand(0);
912 SDValue ShiftOp1 = Shift.getOperand(1);
915 if (ShiftOp1.getOpcode() != ISD::Constant) {
916 return SelectCode(N);
920 cast<ConstantSDNode>(ShiftOp1.getNode())->getSExtValue();
921 if (ShiftConst != 32) {
922 return SelectCode(N);
925 // Shifting a i64 signed multiply
926 SDValue Mul = ShiftOp0;
927 if (Mul.getOpcode() != ISD::MUL) {
928 return SelectCode(N);
931 SDValue MulOp0 = Mul.getOperand(0);
932 SDValue MulOp1 = Mul.getOperand(1);
937 // Handle sign_extend and sextload
938 if (MulOp0.getOpcode() == ISD::SIGN_EXTEND) {
939 SDValue Sext0 = MulOp0.getOperand(0);
940 if (Sext0.getNode()->getValueType(0) != MVT::i32) {
941 return SelectCode(N);
945 } else if (MulOp0.getOpcode() == ISD::LOAD) {
946 LoadSDNode *LD = cast<LoadSDNode>(MulOp0.getNode());
947 if (LD->getMemoryVT() != MVT::i32 ||
948 LD->getExtensionType() != ISD::SEXTLOAD ||
949 LD->getAddressingMode() != ISD::UNINDEXED) {
950 return SelectCode(N);
953 SDValue Chain = LD->getChain();
954 SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
955 OP0 = SDValue (CurDAG->getMachineNode(Hexagon::LDriw, dl, MVT::i32,
958 TargetConst0, Chain), 0);
960 return SelectCode(N);
963 // Same goes for the second operand.
964 if (MulOp1.getOpcode() == ISD::SIGN_EXTEND) {
965 SDValue Sext1 = MulOp1.getOperand(0);
966 if (Sext1.getNode()->getValueType(0) != MVT::i32)
967 return SelectCode(N);
970 } else if (MulOp1.getOpcode() == ISD::LOAD) {
971 LoadSDNode *LD = cast<LoadSDNode>(MulOp1.getNode());
972 if (LD->getMemoryVT() != MVT::i32 ||
973 LD->getExtensionType() != ISD::SEXTLOAD ||
974 LD->getAddressingMode() != ISD::UNINDEXED) {
975 return SelectCode(N);
978 SDValue Chain = LD->getChain();
979 SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
980 OP1 = SDValue (CurDAG->getMachineNode(Hexagon::LDriw, dl, MVT::i32,
983 TargetConst0, Chain), 0);
985 return SelectCode(N);
988 // Generate a mpy instruction.
989 SDNode *Result = CurDAG->getMachineNode(Hexagon::MPY, dl, MVT::i32,
991 ReplaceUses(N, Result);
996 return SelectCode(N);
1000 SDNode *HexagonDAGToDAGISel::SelectSHL(SDNode *N) {
1001 DebugLoc dl = N->getDebugLoc();
1002 if (N->getValueType(0) == MVT::i32) {
1003 SDValue Shl_0 = N->getOperand(0);
1004 SDValue Shl_1 = N->getOperand(1);
1006 if (Shl_1.getOpcode() == ISD::Constant) {
1007 if (Shl_0.getOpcode() == ISD::MUL) {
1008 SDValue Mul_0 = Shl_0.getOperand(0); // Val
1009 SDValue Mul_1 = Shl_0.getOperand(1); // Const
1010 // RHS of mul is const.
1011 if (Mul_1.getOpcode() == ISD::Constant) {
1013 cast<ConstantSDNode>(Shl_1.getNode())->getSExtValue();
1015 cast<ConstantSDNode>(Mul_1.getNode())->getSExtValue();
1016 int32_t ValConst = MulConst << ShlConst;
1017 SDValue Val = CurDAG->getTargetConstant(ValConst,
1019 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Val.getNode()))
1020 if (isInt<9>(CN->getSExtValue())) {
1022 CurDAG->getMachineNode(Hexagon::MPYI_ri, dl,
1023 MVT::i32, Mul_0, Val);
1024 ReplaceUses(N, Result);
1029 } else if (Shl_0.getOpcode() == ISD::SUB) {
1030 SDValue Sub_0 = Shl_0.getOperand(0); // Const 0
1031 SDValue Sub_1 = Shl_0.getOperand(1); // Val
1032 if (Sub_0.getOpcode() == ISD::Constant) {
1034 cast<ConstantSDNode>(Sub_0.getNode())->getSExtValue();
1035 if (SubConst == 0) {
1036 if (Sub_1.getOpcode() == ISD::SHL) {
1037 SDValue Shl2_0 = Sub_1.getOperand(0); // Val
1038 SDValue Shl2_1 = Sub_1.getOperand(1); // Const
1039 if (Shl2_1.getOpcode() == ISD::Constant) {
1041 cast<ConstantSDNode>(Shl_1.getNode())->getSExtValue();
1043 cast<ConstantSDNode>(Shl2_1.getNode())->getSExtValue();
1044 int32_t ValConst = 1 << (ShlConst+Shl2Const);
1045 SDValue Val = CurDAG->getTargetConstant(-ValConst, MVT::i32);
1046 if (ConstantSDNode *CN =
1047 dyn_cast<ConstantSDNode>(Val.getNode()))
1048 if (isInt<9>(CN->getSExtValue())) {
1050 CurDAG->getMachineNode(Hexagon::MPYI_ri, dl, MVT::i32,
1052 ReplaceUses(N, Result);
1062 return SelectCode(N);
1067 // If there is an zero_extend followed an intrinsic in DAG (this means - the
1068 // result of the intrinsic is predicate); convert the zero_extend to
1069 // transfer instruction.
1071 // Zero extend -> transfer is lowered here. Otherwise, zero_extend will be
1072 // converted into a MUX as predicate registers defined as 1 bit in the
1073 // compiler. Architecture defines them as 8-bit registers.
1074 // We want to preserve all the lower 8-bits and, not just 1 LSB bit.
1076 SDNode *HexagonDAGToDAGISel::SelectZeroExtend(SDNode *N) {
1077 DebugLoc dl = N->getDebugLoc();
1078 SDNode *IsIntrinsic = N->getOperand(0).getNode();
1079 if ((IsIntrinsic->getOpcode() == ISD::INTRINSIC_WO_CHAIN)) {
1081 cast<ConstantSDNode>(IsIntrinsic->getOperand(0))->getZExtValue();
1082 if (doesIntrinsicReturnPredicate(ID)) {
1083 // Now we need to differentiate target data types.
1084 if (N->getValueType(0) == MVT::i64) {
1085 // Convert the zero_extend to Rs = Pd followed by COMBINE_rr(0,Rs).
1086 SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
1087 SDNode *Result_1 = CurDAG->getMachineNode(Hexagon::TFR_RsPd, dl,
1089 SDValue(IsIntrinsic, 0));
1090 SDNode *Result_2 = CurDAG->getMachineNode(Hexagon::TFRI, dl,
1093 SDNode *Result_3 = CurDAG->getMachineNode(Hexagon::COMBINE_rr, dl,
1094 MVT::i64, MVT::Other,
1095 SDValue(Result_2, 0),
1096 SDValue(Result_1, 0));
1097 ReplaceUses(N, Result_3);
1100 if (N->getValueType(0) == MVT::i32) {
1101 // Convert the zero_extend to Rs = Pd
1102 SDNode* RsPd = CurDAG->getMachineNode(Hexagon::TFR_RsPd, dl,
1104 SDValue(IsIntrinsic, 0));
1105 ReplaceUses(N, RsPd);
1108 llvm_unreachable("Unexpected value type");
1111 return SelectCode(N);
1116 // Checking for intrinsics which have predicate registers as operand(s)
1117 // and lowering to the actual intrinsic.
1119 SDNode *HexagonDAGToDAGISel::SelectIntrinsicWOChain(SDNode *N) {
1120 DebugLoc dl = N->getDebugLoc();
1121 unsigned ID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
1122 unsigned IntrinsicWithPred = doesIntrinsicContainPredicate(ID);
1124 // We are concerned with only those intrinsics that have predicate registers
1125 // as at least one of the operands.
1126 if (IntrinsicWithPred) {
1127 SmallVector<SDValue, 8> Ops;
1128 const MCInstrDesc &MCID = TII->get(IntrinsicWithPred);
1129 const TargetRegisterInfo *TRI = TM.getRegisterInfo();
1131 // Iterate over all the operands of the intrinsics.
1132 // For PredRegs, do the transfer.
1133 // For Double/Int Regs, just preserve the value
1134 // For immediates, lower it.
1135 for (unsigned i = 1; i < N->getNumOperands(); ++i) {
1136 SDNode *Arg = N->getOperand(i).getNode();
1137 const TargetRegisterClass *RC = TII->getRegClass(MCID, i, TRI);
1139 if (RC == Hexagon::IntRegsRegisterClass ||
1140 RC == Hexagon::DoubleRegsRegisterClass) {
1141 Ops.push_back(SDValue(Arg, 0));
1142 } else if (RC == Hexagon::PredRegsRegisterClass) {
1144 SDNode *PdRs = CurDAG->getMachineNode(Hexagon::TFR_PdRs, dl, MVT::i1,
1146 Ops.push_back(SDValue(PdRs,0));
1147 } else if (RC == NULL && (dyn_cast<ConstantSDNode>(Arg) != NULL)) {
1148 // This is immediate operand. Lower it here making sure that we DO have
1149 // const SDNode for immediate value.
1150 int32_t Val = cast<ConstantSDNode>(Arg)->getSExtValue();
1151 SDValue SDVal = CurDAG->getTargetConstant(Val, MVT::i32);
1152 Ops.push_back(SDVal);
1154 llvm_unreachable("Unimplemented");
1157 EVT ReturnValueVT = N->getValueType(0);
1158 SDNode *Result = CurDAG->getMachineNode(IntrinsicWithPred, dl,
1160 Ops.data(), Ops.size());
1161 ReplaceUses(N, Result);
1164 return SelectCode(N);
1168 // Map floating point constant values.
1170 SDNode *HexagonDAGToDAGISel::SelectConstantFP(SDNode *N) {
1171 DebugLoc dl = N->getDebugLoc();
1172 ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);
1173 APFloat APF = CN->getValueAPF();
1174 if (N->getValueType(0) == MVT::f32) {
1175 return CurDAG->getMachineNode(Hexagon::TFRI_f, dl, MVT::f32,
1176 CurDAG->getTargetConstantFP(APF.convertToFloat(), MVT::f32));
1178 else if (N->getValueType(0) == MVT::f64) {
1179 return CurDAG->getMachineNode(Hexagon::CONST64_Float_Real, dl, MVT::f64,
1180 CurDAG->getTargetConstantFP(APF.convertToDouble(), MVT::f64));
1183 return SelectCode(N);
1188 // Map predicate true (encoded as -1 in LLVM) to a XOR.
1190 SDNode *HexagonDAGToDAGISel::SelectConstant(SDNode *N) {
1191 DebugLoc dl = N->getDebugLoc();
1192 if (N->getValueType(0) == MVT::i1) {
1194 int32_t Val = cast<ConstantSDNode>(N)->getSExtValue();
1196 // Create the IntReg = 1 node.
1198 CurDAG->getMachineNode(Hexagon::TFRI, dl, MVT::i32,
1199 CurDAG->getTargetConstant(0, MVT::i32));
1202 SDNode* Pd = CurDAG->getMachineNode(Hexagon::TFR_PdRs, dl, MVT::i1,
1203 SDValue(IntRegTFR, 0));
1206 SDNode* NotPd = CurDAG->getMachineNode(Hexagon::NOT_p, dl, MVT::i1,
1210 Result = CurDAG->getMachineNode(Hexagon::XOR_pp, dl, MVT::i1,
1211 SDValue(Pd, 0), SDValue(NotPd, 0));
1213 // We have just built:
1215 // Pd = xor(not(Pd), Pd)
1217 ReplaceUses(N, Result);
1222 return SelectCode(N);
1227 // Map add followed by a asr -> asr +=.
1229 SDNode *HexagonDAGToDAGISel::SelectAdd(SDNode *N) {
1230 DebugLoc dl = N->getDebugLoc();
1231 if (N->getValueType(0) != MVT::i32) {
1232 return SelectCode(N);
1234 // Identify nodes of the form: add(asr(...)).
1235 SDNode* Src1 = N->getOperand(0).getNode();
1236 if (Src1->getOpcode() != ISD::SRA || !Src1->hasOneUse()
1237 || Src1->getValueType(0) != MVT::i32) {
1238 return SelectCode(N);
1241 // Build Rd = Rd' + asr(Rs, Rt). The machine constraints will ensure that
1242 // Rd and Rd' are assigned to the same register
1243 SDNode* Result = CurDAG->getMachineNode(Hexagon::ASR_rr_acc, dl, MVT::i32,
1245 Src1->getOperand(0),
1246 Src1->getOperand(1));
1247 ReplaceUses(N, Result);
1253 SDNode *HexagonDAGToDAGISel::Select(SDNode *N) {
1254 if (N->isMachineOpcode())
1255 return NULL; // Already selected.
1258 switch (N->getOpcode()) {
1260 return SelectConstant(N);
1262 case ISD::ConstantFP:
1263 return SelectConstantFP(N);
1266 return SelectAdd(N);
1269 return SelectSHL(N);
1272 return SelectLoad(N);
1275 return SelectStore(N);
1278 return SelectSelect(N);
1281 return SelectTruncate(N);
1284 return SelectMul(N);
1286 case ISD::ZERO_EXTEND:
1287 return SelectZeroExtend(N);
1289 case ISD::INTRINSIC_WO_CHAIN:
1290 return SelectIntrinsicWOChain(N);
1293 return SelectCode(N);
1298 // Hexagon_TODO: Five functions for ADDRri?! Surely there must be a better way
1299 // to define these instructions.
1301 bool HexagonDAGToDAGISel::SelectADDRri(SDValue& Addr, SDValue &Base,
1303 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
1304 Addr.getOpcode() == ISD::TargetGlobalAddress)
1305 return false; // Direct calls.
1307 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
1308 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
1309 Offset = CurDAG->getTargetConstant(0, MVT::i32);
1313 Offset = CurDAG->getTargetConstant(0, MVT::i32);
1318 bool HexagonDAGToDAGISel::SelectADDRriS11_0(SDValue& Addr, SDValue &Base,
1320 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
1321 Addr.getOpcode() == ISD::TargetGlobalAddress)
1322 return false; // Direct calls.
1324 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
1325 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
1326 Offset = CurDAG->getTargetConstant(0, MVT::i32);
1327 return (IsS11_0_Offset(Offset.getNode()));
1330 Offset = CurDAG->getTargetConstant(0, MVT::i32);
1331 return (IsS11_0_Offset(Offset.getNode()));
1335 bool HexagonDAGToDAGISel::SelectADDRriS11_1(SDValue& Addr, SDValue &Base,
1337 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
1338 Addr.getOpcode() == ISD::TargetGlobalAddress)
1339 return false; // Direct calls.
1341 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
1342 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
1343 Offset = CurDAG->getTargetConstant(0, MVT::i32);
1344 return (IsS11_1_Offset(Offset.getNode()));
1347 Offset = CurDAG->getTargetConstant(0, MVT::i32);
1348 return (IsS11_1_Offset(Offset.getNode()));
1352 bool HexagonDAGToDAGISel::SelectADDRriS11_2(SDValue& Addr, SDValue &Base,
1354 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
1355 Addr.getOpcode() == ISD::TargetGlobalAddress)
1356 return false; // Direct calls.
1358 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
1359 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
1360 Offset = CurDAG->getTargetConstant(0, MVT::i32);
1361 return (IsS11_2_Offset(Offset.getNode()));
1364 Offset = CurDAG->getTargetConstant(0, MVT::i32);
1365 return (IsS11_2_Offset(Offset.getNode()));
1369 bool HexagonDAGToDAGISel::SelectADDRriU6_0(SDValue& Addr, SDValue &Base,
1371 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
1372 Addr.getOpcode() == ISD::TargetGlobalAddress)
1373 return false; // Direct calls.
1375 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
1376 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
1377 Offset = CurDAG->getTargetConstant(0, MVT::i32);
1378 return (IsU6_0_Offset(Offset.getNode()));
1381 Offset = CurDAG->getTargetConstant(0, MVT::i32);
1382 return (IsU6_0_Offset(Offset.getNode()));
1386 bool HexagonDAGToDAGISel::SelectADDRriU6_1(SDValue& Addr, SDValue &Base,
1388 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
1389 Addr.getOpcode() == ISD::TargetGlobalAddress)
1390 return false; // Direct calls.
1392 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
1393 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
1394 Offset = CurDAG->getTargetConstant(0, MVT::i32);
1395 return (IsU6_1_Offset(Offset.getNode()));
1398 Offset = CurDAG->getTargetConstant(0, MVT::i32);
1399 return (IsU6_1_Offset(Offset.getNode()));
1403 bool HexagonDAGToDAGISel::SelectADDRriU6_2(SDValue& Addr, SDValue &Base,
1405 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
1406 Addr.getOpcode() == ISD::TargetGlobalAddress)
1407 return false; // Direct calls.
1409 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
1410 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
1411 Offset = CurDAG->getTargetConstant(0, MVT::i32);
1412 return (IsU6_2_Offset(Offset.getNode()));
1415 Offset = CurDAG->getTargetConstant(0, MVT::i32);
1416 return (IsU6_2_Offset(Offset.getNode()));
1420 bool HexagonDAGToDAGISel::SelectMEMriS11_2(SDValue& Addr, SDValue &Base,
1423 if (Addr.getOpcode() != ISD::ADD) {
1424 return(SelectADDRriS11_2(Addr, Base, Offset));
1427 return SelectADDRriS11_2(Addr, Base, Offset);
1431 bool HexagonDAGToDAGISel::SelectADDRriS11_3(SDValue& Addr, SDValue &Base,
1433 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
1434 Addr.getOpcode() == ISD::TargetGlobalAddress)
1435 return false; // Direct calls.
1437 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
1438 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
1439 Offset = CurDAG->getTargetConstant(0, MVT::i32);
1440 return (IsS11_3_Offset(Offset.getNode()));
1443 Offset = CurDAG->getTargetConstant(0, MVT::i32);
1444 return (IsS11_3_Offset(Offset.getNode()));
1447 bool HexagonDAGToDAGISel::SelectADDRrr(SDValue &Addr, SDValue &R1,
1449 if (Addr.getOpcode() == ISD::FrameIndex) return false;
1450 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
1451 Addr.getOpcode() == ISD::TargetGlobalAddress)
1452 return false; // Direct calls.
1454 if (Addr.getOpcode() == ISD::ADD) {
1455 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
1456 if (isInt<13>(CN->getSExtValue()))
1457 return false; // Let the reg+imm pattern catch this!
1458 R1 = Addr.getOperand(0);
1459 R2 = Addr.getOperand(1);
1469 // Handle generic address case. It is accessed from inlined asm =m constraints,
1470 // which could have any kind of pointer.
1471 bool HexagonDAGToDAGISel::SelectAddr(SDNode *Op, SDValue Addr,
1472 SDValue &Base, SDValue &Offset) {
1473 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
1474 Addr.getOpcode() == ISD::TargetGlobalAddress)
1475 return false; // Direct calls.
1477 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
1478 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
1479 Offset = CurDAG->getTargetConstant(0, MVT::i32);
1483 if (Addr.getOpcode() == ISD::ADD) {
1484 Base = Addr.getOperand(0);
1485 Offset = Addr.getOperand(1);
1490 Offset = CurDAG->getTargetConstant(0, MVT::i32);
1495 bool HexagonDAGToDAGISel::
1496 SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
1497 std::vector<SDValue> &OutOps) {
1500 switch (ConstraintCode) {
1501 case 'o': // Offsetable.
1502 case 'v': // Not offsetable.
1503 default: return true;
1504 case 'm': // Memory.
1505 if (!SelectAddr(Op.getNode(), Op, Op0, Op1))
1510 OutOps.push_back(Op0);
1511 OutOps.push_back(Op1);