1 //===-- HexagonISelDAGToDAG.cpp - A dag to dag inst selector for Hexagon --===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the Hexagon target.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "hexagon-isel"
16 #include "HexagonISelLowering.h"
17 #include "HexagonTargetMachine.h"
18 #include "llvm/ADT/DenseMap.h"
19 #include "llvm/IR/Intrinsics.h"
20 #include "llvm/CodeGen/SelectionDAGISel.h"
21 #include "llvm/Support/CommandLine.h"
22 #include "llvm/Support/Compiler.h"
23 #include "llvm/Support/Debug.h"
28 MaxNumOfUsesForConstExtenders("ga-max-num-uses-for-constant-extenders",
29 cl::Hidden, cl::init(2),
30 cl::desc("Maximum number of uses of a global address such that we still us a"
31 "constant extended instruction"));
33 //===----------------------------------------------------------------------===//
34 // Instruction Selector Implementation
35 //===----------------------------------------------------------------------===//
38 void initializeHexagonDAGToDAGISelPass(PassRegistry&);
41 //===--------------------------------------------------------------------===//
42 /// HexagonDAGToDAGISel - Hexagon specific code to select Hexagon machine
43 /// instructions for SelectionDAG operations.
46 class HexagonDAGToDAGISel : public SelectionDAGISel {
47 /// Subtarget - Keep a pointer to the Hexagon Subtarget around so that we can
48 /// make the right decision when generating code for different targets.
49 const HexagonSubtarget &Subtarget;
51 // Keep a reference to HexagonTargetMachine.
52 HexagonTargetMachine& TM;
53 const HexagonInstrInfo *TII;
54 DenseMap<const GlobalValue *, unsigned> GlobalAddressUseCountMap;
56 explicit HexagonDAGToDAGISel(HexagonTargetMachine &targetmachine,
57 CodeGenOpt::Level OptLevel)
58 : SelectionDAGISel(targetmachine, OptLevel),
59 Subtarget(targetmachine.getSubtarget<HexagonSubtarget>()),
61 TII(static_cast<const HexagonInstrInfo*>(TM.getInstrInfo())) {
62 initializeHexagonDAGToDAGISelPass(*PassRegistry::getPassRegistry());
64 bool hasNumUsesBelowThresGA(SDNode *N) const;
66 SDNode *Select(SDNode *N);
68 // Complex Pattern Selectors.
69 inline bool foldGlobalAddress(SDValue &N, SDValue &R);
70 inline bool foldGlobalAddressGP(SDValue &N, SDValue &R);
71 bool foldGlobalAddressImpl(SDValue &N, SDValue &R, bool ShouldLookForGP);
72 bool SelectADDRri(SDValue& N, SDValue &R1, SDValue &R2);
73 bool SelectADDRriS11_0(SDValue& N, SDValue &R1, SDValue &R2);
74 bool SelectADDRriS11_1(SDValue& N, SDValue &R1, SDValue &R2);
75 bool SelectADDRriS11_2(SDValue& N, SDValue &R1, SDValue &R2);
76 bool SelectMEMriS11_2(SDValue& Addr, SDValue &Base, SDValue &Offset);
77 bool SelectADDRriS11_3(SDValue& N, SDValue &R1, SDValue &R2);
78 bool SelectADDRrr(SDValue &Addr, SDValue &Base, SDValue &Offset);
79 bool SelectADDRriU6_0(SDValue& N, SDValue &R1, SDValue &R2);
80 bool SelectADDRriU6_1(SDValue& N, SDValue &R1, SDValue &R2);
81 bool SelectADDRriU6_2(SDValue& N, SDValue &R1, SDValue &R2);
83 virtual const char *getPassName() const {
84 return "Hexagon DAG->DAG Pattern Instruction Selection";
87 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
88 /// inline asm expressions.
89 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
91 std::vector<SDValue> &OutOps);
92 bool SelectAddr(SDNode *Op, SDValue Addr, SDValue &Base, SDValue &Offset);
94 SDNode *SelectLoad(SDNode *N);
95 SDNode *SelectBaseOffsetLoad(LoadSDNode *LD, DebugLoc dl);
96 SDNode *SelectIndexedLoad(LoadSDNode *LD, DebugLoc dl);
97 SDNode *SelectIndexedLoadZeroExtend64(LoadSDNode *LD, unsigned Opcode,
99 SDNode *SelectIndexedLoadSignExtend64(LoadSDNode *LD, unsigned Opcode,
101 SDNode *SelectBaseOffsetStore(StoreSDNode *ST, DebugLoc dl);
102 SDNode *SelectIndexedStore(StoreSDNode *ST, DebugLoc dl);
103 SDNode *SelectStore(SDNode *N);
104 SDNode *SelectSHL(SDNode *N);
105 SDNode *SelectSelect(SDNode *N);
106 SDNode *SelectTruncate(SDNode *N);
107 SDNode *SelectMul(SDNode *N);
108 SDNode *SelectZeroExtend(SDNode *N);
109 SDNode *SelectIntrinsicWOChain(SDNode *N);
110 SDNode *SelectIntrinsicWChain(SDNode *N);
111 SDNode *SelectConstant(SDNode *N);
112 SDNode *SelectConstantFP(SDNode *N);
113 SDNode *SelectAdd(SDNode *N);
114 bool isConstExtProfitable(SDNode *N) const;
116 // XformMskToBitPosU5Imm - Returns the bit position which
117 // the single bit 32 bit mask represents.
118 // Used in Clr and Set bit immediate memops.
119 SDValue XformMskToBitPosU5Imm(uint32_t Imm) {
121 bitPos = Log2_32(Imm);
122 assert(bitPos >= 0 && bitPos < 32 &&
123 "Constant out of range for 32 BitPos Memops");
124 return CurDAG->getTargetConstant(bitPos, MVT::i32);
127 // XformMskToBitPosU4Imm - Returns the bit position which the single bit 16 bit
128 // mask represents. Used in Clr and Set bit immediate memops.
129 SDValue XformMskToBitPosU4Imm(uint16_t Imm) {
130 return XformMskToBitPosU5Imm(Imm);
133 // XformMskToBitPosU3Imm - Returns the bit position which the single bit 8 bit
134 // mask represents. Used in Clr and Set bit immediate memops.
135 SDValue XformMskToBitPosU3Imm(uint8_t Imm) {
136 return XformMskToBitPosU5Imm(Imm);
139 // Return true if there is exactly one bit set in V, i.e., if V is one of the
140 // following integers: 2^0, 2^1, ..., 2^31.
141 bool ImmIsSingleBit(uint32_t v) const {
142 uint32_t c = CountPopulation_64(v);
143 // Only return true if we counted 1 bit.
147 // XformM5ToU5Imm - Return a target constant with the specified value, of type
148 // i32 where the negative literal is transformed into a positive literal for
150 inline SDValue XformM5ToU5Imm(signed Imm) {
151 assert( (Imm >= -31 && Imm <= -1) && "Constant out of range for Memops");
152 return CurDAG->getTargetConstant( - Imm, MVT::i32);
156 // XformU7ToU7M1Imm - Return a target constant decremented by 1, in range
157 // [1..128], used in cmpb.gtu instructions.
158 inline SDValue XformU7ToU7M1Imm(signed Imm) {
159 assert((Imm >= 1 && Imm <= 128) && "Constant out of range for cmpb op");
160 return CurDAG->getTargetConstant(Imm - 1, MVT::i8);
163 // Include the pieces autogenerated from the target description.
164 #include "HexagonGenDAGISel.inc"
166 } // end anonymous namespace
169 /// createHexagonISelDag - This pass converts a legalized DAG into a
170 /// Hexagon-specific DAG, ready for instruction scheduling.
172 FunctionPass *llvm::createHexagonISelDag(HexagonTargetMachine &TM,
173 CodeGenOpt::Level OptLevel) {
174 return new HexagonDAGToDAGISel(TM, OptLevel);
177 static void initializePassOnce(PassRegistry &Registry) {
178 const char *Name = "Hexagon DAG->DAG Pattern Instruction Selection";
179 PassInfo *PI = new PassInfo(Name, "hexagon-isel",
180 &SelectionDAGISel::ID, 0, false, false);
181 Registry.registerPass(*PI, true);
184 void llvm::initializeHexagonDAGToDAGISelPass(PassRegistry &Registry) {
185 CALL_ONCE_INITIALIZATION(initializePassOnce)
189 static bool IsS11_0_Offset(SDNode * S) {
190 ConstantSDNode *N = cast<ConstantSDNode>(S);
192 // immS16 predicate - True if the immediate fits in a 16-bit sign extended
194 int64_t v = (int64_t)N->getSExtValue();
199 static bool IsS11_1_Offset(SDNode * S) {
200 ConstantSDNode *N = cast<ConstantSDNode>(S);
202 // immS16 predicate - True if the immediate fits in a 16-bit sign extended
204 int64_t v = (int64_t)N->getSExtValue();
205 return isShiftedInt<11,1>(v);
209 static bool IsS11_2_Offset(SDNode * S) {
210 ConstantSDNode *N = cast<ConstantSDNode>(S);
212 // immS16 predicate - True if the immediate fits in a 16-bit sign extended
214 int64_t v = (int64_t)N->getSExtValue();
215 return isShiftedInt<11,2>(v);
219 static bool IsS11_3_Offset(SDNode * S) {
220 ConstantSDNode *N = cast<ConstantSDNode>(S);
222 // immS16 predicate - True if the immediate fits in a 16-bit sign extended
224 int64_t v = (int64_t)N->getSExtValue();
225 return isShiftedInt<11,3>(v);
229 static bool IsU6_0_Offset(SDNode * S) {
230 ConstantSDNode *N = cast<ConstantSDNode>(S);
232 // u6 predicate - True if the immediate fits in a 6-bit unsigned extended
234 int64_t v = (int64_t)N->getSExtValue();
239 static bool IsU6_1_Offset(SDNode * S) {
240 ConstantSDNode *N = cast<ConstantSDNode>(S);
242 // u6 predicate - True if the immediate fits in a 6-bit unsigned extended
244 int64_t v = (int64_t)N->getSExtValue();
245 return isShiftedUInt<6,1>(v);
249 static bool IsU6_2_Offset(SDNode * S) {
250 ConstantSDNode *N = cast<ConstantSDNode>(S);
252 // u6 predicate - True if the immediate fits in a 6-bit unsigned extended
254 int64_t v = (int64_t)N->getSExtValue();
255 return isShiftedUInt<6,2>(v);
259 // Intrinsics that return a a predicate.
260 static unsigned doesIntrinsicReturnPredicate(unsigned ID)
265 case Intrinsic::hexagon_C2_cmpeq:
266 case Intrinsic::hexagon_C2_cmpgt:
267 case Intrinsic::hexagon_C2_cmpgtu:
268 case Intrinsic::hexagon_C2_cmpgtup:
269 case Intrinsic::hexagon_C2_cmpgtp:
270 case Intrinsic::hexagon_C2_cmpeqp:
271 case Intrinsic::hexagon_C2_bitsset:
272 case Intrinsic::hexagon_C2_bitsclr:
273 case Intrinsic::hexagon_C2_cmpeqi:
274 case Intrinsic::hexagon_C2_cmpgti:
275 case Intrinsic::hexagon_C2_cmpgtui:
276 case Intrinsic::hexagon_C2_cmpgei:
277 case Intrinsic::hexagon_C2_cmpgeui:
278 case Intrinsic::hexagon_C2_cmplt:
279 case Intrinsic::hexagon_C2_cmpltu:
280 case Intrinsic::hexagon_C2_bitsclri:
281 case Intrinsic::hexagon_C2_and:
282 case Intrinsic::hexagon_C2_or:
283 case Intrinsic::hexagon_C2_xor:
284 case Intrinsic::hexagon_C2_andn:
285 case Intrinsic::hexagon_C2_not:
286 case Intrinsic::hexagon_C2_orn:
287 case Intrinsic::hexagon_C2_pxfer_map:
288 case Intrinsic::hexagon_C2_any8:
289 case Intrinsic::hexagon_C2_all8:
290 case Intrinsic::hexagon_A2_vcmpbeq:
291 case Intrinsic::hexagon_A2_vcmpbgtu:
292 case Intrinsic::hexagon_A2_vcmpheq:
293 case Intrinsic::hexagon_A2_vcmphgt:
294 case Intrinsic::hexagon_A2_vcmphgtu:
295 case Intrinsic::hexagon_A2_vcmpweq:
296 case Intrinsic::hexagon_A2_vcmpwgt:
297 case Intrinsic::hexagon_A2_vcmpwgtu:
298 case Intrinsic::hexagon_C2_tfrrp:
299 case Intrinsic::hexagon_S2_tstbit_i:
300 case Intrinsic::hexagon_S2_tstbit_r:
306 // Intrinsics that have predicate operands.
307 static unsigned doesIntrinsicContainPredicate(unsigned ID)
312 case Intrinsic::hexagon_C2_tfrpr:
313 return Hexagon::TFR_RsPd;
314 case Intrinsic::hexagon_C2_and:
315 return Hexagon::AND_pp;
316 case Intrinsic::hexagon_C2_xor:
317 return Hexagon::XOR_pp;
318 case Intrinsic::hexagon_C2_or:
319 return Hexagon::OR_pp;
320 case Intrinsic::hexagon_C2_not:
321 return Hexagon::NOT_p;
322 case Intrinsic::hexagon_C2_any8:
323 return Hexagon::ANY_pp;
324 case Intrinsic::hexagon_C2_all8:
325 return Hexagon::ALL_pp;
326 case Intrinsic::hexagon_C2_vitpack:
327 return Hexagon::VITPACK_pp;
328 case Intrinsic::hexagon_C2_mask:
329 return Hexagon::MASK_p;
330 case Intrinsic::hexagon_C2_mux:
331 return Hexagon::MUX_rr;
333 // Mapping hexagon_C2_muxir to MUX_pri. This is pretty weird - but
334 // that's how it's mapped in q6protos.h.
335 case Intrinsic::hexagon_C2_muxir:
336 return Hexagon::MUX_ri;
338 // Mapping hexagon_C2_muxri to MUX_pir. This is pretty weird - but
339 // that's how it's mapped in q6protos.h.
340 case Intrinsic::hexagon_C2_muxri:
341 return Hexagon::MUX_ir;
343 case Intrinsic::hexagon_C2_muxii:
344 return Hexagon::MUX_ii;
345 case Intrinsic::hexagon_C2_vmux:
346 return Hexagon::VMUX_prr64;
347 case Intrinsic::hexagon_S2_valignrb:
348 return Hexagon::VALIGN_rrp;
349 case Intrinsic::hexagon_S2_vsplicerb:
350 return Hexagon::VSPLICE_rrp;
355 static bool OffsetFitsS11(EVT MemType, int64_t Offset) {
356 if (MemType == MVT::i64 && isShiftedInt<11,3>(Offset)) {
359 if (MemType == MVT::i32 && isShiftedInt<11,2>(Offset)) {
362 if (MemType == MVT::i16 && isShiftedInt<11,1>(Offset)) {
365 if (MemType == MVT::i8 && isInt<11>(Offset)) {
373 // Try to lower loads of GlobalAdresses into base+offset loads. Custom
374 // lowering for GlobalAddress nodes has already turned it into a
377 SDNode *HexagonDAGToDAGISel::SelectBaseOffsetLoad(LoadSDNode *LD, DebugLoc dl) {
378 SDValue Chain = LD->getChain();
379 SDNode* Const32 = LD->getBasePtr().getNode();
382 if (Const32->getOpcode() == HexagonISD::CONST32 &&
383 ISD::isNormalLoad(LD)) {
384 SDValue Base = Const32->getOperand(0);
385 EVT LoadedVT = LD->getMemoryVT();
386 int64_t Offset = cast<GlobalAddressSDNode>(Base)->getOffset();
387 if (Offset != 0 && OffsetFitsS11(LoadedVT, Offset)) {
388 MVT PointerTy = TLI.getPointerTy();
389 const GlobalValue* GV =
390 cast<GlobalAddressSDNode>(Base)->getGlobal();
392 CurDAG->getTargetGlobalAddress(GV, dl, PointerTy, 0);
393 SDNode* NewBase = CurDAG->getMachineNode(Hexagon::CONST32_set,
396 // Figure out base + offset opcode
397 if (LoadedVT == MVT::i64) Opcode = Hexagon::LDrid_indexed;
398 else if (LoadedVT == MVT::i32) Opcode = Hexagon::LDriw_indexed;
399 else if (LoadedVT == MVT::i16) Opcode = Hexagon::LDrih_indexed;
400 else if (LoadedVT == MVT::i8) Opcode = Hexagon::LDrib_indexed;
401 else llvm_unreachable("unknown memory type");
403 // Build indexed load.
404 SDValue TargetConstOff = CurDAG->getTargetConstant(Offset, PointerTy);
405 SDNode* Result = CurDAG->getMachineNode(Opcode, dl,
411 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
412 MemOp[0] = LD->getMemOperand();
413 cast<MachineSDNode>(Result)->setMemRefs(MemOp, MemOp + 1);
414 ReplaceUses(LD, Result);
419 return SelectCode(LD);
423 SDNode *HexagonDAGToDAGISel::SelectIndexedLoadSignExtend64(LoadSDNode *LD,
427 SDValue Chain = LD->getChain();
428 EVT LoadedVT = LD->getMemoryVT();
429 SDValue Base = LD->getBasePtr();
430 SDValue Offset = LD->getOffset();
431 SDNode *OffsetNode = Offset.getNode();
432 int32_t Val = cast<ConstantSDNode>(OffsetNode)->getSExtValue();
433 SDValue N1 = LD->getOperand(1);
436 if (SelectADDRriS11_2(N1, CPTmpN1_0, CPTmpN1_1) &&
437 N1.getNode()->getValueType(0) == MVT::i32) {
438 if (TII->isValidAutoIncImm(LoadedVT, Val)) {
439 SDValue TargetConst = CurDAG->getTargetConstant(Val, MVT::i32);
440 SDNode *Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::i32, MVT::i32,
441 MVT::Other, Base, TargetConst,
443 SDNode *Result_2 = CurDAG->getMachineNode(Hexagon::SXTW, dl, MVT::i64,
444 SDValue(Result_1, 0));
445 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
446 MemOp[0] = LD->getMemOperand();
447 cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1);
448 const SDValue Froms[] = { SDValue(LD, 0),
452 const SDValue Tos[] = { SDValue(Result_2, 0),
453 SDValue(Result_1, 1),
456 ReplaceUses(Froms, Tos, 3);
459 SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
460 SDValue TargetConstVal = CurDAG->getTargetConstant(Val, MVT::i32);
461 SDNode *Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::i32,
462 MVT::Other, Base, TargetConst0,
464 SDNode *Result_2 = CurDAG->getMachineNode(Hexagon::SXTW, dl,
465 MVT::i64, SDValue(Result_1, 0));
466 SDNode* Result_3 = CurDAG->getMachineNode(Hexagon::ADD_ri, dl,
467 MVT::i32, Base, TargetConstVal,
468 SDValue(Result_1, 1));
469 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
470 MemOp[0] = LD->getMemOperand();
471 cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1);
472 const SDValue Froms[] = { SDValue(LD, 0),
476 const SDValue Tos[] = { SDValue(Result_2, 0),
477 SDValue(Result_3, 0),
480 ReplaceUses(Froms, Tos, 3);
483 return SelectCode(LD);
487 SDNode *HexagonDAGToDAGISel::SelectIndexedLoadZeroExtend64(LoadSDNode *LD,
491 SDValue Chain = LD->getChain();
492 EVT LoadedVT = LD->getMemoryVT();
493 SDValue Base = LD->getBasePtr();
494 SDValue Offset = LD->getOffset();
495 SDNode *OffsetNode = Offset.getNode();
496 int32_t Val = cast<ConstantSDNode>(OffsetNode)->getSExtValue();
497 SDValue N1 = LD->getOperand(1);
500 if (SelectADDRriS11_2(N1, CPTmpN1_0, CPTmpN1_1) &&
501 N1.getNode()->getValueType(0) == MVT::i32) {
502 if (TII->isValidAutoIncImm(LoadedVT, Val)) {
503 SDValue TargetConstVal = CurDAG->getTargetConstant(Val, MVT::i32);
504 SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
505 SDNode *Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::i32,
506 MVT::i32, MVT::Other, Base,
507 TargetConstVal, Chain);
508 SDNode *Result_2 = CurDAG->getMachineNode(Hexagon::TFRI, dl, MVT::i32,
510 SDNode *Result_3 = CurDAG->getMachineNode(Hexagon::COMBINE_rr, dl,
511 MVT::i64, MVT::Other,
513 SDValue(Result_1,0));
514 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
515 MemOp[0] = LD->getMemOperand();
516 cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1);
517 const SDValue Froms[] = { SDValue(LD, 0),
521 const SDValue Tos[] = { SDValue(Result_3, 0),
522 SDValue(Result_1, 1),
525 ReplaceUses(Froms, Tos, 3);
529 // Generate an indirect load.
530 SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
531 SDValue TargetConstVal = CurDAG->getTargetConstant(Val, MVT::i32);
532 SDNode *Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::i32,
534 Base, TargetConst0, Chain);
535 SDNode *Result_2 = CurDAG->getMachineNode(Hexagon::TFRI, dl, MVT::i32,
537 SDNode *Result_3 = CurDAG->getMachineNode(Hexagon::COMBINE_rr, dl,
538 MVT::i64, MVT::Other,
540 SDValue(Result_1,0));
541 // Add offset to base.
542 SDNode* Result_4 = CurDAG->getMachineNode(Hexagon::ADD_ri, dl, MVT::i32,
543 Base, TargetConstVal,
544 SDValue(Result_1, 1));
545 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
546 MemOp[0] = LD->getMemOperand();
547 cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1);
548 const SDValue Froms[] = { SDValue(LD, 0),
552 const SDValue Tos[] = { SDValue(Result_3, 0), // Load value.
553 SDValue(Result_4, 0), // New address.
556 ReplaceUses(Froms, Tos, 3);
560 return SelectCode(LD);
564 SDNode *HexagonDAGToDAGISel::SelectIndexedLoad(LoadSDNode *LD, DebugLoc dl) {
565 SDValue Chain = LD->getChain();
566 SDValue Base = LD->getBasePtr();
567 SDValue Offset = LD->getOffset();
568 SDNode *OffsetNode = Offset.getNode();
569 // Get the constant value.
570 int32_t Val = cast<ConstantSDNode>(OffsetNode)->getSExtValue();
571 EVT LoadedVT = LD->getMemoryVT();
574 // Check for zero ext loads.
575 bool zextval = (LD->getExtensionType() == ISD::ZEXTLOAD);
577 // Figure out the opcode.
578 if (LoadedVT == MVT::i64) {
579 if (TII->isValidAutoIncImm(LoadedVT, Val))
580 Opcode = Hexagon::POST_LDrid;
582 Opcode = Hexagon::LDrid;
583 } else if (LoadedVT == MVT::i32) {
584 if (TII->isValidAutoIncImm(LoadedVT, Val))
585 Opcode = Hexagon::POST_LDriw;
587 Opcode = Hexagon::LDriw;
588 } else if (LoadedVT == MVT::i16) {
589 if (TII->isValidAutoIncImm(LoadedVT, Val))
590 Opcode = zextval ? Hexagon::POST_LDriuh : Hexagon::POST_LDrih;
592 Opcode = zextval ? Hexagon::LDriuh : Hexagon::LDrih;
593 } else if (LoadedVT == MVT::i8) {
594 if (TII->isValidAutoIncImm(LoadedVT, Val))
595 Opcode = zextval ? Hexagon::POST_LDriub : Hexagon::POST_LDrib;
597 Opcode = zextval ? Hexagon::LDriub : Hexagon::LDrib;
599 llvm_unreachable("unknown memory type");
601 // For zero ext i64 loads, we need to add combine instructions.
602 if (LD->getValueType(0) == MVT::i64 &&
603 LD->getExtensionType() == ISD::ZEXTLOAD) {
604 return SelectIndexedLoadZeroExtend64(LD, Opcode, dl);
606 if (LD->getValueType(0) == MVT::i64 &&
607 LD->getExtensionType() == ISD::SEXTLOAD) {
608 // Handle sign ext i64 loads.
609 return SelectIndexedLoadSignExtend64(LD, Opcode, dl);
611 if (TII->isValidAutoIncImm(LoadedVT, Val)) {
612 SDValue TargetConstVal = CurDAG->getTargetConstant(Val, MVT::i32);
613 SDNode* Result = CurDAG->getMachineNode(Opcode, dl,
615 MVT::i32, MVT::Other, Base,
616 TargetConstVal, Chain);
617 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
618 MemOp[0] = LD->getMemOperand();
619 cast<MachineSDNode>(Result)->setMemRefs(MemOp, MemOp + 1);
620 const SDValue Froms[] = { SDValue(LD, 0),
624 const SDValue Tos[] = { SDValue(Result, 0),
628 ReplaceUses(Froms, Tos, 3);
631 SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
632 SDValue TargetConstVal = CurDAG->getTargetConstant(Val, MVT::i32);
633 SDNode* Result_1 = CurDAG->getMachineNode(Opcode, dl,
635 MVT::Other, Base, TargetConst0,
637 SDNode* Result_2 = CurDAG->getMachineNode(Hexagon::ADD_ri, dl, MVT::i32,
638 Base, TargetConstVal,
639 SDValue(Result_1, 1));
640 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
641 MemOp[0] = LD->getMemOperand();
642 cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1);
643 const SDValue Froms[] = { SDValue(LD, 0),
647 const SDValue Tos[] = { SDValue(Result_1, 0),
648 SDValue(Result_2, 0),
651 ReplaceUses(Froms, Tos, 3);
657 SDNode *HexagonDAGToDAGISel::SelectLoad(SDNode *N) {
659 DebugLoc dl = N->getDebugLoc();
660 LoadSDNode *LD = cast<LoadSDNode>(N);
661 ISD::MemIndexedMode AM = LD->getAddressingMode();
663 // Handle indexed loads.
664 if (AM != ISD::UNINDEXED) {
665 result = SelectIndexedLoad(LD, dl);
667 result = SelectBaseOffsetLoad(LD, dl);
674 SDNode *HexagonDAGToDAGISel::SelectIndexedStore(StoreSDNode *ST, DebugLoc dl) {
675 SDValue Chain = ST->getChain();
676 SDValue Base = ST->getBasePtr();
677 SDValue Offset = ST->getOffset();
678 SDValue Value = ST->getValue();
679 SDNode *OffsetNode = Offset.getNode();
680 // Get the constant value.
681 int32_t Val = cast<ConstantSDNode>(OffsetNode)->getSExtValue();
682 EVT StoredVT = ST->getMemoryVT();
684 // Offset value must be within representable range
685 // and must have correct alignment properties.
686 if (TII->isValidAutoIncImm(StoredVT, Val)) {
687 SDValue Ops[] = {Base, CurDAG->getTargetConstant(Val, MVT::i32), Value,
691 // Figure out the post inc version of opcode.
692 if (StoredVT == MVT::i64) Opcode = Hexagon::POST_STdri;
693 else if (StoredVT == MVT::i32) Opcode = Hexagon::POST_STwri;
694 else if (StoredVT == MVT::i16) Opcode = Hexagon::POST_SThri;
695 else if (StoredVT == MVT::i8) Opcode = Hexagon::POST_STbri;
696 else llvm_unreachable("unknown memory type");
698 // Build post increment store.
699 SDNode* Result = CurDAG->getMachineNode(Opcode, dl, MVT::i32,
701 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
702 MemOp[0] = ST->getMemOperand();
703 cast<MachineSDNode>(Result)->setMemRefs(MemOp, MemOp + 1);
705 ReplaceUses(ST, Result);
706 ReplaceUses(SDValue(ST,1), SDValue(Result,1));
710 // Note: Order of operands matches the def of instruction:
711 // def STrid : STInst<(outs), (ins MEMri:$addr, DoubleRegs:$src1), ...
712 // and it differs for POST_ST* for instance.
713 SDValue Ops[] = { Base, CurDAG->getTargetConstant(0, MVT::i32), Value,
717 // Figure out the opcode.
718 if (StoredVT == MVT::i64) Opcode = Hexagon::STrid;
719 else if (StoredVT == MVT::i32) Opcode = Hexagon::STriw_indexed;
720 else if (StoredVT == MVT::i16) Opcode = Hexagon::STrih;
721 else if (StoredVT == MVT::i8) Opcode = Hexagon::STrib;
722 else llvm_unreachable("unknown memory type");
724 // Build regular store.
725 SDValue TargetConstVal = CurDAG->getTargetConstant(Val, MVT::i32);
726 SDNode* Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::Other, Ops);
727 // Build splitted incriment instruction.
728 SDNode* Result_2 = CurDAG->getMachineNode(Hexagon::ADD_ri, dl, MVT::i32,
731 SDValue(Result_1, 0));
732 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
733 MemOp[0] = ST->getMemOperand();
734 cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1);
736 ReplaceUses(SDValue(ST,0), SDValue(Result_2,0));
737 ReplaceUses(SDValue(ST,1), SDValue(Result_1,0));
742 SDNode *HexagonDAGToDAGISel::SelectBaseOffsetStore(StoreSDNode *ST,
744 SDValue Chain = ST->getChain();
745 SDNode* Const32 = ST->getBasePtr().getNode();
746 SDValue Value = ST->getValue();
749 // Try to lower stores of GlobalAdresses into indexed stores. Custom
750 // lowering for GlobalAddress nodes has already turned it into a
751 // CONST32. Avoid truncating stores for the moment. Post-inc stores
752 // do the same. Don't think there's a reason for it, so will file a
754 if ((Const32->getOpcode() == HexagonISD::CONST32) &&
755 !(Value.getValueType() == MVT::i64 && ST->isTruncatingStore())) {
756 SDValue Base = Const32->getOperand(0);
757 if (Base.getOpcode() == ISD::TargetGlobalAddress) {
758 EVT StoredVT = ST->getMemoryVT();
759 int64_t Offset = cast<GlobalAddressSDNode>(Base)->getOffset();
760 if (Offset != 0 && OffsetFitsS11(StoredVT, Offset)) {
761 MVT PointerTy = TLI.getPointerTy();
762 const GlobalValue* GV =
763 cast<GlobalAddressSDNode>(Base)->getGlobal();
765 CurDAG->getTargetGlobalAddress(GV, dl, PointerTy, 0);
766 SDNode* NewBase = CurDAG->getMachineNode(Hexagon::CONST32_set,
770 // Figure out base + offset opcode
771 if (StoredVT == MVT::i64) Opcode = Hexagon::STrid_indexed;
772 else if (StoredVT == MVT::i32) Opcode = Hexagon::STriw_indexed;
773 else if (StoredVT == MVT::i16) Opcode = Hexagon::STrih_indexed;
774 else if (StoredVT == MVT::i8) Opcode = Hexagon::STrib_indexed;
775 else llvm_unreachable("unknown memory type");
777 SDValue Ops[] = {SDValue(NewBase,0),
778 CurDAG->getTargetConstant(Offset,PointerTy),
780 // build indexed store
781 SDNode* Result = CurDAG->getMachineNode(Opcode, dl,
783 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
784 MemOp[0] = ST->getMemOperand();
785 cast<MachineSDNode>(Result)->setMemRefs(MemOp, MemOp + 1);
786 ReplaceUses(ST, Result);
792 return SelectCode(ST);
796 SDNode *HexagonDAGToDAGISel::SelectStore(SDNode *N) {
797 DebugLoc dl = N->getDebugLoc();
798 StoreSDNode *ST = cast<StoreSDNode>(N);
799 ISD::MemIndexedMode AM = ST->getAddressingMode();
801 // Handle indexed stores.
802 if (AM != ISD::UNINDEXED) {
803 return SelectIndexedStore(ST, dl);
806 return SelectBaseOffsetStore(ST, dl);
809 SDNode *HexagonDAGToDAGISel::SelectMul(SDNode *N) {
810 DebugLoc dl = N->getDebugLoc();
813 // %conv.i = sext i32 %tmp1 to i64
814 // %conv2.i = sext i32 %add to i64
815 // %mul.i = mul nsw i64 %conv2.i, %conv.i
817 // --- match with the following ---
819 // %mul.i = mpy (%tmp1, %add)
822 if (N->getValueType(0) == MVT::i64) {
823 // Shifting a i64 signed multiply.
824 SDValue MulOp0 = N->getOperand(0);
825 SDValue MulOp1 = N->getOperand(1);
830 // Handle sign_extend and sextload.
831 if (MulOp0.getOpcode() == ISD::SIGN_EXTEND) {
832 SDValue Sext0 = MulOp0.getOperand(0);
833 if (Sext0.getNode()->getValueType(0) != MVT::i32) {
834 return SelectCode(N);
838 } else if (MulOp0.getOpcode() == ISD::LOAD) {
839 LoadSDNode *LD = cast<LoadSDNode>(MulOp0.getNode());
840 if (LD->getMemoryVT() != MVT::i32 ||
841 LD->getExtensionType() != ISD::SEXTLOAD ||
842 LD->getAddressingMode() != ISD::UNINDEXED) {
843 return SelectCode(N);
846 SDValue Chain = LD->getChain();
847 SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
848 OP0 = SDValue (CurDAG->getMachineNode(Hexagon::LDriw, dl, MVT::i32,
850 LD->getBasePtr(), TargetConst0,
853 return SelectCode(N);
856 // Same goes for the second operand.
857 if (MulOp1.getOpcode() == ISD::SIGN_EXTEND) {
858 SDValue Sext1 = MulOp1.getOperand(0);
859 if (Sext1.getNode()->getValueType(0) != MVT::i32) {
860 return SelectCode(N);
864 } else if (MulOp1.getOpcode() == ISD::LOAD) {
865 LoadSDNode *LD = cast<LoadSDNode>(MulOp1.getNode());
866 if (LD->getMemoryVT() != MVT::i32 ||
867 LD->getExtensionType() != ISD::SEXTLOAD ||
868 LD->getAddressingMode() != ISD::UNINDEXED) {
869 return SelectCode(N);
872 SDValue Chain = LD->getChain();
873 SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
874 OP1 = SDValue (CurDAG->getMachineNode(Hexagon::LDriw, dl, MVT::i32,
876 LD->getBasePtr(), TargetConst0,
879 return SelectCode(N);
882 // Generate a mpy instruction.
883 SDNode *Result = CurDAG->getMachineNode(Hexagon::MPY64, dl, MVT::i64,
885 ReplaceUses(N, Result);
889 return SelectCode(N);
893 SDNode *HexagonDAGToDAGISel::SelectSelect(SDNode *N) {
894 DebugLoc dl = N->getDebugLoc();
895 SDValue N0 = N->getOperand(0);
896 if (N0.getOpcode() == ISD::SETCC) {
897 SDValue N00 = N0.getOperand(0);
898 if (N00.getOpcode() == ISD::SIGN_EXTEND_INREG) {
899 SDValue N000 = N00.getOperand(0);
900 SDValue N001 = N00.getOperand(1);
901 if (cast<VTSDNode>(N001)->getVT() == MVT::i16) {
902 SDValue N01 = N0.getOperand(1);
903 SDValue N02 = N0.getOperand(2);
905 // Pattern: (select:i32 (setcc:i1 (sext_inreg:i32 IntRegs:i32:$src2,
906 // i16:Other),IntRegs:i32:$src1, SETLT:Other),IntRegs:i32:$src1,
907 // IntRegs:i32:$src2)
908 // Emits: (MAXh_rr:i32 IntRegs:i32:$src1, IntRegs:i32:$src2)
909 // Pattern complexity = 9 cost = 1 size = 0.
910 if (cast<CondCodeSDNode>(N02)->get() == ISD::SETLT) {
911 SDValue N1 = N->getOperand(1);
913 SDValue N2 = N->getOperand(2);
915 N0.getNode()->getValueType(N0.getResNo()) == MVT::i1 &&
916 N00.getNode()->getValueType(N00.getResNo()) == MVT::i32) {
917 SDNode *SextNode = CurDAG->getMachineNode(Hexagon::SXTH, dl,
919 SDNode *Result = CurDAG->getMachineNode(Hexagon::MAXw_rr, dl,
921 SDValue(SextNode, 0),
923 ReplaceUses(N, Result);
929 // Pattern: (select:i32 (setcc:i1 (sext_inreg:i32 IntRegs:i32:$src2,
930 // i16:Other), IntRegs:i32:$src1, SETGT:Other), IntRegs:i32:$src1,
931 // IntRegs:i32:$src2)
932 // Emits: (MINh_rr:i32 IntRegs:i32:$src1, IntRegs:i32:$src2)
933 // Pattern complexity = 9 cost = 1 size = 0.
934 if (cast<CondCodeSDNode>(N02)->get() == ISD::SETGT) {
935 SDValue N1 = N->getOperand(1);
937 SDValue N2 = N->getOperand(2);
939 N0.getNode()->getValueType(N0.getResNo()) == MVT::i1 &&
940 N00.getNode()->getValueType(N00.getResNo()) == MVT::i32) {
941 SDNode *SextNode = CurDAG->getMachineNode(Hexagon::SXTH, dl,
943 SDNode *Result = CurDAG->getMachineNode(Hexagon::MINw_rr, dl,
945 SDValue(SextNode, 0),
947 ReplaceUses(N, Result);
956 return SelectCode(N);
960 SDNode *HexagonDAGToDAGISel::SelectTruncate(SDNode *N) {
961 DebugLoc dl = N->getDebugLoc();
962 SDValue Shift = N->getOperand(0);
965 // %conv.i = sext i32 %tmp1 to i64
966 // %conv2.i = sext i32 %add to i64
967 // %mul.i = mul nsw i64 %conv2.i, %conv.i
968 // %shr5.i = lshr i64 %mul.i, 32
969 // %conv3.i = trunc i64 %shr5.i to i32
971 // --- match with the following ---
973 // %conv3.i = mpy (%tmp1, %add)
976 if (N->getValueType(0) == MVT::i32) {
978 if (Shift.getNode()->getValueType(0) == MVT::i64) {
979 // Trunc child is logical shift right.
980 if (Shift.getOpcode() != ISD::SRL) {
981 return SelectCode(N);
984 SDValue ShiftOp0 = Shift.getOperand(0);
985 SDValue ShiftOp1 = Shift.getOperand(1);
988 if (ShiftOp1.getOpcode() != ISD::Constant) {
989 return SelectCode(N);
993 cast<ConstantSDNode>(ShiftOp1.getNode())->getSExtValue();
994 if (ShiftConst != 32) {
995 return SelectCode(N);
998 // Shifting a i64 signed multiply
999 SDValue Mul = ShiftOp0;
1000 if (Mul.getOpcode() != ISD::MUL) {
1001 return SelectCode(N);
1004 SDValue MulOp0 = Mul.getOperand(0);
1005 SDValue MulOp1 = Mul.getOperand(1);
1010 // Handle sign_extend and sextload
1011 if (MulOp0.getOpcode() == ISD::SIGN_EXTEND) {
1012 SDValue Sext0 = MulOp0.getOperand(0);
1013 if (Sext0.getNode()->getValueType(0) != MVT::i32) {
1014 return SelectCode(N);
1018 } else if (MulOp0.getOpcode() == ISD::LOAD) {
1019 LoadSDNode *LD = cast<LoadSDNode>(MulOp0.getNode());
1020 if (LD->getMemoryVT() != MVT::i32 ||
1021 LD->getExtensionType() != ISD::SEXTLOAD ||
1022 LD->getAddressingMode() != ISD::UNINDEXED) {
1023 return SelectCode(N);
1026 SDValue Chain = LD->getChain();
1027 SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
1028 OP0 = SDValue (CurDAG->getMachineNode(Hexagon::LDriw, dl, MVT::i32,
1031 TargetConst0, Chain), 0);
1033 return SelectCode(N);
1036 // Same goes for the second operand.
1037 if (MulOp1.getOpcode() == ISD::SIGN_EXTEND) {
1038 SDValue Sext1 = MulOp1.getOperand(0);
1039 if (Sext1.getNode()->getValueType(0) != MVT::i32)
1040 return SelectCode(N);
1043 } else if (MulOp1.getOpcode() == ISD::LOAD) {
1044 LoadSDNode *LD = cast<LoadSDNode>(MulOp1.getNode());
1045 if (LD->getMemoryVT() != MVT::i32 ||
1046 LD->getExtensionType() != ISD::SEXTLOAD ||
1047 LD->getAddressingMode() != ISD::UNINDEXED) {
1048 return SelectCode(N);
1051 SDValue Chain = LD->getChain();
1052 SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
1053 OP1 = SDValue (CurDAG->getMachineNode(Hexagon::LDriw, dl, MVT::i32,
1056 TargetConst0, Chain), 0);
1058 return SelectCode(N);
1061 // Generate a mpy instruction.
1062 SDNode *Result = CurDAG->getMachineNode(Hexagon::MPY, dl, MVT::i32,
1064 ReplaceUses(N, Result);
1069 return SelectCode(N);
1073 SDNode *HexagonDAGToDAGISel::SelectSHL(SDNode *N) {
1074 DebugLoc dl = N->getDebugLoc();
1075 if (N->getValueType(0) == MVT::i32) {
1076 SDValue Shl_0 = N->getOperand(0);
1077 SDValue Shl_1 = N->getOperand(1);
1079 if (Shl_1.getOpcode() == ISD::Constant) {
1080 if (Shl_0.getOpcode() == ISD::MUL) {
1081 SDValue Mul_0 = Shl_0.getOperand(0); // Val
1082 SDValue Mul_1 = Shl_0.getOperand(1); // Const
1083 // RHS of mul is const.
1084 if (Mul_1.getOpcode() == ISD::Constant) {
1086 cast<ConstantSDNode>(Shl_1.getNode())->getSExtValue();
1088 cast<ConstantSDNode>(Mul_1.getNode())->getSExtValue();
1089 int32_t ValConst = MulConst << ShlConst;
1090 SDValue Val = CurDAG->getTargetConstant(ValConst,
1092 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Val.getNode()))
1093 if (isInt<9>(CN->getSExtValue())) {
1095 CurDAG->getMachineNode(Hexagon::MPYI_ri, dl,
1096 MVT::i32, Mul_0, Val);
1097 ReplaceUses(N, Result);
1102 } else if (Shl_0.getOpcode() == ISD::SUB) {
1103 SDValue Sub_0 = Shl_0.getOperand(0); // Const 0
1104 SDValue Sub_1 = Shl_0.getOperand(1); // Val
1105 if (Sub_0.getOpcode() == ISD::Constant) {
1107 cast<ConstantSDNode>(Sub_0.getNode())->getSExtValue();
1108 if (SubConst == 0) {
1109 if (Sub_1.getOpcode() == ISD::SHL) {
1110 SDValue Shl2_0 = Sub_1.getOperand(0); // Val
1111 SDValue Shl2_1 = Sub_1.getOperand(1); // Const
1112 if (Shl2_1.getOpcode() == ISD::Constant) {
1114 cast<ConstantSDNode>(Shl_1.getNode())->getSExtValue();
1116 cast<ConstantSDNode>(Shl2_1.getNode())->getSExtValue();
1117 int32_t ValConst = 1 << (ShlConst+Shl2Const);
1118 SDValue Val = CurDAG->getTargetConstant(-ValConst, MVT::i32);
1119 if (ConstantSDNode *CN =
1120 dyn_cast<ConstantSDNode>(Val.getNode()))
1121 if (isInt<9>(CN->getSExtValue())) {
1123 CurDAG->getMachineNode(Hexagon::MPYI_ri, dl, MVT::i32,
1125 ReplaceUses(N, Result);
1135 return SelectCode(N);
1140 // If there is an zero_extend followed an intrinsic in DAG (this means - the
1141 // result of the intrinsic is predicate); convert the zero_extend to
1142 // transfer instruction.
1144 // Zero extend -> transfer is lowered here. Otherwise, zero_extend will be
1145 // converted into a MUX as predicate registers defined as 1 bit in the
1146 // compiler. Architecture defines them as 8-bit registers.
1147 // We want to preserve all the lower 8-bits and, not just 1 LSB bit.
1149 SDNode *HexagonDAGToDAGISel::SelectZeroExtend(SDNode *N) {
1150 DebugLoc dl = N->getDebugLoc();
1151 SDNode *IsIntrinsic = N->getOperand(0).getNode();
1152 if ((IsIntrinsic->getOpcode() == ISD::INTRINSIC_WO_CHAIN)) {
1154 cast<ConstantSDNode>(IsIntrinsic->getOperand(0))->getZExtValue();
1155 if (doesIntrinsicReturnPredicate(ID)) {
1156 // Now we need to differentiate target data types.
1157 if (N->getValueType(0) == MVT::i64) {
1158 // Convert the zero_extend to Rs = Pd followed by COMBINE_rr(0,Rs).
1159 SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
1160 SDNode *Result_1 = CurDAG->getMachineNode(Hexagon::TFR_RsPd, dl,
1162 SDValue(IsIntrinsic, 0));
1163 SDNode *Result_2 = CurDAG->getMachineNode(Hexagon::TFRI, dl,
1166 SDNode *Result_3 = CurDAG->getMachineNode(Hexagon::COMBINE_rr, dl,
1167 MVT::i64, MVT::Other,
1168 SDValue(Result_2, 0),
1169 SDValue(Result_1, 0));
1170 ReplaceUses(N, Result_3);
1173 if (N->getValueType(0) == MVT::i32) {
1174 // Convert the zero_extend to Rs = Pd
1175 SDNode* RsPd = CurDAG->getMachineNode(Hexagon::TFR_RsPd, dl,
1177 SDValue(IsIntrinsic, 0));
1178 ReplaceUses(N, RsPd);
1181 llvm_unreachable("Unexpected value type");
1184 return SelectCode(N);
1189 // Checking for intrinsics which have predicate registers as operand(s)
1190 // and lowering to the actual intrinsic.
1192 SDNode *HexagonDAGToDAGISel::SelectIntrinsicWOChain(SDNode *N) {
1193 DebugLoc dl = N->getDebugLoc();
1194 unsigned ID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
1195 unsigned IntrinsicWithPred = doesIntrinsicContainPredicate(ID);
1197 // We are concerned with only those intrinsics that have predicate registers
1198 // as at least one of the operands.
1199 if (IntrinsicWithPred) {
1200 SmallVector<SDValue, 8> Ops;
1201 const MCInstrDesc &MCID = TII->get(IntrinsicWithPred);
1202 const TargetRegisterInfo *TRI = TM.getRegisterInfo();
1204 // Iterate over all the operands of the intrinsics.
1205 // For PredRegs, do the transfer.
1206 // For Double/Int Regs, just preserve the value
1207 // For immediates, lower it.
1208 for (unsigned i = 1; i < N->getNumOperands(); ++i) {
1209 SDNode *Arg = N->getOperand(i).getNode();
1210 const TargetRegisterClass *RC = TII->getRegClass(MCID, i, TRI, *MF);
1212 if (RC == &Hexagon::IntRegsRegClass ||
1213 RC == &Hexagon::DoubleRegsRegClass) {
1214 Ops.push_back(SDValue(Arg, 0));
1215 } else if (RC == &Hexagon::PredRegsRegClass) {
1217 SDNode *PdRs = CurDAG->getMachineNode(Hexagon::TFR_PdRs, dl, MVT::i1,
1219 Ops.push_back(SDValue(PdRs,0));
1220 } else if (RC == NULL && (dyn_cast<ConstantSDNode>(Arg) != NULL)) {
1221 // This is immediate operand. Lower it here making sure that we DO have
1222 // const SDNode for immediate value.
1223 int32_t Val = cast<ConstantSDNode>(Arg)->getSExtValue();
1224 SDValue SDVal = CurDAG->getTargetConstant(Val, MVT::i32);
1225 Ops.push_back(SDVal);
1227 llvm_unreachable("Unimplemented");
1230 EVT ReturnValueVT = N->getValueType(0);
1231 SDNode *Result = CurDAG->getMachineNode(IntrinsicWithPred, dl,
1232 ReturnValueVT, Ops);
1233 ReplaceUses(N, Result);
1236 return SelectCode(N);
1240 // Map floating point constant values.
1242 SDNode *HexagonDAGToDAGISel::SelectConstantFP(SDNode *N) {
1243 DebugLoc dl = N->getDebugLoc();
1244 ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);
1245 APFloat APF = CN->getValueAPF();
1246 if (N->getValueType(0) == MVT::f32) {
1247 return CurDAG->getMachineNode(Hexagon::TFRI_f, dl, MVT::f32,
1248 CurDAG->getTargetConstantFP(APF.convertToFloat(), MVT::f32));
1250 else if (N->getValueType(0) == MVT::f64) {
1251 return CurDAG->getMachineNode(Hexagon::CONST64_Float_Real, dl, MVT::f64,
1252 CurDAG->getTargetConstantFP(APF.convertToDouble(), MVT::f64));
1255 return SelectCode(N);
1260 // Map predicate true (encoded as -1 in LLVM) to a XOR.
1262 SDNode *HexagonDAGToDAGISel::SelectConstant(SDNode *N) {
1263 DebugLoc dl = N->getDebugLoc();
1264 if (N->getValueType(0) == MVT::i1) {
1266 int32_t Val = cast<ConstantSDNode>(N)->getSExtValue();
1268 // Create the IntReg = 1 node.
1270 CurDAG->getMachineNode(Hexagon::TFRI, dl, MVT::i32,
1271 CurDAG->getTargetConstant(0, MVT::i32));
1274 SDNode* Pd = CurDAG->getMachineNode(Hexagon::TFR_PdRs, dl, MVT::i1,
1275 SDValue(IntRegTFR, 0));
1278 SDNode* NotPd = CurDAG->getMachineNode(Hexagon::NOT_p, dl, MVT::i1,
1282 Result = CurDAG->getMachineNode(Hexagon::XOR_pp, dl, MVT::i1,
1283 SDValue(Pd, 0), SDValue(NotPd, 0));
1285 // We have just built:
1287 // Pd = xor(not(Pd), Pd)
1289 ReplaceUses(N, Result);
1294 return SelectCode(N);
1299 // Map add followed by a asr -> asr +=.
1301 SDNode *HexagonDAGToDAGISel::SelectAdd(SDNode *N) {
1302 DebugLoc dl = N->getDebugLoc();
1303 if (N->getValueType(0) != MVT::i32) {
1304 return SelectCode(N);
1306 // Identify nodes of the form: add(asr(...)).
1307 SDNode* Src1 = N->getOperand(0).getNode();
1308 if (Src1->getOpcode() != ISD::SRA || !Src1->hasOneUse()
1309 || Src1->getValueType(0) != MVT::i32) {
1310 return SelectCode(N);
1313 // Build Rd = Rd' + asr(Rs, Rt). The machine constraints will ensure that
1314 // Rd and Rd' are assigned to the same register
1315 SDNode* Result = CurDAG->getMachineNode(Hexagon::ASR_ADD_rr, dl, MVT::i32,
1317 Src1->getOperand(0),
1318 Src1->getOperand(1));
1319 ReplaceUses(N, Result);
1325 SDNode *HexagonDAGToDAGISel::Select(SDNode *N) {
1326 if (N->isMachineOpcode())
1327 return NULL; // Already selected.
1330 switch (N->getOpcode()) {
1332 return SelectConstant(N);
1334 case ISD::ConstantFP:
1335 return SelectConstantFP(N);
1338 return SelectAdd(N);
1341 return SelectSHL(N);
1344 return SelectLoad(N);
1347 return SelectStore(N);
1350 return SelectSelect(N);
1353 return SelectTruncate(N);
1356 return SelectMul(N);
1358 case ISD::ZERO_EXTEND:
1359 return SelectZeroExtend(N);
1361 case ISD::INTRINSIC_WO_CHAIN:
1362 return SelectIntrinsicWOChain(N);
1365 return SelectCode(N);
1370 // Hexagon_TODO: Five functions for ADDRri?! Surely there must be a better way
1371 // to define these instructions.
1373 bool HexagonDAGToDAGISel::SelectADDRri(SDValue& Addr, SDValue &Base,
1375 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
1376 Addr.getOpcode() == ISD::TargetGlobalAddress)
1377 return false; // Direct calls.
1379 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
1380 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
1381 Offset = CurDAG->getTargetConstant(0, MVT::i32);
1385 Offset = CurDAG->getTargetConstant(0, MVT::i32);
1390 bool HexagonDAGToDAGISel::SelectADDRriS11_0(SDValue& Addr, SDValue &Base,
1392 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
1393 Addr.getOpcode() == ISD::TargetGlobalAddress)
1394 return false; // Direct calls.
1396 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
1397 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
1398 Offset = CurDAG->getTargetConstant(0, MVT::i32);
1399 return (IsS11_0_Offset(Offset.getNode()));
1402 Offset = CurDAG->getTargetConstant(0, MVT::i32);
1403 return (IsS11_0_Offset(Offset.getNode()));
1407 bool HexagonDAGToDAGISel::SelectADDRriS11_1(SDValue& Addr, SDValue &Base,
1409 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
1410 Addr.getOpcode() == ISD::TargetGlobalAddress)
1411 return false; // Direct calls.
1413 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
1414 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
1415 Offset = CurDAG->getTargetConstant(0, MVT::i32);
1416 return (IsS11_1_Offset(Offset.getNode()));
1419 Offset = CurDAG->getTargetConstant(0, MVT::i32);
1420 return (IsS11_1_Offset(Offset.getNode()));
1424 bool HexagonDAGToDAGISel::SelectADDRriS11_2(SDValue& Addr, SDValue &Base,
1426 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
1427 Addr.getOpcode() == ISD::TargetGlobalAddress)
1428 return false; // Direct calls.
1430 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
1431 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
1432 Offset = CurDAG->getTargetConstant(0, MVT::i32);
1433 return (IsS11_2_Offset(Offset.getNode()));
1436 Offset = CurDAG->getTargetConstant(0, MVT::i32);
1437 return (IsS11_2_Offset(Offset.getNode()));
1441 bool HexagonDAGToDAGISel::SelectADDRriU6_0(SDValue& Addr, SDValue &Base,
1443 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
1444 Addr.getOpcode() == ISD::TargetGlobalAddress)
1445 return false; // Direct calls.
1447 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
1448 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
1449 Offset = CurDAG->getTargetConstant(0, MVT::i32);
1450 return (IsU6_0_Offset(Offset.getNode()));
1453 Offset = CurDAG->getTargetConstant(0, MVT::i32);
1454 return (IsU6_0_Offset(Offset.getNode()));
1458 bool HexagonDAGToDAGISel::SelectADDRriU6_1(SDValue& Addr, SDValue &Base,
1460 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
1461 Addr.getOpcode() == ISD::TargetGlobalAddress)
1462 return false; // Direct calls.
1464 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
1465 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
1466 Offset = CurDAG->getTargetConstant(0, MVT::i32);
1467 return (IsU6_1_Offset(Offset.getNode()));
1470 Offset = CurDAG->getTargetConstant(0, MVT::i32);
1471 return (IsU6_1_Offset(Offset.getNode()));
1475 bool HexagonDAGToDAGISel::SelectADDRriU6_2(SDValue& Addr, SDValue &Base,
1477 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
1478 Addr.getOpcode() == ISD::TargetGlobalAddress)
1479 return false; // Direct calls.
1481 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
1482 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
1483 Offset = CurDAG->getTargetConstant(0, MVT::i32);
1484 return (IsU6_2_Offset(Offset.getNode()));
1487 Offset = CurDAG->getTargetConstant(0, MVT::i32);
1488 return (IsU6_2_Offset(Offset.getNode()));
1492 bool HexagonDAGToDAGISel::SelectMEMriS11_2(SDValue& Addr, SDValue &Base,
1495 if (Addr.getOpcode() != ISD::ADD) {
1496 return(SelectADDRriS11_2(Addr, Base, Offset));
1499 return SelectADDRriS11_2(Addr, Base, Offset);
1503 bool HexagonDAGToDAGISel::SelectADDRriS11_3(SDValue& Addr, SDValue &Base,
1505 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
1506 Addr.getOpcode() == ISD::TargetGlobalAddress)
1507 return false; // Direct calls.
1509 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
1510 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
1511 Offset = CurDAG->getTargetConstant(0, MVT::i32);
1512 return (IsS11_3_Offset(Offset.getNode()));
1515 Offset = CurDAG->getTargetConstant(0, MVT::i32);
1516 return (IsS11_3_Offset(Offset.getNode()));
1519 bool HexagonDAGToDAGISel::SelectADDRrr(SDValue &Addr, SDValue &R1,
1521 if (Addr.getOpcode() == ISD::FrameIndex) return false;
1522 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
1523 Addr.getOpcode() == ISD::TargetGlobalAddress)
1524 return false; // Direct calls.
1526 if (Addr.getOpcode() == ISD::ADD) {
1527 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
1528 if (isInt<13>(CN->getSExtValue()))
1529 return false; // Let the reg+imm pattern catch this!
1530 R1 = Addr.getOperand(0);
1531 R2 = Addr.getOperand(1);
1541 // Handle generic address case. It is accessed from inlined asm =m constraints,
1542 // which could have any kind of pointer.
1543 bool HexagonDAGToDAGISel::SelectAddr(SDNode *Op, SDValue Addr,
1544 SDValue &Base, SDValue &Offset) {
1545 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
1546 Addr.getOpcode() == ISD::TargetGlobalAddress)
1547 return false; // Direct calls.
1549 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
1550 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
1551 Offset = CurDAG->getTargetConstant(0, MVT::i32);
1555 if (Addr.getOpcode() == ISD::ADD) {
1556 Base = Addr.getOperand(0);
1557 Offset = Addr.getOperand(1);
1562 Offset = CurDAG->getTargetConstant(0, MVT::i32);
1567 bool HexagonDAGToDAGISel::
1568 SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
1569 std::vector<SDValue> &OutOps) {
1572 switch (ConstraintCode) {
1573 case 'o': // Offsetable.
1574 case 'v': // Not offsetable.
1575 default: return true;
1576 case 'm': // Memory.
1577 if (!SelectAddr(Op.getNode(), Op, Op0, Op1))
1582 OutOps.push_back(Op0);
1583 OutOps.push_back(Op1);
1587 bool HexagonDAGToDAGISel::isConstExtProfitable(SDNode *N) const {
1588 unsigned UseCount = 0;
1589 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
1593 return (UseCount <= 1);
1597 //===--------------------------------------------------------------------===//
1598 // Return 'true' if use count of the global address is below threshold.
1599 //===--------------------------------------------------------------------===//
1600 bool HexagonDAGToDAGISel::hasNumUsesBelowThresGA(SDNode *N) const {
1601 assert(N->getOpcode() == ISD::TargetGlobalAddress &&
1602 "Expecting a target global address");
1604 // Always try to fold the address.
1605 if (TM.getOptLevel() == CodeGenOpt::Aggressive)
1608 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(N);
1609 DenseMap<const GlobalValue *, unsigned>::const_iterator GI =
1610 GlobalAddressUseCountMap.find(GA->getGlobal());
1612 if (GI == GlobalAddressUseCountMap.end())
1615 return GI->second <= MaxNumOfUsesForConstExtenders;
1618 //===--------------------------------------------------------------------===//
1619 // Return true if the non GP-relative global address can be folded.
1620 //===--------------------------------------------------------------------===//
1621 inline bool HexagonDAGToDAGISel::foldGlobalAddress(SDValue &N, SDValue &R) {
1622 return foldGlobalAddressImpl(N, R, false);
1625 //===--------------------------------------------------------------------===//
1626 // Return true if the GP-relative global address can be folded.
1627 //===--------------------------------------------------------------------===//
1628 inline bool HexagonDAGToDAGISel::foldGlobalAddressGP(SDValue &N, SDValue &R) {
1629 return foldGlobalAddressImpl(N, R, true);
1632 //===--------------------------------------------------------------------===//
1633 // Fold offset of the global address if number of uses are below threshold.
1634 //===--------------------------------------------------------------------===//
1635 bool HexagonDAGToDAGISel::foldGlobalAddressImpl(SDValue &N, SDValue &R,
1636 bool ShouldLookForGP) {
1637 if (N.getOpcode() == ISD::ADD) {
1638 SDValue N0 = N.getOperand(0);
1639 SDValue N1 = N.getOperand(1);
1640 if ((ShouldLookForGP && (N0.getOpcode() == HexagonISD::CONST32_GP)) ||
1641 (!ShouldLookForGP && (N0.getOpcode() == HexagonISD::CONST32))) {
1642 ConstantSDNode *Const = dyn_cast<ConstantSDNode>(N1);
1643 GlobalAddressSDNode *GA =
1644 dyn_cast<GlobalAddressSDNode>(N0.getOperand(0));
1647 (GA->getOpcode() == ISD::TargetGlobalAddress)) {
1648 if ((N0.getOpcode() == HexagonISD::CONST32) &&
1649 !hasNumUsesBelowThresGA(GA))
1651 R = CurDAG->getTargetGlobalAddress(GA->getGlobal(),
1652 Const->getDebugLoc(),
1655 (uint64_t)Const->getSExtValue());