1 //===------- HexagonCopyToCombine.cpp - Hexagon Copy-To-Combine Pass ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
9 // This pass replaces transfer instructions by combine instructions.
10 // We walk along a basic block and look for two combinable instructions and try
11 // to move them together. If we can move them next to each other we do so and
12 // replace them with a combine instruction.
13 //===----------------------------------------------------------------------===//
14 #include "llvm/PassSupport.h"
16 #include "HexagonInstrInfo.h"
17 #include "HexagonMachineFunctionInfo.h"
18 #include "HexagonRegisterInfo.h"
19 #include "HexagonSubtarget.h"
20 #include "HexagonTargetMachine.h"
21 #include "llvm/ADT/DenseMap.h"
22 #include "llvm/ADT/DenseSet.h"
23 #include "llvm/CodeGen/MachineBasicBlock.h"
24 #include "llvm/CodeGen/MachineFunction.h"
25 #include "llvm/CodeGen/MachineFunctionPass.h"
26 #include "llvm/CodeGen/MachineInstr.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/Passes.h"
29 #include "llvm/Support/CodeGen.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/raw_ostream.h"
33 #include "llvm/Target/TargetRegisterInfo.h"
37 #define DEBUG_TYPE "hexagon-copy-combine"
40 cl::opt<bool> IsCombinesDisabled("disable-merge-into-combines",
41 cl::Hidden, cl::ZeroOrMore,
43 cl::desc("Disable merging into combines"));
46 MaxNumOfInstsBetweenNewValueStoreAndTFR("max-num-inst-between-tfr-and-nv-store",
47 cl::Hidden, cl::init(4),
48 cl::desc("Maximum distance between a tfr feeding a store we "
49 "consider the store still to be newifiable"));
52 void initializeHexagonCopyToCombinePass(PassRegistry&);
58 class HexagonCopyToCombine : public MachineFunctionPass {
59 const HexagonInstrInfo *TII;
60 const TargetRegisterInfo *TRI;
61 bool ShouldCombineAggressively;
63 DenseSet<MachineInstr *> PotentiallyNewifiableTFR;
67 HexagonCopyToCombine() : MachineFunctionPass(ID) {
68 initializeHexagonCopyToCombinePass(*PassRegistry::getPassRegistry());
71 void getAnalysisUsage(AnalysisUsage &AU) const override {
72 MachineFunctionPass::getAnalysisUsage(AU);
75 const char *getPassName() const override {
76 return "Hexagon Copy-To-Combine Pass";
79 bool runOnMachineFunction(MachineFunction &Fn) override;
82 MachineInstr *findPairable(MachineInstr *I1, bool &DoInsertAtI1);
84 void findPotentialNewifiableTFRs(MachineBasicBlock &);
86 void combine(MachineInstr *I1, MachineInstr *I2,
87 MachineBasicBlock::iterator &MI, bool DoInsertAtI1);
89 bool isSafeToMoveTogether(MachineInstr *I1, MachineInstr *I2,
90 unsigned I1DestReg, unsigned I2DestReg,
93 void emitCombineRR(MachineBasicBlock::iterator &Before, unsigned DestReg,
94 MachineOperand &HiOperand, MachineOperand &LoOperand);
96 void emitCombineRI(MachineBasicBlock::iterator &Before, unsigned DestReg,
97 MachineOperand &HiOperand, MachineOperand &LoOperand);
99 void emitCombineIR(MachineBasicBlock::iterator &Before, unsigned DestReg,
100 MachineOperand &HiOperand, MachineOperand &LoOperand);
102 void emitCombineII(MachineBasicBlock::iterator &Before, unsigned DestReg,
103 MachineOperand &HiOperand, MachineOperand &LoOperand);
106 } // End anonymous namespace.
108 char HexagonCopyToCombine::ID = 0;
110 INITIALIZE_PASS(HexagonCopyToCombine, "hexagon-copy-combine",
111 "Hexagon Copy-To-Combine Pass", false, false)
113 static bool isCombinableInstType(MachineInstr *MI,
114 const HexagonInstrInfo *TII,
115 bool ShouldCombineAggressively) {
116 switch(MI->getOpcode()) {
117 case Hexagon::A2_tfr: {
118 // A COPY instruction can be combined if its arguments are IntRegs (32bit).
119 const MachineOperand &Op0 = MI->getOperand(0);
120 const MachineOperand &Op1 = MI->getOperand(1);
121 assert(Op0.isReg() && Op1.isReg());
123 unsigned DestReg = Op0.getReg();
124 unsigned SrcReg = Op1.getReg();
125 return Hexagon::IntRegsRegClass.contains(DestReg) &&
126 Hexagon::IntRegsRegClass.contains(SrcReg);
129 case Hexagon::A2_tfrsi: {
130 // A transfer-immediate can be combined if its argument is a signed 8bit
132 const MachineOperand &Op0 = MI->getOperand(0);
133 const MachineOperand &Op1 = MI->getOperand(1);
136 unsigned DestReg = Op0.getReg();
137 // Ensure that TargetFlags are MO_NO_FLAG for a global. This is a
138 // workaround for an ABI bug that prevents GOT relocations on combine
140 if (!Op1.isImm() && Op1.getTargetFlags() != HexagonII::MO_NO_FLAG)
143 // Only combine constant extended A2_tfrsi if we are in aggressive mode.
144 bool NotExt = Op1.isImm() && isInt<8>(Op1.getImm());
145 return Hexagon::IntRegsRegClass.contains(DestReg) &&
146 (ShouldCombineAggressively || NotExt);
156 template <unsigned N>
157 static bool isGreaterThanNBitTFRI(const MachineInstr *I) {
158 if (I->getOpcode() == Hexagon::TFRI64_V4 ||
159 I->getOpcode() == Hexagon::A2_tfrsi) {
160 const MachineOperand &Op = I->getOperand(1);
161 return !Op.isImm() || !isInt<N>(Op.getImm());
166 /// areCombinableOperations - Returns true if the two instruction can be merge
167 /// into a combine (ignoring register constraints).
168 static bool areCombinableOperations(const TargetRegisterInfo *TRI,
169 MachineInstr *HighRegInst,
170 MachineInstr *LowRegInst) {
171 unsigned HiOpc = HighRegInst->getOpcode();
172 unsigned LoOpc = LowRegInst->getOpcode();
173 assert((HiOpc == Hexagon::A2_tfr || HiOpc == Hexagon::A2_tfrsi) &&
174 (LoOpc == Hexagon::A2_tfr || LoOpc == Hexagon::A2_tfrsi) &&
175 "Assume individual instructions are of a combinable type");
177 // There is no combine of two constant extended values.
178 if (isGreaterThanNBitTFRI<8>(HighRegInst) &&
179 isGreaterThanNBitTFRI<6>(LowRegInst))
185 static bool isEvenReg(unsigned Reg) {
186 assert(TargetRegisterInfo::isPhysicalRegister(Reg) &&
187 Hexagon::IntRegsRegClass.contains(Reg));
188 return (Reg - Hexagon::R0) % 2 == 0;
191 static void removeKillInfo(MachineInstr *MI, unsigned RegNotKilled) {
192 for (unsigned I = 0, E = MI->getNumOperands(); I != E; ++I) {
193 MachineOperand &Op = MI->getOperand(I);
194 if (!Op.isReg() || Op.getReg() != RegNotKilled || !Op.isKill())
200 /// isUnsafeToMoveAcross - Returns true if it is unsafe to move a copy
201 /// instruction from \p UseReg to \p DestReg over the instruction \p I.
202 static bool isUnsafeToMoveAcross(MachineInstr *I, unsigned UseReg,
204 const TargetRegisterInfo *TRI) {
205 return (UseReg && (I->modifiesRegister(UseReg, TRI))) ||
206 I->modifiesRegister(DestReg, TRI) ||
207 I->readsRegister(DestReg, TRI) ||
208 I->hasUnmodeledSideEffects() ||
209 I->isInlineAsm() || I->isDebugValue();
212 static unsigned UseReg(const MachineOperand& MO) {
213 return MO.isReg() ? MO.getReg() : 0;
216 /// isSafeToMoveTogether - Returns true if it is safe to move I1 next to I2 such
217 /// that the two instructions can be paired in a combine.
218 bool HexagonCopyToCombine::isSafeToMoveTogether(MachineInstr *I1,
222 bool &DoInsertAtI1) {
223 unsigned I2UseReg = UseReg(I2->getOperand(1));
225 // It is not safe to move I1 and I2 into one combine if I2 has a true
227 if (I2UseReg && I1->modifiesRegister(I2UseReg, TRI))
232 // First try to move I2 towards I1.
234 // A reverse_iterator instantiated like below starts before I2, and I1
236 // Look at instructions I in between I2 and (excluding) I1.
237 MachineBasicBlock::reverse_iterator I(I2),
238 End = --(MachineBasicBlock::reverse_iterator(I1));
239 // At 03 we got better results (dhrystone!) by being more conservative.
240 if (!ShouldCombineAggressively)
241 End = MachineBasicBlock::reverse_iterator(I1);
242 // If I2 kills its operand and we move I2 over an instruction that also
243 // uses I2's use reg we need to modify that (first) instruction to now kill
245 unsigned KilledOperand = 0;
246 if (I2->killsRegister(I2UseReg))
247 KilledOperand = I2UseReg;
248 MachineInstr *KillingInstr = nullptr;
250 for (; I != End; ++I) {
251 // If the intervening instruction I:
252 // * modifies I2's use reg
253 // * modifies I2's def reg
254 // * reads I2's def reg
255 // * or has unmodelled side effects
256 // we can't move I2 across it.
257 if (isUnsafeToMoveAcross(&*I, I2UseReg, I2DestReg, TRI)) {
262 // Update first use of the killed operand.
263 if (!KillingInstr && KilledOperand &&
264 I->readsRegister(KilledOperand, TRI))
268 // Update the intermediate instruction to with the kill flag.
270 bool Added = KillingInstr->addRegisterKilled(KilledOperand, TRI, true);
271 (void)Added; // suppress compiler warning
272 assert(Added && "Must successfully update kill flag");
273 removeKillInfo(I2, KilledOperand);
280 // Try to move I1 towards I2.
282 // Look at instructions I in between I1 and (excluding) I2.
283 MachineBasicBlock::iterator I(I1), End(I2);
284 // At O3 we got better results (dhrystone) by being more conservative here.
285 if (!ShouldCombineAggressively)
286 End = std::next(MachineBasicBlock::iterator(I2));
287 unsigned I1UseReg = UseReg(I1->getOperand(1));
288 // Track killed operands. If we move across an instruction that kills our
289 // operand, we need to update the kill information on the moved I1. It kills
291 MachineInstr *KillingInstr = nullptr;
292 unsigned KilledOperand = 0;
295 // If the intervening instruction I:
296 // * modifies I1's use reg
297 // * modifies I1's def reg
298 // * reads I1's def reg
299 // * or has unmodelled side effects
300 // We introduce this special case because llvm has no api to remove a
301 // kill flag for a register (a removeRegisterKilled() analogous to
302 // addRegisterKilled) that handles aliased register correctly.
303 // * or has a killed aliased register use of I1's use reg
304 // %D4<def> = TFRI64 16
305 // %R6<def> = TFR %R9
306 // %R8<def> = KILL %R8, %D4<imp-use,kill>
307 // If we want to move R6 = across the KILL instruction we would have
308 // to remove the %D4<imp-use,kill> operand. For now, we are
309 // conservative and disallow the move.
310 // we can't move I1 across it.
311 if (isUnsafeToMoveAcross(I, I1UseReg, I1DestReg, TRI) ||
312 // Check for an aliased register kill. Bail out if we see one.
313 (!I->killsRegister(I1UseReg) && I->killsRegister(I1UseReg, TRI)))
316 // Check for an exact kill (registers match).
317 if (I1UseReg && I->killsRegister(I1UseReg)) {
318 assert(!KillingInstr && "Should only see one killing instruction");
319 KilledOperand = I1UseReg;
324 removeKillInfo(KillingInstr, KilledOperand);
325 // Update I1 to set the kill flag. This flag will later be picked up by
326 // the new COMBINE instruction.
327 bool Added = I1->addRegisterKilled(KilledOperand, TRI);
328 (void)Added; // suppress compiler warning
329 assert(Added && "Must successfully update kill flag");
331 DoInsertAtI1 = false;
337 /// findPotentialNewifiableTFRs - Finds tranfers that feed stores that could be
338 /// newified. (A use of a 64 bit register define can not be newified)
340 HexagonCopyToCombine::findPotentialNewifiableTFRs(MachineBasicBlock &BB) {
341 DenseMap<unsigned, MachineInstr *> LastDef;
342 for (MachineBasicBlock::iterator I = BB.begin(), E = BB.end(); I != E; ++I) {
343 MachineInstr *MI = I;
344 // Mark TFRs that feed a potential new value store as such.
345 if(TII->mayBeNewStore(MI)) {
346 // Look for uses of TFR instructions.
347 for (unsigned OpdIdx = 0, OpdE = MI->getNumOperands(); OpdIdx != OpdE;
349 MachineOperand &Op = MI->getOperand(OpdIdx);
351 // Skip over anything except register uses.
352 if (!Op.isReg() || !Op.isUse() || !Op.getReg())
355 // Look for the defining instruction.
356 unsigned Reg = Op.getReg();
357 MachineInstr *DefInst = LastDef[Reg];
360 if (!isCombinableInstType(DefInst, TII, ShouldCombineAggressively))
363 // Only close newifiable stores should influence the decision.
364 MachineBasicBlock::iterator It(DefInst);
365 unsigned NumInstsToDef = 0;
369 if (NumInstsToDef > MaxNumOfInstsBetweenNewValueStoreAndTFR)
372 PotentiallyNewifiableTFR.insert(DefInst);
374 // Skip to next instruction.
378 // Put instructions that last defined integer or double registers into the
380 for (unsigned I = 0, E = MI->getNumOperands(); I != E; ++I) {
381 MachineOperand &Op = MI->getOperand(I);
382 if (!Op.isReg() || !Op.isDef() || !Op.getReg())
384 unsigned Reg = Op.getReg();
385 if (Hexagon::DoubleRegsRegClass.contains(Reg)) {
386 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
387 LastDef[*SubRegs] = MI;
389 } else if (Hexagon::IntRegsRegClass.contains(Reg))
395 bool HexagonCopyToCombine::runOnMachineFunction(MachineFunction &MF) {
397 if (IsCombinesDisabled) return false;
399 bool HasChanged = false;
402 TRI = MF.getSubtarget().getRegisterInfo();
403 TII = MF.getSubtarget<HexagonSubtarget>().getInstrInfo();
405 // Combine aggressively (for code size)
406 ShouldCombineAggressively =
407 MF.getTarget().getOptLevel() <= CodeGenOpt::Default;
409 // Traverse basic blocks.
410 for (MachineFunction::iterator BI = MF.begin(), BE = MF.end(); BI != BE;
412 PotentiallyNewifiableTFR.clear();
413 findPotentialNewifiableTFRs(*BI);
415 // Traverse instructions in basic block.
416 for(MachineBasicBlock::iterator MI = BI->begin(), End = BI->end();
418 MachineInstr *I1 = MI++;
419 // Don't combine a TFR whose user could be newified (instructions that
420 // define double registers can not be newified - Programmer's Ref Manual
421 // 5.4.2 New-value stores).
422 if (ShouldCombineAggressively && PotentiallyNewifiableTFR.count(I1))
425 // Ignore instructions that are not combinable.
426 if (!isCombinableInstType(I1, TII, ShouldCombineAggressively))
429 // Find a second instruction that can be merged into a combine
431 bool DoInsertAtI1 = false;
432 MachineInstr *I2 = findPairable(I1, DoInsertAtI1);
435 combine(I1, I2, MI, DoInsertAtI1);
443 /// findPairable - Returns an instruction that can be merged with \p I1 into a
444 /// COMBINE instruction or 0 if no such instruction can be found. Returns true
445 /// in \p DoInsertAtI1 if the combine must be inserted at instruction \p I1
446 /// false if the combine must be inserted at the returned instruction.
447 MachineInstr *HexagonCopyToCombine::findPairable(MachineInstr *I1,
448 bool &DoInsertAtI1) {
449 MachineBasicBlock::iterator I2 = std::next(MachineBasicBlock::iterator(I1));
450 unsigned I1DestReg = I1->getOperand(0).getReg();
452 for (MachineBasicBlock::iterator End = I1->getParent()->end(); I2 != End;
454 // Bail out early if we see a second definition of I1DestReg.
455 if (I2->modifiesRegister(I1DestReg, TRI))
458 // Ignore non-combinable instructions.
459 if (!isCombinableInstType(I2, TII, ShouldCombineAggressively))
462 // Don't combine a TFR whose user could be newified.
463 if (ShouldCombineAggressively && PotentiallyNewifiableTFR.count(I2))
466 unsigned I2DestReg = I2->getOperand(0).getReg();
468 // Check that registers are adjacent and that the first destination register
470 bool IsI1LowReg = (I2DestReg - I1DestReg) == 1;
471 bool IsI2LowReg = (I1DestReg - I2DestReg) == 1;
472 unsigned FirstRegIndex = IsI1LowReg ? I1DestReg : I2DestReg;
473 if ((!IsI1LowReg && !IsI2LowReg) || !isEvenReg(FirstRegIndex))
476 // Check that the two instructions are combinable. V4 allows more
477 // instructions to be merged into a combine.
478 // The order matters because in a TFRI we might can encode a int8 as the
479 // hi reg operand but only a uint6 as the low reg operand.
480 if ((IsI2LowReg && !areCombinableOperations(TRI, I1, I2)) ||
481 (IsI1LowReg && !areCombinableOperations(TRI, I2, I1)))
484 if (isSafeToMoveTogether(I1, I2, I1DestReg, I2DestReg,
488 // Not safe. Stop searching.
494 void HexagonCopyToCombine::combine(MachineInstr *I1, MachineInstr *I2,
495 MachineBasicBlock::iterator &MI,
497 // We are going to delete I2. If MI points to I2 advance it to the next
499 if ((MachineInstr *)MI == I2) ++MI;
501 // Figure out whether I1 or I2 goes into the lowreg part.
502 unsigned I1DestReg = I1->getOperand(0).getReg();
503 unsigned I2DestReg = I2->getOperand(0).getReg();
504 bool IsI1Loreg = (I2DestReg - I1DestReg) == 1;
505 unsigned LoRegDef = IsI1Loreg ? I1DestReg : I2DestReg;
507 // Get the double word register.
508 unsigned DoubleRegDest =
509 TRI->getMatchingSuperReg(LoRegDef, Hexagon::subreg_loreg,
510 &Hexagon::DoubleRegsRegClass);
511 assert(DoubleRegDest != 0 && "Expect a valid register");
514 // Setup source operands.
515 MachineOperand &LoOperand = IsI1Loreg ? I1->getOperand(1) :
517 MachineOperand &HiOperand = IsI1Loreg ? I2->getOperand(1) :
520 // Figure out which source is a register and which a constant.
521 bool IsHiReg = HiOperand.isReg();
522 bool IsLoReg = LoOperand.isReg();
524 MachineBasicBlock::iterator InsertPt(DoInsertAtI1 ? I1 : I2);
526 if (IsHiReg && IsLoReg)
527 emitCombineRR(InsertPt, DoubleRegDest, HiOperand, LoOperand);
529 emitCombineRI(InsertPt, DoubleRegDest, HiOperand, LoOperand);
531 emitCombineIR(InsertPt, DoubleRegDest, HiOperand, LoOperand);
533 emitCombineII(InsertPt, DoubleRegDest, HiOperand, LoOperand);
535 I1->eraseFromParent();
536 I2->eraseFromParent();
539 void HexagonCopyToCombine::emitCombineII(MachineBasicBlock::iterator &InsertPt,
540 unsigned DoubleDestReg,
541 MachineOperand &HiOperand,
542 MachineOperand &LoOperand) {
543 DebugLoc DL = InsertPt->getDebugLoc();
544 MachineBasicBlock *BB = InsertPt->getParent();
547 if (HiOperand.isGlobal()) {
548 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A2_combineii), DoubleDestReg)
549 .addGlobalAddress(HiOperand.getGlobal(), HiOperand.getOffset(),
550 HiOperand.getTargetFlags())
551 .addImm(LoOperand.getImm());
554 if (LoOperand.isGlobal()) {
555 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineii), DoubleDestReg)
556 .addImm(HiOperand.getImm())
557 .addGlobalAddress(LoOperand.getGlobal(), LoOperand.getOffset(),
558 LoOperand.getTargetFlags());
562 // Handle block addresses.
563 if (HiOperand.isBlockAddress()) {
564 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A2_combineii), DoubleDestReg)
565 .addBlockAddress(HiOperand.getBlockAddress(), HiOperand.getOffset(),
566 HiOperand.getTargetFlags())
567 .addImm(LoOperand.getImm());
570 if (LoOperand.isBlockAddress()) {
571 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineii), DoubleDestReg)
572 .addImm(HiOperand.getImm())
573 .addBlockAddress(LoOperand.getBlockAddress(), LoOperand.getOffset(),
574 LoOperand.getTargetFlags());
578 // Handle jump tables.
579 if (HiOperand.isJTI()) {
580 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A2_combineii), DoubleDestReg)
581 .addJumpTableIndex(HiOperand.getIndex(), HiOperand.getTargetFlags())
582 .addImm(LoOperand.getImm());
585 if (LoOperand.isJTI()) {
586 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineii), DoubleDestReg)
587 .addImm(HiOperand.getImm())
588 .addJumpTableIndex(LoOperand.getIndex(), LoOperand.getTargetFlags());
592 // Handle constant pools.
593 if (HiOperand.isCPI()) {
594 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A2_combineii), DoubleDestReg)
595 .addConstantPoolIndex(HiOperand.getIndex(), HiOperand.getOffset(),
596 HiOperand.getTargetFlags())
597 .addImm(LoOperand.getImm());
600 if (LoOperand.isCPI()) {
601 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineii), DoubleDestReg)
602 .addImm(HiOperand.getImm())
603 .addConstantPoolIndex(LoOperand.getIndex(), LoOperand.getOffset(),
604 LoOperand.getTargetFlags());
608 // First preference should be given to Hexagon::A2_combineii instruction
609 // as it can include U6 (in Hexagon::A4_combineii) as well.
610 // In this instruction, HiOperand is const extended, if required.
611 if (isInt<8>(LoOperand.getImm())) {
612 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A2_combineii), DoubleDestReg)
613 .addImm(HiOperand.getImm())
614 .addImm(LoOperand.getImm());
618 // In this instruction, LoOperand is const extended, if required.
619 if (isInt<8>(HiOperand.getImm())) {
620 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineii), DoubleDestReg)
621 .addImm(HiOperand.getImm())
622 .addImm(LoOperand.getImm());
626 // Insert new combine instruction.
627 // DoubleRegDest = combine #HiImm, #LoImm
628 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A2_combineii), DoubleDestReg)
629 .addImm(HiOperand.getImm())
630 .addImm(LoOperand.getImm());
633 void HexagonCopyToCombine::emitCombineIR(MachineBasicBlock::iterator &InsertPt,
634 unsigned DoubleDestReg,
635 MachineOperand &HiOperand,
636 MachineOperand &LoOperand) {
637 unsigned LoReg = LoOperand.getReg();
638 unsigned LoRegKillFlag = getKillRegState(LoOperand.isKill());
640 DebugLoc DL = InsertPt->getDebugLoc();
641 MachineBasicBlock *BB = InsertPt->getParent();
644 if (HiOperand.isGlobal()) {
645 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineir), DoubleDestReg)
646 .addGlobalAddress(HiOperand.getGlobal(), HiOperand.getOffset(),
647 HiOperand.getTargetFlags())
648 .addReg(LoReg, LoRegKillFlag);
651 // Handle block addresses.
652 if (HiOperand.isBlockAddress()) {
653 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineir), DoubleDestReg)
654 .addBlockAddress(HiOperand.getBlockAddress(), HiOperand.getOffset(),
655 HiOperand.getTargetFlags())
656 .addReg(LoReg, LoRegKillFlag);
659 // Handle jump tables.
660 if (HiOperand.isJTI()) {
661 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineir), DoubleDestReg)
662 .addJumpTableIndex(HiOperand.getIndex(), HiOperand.getTargetFlags())
663 .addReg(LoReg, LoRegKillFlag);
666 // Handle constant pools.
667 if (HiOperand.isCPI()) {
668 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineir), DoubleDestReg)
669 .addConstantPoolIndex(HiOperand.getIndex(), HiOperand.getOffset(),
670 HiOperand.getTargetFlags())
671 .addReg(LoReg, LoRegKillFlag);
674 // Insert new combine instruction.
675 // DoubleRegDest = combine #HiImm, LoReg
676 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineir), DoubleDestReg)
677 .addImm(HiOperand.getImm())
678 .addReg(LoReg, LoRegKillFlag);
681 void HexagonCopyToCombine::emitCombineRI(MachineBasicBlock::iterator &InsertPt,
682 unsigned DoubleDestReg,
683 MachineOperand &HiOperand,
684 MachineOperand &LoOperand) {
685 unsigned HiRegKillFlag = getKillRegState(HiOperand.isKill());
686 unsigned HiReg = HiOperand.getReg();
688 DebugLoc DL = InsertPt->getDebugLoc();
689 MachineBasicBlock *BB = InsertPt->getParent();
692 if (LoOperand.isGlobal()) {
693 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineri), DoubleDestReg)
694 .addReg(HiReg, HiRegKillFlag)
695 .addGlobalAddress(LoOperand.getGlobal(), LoOperand.getOffset(),
696 LoOperand.getTargetFlags());
699 // Handle block addresses.
700 if (LoOperand.isBlockAddress()) {
701 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineri), DoubleDestReg)
702 .addReg(HiReg, HiRegKillFlag)
703 .addBlockAddress(LoOperand.getBlockAddress(), LoOperand.getOffset(),
704 LoOperand.getTargetFlags());
707 // Handle jump tables.
708 if (LoOperand.isJTI()) {
709 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineri), DoubleDestReg)
710 .addReg(HiOperand.getReg(), HiRegKillFlag)
711 .addJumpTableIndex(LoOperand.getIndex(), LoOperand.getTargetFlags());
714 // Handle constant pools.
715 if (LoOperand.isCPI()) {
716 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineri), DoubleDestReg)
717 .addReg(HiOperand.getReg(), HiRegKillFlag)
718 .addConstantPoolIndex(LoOperand.getIndex(), LoOperand.getOffset(),
719 LoOperand.getTargetFlags());
723 // Insert new combine instruction.
724 // DoubleRegDest = combine HiReg, #LoImm
725 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineri), DoubleDestReg)
726 .addReg(HiReg, HiRegKillFlag)
727 .addImm(LoOperand.getImm());
730 void HexagonCopyToCombine::emitCombineRR(MachineBasicBlock::iterator &InsertPt,
731 unsigned DoubleDestReg,
732 MachineOperand &HiOperand,
733 MachineOperand &LoOperand) {
734 unsigned LoRegKillFlag = getKillRegState(LoOperand.isKill());
735 unsigned HiRegKillFlag = getKillRegState(HiOperand.isKill());
736 unsigned LoReg = LoOperand.getReg();
737 unsigned HiReg = HiOperand.getReg();
739 DebugLoc DL = InsertPt->getDebugLoc();
740 MachineBasicBlock *BB = InsertPt->getParent();
742 // Insert new combine instruction.
743 // DoubleRegDest = combine HiReg, LoReg
744 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A2_combinew), DoubleDestReg)
745 .addReg(HiReg, HiRegKillFlag)
746 .addReg(LoReg, LoRegKillFlag);
749 FunctionPass *llvm::createHexagonCopyToCombine() {
750 return new HexagonCopyToCombine();