1 //===-- Hexagon.td - Describe the Hexagon Target Machine --*- tablegen -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This is the top level entry point for the Hexagon target.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Target-independent interfaces which we are implementing
16 //===----------------------------------------------------------------------===//
18 include "llvm/Target/Target.td"
20 //===----------------------------------------------------------------------===//
21 // Hexagon Subtarget features.
22 //===----------------------------------------------------------------------===//
24 // Hexagon Archtectures
25 def ArchV2 : SubtargetFeature<"v2", "HexagonArchVersion", "V2",
27 def ArchV3 : SubtargetFeature<"v3", "HexagonArchVersion", "V3",
29 def ArchV4 : SubtargetFeature<"v4", "HexagonArchVersion", "V4",
32 //===----------------------------------------------------------------------===//
33 // Register File, Calling Conv, Instruction Descriptions
34 //===----------------------------------------------------------------------===//
35 include "HexagonSchedule.td"
36 include "HexagonRegisterInfo.td"
37 include "HexagonCallingConv.td"
38 include "HexagonInstrInfo.td"
39 include "HexagonIntrinsics.td"
40 include "HexagonIntrinsicsDerived.td"
42 def HexagonInstrInfo : InstrInfo;
44 //===----------------------------------------------------------------------===//
45 // Hexagon processors supported.
46 //===----------------------------------------------------------------------===//
48 class Proc<string Name, ProcessorItineraries Itin,
49 list<SubtargetFeature> Features>
50 : Processor<Name, Itin, Features>;
52 def : Proc<"hexagonv2", HexagonItineraries, [ArchV2]>;
53 def : Proc<"hexagonv3", HexagonItineraries, [ArchV2, ArchV3]>;
54 def : Proc<"hexagonv4", HexagonItinerariesV4, [ArchV2, ArchV3, ArchV4]>;
56 // Hexagon Uses the MC printer for assembler output, so make sure the TableGen
57 // AsmWriter bits get associated with the correct class.
58 def HexagonAsmWriter : AsmWriter {
59 string AsmWriterClassName = "InstPrinter";
60 bit isMCAsmWriter = 1;
63 //===----------------------------------------------------------------------===//
64 // Declare the target which we are implementing
65 //===----------------------------------------------------------------------===//
67 def Hexagon : Target {
68 // Pull in Instruction Info:
69 let InstructionSet = HexagonInstrInfo;
71 let AssemblyWriters = [HexagonAsmWriter];