1 //===-- Hexagon.td - Describe the Hexagon Target Machine --*- tablegen -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This is the top level entry point for the Hexagon target.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Target-independent interfaces which we are implementing
16 //===----------------------------------------------------------------------===//
18 include "llvm/Target/Target.td"
20 //===----------------------------------------------------------------------===//
21 // Hexagon Subtarget features.
22 //===----------------------------------------------------------------------===//
24 // Hexagon Archtectures
25 def ArchV2 : SubtargetFeature<"v2", "HexagonArchVersion", "V2",
27 def ArchV3 : SubtargetFeature<"v3", "HexagonArchVersion", "V3",
29 def ArchV4 : SubtargetFeature<"v4", "HexagonArchVersion", "V4",
31 def ArchV5 : SubtargetFeature<"v5", "HexagonArchVersion", "V5",
34 //===----------------------------------------------------------------------===//
35 // Hexagon Instruction Predicate Definitions.
36 //===----------------------------------------------------------------------===//
37 def HasV2T : Predicate<"Subtarget.hasV2TOps()">;
38 def HasV2TOnly : Predicate<"Subtarget.hasV2TOpsOnly()">;
39 def NoV2T : Predicate<"!Subtarget.hasV2TOps()">;
40 def HasV3T : Predicate<"Subtarget.hasV3TOps()">;
41 def HasV3TOnly : Predicate<"Subtarget.hasV3TOpsOnly()">;
42 def NoV3T : Predicate<"!Subtarget.hasV3TOps()">;
43 def HasV4T : Predicate<"Subtarget.hasV4TOps()">;
44 def NoV4T : Predicate<"!Subtarget.hasV4TOps()">;
45 def HasV5T : Predicate<"Subtarget.hasV5TOps()">;
46 def NoV5T : Predicate<"!Subtarget.hasV5TOps()">;
47 def UseMEMOP : Predicate<"Subtarget.useMemOps()">;
48 def IEEERndNearV5T : Predicate<"Subtarget.modeIEEERndNear()">;
50 //===----------------------------------------------------------------------===//
51 // Classes used for relation maps.
52 //===----------------------------------------------------------------------===//
53 // PredRel - Filter class used to relate non-predicated instructions with their
56 // PredNewRel - Filter class used to relate predicated instructions with their
57 // predicate-new forms.
58 class PredNewRel: PredRel;
59 // ImmRegRel - Filter class used to relate instructions having reg-reg form
60 // with their reg-imm counterparts.
62 // NewValueRel - Filter class used to relate regular store instructions with
63 // their new-value store form.
64 class NewValueRel: PredNewRel;
65 // NewValueRel - Filter class used to relate load/store instructions having
66 // different addressing modes with each other.
67 class AddrModeRel: NewValueRel;
69 //===----------------------------------------------------------------------===//
70 // Generate mapping table to relate non-predicate instructions with their
71 // predicated formats - true and false.
74 def getPredOpcode : InstrMapping {
75 let FilterClass = "PredRel";
76 // Instructions with the same BaseOpcode and isNVStore values form a row.
77 let RowFields = ["BaseOpcode", "isNVStore", "PNewValue"];
78 // Instructions with the same predicate sense form a column.
79 let ColFields = ["PredSense"];
80 // The key column is the unpredicated instructions.
82 // Value columns are PredSense=true and PredSense=false
83 let ValueCols = [["true"], ["false"]];
86 //===----------------------------------------------------------------------===//
87 // Generate mapping table to relate predicated instructions with their .new
90 def getPredNewOpcode : InstrMapping {
91 let FilterClass = "PredNewRel";
92 let RowFields = ["BaseOpcode", "PredSense", "isNVStore"];
93 let ColFields = ["PNewValue"];
95 let ValueCols = [["new"]];
98 //===----------------------------------------------------------------------===//
99 // Generate mapping table to relate store instructions with their new-value
102 def getNewValueOpcode : InstrMapping {
103 let FilterClass = "NewValueRel";
104 let RowFields = ["BaseOpcode", "PredSense", "PNewValue"];
105 let ColFields = ["isNVStore"];
107 let ValueCols = [["1"]];
110 def getBasedWithImmOffset : InstrMapping {
111 let FilterClass = "AddrModeRel";
112 let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore",
113 "isMEMri", "isFloat"];
114 let ColFields = ["addrMode"];
115 let KeyCol = ["Absolute"];
116 let ValueCols = [["BaseImmOffset"]];
119 def getBaseWithRegOffset : InstrMapping {
120 let FilterClass = "AddrModeRel";
121 let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore"];
122 let ColFields = ["addrMode"];
123 let KeyCol = ["BaseImmOffset"];
124 let ValueCols = [["BaseRegOffset"]];
127 def getRegForm : InstrMapping {
128 let FilterClass = "ImmRegRel";
129 let RowFields = ["CextOpcode", "PredSense", "PNewValue"];
130 let ColFields = ["InputType"];
131 let KeyCol = ["imm"];
132 let ValueCols = [["reg"]];
135 //===----------------------------------------------------------------------===//
136 // Register File, Calling Conv, Instruction Descriptions
137 //===----------------------------------------------------------------------===//
138 include "HexagonSchedule.td"
139 include "HexagonRegisterInfo.td"
140 include "HexagonCallingConv.td"
141 include "HexagonInstrInfo.td"
142 include "HexagonIntrinsics.td"
143 include "HexagonIntrinsicsDerived.td"
145 def HexagonInstrInfo : InstrInfo;
147 //===----------------------------------------------------------------------===//
148 // Hexagon processors supported.
149 //===----------------------------------------------------------------------===//
151 class Proc<string Name, SchedMachineModel Model,
152 list<SubtargetFeature> Features>
153 : ProcessorModel<Name, Model, Features>;
155 def : Proc<"hexagonv2", HexagonModel, [ArchV2]>;
156 def : Proc<"hexagonv3", HexagonModel, [ArchV2, ArchV3]>;
157 def : Proc<"hexagonv4", HexagonModelV4, [ArchV2, ArchV3, ArchV4]>;
158 def : Proc<"hexagonv5", HexagonModelV4, [ArchV2, ArchV3, ArchV4, ArchV5]>;
161 // Hexagon Uses the MC printer for assembler output, so make sure the TableGen
162 // AsmWriter bits get associated with the correct class.
163 def HexagonAsmWriter : AsmWriter {
164 string AsmWriterClassName = "InstPrinter";
165 bit isMCAsmWriter = 1;
168 //===----------------------------------------------------------------------===//
169 // Declare the target which we are implementing
170 //===----------------------------------------------------------------------===//
172 def Hexagon : Target {
173 // Pull in Instruction Info:
174 let InstructionSet = HexagonInstrInfo;
176 let AssemblyWriters = [HexagonAsmWriter];