1 //===-- Hexagon.td - Describe the Hexagon Target Machine --*- tablegen -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This is the top level entry point for the Hexagon target.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Target-independent interfaces which we are implementing
16 //===----------------------------------------------------------------------===//
18 include "llvm/Target/Target.td"
20 //===----------------------------------------------------------------------===//
21 // Hexagon Subtarget features.
22 //===----------------------------------------------------------------------===//
24 // Hexagon Architectures
25 def ArchV4: SubtargetFeature<"v4", "HexagonArchVersion", "V4", "Hexagon V4">;
26 def ArchV5: SubtargetFeature<"v5", "HexagonArchVersion", "V5", "Hexagon V5">;
27 def ArchV55: SubtargetFeature<"v55", "HexagonArchVersion", "V55", "Hexagon V55">;
28 def ArchV60: SubtargetFeature<"v60", "HexagonArchVersion", "V60", "Hexagon V60">;
30 // Hexagon ISA Extensions
31 def ExtensionHVX: SubtargetFeature<"hvx", "UseHVXOps",
32 "true", "Hexagon HVX instructions">;
33 def ExtensionHVXDbl: SubtargetFeature<"hvxDbl", "UseHVXDblOps",
34 "true", "Hexagon HVX Double instructions">;
36 //===----------------------------------------------------------------------===//
37 // Hexagon Instruction Predicate Definitions.
38 //===----------------------------------------------------------------------===//
39 def HasV5T : Predicate<"HST->hasV5TOps()">;
40 def NoV5T : Predicate<"!HST->hasV5TOps()">;
41 def HasV55T : Predicate<"HST->hasV55TOps()">,
42 AssemblerPredicate<"ArchV55">;
43 def HasV60T : Predicate<"HST->hasV60TOps()">,
44 AssemblerPredicate<"ArchV60">;
45 def UseMEMOP : Predicate<"HST->useMemOps()">;
46 def IEEERndNearV5T : Predicate<"HST->modeIEEERndNear()">;
47 def UseHVXDbl : Predicate<"HST->useHVXDblOps()">,
48 AssemblerPredicate<"ExtensionHVXDbl">;
49 def UseHVXSgl : Predicate<"HST->useHVXSglOps()">;
51 def UseHVX : Predicate<"HST->useHVXOps()">,
52 AssemblerPredicate<"ExtensionHVX">;
54 //===----------------------------------------------------------------------===//
55 // Classes used for relation maps.
56 //===----------------------------------------------------------------------===//
59 // PredRel - Filter class used to relate non-predicated instructions with their
62 // PredNewRel - Filter class used to relate predicated instructions with their
63 // predicate-new forms.
64 class PredNewRel: PredRel;
65 // ImmRegRel - Filter class used to relate instructions having reg-reg form
66 // with their reg-imm counterparts.
68 // NewValueRel - Filter class used to relate regular store instructions with
69 // their new-value store form.
70 class NewValueRel: PredNewRel;
71 // NewValueRel - Filter class used to relate load/store instructions having
72 // different addressing modes with each other.
73 class AddrModeRel: NewValueRel;
75 //===----------------------------------------------------------------------===//
76 // Generate mapping table to relate non-predicate instructions with their
77 // predicated formats - true and false.
80 def getPredOpcode : InstrMapping {
81 let FilterClass = "PredRel";
82 // Instructions with the same BaseOpcode and isNVStore values form a row.
83 let RowFields = ["BaseOpcode", "isNVStore", "PNewValue", "isNT"];
84 // Instructions with the same predicate sense form a column.
85 let ColFields = ["PredSense"];
86 // The key column is the unpredicated instructions.
88 // Value columns are PredSense=true and PredSense=false
89 let ValueCols = [["true"], ["false"]];
92 //===----------------------------------------------------------------------===//
93 // Generate mapping table to relate predicate-true instructions with their
94 // predicate-false forms
96 def getFalsePredOpcode : InstrMapping {
97 let FilterClass = "PredRel";
98 let RowFields = ["BaseOpcode", "PNewValue", "isNVStore", "isBrTaken", "isNT"];
99 let ColFields = ["PredSense"];
100 let KeyCol = ["true"];
101 let ValueCols = [["false"]];
104 //===----------------------------------------------------------------------===//
105 // Generate mapping table to relate predicate-false instructions with their
106 // predicate-true forms
108 def getTruePredOpcode : InstrMapping {
109 let FilterClass = "PredRel";
110 let RowFields = ["BaseOpcode", "PNewValue", "isNVStore", "isBrTaken", "isNT"];
111 let ColFields = ["PredSense"];
112 let KeyCol = ["false"];
113 let ValueCols = [["true"]];
116 //===----------------------------------------------------------------------===//
117 // Generate mapping table to relate predicated instructions with their .new
120 def getPredNewOpcode : InstrMapping {
121 let FilterClass = "PredNewRel";
122 let RowFields = ["BaseOpcode", "PredSense", "isNVStore", "isBrTaken"];
123 let ColFields = ["PNewValue"];
125 let ValueCols = [["new"]];
128 //===----------------------------------------------------------------------===//
129 // Generate mapping table to relate .new predicated instructions with their old
132 def getPredOldOpcode : InstrMapping {
133 let FilterClass = "PredNewRel";
134 let RowFields = ["BaseOpcode", "PredSense", "isNVStore"];
135 let ColFields = ["PNewValue"];
136 let KeyCol = ["new"];
137 let ValueCols = [[""]];
140 //===----------------------------------------------------------------------===//
141 // Generate mapping table to relate store instructions with their new-value
144 def getNewValueOpcode : InstrMapping {
145 let FilterClass = "NewValueRel";
146 let RowFields = ["BaseOpcode", "PredSense", "PNewValue", "addrMode", "isNT"];
147 let ColFields = ["NValueST"];
148 let KeyCol = ["false"];
149 let ValueCols = [["true"]];
152 //===----------------------------------------------------------------------===//
153 // Generate mapping table to relate new-value store instructions with their old
156 def getNonNVStore : InstrMapping {
157 let FilterClass = "NewValueRel";
158 let RowFields = ["BaseOpcode", "PredSense", "PNewValue", "addrMode", "isNT"];
159 let ColFields = ["NValueST"];
160 let KeyCol = ["true"];
161 let ValueCols = [["false"]];
164 def getBaseWithImmOffset : InstrMapping {
165 let FilterClass = "AddrModeRel";
166 let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore",
168 let ColFields = ["addrMode"];
169 let KeyCol = ["Absolute"];
170 let ValueCols = [["BaseImmOffset"]];
173 def getBaseWithRegOffset : InstrMapping {
174 let FilterClass = "AddrModeRel";
175 let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore"];
176 let ColFields = ["addrMode"];
177 let KeyCol = ["BaseImmOffset"];
178 let ValueCols = [["BaseRegOffset"]];
181 def getRegForm : InstrMapping {
182 let FilterClass = "ImmRegRel";
183 let RowFields = ["CextOpcode", "PredSense", "PNewValue"];
184 let ColFields = ["InputType"];
185 let KeyCol = ["imm"];
186 let ValueCols = [["reg"]];
189 //===----------------------------------------------------------------------===//
190 // Register File, Calling Conv, Instruction Descriptions
191 //===----------------------------------------------------------------------===//
192 include "HexagonSchedule.td"
193 include "HexagonRegisterInfo.td"
194 include "HexagonCallingConv.td"
195 include "HexagonInstrInfo.td"
196 include "HexagonIntrinsics.td"
197 include "HexagonIntrinsicsDerived.td"
199 def HexagonInstrInfo : InstrInfo;
201 //===----------------------------------------------------------------------===//
202 // Hexagon processors supported.
203 //===----------------------------------------------------------------------===//
205 class Proc<string Name, SchedMachineModel Model,
206 list<SubtargetFeature> Features>
207 : ProcessorModel<Name, Model, Features>;
209 def : Proc<"hexagonv4", HexagonModelV4,
211 def : Proc<"hexagonv5", HexagonModelV4,
214 //===----------------------------------------------------------------------===//
215 // Declare the target which we are implementing
216 //===----------------------------------------------------------------------===//
218 def HexagonAsmParserVariant : AsmParserVariant {
220 string TokenizingCharacters = "#()=:.<>!+*";
223 def Hexagon : Target {
224 // Pull in Instruction Info:
225 let InstructionSet = HexagonInstrInfo;
226 let AssemblyParserVariants = [HexagonAsmParserVariant];