1 //===-- Hexagon.td - Describe the Hexagon Target Machine --*- tablegen -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This is the top level entry point for the Hexagon target.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Target-independent interfaces which we are implementing
16 //===----------------------------------------------------------------------===//
18 include "llvm/Target/Target.td"
20 //===----------------------------------------------------------------------===//
21 // Hexagon Subtarget features.
22 //===----------------------------------------------------------------------===//
24 // Hexagon Architectures
25 def ArchV4: SubtargetFeature<"v4", "HexagonArchVersion", "V4", "Hexagon V4">;
26 def ArchV5: SubtargetFeature<"v5", "HexagonArchVersion", "V5", "Hexagon V5">;
28 //===----------------------------------------------------------------------===//
29 // Hexagon Instruction Predicate Definitions.
30 //===----------------------------------------------------------------------===//
31 def HasV5T : Predicate<"HST.hasV5TOps()">;
32 def NoV5T : Predicate<"!HST.hasV5TOps()">;
33 def UseMEMOP : Predicate<"HST.useMemOps()">;
34 def IEEERndNearV5T : Predicate<"HST.modeIEEERndNear()">;
36 //===----------------------------------------------------------------------===//
37 // Classes used for relation maps.
38 //===----------------------------------------------------------------------===//
41 // PredRel - Filter class used to relate non-predicated instructions with their
44 // PredNewRel - Filter class used to relate predicated instructions with their
45 // predicate-new forms.
46 class PredNewRel: PredRel;
47 // ImmRegRel - Filter class used to relate instructions having reg-reg form
48 // with their reg-imm counterparts.
50 // NewValueRel - Filter class used to relate regular store instructions with
51 // their new-value store form.
52 class NewValueRel: PredNewRel;
53 // NewValueRel - Filter class used to relate load/store instructions having
54 // different addressing modes with each other.
55 class AddrModeRel: NewValueRel;
57 //===----------------------------------------------------------------------===//
58 // Generate mapping table to relate non-predicate instructions with their
59 // predicated formats - true and false.
62 def getPredOpcode : InstrMapping {
63 let FilterClass = "PredRel";
64 // Instructions with the same BaseOpcode and isNVStore values form a row.
65 let RowFields = ["BaseOpcode", "isNVStore", "PNewValue"];
66 // Instructions with the same predicate sense form a column.
67 let ColFields = ["PredSense"];
68 // The key column is the unpredicated instructions.
70 // Value columns are PredSense=true and PredSense=false
71 let ValueCols = [["true"], ["false"]];
74 //===----------------------------------------------------------------------===//
75 // Generate mapping table to relate predicate-true instructions with their
76 // predicate-false forms
78 def getFalsePredOpcode : InstrMapping {
79 let FilterClass = "PredRel";
80 let RowFields = ["BaseOpcode", "PNewValue", "isNVStore", "isBrTaken"];
81 let ColFields = ["PredSense"];
82 let KeyCol = ["true"];
83 let ValueCols = [["false"]];
86 //===----------------------------------------------------------------------===//
87 // Generate mapping table to relate predicate-false instructions with their
88 // predicate-true forms
90 def getTruePredOpcode : InstrMapping {
91 let FilterClass = "PredRel";
92 let RowFields = ["BaseOpcode", "PNewValue", "isNVStore", "isBrTaken"];
93 let ColFields = ["PredSense"];
94 let KeyCol = ["false"];
95 let ValueCols = [["true"]];
98 //===----------------------------------------------------------------------===//
99 // Generate mapping table to relate predicated instructions with their .new
102 def getPredNewOpcode : InstrMapping {
103 let FilterClass = "PredNewRel";
104 let RowFields = ["BaseOpcode", "PredSense", "isNVStore", "isBrTaken"];
105 let ColFields = ["PNewValue"];
107 let ValueCols = [["new"]];
110 //===----------------------------------------------------------------------===//
111 // Generate mapping table to relate .new predicated instructions with their old
114 def getPredOldOpcode : InstrMapping {
115 let FilterClass = "PredNewRel";
116 let RowFields = ["BaseOpcode", "PredSense", "isNVStore"];
117 let ColFields = ["PNewValue"];
118 let KeyCol = ["new"];
119 let ValueCols = [[""]];
122 //===----------------------------------------------------------------------===//
123 // Generate mapping table to relate store instructions with their new-value
126 def getNewValueOpcode : InstrMapping {
127 let FilterClass = "NewValueRel";
128 let RowFields = ["BaseOpcode", "PredSense", "PNewValue", "addrMode"];
129 let ColFields = ["NValueST"];
130 let KeyCol = ["false"];
131 let ValueCols = [["true"]];
134 //===----------------------------------------------------------------------===//
135 // Generate mapping table to relate new-value store instructions with their old
138 def getNonNVStore : InstrMapping {
139 let FilterClass = "NewValueRel";
140 let RowFields = ["BaseOpcode", "PredSense", "PNewValue", "addrMode"];
141 let ColFields = ["NValueST"];
142 let KeyCol = ["true"];
143 let ValueCols = [["false"]];
146 def getBasedWithImmOffset : InstrMapping {
147 let FilterClass = "AddrModeRel";
148 let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore",
149 "isMEMri", "isFloat"];
150 let ColFields = ["addrMode"];
151 let KeyCol = ["Absolute"];
152 let ValueCols = [["BaseImmOffset"]];
155 def getBaseWithRegOffset : InstrMapping {
156 let FilterClass = "AddrModeRel";
157 let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore"];
158 let ColFields = ["addrMode"];
159 let KeyCol = ["BaseImmOffset"];
160 let ValueCols = [["BaseRegOffset"]];
163 def getRegForm : InstrMapping {
164 let FilterClass = "ImmRegRel";
165 let RowFields = ["CextOpcode", "PredSense", "PNewValue"];
166 let ColFields = ["InputType"];
167 let KeyCol = ["imm"];
168 let ValueCols = [["reg"]];
171 //===----------------------------------------------------------------------===//
172 // Register File, Calling Conv, Instruction Descriptions
173 //===----------------------------------------------------------------------===//
174 include "HexagonSchedule.td"
175 include "HexagonRegisterInfo.td"
176 include "HexagonCallingConv.td"
177 include "HexagonInstrInfo.td"
178 include "HexagonIntrinsics.td"
179 include "HexagonIntrinsicsDerived.td"
181 def HexagonInstrInfo : InstrInfo;
183 //===----------------------------------------------------------------------===//
184 // Hexagon processors supported.
185 //===----------------------------------------------------------------------===//
187 class Proc<string Name, SchedMachineModel Model,
188 list<SubtargetFeature> Features>
189 : ProcessorModel<Name, Model, Features>;
191 def : Proc<"hexagonv4", HexagonModelV4,
193 def : Proc<"hexagonv5", HexagonModelV4,
196 //===----------------------------------------------------------------------===//
197 // Declare the target which we are implementing
198 //===----------------------------------------------------------------------===//
200 def Hexagon : Target {
201 // Pull in Instruction Info:
202 let InstructionSet = HexagonInstrInfo;