1 //===-- HexagonDisassembler.cpp - Disassembler for Hexagon ISA ------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/HexagonBaseInfo.h"
11 #include "MCTargetDesc/HexagonMCInst.h"
12 #include "MCTargetDesc/HexagonMCTargetDesc.h"
13 #include "llvm/MC/MCContext.h"
14 #include "llvm/MC/MCDisassembler.h"
15 #include "llvm/MC/MCExpr.h"
16 #include "llvm/MC/MCFixedLenDisassembler.h"
17 #include "llvm/MC/MCInst.h"
18 #include "llvm/MC/MCInstrDesc.h"
19 #include "llvm/MC/MCSubtargetInfo.h"
20 #include "llvm/Support/Debug.h"
21 #include "llvm/Support/Endian.h"
22 #include "llvm/Support/ErrorHandling.h"
23 #include "llvm/Support/LEB128.h"
24 #include "llvm/Support/TargetRegistry.h"
25 #include "llvm/Support/raw_ostream.h"
31 #define DEBUG_TYPE "hexagon-disassembler"
33 // Pull DecodeStatus and its enum values into the global namespace.
34 typedef llvm::MCDisassembler::DecodeStatus DecodeStatus;
37 /// \brief Hexagon disassembler for all Hexagon platforms.
38 class HexagonDisassembler : public MCDisassembler {
40 HexagonDisassembler(MCSubtargetInfo const &STI, MCContext &Ctx)
41 : MCDisassembler(STI, Ctx) {}
43 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
44 ArrayRef<uint8_t> Bytes, uint64_t Address,
46 raw_ostream &CStream) const override;
50 static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo,
51 uint64_t Address, const void *Decoder);
52 static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo,
53 uint64_t Address, const void *Decoder);
54 static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo,
55 uint64_t Address, void const *Decoder);
57 static const uint16_t IntRegDecoderTable[] = {
58 Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4,
59 Hexagon::R5, Hexagon::R6, Hexagon::R7, Hexagon::R8, Hexagon::R9,
60 Hexagon::R10, Hexagon::R11, Hexagon::R12, Hexagon::R13, Hexagon::R14,
61 Hexagon::R15, Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19,
62 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, Hexagon::R24,
63 Hexagon::R25, Hexagon::R26, Hexagon::R27, Hexagon::R28, Hexagon::R29,
64 Hexagon::R30, Hexagon::R31 };
66 static const uint16_t PredRegDecoderTable[] = { Hexagon::P0, Hexagon::P1,
67 Hexagon::P2, Hexagon::P3 };
69 static DecodeStatus DecodeRegisterClass(MCInst &Inst, unsigned RegNo,
70 const uint16_t Table[], size_t Size) {
72 Inst.addOperand(MCOperand::CreateReg(Table[RegNo]));
73 return MCDisassembler::Success;
76 return MCDisassembler::Fail;
79 static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo,
81 void const *Decoder) {
83 return MCDisassembler::Fail;
85 unsigned Register = IntRegDecoderTable[RegNo];
86 Inst.addOperand(MCOperand::CreateReg(Register));
87 return MCDisassembler::Success;
90 static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo,
91 uint64_t /*Address*/, const void *Decoder) {
92 static const uint16_t CtrlRegDecoderTable[] = {
93 Hexagon::SA0, Hexagon::LC0, Hexagon::SA1, Hexagon::LC1,
94 Hexagon::P3_0, Hexagon::NoRegister, Hexagon::C6, Hexagon::C7,
95 Hexagon::USR, Hexagon::PC, Hexagon::UGP, Hexagon::GP,
96 Hexagon::CS0, Hexagon::CS1, Hexagon::UPCL, Hexagon::UPCH
99 if (RegNo >= sizeof(CtrlRegDecoderTable) / sizeof(CtrlRegDecoderTable[0]))
100 return MCDisassembler::Fail;
102 if (CtrlRegDecoderTable[RegNo] == Hexagon::NoRegister)
103 return MCDisassembler::Fail;
105 unsigned Register = CtrlRegDecoderTable[RegNo];
106 Inst.addOperand(MCOperand::CreateReg(Register));
107 return MCDisassembler::Success;
110 static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo,
111 uint64_t /*Address*/, void const *Decoder) {
112 static const uint16_t CtrlReg64DecoderTable[] = {
113 Hexagon::C1_0, Hexagon::NoRegister,
114 Hexagon::C3_2, Hexagon::NoRegister,
115 Hexagon::NoRegister, Hexagon::NoRegister,
116 Hexagon::C7_6, Hexagon::NoRegister,
117 Hexagon::C9_8, Hexagon::NoRegister,
118 Hexagon::C11_10, Hexagon::NoRegister,
119 Hexagon::CS, Hexagon::NoRegister,
120 Hexagon::UPC, Hexagon::NoRegister
123 if (RegNo >= sizeof(CtrlReg64DecoderTable) / sizeof(CtrlReg64DecoderTable[0]))
124 return MCDisassembler::Fail;
126 if (CtrlReg64DecoderTable[RegNo] == Hexagon::NoRegister)
127 return MCDisassembler::Fail;
129 unsigned Register = CtrlReg64DecoderTable[RegNo];
130 Inst.addOperand(MCOperand::CreateReg(Register));
131 return MCDisassembler::Success;
134 static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo,
135 uint64_t /*Address*/, const void *Decoder) {
136 unsigned Register = 0;
139 Register = Hexagon::M0;
142 Register = Hexagon::M1;
145 return MCDisassembler::Fail;
147 Inst.addOperand(MCOperand::CreateReg(Register));
148 return MCDisassembler::Success;
151 static DecodeStatus DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo,
152 uint64_t /*Address*/, const void *Decoder) {
153 static const uint16_t DoubleRegDecoderTable[] = {
154 Hexagon::D0, Hexagon::D1, Hexagon::D2, Hexagon::D3,
155 Hexagon::D4, Hexagon::D5, Hexagon::D6, Hexagon::D7,
156 Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11,
157 Hexagon::D12, Hexagon::D13, Hexagon::D14, Hexagon::D15
160 return (DecodeRegisterClass(Inst, RegNo >> 1,
161 DoubleRegDecoderTable,
162 sizeof (DoubleRegDecoderTable)));
165 static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo,
166 uint64_t /*Address*/,
167 void const *Decoder) {
169 return MCDisassembler::Fail;
171 unsigned Register = PredRegDecoderTable[RegNo];
172 Inst.addOperand(MCOperand::CreateReg(Register));
173 return MCDisassembler::Success;
176 #include "HexagonGenDisassemblerTables.inc"
178 static MCDisassembler *createHexagonDisassembler(Target const &T,
179 MCSubtargetInfo const &STI,
181 return new HexagonDisassembler(STI, Ctx);
184 extern "C" void LLVMInitializeHexagonDisassembler() {
185 TargetRegistry::RegisterMCDisassembler(TheHexagonTarget,
186 createHexagonDisassembler);
189 DecodeStatus HexagonDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
190 ArrayRef<uint8_t> Bytes,
193 raw_ostream &cs) const {
195 if (Bytes.size() < 4)
196 return MCDisassembler::Fail;
199 llvm::support::endian::read<uint32_t, llvm::support::little,
200 llvm::support::unaligned>(Bytes.data());
202 // Remove parse bits.
203 insn &= ~static_cast<uint32_t>(HexagonII::InstParseBits::INST_PARSE_MASK);
204 DecodeStatus Result = decodeInstruction(DecoderTable32, MI, insn, Address, this, STI);
205 HexagonMCInst::AppendImplicitOperands(MI);