1 //===-- HexagonDisassembler.cpp - Disassembler for Hexagon ISA ------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #define DEBUG_TYPE "hexagon-disassembler"
13 #include "MCTargetDesc/HexagonBaseInfo.h"
14 #include "MCTargetDesc/HexagonMCChecker.h"
15 #include "MCTargetDesc/HexagonMCTargetDesc.h"
16 #include "MCTargetDesc/HexagonMCInstrInfo.h"
17 #include "MCTargetDesc/HexagonInstPrinter.h"
18 #include "llvm/ADT/StringExtras.h"
19 #include "llvm/MC/MCDisassembler.h"
20 #include "llvm/MC/MCContext.h"
21 #include "llvm/MC/MCExpr.h"
22 #include "llvm/MC/MCFixedLenDisassembler.h"
23 #include "llvm/MC/MCInst.h"
24 #include "llvm/MC/MCInstrDesc.h"
25 #include "llvm/MC/MCInstrInfo.h"
26 #include "llvm/MC/MCSubtargetInfo.h"
27 #include "llvm/Support/Debug.h"
28 #include "llvm/Support/ErrorHandling.h"
29 #include "llvm/Support/LEB128.h"
30 #include "llvm/Support/MemoryObject.h"
31 #include "llvm/Support/raw_ostream.h"
32 #include "llvm/Support/TargetRegistry.h"
36 using namespace Hexagon;
38 typedef MCDisassembler::DecodeStatus DecodeStatus;
41 /// \brief Hexagon disassembler for all Hexagon platforms.
42 class HexagonDisassembler : public MCDisassembler {
44 std::unique_ptr<MCInstrInfo const> const MCII;
45 std::unique_ptr<MCInst *> CurrentBundle;
46 HexagonDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
47 MCInstrInfo const *MCII)
48 : MCDisassembler(STI, Ctx), MCII(MCII), CurrentBundle(new MCInst *) {}
50 DecodeStatus getSingleInstruction(MCInst &Instr, MCInst &MCB,
51 ArrayRef<uint8_t> Bytes, uint64_t Address,
52 raw_ostream &VStream, raw_ostream &CStream,
53 bool &Complete) const;
54 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
55 ArrayRef<uint8_t> Bytes, uint64_t Address,
57 raw_ostream &CStream) const override;
59 void adjustExtendedInstructions(MCInst &MCI, MCInst const &MCB) const;
60 void addSubinstOperands(MCInst *MI, unsigned opcode, unsigned inst) const;
64 // Forward declare these because the auto-generated code will reference them.
65 // Definitions are further down.
67 static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo,
70 static DecodeStatus DecodeIntRegsLow8RegisterClass(MCInst &Inst, unsigned RegNo,
73 static DecodeStatus DecodeVectorRegsRegisterClass(MCInst &Inst, unsigned RegNo,
76 static DecodeStatus DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo,
79 static DecodeStatus DecodeVecDblRegsRegisterClass(MCInst &Inst, unsigned RegNo,
82 static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo,
85 static DecodeStatus DecodeVecPredRegsRegisterClass(MCInst &Inst, unsigned RegNo,
88 static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo,
91 static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo,
94 static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo,
98 static DecodeStatus decodeSpecial(MCInst &MI, uint32_t insn);
99 static DecodeStatus decodeImmext(MCInst &MI, uint32_t insn,
100 void const *Decoder);
102 static unsigned GetSubinstOpcode(unsigned IClass, unsigned inst, unsigned &op,
105 static unsigned getRegFromSubinstEncoding(unsigned encoded_reg);
107 static DecodeStatus unsignedImmDecoder(MCInst &MI, unsigned tmp,
108 uint64_t Address, const void *Decoder);
109 static DecodeStatus s16ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
110 const void *Decoder);
111 static DecodeStatus s12ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
112 const void *Decoder);
113 static DecodeStatus s11_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
114 const void *Decoder);
115 static DecodeStatus s11_1ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
116 const void *Decoder);
117 static DecodeStatus s11_2ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
118 const void *Decoder);
119 static DecodeStatus s11_3ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
120 const void *Decoder);
121 static DecodeStatus s10ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
122 const void *Decoder);
123 static DecodeStatus s8ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
124 const void *Decoder);
125 static DecodeStatus s6_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
126 const void *Decoder);
127 static DecodeStatus s4_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
128 const void *Decoder);
129 static DecodeStatus s4_1ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
130 const void *Decoder);
131 static DecodeStatus s4_2ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
132 const void *Decoder);
133 static DecodeStatus s4_3ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
134 const void *Decoder);
135 static DecodeStatus s4_6ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
136 const void *Decoder);
137 static DecodeStatus s3_6ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
138 const void *Decoder);
139 static DecodeStatus brtargetDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
140 const void *Decoder);
142 #include "HexagonGenDisassemblerTables.inc"
144 static MCDisassembler *createHexagonDisassembler(const Target &T,
145 const MCSubtargetInfo &STI,
147 return new HexagonDisassembler(STI, Ctx, T.createMCInstrInfo());
150 extern "C" void LLVMInitializeHexagonDisassembler() {
151 TargetRegistry::RegisterMCDisassembler(TheHexagonTarget,
152 createHexagonDisassembler);
155 DecodeStatus HexagonDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
156 ArrayRef<uint8_t> Bytes,
159 raw_ostream &cs) const {
160 DecodeStatus Result = DecodeStatus::Success;
161 bool Complete = false;
164 *CurrentBundle = &MI;
165 MI = HexagonMCInstrInfo::createBundle();
166 while (Result == Success && Complete == false) {
167 if (Bytes.size() < HEXAGON_INSTR_SIZE)
168 return MCDisassembler::Fail;
169 MCInst *Inst = new (getContext()) MCInst;
170 Result = getSingleInstruction(*Inst, MI, Bytes, Address, os, cs, Complete);
171 MI.addOperand(MCOperand::createInst(Inst));
172 Size += HEXAGON_INSTR_SIZE;
173 Bytes = Bytes.slice(HEXAGON_INSTR_SIZE);
175 if(Result == MCDisassembler::Fail)
177 HexagonMCChecker Checker (*MCII, STI, MI, MI, *getContext().getRegisterInfo());
179 return MCDisassembler::Fail;
180 return MCDisassembler::Success;
184 HexagonDisassembler const &disassembler(void const *Decoder) {
185 return *static_cast<HexagonDisassembler const *>(Decoder);
187 MCContext &contextFromDecoder(void const *Decoder) {
188 return disassembler(Decoder).getContext();
192 DecodeStatus HexagonDisassembler::getSingleInstruction(
193 MCInst &MI, MCInst &MCB, ArrayRef<uint8_t> Bytes, uint64_t Address,
194 raw_ostream &os, raw_ostream &cs, bool &Complete) const {
195 assert(Bytes.size() >= HEXAGON_INSTR_SIZE);
197 uint32_t Instruction =
198 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0);
200 auto BundleSize = HexagonMCInstrInfo::bundleSize(MCB);
201 if ((Instruction & HexagonII::INST_PARSE_MASK) ==
202 HexagonII::INST_PARSE_LOOP_END) {
204 HexagonMCInstrInfo::setInnerLoop(MCB);
205 else if (BundleSize == 1)
206 HexagonMCInstrInfo::setOuterLoop(MCB);
208 return DecodeStatus::Fail;
211 DecodeStatus Result = DecodeStatus::Success;
212 if ((Instruction & HexagonII::INST_PARSE_MASK) ==
213 HexagonII::INST_PARSE_DUPLEX) {
214 // Determine the instruction class of each instruction in the duplex.
215 unsigned duplexIClass, IClassLow, IClassHigh;
217 duplexIClass = ((Instruction >> 28) & 0xe) | ((Instruction >> 13) & 0x1);
218 switch (duplexIClass) {
220 return MCDisassembler::Fail;
222 IClassLow = HexagonII::HSIG_L1;
223 IClassHigh = HexagonII::HSIG_L1;
226 IClassLow = HexagonII::HSIG_L2;
227 IClassHigh = HexagonII::HSIG_L1;
230 IClassLow = HexagonII::HSIG_L2;
231 IClassHigh = HexagonII::HSIG_L2;
234 IClassLow = HexagonII::HSIG_A;
235 IClassHigh = HexagonII::HSIG_A;
238 IClassLow = HexagonII::HSIG_L1;
239 IClassHigh = HexagonII::HSIG_A;
242 IClassLow = HexagonII::HSIG_L2;
243 IClassHigh = HexagonII::HSIG_A;
246 IClassLow = HexagonII::HSIG_S1;
247 IClassHigh = HexagonII::HSIG_A;
250 IClassLow = HexagonII::HSIG_S2;
251 IClassHigh = HexagonII::HSIG_A;
254 IClassLow = HexagonII::HSIG_S1;
255 IClassHigh = HexagonII::HSIG_L1;
258 IClassLow = HexagonII::HSIG_S1;
259 IClassHigh = HexagonII::HSIG_L2;
262 IClassLow = HexagonII::HSIG_S1;
263 IClassHigh = HexagonII::HSIG_S1;
266 IClassLow = HexagonII::HSIG_S2;
267 IClassHigh = HexagonII::HSIG_S1;
270 IClassLow = HexagonII::HSIG_S2;
271 IClassHigh = HexagonII::HSIG_L1;
274 IClassLow = HexagonII::HSIG_S2;
275 IClassHigh = HexagonII::HSIG_L2;
278 IClassLow = HexagonII::HSIG_S2;
279 IClassHigh = HexagonII::HSIG_S2;
283 // Set the MCInst to be a duplex instruction. Which one doesn't matter.
284 MI.setOpcode(Hexagon::DuplexIClass0);
286 // Decode each instruction in the duplex.
287 // Create an MCInst for each instruction.
288 unsigned instLow = Instruction & 0x1fff;
289 unsigned instHigh = (Instruction >> 16) & 0x1fff;
291 if (GetSubinstOpcode(IClassLow, instLow, opLow, os) !=
292 MCDisassembler::Success)
293 return MCDisassembler::Fail;
295 if (GetSubinstOpcode(IClassHigh, instHigh, opHigh, os) !=
296 MCDisassembler::Success)
297 return MCDisassembler::Fail;
298 MCInst *MILow = new (getContext()) MCInst;
299 MILow->setOpcode(opLow);
300 MCInst *MIHigh = new (getContext()) MCInst;
301 MIHigh->setOpcode(opHigh);
302 addSubinstOperands(MILow, opLow, instLow);
303 addSubinstOperands(MIHigh, opHigh, instHigh);
304 // see ConvertToSubInst() in
305 // lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp
307 // Add the duplex instruction MCInsts as operands to the passed in MCInst.
308 MCOperand OPLow = MCOperand::createInst(MILow);
309 MCOperand OPHigh = MCOperand::createInst(MIHigh);
310 MI.addOperand(OPLow);
311 MI.addOperand(OPHigh);
314 if ((Instruction & HexagonII::INST_PARSE_MASK) ==
315 HexagonII::INST_PARSE_PACKET_END)
317 // Calling the auto-generated decoder function.
319 decodeInstruction(DecoderTable32, MI, Instruction, Address, this, STI);
321 // If a, "standard" insn isn't found check special cases.
322 if (MCDisassembler::Success != Result ||
323 MI.getOpcode() == Hexagon::A4_ext) {
324 Result = decodeImmext(MI, Instruction, this);
325 if (MCDisassembler::Success != Result) {
326 Result = decodeSpecial(MI, Instruction);
329 // If the instruction is a compound instruction, register values will
330 // follow the duplex model, so the register values in the MCInst are
331 // incorrect. If the instruction is a compound, loop through the
332 // operands and change registers appropriately.
333 if (llvm::HexagonMCInstrInfo::getType(*MCII, MI) ==
334 HexagonII::TypeCOMPOUND) {
335 for (MCInst::iterator i = MI.begin(), last = MI.end(); i < last; ++i) {
337 unsigned reg = i->getReg() - Hexagon::R0;
338 i->setReg(getRegFromSubinstEncoding(reg));
345 if (HexagonMCInstrInfo::isNewValue(*MCII, MI)) {
346 unsigned OpIndex = HexagonMCInstrInfo::getNewValueOp(*MCII, MI);
347 MCOperand &MCO = MI.getOperand(OpIndex);
348 assert(MCO.isReg() && "New value consumers must be registers");
350 getContext().getRegisterInfo()->getEncodingValue(MCO.getReg());
351 if ((Register & 0x6) == 0)
352 // HexagonPRM 10.11 Bit 1-2 == 0 is reserved
353 return MCDisassembler::Fail;
354 unsigned Lookback = (Register & 0x6) >> 1;
356 bool Vector = HexagonMCInstrInfo::isVector(*MCII, MI);
357 auto Instructions = HexagonMCInstrInfo::bundleInstructions(**CurrentBundle);
358 auto i = Instructions.end() - 1;
359 for (auto n = Instructions.begin() - 1;; --i, ++Offset) {
361 // Couldn't find producer
362 return MCDisassembler::Fail;
363 if (Vector && !HexagonMCInstrInfo::isVector(*MCII, *i->getInst()))
364 // Skip scalars when calculating distances for vectors
366 if (HexagonMCInstrInfo::isImmext(*i->getInst()))
368 if (Offset == Lookback)
371 auto const &Inst = *i->getInst();
372 bool SubregBit = (Register & 0x1) != 0;
373 if (SubregBit && HexagonMCInstrInfo::hasNewValue2(*MCII, Inst)) {
374 // If subreg bit is set we're selecting the second produced newvalue
376 HexagonMCInstrInfo::getNewValueOperand2(*MCII, Inst).getReg();
377 assert(Producer != Hexagon::NoRegister);
378 MCO.setReg(Producer);
379 } else if (HexagonMCInstrInfo::hasNewValue(*MCII, Inst)) {
381 HexagonMCInstrInfo::getNewValueOperand(*MCII, Inst).getReg();
382 if (Producer >= Hexagon::W0 && Producer <= Hexagon::W15)
383 Producer = ((Producer - Hexagon::W0) << 1) + SubregBit + Hexagon::V0;
385 // Subreg bit should not be set for non-doublevector newvalue producers
386 return MCDisassembler::Fail;
387 assert(Producer != Hexagon::NoRegister);
388 MCO.setReg(Producer);
390 return MCDisassembler::Fail;
393 adjustExtendedInstructions(MI, MCB);
394 MCInst const *Extender =
395 HexagonMCInstrInfo::extenderForIndex(MCB,
396 HexagonMCInstrInfo::bundleSize(MCB));
397 if(Extender != nullptr) {
398 MCInst const & Inst = HexagonMCInstrInfo::isDuplex(*MCII, MI) ?
399 *MI.getOperand(1).getInst() : MI;
400 if (!HexagonMCInstrInfo::isExtendable(*MCII, Inst) &&
401 !HexagonMCInstrInfo::isExtended(*MCII, Inst))
402 return MCDisassembler::Fail;
407 void HexagonDisassembler::adjustExtendedInstructions(MCInst &MCI,
408 MCInst const &MCB) const {
409 if (!HexagonMCInstrInfo::hasExtenderForIndex(
410 MCB, HexagonMCInstrInfo::bundleSize(MCB))) {
412 // This code is used by the disassembler to disambiguate between GP
413 // relative and absolute addressing instructions since they both have
414 // same encoding bits. However, an absolute addressing instruction must
415 // follow an immediate extender. Disassembler alwaus select absolute
416 // addressing instructions first and uses this code to change them into
417 // GP relative instruction in the absence of the corresponding immediate
419 switch (MCI.getOpcode()) {
420 case Hexagon::S2_storerbabs:
421 opcode = Hexagon::S2_storerbgp;
423 case Hexagon::S2_storerhabs:
424 opcode = Hexagon::S2_storerhgp;
426 case Hexagon::S2_storerfabs:
427 opcode = Hexagon::S2_storerfgp;
429 case Hexagon::S2_storeriabs:
430 opcode = Hexagon::S2_storerigp;
432 case Hexagon::S2_storerbnewabs:
433 opcode = Hexagon::S2_storerbnewgp;
435 case Hexagon::S2_storerhnewabs:
436 opcode = Hexagon::S2_storerhnewgp;
438 case Hexagon::S2_storerinewabs:
439 opcode = Hexagon::S2_storerinewgp;
441 case Hexagon::S2_storerdabs:
442 opcode = Hexagon::S2_storerdgp;
444 case Hexagon::L4_loadrb_abs:
445 opcode = Hexagon::L2_loadrbgp;
447 case Hexagon::L4_loadrub_abs:
448 opcode = Hexagon::L2_loadrubgp;
450 case Hexagon::L4_loadrh_abs:
451 opcode = Hexagon::L2_loadrhgp;
453 case Hexagon::L4_loadruh_abs:
454 opcode = Hexagon::L2_loadruhgp;
456 case Hexagon::L4_loadri_abs:
457 opcode = Hexagon::L2_loadrigp;
459 case Hexagon::L4_loadrd_abs:
460 opcode = Hexagon::L2_loadrdgp;
463 opcode = MCI.getOpcode();
465 MCI.setOpcode(opcode);
470 extern const MCInstrDesc HexagonInsts[];
473 static DecodeStatus DecodeRegisterClass(MCInst &Inst, unsigned RegNo,
474 ArrayRef<uint16_t> Table) {
475 if (RegNo < Table.size()) {
476 Inst.addOperand(MCOperand::createReg(Table[RegNo]));
477 return MCDisassembler::Success;
480 return MCDisassembler::Fail;
483 static DecodeStatus DecodeIntRegsLow8RegisterClass(MCInst &Inst, unsigned RegNo,
485 const void *Decoder) {
486 return DecodeIntRegsRegisterClass(Inst, RegNo, Address, Decoder);
489 static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo,
491 const void *Decoder) {
492 static const uint16_t IntRegDecoderTable[] = {
493 Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4,
494 Hexagon::R5, Hexagon::R6, Hexagon::R7, Hexagon::R8, Hexagon::R9,
495 Hexagon::R10, Hexagon::R11, Hexagon::R12, Hexagon::R13, Hexagon::R14,
496 Hexagon::R15, Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19,
497 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, Hexagon::R24,
498 Hexagon::R25, Hexagon::R26, Hexagon::R27, Hexagon::R28, Hexagon::R29,
499 Hexagon::R30, Hexagon::R31};
501 return (DecodeRegisterClass(Inst, RegNo, IntRegDecoderTable));
504 static DecodeStatus DecodeVectorRegsRegisterClass(MCInst &Inst, unsigned RegNo,
505 uint64_t /*Address*/,
506 const void *Decoder) {
507 static const uint16_t VecRegDecoderTable[] = {
508 Hexagon::V0, Hexagon::V1, Hexagon::V2, Hexagon::V3, Hexagon::V4,
509 Hexagon::V5, Hexagon::V6, Hexagon::V7, Hexagon::V8, Hexagon::V9,
510 Hexagon::V10, Hexagon::V11, Hexagon::V12, Hexagon::V13, Hexagon::V14,
511 Hexagon::V15, Hexagon::V16, Hexagon::V17, Hexagon::V18, Hexagon::V19,
512 Hexagon::V20, Hexagon::V21, Hexagon::V22, Hexagon::V23, Hexagon::V24,
513 Hexagon::V25, Hexagon::V26, Hexagon::V27, Hexagon::V28, Hexagon::V29,
514 Hexagon::V30, Hexagon::V31};
516 return (DecodeRegisterClass(Inst, RegNo, VecRegDecoderTable));
519 static DecodeStatus DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo,
520 uint64_t /*Address*/,
521 const void *Decoder) {
522 static const uint16_t DoubleRegDecoderTable[] = {
523 Hexagon::D0, Hexagon::D1, Hexagon::D2, Hexagon::D3,
524 Hexagon::D4, Hexagon::D5, Hexagon::D6, Hexagon::D7,
525 Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11,
526 Hexagon::D12, Hexagon::D13, Hexagon::D14, Hexagon::D15};
528 return (DecodeRegisterClass(Inst, RegNo >> 1, DoubleRegDecoderTable));
531 static DecodeStatus DecodeVecDblRegsRegisterClass(MCInst &Inst, unsigned RegNo,
532 uint64_t /*Address*/,
533 const void *Decoder) {
534 static const uint16_t VecDblRegDecoderTable[] = {
535 Hexagon::W0, Hexagon::W1, Hexagon::W2, Hexagon::W3,
536 Hexagon::W4, Hexagon::W5, Hexagon::W6, Hexagon::W7,
537 Hexagon::W8, Hexagon::W9, Hexagon::W10, Hexagon::W11,
538 Hexagon::W12, Hexagon::W13, Hexagon::W14, Hexagon::W15};
540 return (DecodeRegisterClass(Inst, RegNo >> 1, VecDblRegDecoderTable));
543 static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo,
544 uint64_t /*Address*/,
545 const void *Decoder) {
546 static const uint16_t PredRegDecoderTable[] = {Hexagon::P0, Hexagon::P1,
547 Hexagon::P2, Hexagon::P3};
549 return (DecodeRegisterClass(Inst, RegNo, PredRegDecoderTable));
552 static DecodeStatus DecodeVecPredRegsRegisterClass(MCInst &Inst, unsigned RegNo,
553 uint64_t /*Address*/,
554 const void *Decoder) {
555 static const uint16_t VecPredRegDecoderTable[] = {Hexagon::Q0, Hexagon::Q1,
556 Hexagon::Q2, Hexagon::Q3};
558 return (DecodeRegisterClass(Inst, RegNo, VecPredRegDecoderTable));
561 static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo,
562 uint64_t /*Address*/,
563 const void *Decoder) {
564 static const uint16_t CtrlRegDecoderTable[] = {
565 Hexagon::SA0, Hexagon::LC0, Hexagon::SA1, Hexagon::LC1,
566 Hexagon::P3_0, Hexagon::C5, Hexagon::C6, Hexagon::C7,
567 Hexagon::USR, Hexagon::PC, Hexagon::UGP, Hexagon::GP,
568 Hexagon::CS0, Hexagon::CS1, Hexagon::UPCL, Hexagon::UPC
571 if (RegNo >= array_lengthof(CtrlRegDecoderTable))
572 return MCDisassembler::Fail;
574 if (CtrlRegDecoderTable[RegNo] == Hexagon::NoRegister)
575 return MCDisassembler::Fail;
577 unsigned Register = CtrlRegDecoderTable[RegNo];
578 Inst.addOperand(MCOperand::createReg(Register));
579 return MCDisassembler::Success;
582 static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo,
583 uint64_t /*Address*/,
584 const void *Decoder) {
585 static const uint16_t CtrlReg64DecoderTable[] = {
586 Hexagon::C1_0, Hexagon::NoRegister,
587 Hexagon::C3_2, Hexagon::NoRegister,
588 Hexagon::C7_6, Hexagon::NoRegister,
589 Hexagon::C9_8, Hexagon::NoRegister,
590 Hexagon::C11_10, Hexagon::NoRegister,
591 Hexagon::CS, Hexagon::NoRegister,
592 Hexagon::UPC, Hexagon::NoRegister
595 if (RegNo >= array_lengthof(CtrlReg64DecoderTable))
596 return MCDisassembler::Fail;
598 if (CtrlReg64DecoderTable[RegNo] == Hexagon::NoRegister)
599 return MCDisassembler::Fail;
601 unsigned Register = CtrlReg64DecoderTable[RegNo];
602 Inst.addOperand(MCOperand::createReg(Register));
603 return MCDisassembler::Success;
606 static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo,
607 uint64_t /*Address*/,
608 const void *Decoder) {
609 unsigned Register = 0;
612 Register = Hexagon::M0;
615 Register = Hexagon::M1;
618 return MCDisassembler::Fail;
620 Inst.addOperand(MCOperand::createReg(Register));
621 return MCDisassembler::Success;
625 uint32_t fullValue(MCInstrInfo const &MCII,
629 MCInst const *Extender = HexagonMCInstrInfo::extenderForIndex(
630 MCB, HexagonMCInstrInfo::bundleSize(MCB));
631 if(!Extender || MI.size() != HexagonMCInstrInfo::getExtendableOp(MCII, MI))
633 unsigned Alignment = HexagonMCInstrInfo::getExtentAlignment(MCII, MI);
634 uint32_t Lower6 = static_cast<uint32_t>(Value >> Alignment) & 0x3f;
636 bool Success = Extender->getOperand(0).getExpr()->evaluateAsAbsolute(Bits);
637 assert(Success);(void)Success;
638 uint32_t Upper26 = static_cast<uint32_t>(Bits);
639 uint32_t Operand = Upper26 | Lower6;
643 void signedDecoder(MCInst &MI, unsigned tmp, const void *Decoder) {
644 HexagonDisassembler const &Disassembler = disassembler(Decoder);
645 int64_t FullValue = fullValue(*Disassembler.MCII,
646 **Disassembler.CurrentBundle,
647 MI, SignExtend64<T>(tmp));
648 int64_t Extended = SignExtend64<32>(FullValue);
649 HexagonMCInstrInfo::addConstant(MI, Extended,
650 Disassembler.getContext());
654 static DecodeStatus unsignedImmDecoder(MCInst &MI, unsigned tmp,
655 uint64_t /*Address*/,
656 const void *Decoder) {
657 HexagonDisassembler const &Disassembler = disassembler(Decoder);
658 int64_t FullValue = fullValue(*Disassembler.MCII,
659 **Disassembler.CurrentBundle,
661 assert(FullValue >= 0 && "Negative in unsigned decoder");
662 HexagonMCInstrInfo::addConstant(MI, FullValue, Disassembler.getContext());
663 return MCDisassembler::Success;
666 static DecodeStatus s16ImmDecoder(MCInst &MI, unsigned tmp,
667 uint64_t /*Address*/, const void *Decoder) {
668 signedDecoder<16>(MI, tmp, Decoder);
669 return MCDisassembler::Success;
672 static DecodeStatus s12ImmDecoder(MCInst &MI, unsigned tmp,
673 uint64_t /*Address*/, const void *Decoder) {
674 signedDecoder<12>(MI, tmp, Decoder);
675 return MCDisassembler::Success;
678 static DecodeStatus s11_0ImmDecoder(MCInst &MI, unsigned tmp,
679 uint64_t /*Address*/, const void *Decoder) {
680 signedDecoder<11>(MI, tmp, Decoder);
681 return MCDisassembler::Success;
684 static DecodeStatus s11_1ImmDecoder(MCInst &MI, unsigned tmp,
685 uint64_t /*Address*/, const void *Decoder) {
686 HexagonMCInstrInfo::addConstant(MI, SignExtend64<12>(tmp), contextFromDecoder(Decoder));
687 return MCDisassembler::Success;
690 static DecodeStatus s11_2ImmDecoder(MCInst &MI, unsigned tmp,
691 uint64_t /*Address*/, const void *Decoder) {
692 signedDecoder<13>(MI, tmp, Decoder);
693 return MCDisassembler::Success;
696 static DecodeStatus s11_3ImmDecoder(MCInst &MI, unsigned tmp,
697 uint64_t /*Address*/, const void *Decoder) {
698 signedDecoder<14>(MI, tmp, Decoder);
699 return MCDisassembler::Success;
702 static DecodeStatus s10ImmDecoder(MCInst &MI, unsigned tmp,
703 uint64_t /*Address*/, const void *Decoder) {
704 signedDecoder<10>(MI, tmp, Decoder);
705 return MCDisassembler::Success;
708 static DecodeStatus s8ImmDecoder(MCInst &MI, unsigned tmp, uint64_t /*Address*/,
709 const void *Decoder) {
710 signedDecoder<8>(MI, tmp, Decoder);
711 return MCDisassembler::Success;
714 static DecodeStatus s6_0ImmDecoder(MCInst &MI, unsigned tmp,
715 uint64_t /*Address*/, const void *Decoder) {
716 signedDecoder<6>(MI, tmp, Decoder);
717 return MCDisassembler::Success;
720 static DecodeStatus s4_0ImmDecoder(MCInst &MI, unsigned tmp,
721 uint64_t /*Address*/, const void *Decoder) {
722 signedDecoder<4>(MI, tmp, Decoder);
723 return MCDisassembler::Success;
726 static DecodeStatus s4_1ImmDecoder(MCInst &MI, unsigned tmp,
727 uint64_t /*Address*/, const void *Decoder) {
728 signedDecoder<5>(MI, tmp, Decoder);
729 return MCDisassembler::Success;
732 static DecodeStatus s4_2ImmDecoder(MCInst &MI, unsigned tmp,
733 uint64_t /*Address*/, const void *Decoder) {
734 signedDecoder<6>(MI, tmp, Decoder);
735 return MCDisassembler::Success;
738 static DecodeStatus s4_3ImmDecoder(MCInst &MI, unsigned tmp,
739 uint64_t /*Address*/, const void *Decoder) {
740 signedDecoder<7>(MI, tmp, Decoder);
741 return MCDisassembler::Success;
744 static DecodeStatus s4_6ImmDecoder(MCInst &MI, unsigned tmp,
745 uint64_t /*Address*/, const void *Decoder) {
746 signedDecoder<10>(MI, tmp, Decoder);
747 return MCDisassembler::Success;
750 static DecodeStatus s3_6ImmDecoder(MCInst &MI, unsigned tmp,
751 uint64_t /*Address*/, const void *Decoder) {
752 signedDecoder<19>(MI, tmp, Decoder);
753 return MCDisassembler::Success;
756 // custom decoder for various jump/call immediates
757 static DecodeStatus brtargetDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
758 const void *Decoder) {
759 HexagonDisassembler const &Disassembler = disassembler(Decoder);
760 unsigned Bits = HexagonMCInstrInfo::getExtentBits(*Disassembler.MCII, MI);
761 // r13_2 is not extendable, so if there are no extent bits, it's r13_2
764 uint32_t FullValue = fullValue(*Disassembler.MCII,
765 **Disassembler.CurrentBundle,
766 MI, SignExtend64(tmp, Bits));
767 int64_t Extended = SignExtend64<32>(FullValue) + Address;
768 if (!Disassembler.tryAddingSymbolicOperand(MI, Extended, Address, true,
770 HexagonMCInstrInfo::addConstant(MI, Extended, Disassembler.getContext());
771 return MCDisassembler::Success;
774 // Addressing mode dependent load store opcode map.
775 // - If an insn is preceded by an extender the address is absolute.
776 // - memw(##symbol) = r0
777 // - If an insn is not preceded by an extender the address is GP relative.
778 // - memw(gp + #symbol) = r0
779 // Please note that the instructions must be ordered in the descending order
781 // HexagonII::INST_ICLASS_ST
782 static const unsigned int StoreConditionalOpcodeData[][2] = {
783 {S4_pstorerdfnew_abs, 0xafc02084},
784 {S4_pstorerdtnew_abs, 0xafc02080},
785 {S4_pstorerdf_abs, 0xafc00084},
786 {S4_pstorerdt_abs, 0xafc00080},
787 {S4_pstorerinewfnew_abs, 0xafa03084},
788 {S4_pstorerinewtnew_abs, 0xafa03080},
789 {S4_pstorerhnewfnew_abs, 0xafa02884},
790 {S4_pstorerhnewtnew_abs, 0xafa02880},
791 {S4_pstorerbnewfnew_abs, 0xafa02084},
792 {S4_pstorerbnewtnew_abs, 0xafa02080},
793 {S4_pstorerinewf_abs, 0xafa01084},
794 {S4_pstorerinewt_abs, 0xafa01080},
795 {S4_pstorerhnewf_abs, 0xafa00884},
796 {S4_pstorerhnewt_abs, 0xafa00880},
797 {S4_pstorerbnewf_abs, 0xafa00084},
798 {S4_pstorerbnewt_abs, 0xafa00080},
799 {S4_pstorerifnew_abs, 0xaf802084},
800 {S4_pstoreritnew_abs, 0xaf802080},
801 {S4_pstorerif_abs, 0xaf800084},
802 {S4_pstorerit_abs, 0xaf800080},
803 {S4_pstorerhfnew_abs, 0xaf402084},
804 {S4_pstorerhtnew_abs, 0xaf402080},
805 {S4_pstorerhf_abs, 0xaf400084},
806 {S4_pstorerht_abs, 0xaf400080},
807 {S4_pstorerbfnew_abs, 0xaf002084},
808 {S4_pstorerbtnew_abs, 0xaf002080},
809 {S4_pstorerbf_abs, 0xaf000084},
810 {S4_pstorerbt_abs, 0xaf000080}};
811 // HexagonII::INST_ICLASS_LD
813 // HexagonII::INST_ICLASS_LD_ST_2
814 static unsigned int LoadStoreOpcodeData[][2] = {{L4_loadrd_abs, 0x49c00000},
815 {L4_loadri_abs, 0x49800000},
816 {L4_loadruh_abs, 0x49600000},
817 {L4_loadrh_abs, 0x49400000},
818 {L4_loadrub_abs, 0x49200000},
819 {L4_loadrb_abs, 0x49000000},
820 {S2_storerdabs, 0x48c00000},
821 {S2_storerinewabs, 0x48a01000},
822 {S2_storerhnewabs, 0x48a00800},
823 {S2_storerbnewabs, 0x48a00000},
824 {S2_storeriabs, 0x48800000},
825 {S2_storerfabs, 0x48600000},
826 {S2_storerhabs, 0x48400000},
827 {S2_storerbabs, 0x48000000}};
828 static const size_t NumCondS = array_lengthof(StoreConditionalOpcodeData);
829 static const size_t NumLS = array_lengthof(LoadStoreOpcodeData);
831 static DecodeStatus decodeSpecial(MCInst &MI, uint32_t insn) {
833 unsigned MachineOpcode = 0;
834 unsigned LLVMOpcode = 0;
836 if ((insn & HexagonII::INST_ICLASS_MASK) == HexagonII::INST_ICLASS_ST) {
837 for (size_t i = 0; i < NumCondS; ++i) {
838 if ((insn & StoreConditionalOpcodeData[i][1]) ==
839 StoreConditionalOpcodeData[i][1]) {
840 MachineOpcode = StoreConditionalOpcodeData[i][1];
841 LLVMOpcode = StoreConditionalOpcodeData[i][0];
846 if ((insn & HexagonII::INST_ICLASS_MASK) == HexagonII::INST_ICLASS_LD_ST_2) {
847 for (size_t i = 0; i < NumLS; ++i) {
848 if ((insn & LoadStoreOpcodeData[i][1]) == LoadStoreOpcodeData[i][1]) {
849 MachineOpcode = LoadStoreOpcodeData[i][1];
850 LLVMOpcode = LoadStoreOpcodeData[i][0];
859 MI.setOpcode(LLVMOpcode);
860 // Remove the parse bits from the insn.
861 insn &= ~HexagonII::INST_PARSE_MASK;
863 switch (LLVMOpcode) {
865 return MCDisassembler::Fail;
868 case Hexagon::S4_pstorerdf_abs:
869 case Hexagon::S4_pstorerdt_abs:
870 case Hexagon::S4_pstorerdfnew_abs:
871 case Hexagon::S4_pstorerdtnew_abs: {
873 Value = insn & UINT64_C(3);
874 DecodePredRegsRegisterClass(MI, Value, 0, 0);
876 Value = (insn >> 12) & UINT64_C(48);
877 Value |= (insn >> 3) & UINT64_C(15);
878 MI.addOperand(MCOperand::createImm(Value));
880 Value = (insn >> 8) & UINT64_C(31);
881 DecodeDoubleRegsRegisterClass(MI, Value, 0, 0);
885 case Hexagon::S4_pstorerbnewf_abs:
886 case Hexagon::S4_pstorerbnewt_abs:
887 case Hexagon::S4_pstorerbnewfnew_abs:
888 case Hexagon::S4_pstorerbnewtnew_abs:
889 case Hexagon::S4_pstorerhnewf_abs:
890 case Hexagon::S4_pstorerhnewt_abs:
891 case Hexagon::S4_pstorerhnewfnew_abs:
892 case Hexagon::S4_pstorerhnewtnew_abs:
893 case Hexagon::S4_pstorerinewf_abs:
894 case Hexagon::S4_pstorerinewt_abs:
895 case Hexagon::S4_pstorerinewfnew_abs:
896 case Hexagon::S4_pstorerinewtnew_abs: {
898 Value = insn & UINT64_C(3);
899 DecodePredRegsRegisterClass(MI, Value, 0, 0);
901 Value = (insn >> 12) & UINT64_C(48);
902 Value |= (insn >> 3) & UINT64_C(15);
903 MI.addOperand(MCOperand::createImm(Value));
905 Value = (insn >> 8) & UINT64_C(7);
906 DecodeIntRegsRegisterClass(MI, Value, 0, 0);
910 case Hexagon::S4_pstorerbf_abs:
911 case Hexagon::S4_pstorerbt_abs:
912 case Hexagon::S4_pstorerbfnew_abs:
913 case Hexagon::S4_pstorerbtnew_abs:
914 case Hexagon::S4_pstorerhf_abs:
915 case Hexagon::S4_pstorerht_abs:
916 case Hexagon::S4_pstorerhfnew_abs:
917 case Hexagon::S4_pstorerhtnew_abs:
918 case Hexagon::S4_pstorerif_abs:
919 case Hexagon::S4_pstorerit_abs:
920 case Hexagon::S4_pstorerifnew_abs:
921 case Hexagon::S4_pstoreritnew_abs: {
923 Value = insn & UINT64_C(3);
924 DecodePredRegsRegisterClass(MI, Value, 0, 0);
926 Value = (insn >> 12) & UINT64_C(48);
927 Value |= (insn >> 3) & UINT64_C(15);
928 MI.addOperand(MCOperand::createImm(Value));
930 Value = (insn >> 8) & UINT64_C(31);
931 DecodeIntRegsRegisterClass(MI, Value, 0, 0);
935 case Hexagon::L4_ploadrdf_abs:
936 case Hexagon::L4_ploadrdt_abs:
937 case Hexagon::L4_ploadrdfnew_abs:
938 case Hexagon::L4_ploadrdtnew_abs: {
940 Value = insn & UINT64_C(31);
941 DecodeDoubleRegsRegisterClass(MI, Value, 0, 0);
943 Value = ((insn >> 9) & UINT64_C(3));
944 DecodePredRegsRegisterClass(MI, Value, 0, 0);
946 Value = ((insn >> 15) & UINT64_C(62));
947 Value |= ((insn >> 8) & UINT64_C(1));
948 MI.addOperand(MCOperand::createImm(Value));
952 case Hexagon::L4_ploadrbf_abs:
953 case Hexagon::L4_ploadrbt_abs:
954 case Hexagon::L4_ploadrbfnew_abs:
955 case Hexagon::L4_ploadrbtnew_abs:
956 case Hexagon::L4_ploadrhf_abs:
957 case Hexagon::L4_ploadrht_abs:
958 case Hexagon::L4_ploadrhfnew_abs:
959 case Hexagon::L4_ploadrhtnew_abs:
960 case Hexagon::L4_ploadrubf_abs:
961 case Hexagon::L4_ploadrubt_abs:
962 case Hexagon::L4_ploadrubfnew_abs:
963 case Hexagon::L4_ploadrubtnew_abs:
964 case Hexagon::L4_ploadruhf_abs:
965 case Hexagon::L4_ploadruht_abs:
966 case Hexagon::L4_ploadruhfnew_abs:
967 case Hexagon::L4_ploadruhtnew_abs:
968 case Hexagon::L4_ploadrif_abs:
969 case Hexagon::L4_ploadrit_abs:
970 case Hexagon::L4_ploadrifnew_abs:
971 case Hexagon::L4_ploadritnew_abs:
973 Value = insn & UINT64_C(31);
974 DecodeIntRegsRegisterClass(MI, Value, 0, 0);
976 Value = (insn >> 9) & UINT64_C(3);
977 DecodePredRegsRegisterClass(MI, Value, 0, 0);
979 Value = (insn >> 15) & UINT64_C(62);
980 Value |= (insn >> 8) & UINT64_C(1);
981 MI.addOperand(MCOperand::createImm(Value));
985 case (Hexagon::L4_loadri_abs):
988 case Hexagon::L4_loadrh_abs:
989 case Hexagon::L4_loadruh_abs:
992 case Hexagon::L4_loadrb_abs:
993 case Hexagon::L4_loadrub_abs: {
995 Value |= insn & UINT64_C(31);
996 DecodeIntRegsRegisterClass(MI, Value, 0, 0);
997 Value = (insn >> 11) & UINT64_C(49152);
998 Value |= (insn >> 7) & UINT64_C(15872);
999 Value |= (insn >> 5) & UINT64_C(511);
1000 MI.addOperand(MCOperand::createImm(Value << shift));
1004 case Hexagon::L4_loadrd_abs: {
1005 Value = insn & UINT64_C(31);
1006 DecodeDoubleRegsRegisterClass(MI, Value, 0, 0);
1007 Value = (insn >> 11) & UINT64_C(49152);
1008 Value |= (insn >> 7) & UINT64_C(15872);
1009 Value |= (insn >> 5) & UINT64_C(511);
1010 MI.addOperand(MCOperand::createImm(Value << 3));
1014 case Hexagon::S2_storerdabs: {
1016 Value = (insn >> 11) & UINT64_C(49152);
1017 Value |= (insn >> 7) & UINT64_C(15872);
1018 Value |= (insn >> 5) & UINT64_C(256);
1019 Value |= insn & UINT64_C(255);
1020 MI.addOperand(MCOperand::createImm(Value << 3));
1022 Value = (insn >> 8) & UINT64_C(31);
1023 DecodeDoubleRegsRegisterClass(MI, Value, 0, 0);
1028 case Hexagon::S2_storerinewabs:
1031 case Hexagon::S2_storerhnewabs:
1034 case Hexagon::S2_storerbnewabs: {
1035 Value = (insn >> 11) & UINT64_C(49152);
1036 Value |= (insn >> 7) & UINT64_C(15872);
1037 Value |= (insn >> 5) & UINT64_C(256);
1038 Value |= insn & UINT64_C(255);
1039 MI.addOperand(MCOperand::createImm(Value << shift));
1041 Value = (insn >> 8) & UINT64_C(7);
1042 DecodeIntRegsRegisterClass(MI, Value, 0, 0);
1047 case Hexagon::S2_storeriabs:
1050 case Hexagon::S2_storerhabs:
1051 case Hexagon::S2_storerfabs:
1054 case Hexagon::S2_storerbabs: {
1055 Value = (insn >> 11) & UINT64_C(49152);
1056 Value |= (insn >> 7) & UINT64_C(15872);
1057 Value |= (insn >> 5) & UINT64_C(256);
1058 Value |= insn & UINT64_C(255);
1059 MI.addOperand(MCOperand::createImm(Value << shift));
1061 Value = (insn >> 8) & UINT64_C(31);
1062 DecodeIntRegsRegisterClass(MI, Value, 0, 0);
1066 return MCDisassembler::Success;
1068 return MCDisassembler::Fail;
1071 static DecodeStatus decodeImmext(MCInst &MI, uint32_t insn,
1072 void const *Decoder) {
1074 // Instruction Class for a constant a extender: bits 31:28 = 0x0000
1075 if ((~insn & 0xf0000000) == 0xf0000000) {
1077 // 27:16 High 12 bits of 26-bit extender.
1078 Value = (insn & 0x0fff0000) << 4;
1079 // 13:0 Low 14 bits of 26-bit extender.
1080 Value |= ((insn & 0x3fff) << 6);
1081 MI.setOpcode(Hexagon::A4_ext);
1082 HexagonMCInstrInfo::addConstant(MI, Value, contextFromDecoder(Decoder));
1083 return MCDisassembler::Success;
1085 return MCDisassembler::Fail;
1088 // These values are from HexagonGenMCCodeEmitter.inc and HexagonIsetDx.td
1089 enum subInstBinaryValues {
1090 V4_SA1_addi_BITS = 0x0000,
1091 V4_SA1_addi_MASK = 0x1800,
1092 V4_SA1_addrx_BITS = 0x1800,
1093 V4_SA1_addrx_MASK = 0x1f00,
1094 V4_SA1_addsp_BITS = 0x0c00,
1095 V4_SA1_addsp_MASK = 0x1c00,
1096 V4_SA1_and1_BITS = 0x1200,
1097 V4_SA1_and1_MASK = 0x1f00,
1098 V4_SA1_clrf_BITS = 0x1a70,
1099 V4_SA1_clrf_MASK = 0x1e70,
1100 V4_SA1_clrfnew_BITS = 0x1a50,
1101 V4_SA1_clrfnew_MASK = 0x1e70,
1102 V4_SA1_clrt_BITS = 0x1a60,
1103 V4_SA1_clrt_MASK = 0x1e70,
1104 V4_SA1_clrtnew_BITS = 0x1a40,
1105 V4_SA1_clrtnew_MASK = 0x1e70,
1106 V4_SA1_cmpeqi_BITS = 0x1900,
1107 V4_SA1_cmpeqi_MASK = 0x1f00,
1108 V4_SA1_combine0i_BITS = 0x1c00,
1109 V4_SA1_combine0i_MASK = 0x1d18,
1110 V4_SA1_combine1i_BITS = 0x1c08,
1111 V4_SA1_combine1i_MASK = 0x1d18,
1112 V4_SA1_combine2i_BITS = 0x1c10,
1113 V4_SA1_combine2i_MASK = 0x1d18,
1114 V4_SA1_combine3i_BITS = 0x1c18,
1115 V4_SA1_combine3i_MASK = 0x1d18,
1116 V4_SA1_combinerz_BITS = 0x1d08,
1117 V4_SA1_combinerz_MASK = 0x1d08,
1118 V4_SA1_combinezr_BITS = 0x1d00,
1119 V4_SA1_combinezr_MASK = 0x1d08,
1120 V4_SA1_dec_BITS = 0x1300,
1121 V4_SA1_dec_MASK = 0x1f00,
1122 V4_SA1_inc_BITS = 0x1100,
1123 V4_SA1_inc_MASK = 0x1f00,
1124 V4_SA1_seti_BITS = 0x0800,
1125 V4_SA1_seti_MASK = 0x1c00,
1126 V4_SA1_setin1_BITS = 0x1a00,
1127 V4_SA1_setin1_MASK = 0x1e40,
1128 V4_SA1_sxtb_BITS = 0x1500,
1129 V4_SA1_sxtb_MASK = 0x1f00,
1130 V4_SA1_sxth_BITS = 0x1400,
1131 V4_SA1_sxth_MASK = 0x1f00,
1132 V4_SA1_tfr_BITS = 0x1000,
1133 V4_SA1_tfr_MASK = 0x1f00,
1134 V4_SA1_zxtb_BITS = 0x1700,
1135 V4_SA1_zxtb_MASK = 0x1f00,
1136 V4_SA1_zxth_BITS = 0x1600,
1137 V4_SA1_zxth_MASK = 0x1f00,
1138 V4_SL1_loadri_io_BITS = 0x0000,
1139 V4_SL1_loadri_io_MASK = 0x1000,
1140 V4_SL1_loadrub_io_BITS = 0x1000,
1141 V4_SL1_loadrub_io_MASK = 0x1000,
1142 V4_SL2_deallocframe_BITS = 0x1f00,
1143 V4_SL2_deallocframe_MASK = 0x1fc0,
1144 V4_SL2_jumpr31_BITS = 0x1fc0,
1145 V4_SL2_jumpr31_MASK = 0x1fc4,
1146 V4_SL2_jumpr31_f_BITS = 0x1fc5,
1147 V4_SL2_jumpr31_f_MASK = 0x1fc7,
1148 V4_SL2_jumpr31_fnew_BITS = 0x1fc7,
1149 V4_SL2_jumpr31_fnew_MASK = 0x1fc7,
1150 V4_SL2_jumpr31_t_BITS = 0x1fc4,
1151 V4_SL2_jumpr31_t_MASK = 0x1fc7,
1152 V4_SL2_jumpr31_tnew_BITS = 0x1fc6,
1153 V4_SL2_jumpr31_tnew_MASK = 0x1fc7,
1154 V4_SL2_loadrb_io_BITS = 0x1000,
1155 V4_SL2_loadrb_io_MASK = 0x1800,
1156 V4_SL2_loadrd_sp_BITS = 0x1e00,
1157 V4_SL2_loadrd_sp_MASK = 0x1f00,
1158 V4_SL2_loadrh_io_BITS = 0x0000,
1159 V4_SL2_loadrh_io_MASK = 0x1800,
1160 V4_SL2_loadri_sp_BITS = 0x1c00,
1161 V4_SL2_loadri_sp_MASK = 0x1e00,
1162 V4_SL2_loadruh_io_BITS = 0x0800,
1163 V4_SL2_loadruh_io_MASK = 0x1800,
1164 V4_SL2_return_BITS = 0x1f40,
1165 V4_SL2_return_MASK = 0x1fc4,
1166 V4_SL2_return_f_BITS = 0x1f45,
1167 V4_SL2_return_f_MASK = 0x1fc7,
1168 V4_SL2_return_fnew_BITS = 0x1f47,
1169 V4_SL2_return_fnew_MASK = 0x1fc7,
1170 V4_SL2_return_t_BITS = 0x1f44,
1171 V4_SL2_return_t_MASK = 0x1fc7,
1172 V4_SL2_return_tnew_BITS = 0x1f46,
1173 V4_SL2_return_tnew_MASK = 0x1fc7,
1174 V4_SS1_storeb_io_BITS = 0x1000,
1175 V4_SS1_storeb_io_MASK = 0x1000,
1176 V4_SS1_storew_io_BITS = 0x0000,
1177 V4_SS1_storew_io_MASK = 0x1000,
1178 V4_SS2_allocframe_BITS = 0x1c00,
1179 V4_SS2_allocframe_MASK = 0x1e00,
1180 V4_SS2_storebi0_BITS = 0x1200,
1181 V4_SS2_storebi0_MASK = 0x1f00,
1182 V4_SS2_storebi1_BITS = 0x1300,
1183 V4_SS2_storebi1_MASK = 0x1f00,
1184 V4_SS2_stored_sp_BITS = 0x0a00,
1185 V4_SS2_stored_sp_MASK = 0x1e00,
1186 V4_SS2_storeh_io_BITS = 0x0000,
1187 V4_SS2_storeh_io_MASK = 0x1800,
1188 V4_SS2_storew_sp_BITS = 0x0800,
1189 V4_SS2_storew_sp_MASK = 0x1e00,
1190 V4_SS2_storewi0_BITS = 0x1000,
1191 V4_SS2_storewi0_MASK = 0x1f00,
1192 V4_SS2_storewi1_BITS = 0x1100,
1193 V4_SS2_storewi1_MASK = 0x1f00
1196 static unsigned GetSubinstOpcode(unsigned IClass, unsigned inst, unsigned &op,
1199 case HexagonII::HSIG_L1:
1200 if ((inst & V4_SL1_loadri_io_MASK) == V4_SL1_loadri_io_BITS)
1201 op = Hexagon::V4_SL1_loadri_io;
1202 else if ((inst & V4_SL1_loadrub_io_MASK) == V4_SL1_loadrub_io_BITS)
1203 op = Hexagon::V4_SL1_loadrub_io;
1205 os << "<unknown subinstruction>";
1206 return MCDisassembler::Fail;
1209 case HexagonII::HSIG_L2:
1210 if ((inst & V4_SL2_deallocframe_MASK) == V4_SL2_deallocframe_BITS)
1211 op = Hexagon::V4_SL2_deallocframe;
1212 else if ((inst & V4_SL2_jumpr31_MASK) == V4_SL2_jumpr31_BITS)
1213 op = Hexagon::V4_SL2_jumpr31;
1214 else if ((inst & V4_SL2_jumpr31_f_MASK) == V4_SL2_jumpr31_f_BITS)
1215 op = Hexagon::V4_SL2_jumpr31_f;
1216 else if ((inst & V4_SL2_jumpr31_fnew_MASK) == V4_SL2_jumpr31_fnew_BITS)
1217 op = Hexagon::V4_SL2_jumpr31_fnew;
1218 else if ((inst & V4_SL2_jumpr31_t_MASK) == V4_SL2_jumpr31_t_BITS)
1219 op = Hexagon::V4_SL2_jumpr31_t;
1220 else if ((inst & V4_SL2_jumpr31_tnew_MASK) == V4_SL2_jumpr31_tnew_BITS)
1221 op = Hexagon::V4_SL2_jumpr31_tnew;
1222 else if ((inst & V4_SL2_loadrb_io_MASK) == V4_SL2_loadrb_io_BITS)
1223 op = Hexagon::V4_SL2_loadrb_io;
1224 else if ((inst & V4_SL2_loadrd_sp_MASK) == V4_SL2_loadrd_sp_BITS)
1225 op = Hexagon::V4_SL2_loadrd_sp;
1226 else if ((inst & V4_SL2_loadrh_io_MASK) == V4_SL2_loadrh_io_BITS)
1227 op = Hexagon::V4_SL2_loadrh_io;
1228 else if ((inst & V4_SL2_loadri_sp_MASK) == V4_SL2_loadri_sp_BITS)
1229 op = Hexagon::V4_SL2_loadri_sp;
1230 else if ((inst & V4_SL2_loadruh_io_MASK) == V4_SL2_loadruh_io_BITS)
1231 op = Hexagon::V4_SL2_loadruh_io;
1232 else if ((inst & V4_SL2_return_MASK) == V4_SL2_return_BITS)
1233 op = Hexagon::V4_SL2_return;
1234 else if ((inst & V4_SL2_return_f_MASK) == V4_SL2_return_f_BITS)
1235 op = Hexagon::V4_SL2_return_f;
1236 else if ((inst & V4_SL2_return_fnew_MASK) == V4_SL2_return_fnew_BITS)
1237 op = Hexagon::V4_SL2_return_fnew;
1238 else if ((inst & V4_SL2_return_t_MASK) == V4_SL2_return_t_BITS)
1239 op = Hexagon::V4_SL2_return_t;
1240 else if ((inst & V4_SL2_return_tnew_MASK) == V4_SL2_return_tnew_BITS)
1241 op = Hexagon::V4_SL2_return_tnew;
1243 os << "<unknown subinstruction>";
1244 return MCDisassembler::Fail;
1247 case HexagonII::HSIG_A:
1248 if ((inst & V4_SA1_addi_MASK) == V4_SA1_addi_BITS)
1249 op = Hexagon::V4_SA1_addi;
1250 else if ((inst & V4_SA1_addrx_MASK) == V4_SA1_addrx_BITS)
1251 op = Hexagon::V4_SA1_addrx;
1252 else if ((inst & V4_SA1_addsp_MASK) == V4_SA1_addsp_BITS)
1253 op = Hexagon::V4_SA1_addsp;
1254 else if ((inst & V4_SA1_and1_MASK) == V4_SA1_and1_BITS)
1255 op = Hexagon::V4_SA1_and1;
1256 else if ((inst & V4_SA1_clrf_MASK) == V4_SA1_clrf_BITS)
1257 op = Hexagon::V4_SA1_clrf;
1258 else if ((inst & V4_SA1_clrfnew_MASK) == V4_SA1_clrfnew_BITS)
1259 op = Hexagon::V4_SA1_clrfnew;
1260 else if ((inst & V4_SA1_clrt_MASK) == V4_SA1_clrt_BITS)
1261 op = Hexagon::V4_SA1_clrt;
1262 else if ((inst & V4_SA1_clrtnew_MASK) == V4_SA1_clrtnew_BITS)
1263 op = Hexagon::V4_SA1_clrtnew;
1264 else if ((inst & V4_SA1_cmpeqi_MASK) == V4_SA1_cmpeqi_BITS)
1265 op = Hexagon::V4_SA1_cmpeqi;
1266 else if ((inst & V4_SA1_combine0i_MASK) == V4_SA1_combine0i_BITS)
1267 op = Hexagon::V4_SA1_combine0i;
1268 else if ((inst & V4_SA1_combine1i_MASK) == V4_SA1_combine1i_BITS)
1269 op = Hexagon::V4_SA1_combine1i;
1270 else if ((inst & V4_SA1_combine2i_MASK) == V4_SA1_combine2i_BITS)
1271 op = Hexagon::V4_SA1_combine2i;
1272 else if ((inst & V4_SA1_combine3i_MASK) == V4_SA1_combine3i_BITS)
1273 op = Hexagon::V4_SA1_combine3i;
1274 else if ((inst & V4_SA1_combinerz_MASK) == V4_SA1_combinerz_BITS)
1275 op = Hexagon::V4_SA1_combinerz;
1276 else if ((inst & V4_SA1_combinezr_MASK) == V4_SA1_combinezr_BITS)
1277 op = Hexagon::V4_SA1_combinezr;
1278 else if ((inst & V4_SA1_dec_MASK) == V4_SA1_dec_BITS)
1279 op = Hexagon::V4_SA1_dec;
1280 else if ((inst & V4_SA1_inc_MASK) == V4_SA1_inc_BITS)
1281 op = Hexagon::V4_SA1_inc;
1282 else if ((inst & V4_SA1_seti_MASK) == V4_SA1_seti_BITS)
1283 op = Hexagon::V4_SA1_seti;
1284 else if ((inst & V4_SA1_setin1_MASK) == V4_SA1_setin1_BITS)
1285 op = Hexagon::V4_SA1_setin1;
1286 else if ((inst & V4_SA1_sxtb_MASK) == V4_SA1_sxtb_BITS)
1287 op = Hexagon::V4_SA1_sxtb;
1288 else if ((inst & V4_SA1_sxth_MASK) == V4_SA1_sxth_BITS)
1289 op = Hexagon::V4_SA1_sxth;
1290 else if ((inst & V4_SA1_tfr_MASK) == V4_SA1_tfr_BITS)
1291 op = Hexagon::V4_SA1_tfr;
1292 else if ((inst & V4_SA1_zxtb_MASK) == V4_SA1_zxtb_BITS)
1293 op = Hexagon::V4_SA1_zxtb;
1294 else if ((inst & V4_SA1_zxth_MASK) == V4_SA1_zxth_BITS)
1295 op = Hexagon::V4_SA1_zxth;
1297 os << "<unknown subinstruction>";
1298 return MCDisassembler::Fail;
1301 case HexagonII::HSIG_S1:
1302 if ((inst & V4_SS1_storeb_io_MASK) == V4_SS1_storeb_io_BITS)
1303 op = Hexagon::V4_SS1_storeb_io;
1304 else if ((inst & V4_SS1_storew_io_MASK) == V4_SS1_storew_io_BITS)
1305 op = Hexagon::V4_SS1_storew_io;
1307 os << "<unknown subinstruction>";
1308 return MCDisassembler::Fail;
1311 case HexagonII::HSIG_S2:
1312 if ((inst & V4_SS2_allocframe_MASK) == V4_SS2_allocframe_BITS)
1313 op = Hexagon::V4_SS2_allocframe;
1314 else if ((inst & V4_SS2_storebi0_MASK) == V4_SS2_storebi0_BITS)
1315 op = Hexagon::V4_SS2_storebi0;
1316 else if ((inst & V4_SS2_storebi1_MASK) == V4_SS2_storebi1_BITS)
1317 op = Hexagon::V4_SS2_storebi1;
1318 else if ((inst & V4_SS2_stored_sp_MASK) == V4_SS2_stored_sp_BITS)
1319 op = Hexagon::V4_SS2_stored_sp;
1320 else if ((inst & V4_SS2_storeh_io_MASK) == V4_SS2_storeh_io_BITS)
1321 op = Hexagon::V4_SS2_storeh_io;
1322 else if ((inst & V4_SS2_storew_sp_MASK) == V4_SS2_storew_sp_BITS)
1323 op = Hexagon::V4_SS2_storew_sp;
1324 else if ((inst & V4_SS2_storewi0_MASK) == V4_SS2_storewi0_BITS)
1325 op = Hexagon::V4_SS2_storewi0;
1326 else if ((inst & V4_SS2_storewi1_MASK) == V4_SS2_storewi1_BITS)
1327 op = Hexagon::V4_SS2_storewi1;
1329 os << "<unknown subinstruction>";
1330 return MCDisassembler::Fail;
1335 return MCDisassembler::Fail;
1337 return MCDisassembler::Success;
1340 static unsigned getRegFromSubinstEncoding(unsigned encoded_reg) {
1341 if (encoded_reg < 8)
1342 return Hexagon::R0 + encoded_reg;
1343 else if (encoded_reg < 16)
1344 return Hexagon::R0 + encoded_reg + 8;
1346 // patently false value
1347 return Hexagon::NoRegister;
1350 static unsigned getDRegFromSubinstEncoding(unsigned encoded_dreg) {
1351 if (encoded_dreg < 4)
1352 return Hexagon::D0 + encoded_dreg;
1353 else if (encoded_dreg < 8)
1354 return Hexagon::D0 + encoded_dreg + 4;
1356 // patently false value
1357 return Hexagon::NoRegister;
1360 void HexagonDisassembler::addSubinstOperands(MCInst *MI, unsigned opcode,
1361 unsigned inst) const {
1365 case Hexagon::V4_SL2_deallocframe:
1366 case Hexagon::V4_SL2_jumpr31:
1367 case Hexagon::V4_SL2_jumpr31_f:
1368 case Hexagon::V4_SL2_jumpr31_fnew:
1369 case Hexagon::V4_SL2_jumpr31_t:
1370 case Hexagon::V4_SL2_jumpr31_tnew:
1371 case Hexagon::V4_SL2_return:
1372 case Hexagon::V4_SL2_return_f:
1373 case Hexagon::V4_SL2_return_fnew:
1374 case Hexagon::V4_SL2_return_t:
1375 case Hexagon::V4_SL2_return_tnew:
1376 // no operands for these instructions
1378 case Hexagon::V4_SS2_allocframe:
1380 operand = ((inst & 0x1f0) >> 4) << 3;
1381 HexagonMCInstrInfo::addConstant(*MI, operand, getContext());
1383 case Hexagon::V4_SL1_loadri_io:
1384 // Rd 3-0, Rs 7-4, u 11-8{4_2}
1385 operand = getRegFromSubinstEncoding(inst & 0xf);
1386 Op = MCOperand::createReg(operand);
1388 operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4);
1389 Op = MCOperand::createReg(operand);
1391 operand = (inst & 0xf00) >> 6;
1392 HexagonMCInstrInfo::addConstant(*MI, operand, getContext());
1394 case Hexagon::V4_SL1_loadrub_io:
1395 // Rd 3-0, Rs 7-4, u 11-8
1396 operand = getRegFromSubinstEncoding(inst & 0xf);
1397 Op = MCOperand::createReg(operand);
1399 operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4);
1400 Op = MCOperand::createReg(operand);
1402 operand = (inst & 0xf00) >> 8;
1403 HexagonMCInstrInfo::addConstant(*MI, operand, getContext());
1405 case Hexagon::V4_SL2_loadrb_io:
1406 // Rd 3-0, Rs 7-4, u 10-8
1407 operand = getRegFromSubinstEncoding(inst & 0xf);
1408 Op = MCOperand::createReg(operand);
1410 operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4);
1411 Op = MCOperand::createReg(operand);
1413 operand = (inst & 0x700) >> 8;
1414 HexagonMCInstrInfo::addConstant(*MI, operand, getContext());
1416 case Hexagon::V4_SL2_loadrh_io:
1417 case Hexagon::V4_SL2_loadruh_io:
1418 // Rd 3-0, Rs 7-4, u 10-8{3_1}
1419 operand = getRegFromSubinstEncoding(inst & 0xf);
1420 Op = MCOperand::createReg(operand);
1422 operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4);
1423 Op = MCOperand::createReg(operand);
1425 operand = ((inst & 0x700) >> 8) << 1;
1426 HexagonMCInstrInfo::addConstant(*MI, operand, getContext());
1428 case Hexagon::V4_SL2_loadrd_sp:
1429 // Rdd 2-0, u 7-3{5_3}
1430 operand = getDRegFromSubinstEncoding(inst & 0x7);
1431 Op = MCOperand::createReg(operand);
1433 operand = ((inst & 0x0f8) >> 3) << 3;
1434 HexagonMCInstrInfo::addConstant(*MI, operand, getContext());
1436 case Hexagon::V4_SL2_loadri_sp:
1437 // Rd 3-0, u 8-4{5_2}
1438 operand = getRegFromSubinstEncoding(inst & 0xf);
1439 Op = MCOperand::createReg(operand);
1441 operand = ((inst & 0x1f0) >> 4) << 2;
1442 HexagonMCInstrInfo::addConstant(*MI, operand, getContext());
1444 case Hexagon::V4_SA1_addi:
1445 // Rx 3-0 (x2), s7 10-4
1446 operand = getRegFromSubinstEncoding(inst & 0xf);
1447 Op = MCOperand::createReg(operand);
1450 operand = SignExtend64<7>((inst & 0x7f0) >> 4);
1451 HexagonMCInstrInfo::addConstant(*MI, operand, getContext());
1453 case Hexagon::V4_SA1_addrx:
1454 // Rx 3-0 (x2), Rs 7-4
1455 operand = getRegFromSubinstEncoding(inst & 0xf);
1456 Op = MCOperand::createReg(operand);
1459 operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4);
1460 Op = MCOperand::createReg(operand);
1462 case Hexagon::V4_SA1_and1:
1463 case Hexagon::V4_SA1_dec:
1464 case Hexagon::V4_SA1_inc:
1465 case Hexagon::V4_SA1_sxtb:
1466 case Hexagon::V4_SA1_sxth:
1467 case Hexagon::V4_SA1_tfr:
1468 case Hexagon::V4_SA1_zxtb:
1469 case Hexagon::V4_SA1_zxth:
1471 operand = getRegFromSubinstEncoding(inst & 0xf);
1472 Op = MCOperand::createReg(operand);
1474 operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4);
1475 Op = MCOperand::createReg(operand);
1478 case Hexagon::V4_SA1_addsp:
1479 // Rd 3-0, u 9-4{6_2}
1480 operand = getRegFromSubinstEncoding(inst & 0xf);
1481 Op = MCOperand::createReg(operand);
1483 operand = ((inst & 0x3f0) >> 4) << 2;
1484 HexagonMCInstrInfo::addConstant(*MI, operand, getContext());
1486 case Hexagon::V4_SA1_seti:
1488 operand = getRegFromSubinstEncoding(inst & 0xf);
1489 Op = MCOperand::createReg(operand);
1491 operand = (inst & 0x3f0) >> 4;
1492 HexagonMCInstrInfo::addConstant(*MI, operand, getContext());
1494 case Hexagon::V4_SA1_clrf:
1495 case Hexagon::V4_SA1_clrfnew:
1496 case Hexagon::V4_SA1_clrt:
1497 case Hexagon::V4_SA1_clrtnew:
1498 case Hexagon::V4_SA1_setin1:
1500 operand = getRegFromSubinstEncoding(inst & 0xf);
1501 Op = MCOperand::createReg(operand);
1504 case Hexagon::V4_SA1_cmpeqi:
1506 operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4);
1507 Op = MCOperand::createReg(operand);
1509 operand = inst & 0x3;
1510 HexagonMCInstrInfo::addConstant(*MI, operand, getContext());
1512 case Hexagon::V4_SA1_combine0i:
1513 case Hexagon::V4_SA1_combine1i:
1514 case Hexagon::V4_SA1_combine2i:
1515 case Hexagon::V4_SA1_combine3i:
1517 operand = getDRegFromSubinstEncoding(inst & 0x7);
1518 Op = MCOperand::createReg(operand);
1520 operand = (inst & 0x060) >> 5;
1521 HexagonMCInstrInfo::addConstant(*MI, operand, getContext());
1523 case Hexagon::V4_SA1_combinerz:
1524 case Hexagon::V4_SA1_combinezr:
1526 operand = getDRegFromSubinstEncoding(inst & 0x7);
1527 Op = MCOperand::createReg(operand);
1529 operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4);
1530 Op = MCOperand::createReg(operand);
1533 case Hexagon::V4_SS1_storeb_io:
1534 // Rs 7-4, u 11-8, Rt 3-0
1535 operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4);
1536 Op = MCOperand::createReg(operand);
1538 operand = (inst & 0xf00) >> 8;
1539 HexagonMCInstrInfo::addConstant(*MI, operand, getContext());
1540 operand = getRegFromSubinstEncoding(inst & 0xf);
1541 Op = MCOperand::createReg(operand);
1544 case Hexagon::V4_SS1_storew_io:
1545 // Rs 7-4, u 11-8{4_2}, Rt 3-0
1546 operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4);
1547 Op = MCOperand::createReg(operand);
1549 operand = ((inst & 0xf00) >> 8) << 2;
1550 HexagonMCInstrInfo::addConstant(*MI, operand, getContext());
1551 operand = getRegFromSubinstEncoding(inst & 0xf);
1552 Op = MCOperand::createReg(operand);
1555 case Hexagon::V4_SS2_storebi0:
1556 case Hexagon::V4_SS2_storebi1:
1558 operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4);
1559 Op = MCOperand::createReg(operand);
1561 operand = inst & 0xf;
1562 HexagonMCInstrInfo::addConstant(*MI, operand, getContext());
1564 case Hexagon::V4_SS2_storewi0:
1565 case Hexagon::V4_SS2_storewi1:
1566 // Rs 7-4, u 3-0{4_2}
1567 operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4);
1568 Op = MCOperand::createReg(operand);
1570 operand = (inst & 0xf) << 2;
1571 HexagonMCInstrInfo::addConstant(*MI, operand, getContext());
1573 case Hexagon::V4_SS2_stored_sp:
1574 // s 8-3{6_3}, Rtt 2-0
1575 operand = SignExtend64<9>(((inst & 0x1f8) >> 3) << 3);
1576 HexagonMCInstrInfo::addConstant(*MI, operand, getContext());
1577 operand = getDRegFromSubinstEncoding(inst & 0x7);
1578 Op = MCOperand::createReg(operand);
1581 case Hexagon::V4_SS2_storeh_io:
1582 // Rs 7-4, u 10-8{3_1}, Rt 3-0
1583 operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4);
1584 Op = MCOperand::createReg(operand);
1586 operand = ((inst & 0x700) >> 8) << 1;
1587 HexagonMCInstrInfo::addConstant(*MI, operand, getContext());
1588 operand = getRegFromSubinstEncoding(inst & 0xf);
1589 Op = MCOperand::createReg(operand);
1592 case Hexagon::V4_SS2_storew_sp:
1593 // u 8-4{5_2}, Rd 3-0
1594 operand = ((inst & 0x1f0) >> 4) << 2;
1595 HexagonMCInstrInfo::addConstant(*MI, operand, getContext());
1596 operand = getRegFromSubinstEncoding(inst & 0xf);
1597 Op = MCOperand::createReg(operand);
1601 // don't crash with an invalid subinstruction
1602 // llvm_unreachable("Invalid subinstruction in duplex instruction");