1 //===- SPURegisterInfo.td - The Cell SPU Register File -----*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by a team from the Computer Systems Research
6 // Department at The Aerospace Corporation and is distributed under the
7 // University of Illinois Open Source License. See LICENSE.TXT for details.
9 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
14 class SPUReg<string n> : Register<n> {
15 let Namespace = "SPU";
18 // The SPU's register are all 128-bits wide, which makes specifying the
19 // registers relatively easy, if relatively mundane:
21 class SPUVecReg<bits<7> num, string n> : SPUReg<n> {
22 field bits<7> Num = num;
25 def R0 : SPUVecReg<0, "$lr">, DwarfRegNum<[0]>;
26 def R1 : SPUVecReg<1, "$sp">, DwarfRegNum<[1]>;
27 def R2 : SPUVecReg<2, "$2">, DwarfRegNum<[2]>;
28 def R3 : SPUVecReg<3, "$3">, DwarfRegNum<[3]>;
29 def R4 : SPUVecReg<4, "$4">, DwarfRegNum<[4]>;
30 def R5 : SPUVecReg<5, "$5">, DwarfRegNum<[5]>;
31 def R6 : SPUVecReg<6, "$6">, DwarfRegNum<[6]>;
32 def R7 : SPUVecReg<7, "$7">, DwarfRegNum<[7]>;
33 def R8 : SPUVecReg<8, "$8">, DwarfRegNum<[8]>;
34 def R9 : SPUVecReg<9, "$9">, DwarfRegNum<[9]>;
35 def R10 : SPUVecReg<10, "$10">, DwarfRegNum<[10]>;
36 def R11 : SPUVecReg<11, "$11">, DwarfRegNum<[11]>;
37 def R12 : SPUVecReg<12, "$12">, DwarfRegNum<[12]>;
38 def R13 : SPUVecReg<13, "$13">, DwarfRegNum<[13]>;
39 def R14 : SPUVecReg<14, "$14">, DwarfRegNum<[14]>;
40 def R15 : SPUVecReg<15, "$15">, DwarfRegNum<[15]>;
41 def R16 : SPUVecReg<16, "$16">, DwarfRegNum<[16]>;
42 def R17 : SPUVecReg<17, "$17">, DwarfRegNum<[17]>;
43 def R18 : SPUVecReg<18, "$18">, DwarfRegNum<[18]>;
44 def R19 : SPUVecReg<19, "$19">, DwarfRegNum<[19]>;
45 def R20 : SPUVecReg<20, "$20">, DwarfRegNum<[20]>;
46 def R21 : SPUVecReg<21, "$21">, DwarfRegNum<[21]>;
47 def R22 : SPUVecReg<22, "$22">, DwarfRegNum<[22]>;
48 def R23 : SPUVecReg<23, "$23">, DwarfRegNum<[23]>;
49 def R24 : SPUVecReg<24, "$24">, DwarfRegNum<[24]>;
50 def R25 : SPUVecReg<25, "$25">, DwarfRegNum<[25]>;
51 def R26 : SPUVecReg<26, "$26">, DwarfRegNum<[26]>;
52 def R27 : SPUVecReg<27, "$27">, DwarfRegNum<[27]>;
53 def R28 : SPUVecReg<28, "$28">, DwarfRegNum<[28]>;
54 def R29 : SPUVecReg<29, "$29">, DwarfRegNum<[29]>;
55 def R30 : SPUVecReg<30, "$30">, DwarfRegNum<[30]>;
56 def R31 : SPUVecReg<31, "$31">, DwarfRegNum<[31]>;
57 def R32 : SPUVecReg<32, "$32">, DwarfRegNum<[32]>;
58 def R33 : SPUVecReg<33, "$33">, DwarfRegNum<[33]>;
59 def R34 : SPUVecReg<34, "$34">, DwarfRegNum<[34]>;
60 def R35 : SPUVecReg<35, "$35">, DwarfRegNum<[35]>;
61 def R36 : SPUVecReg<36, "$36">, DwarfRegNum<[36]>;
62 def R37 : SPUVecReg<37, "$37">, DwarfRegNum<[37]>;
63 def R38 : SPUVecReg<38, "$38">, DwarfRegNum<[38]>;
64 def R39 : SPUVecReg<39, "$39">, DwarfRegNum<[39]>;
65 def R40 : SPUVecReg<40, "$40">, DwarfRegNum<[40]>;
66 def R41 : SPUVecReg<41, "$41">, DwarfRegNum<[41]>;
67 def R42 : SPUVecReg<42, "$42">, DwarfRegNum<[42]>;
68 def R43 : SPUVecReg<43, "$43">, DwarfRegNum<[43]>;
69 def R44 : SPUVecReg<44, "$44">, DwarfRegNum<[44]>;
70 def R45 : SPUVecReg<45, "$45">, DwarfRegNum<[45]>;
71 def R46 : SPUVecReg<46, "$46">, DwarfRegNum<[46]>;
72 def R47 : SPUVecReg<47, "$47">, DwarfRegNum<[47]>;
73 def R48 : SPUVecReg<48, "$48">, DwarfRegNum<[48]>;
74 def R49 : SPUVecReg<49, "$49">, DwarfRegNum<[49]>;
75 def R50 : SPUVecReg<50, "$50">, DwarfRegNum<[50]>;
76 def R51 : SPUVecReg<51, "$51">, DwarfRegNum<[51]>;
77 def R52 : SPUVecReg<52, "$52">, DwarfRegNum<[52]>;
78 def R53 : SPUVecReg<53, "$53">, DwarfRegNum<[53]>;
79 def R54 : SPUVecReg<54, "$54">, DwarfRegNum<[54]>;
80 def R55 : SPUVecReg<55, "$55">, DwarfRegNum<[55]>;
81 def R56 : SPUVecReg<56, "$56">, DwarfRegNum<[56]>;
82 def R57 : SPUVecReg<57, "$57">, DwarfRegNum<[57]>;
83 def R58 : SPUVecReg<58, "$58">, DwarfRegNum<[58]>;
84 def R59 : SPUVecReg<59, "$59">, DwarfRegNum<[59]>;
85 def R60 : SPUVecReg<60, "$60">, DwarfRegNum<[60]>;
86 def R61 : SPUVecReg<61, "$61">, DwarfRegNum<[61]>;
87 def R62 : SPUVecReg<62, "$62">, DwarfRegNum<[62]>;
88 def R63 : SPUVecReg<63, "$63">, DwarfRegNum<[63]>;
89 def R64 : SPUVecReg<64, "$64">, DwarfRegNum<[64]>;
90 def R65 : SPUVecReg<65, "$65">, DwarfRegNum<[65]>;
91 def R66 : SPUVecReg<66, "$66">, DwarfRegNum<[66]>;
92 def R67 : SPUVecReg<67, "$67">, DwarfRegNum<[67]>;
93 def R68 : SPUVecReg<68, "$68">, DwarfRegNum<[68]>;
94 def R69 : SPUVecReg<69, "$69">, DwarfRegNum<[69]>;
95 def R70 : SPUVecReg<70, "$70">, DwarfRegNum<[70]>;
96 def R71 : SPUVecReg<71, "$71">, DwarfRegNum<[71]>;
97 def R72 : SPUVecReg<72, "$72">, DwarfRegNum<[72]>;
98 def R73 : SPUVecReg<73, "$73">, DwarfRegNum<[73]>;
99 def R74 : SPUVecReg<74, "$74">, DwarfRegNum<[74]>;
100 def R75 : SPUVecReg<75, "$75">, DwarfRegNum<[75]>;
101 def R76 : SPUVecReg<76, "$76">, DwarfRegNum<[76]>;
102 def R77 : SPUVecReg<77, "$77">, DwarfRegNum<[77]>;
103 def R78 : SPUVecReg<78, "$78">, DwarfRegNum<[78]>;
104 def R79 : SPUVecReg<79, "$79">, DwarfRegNum<[79]>;
105 def R80 : SPUVecReg<80, "$80">, DwarfRegNum<[80]>;
106 def R81 : SPUVecReg<81, "$81">, DwarfRegNum<[81]>;
107 def R82 : SPUVecReg<82, "$82">, DwarfRegNum<[82]>;
108 def R83 : SPUVecReg<83, "$83">, DwarfRegNum<[83]>;
109 def R84 : SPUVecReg<84, "$84">, DwarfRegNum<[84]>;
110 def R85 : SPUVecReg<85, "$85">, DwarfRegNum<[85]>;
111 def R86 : SPUVecReg<86, "$86">, DwarfRegNum<[86]>;
112 def R87 : SPUVecReg<87, "$87">, DwarfRegNum<[87]>;
113 def R88 : SPUVecReg<88, "$88">, DwarfRegNum<[88]>;
114 def R89 : SPUVecReg<89, "$89">, DwarfRegNum<[89]>;
115 def R90 : SPUVecReg<90, "$90">, DwarfRegNum<[90]>;
116 def R91 : SPUVecReg<91, "$91">, DwarfRegNum<[91]>;
117 def R92 : SPUVecReg<92, "$92">, DwarfRegNum<[92]>;
118 def R93 : SPUVecReg<93, "$93">, DwarfRegNum<[93]>;
119 def R94 : SPUVecReg<94, "$94">, DwarfRegNum<[94]>;
120 def R95 : SPUVecReg<95, "$95">, DwarfRegNum<[95]>;
121 def R96 : SPUVecReg<96, "$96">, DwarfRegNum<[96]>;
122 def R97 : SPUVecReg<97, "$97">, DwarfRegNum<[97]>;
123 def R98 : SPUVecReg<98, "$98">, DwarfRegNum<[98]>;
124 def R99 : SPUVecReg<99, "$99">, DwarfRegNum<[99]>;
125 def R100 : SPUVecReg<100, "$100">, DwarfRegNum<[100]>;
126 def R101 : SPUVecReg<101, "$101">, DwarfRegNum<[101]>;
127 def R102 : SPUVecReg<102, "$102">, DwarfRegNum<[102]>;
128 def R103 : SPUVecReg<103, "$103">, DwarfRegNum<[103]>;
129 def R104 : SPUVecReg<104, "$104">, DwarfRegNum<[104]>;
130 def R105 : SPUVecReg<105, "$105">, DwarfRegNum<[105]>;
131 def R106 : SPUVecReg<106, "$106">, DwarfRegNum<[106]>;
132 def R107 : SPUVecReg<107, "$107">, DwarfRegNum<[107]>;
133 def R108 : SPUVecReg<108, "$108">, DwarfRegNum<[108]>;
134 def R109 : SPUVecReg<109, "$109">, DwarfRegNum<[109]>;
135 def R110 : SPUVecReg<110, "$110">, DwarfRegNum<[110]>;
136 def R111 : SPUVecReg<111, "$111">, DwarfRegNum<[111]>;
137 def R112 : SPUVecReg<112, "$112">, DwarfRegNum<[112]>;
138 def R113 : SPUVecReg<113, "$113">, DwarfRegNum<[113]>;
139 def R114 : SPUVecReg<114, "$114">, DwarfRegNum<[114]>;
140 def R115 : SPUVecReg<115, "$115">, DwarfRegNum<[115]>;
141 def R116 : SPUVecReg<116, "$116">, DwarfRegNum<[116]>;
142 def R117 : SPUVecReg<117, "$117">, DwarfRegNum<[117]>;
143 def R118 : SPUVecReg<118, "$118">, DwarfRegNum<[118]>;
144 def R119 : SPUVecReg<119, "$119">, DwarfRegNum<[119]>;
145 def R120 : SPUVecReg<120, "$120">, DwarfRegNum<[120]>;
146 def R121 : SPUVecReg<121, "$121">, DwarfRegNum<[121]>;
147 def R122 : SPUVecReg<122, "$122">, DwarfRegNum<[122]>;
148 def R123 : SPUVecReg<123, "$123">, DwarfRegNum<[123]>;
149 def R124 : SPUVecReg<124, "$124">, DwarfRegNum<[124]>;
150 def R125 : SPUVecReg<125, "$125">, DwarfRegNum<[125]>;
151 def R126 : SPUVecReg<126, "$126">, DwarfRegNum<[126]>;
152 def R127 : SPUVecReg<127, "$127">, DwarfRegNum<[127]>;
154 /* Need floating point status register here: */
155 /* def FPCSR : ... */
157 // The SPU's registers as 128-bit wide entities, and can function as general
158 // purpose registers, where the operands are in the "preferred slot":
159 def GPRC : RegisterClass<"SPU", [i128], 128,
161 /* volatile register */
162 R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16,
163 R17, R18, R19, R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R31,
164 R32, R33, R34, R35, R36, R37, R38, R39, R40, R41, R42, R43, R44, R45, R46,
165 R47, R48, R49, R50, R51, R52, R53, R54, R55, R56, R57, R58, R59, R60, R61,
166 R62, R63, R64, R65, R66, R67, R68, R69, R70, R71, R72, R73, R74, R75, R76,
168 /* non-volatile register: take hint from PPC and allocate in reverse order */
169 R127, R126, R125, R124, R123, R122, R121, R120, R119, R118, R117, R116, R115,
170 R114, R113, R112, R111, R110, R109, R108, R107, R106, R105, R104, R103, R102,
171 R101, R100, R99, R98, R97, R96, R95, R94, R93, R92, R91, R90, R89, R88, R87,
172 R86, R85, R84, R83, R82, R81, R80,
173 /* environment ptr, SP, LR */
176 let MethodProtos = [{
177 iterator allocation_order_begin(const MachineFunction &MF) const;
178 iterator allocation_order_end(const MachineFunction &MF) const;
180 let MethodBodies = [{
182 GPRCClass::allocation_order_begin(const MachineFunction &MF) const {
186 GPRCClass::allocation_order_end(const MachineFunction &MF) const {
187 return end()-3; // don't allocate R2, R1, or R0 (envp, sp, lr)
192 // The SPU's registers as 64-bit wide (double word integer) "preferred slot":
193 def R64C : RegisterClass<"SPU", [i64], 128,
195 /* volatile register */
196 R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16,
197 R17, R18, R19, R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R31,
198 R32, R33, R34, R35, R36, R37, R38, R39, R40, R41, R42, R43, R44, R45, R46,
199 R47, R48, R49, R50, R51, R52, R53, R54, R55, R56, R57, R58, R59, R60, R61,
200 R62, R63, R64, R65, R66, R67, R68, R69, R70, R71, R72, R73, R74, R75, R76,
202 /* non-volatile register: take hint from PPC and allocate in reverse order */
203 R127, R126, R125, R124, R123, R122, R121, R120, R119, R118, R117, R116, R115,
204 R114, R113, R112, R111, R110, R109, R108, R107, R106, R105, R104, R103, R102,
205 R101, R100, R99, R98, R97, R96, R95, R94, R93, R92, R91, R90, R89, R88, R87,
206 R86, R85, R84, R83, R82, R81, R80,
207 /* environment ptr, SP, LR */
210 let MethodProtos = [{
211 iterator allocation_order_begin(const MachineFunction &MF) const;
212 iterator allocation_order_end(const MachineFunction &MF) const;
214 let MethodBodies = [{
216 R64CClass::allocation_order_begin(const MachineFunction &MF) const {
220 R64CClass::allocation_order_end(const MachineFunction &MF) const {
221 return end()-3; // don't allocate R2, R1, or R0 (envp, sp, lr)
226 // The SPU's registers as 64-bit wide (double word) FP "preferred slot":
227 def R64FP : RegisterClass<"SPU", [f64], 128,
229 /* volatile register */
230 R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16,
231 R17, R18, R19, R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R31,
232 R32, R33, R34, R35, R36, R37, R38, R39, R40, R41, R42, R43, R44, R45, R46,
233 R47, R48, R49, R50, R51, R52, R53, R54, R55, R56, R57, R58, R59, R60, R61,
234 R62, R63, R64, R65, R66, R67, R68, R69, R70, R71, R72, R73, R74, R75, R76,
236 /* non-volatile register: take hint from PPC and allocate in reverse order */
237 R127, R126, R125, R124, R123, R122, R121, R120, R119, R118, R117, R116, R115,
238 R114, R113, R112, R111, R110, R109, R108, R107, R106, R105, R104, R103, R102,
239 R101, R100, R99, R98, R97, R96, R95, R94, R93, R92, R91, R90, R89, R88, R87,
240 R86, R85, R84, R83, R82, R81, R80,
241 /* environment ptr, SP, LR */
244 let MethodProtos = [{
245 iterator allocation_order_begin(const MachineFunction &MF) const;
246 iterator allocation_order_end(const MachineFunction &MF) const;
248 let MethodBodies = [{
250 R64FPClass::allocation_order_begin(const MachineFunction &MF) const {
254 R64FPClass::allocation_order_end(const MachineFunction &MF) const {
255 return end()-3; // don't allocate R2, R1, or R0 (envp, sp, lr)
260 // The SPU's registers as 32-bit wide (word) "preferred slot":
261 def R32C : RegisterClass<"SPU", [i32], 128,
263 /* volatile register */
264 R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16,
265 R17, R18, R19, R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R31,
266 R32, R33, R34, R35, R36, R37, R38, R39, R40, R41, R42, R43, R44, R45, R46,
267 R47, R48, R49, R50, R51, R52, R53, R54, R55, R56, R57, R58, R59, R60, R61,
268 R62, R63, R64, R65, R66, R67, R68, R69, R70, R71, R72, R73, R74, R75, R76,
270 /* non-volatile register: take hint from PPC and allocate in reverse order */
271 R127, R126, R125, R124, R123, R122, R121, R120, R119, R118, R117, R116, R115,
272 R114, R113, R112, R111, R110, R109, R108, R107, R106, R105, R104, R103, R102,
273 R101, R100, R99, R98, R97, R96, R95, R94, R93, R92, R91, R90, R89, R88, R87,
274 R86, R85, R84, R83, R82, R81, R80,
275 /* environment ptr, SP, LR */
278 let MethodProtos = [{
279 iterator allocation_order_begin(const MachineFunction &MF) const;
280 iterator allocation_order_end(const MachineFunction &MF) const;
282 let MethodBodies = [{
284 R32CClass::allocation_order_begin(const MachineFunction &MF) const {
288 R32CClass::allocation_order_end(const MachineFunction &MF) const {
289 return end()-3; // don't allocate R2, R1, or R0 (envp, sp, lr)
294 // The SPU's registers as single precision floating point "preferred slot":
295 def R32FP : RegisterClass<"SPU", [f32], 128,
297 /* volatile register */
298 R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16,
299 R17, R18, R19, R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R31,
300 R32, R33, R34, R35, R36, R37, R38, R39, R40, R41, R42, R43, R44, R45, R46,
301 R47, R48, R49, R50, R51, R52, R53, R54, R55, R56, R57, R58, R59, R60, R61,
302 R62, R63, R64, R65, R66, R67, R68, R69, R70, R71, R72, R73, R74, R75, R76,
304 /* non-volatile register: take hint from PPC and allocate in reverse order */
305 R127, R126, R125, R124, R123, R122, R121, R120, R119, R118, R117, R116, R115,
306 R114, R113, R112, R111, R110, R109, R108, R107, R106, R105, R104, R103, R102,
307 R101, R100, R99, R98, R97, R96, R95, R94, R93, R92, R91, R90, R89, R88, R87,
308 R86, R85, R84, R83, R82, R81, R80,
309 /* environment ptr, SP, LR */
312 let MethodProtos = [{
313 iterator allocation_order_begin(const MachineFunction &MF) const;
314 iterator allocation_order_end(const MachineFunction &MF) const;
316 let MethodBodies = [{
318 R32FPClass::allocation_order_begin(const MachineFunction &MF) const {
322 R32FPClass::allocation_order_end(const MachineFunction &MF) const {
323 return end()-3; // don't allocate R2, R1, or R0 (envp, sp, lr)
328 // The SPU's registers as 16-bit wide (halfword) "preferred slot":
329 def R16C : RegisterClass<"SPU", [i16], 128,
331 /* volatile register */
332 R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16,
333 R17, R18, R19, R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R31,
334 R32, R33, R34, R35, R36, R37, R38, R39, R40, R41, R42, R43, R44, R45, R46,
335 R47, R48, R49, R50, R51, R52, R53, R54, R55, R56, R57, R58, R59, R60, R61,
336 R62, R63, R64, R65, R66, R67, R68, R69, R70, R71, R72, R73, R74, R75, R76,
338 /* non-volatile register: take hint from PPC and allocate in reverse order */
339 R127, R126, R125, R124, R123, R122, R121, R120, R119, R118, R117, R116, R115,
340 R114, R113, R112, R111, R110, R109, R108, R107, R106, R105, R104, R103, R102,
341 R101, R100, R99, R98, R97, R96, R95, R94, R93, R92, R91, R90, R89, R88, R87,
342 R86, R85, R84, R83, R82, R81, R80,
343 /* environment ptr, SP, LR */
346 let MethodProtos = [{
347 iterator allocation_order_begin(const MachineFunction &MF) const;
348 iterator allocation_order_end(const MachineFunction &MF) const;
350 let MethodBodies = [{
352 R16CClass::allocation_order_begin(const MachineFunction &MF) const {
356 R16CClass::allocation_order_end(const MachineFunction &MF) const {
357 return end()-3; // don't allocate R2, R1, or R0 (envp, sp, lr)
362 // The SPU's registers as vector registers:
363 def VECREG : RegisterClass<"SPU", [v16i8,v8i16,v4i32,v4f32,v2i64,v2f64], 128,
365 /* volatile register */
366 R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16,
367 R17, R18, R19, R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R31,
368 R32, R33, R34, R35, R36, R37, R38, R39, R40, R41, R42, R43, R44, R45, R46,
369 R47, R48, R49, R50, R51, R52, R53, R54, R55, R56, R57, R58, R59, R60, R61,
370 R62, R63, R64, R65, R66, R67, R68, R69, R70, R71, R72, R73, R74, R75, R76,
372 /* non-volatile register: take hint from PPC and allocate in reverse order */
373 R127, R126, R125, R124, R123, R122, R121, R120, R119, R118, R117, R116, R115,
374 R114, R113, R112, R111, R110, R109, R108, R107, R106, R105, R104, R103, R102,
375 R101, R100, R99, R98, R97, R96, R95, R94, R93, R92, R91, R90, R89, R88, R87,
376 R86, R85, R84, R83, R82, R81, R80,
377 /* environment ptr, SP, LR */
380 let MethodProtos = [{
381 iterator allocation_order_begin(const MachineFunction &MF) const;
382 iterator allocation_order_end(const MachineFunction &MF) const;
384 let MethodBodies = [{
385 VECREGClass::iterator
386 VECREGClass::allocation_order_begin(const MachineFunction &MF) const {
389 VECREGClass::iterator
390 VECREGClass::allocation_order_end(const MachineFunction &MF) const {
391 return end()-3; // don't allocate R2, R1, or R0 (envp, sp, lr)